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c05ce083 AD |
1 | /* |
2 | * Copyright 2008-2009 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Dave Airlie <airlied@redhat.com> | |
26 | * Alex Deucher <alexander.deucher@amd.com> | |
27 | */ | |
28 | ||
29 | #include "drmP.h" | |
30 | #include "drm.h" | |
31 | #include "radeon_drm.h" | |
32 | #include "radeon_drv.h" | |
33 | ||
34 | #include "r600_microcode.h" | |
35 | ||
36 | # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ | |
37 | # define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1)) | |
38 | ||
39 | #define R600_PTE_VALID (1 << 0) | |
40 | #define R600_PTE_SYSTEM (1 << 1) | |
41 | #define R600_PTE_SNOOPED (1 << 2) | |
42 | #define R600_PTE_READABLE (1 << 5) | |
43 | #define R600_PTE_WRITEABLE (1 << 6) | |
44 | ||
45 | /* MAX values used for gfx init */ | |
46 | #define R6XX_MAX_SH_GPRS 256 | |
47 | #define R6XX_MAX_TEMP_GPRS 16 | |
48 | #define R6XX_MAX_SH_THREADS 256 | |
49 | #define R6XX_MAX_SH_STACK_ENTRIES 4096 | |
50 | #define R6XX_MAX_BACKENDS 8 | |
51 | #define R6XX_MAX_BACKENDS_MASK 0xff | |
52 | #define R6XX_MAX_SIMDS 8 | |
53 | #define R6XX_MAX_SIMDS_MASK 0xff | |
54 | #define R6XX_MAX_PIPES 8 | |
55 | #define R6XX_MAX_PIPES_MASK 0xff | |
56 | ||
57 | #define R7XX_MAX_SH_GPRS 256 | |
58 | #define R7XX_MAX_TEMP_GPRS 16 | |
59 | #define R7XX_MAX_SH_THREADS 256 | |
60 | #define R7XX_MAX_SH_STACK_ENTRIES 4096 | |
61 | #define R7XX_MAX_BACKENDS 8 | |
62 | #define R7XX_MAX_BACKENDS_MASK 0xff | |
63 | #define R7XX_MAX_SIMDS 16 | |
64 | #define R7XX_MAX_SIMDS_MASK 0xffff | |
65 | #define R7XX_MAX_PIPES 8 | |
66 | #define R7XX_MAX_PIPES_MASK 0xff | |
67 | ||
68 | static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries) | |
69 | { | |
70 | int i; | |
71 | ||
72 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | |
73 | ||
74 | for (i = 0; i < dev_priv->usec_timeout; i++) { | |
75 | int slots; | |
76 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) | |
77 | slots = (RADEON_READ(R600_GRBM_STATUS) | |
78 | & R700_CMDFIFO_AVAIL_MASK); | |
79 | else | |
80 | slots = (RADEON_READ(R600_GRBM_STATUS) | |
81 | & R600_CMDFIFO_AVAIL_MASK); | |
82 | if (slots >= entries) | |
83 | return 0; | |
84 | DRM_UDELAY(1); | |
85 | } | |
86 | DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n", | |
87 | RADEON_READ(R600_GRBM_STATUS), | |
88 | RADEON_READ(R600_GRBM_STATUS2)); | |
89 | ||
90 | return -EBUSY; | |
91 | } | |
92 | ||
93 | static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv) | |
94 | { | |
95 | int i, ret; | |
96 | ||
97 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | |
98 | ||
99 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) | |
100 | ret = r600_do_wait_for_fifo(dev_priv, 8); | |
101 | else | |
102 | ret = r600_do_wait_for_fifo(dev_priv, 16); | |
103 | if (ret) | |
104 | return ret; | |
105 | for (i = 0; i < dev_priv->usec_timeout; i++) { | |
106 | if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE)) | |
107 | return 0; | |
108 | DRM_UDELAY(1); | |
109 | } | |
110 | DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n", | |
111 | RADEON_READ(R600_GRBM_STATUS), | |
112 | RADEON_READ(R600_GRBM_STATUS2)); | |
113 | ||
114 | return -EBUSY; | |
115 | } | |
116 | ||
c1556f71 | 117 | void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) |
c05ce083 AD |
118 | { |
119 | struct drm_sg_mem *entry = dev->sg; | |
120 | int max_pages; | |
121 | int pages; | |
122 | int i; | |
123 | ||
08932156 AD |
124 | if (!entry) |
125 | return; | |
126 | ||
c05ce083 | 127 | if (gart_info->bus_addr) { |
06f0a488 | 128 | max_pages = (gart_info->table_size / sizeof(u64)); |
c05ce083 AD |
129 | pages = (entry->pages <= max_pages) |
130 | ? entry->pages : max_pages; | |
131 | ||
132 | for (i = 0; i < pages; i++) { | |
133 | if (!entry->busaddr[i]) | |
134 | break; | |
a763d7dc DA |
135 | pci_unmap_page(dev->pdev, entry->busaddr[i], |
136 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
c05ce083 AD |
137 | } |
138 | if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) | |
139 | gart_info->bus_addr = 0; | |
140 | } | |
141 | } | |
142 | ||
143 | /* R600 has page table setup */ | |
144 | int r600_page_table_init(struct drm_device *dev) | |
145 | { | |
146 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
147 | struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info; | |
eb1d9195 | 148 | struct drm_local_map *map = &gart_info->mapping; |
c05ce083 AD |
149 | struct drm_sg_mem *entry = dev->sg; |
150 | int ret = 0; | |
151 | int i, j; | |
eb1d9195 DA |
152 | int pages; |
153 | u64 page_base; | |
c05ce083 | 154 | dma_addr_t entry_addr; |
eb1d9195 | 155 | int max_ati_pages, max_real_pages, gart_idx; |
c05ce083 AD |
156 | |
157 | /* okay page table is available - lets rock */ | |
eb1d9195 DA |
158 | max_ati_pages = (gart_info->table_size / sizeof(u64)); |
159 | max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); | |
c05ce083 | 160 | |
eb1d9195 DA |
161 | pages = (entry->pages <= max_real_pages) ? |
162 | entry->pages : max_real_pages; | |
c05ce083 | 163 | |
eb1d9195 | 164 | memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u64)); |
c05ce083 | 165 | |
eb1d9195 | 166 | gart_idx = 0; |
c05ce083 | 167 | for (i = 0; i < pages; i++) { |
a763d7dc DA |
168 | entry->busaddr[i] = pci_map_page(dev->pdev, |
169 | entry->pagelist[i], 0, | |
170 | PAGE_SIZE, | |
171 | PCI_DMA_BIDIRECTIONAL); | |
c05ce083 AD |
172 | if (entry->busaddr[i] == 0) { |
173 | DRM_ERROR("unable to map PCIGART pages!\n"); | |
174 | r600_page_table_cleanup(dev, gart_info); | |
175 | ret = -EINVAL; | |
176 | goto done; | |
177 | } | |
178 | entry_addr = entry->busaddr[i]; | |
179 | for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { | |
180 | page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK; | |
181 | page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; | |
182 | page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE; | |
183 | ||
eb1d9195 DA |
184 | DRM_WRITE64(map, gart_idx * sizeof(u64), page_base); |
185 | ||
186 | gart_idx++; | |
c05ce083 AD |
187 | |
188 | if ((i % 128) == 0) | |
189 | DRM_DEBUG("page entry %d: 0x%016llx\n", | |
190 | i, (unsigned long long)page_base); | |
c05ce083 AD |
191 | entry_addr += ATI_PCIGART_PAGE_SIZE; |
192 | } | |
193 | } | |
194 | done: | |
195 | return ret; | |
196 | } | |
197 | ||
198 | static void r600_vm_flush_gart_range(struct drm_device *dev) | |
199 | { | |
200 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
201 | u32 resp, countdown = 1000; | |
202 | RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12); | |
203 | RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); | |
204 | RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2); | |
205 | ||
206 | do { | |
207 | resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE); | |
208 | countdown--; | |
209 | DRM_UDELAY(1); | |
210 | } while (((resp & 0xf0) == 0) && countdown); | |
211 | } | |
212 | ||
213 | static void r600_vm_init(struct drm_device *dev) | |
214 | { | |
215 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
216 | /* initialise the VM to use the page table we constructed up there */ | |
217 | u32 vm_c0, i; | |
218 | u32 mc_rd_a; | |
219 | u32 vm_l2_cntl, vm_l2_cntl3; | |
220 | /* okay set up the PCIE aperture type thingo */ | |
221 | RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); | |
222 | RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); | |
223 | RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); | |
224 | ||
225 | /* setup MC RD a */ | |
226 | mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS | | |
227 | R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) | | |
228 | R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY; | |
229 | ||
230 | RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a); | |
231 | RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a); | |
232 | ||
233 | RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a); | |
234 | RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a); | |
235 | ||
236 | RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a); | |
237 | RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a); | |
238 | ||
239 | RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a); | |
240 | RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a); | |
241 | ||
242 | RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING); | |
243 | RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/); | |
244 | ||
245 | RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a); | |
246 | RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a); | |
247 | ||
248 | RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE); | |
249 | RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a); | |
250 | ||
251 | vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W; | |
252 | vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7); | |
253 | RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); | |
254 | ||
255 | RADEON_WRITE(R600_VM_L2_CNTL2, 0); | |
256 | vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) | | |
257 | R600_VM_L2_CNTL3_BANK_SELECT_1(1) | | |
258 | R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2)); | |
259 | RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); | |
260 | ||
261 | vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT; | |
262 | ||
263 | RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); | |
264 | ||
265 | vm_c0 &= ~R600_VM_ENABLE_CONTEXT; | |
266 | ||
267 | /* disable all other contexts */ | |
268 | for (i = 1; i < 8; i++) | |
269 | RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); | |
270 | ||
271 | RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); | |
272 | RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); | |
273 | RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); | |
274 | ||
275 | r600_vm_flush_gart_range(dev); | |
276 | } | |
277 | ||
278 | /* load r600 microcode */ | |
279 | static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) | |
280 | { | |
281 | int i; | |
282 | ||
283 | r600_do_cp_stop(dev_priv); | |
284 | ||
285 | RADEON_WRITE(R600_CP_RB_CNTL, | |
286 | R600_RB_NO_UPDATE | | |
287 | R600_RB_BLKSZ(15) | | |
288 | R600_RB_BUFSZ(3)); | |
289 | ||
290 | RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); | |
291 | RADEON_READ(R600_GRBM_SOFT_RESET); | |
292 | DRM_UDELAY(15000); | |
293 | RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); | |
294 | ||
295 | RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); | |
296 | ||
297 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600)) { | |
298 | DRM_INFO("Loading R600 CP Microcode\n"); | |
299 | for (i = 0; i < PM4_UCODE_SIZE; i++) { | |
300 | RADEON_WRITE(R600_CP_ME_RAM_DATA, | |
301 | R600_cp_microcode[i][0]); | |
302 | RADEON_WRITE(R600_CP_ME_RAM_DATA, | |
303 | R600_cp_microcode[i][1]); | |
304 | RADEON_WRITE(R600_CP_ME_RAM_DATA, | |
305 | R600_cp_microcode[i][2]); | |
306 | } | |
307 | ||
308 | RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); | |
309 | DRM_INFO("Loading R600 PFP Microcode\n"); | |
310 | for (i = 0; i < PFP_UCODE_SIZE; i++) | |
311 | RADEON_WRITE(R600_CP_PFP_UCODE_DATA, R600_pfp_microcode[i]); | |
312 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610)) { | |
313 | DRM_INFO("Loading RV610 CP Microcode\n"); | |
314 | for (i = 0; i < PM4_UCODE_SIZE; i++) { | |
315 | RADEON_WRITE(R600_CP_ME_RAM_DATA, | |
316 | RV610_cp_microcode[i][0]); | |
317 | RADEON_WRITE(R600_CP_ME_RAM_DATA, | |
318 | RV610_cp_microcode[i][1]); | |
319 | RADEON_WRITE(R600_CP_ME_RAM_DATA, | |
320 | RV610_cp_microcode[i][2]); | |
321 | } | |
322 | ||
323 | RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); | |
324 | DRM_INFO("Loading RV610 PFP Microcode\n"); | |
325 | for (i = 0; i < PFP_UCODE_SIZE; i++) | |
326 | RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV610_pfp_microcode[i]); | |
327 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) { | |
328 | DRM_INFO("Loading RV630 CP Microcode\n"); | |
329 | for (i = 0; i < PM4_UCODE_SIZE; i++) { | |
330 | RADEON_WRITE(R600_CP_ME_RAM_DATA, | |
331 | RV630_cp_microcode[i][0]); | |
332 | RADEON_WRITE(R600_CP_ME_RAM_DATA, | |
333 | RV630_cp_microcode[i][1]); | |
334 | RADEON_WRITE(R600_CP_ME_RAM_DATA, | |
335 | RV630_cp_microcode[i][2]); | |
336 | } | |
337 | ||
338 | RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); | |
339 | DRM_INFO("Loading RV630 PFP Microcode\n"); | |
340 | for (i = 0; i < PFP_UCODE_SIZE; i++) | |
341 | RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV630_pfp_microcode[i]); | |
342 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620)) { | |
343 | DRM_INFO("Loading RV620 CP Microcode\n"); | |
344 | for (i = 0; i < PM4_UCODE_SIZE; i++) { | |
345 | RADEON_WRITE(R600_CP_ME_RAM_DATA, | |
346 | RV620_cp_microcode[i][0]); | |
347 | RADEON_WRITE(R600_CP_ME_RAM_DATA, | |
348 | RV620_cp_microcode[i][1]); | |
349 | RADEON_WRITE(R600_CP_ME_RAM_DATA, | |
350 | RV620_cp_microcode[i][2]); | |
351 | } | |
352 | ||
353 | RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); | |
354 | DRM_INFO("Loading RV620 PFP Microcode\n"); | |
355 | for (i = 0; i < PFP_UCODE_SIZE; i++) | |
356 | RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV620_pfp_microcode[i]); | |
357 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) { | |
358 | DRM_INFO("Loading RV635 CP Microcode\n"); | |
359 | for (i = 0; i < PM4_UCODE_SIZE; i++) { | |
360 | RADEON_WRITE(R600_CP_ME_RAM_DATA, | |
361 | RV635_cp_microcode[i][0]); | |
362 | RADEON_WRITE(R600_CP_ME_RAM_DATA, | |
363 | RV635_cp_microcode[i][1]); | |
364 | RADEON_WRITE(R600_CP_ME_RAM_DATA, | |
365 | RV635_cp_microcode[i][2]); | |
366 | } | |
367 | ||
368 | RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); | |
369 | DRM_INFO("Loading RV635 PFP Microcode\n"); | |
370 | for (i = 0; i < PFP_UCODE_SIZE; i++) | |
371 | RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV635_pfp_microcode[i]); | |
372 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)) { | |
373 | DRM_INFO("Loading RV670 CP Microcode\n"); | |
374 | for (i = 0; i < PM4_UCODE_SIZE; i++) { | |
375 | RADEON_WRITE(R600_CP_ME_RAM_DATA, | |
376 | RV670_cp_microcode[i][0]); | |
377 | RADEON_WRITE(R600_CP_ME_RAM_DATA, | |
378 | RV670_cp_microcode[i][1]); | |
379 | RADEON_WRITE(R600_CP_ME_RAM_DATA, | |
380 | RV670_cp_microcode[i][2]); | |
381 | } | |
382 | ||
383 | RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); | |
384 | DRM_INFO("Loading RV670 PFP Microcode\n"); | |
385 | for (i = 0; i < PFP_UCODE_SIZE; i++) | |
386 | RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]); | |
387 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) { | |
388 | DRM_INFO("Loading RS780 CP Microcode\n"); | |
389 | for (i = 0; i < PM4_UCODE_SIZE; i++) { | |
390 | RADEON_WRITE(R600_CP_ME_RAM_DATA, | |
391 | RV670_cp_microcode[i][0]); | |
392 | RADEON_WRITE(R600_CP_ME_RAM_DATA, | |
393 | RV670_cp_microcode[i][1]); | |
394 | RADEON_WRITE(R600_CP_ME_RAM_DATA, | |
395 | RV670_cp_microcode[i][2]); | |
396 | } | |
397 | ||
398 | RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); | |
399 | DRM_INFO("Loading RS780 PFP Microcode\n"); | |
400 | for (i = 0; i < PFP_UCODE_SIZE; i++) | |
401 | RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]); | |
402 | } | |
403 | RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); | |
404 | RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); | |
405 | RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); | |
406 | ||
407 | } | |
408 | ||
409 | static void r700_vm_init(struct drm_device *dev) | |
410 | { | |
411 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
412 | /* initialise the VM to use the page table we constructed up there */ | |
413 | u32 vm_c0, i; | |
414 | u32 mc_vm_md_l1; | |
415 | u32 vm_l2_cntl, vm_l2_cntl3; | |
416 | /* okay set up the PCIE aperture type thingo */ | |
417 | RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); | |
418 | RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); | |
419 | RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); | |
420 | ||
421 | mc_vm_md_l1 = R700_ENABLE_L1_TLB | | |
422 | R700_ENABLE_L1_FRAGMENT_PROCESSING | | |
423 | R700_SYSTEM_ACCESS_MODE_IN_SYS | | |
424 | R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | | |
425 | R700_EFFECTIVE_L1_TLB_SIZE(5) | | |
426 | R700_EFFECTIVE_L1_QUEUE_SIZE(5); | |
427 | ||
428 | RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1); | |
429 | RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1); | |
430 | RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1); | |
431 | RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1); | |
432 | RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1); | |
433 | RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1); | |
434 | RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1); | |
435 | ||
436 | vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W; | |
437 | vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7); | |
438 | RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); | |
439 | ||
440 | RADEON_WRITE(R600_VM_L2_CNTL2, 0); | |
441 | vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2); | |
442 | RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); | |
443 | ||
444 | vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT; | |
445 | ||
446 | RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); | |
447 | ||
448 | vm_c0 &= ~R600_VM_ENABLE_CONTEXT; | |
449 | ||
450 | /* disable all other contexts */ | |
451 | for (i = 1; i < 8; i++) | |
452 | RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); | |
453 | ||
454 | RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); | |
455 | RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); | |
456 | RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); | |
457 | ||
458 | r600_vm_flush_gart_range(dev); | |
459 | } | |
460 | ||
461 | /* load r600 microcode */ | |
462 | static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) | |
463 | { | |
464 | int i; | |
465 | ||
466 | r600_do_cp_stop(dev_priv); | |
467 | ||
468 | RADEON_WRITE(R600_CP_RB_CNTL, | |
469 | R600_RB_NO_UPDATE | | |
470 | (15 << 8) | | |
471 | (3 << 0)); | |
472 | ||
473 | RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); | |
474 | RADEON_READ(R600_GRBM_SOFT_RESET); | |
475 | DRM_UDELAY(15000); | |
476 | RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); | |
477 | ||
478 | ||
479 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)) { | |
480 | RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); | |
481 | DRM_INFO("Loading RV770 PFP Microcode\n"); | |
482 | for (i = 0; i < R700_PFP_UCODE_SIZE; i++) | |
483 | RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV770_pfp_microcode[i]); | |
484 | RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); | |
485 | ||
486 | RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); | |
487 | DRM_INFO("Loading RV770 CP Microcode\n"); | |
488 | for (i = 0; i < R700_PM4_UCODE_SIZE; i++) | |
489 | RADEON_WRITE(R600_CP_ME_RAM_DATA, RV770_cp_microcode[i]); | |
490 | RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); | |
491 | ||
492 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV730)) { | |
493 | RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); | |
494 | DRM_INFO("Loading RV730 PFP Microcode\n"); | |
495 | for (i = 0; i < R700_PFP_UCODE_SIZE; i++) | |
496 | RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV730_pfp_microcode[i]); | |
497 | RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); | |
498 | ||
499 | RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); | |
500 | DRM_INFO("Loading RV730 CP Microcode\n"); | |
501 | for (i = 0; i < R700_PM4_UCODE_SIZE; i++) | |
502 | RADEON_WRITE(R600_CP_ME_RAM_DATA, RV730_cp_microcode[i]); | |
503 | RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); | |
504 | ||
505 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)) { | |
506 | RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); | |
507 | DRM_INFO("Loading RV710 PFP Microcode\n"); | |
508 | for (i = 0; i < R700_PFP_UCODE_SIZE; i++) | |
509 | RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV710_pfp_microcode[i]); | |
510 | RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); | |
511 | ||
512 | RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); | |
513 | DRM_INFO("Loading RV710 CP Microcode\n"); | |
514 | for (i = 0; i < R700_PM4_UCODE_SIZE; i++) | |
515 | RADEON_WRITE(R600_CP_ME_RAM_DATA, RV710_cp_microcode[i]); | |
516 | RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); | |
517 | ||
518 | } | |
519 | RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); | |
520 | RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); | |
521 | RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); | |
522 | ||
523 | } | |
524 | ||
525 | static void r600_test_writeback(drm_radeon_private_t *dev_priv) | |
526 | { | |
527 | u32 tmp; | |
528 | ||
529 | /* Start with assuming that writeback doesn't work */ | |
530 | dev_priv->writeback_works = 0; | |
531 | ||
532 | /* Writeback doesn't seem to work everywhere, test it here and possibly | |
533 | * enable it if it appears to work | |
534 | */ | |
535 | radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); | |
536 | ||
537 | RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef); | |
538 | ||
539 | for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { | |
540 | u32 val; | |
541 | ||
542 | val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1)); | |
543 | if (val == 0xdeadbeef) | |
544 | break; | |
545 | DRM_UDELAY(1); | |
546 | } | |
547 | ||
548 | if (tmp < dev_priv->usec_timeout) { | |
549 | dev_priv->writeback_works = 1; | |
550 | DRM_INFO("writeback test succeeded in %d usecs\n", tmp); | |
551 | } else { | |
552 | dev_priv->writeback_works = 0; | |
553 | DRM_INFO("writeback test failed\n"); | |
554 | } | |
555 | if (radeon_no_wb == 1) { | |
556 | dev_priv->writeback_works = 0; | |
557 | DRM_INFO("writeback forced off\n"); | |
558 | } | |
559 | ||
560 | if (!dev_priv->writeback_works) { | |
561 | /* Disable writeback to avoid unnecessary bus master transfer */ | |
562 | RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) | | |
563 | RADEON_RB_NO_UPDATE); | |
564 | RADEON_WRITE(R600_SCRATCH_UMSK, 0); | |
565 | } | |
566 | } | |
567 | ||
568 | int r600_do_engine_reset(struct drm_device *dev) | |
569 | { | |
570 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
571 | u32 cp_ptr, cp_me_cntl, cp_rb_cntl; | |
572 | ||
573 | DRM_INFO("Resetting GPU\n"); | |
574 | ||
575 | cp_ptr = RADEON_READ(R600_CP_RB_WPTR); | |
576 | cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL); | |
577 | RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT); | |
578 | ||
579 | RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff); | |
580 | RADEON_READ(R600_GRBM_SOFT_RESET); | |
581 | DRM_UDELAY(50); | |
582 | RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); | |
583 | RADEON_READ(R600_GRBM_SOFT_RESET); | |
584 | ||
585 | RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); | |
586 | cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL); | |
587 | RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA); | |
588 | ||
589 | RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr); | |
590 | RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr); | |
591 | RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl); | |
592 | RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl); | |
593 | ||
594 | /* Reset the CP ring */ | |
595 | r600_do_cp_reset(dev_priv); | |
596 | ||
597 | /* The CP is no longer running after an engine reset */ | |
598 | dev_priv->cp_running = 0; | |
599 | ||
600 | /* Reset any pending vertex, indirect buffers */ | |
601 | radeon_freelist_reset(dev); | |
602 | ||
603 | return 0; | |
604 | ||
605 | } | |
606 | ||
607 | static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, | |
608 | u32 num_backends, | |
609 | u32 backend_disable_mask) | |
610 | { | |
611 | u32 backend_map = 0; | |
612 | u32 enabled_backends_mask; | |
613 | u32 enabled_backends_count; | |
614 | u32 cur_pipe; | |
615 | u32 swizzle_pipe[R6XX_MAX_PIPES]; | |
616 | u32 cur_backend; | |
617 | u32 i; | |
618 | ||
619 | if (num_tile_pipes > R6XX_MAX_PIPES) | |
620 | num_tile_pipes = R6XX_MAX_PIPES; | |
621 | if (num_tile_pipes < 1) | |
622 | num_tile_pipes = 1; | |
623 | if (num_backends > R6XX_MAX_BACKENDS) | |
624 | num_backends = R6XX_MAX_BACKENDS; | |
625 | if (num_backends < 1) | |
626 | num_backends = 1; | |
627 | ||
628 | enabled_backends_mask = 0; | |
629 | enabled_backends_count = 0; | |
630 | for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { | |
631 | if (((backend_disable_mask >> i) & 1) == 0) { | |
632 | enabled_backends_mask |= (1 << i); | |
633 | ++enabled_backends_count; | |
634 | } | |
635 | if (enabled_backends_count == num_backends) | |
636 | break; | |
637 | } | |
638 | ||
639 | if (enabled_backends_count == 0) { | |
640 | enabled_backends_mask = 1; | |
641 | enabled_backends_count = 1; | |
642 | } | |
643 | ||
644 | if (enabled_backends_count != num_backends) | |
645 | num_backends = enabled_backends_count; | |
646 | ||
647 | memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); | |
648 | switch (num_tile_pipes) { | |
649 | case 1: | |
650 | swizzle_pipe[0] = 0; | |
651 | break; | |
652 | case 2: | |
653 | swizzle_pipe[0] = 0; | |
654 | swizzle_pipe[1] = 1; | |
655 | break; | |
656 | case 3: | |
657 | swizzle_pipe[0] = 0; | |
658 | swizzle_pipe[1] = 1; | |
659 | swizzle_pipe[2] = 2; | |
660 | break; | |
661 | case 4: | |
662 | swizzle_pipe[0] = 0; | |
663 | swizzle_pipe[1] = 1; | |
664 | swizzle_pipe[2] = 2; | |
665 | swizzle_pipe[3] = 3; | |
666 | break; | |
667 | case 5: | |
668 | swizzle_pipe[0] = 0; | |
669 | swizzle_pipe[1] = 1; | |
670 | swizzle_pipe[2] = 2; | |
671 | swizzle_pipe[3] = 3; | |
672 | swizzle_pipe[4] = 4; | |
673 | break; | |
674 | case 6: | |
675 | swizzle_pipe[0] = 0; | |
676 | swizzle_pipe[1] = 2; | |
677 | swizzle_pipe[2] = 4; | |
678 | swizzle_pipe[3] = 5; | |
679 | swizzle_pipe[4] = 1; | |
680 | swizzle_pipe[5] = 3; | |
681 | break; | |
682 | case 7: | |
683 | swizzle_pipe[0] = 0; | |
684 | swizzle_pipe[1] = 2; | |
685 | swizzle_pipe[2] = 4; | |
686 | swizzle_pipe[3] = 6; | |
687 | swizzle_pipe[4] = 1; | |
688 | swizzle_pipe[5] = 3; | |
689 | swizzle_pipe[6] = 5; | |
690 | break; | |
691 | case 8: | |
692 | swizzle_pipe[0] = 0; | |
693 | swizzle_pipe[1] = 2; | |
694 | swizzle_pipe[2] = 4; | |
695 | swizzle_pipe[3] = 6; | |
696 | swizzle_pipe[4] = 1; | |
697 | swizzle_pipe[5] = 3; | |
698 | swizzle_pipe[6] = 5; | |
699 | swizzle_pipe[7] = 7; | |
700 | break; | |
701 | } | |
702 | ||
703 | cur_backend = 0; | |
704 | for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { | |
705 | while (((1 << cur_backend) & enabled_backends_mask) == 0) | |
706 | cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; | |
707 | ||
708 | backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); | |
709 | ||
710 | cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; | |
711 | } | |
712 | ||
713 | return backend_map; | |
714 | } | |
715 | ||
716 | static int r600_count_pipe_bits(uint32_t val) | |
717 | { | |
718 | int i, ret = 0; | |
719 | for (i = 0; i < 32; i++) { | |
720 | ret += val & 1; | |
721 | val >>= 1; | |
722 | } | |
723 | return ret; | |
724 | } | |
725 | ||
726 | static void r600_gfx_init(struct drm_device *dev, | |
727 | drm_radeon_private_t *dev_priv) | |
728 | { | |
729 | int i, j, num_qd_pipes; | |
730 | u32 sx_debug_1; | |
731 | u32 tc_cntl; | |
732 | u32 arb_pop; | |
733 | u32 num_gs_verts_per_thread; | |
734 | u32 vgt_gs_per_es; | |
735 | u32 gs_prim_buffer_depth = 0; | |
736 | u32 sq_ms_fifo_sizes; | |
737 | u32 sq_config; | |
738 | u32 sq_gpr_resource_mgmt_1 = 0; | |
739 | u32 sq_gpr_resource_mgmt_2 = 0; | |
740 | u32 sq_thread_resource_mgmt = 0; | |
741 | u32 sq_stack_resource_mgmt_1 = 0; | |
742 | u32 sq_stack_resource_mgmt_2 = 0; | |
743 | u32 hdp_host_path_cntl; | |
744 | u32 backend_map; | |
745 | u32 gb_tiling_config = 0; | |
746 | u32 cc_rb_backend_disable = 0; | |
747 | u32 cc_gc_shader_pipe_config = 0; | |
748 | u32 ramcfg; | |
749 | ||
750 | /* setup chip specs */ | |
751 | switch (dev_priv->flags & RADEON_FAMILY_MASK) { | |
752 | case CHIP_R600: | |
753 | dev_priv->r600_max_pipes = 4; | |
754 | dev_priv->r600_max_tile_pipes = 8; | |
755 | dev_priv->r600_max_simds = 4; | |
756 | dev_priv->r600_max_backends = 4; | |
757 | dev_priv->r600_max_gprs = 256; | |
758 | dev_priv->r600_max_threads = 192; | |
759 | dev_priv->r600_max_stack_entries = 256; | |
760 | dev_priv->r600_max_hw_contexts = 8; | |
761 | dev_priv->r600_max_gs_threads = 16; | |
762 | dev_priv->r600_sx_max_export_size = 128; | |
763 | dev_priv->r600_sx_max_export_pos_size = 16; | |
764 | dev_priv->r600_sx_max_export_smx_size = 128; | |
765 | dev_priv->r600_sq_num_cf_insts = 2; | |
766 | break; | |
767 | case CHIP_RV630: | |
768 | case CHIP_RV635: | |
769 | dev_priv->r600_max_pipes = 2; | |
770 | dev_priv->r600_max_tile_pipes = 2; | |
771 | dev_priv->r600_max_simds = 3; | |
772 | dev_priv->r600_max_backends = 1; | |
773 | dev_priv->r600_max_gprs = 128; | |
774 | dev_priv->r600_max_threads = 192; | |
775 | dev_priv->r600_max_stack_entries = 128; | |
776 | dev_priv->r600_max_hw_contexts = 8; | |
777 | dev_priv->r600_max_gs_threads = 4; | |
778 | dev_priv->r600_sx_max_export_size = 128; | |
779 | dev_priv->r600_sx_max_export_pos_size = 16; | |
780 | dev_priv->r600_sx_max_export_smx_size = 128; | |
781 | dev_priv->r600_sq_num_cf_insts = 2; | |
782 | break; | |
783 | case CHIP_RV610: | |
784 | case CHIP_RS780: | |
785 | case CHIP_RV620: | |
786 | dev_priv->r600_max_pipes = 1; | |
787 | dev_priv->r600_max_tile_pipes = 1; | |
788 | dev_priv->r600_max_simds = 2; | |
789 | dev_priv->r600_max_backends = 1; | |
790 | dev_priv->r600_max_gprs = 128; | |
791 | dev_priv->r600_max_threads = 192; | |
792 | dev_priv->r600_max_stack_entries = 128; | |
793 | dev_priv->r600_max_hw_contexts = 4; | |
794 | dev_priv->r600_max_gs_threads = 4; | |
795 | dev_priv->r600_sx_max_export_size = 128; | |
796 | dev_priv->r600_sx_max_export_pos_size = 16; | |
797 | dev_priv->r600_sx_max_export_smx_size = 128; | |
798 | dev_priv->r600_sq_num_cf_insts = 1; | |
799 | break; | |
800 | case CHIP_RV670: | |
801 | dev_priv->r600_max_pipes = 4; | |
802 | dev_priv->r600_max_tile_pipes = 4; | |
803 | dev_priv->r600_max_simds = 4; | |
804 | dev_priv->r600_max_backends = 4; | |
805 | dev_priv->r600_max_gprs = 192; | |
806 | dev_priv->r600_max_threads = 192; | |
807 | dev_priv->r600_max_stack_entries = 256; | |
808 | dev_priv->r600_max_hw_contexts = 8; | |
809 | dev_priv->r600_max_gs_threads = 16; | |
810 | dev_priv->r600_sx_max_export_size = 128; | |
811 | dev_priv->r600_sx_max_export_pos_size = 16; | |
812 | dev_priv->r600_sx_max_export_smx_size = 128; | |
813 | dev_priv->r600_sq_num_cf_insts = 2; | |
814 | break; | |
815 | default: | |
816 | break; | |
817 | } | |
818 | ||
819 | /* Initialize HDP */ | |
820 | j = 0; | |
821 | for (i = 0; i < 32; i++) { | |
822 | RADEON_WRITE((0x2c14 + j), 0x00000000); | |
823 | RADEON_WRITE((0x2c18 + j), 0x00000000); | |
824 | RADEON_WRITE((0x2c1c + j), 0x00000000); | |
825 | RADEON_WRITE((0x2c20 + j), 0x00000000); | |
826 | RADEON_WRITE((0x2c24 + j), 0x00000000); | |
827 | j += 0x18; | |
828 | } | |
829 | ||
830 | RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); | |
831 | ||
832 | /* setup tiling, simd, pipe config */ | |
833 | ramcfg = RADEON_READ(R600_RAMCFG); | |
834 | ||
835 | switch (dev_priv->r600_max_tile_pipes) { | |
836 | case 1: | |
837 | gb_tiling_config |= R600_PIPE_TILING(0); | |
838 | break; | |
839 | case 2: | |
840 | gb_tiling_config |= R600_PIPE_TILING(1); | |
841 | break; | |
842 | case 4: | |
843 | gb_tiling_config |= R600_PIPE_TILING(2); | |
844 | break; | |
845 | case 8: | |
846 | gb_tiling_config |= R600_PIPE_TILING(3); | |
847 | break; | |
848 | default: | |
849 | break; | |
850 | } | |
851 | ||
852 | gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK); | |
853 | ||
854 | gb_tiling_config |= R600_GROUP_SIZE(0); | |
855 | ||
856 | if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) { | |
857 | gb_tiling_config |= R600_ROW_TILING(3); | |
858 | gb_tiling_config |= R600_SAMPLE_SPLIT(3); | |
859 | } else { | |
860 | gb_tiling_config |= | |
861 | R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK)); | |
862 | gb_tiling_config |= | |
863 | R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK)); | |
864 | } | |
865 | ||
866 | gb_tiling_config |= R600_BANK_SWAPS(1); | |
867 | ||
868 | backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, | |
869 | dev_priv->r600_max_backends, | |
870 | (0xff << dev_priv->r600_max_backends) & 0xff); | |
871 | gb_tiling_config |= R600_BACKEND_MAP(backend_map); | |
872 | ||
873 | cc_gc_shader_pipe_config = | |
874 | R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK); | |
875 | cc_gc_shader_pipe_config |= | |
876 | R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK); | |
877 | ||
878 | cc_rb_backend_disable = | |
879 | R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK); | |
880 | ||
881 | RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); | |
882 | RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); | |
883 | RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); | |
884 | ||
885 | RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); | |
886 | RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); | |
887 | RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); | |
888 | ||
889 | num_qd_pipes = | |
890 | R6XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK); | |
891 | RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); | |
892 | RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); | |
893 | ||
894 | /* set HW defaults for 3D engine */ | |
895 | RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | | |
896 | R600_ROQ_IB2_START(0x2b))); | |
897 | ||
898 | RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) | | |
899 | R600_ROQ_END(0x40))); | |
900 | ||
901 | RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO | | |
902 | R600_SYNC_GRADIENT | | |
903 | R600_SYNC_WALKER | | |
904 | R600_SYNC_ALIGNER)); | |
905 | ||
906 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) | |
907 | RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021); | |
908 | ||
909 | sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1); | |
910 | sx_debug_1 |= R600_SMX_EVENT_RELEASE; | |
911 | if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600)) | |
912 | sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS; | |
913 | RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1); | |
914 | ||
915 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || | |
916 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || | |
917 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || | |
918 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || | |
919 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) | |
920 | RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE); | |
921 | else | |
922 | RADEON_WRITE(R600_DB_DEBUG, 0); | |
923 | ||
924 | RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) | | |
925 | R600_DEPTH_FLUSH(16) | | |
926 | R600_DEPTH_PENDING_FREE(4) | | |
927 | R600_DEPTH_CACHELINE_FREE(16))); | |
928 | RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); | |
929 | RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0); | |
930 | ||
931 | RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); | |
932 | RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0)); | |
933 | ||
934 | sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES); | |
935 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || | |
936 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || | |
937 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) { | |
938 | sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) | | |
939 | R600_FETCH_FIFO_HIWATER(0xa) | | |
940 | R600_DONE_FIFO_HIWATER(0xe0) | | |
941 | R600_ALU_UPDATE_FIFO_HIWATER(0x8)); | |
942 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || | |
943 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) { | |
944 | sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff); | |
945 | sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4); | |
946 | } | |
947 | RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); | |
948 | ||
949 | /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT | |
950 | * should be adjusted as needed by the 2D/3D drivers. This just sets default values | |
951 | */ | |
952 | sq_config = RADEON_READ(R600_SQ_CONFIG); | |
953 | sq_config &= ~(R600_PS_PRIO(3) | | |
954 | R600_VS_PRIO(3) | | |
955 | R600_GS_PRIO(3) | | |
956 | R600_ES_PRIO(3)); | |
957 | sq_config |= (R600_DX9_CONSTS | | |
958 | R600_VC_ENABLE | | |
959 | R600_PS_PRIO(0) | | |
960 | R600_VS_PRIO(1) | | |
961 | R600_GS_PRIO(2) | | |
962 | R600_ES_PRIO(3)); | |
963 | ||
964 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) { | |
965 | sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) | | |
966 | R600_NUM_VS_GPRS(124) | | |
967 | R600_NUM_CLAUSE_TEMP_GPRS(4)); | |
968 | sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) | | |
969 | R600_NUM_ES_GPRS(0)); | |
970 | sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) | | |
971 | R600_NUM_VS_THREADS(48) | | |
972 | R600_NUM_GS_THREADS(4) | | |
973 | R600_NUM_ES_THREADS(4)); | |
974 | sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) | | |
975 | R600_NUM_VS_STACK_ENTRIES(128)); | |
976 | sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) | | |
977 | R600_NUM_ES_STACK_ENTRIES(0)); | |
978 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || | |
979 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || | |
980 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) { | |
981 | /* no vertex cache */ | |
982 | sq_config &= ~R600_VC_ENABLE; | |
983 | ||
984 | sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | | |
985 | R600_NUM_VS_GPRS(44) | | |
986 | R600_NUM_CLAUSE_TEMP_GPRS(2)); | |
987 | sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) | | |
988 | R600_NUM_ES_GPRS(17)); | |
989 | sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | | |
990 | R600_NUM_VS_THREADS(78) | | |
991 | R600_NUM_GS_THREADS(4) | | |
992 | R600_NUM_ES_THREADS(31)); | |
993 | sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) | | |
994 | R600_NUM_VS_STACK_ENTRIES(40)); | |
995 | sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) | | |
996 | R600_NUM_ES_STACK_ENTRIES(16)); | |
997 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || | |
998 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) { | |
999 | sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | | |
1000 | R600_NUM_VS_GPRS(44) | | |
1001 | R600_NUM_CLAUSE_TEMP_GPRS(2)); | |
1002 | sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) | | |
1003 | R600_NUM_ES_GPRS(18)); | |
1004 | sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | | |
1005 | R600_NUM_VS_THREADS(78) | | |
1006 | R600_NUM_GS_THREADS(4) | | |
1007 | R600_NUM_ES_THREADS(31)); | |
1008 | sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) | | |
1009 | R600_NUM_VS_STACK_ENTRIES(40)); | |
1010 | sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) | | |
1011 | R600_NUM_ES_STACK_ENTRIES(16)); | |
1012 | } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) { | |
1013 | sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | | |
1014 | R600_NUM_VS_GPRS(44) | | |
1015 | R600_NUM_CLAUSE_TEMP_GPRS(2)); | |
1016 | sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) | | |
1017 | R600_NUM_ES_GPRS(17)); | |
1018 | sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | | |
1019 | R600_NUM_VS_THREADS(78) | | |
1020 | R600_NUM_GS_THREADS(4) | | |
1021 | R600_NUM_ES_THREADS(31)); | |
1022 | sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) | | |
1023 | R600_NUM_VS_STACK_ENTRIES(64)); | |
1024 | sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) | | |
1025 | R600_NUM_ES_STACK_ENTRIES(64)); | |
1026 | } | |
1027 | ||
1028 | RADEON_WRITE(R600_SQ_CONFIG, sq_config); | |
1029 | RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); | |
1030 | RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); | |
1031 | RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); | |
1032 | RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); | |
1033 | RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); | |
1034 | ||
1035 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || | |
1036 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || | |
1037 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) | |
1038 | RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY)); | |
1039 | else | |
1040 | RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC)); | |
1041 | ||
1042 | RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) | | |
1043 | R600_S0_Y(0x4) | | |
1044 | R600_S1_X(0x4) | | |
1045 | R600_S1_Y(0xc))); | |
1046 | RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) | | |
1047 | R600_S0_Y(0xe) | | |
1048 | R600_S1_X(0x2) | | |
1049 | R600_S1_Y(0x2) | | |
1050 | R600_S2_X(0xa) | | |
1051 | R600_S2_Y(0x6) | | |
1052 | R600_S3_X(0x6) | | |
1053 | R600_S3_Y(0xa))); | |
1054 | RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) | | |
1055 | R600_S0_Y(0xb) | | |
1056 | R600_S1_X(0x4) | | |
1057 | R600_S1_Y(0xc) | | |
1058 | R600_S2_X(0x1) | | |
1059 | R600_S2_Y(0x6) | | |
1060 | R600_S3_X(0xa) | | |
1061 | R600_S3_Y(0xe))); | |
1062 | RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) | | |
1063 | R600_S4_Y(0x1) | | |
1064 | R600_S5_X(0x0) | | |
1065 | R600_S5_Y(0x0) | | |
1066 | R600_S6_X(0xb) | | |
1067 | R600_S6_Y(0x4) | | |
1068 | R600_S7_X(0x7) | | |
1069 | R600_S7_Y(0x8))); | |
1070 | ||
1071 | ||
1072 | switch (dev_priv->flags & RADEON_FAMILY_MASK) { | |
1073 | case CHIP_R600: | |
1074 | case CHIP_RV630: | |
1075 | case CHIP_RV635: | |
1076 | gs_prim_buffer_depth = 0; | |
1077 | break; | |
1078 | case CHIP_RV610: | |
1079 | case CHIP_RS780: | |
1080 | case CHIP_RV620: | |
1081 | gs_prim_buffer_depth = 32; | |
1082 | break; | |
1083 | case CHIP_RV670: | |
1084 | gs_prim_buffer_depth = 128; | |
1085 | break; | |
1086 | default: | |
1087 | break; | |
1088 | } | |
1089 | ||
1090 | num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; | |
1091 | vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; | |
1092 | /* Max value for this is 256 */ | |
1093 | if (vgt_gs_per_es > 256) | |
1094 | vgt_gs_per_es = 256; | |
1095 | ||
1096 | RADEON_WRITE(R600_VGT_ES_PER_GS, 128); | |
1097 | RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); | |
1098 | RADEON_WRITE(R600_VGT_GS_PER_VS, 2); | |
1099 | RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); | |
1100 | ||
1101 | /* more default values. 2D/3D driver should adjust as needed */ | |
1102 | RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); | |
1103 | RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); | |
1104 | RADEON_WRITE(R600_SX_MISC, 0); | |
1105 | RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); | |
1106 | RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); | |
1107 | RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); | |
1108 | RADEON_WRITE(R600_SPI_INPUT_Z, 0); | |
1109 | RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); | |
1110 | RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); | |
1111 | ||
1112 | /* clear render buffer base addresses */ | |
1113 | RADEON_WRITE(R600_CB_COLOR0_BASE, 0); | |
1114 | RADEON_WRITE(R600_CB_COLOR1_BASE, 0); | |
1115 | RADEON_WRITE(R600_CB_COLOR2_BASE, 0); | |
1116 | RADEON_WRITE(R600_CB_COLOR3_BASE, 0); | |
1117 | RADEON_WRITE(R600_CB_COLOR4_BASE, 0); | |
1118 | RADEON_WRITE(R600_CB_COLOR5_BASE, 0); | |
1119 | RADEON_WRITE(R600_CB_COLOR6_BASE, 0); | |
1120 | RADEON_WRITE(R600_CB_COLOR7_BASE, 0); | |
1121 | ||
1122 | switch (dev_priv->flags & RADEON_FAMILY_MASK) { | |
1123 | case CHIP_RV610: | |
1124 | case CHIP_RS780: | |
1125 | case CHIP_RV620: | |
1126 | tc_cntl = R600_TC_L2_SIZE(8); | |
1127 | break; | |
1128 | case CHIP_RV630: | |
1129 | case CHIP_RV635: | |
1130 | tc_cntl = R600_TC_L2_SIZE(4); | |
1131 | break; | |
1132 | case CHIP_R600: | |
1133 | tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT; | |
1134 | break; | |
1135 | default: | |
1136 | tc_cntl = R600_TC_L2_SIZE(0); | |
1137 | break; | |
1138 | } | |
1139 | ||
1140 | RADEON_WRITE(R600_TC_CNTL, tc_cntl); | |
1141 | ||
1142 | hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL); | |
1143 | RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); | |
1144 | ||
1145 | arb_pop = RADEON_READ(R600_ARB_POP); | |
1146 | arb_pop |= R600_ENABLE_TC128; | |
1147 | RADEON_WRITE(R600_ARB_POP, arb_pop); | |
1148 | ||
1149 | RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); | |
1150 | RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | | |
1151 | R600_NUM_CLIP_SEQ(3))); | |
1152 | RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095)); | |
1153 | ||
1154 | } | |
1155 | ||
1156 | static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes, | |
1157 | u32 num_backends, | |
1158 | u32 backend_disable_mask) | |
1159 | { | |
1160 | u32 backend_map = 0; | |
1161 | u32 enabled_backends_mask; | |
1162 | u32 enabled_backends_count; | |
1163 | u32 cur_pipe; | |
1164 | u32 swizzle_pipe[R7XX_MAX_PIPES]; | |
1165 | u32 cur_backend; | |
1166 | u32 i; | |
1167 | ||
1168 | if (num_tile_pipes > R7XX_MAX_PIPES) | |
1169 | num_tile_pipes = R7XX_MAX_PIPES; | |
1170 | if (num_tile_pipes < 1) | |
1171 | num_tile_pipes = 1; | |
1172 | if (num_backends > R7XX_MAX_BACKENDS) | |
1173 | num_backends = R7XX_MAX_BACKENDS; | |
1174 | if (num_backends < 1) | |
1175 | num_backends = 1; | |
1176 | ||
1177 | enabled_backends_mask = 0; | |
1178 | enabled_backends_count = 0; | |
1179 | for (i = 0; i < R7XX_MAX_BACKENDS; ++i) { | |
1180 | if (((backend_disable_mask >> i) & 1) == 0) { | |
1181 | enabled_backends_mask |= (1 << i); | |
1182 | ++enabled_backends_count; | |
1183 | } | |
1184 | if (enabled_backends_count == num_backends) | |
1185 | break; | |
1186 | } | |
1187 | ||
1188 | if (enabled_backends_count == 0) { | |
1189 | enabled_backends_mask = 1; | |
1190 | enabled_backends_count = 1; | |
1191 | } | |
1192 | ||
1193 | if (enabled_backends_count != num_backends) | |
1194 | num_backends = enabled_backends_count; | |
1195 | ||
1196 | memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); | |
1197 | switch (num_tile_pipes) { | |
1198 | case 1: | |
1199 | swizzle_pipe[0] = 0; | |
1200 | break; | |
1201 | case 2: | |
1202 | swizzle_pipe[0] = 0; | |
1203 | swizzle_pipe[1] = 1; | |
1204 | break; | |
1205 | case 3: | |
1206 | swizzle_pipe[0] = 0; | |
1207 | swizzle_pipe[1] = 2; | |
1208 | swizzle_pipe[2] = 1; | |
1209 | break; | |
1210 | case 4: | |
1211 | swizzle_pipe[0] = 0; | |
1212 | swizzle_pipe[1] = 2; | |
1213 | swizzle_pipe[2] = 3; | |
1214 | swizzle_pipe[3] = 1; | |
1215 | break; | |
1216 | case 5: | |
1217 | swizzle_pipe[0] = 0; | |
1218 | swizzle_pipe[1] = 2; | |
1219 | swizzle_pipe[2] = 4; | |
1220 | swizzle_pipe[3] = 1; | |
1221 | swizzle_pipe[4] = 3; | |
1222 | break; | |
1223 | case 6: | |
1224 | swizzle_pipe[0] = 0; | |
1225 | swizzle_pipe[1] = 2; | |
1226 | swizzle_pipe[2] = 4; | |
1227 | swizzle_pipe[3] = 5; | |
1228 | swizzle_pipe[4] = 3; | |
1229 | swizzle_pipe[5] = 1; | |
1230 | break; | |
1231 | case 7: | |
1232 | swizzle_pipe[0] = 0; | |
1233 | swizzle_pipe[1] = 2; | |
1234 | swizzle_pipe[2] = 4; | |
1235 | swizzle_pipe[3] = 6; | |
1236 | swizzle_pipe[4] = 3; | |
1237 | swizzle_pipe[5] = 1; | |
1238 | swizzle_pipe[6] = 5; | |
1239 | break; | |
1240 | case 8: | |
1241 | swizzle_pipe[0] = 0; | |
1242 | swizzle_pipe[1] = 2; | |
1243 | swizzle_pipe[2] = 4; | |
1244 | swizzle_pipe[3] = 6; | |
1245 | swizzle_pipe[4] = 3; | |
1246 | swizzle_pipe[5] = 1; | |
1247 | swizzle_pipe[6] = 7; | |
1248 | swizzle_pipe[7] = 5; | |
1249 | break; | |
1250 | } | |
1251 | ||
1252 | cur_backend = 0; | |
1253 | for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { | |
1254 | while (((1 << cur_backend) & enabled_backends_mask) == 0) | |
1255 | cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; | |
1256 | ||
1257 | backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); | |
1258 | ||
1259 | cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; | |
1260 | } | |
1261 | ||
1262 | return backend_map; | |
1263 | } | |
1264 | ||
1265 | static void r700_gfx_init(struct drm_device *dev, | |
1266 | drm_radeon_private_t *dev_priv) | |
1267 | { | |
1268 | int i, j, num_qd_pipes; | |
1269 | u32 sx_debug_1; | |
1270 | u32 smx_dc_ctl0; | |
1271 | u32 num_gs_verts_per_thread; | |
1272 | u32 vgt_gs_per_es; | |
1273 | u32 gs_prim_buffer_depth = 0; | |
1274 | u32 sq_ms_fifo_sizes; | |
1275 | u32 sq_config; | |
1276 | u32 sq_thread_resource_mgmt; | |
1277 | u32 hdp_host_path_cntl; | |
1278 | u32 sq_dyn_gpr_size_simd_ab_0; | |
1279 | u32 backend_map; | |
1280 | u32 gb_tiling_config = 0; | |
1281 | u32 cc_rb_backend_disable = 0; | |
1282 | u32 cc_gc_shader_pipe_config = 0; | |
1283 | u32 mc_arb_ramcfg; | |
1284 | u32 db_debug4; | |
1285 | ||
1286 | /* setup chip specs */ | |
1287 | switch (dev_priv->flags & RADEON_FAMILY_MASK) { | |
1288 | case CHIP_RV770: | |
1289 | dev_priv->r600_max_pipes = 4; | |
1290 | dev_priv->r600_max_tile_pipes = 8; | |
1291 | dev_priv->r600_max_simds = 10; | |
1292 | dev_priv->r600_max_backends = 4; | |
1293 | dev_priv->r600_max_gprs = 256; | |
1294 | dev_priv->r600_max_threads = 248; | |
1295 | dev_priv->r600_max_stack_entries = 512; | |
1296 | dev_priv->r600_max_hw_contexts = 8; | |
1297 | dev_priv->r600_max_gs_threads = 16 * 2; | |
1298 | dev_priv->r600_sx_max_export_size = 128; | |
1299 | dev_priv->r600_sx_max_export_pos_size = 16; | |
1300 | dev_priv->r600_sx_max_export_smx_size = 112; | |
1301 | dev_priv->r600_sq_num_cf_insts = 2; | |
1302 | ||
1303 | dev_priv->r700_sx_num_of_sets = 7; | |
1304 | dev_priv->r700_sc_prim_fifo_size = 0xF9; | |
1305 | dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; | |
1306 | dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; | |
1307 | break; | |
1308 | case CHIP_RV730: | |
1309 | dev_priv->r600_max_pipes = 2; | |
1310 | dev_priv->r600_max_tile_pipes = 4; | |
1311 | dev_priv->r600_max_simds = 8; | |
1312 | dev_priv->r600_max_backends = 2; | |
1313 | dev_priv->r600_max_gprs = 128; | |
1314 | dev_priv->r600_max_threads = 248; | |
1315 | dev_priv->r600_max_stack_entries = 256; | |
1316 | dev_priv->r600_max_hw_contexts = 8; | |
1317 | dev_priv->r600_max_gs_threads = 16 * 2; | |
1318 | dev_priv->r600_sx_max_export_size = 256; | |
1319 | dev_priv->r600_sx_max_export_pos_size = 32; | |
1320 | dev_priv->r600_sx_max_export_smx_size = 224; | |
1321 | dev_priv->r600_sq_num_cf_insts = 2; | |
1322 | ||
1323 | dev_priv->r700_sx_num_of_sets = 7; | |
1324 | dev_priv->r700_sc_prim_fifo_size = 0xf9; | |
1325 | dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; | |
1326 | dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; | |
1327 | break; | |
1328 | case CHIP_RV710: | |
1329 | dev_priv->r600_max_pipes = 2; | |
1330 | dev_priv->r600_max_tile_pipes = 2; | |
1331 | dev_priv->r600_max_simds = 2; | |
1332 | dev_priv->r600_max_backends = 1; | |
1333 | dev_priv->r600_max_gprs = 256; | |
1334 | dev_priv->r600_max_threads = 192; | |
1335 | dev_priv->r600_max_stack_entries = 256; | |
1336 | dev_priv->r600_max_hw_contexts = 4; | |
1337 | dev_priv->r600_max_gs_threads = 8 * 2; | |
1338 | dev_priv->r600_sx_max_export_size = 128; | |
1339 | dev_priv->r600_sx_max_export_pos_size = 16; | |
1340 | dev_priv->r600_sx_max_export_smx_size = 112; | |
1341 | dev_priv->r600_sq_num_cf_insts = 1; | |
1342 | ||
1343 | dev_priv->r700_sx_num_of_sets = 7; | |
1344 | dev_priv->r700_sc_prim_fifo_size = 0x40; | |
1345 | dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; | |
1346 | dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; | |
1347 | break; | |
1348 | default: | |
1349 | break; | |
1350 | } | |
1351 | ||
1352 | /* Initialize HDP */ | |
1353 | j = 0; | |
1354 | for (i = 0; i < 32; i++) { | |
1355 | RADEON_WRITE((0x2c14 + j), 0x00000000); | |
1356 | RADEON_WRITE((0x2c18 + j), 0x00000000); | |
1357 | RADEON_WRITE((0x2c1c + j), 0x00000000); | |
1358 | RADEON_WRITE((0x2c20 + j), 0x00000000); | |
1359 | RADEON_WRITE((0x2c24 + j), 0x00000000); | |
1360 | j += 0x18; | |
1361 | } | |
1362 | ||
1363 | RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); | |
1364 | ||
1365 | /* setup tiling, simd, pipe config */ | |
1366 | mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG); | |
1367 | ||
1368 | switch (dev_priv->r600_max_tile_pipes) { | |
1369 | case 1: | |
1370 | gb_tiling_config |= R600_PIPE_TILING(0); | |
1371 | break; | |
1372 | case 2: | |
1373 | gb_tiling_config |= R600_PIPE_TILING(1); | |
1374 | break; | |
1375 | case 4: | |
1376 | gb_tiling_config |= R600_PIPE_TILING(2); | |
1377 | break; | |
1378 | case 8: | |
1379 | gb_tiling_config |= R600_PIPE_TILING(3); | |
1380 | break; | |
1381 | default: | |
1382 | break; | |
1383 | } | |
1384 | ||
1385 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770) | |
1386 | gb_tiling_config |= R600_BANK_TILING(1); | |
1387 | else | |
1388 | gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK); | |
1389 | ||
1390 | gb_tiling_config |= R600_GROUP_SIZE(0); | |
1391 | ||
1392 | if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) { | |
1393 | gb_tiling_config |= R600_ROW_TILING(3); | |
1394 | gb_tiling_config |= R600_SAMPLE_SPLIT(3); | |
1395 | } else { | |
1396 | gb_tiling_config |= | |
1397 | R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK)); | |
1398 | gb_tiling_config |= | |
1399 | R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK)); | |
1400 | } | |
1401 | ||
1402 | gb_tiling_config |= R600_BANK_SWAPS(1); | |
1403 | ||
1404 | backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, | |
1405 | dev_priv->r600_max_backends, | |
1406 | (0xff << dev_priv->r600_max_backends) & 0xff); | |
1407 | gb_tiling_config |= R600_BACKEND_MAP(backend_map); | |
1408 | ||
1409 | cc_gc_shader_pipe_config = | |
1410 | R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK); | |
1411 | cc_gc_shader_pipe_config |= | |
1412 | R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK); | |
1413 | ||
1414 | cc_rb_backend_disable = | |
1415 | R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK); | |
1416 | ||
1417 | RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); | |
1418 | RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); | |
1419 | RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); | |
1420 | ||
1421 | RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); | |
1422 | RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); | |
1423 | RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); | |
1424 | ||
1425 | RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); | |
1426 | RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0); | |
1427 | RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0); | |
1428 | RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0); | |
1429 | RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0); | |
1430 | ||
1431 | num_qd_pipes = | |
1432 | R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK); | |
1433 | RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); | |
1434 | RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); | |
1435 | ||
1436 | /* set HW defaults for 3D engine */ | |
1437 | RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | | |
1438 | R600_ROQ_IB2_START(0x2b))); | |
1439 | ||
1440 | RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30)); | |
1441 | ||
1442 | RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO | | |
1443 | R600_SYNC_GRADIENT | | |
1444 | R600_SYNC_WALKER | | |
1445 | R600_SYNC_ALIGNER)); | |
1446 | ||
1447 | sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1); | |
1448 | sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS; | |
1449 | RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1); | |
1450 | ||
1451 | smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0); | |
1452 | smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff); | |
1453 | smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1); | |
1454 | RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0); | |
1455 | ||
1456 | RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) | | |
1457 | R700_GS_FLUSH_CTL(4) | | |
1458 | R700_ACK_FLUSH_CTL(3) | | |
1459 | R700_SYNC_FLUSH_CTL)); | |
1460 | ||
1461 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770) | |
1462 | RADEON_WRITE(R700_DB_DEBUG3, R700_DB_CLK_OFF_DELAY(0x1f)); | |
1463 | else { | |
1464 | db_debug4 = RADEON_READ(RV700_DB_DEBUG4); | |
1465 | db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER; | |
1466 | RADEON_WRITE(RV700_DB_DEBUG4, db_debug4); | |
1467 | } | |
1468 | ||
1469 | RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) | | |
1470 | R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) | | |
1471 | R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1))); | |
1472 | ||
1473 | RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) | | |
1474 | R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) | | |
1475 | R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize))); | |
1476 | ||
1477 | RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); | |
1478 | ||
1479 | RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1); | |
1480 | ||
1481 | RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); | |
1482 | ||
1483 | RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4)); | |
1484 | ||
1485 | RADEON_WRITE(R600_CP_PERFMON_CNTL, 0); | |
1486 | ||
1487 | sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) | | |
1488 | R600_DONE_FIFO_HIWATER(0xe0) | | |
1489 | R600_ALU_UPDATE_FIFO_HIWATER(0x8)); | |
1490 | switch (dev_priv->flags & RADEON_FAMILY_MASK) { | |
1491 | case CHIP_RV770: | |
1492 | sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1); | |
1493 | break; | |
1494 | case CHIP_RV730: | |
1495 | case CHIP_RV710: | |
1496 | default: | |
1497 | sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4); | |
1498 | break; | |
1499 | } | |
1500 | RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); | |
1501 | ||
1502 | /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT | |
1503 | * should be adjusted as needed by the 2D/3D drivers. This just sets default values | |
1504 | */ | |
1505 | sq_config = RADEON_READ(R600_SQ_CONFIG); | |
1506 | sq_config &= ~(R600_PS_PRIO(3) | | |
1507 | R600_VS_PRIO(3) | | |
1508 | R600_GS_PRIO(3) | | |
1509 | R600_ES_PRIO(3)); | |
1510 | sq_config |= (R600_DX9_CONSTS | | |
1511 | R600_VC_ENABLE | | |
1512 | R600_EXPORT_SRC_C | | |
1513 | R600_PS_PRIO(0) | | |
1514 | R600_VS_PRIO(1) | | |
1515 | R600_GS_PRIO(2) | | |
1516 | R600_ES_PRIO(3)); | |
1517 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) | |
1518 | /* no vertex cache */ | |
1519 | sq_config &= ~R600_VC_ENABLE; | |
1520 | ||
1521 | RADEON_WRITE(R600_SQ_CONFIG, sq_config); | |
1522 | ||
1523 | RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) | | |
1524 | R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) | | |
1525 | R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2))); | |
1526 | ||
1527 | RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) | | |
1528 | R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64))); | |
1529 | ||
1530 | sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) | | |
1531 | R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) | | |
1532 | R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8)); | |
1533 | if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads) | |
1534 | sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads); | |
1535 | else | |
1536 | sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8); | |
1537 | RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); | |
1538 | ||
1539 | RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) | | |
1540 | R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); | |
1541 | ||
1542 | RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) | | |
1543 | R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); | |
1544 | ||
1545 | sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) | | |
1546 | R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) | | |
1547 | R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) | | |
1548 | R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64)); | |
1549 | ||
1550 | RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); | |
1551 | RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); | |
1552 | RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); | |
1553 | RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); | |
1554 | RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); | |
1555 | RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); | |
1556 | RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); | |
1557 | RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); | |
1558 | ||
1559 | RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) | | |
1560 | R700_FORCE_EOV_MAX_REZ_CNT(255))); | |
1561 | ||
1562 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) | |
1563 | RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) | | |
1564 | R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO))); | |
1565 | else | |
1566 | RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) | | |
1567 | R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO))); | |
1568 | ||
1569 | switch (dev_priv->flags & RADEON_FAMILY_MASK) { | |
1570 | case CHIP_RV770: | |
1571 | case CHIP_RV730: | |
1572 | gs_prim_buffer_depth = 384; | |
1573 | break; | |
1574 | case CHIP_RV710: | |
1575 | gs_prim_buffer_depth = 128; | |
1576 | break; | |
1577 | default: | |
1578 | break; | |
1579 | } | |
1580 | ||
1581 | num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; | |
1582 | vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; | |
1583 | /* Max value for this is 256 */ | |
1584 | if (vgt_gs_per_es > 256) | |
1585 | vgt_gs_per_es = 256; | |
1586 | ||
1587 | RADEON_WRITE(R600_VGT_ES_PER_GS, 128); | |
1588 | RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); | |
1589 | RADEON_WRITE(R600_VGT_GS_PER_VS, 2); | |
1590 | ||
1591 | /* more default values. 2D/3D driver should adjust as needed */ | |
1592 | RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); | |
1593 | RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); | |
1594 | RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); | |
1595 | RADEON_WRITE(R600_SX_MISC, 0); | |
1596 | RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); | |
1597 | RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa); | |
1598 | RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); | |
1599 | RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff); | |
1600 | RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); | |
1601 | RADEON_WRITE(R600_SPI_INPUT_Z, 0); | |
1602 | RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); | |
1603 | RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); | |
1604 | ||
1605 | /* clear render buffer base addresses */ | |
1606 | RADEON_WRITE(R600_CB_COLOR0_BASE, 0); | |
1607 | RADEON_WRITE(R600_CB_COLOR1_BASE, 0); | |
1608 | RADEON_WRITE(R600_CB_COLOR2_BASE, 0); | |
1609 | RADEON_WRITE(R600_CB_COLOR3_BASE, 0); | |
1610 | RADEON_WRITE(R600_CB_COLOR4_BASE, 0); | |
1611 | RADEON_WRITE(R600_CB_COLOR5_BASE, 0); | |
1612 | RADEON_WRITE(R600_CB_COLOR6_BASE, 0); | |
1613 | RADEON_WRITE(R600_CB_COLOR7_BASE, 0); | |
1614 | ||
1615 | RADEON_WRITE(R700_TCP_CNTL, 0); | |
1616 | ||
1617 | hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL); | |
1618 | RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); | |
1619 | ||
1620 | RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); | |
1621 | ||
1622 | RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | | |
1623 | R600_NUM_CLIP_SEQ(3))); | |
1624 | ||
1625 | } | |
1626 | ||
1627 | static void r600_cp_init_ring_buffer(struct drm_device *dev, | |
1628 | drm_radeon_private_t *dev_priv, | |
1629 | struct drm_file *file_priv) | |
1630 | { | |
1631 | struct drm_radeon_master_private *master_priv; | |
1632 | u32 ring_start; | |
6546bf6d | 1633 | u64 rptr_addr; |
c05ce083 AD |
1634 | |
1635 | if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) | |
1636 | r700_gfx_init(dev, dev_priv); | |
1637 | else | |
1638 | r600_gfx_init(dev, dev_priv); | |
1639 | ||
1640 | RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); | |
1641 | RADEON_READ(R600_GRBM_SOFT_RESET); | |
1642 | DRM_UDELAY(15000); | |
1643 | RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); | |
1644 | ||
1645 | ||
1646 | /* Set ring buffer size */ | |
1647 | #ifdef __BIG_ENDIAN | |
1648 | RADEON_WRITE(R600_CP_RB_CNTL, | |
1649 | RADEON_BUF_SWAP_32BIT | | |
1650 | RADEON_RB_NO_UPDATE | | |
1651 | (dev_priv->ring.rptr_update_l2qw << 8) | | |
1652 | dev_priv->ring.size_l2qw); | |
1653 | #else | |
1654 | RADEON_WRITE(R600_CP_RB_CNTL, | |
1655 | RADEON_RB_NO_UPDATE | | |
1656 | (dev_priv->ring.rptr_update_l2qw << 8) | | |
1657 | dev_priv->ring.size_l2qw); | |
1658 | #endif | |
1659 | ||
1660 | RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x4); | |
1661 | ||
1662 | /* Set the write pointer delay */ | |
1663 | RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); | |
1664 | ||
1665 | #ifdef __BIG_ENDIAN | |
1666 | RADEON_WRITE(R600_CP_RB_CNTL, | |
1667 | RADEON_BUF_SWAP_32BIT | | |
1668 | RADEON_RB_NO_UPDATE | | |
1669 | RADEON_RB_RPTR_WR_ENA | | |
1670 | (dev_priv->ring.rptr_update_l2qw << 8) | | |
1671 | dev_priv->ring.size_l2qw); | |
1672 | #else | |
1673 | RADEON_WRITE(R600_CP_RB_CNTL, | |
1674 | RADEON_RB_NO_UPDATE | | |
1675 | RADEON_RB_RPTR_WR_ENA | | |
1676 | (dev_priv->ring.rptr_update_l2qw << 8) | | |
1677 | dev_priv->ring.size_l2qw); | |
1678 | #endif | |
1679 | ||
1680 | /* Initialize the ring buffer's read and write pointers */ | |
1681 | RADEON_WRITE(R600_CP_RB_RPTR_WR, 0); | |
1682 | RADEON_WRITE(R600_CP_RB_WPTR, 0); | |
1683 | SET_RING_HEAD(dev_priv, 0); | |
1684 | dev_priv->ring.tail = 0; | |
1685 | ||
1686 | #if __OS_HAS_AGP | |
1687 | if (dev_priv->flags & RADEON_IS_AGP) { | |
6546bf6d DA |
1688 | rptr_addr = dev_priv->ring_rptr->offset |
1689 | - dev->agp->base + | |
1690 | dev_priv->gart_vm_start; | |
c05ce083 AD |
1691 | } else |
1692 | #endif | |
1693 | { | |
6546bf6d DA |
1694 | rptr_addr = dev_priv->ring_rptr->offset |
1695 | - ((unsigned long) dev->sg->virtual) | |
1696 | + dev_priv->gart_vm_start; | |
c05ce083 | 1697 | } |
6546bf6d DA |
1698 | RADEON_WRITE(R600_CP_RB_RPTR_ADDR, |
1699 | rptr_addr & 0xffffffff); | |
1700 | RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, | |
1701 | upper_32_bits(rptr_addr)); | |
c05ce083 AD |
1702 | |
1703 | #ifdef __BIG_ENDIAN | |
1704 | RADEON_WRITE(R600_CP_RB_CNTL, | |
1705 | RADEON_BUF_SWAP_32BIT | | |
1706 | (dev_priv->ring.rptr_update_l2qw << 8) | | |
1707 | dev_priv->ring.size_l2qw); | |
1708 | #else | |
1709 | RADEON_WRITE(R600_CP_RB_CNTL, | |
1710 | (dev_priv->ring.rptr_update_l2qw << 8) | | |
1711 | dev_priv->ring.size_l2qw); | |
1712 | #endif | |
1713 | ||
1714 | #if __OS_HAS_AGP | |
1715 | if (dev_priv->flags & RADEON_IS_AGP) { | |
1716 | /* XXX */ | |
1717 | radeon_write_agp_base(dev_priv, dev->agp->base); | |
1718 | ||
1719 | /* XXX */ | |
1720 | radeon_write_agp_location(dev_priv, | |
1721 | (((dev_priv->gart_vm_start - 1 + | |
1722 | dev_priv->gart_size) & 0xffff0000) | | |
1723 | (dev_priv->gart_vm_start >> 16))); | |
1724 | ||
1725 | ring_start = (dev_priv->cp_ring->offset | |
1726 | - dev->agp->base | |
1727 | + dev_priv->gart_vm_start); | |
1728 | } else | |
1729 | #endif | |
1730 | ring_start = (dev_priv->cp_ring->offset | |
1731 | - (unsigned long)dev->sg->virtual | |
1732 | + dev_priv->gart_vm_start); | |
1733 | ||
1734 | RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8); | |
1735 | ||
1736 | RADEON_WRITE(R600_CP_ME_CNTL, 0xff); | |
1737 | ||
1738 | RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28)); | |
1739 | ||
c05ce083 AD |
1740 | /* Initialize the scratch register pointer. This will cause |
1741 | * the scratch register values to be written out to memory | |
1742 | * whenever they are updated. | |
1743 | * | |
1744 | * We simply put this behind the ring read pointer, this works | |
1745 | * with PCI GART as well as (whatever kind of) AGP GART | |
1746 | */ | |
6546bf6d DA |
1747 | { |
1748 | u64 scratch_addr; | |
1749 | ||
1750 | scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR); | |
1751 | scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32; | |
1752 | scratch_addr += R600_SCRATCH_REG_OFFSET; | |
1753 | scratch_addr >>= 8; | |
1754 | scratch_addr &= 0xffffffff; | |
1755 | ||
1756 | RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr); | |
1757 | } | |
c05ce083 AD |
1758 | |
1759 | RADEON_WRITE(R600_SCRATCH_UMSK, 0x7); | |
1760 | ||
1761 | /* Turn on bus mastering */ | |
1762 | radeon_enable_bm(dev_priv); | |
1763 | ||
1764 | radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0); | |
1765 | RADEON_WRITE(R600_LAST_FRAME_REG, 0); | |
1766 | ||
1767 | radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); | |
1768 | RADEON_WRITE(R600_LAST_DISPATCH_REG, 0); | |
1769 | ||
1770 | radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0); | |
1771 | RADEON_WRITE(R600_LAST_CLEAR_REG, 0); | |
1772 | ||
1773 | /* reset sarea copies of these */ | |
1774 | master_priv = file_priv->master->driver_priv; | |
1775 | if (master_priv->sarea_priv) { | |
1776 | master_priv->sarea_priv->last_frame = 0; | |
1777 | master_priv->sarea_priv->last_dispatch = 0; | |
1778 | master_priv->sarea_priv->last_clear = 0; | |
1779 | } | |
1780 | ||
1781 | r600_do_wait_for_idle(dev_priv); | |
1782 | ||
1783 | } | |
1784 | ||
1785 | int r600_do_cleanup_cp(struct drm_device *dev) | |
1786 | { | |
1787 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1788 | DRM_DEBUG("\n"); | |
1789 | ||
1790 | /* Make sure interrupts are disabled here because the uninstall ioctl | |
1791 | * may not have been called from userspace and after dev_private | |
1792 | * is freed, it's too late. | |
1793 | */ | |
1794 | if (dev->irq_enabled) | |
1795 | drm_irq_uninstall(dev); | |
1796 | ||
1797 | #if __OS_HAS_AGP | |
1798 | if (dev_priv->flags & RADEON_IS_AGP) { | |
1799 | if (dev_priv->cp_ring != NULL) { | |
1800 | drm_core_ioremapfree(dev_priv->cp_ring, dev); | |
1801 | dev_priv->cp_ring = NULL; | |
1802 | } | |
1803 | if (dev_priv->ring_rptr != NULL) { | |
1804 | drm_core_ioremapfree(dev_priv->ring_rptr, dev); | |
1805 | dev_priv->ring_rptr = NULL; | |
1806 | } | |
1807 | if (dev->agp_buffer_map != NULL) { | |
1808 | drm_core_ioremapfree(dev->agp_buffer_map, dev); | |
1809 | dev->agp_buffer_map = NULL; | |
1810 | } | |
1811 | } else | |
1812 | #endif | |
1813 | { | |
1814 | ||
1815 | if (dev_priv->gart_info.bus_addr) | |
1816 | r600_page_table_cleanup(dev, &dev_priv->gart_info); | |
1817 | ||
1818 | if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) { | |
1819 | drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); | |
8f497aad | 1820 | dev_priv->gart_info.addr = NULL; |
c05ce083 AD |
1821 | } |
1822 | } | |
1823 | /* only clear to the start of flags */ | |
1824 | memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); | |
1825 | ||
1826 | return 0; | |
1827 | } | |
1828 | ||
1829 | int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, | |
1830 | struct drm_file *file_priv) | |
1831 | { | |
1832 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1833 | struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; | |
1834 | ||
1835 | DRM_DEBUG("\n"); | |
1836 | ||
1837 | /* if we require new memory map but we don't have it fail */ | |
1838 | if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { | |
1839 | DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); | |
1840 | r600_do_cleanup_cp(dev); | |
1841 | return -EINVAL; | |
1842 | } | |
1843 | ||
1844 | if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { | |
1845 | DRM_DEBUG("Forcing AGP card to PCI mode\n"); | |
1846 | dev_priv->flags &= ~RADEON_IS_AGP; | |
1847 | /* The writeback test succeeds, but when writeback is enabled, | |
1848 | * the ring buffer read ptr update fails after first 128 bytes. | |
1849 | */ | |
1850 | radeon_no_wb = 1; | |
1851 | } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) | |
1852 | && !init->is_pci) { | |
1853 | DRM_DEBUG("Restoring AGP flag\n"); | |
1854 | dev_priv->flags |= RADEON_IS_AGP; | |
1855 | } | |
1856 | ||
1857 | dev_priv->usec_timeout = init->usec_timeout; | |
1858 | if (dev_priv->usec_timeout < 1 || | |
1859 | dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { | |
1860 | DRM_DEBUG("TIMEOUT problem!\n"); | |
1861 | r600_do_cleanup_cp(dev); | |
1862 | return -EINVAL; | |
1863 | } | |
1864 | ||
1865 | /* Enable vblank on CRTC1 for older X servers | |
1866 | */ | |
1867 | dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; | |
1868 | ||
1869 | dev_priv->cp_mode = init->cp_mode; | |
1870 | ||
1871 | /* We don't support anything other than bus-mastering ring mode, | |
1872 | * but the ring can be in either AGP or PCI space for the ring | |
1873 | * read pointer. | |
1874 | */ | |
1875 | if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && | |
1876 | (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { | |
1877 | DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); | |
1878 | r600_do_cleanup_cp(dev); | |
1879 | return -EINVAL; | |
1880 | } | |
1881 | ||
1882 | switch (init->fb_bpp) { | |
1883 | case 16: | |
1884 | dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; | |
1885 | break; | |
1886 | case 32: | |
1887 | default: | |
1888 | dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; | |
1889 | break; | |
1890 | } | |
1891 | dev_priv->front_offset = init->front_offset; | |
1892 | dev_priv->front_pitch = init->front_pitch; | |
1893 | dev_priv->back_offset = init->back_offset; | |
1894 | dev_priv->back_pitch = init->back_pitch; | |
1895 | ||
1896 | dev_priv->ring_offset = init->ring_offset; | |
1897 | dev_priv->ring_rptr_offset = init->ring_rptr_offset; | |
1898 | dev_priv->buffers_offset = init->buffers_offset; | |
1899 | dev_priv->gart_textures_offset = init->gart_textures_offset; | |
1900 | ||
1901 | master_priv->sarea = drm_getsarea(dev); | |
1902 | if (!master_priv->sarea) { | |
1903 | DRM_ERROR("could not find sarea!\n"); | |
1904 | r600_do_cleanup_cp(dev); | |
1905 | return -EINVAL; | |
1906 | } | |
1907 | ||
1908 | dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); | |
1909 | if (!dev_priv->cp_ring) { | |
1910 | DRM_ERROR("could not find cp ring region!\n"); | |
1911 | r600_do_cleanup_cp(dev); | |
1912 | return -EINVAL; | |
1913 | } | |
1914 | dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); | |
1915 | if (!dev_priv->ring_rptr) { | |
1916 | DRM_ERROR("could not find ring read pointer!\n"); | |
1917 | r600_do_cleanup_cp(dev); | |
1918 | return -EINVAL; | |
1919 | } | |
1920 | dev->agp_buffer_token = init->buffers_offset; | |
1921 | dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); | |
1922 | if (!dev->agp_buffer_map) { | |
1923 | DRM_ERROR("could not find dma buffer region!\n"); | |
1924 | r600_do_cleanup_cp(dev); | |
1925 | return -EINVAL; | |
1926 | } | |
1927 | ||
1928 | if (init->gart_textures_offset) { | |
1929 | dev_priv->gart_textures = | |
1930 | drm_core_findmap(dev, init->gart_textures_offset); | |
1931 | if (!dev_priv->gart_textures) { | |
1932 | DRM_ERROR("could not find GART texture region!\n"); | |
1933 | r600_do_cleanup_cp(dev); | |
1934 | return -EINVAL; | |
1935 | } | |
1936 | } | |
1937 | ||
1938 | #if __OS_HAS_AGP | |
1939 | /* XXX */ | |
1940 | if (dev_priv->flags & RADEON_IS_AGP) { | |
7659e980 AD |
1941 | drm_core_ioremap_wc(dev_priv->cp_ring, dev); |
1942 | drm_core_ioremap_wc(dev_priv->ring_rptr, dev); | |
1943 | drm_core_ioremap_wc(dev->agp_buffer_map, dev); | |
c05ce083 AD |
1944 | if (!dev_priv->cp_ring->handle || |
1945 | !dev_priv->ring_rptr->handle || | |
1946 | !dev->agp_buffer_map->handle) { | |
1947 | DRM_ERROR("could not find ioremap agp regions!\n"); | |
1948 | r600_do_cleanup_cp(dev); | |
1949 | return -EINVAL; | |
1950 | } | |
1951 | } else | |
1952 | #endif | |
1953 | { | |
1954 | dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset; | |
1955 | dev_priv->ring_rptr->handle = | |
1956 | (void *)dev_priv->ring_rptr->offset; | |
1957 | dev->agp_buffer_map->handle = | |
1958 | (void *)dev->agp_buffer_map->offset; | |
1959 | ||
1960 | DRM_DEBUG("dev_priv->cp_ring->handle %p\n", | |
1961 | dev_priv->cp_ring->handle); | |
1962 | DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", | |
1963 | dev_priv->ring_rptr->handle); | |
1964 | DRM_DEBUG("dev->agp_buffer_map->handle %p\n", | |
1965 | dev->agp_buffer_map->handle); | |
1966 | } | |
1967 | ||
1968 | dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24; | |
1969 | dev_priv->fb_size = | |
1970 | (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000) | |
1971 | - dev_priv->fb_location; | |
1972 | ||
1973 | dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | | |
1974 | ((dev_priv->front_offset | |
1975 | + dev_priv->fb_location) >> 10)); | |
1976 | ||
1977 | dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | | |
1978 | ((dev_priv->back_offset | |
1979 | + dev_priv->fb_location) >> 10)); | |
1980 | ||
1981 | dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | | |
1982 | ((dev_priv->depth_offset | |
1983 | + dev_priv->fb_location) >> 10)); | |
1984 | ||
1985 | dev_priv->gart_size = init->gart_size; | |
1986 | ||
1987 | /* New let's set the memory map ... */ | |
1988 | if (dev_priv->new_memmap) { | |
1989 | u32 base = 0; | |
1990 | ||
1991 | DRM_INFO("Setting GART location based on new memory map\n"); | |
1992 | ||
1993 | /* If using AGP, try to locate the AGP aperture at the same | |
1994 | * location in the card and on the bus, though we have to | |
1995 | * align it down. | |
1996 | */ | |
1997 | #if __OS_HAS_AGP | |
1998 | /* XXX */ | |
1999 | if (dev_priv->flags & RADEON_IS_AGP) { | |
2000 | base = dev->agp->base; | |
2001 | /* Check if valid */ | |
2002 | if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && | |
2003 | base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { | |
2004 | DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", | |
2005 | dev->agp->base); | |
2006 | base = 0; | |
2007 | } | |
2008 | } | |
2009 | #endif | |
2010 | /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ | |
2011 | if (base == 0) { | |
2012 | base = dev_priv->fb_location + dev_priv->fb_size; | |
2013 | if (base < dev_priv->fb_location || | |
2014 | ((base + dev_priv->gart_size) & 0xfffffffful) < base) | |
2015 | base = dev_priv->fb_location | |
2016 | - dev_priv->gart_size; | |
2017 | } | |
2018 | dev_priv->gart_vm_start = base & 0xffc00000u; | |
2019 | if (dev_priv->gart_vm_start != base) | |
2020 | DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", | |
2021 | base, dev_priv->gart_vm_start); | |
2022 | } | |
2023 | ||
2024 | #if __OS_HAS_AGP | |
2025 | /* XXX */ | |
2026 | if (dev_priv->flags & RADEON_IS_AGP) | |
2027 | dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset | |
2028 | - dev->agp->base | |
2029 | + dev_priv->gart_vm_start); | |
2030 | else | |
2031 | #endif | |
2032 | dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset | |
2033 | - (unsigned long)dev->sg->virtual | |
2034 | + dev_priv->gart_vm_start); | |
2035 | ||
2036 | DRM_DEBUG("fb 0x%08x size %d\n", | |
2037 | (unsigned int) dev_priv->fb_location, | |
2038 | (unsigned int) dev_priv->fb_size); | |
2039 | DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); | |
2040 | DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n", | |
2041 | (unsigned int) dev_priv->gart_vm_start); | |
2042 | DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n", | |
2043 | dev_priv->gart_buffers_offset); | |
2044 | ||
2045 | dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; | |
2046 | dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle | |
2047 | + init->ring_size / sizeof(u32)); | |
2048 | dev_priv->ring.size = init->ring_size; | |
2049 | dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); | |
2050 | ||
2051 | dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; | |
2052 | dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8); | |
2053 | ||
2054 | dev_priv->ring.fetch_size = /* init->fetch_size */ 32; | |
2055 | dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16); | |
2056 | ||
2057 | dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; | |
2058 | ||
2059 | dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; | |
2060 | ||
2061 | #if __OS_HAS_AGP | |
2062 | if (dev_priv->flags & RADEON_IS_AGP) { | |
2063 | /* XXX turn off pcie gart */ | |
2064 | } else | |
2065 | #endif | |
2066 | { | |
2067 | dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); | |
2068 | /* if we have an offset set from userspace */ | |
2069 | if (!dev_priv->pcigart_offset_set) { | |
2070 | DRM_ERROR("Need gart offset from userspace\n"); | |
2071 | r600_do_cleanup_cp(dev); | |
2072 | return -EINVAL; | |
2073 | } | |
2074 | ||
2075 | DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset); | |
2076 | ||
2077 | dev_priv->gart_info.bus_addr = | |
2078 | dev_priv->pcigart_offset + dev_priv->fb_location; | |
2079 | dev_priv->gart_info.mapping.offset = | |
2080 | dev_priv->pcigart_offset + dev_priv->fb_aper_offset; | |
2081 | dev_priv->gart_info.mapping.size = | |
2082 | dev_priv->gart_info.table_size; | |
2083 | ||
2084 | drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev); | |
2085 | if (!dev_priv->gart_info.mapping.handle) { | |
2086 | DRM_ERROR("ioremap failed.\n"); | |
2087 | r600_do_cleanup_cp(dev); | |
2088 | return -EINVAL; | |
2089 | } | |
2090 | ||
2091 | dev_priv->gart_info.addr = | |
2092 | dev_priv->gart_info.mapping.handle; | |
2093 | ||
2094 | DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", | |
2095 | dev_priv->gart_info.addr, | |
2096 | dev_priv->pcigart_offset); | |
2097 | ||
2098 | if (r600_page_table_init(dev)) { | |
2099 | DRM_ERROR("Failed to init GART table\n"); | |
2100 | r600_do_cleanup_cp(dev); | |
2101 | return -EINVAL; | |
2102 | } | |
2103 | ||
2104 | if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) | |
2105 | r700_vm_init(dev); | |
2106 | else | |
2107 | r600_vm_init(dev); | |
2108 | } | |
2109 | ||
2110 | if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) | |
2111 | r700_cp_load_microcode(dev_priv); | |
2112 | else | |
2113 | r600_cp_load_microcode(dev_priv); | |
2114 | ||
2115 | r600_cp_init_ring_buffer(dev, dev_priv, file_priv); | |
2116 | ||
2117 | dev_priv->last_buf = 0; | |
2118 | ||
2119 | r600_do_engine_reset(dev); | |
2120 | r600_test_writeback(dev_priv); | |
2121 | ||
2122 | return 0; | |
2123 | } | |
2124 | ||
2125 | int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv) | |
2126 | { | |
2127 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
2128 | ||
2129 | DRM_DEBUG("\n"); | |
2130 | if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) { | |
2131 | r700_vm_init(dev); | |
2132 | r700_cp_load_microcode(dev_priv); | |
2133 | } else { | |
2134 | r600_vm_init(dev); | |
2135 | r600_cp_load_microcode(dev_priv); | |
2136 | } | |
2137 | r600_cp_init_ring_buffer(dev, dev_priv, file_priv); | |
2138 | r600_do_engine_reset(dev); | |
2139 | ||
2140 | return 0; | |
2141 | } | |
2142 | ||
2143 | /* Wait for the CP to go idle. | |
2144 | */ | |
2145 | int r600_do_cp_idle(drm_radeon_private_t *dev_priv) | |
2146 | { | |
2147 | RING_LOCALS; | |
2148 | DRM_DEBUG("\n"); | |
2149 | ||
2150 | BEGIN_RING(5); | |
2151 | OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); | |
2152 | OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); | |
2153 | /* wait for 3D idle clean */ | |
2154 | OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); | |
2155 | OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2); | |
2156 | OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN); | |
2157 | ||
2158 | ADVANCE_RING(); | |
2159 | COMMIT_RING(); | |
2160 | ||
2161 | return r600_do_wait_for_idle(dev_priv); | |
2162 | } | |
2163 | ||
2164 | /* Start the Command Processor. | |
2165 | */ | |
2166 | void r600_do_cp_start(drm_radeon_private_t *dev_priv) | |
2167 | { | |
2168 | u32 cp_me; | |
2169 | RING_LOCALS; | |
2170 | DRM_DEBUG("\n"); | |
2171 | ||
2172 | BEGIN_RING(7); | |
2173 | OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5)); | |
2174 | OUT_RING(0x00000001); | |
2175 | if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) | |
2176 | OUT_RING(0x00000003); | |
2177 | else | |
2178 | OUT_RING(0x00000000); | |
2179 | OUT_RING((dev_priv->r600_max_hw_contexts - 1)); | |
2180 | OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1)); | |
2181 | OUT_RING(0x00000000); | |
2182 | OUT_RING(0x00000000); | |
2183 | ADVANCE_RING(); | |
2184 | COMMIT_RING(); | |
2185 | ||
2186 | /* set the mux and reset the halt bit */ | |
2187 | cp_me = 0xff; | |
2188 | RADEON_WRITE(R600_CP_ME_CNTL, cp_me); | |
2189 | ||
2190 | dev_priv->cp_running = 1; | |
2191 | ||
2192 | } | |
2193 | ||
2194 | void r600_do_cp_reset(drm_radeon_private_t *dev_priv) | |
2195 | { | |
2196 | u32 cur_read_ptr; | |
2197 | DRM_DEBUG("\n"); | |
2198 | ||
2199 | cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR); | |
2200 | RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr); | |
2201 | SET_RING_HEAD(dev_priv, cur_read_ptr); | |
2202 | dev_priv->ring.tail = cur_read_ptr; | |
2203 | } | |
2204 | ||
2205 | void r600_do_cp_stop(drm_radeon_private_t *dev_priv) | |
2206 | { | |
2207 | uint32_t cp_me; | |
2208 | ||
2209 | DRM_DEBUG("\n"); | |
2210 | ||
2211 | cp_me = 0xff | R600_CP_ME_HALT; | |
2212 | ||
2213 | RADEON_WRITE(R600_CP_ME_CNTL, cp_me); | |
2214 | ||
2215 | dev_priv->cp_running = 0; | |
2216 | } | |
2217 | ||
2218 | int r600_cp_dispatch_indirect(struct drm_device *dev, | |
2219 | struct drm_buf *buf, int start, int end) | |
2220 | { | |
2221 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
2222 | RING_LOCALS; | |
2223 | ||
2224 | if (start != end) { | |
2225 | unsigned long offset = (dev_priv->gart_buffers_offset | |
2226 | + buf->offset + start); | |
2227 | int dwords = (end - start + 3) / sizeof(u32); | |
2228 | ||
2229 | DRM_DEBUG("dwords:%d\n", dwords); | |
2230 | DRM_DEBUG("offset 0x%lx\n", offset); | |
2231 | ||
2232 | ||
2233 | /* Indirect buffer data must be a multiple of 16 dwords. | |
2234 | * pad the data with a Type-2 CP packet. | |
2235 | */ | |
2236 | while (dwords & 0xf) { | |
2237 | u32 *data = (u32 *) | |
2238 | ((char *)dev->agp_buffer_map->handle | |
2239 | + buf->offset + start); | |
2240 | data[dwords++] = RADEON_CP_PACKET2; | |
2241 | } | |
2242 | ||
2243 | /* Fire off the indirect buffer */ | |
2244 | BEGIN_RING(4); | |
2245 | OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2)); | |
2246 | OUT_RING((offset & 0xfffffffc)); | |
2247 | OUT_RING((upper_32_bits(offset) & 0xff)); | |
2248 | OUT_RING(dwords); | |
2249 | ADVANCE_RING(); | |
2250 | } | |
2251 | ||
2252 | return 0; | |
2253 | } |