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radeon/kms: cleanup async dma packet checking
[deliverable/linux.git] / drivers / gpu / drm / radeon / r600_cp.c
CommitLineData
c05ce083
AD		 1/*
2 * Copyright 2008-2009 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Dave Airlie <airlied@redhat.com>
26 * Alex Deucher <alexander.deucher@amd.com>
27 */
28
e0cd3608
PG		 29#include <linux/module.h>
30
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/radeon_drm.h>
c05ce083
AD		 33#include "radeon_drv.h"
34
70967ab9
BH		 35#define PFP_UCODE_SIZE 576
36#define PM4_UCODE_SIZE 1792
37#define R700_PFP_UCODE_SIZE 848
38#define R700_PM4_UCODE_SIZE 1360
39
40/* Firmware Names */
41MODULE_FIRMWARE("radeon/R600_pfp.bin");
42MODULE_FIRMWARE("radeon/R600_me.bin");
43MODULE_FIRMWARE("radeon/RV610_pfp.bin");
44MODULE_FIRMWARE("radeon/RV610_me.bin");
45MODULE_FIRMWARE("radeon/RV630_pfp.bin");
46MODULE_FIRMWARE("radeon/RV630_me.bin");
47MODULE_FIRMWARE("radeon/RV620_pfp.bin");
48MODULE_FIRMWARE("radeon/RV620_me.bin");
49MODULE_FIRMWARE("radeon/RV635_pfp.bin");
50MODULE_FIRMWARE("radeon/RV635_me.bin");
51MODULE_FIRMWARE("radeon/RV670_pfp.bin");
52MODULE_FIRMWARE("radeon/RV670_me.bin");
53MODULE_FIRMWARE("radeon/RS780_pfp.bin");
54MODULE_FIRMWARE("radeon/RS780_me.bin");
55MODULE_FIRMWARE("radeon/RV770_pfp.bin");
56MODULE_FIRMWARE("radeon/RV770_me.bin");
57MODULE_FIRMWARE("radeon/RV730_pfp.bin");
58MODULE_FIRMWARE("radeon/RV730_me.bin");
59MODULE_FIRMWARE("radeon/RV710_pfp.bin");
60MODULE_FIRMWARE("radeon/RV710_me.bin");
c05ce083 61
3ce0a23d
JG		 62
63int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
64 unsigned family, u32 *ib, int *l);
65void r600_cs_legacy_init(void);
66
67
c05ce083
AD		 68# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
69# define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1))
70
71#define R600_PTE_VALID (1 << 0)
72#define R600_PTE_SYSTEM (1 << 1)
73#define R600_PTE_SNOOPED (1 << 2)
74#define R600_PTE_READABLE (1 << 5)
75#define R600_PTE_WRITEABLE (1 << 6)
76
77/* MAX values used for gfx init */
78#define R6XX_MAX_SH_GPRS 256
79#define R6XX_MAX_TEMP_GPRS 16
80#define R6XX_MAX_SH_THREADS 256
81#define R6XX_MAX_SH_STACK_ENTRIES 4096
82#define R6XX_MAX_BACKENDS 8
83#define R6XX_MAX_BACKENDS_MASK 0xff
84#define R6XX_MAX_SIMDS 8
85#define R6XX_MAX_SIMDS_MASK 0xff
86#define R6XX_MAX_PIPES 8
87#define R6XX_MAX_PIPES_MASK 0xff
88
89#define R7XX_MAX_SH_GPRS 256
90#define R7XX_MAX_TEMP_GPRS 16
91#define R7XX_MAX_SH_THREADS 256
92#define R7XX_MAX_SH_STACK_ENTRIES 4096
93#define R7XX_MAX_BACKENDS 8
94#define R7XX_MAX_BACKENDS_MASK 0xff
95#define R7XX_MAX_SIMDS 16
96#define R7XX_MAX_SIMDS_MASK 0xffff
97#define R7XX_MAX_PIPES 8
98#define R7XX_MAX_PIPES_MASK 0xff
99
100static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)
101{
102 int i;
103
104 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
105
106 for (i = 0; i < dev_priv->usec_timeout; i++) {
107 int slots;
108 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
109 slots = (RADEON_READ(R600_GRBM_STATUS)
110 & R700_CMDFIFO_AVAIL_MASK);
111 else
112 slots = (RADEON_READ(R600_GRBM_STATUS)
113 & R600_CMDFIFO_AVAIL_MASK);
114 if (slots >= entries)
115 return 0;
116 DRM_UDELAY(1);
117 }
118 DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
119 RADEON_READ(R600_GRBM_STATUS),
120 RADEON_READ(R600_GRBM_STATUS2));
121
122 return -EBUSY;
123}
124
125static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv)
126{
127 int i, ret;
128
129 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
130
131 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
132 ret = r600_do_wait_for_fifo(dev_priv, 8);
133 else
134 ret = r600_do_wait_for_fifo(dev_priv, 16);
135 if (ret)
136 return ret;
137 for (i = 0; i < dev_priv->usec_timeout; i++) {
138 if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE))
139 return 0;
140 DRM_UDELAY(1);
141 }
142 DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
143 RADEON_READ(R600_GRBM_STATUS),
144 RADEON_READ(R600_GRBM_STATUS2));
145
146 return -EBUSY;
147}
148
c1556f71 149void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
c05ce083
AD		 150{
151 struct drm_sg_mem *entry = dev->sg;
152 int max_pages;
153 int pages;
154 int i;
155
08932156
AD		 156 if (!entry)
157 return;
158
c05ce083 159 if (gart_info->bus_addr) {
06f0a488 160 max_pages = (gart_info->table_size / sizeof(u64));
c05ce083
AD		 161 pages = (entry->pages <= max_pages)
162 ? entry->pages : max_pages;
163
164 for (i = 0; i < pages; i++) {
165 if (!entry->busaddr[i])
166 break;
a763d7dc
DA		 167 pci_unmap_page(dev->pdev, entry->busaddr[i],
168 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
c05ce083
AD		 169 }
170 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
171 gart_info->bus_addr = 0;
172 }
173}
174
175/* R600 has page table setup */
176int r600_page_table_init(struct drm_device *dev)
177{
178 drm_radeon_private_t *dev_priv = dev->dev_private;
179 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
eb1d9195 180 struct drm_local_map *map = &gart_info->mapping;
c05ce083
AD		 181 struct drm_sg_mem *entry = dev->sg;
182 int ret = 0;
183 int i, j;
eb1d9195
DA		 184 int pages;
185 u64 page_base;
c05ce083 186 dma_addr_t entry_addr;
eb1d9195 187 int max_ati_pages, max_real_pages, gart_idx;
c05ce083
AD		 188
189 /* okay page table is available - lets rock */
eb1d9195
DA		 190 max_ati_pages = (gart_info->table_size / sizeof(u64));
191 max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE);
c05ce083 192
eb1d9195
DA		 193 pages = (entry->pages <= max_real_pages) ?
194 entry->pages : max_real_pages;
c05ce083 195
eb1d9195 196 memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u64));
c05ce083 197
eb1d9195 198 gart_idx = 0;
c05ce083 199 for (i = 0; i < pages; i++) {
a763d7dc
DA		 200 entry->busaddr[i] = pci_map_page(dev->pdev,
201 entry->pagelist[i], 0,
202 PAGE_SIZE,
203 PCI_DMA_BIDIRECTIONAL);
a30f6fb7 204 if (pci_dma_mapping_error(dev->pdev, entry->busaddr[i])) {
c05ce083
AD		 205 DRM_ERROR("unable to map PCIGART pages!\n");
206 r600_page_table_cleanup(dev, gart_info);
c05ce083
AD		 207 goto done;
208 }
209 entry_addr = entry->busaddr[i];
210 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
211 page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK;
212 page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
213 page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
214
eb1d9195
DA		 215 DRM_WRITE64(map, gart_idx * sizeof(u64), page_base);
216
217 gart_idx++;
c05ce083
AD		 218
219 if ((i % 128) == 0)
220 DRM_DEBUG("page entry %d: 0x%016llx\n",
221 i, (unsigned long long)page_base);
c05ce083
AD		 222 entry_addr += ATI_PCIGART_PAGE_SIZE;
223 }
224 }
41f13fe8 225 ret = 1;
c05ce083
AD		 226done:
227 return ret;
228}
229
230static void r600_vm_flush_gart_range(struct drm_device *dev)
231{
232 drm_radeon_private_t *dev_priv = dev->dev_private;
233 u32 resp, countdown = 1000;
234 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12);
235 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
236 RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2);
237
238 do {
239 resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE);
240 countdown--;
241 DRM_UDELAY(1);
242 } while (((resp & 0xf0) == 0) && countdown);
243}
244
245static void r600_vm_init(struct drm_device *dev)
246{
247 drm_radeon_private_t *dev_priv = dev->dev_private;
248 /* initialise the VM to use the page table we constructed up there */
249 u32 vm_c0, i;
250 u32 mc_rd_a;
251 u32 vm_l2_cntl, vm_l2_cntl3;
252 /* okay set up the PCIE aperture type thingo */
253 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
254 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
255 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
256
257 /* setup MC RD a */
258 mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS |
259 R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) |
260 R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY;
261
262 RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a);
263 RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a);
264
265 RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a);
266 RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a);
267
268 RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a);
269 RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a);
270
271 RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a);
272 RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a);
273
274 RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING);
275 RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/);
276
277 RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a);
278 RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a);
279
280 RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE);
281 RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a);
282
283 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
284 vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7);
285 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
286
287 RADEON_WRITE(R600_VM_L2_CNTL2, 0);
288 vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) |
289 R600_VM_L2_CNTL3_BANK_SELECT_1(1) |
290 R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2));
291 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
292
293 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
294
295 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
296
297 vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
298
299 /* disable all other contexts */
300 for (i = 1; i < 8; i++)
301 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
302
303 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
304 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
305 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
306
307 r600_vm_flush_gart_range(dev);
308}
309
70967ab9
BH		 310static int r600_cp_init_microcode(drm_radeon_private_t *dev_priv)
311{
312 struct platform_device *pdev;
313 const char *chip_name;
314 size_t pfp_req_size, me_req_size;
315 char fw_name[30];
316 int err;
317
318 pdev = platform_device_register_simple("r600_cp", 0, NULL, 0);
319 err = IS_ERR(pdev);
320 if (err) {
321 printk(KERN_ERR "r600_cp: Failed to register firmware\n");
322 return -EINVAL;
323 }
324
325 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
326 case CHIP_R600: chip_name = "R600"; break;
327 case CHIP_RV610: chip_name = "RV610"; break;
328 case CHIP_RV630: chip_name = "RV630"; break;
329 case CHIP_RV620: chip_name = "RV620"; break;
330 case CHIP_RV635: chip_name = "RV635"; break;
331 case CHIP_RV670: chip_name = "RV670"; break;
332 case CHIP_RS780:
333 case CHIP_RS880: chip_name = "RS780"; break;
334 case CHIP_RV770: chip_name = "RV770"; break;
335 case CHIP_RV730:
336 case CHIP_RV740: chip_name = "RV730"; break;
337 case CHIP_RV710: chip_name = "RV710"; break;
338 default: BUG();
339 }
340
341 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
342 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
343 me_req_size = R700_PM4_UCODE_SIZE * 4;
344 } else {
345 pfp_req_size = PFP_UCODE_SIZE * 4;
346 me_req_size = PM4_UCODE_SIZE * 12;
347 }
348
349 DRM_INFO("Loading %s CP Microcode\n", chip_name);
350
351 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
352 err = request_firmware(&dev_priv->pfp_fw, fw_name, &pdev->dev);
353 if (err)
354 goto out;
355 if (dev_priv->pfp_fw->size != pfp_req_size) {
356 printk(KERN_ERR
357 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
358 dev_priv->pfp_fw->size, fw_name);
359 err = -EINVAL;
360 goto out;
361 }
362
363 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
364 err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
365 if (err)
366 goto out;
367 if (dev_priv->me_fw->size != me_req_size) {
368 printk(KERN_ERR
369 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
370 dev_priv->me_fw->size, fw_name);
371 err = -EINVAL;
372 }
373out:
374 platform_device_unregister(pdev);
375
376 if (err) {
377 if (err != -EINVAL)
378 printk(KERN_ERR
379 "r600_cp: Failed to load firmware \"%s\"\n",
380 fw_name);
381 release_firmware(dev_priv->pfp_fw);
382 dev_priv->pfp_fw = NULL;
383 release_firmware(dev_priv->me_fw);
384 dev_priv->me_fw = NULL;
385 }
386 return err;
387}
388
c05ce083
AD		 389static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
390{
70967ab9 391 const __be32 *fw_data;
c05ce083
AD		 392 int i;
393
70967ab9
BH		 394 if (!dev_priv->me_fw || !dev_priv->pfp_fw)
395 return;
396
c05ce083
AD		 397 r600_do_cp_stop(dev_priv);
398
399 RADEON_WRITE(R600_CP_RB_CNTL,
dee54c40
CC		 400#ifdef __BIG_ENDIAN
401 R600_BUF_SWAP_32BIT |
402#endif
c05ce083
AD		 403 R600_RB_NO_UPDATE |
404 R600_RB_BLKSZ(15) |
405 R600_RB_BUFSZ(3));
406
407 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
408 RADEON_READ(R600_GRBM_SOFT_RESET);
4de833c3 409 mdelay(15);
c05ce083
AD		 410 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
411
70967ab9 412 fw_data = (const __be32 *)dev_priv->me_fw->data;
c05ce083 413 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
70967ab9
BH		 414 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
415 RADEON_WRITE(R600_CP_ME_RAM_DATA,
416 be32_to_cpup(fw_data++));
c05ce083 417
70967ab9
BH		 418 fw_data = (const __be32 *)dev_priv->pfp_fw->data;
419 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
420 for (i = 0; i < PFP_UCODE_SIZE; i++)
421 RADEON_WRITE(R600_CP_PFP_UCODE_DATA,
422 be32_to_cpup(fw_data++));
c05ce083 423
c05ce083
AD		 424 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
425 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
426 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
427
428}
429
430static void r700_vm_init(struct drm_device *dev)
431{
432 drm_radeon_private_t *dev_priv = dev->dev_private;
433 /* initialise the VM to use the page table we constructed up there */
434 u32 vm_c0, i;
435 u32 mc_vm_md_l1;
436 u32 vm_l2_cntl, vm_l2_cntl3;
437 /* okay set up the PCIE aperture type thingo */
438 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
439 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
440 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
441
442 mc_vm_md_l1 = R700_ENABLE_L1_TLB |
443 R700_ENABLE_L1_FRAGMENT_PROCESSING |
444 R700_SYSTEM_ACCESS_MODE_IN_SYS |
445 R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
446 R700_EFFECTIVE_L1_TLB_SIZE(5) |
447 R700_EFFECTIVE_L1_QUEUE_SIZE(5);
448
449 RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1);
450 RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1);
451 RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1);
452 RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1);
453 RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1);
454 RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1);
455 RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1);
456
457 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
458 vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7);
459 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
460
461 RADEON_WRITE(R600_VM_L2_CNTL2, 0);
462 vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2);
463 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
464
465 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
466
467 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
468
469 vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
470
471 /* disable all other contexts */
472 for (i = 1; i < 8; i++)
473 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
474
475 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
476 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
477 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
478
479 r600_vm_flush_gart_range(dev);
480}
481
c05ce083
AD		 482static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
483{
70967ab9 484 const __be32 *fw_data;
c05ce083
AD		 485 int i;
486
70967ab9
BH		 487 if (!dev_priv->me_fw || !dev_priv->pfp_fw)
488 return;
489
c05ce083
AD		 490 r600_do_cp_stop(dev_priv);
491
492 RADEON_WRITE(R600_CP_RB_CNTL,
dee54c40
CC		 493#ifdef __BIG_ENDIAN
494 R600_BUF_SWAP_32BIT |
495#endif
c05ce083 496 R600_RB_NO_UPDATE |
dee54c40
CC		 497 R600_RB_BLKSZ(15) |
498 R600_RB_BUFSZ(3));
c05ce083
AD		 499
500 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
501 RADEON_READ(R600_GRBM_SOFT_RESET);
4de833c3 502 mdelay(15);
c05ce083
AD		 503 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
504
70967ab9
BH		 505 fw_data = (const __be32 *)dev_priv->pfp_fw->data;
506 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
507 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
508 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
509 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
c05ce083 510
70967ab9
BH		 511 fw_data = (const __be32 *)dev_priv->me_fw->data;
512 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
513 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
514 RADEON_WRITE(R600_CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
515 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
c05ce083 516
c05ce083
AD		 517 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
518 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
519 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
520
521}
522
523static void r600_test_writeback(drm_radeon_private_t *dev_priv)
524{
525 u32 tmp;
526
527 /* Start with assuming that writeback doesn't work */
528 dev_priv->writeback_works = 0;
529
530 /* Writeback doesn't seem to work everywhere, test it here and possibly
531 * enable it if it appears to work
532 */
533 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
534
535 RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef);
536
537 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
538 u32 val;
539
540 val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1));
541 if (val == 0xdeadbeef)
542 break;
543 DRM_UDELAY(1);
544 }
545
546 if (tmp < dev_priv->usec_timeout) {
547 dev_priv->writeback_works = 1;
548 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
549 } else {
550 dev_priv->writeback_works = 0;
551 DRM_INFO("writeback test failed\n");
552 }
553 if (radeon_no_wb == 1) {
554 dev_priv->writeback_works = 0;
555 DRM_INFO("writeback forced off\n");
556 }
557
558 if (!dev_priv->writeback_works) {
559 /* Disable writeback to avoid unnecessary bus master transfer */
dee54c40
CC		 560 RADEON_WRITE(R600_CP_RB_CNTL,
561#ifdef __BIG_ENDIAN
562 R600_BUF_SWAP_32BIT |
563#endif
564 RADEON_READ(R600_CP_RB_CNTL) |
565 R600_RB_NO_UPDATE);
c05ce083
AD		 566 RADEON_WRITE(R600_SCRATCH_UMSK, 0);
567 }
568}
569
570int r600_do_engine_reset(struct drm_device *dev)
571{
572 drm_radeon_private_t *dev_priv = dev->dev_private;
573 u32 cp_ptr, cp_me_cntl, cp_rb_cntl;
574
575 DRM_INFO("Resetting GPU\n");
576
577 cp_ptr = RADEON_READ(R600_CP_RB_WPTR);
578 cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL);
579 RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT);
580
581 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff);
582 RADEON_READ(R600_GRBM_SOFT_RESET);
583 DRM_UDELAY(50);
584 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
585 RADEON_READ(R600_GRBM_SOFT_RESET);
586
587 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
588 cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL);
dee54c40
CC		 589 RADEON_WRITE(R600_CP_RB_CNTL,
590#ifdef __BIG_ENDIAN
591 R600_BUF_SWAP_32BIT |
592#endif
593 R600_RB_RPTR_WR_ENA);
c05ce083
AD		 594
595 RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr);
596 RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr);
597 RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl);
598 RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl);
599
600 /* Reset the CP ring */
601 r600_do_cp_reset(dev_priv);
602
603 /* The CP is no longer running after an engine reset */
604 dev_priv->cp_running = 0;
605
606 /* Reset any pending vertex, indirect buffers */
607 radeon_freelist_reset(dev);
608
609 return 0;
610
611}
612
613static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
614 u32 num_backends,
615 u32 backend_disable_mask)
616{
617 u32 backend_map = 0;
618 u32 enabled_backends_mask;
619 u32 enabled_backends_count;
620 u32 cur_pipe;
621 u32 swizzle_pipe[R6XX_MAX_PIPES];
622 u32 cur_backend;
623 u32 i;
624
625 if (num_tile_pipes > R6XX_MAX_PIPES)
626 num_tile_pipes = R6XX_MAX_PIPES;
627 if (num_tile_pipes < 1)
628 num_tile_pipes = 1;
629 if (num_backends > R6XX_MAX_BACKENDS)
630 num_backends = R6XX_MAX_BACKENDS;
631 if (num_backends < 1)
632 num_backends = 1;
633
634 enabled_backends_mask = 0;
635 enabled_backends_count = 0;
636 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
637 if (((backend_disable_mask >> i) & 1) == 0) {
638 enabled_backends_mask |= (1 << i);
639 ++enabled_backends_count;
640 }
641 if (enabled_backends_count == num_backends)
642 break;
643 }
644
645 if (enabled_backends_count == 0) {
646 enabled_backends_mask = 1;
647 enabled_backends_count = 1;
648 }
649
650 if (enabled_backends_count != num_backends)
651 num_backends = enabled_backends_count;
652
653 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
654 switch (num_tile_pipes) {
655 case 1:
656 swizzle_pipe[0] = 0;
657 break;
658 case 2:
659 swizzle_pipe[0] = 0;
660 swizzle_pipe[1] = 1;
661 break;
662 case 3:
663 swizzle_pipe[0] = 0;
664 swizzle_pipe[1] = 1;
665 swizzle_pipe[2] = 2;
666 break;
667 case 4:
668 swizzle_pipe[0] = 0;
669 swizzle_pipe[1] = 1;
670 swizzle_pipe[2] = 2;
671 swizzle_pipe[3] = 3;
672 break;
673 case 5:
674 swizzle_pipe[0] = 0;
675 swizzle_pipe[1] = 1;
676 swizzle_pipe[2] = 2;
677 swizzle_pipe[3] = 3;
678 swizzle_pipe[4] = 4;
679 break;
680 case 6:
681 swizzle_pipe[0] = 0;
682 swizzle_pipe[1] = 2;
683 swizzle_pipe[2] = 4;
684 swizzle_pipe[3] = 5;
685 swizzle_pipe[4] = 1;
686 swizzle_pipe[5] = 3;
687 break;
688 case 7:
689 swizzle_pipe[0] = 0;
690 swizzle_pipe[1] = 2;
691 swizzle_pipe[2] = 4;
692 swizzle_pipe[3] = 6;
693 swizzle_pipe[4] = 1;
694 swizzle_pipe[5] = 3;
695 swizzle_pipe[6] = 5;
696 break;
697 case 8:
698 swizzle_pipe[0] = 0;
699 swizzle_pipe[1] = 2;
700 swizzle_pipe[2] = 4;
701 swizzle_pipe[3] = 6;
702 swizzle_pipe[4] = 1;
703 swizzle_pipe[5] = 3;
704 swizzle_pipe[6] = 5;
705 swizzle_pipe[7] = 7;
706 break;
707 }
708
709 cur_backend = 0;
710 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
711 while (((1 << cur_backend) & enabled_backends_mask) == 0)
712 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
713
714 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
715
716 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
717 }
718
719 return backend_map;
720}
721
722static int r600_count_pipe_bits(uint32_t val)
723{
ef8cf3a1 724 return hweight32(val);
c05ce083
AD		 725}
726
727static void r600_gfx_init(struct drm_device *dev,
728 drm_radeon_private_t *dev_priv)
729{
730 int i, j, num_qd_pipes;
731 u32 sx_debug_1;
732 u32 tc_cntl;
733 u32 arb_pop;
734 u32 num_gs_verts_per_thread;
735 u32 vgt_gs_per_es;
736 u32 gs_prim_buffer_depth = 0;
737 u32 sq_ms_fifo_sizes;
738 u32 sq_config;
739 u32 sq_gpr_resource_mgmt_1 = 0;
740 u32 sq_gpr_resource_mgmt_2 = 0;
741 u32 sq_thread_resource_mgmt = 0;
742 u32 sq_stack_resource_mgmt_1 = 0;
743 u32 sq_stack_resource_mgmt_2 = 0;
744 u32 hdp_host_path_cntl;
745 u32 backend_map;
746 u32 gb_tiling_config = 0;
d03f5d59
AD		 747 u32 cc_rb_backend_disable;
748 u32 cc_gc_shader_pipe_config;
c05ce083
AD		 749 u32 ramcfg;
750
751 /* setup chip specs */
752 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
753 case CHIP_R600:
754 dev_priv->r600_max_pipes = 4;
755 dev_priv->r600_max_tile_pipes = 8;
756 dev_priv->r600_max_simds = 4;
757 dev_priv->r600_max_backends = 4;
758 dev_priv->r600_max_gprs = 256;
759 dev_priv->r600_max_threads = 192;
760 dev_priv->r600_max_stack_entries = 256;
761 dev_priv->r600_max_hw_contexts = 8;
762 dev_priv->r600_max_gs_threads = 16;
763 dev_priv->r600_sx_max_export_size = 128;
764 dev_priv->r600_sx_max_export_pos_size = 16;
765 dev_priv->r600_sx_max_export_smx_size = 128;
766 dev_priv->r600_sq_num_cf_insts = 2;
767 break;
768 case CHIP_RV630:
769 case CHIP_RV635:
770 dev_priv->r600_max_pipes = 2;
771 dev_priv->r600_max_tile_pipes = 2;
772 dev_priv->r600_max_simds = 3;
773 dev_priv->r600_max_backends = 1;
774 dev_priv->r600_max_gprs = 128;
775 dev_priv->r600_max_threads = 192;
776 dev_priv->r600_max_stack_entries = 128;
777 dev_priv->r600_max_hw_contexts = 8;
778 dev_priv->r600_max_gs_threads = 4;
779 dev_priv->r600_sx_max_export_size = 128;
780 dev_priv->r600_sx_max_export_pos_size = 16;
781 dev_priv->r600_sx_max_export_smx_size = 128;
782 dev_priv->r600_sq_num_cf_insts = 2;
783 break;
784 case CHIP_RV610:
785 case CHIP_RS780:
6502fbfa 786 case CHIP_RS880:
c05ce083
AD		 787 case CHIP_RV620:
788 dev_priv->r600_max_pipes = 1;
789 dev_priv->r600_max_tile_pipes = 1;
790 dev_priv->r600_max_simds = 2;
791 dev_priv->r600_max_backends = 1;
792 dev_priv->r600_max_gprs = 128;
793 dev_priv->r600_max_threads = 192;
794 dev_priv->r600_max_stack_entries = 128;
795 dev_priv->r600_max_hw_contexts = 4;
796 dev_priv->r600_max_gs_threads = 4;
797 dev_priv->r600_sx_max_export_size = 128;
798 dev_priv->r600_sx_max_export_pos_size = 16;
799 dev_priv->r600_sx_max_export_smx_size = 128;
800 dev_priv->r600_sq_num_cf_insts = 1;
801 break;
802 case CHIP_RV670:
803 dev_priv->r600_max_pipes = 4;
804 dev_priv->r600_max_tile_pipes = 4;
805 dev_priv->r600_max_simds = 4;
806 dev_priv->r600_max_backends = 4;
807 dev_priv->r600_max_gprs = 192;
808 dev_priv->r600_max_threads = 192;
809 dev_priv->r600_max_stack_entries = 256;
810 dev_priv->r600_max_hw_contexts = 8;
811 dev_priv->r600_max_gs_threads = 16;
812 dev_priv->r600_sx_max_export_size = 128;
813 dev_priv->r600_sx_max_export_pos_size = 16;
814 dev_priv->r600_sx_max_export_smx_size = 128;
815 dev_priv->r600_sq_num_cf_insts = 2;
816 break;
817 default:
818 break;
819 }
820
821 /* Initialize HDP */
822 j = 0;
823 for (i = 0; i < 32; i++) {
824 RADEON_WRITE((0x2c14 + j), 0x00000000);
825 RADEON_WRITE((0x2c18 + j), 0x00000000);
826 RADEON_WRITE((0x2c1c + j), 0x00000000);
827 RADEON_WRITE((0x2c20 + j), 0x00000000);
828 RADEON_WRITE((0x2c24 + j), 0x00000000);
829 j += 0x18;
830 }
831
832 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
833
834 /* setup tiling, simd, pipe config */
835 ramcfg = RADEON_READ(R600_RAMCFG);
836
837 switch (dev_priv->r600_max_tile_pipes) {
838 case 1:
839 gb_tiling_config |= R600_PIPE_TILING(0);
840 break;
841 case 2:
842 gb_tiling_config |= R600_PIPE_TILING(1);
843 break;
844 case 4:
845 gb_tiling_config |= R600_PIPE_TILING(2);
846 break;
847 case 8:
848 gb_tiling_config |= R600_PIPE_TILING(3);
849 break;
850 default:
851 break;
852 }
853
854 gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK);
855
856 gb_tiling_config |= R600_GROUP_SIZE(0);
857
858 if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) {
859 gb_tiling_config |= R600_ROW_TILING(3);
860 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
861 } else {
862 gb_tiling_config |=
863 R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
864 gb_tiling_config |=
865 R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
866 }
867
868 gb_tiling_config |= R600_BANK_SWAPS(1);
869
d03f5d59
AD		 870 cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000;
871 cc_rb_backend_disable |=
872 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK);
c05ce083 873
d03f5d59
AD		 874 cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
875 cc_gc_shader_pipe_config |=
c05ce083
AD		 876 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK);
877 cc_gc_shader_pipe_config |=
878 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK);
879
d03f5d59
AD		 880 backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
881 (R6XX_MAX_BACKENDS -
882 r600_count_pipe_bits((cc_rb_backend_disable &
883 R6XX_MAX_BACKENDS_MASK) >> 16)),
884 (cc_rb_backend_disable >> 16));
885 gb_tiling_config |= R600_BACKEND_MAP(backend_map);
c05ce083
AD		 886
887 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config);
888 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
889 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
961fb597
JG		 890 if (gb_tiling_config & 0xc0) {
891 dev_priv->r600_group_size = 512;
892 } else {
893 dev_priv->r600_group_size = 256;
894 }
895 dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7);
896 if (gb_tiling_config & 0x30) {
897 dev_priv->r600_nbanks = 8;
898 } else {
899 dev_priv->r600_nbanks = 4;
900 }
c05ce083
AD		 901
902 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
903 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
904 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
905
906 num_qd_pipes =
d03f5d59 907 R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8);
c05ce083
AD		 908 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
909 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
910
911 /* set HW defaults for 3D engine */
912 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
913 R600_ROQ_IB2_START(0x2b)));
914
915 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) |
916 R600_ROQ_END(0x40)));
917
918 RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
919 R600_SYNC_GRADIENT |
920 R600_SYNC_WALKER |
921 R600_SYNC_ALIGNER));
922
923 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)
924 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021);
925
926 sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1);
927 sx_debug_1 |= R600_SMX_EVENT_RELEASE;
928 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600))
929 sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS;
930 RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1);
931
932 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
933 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
934 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
935 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
6502fbfa
AD		 936 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
937 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
c05ce083
AD		 938 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE);
939 else
940 RADEON_WRITE(R600_DB_DEBUG, 0);
941
942 RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) |
943 R600_DEPTH_FLUSH(16) |
944 R600_DEPTH_PENDING_FREE(4) |
945 R600_DEPTH_CACHELINE_FREE(16)));
946 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
947 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0);
948
949 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
950 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0));
951
952 sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);
953 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
954 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
6502fbfa
AD		 955 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
956 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
c05ce083
AD		 957 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) |
958 R600_FETCH_FIFO_HIWATER(0xa) |
959 R600_DONE_FIFO_HIWATER(0xe0) |
960 R600_ALU_UPDATE_FIFO_HIWATER(0x8));
961 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
962 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
963 sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff);
964 sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4);
965 }
966 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
967
968 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
969 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
970 */
971 sq_config = RADEON_READ(R600_SQ_CONFIG);
972 sq_config &= ~(R600_PS_PRIO(3) |
973 R600_VS_PRIO(3) |
974 R600_GS_PRIO(3) |
975 R600_ES_PRIO(3));
976 sq_config |= (R600_DX9_CONSTS |
977 R600_VC_ENABLE |
978 R600_PS_PRIO(0) |
979 R600_VS_PRIO(1) |
980 R600_GS_PRIO(2) |
981 R600_ES_PRIO(3));
982
983 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) {
984 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) |
985 R600_NUM_VS_GPRS(124) |
986 R600_NUM_CLAUSE_TEMP_GPRS(4));
987 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) |
988 R600_NUM_ES_GPRS(0));
989 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) |
990 R600_NUM_VS_THREADS(48) |
991 R600_NUM_GS_THREADS(4) |
992 R600_NUM_ES_THREADS(4));
993 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) |
994 R600_NUM_VS_STACK_ENTRIES(128));
995 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) |
996 R600_NUM_ES_STACK_ENTRIES(0));
997 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
998 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
6502fbfa
AD		 999 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
1000 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
c05ce083
AD		 1001 /* no vertex cache */
1002 sq_config &= ~R600_VC_ENABLE;
1003
1004 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1005 R600_NUM_VS_GPRS(44) |
1006 R600_NUM_CLAUSE_TEMP_GPRS(2));
1007 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
1008 R600_NUM_ES_GPRS(17));
1009 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
1010 R600_NUM_VS_THREADS(78) |
1011 R600_NUM_GS_THREADS(4) |
1012 R600_NUM_ES_THREADS(31));
1013 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
1014 R600_NUM_VS_STACK_ENTRIES(40));
1015 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
1016 R600_NUM_ES_STACK_ENTRIES(16));
1017 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
1018 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
1019 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1020 R600_NUM_VS_GPRS(44) |
1021 R600_NUM_CLAUSE_TEMP_GPRS(2));
1022 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) |
1023 R600_NUM_ES_GPRS(18));
1024 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
1025 R600_NUM_VS_THREADS(78) |
1026 R600_NUM_GS_THREADS(4) |
1027 R600_NUM_ES_THREADS(31));
1028 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
1029 R600_NUM_VS_STACK_ENTRIES(40));
1030 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
1031 R600_NUM_ES_STACK_ENTRIES(16));
1032 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) {
1033 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1034 R600_NUM_VS_GPRS(44) |
1035 R600_NUM_CLAUSE_TEMP_GPRS(2));
1036 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
1037 R600_NUM_ES_GPRS(17));
1038 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
1039 R600_NUM_VS_THREADS(78) |
1040 R600_NUM_GS_THREADS(4) |
1041 R600_NUM_ES_THREADS(31));
1042 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) |
1043 R600_NUM_VS_STACK_ENTRIES(64));
1044 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) |
1045 R600_NUM_ES_STACK_ENTRIES(64));
1046 }
1047
1048 RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1049 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1050 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1051 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1052 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1053 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1054
1055 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
1056 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
6502fbfa
AD		 1057 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
1058 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
c05ce083
AD		 1059 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY));
1060 else
1061 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC));
1062
1063 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) |
1064 R600_S0_Y(0x4) |
1065 R600_S1_X(0x4) |
1066 R600_S1_Y(0xc)));
1067 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) |
1068 R600_S0_Y(0xe) |
1069 R600_S1_X(0x2) |
1070 R600_S1_Y(0x2) |
1071 R600_S2_X(0xa) |
1072 R600_S2_Y(0x6) |
1073 R600_S3_X(0x6) |
1074 R600_S3_Y(0xa)));
1075 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) |
1076 R600_S0_Y(0xb) |
1077 R600_S1_X(0x4) |
1078 R600_S1_Y(0xc) |
1079 R600_S2_X(0x1) |
1080 R600_S2_Y(0x6) |
1081 R600_S3_X(0xa) |
1082 R600_S3_Y(0xe)));
1083 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) |
1084 R600_S4_Y(0x1) |
1085 R600_S5_X(0x0) |
1086 R600_S5_Y(0x0) |
1087 R600_S6_X(0xb) |
1088 R600_S6_Y(0x4) |
1089 R600_S7_X(0x7) |
1090 R600_S7_Y(0x8)));
1091
1092
1093 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1094 case CHIP_R600:
1095 case CHIP_RV630:
1096 case CHIP_RV635:
1097 gs_prim_buffer_depth = 0;
1098 break;
1099 case CHIP_RV610:
1100 case CHIP_RS780:
6502fbfa 1101 case CHIP_RS880:
c05ce083
AD		 1102 case CHIP_RV620:
1103 gs_prim_buffer_depth = 32;
1104 break;
1105 case CHIP_RV670:
1106 gs_prim_buffer_depth = 128;
1107 break;
1108 default:
1109 break;
1110 }
1111
1112 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1113 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1114 /* Max value for this is 256 */
1115 if (vgt_gs_per_es > 256)
1116 vgt_gs_per_es = 256;
1117
1118 RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1119 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1120 RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1121 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1122
1123 /* more default values. 2D/3D driver should adjust as needed */
1124 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1125 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1126 RADEON_WRITE(R600_SX_MISC, 0);
1127 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1128 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1129 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1130 RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1131 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1132 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1133
1134 /* clear render buffer base addresses */
1135 RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1136 RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1137 RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1138 RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1139 RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1140 RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1141 RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1142 RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1143
1144 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1145 case CHIP_RV610:
1146 case CHIP_RS780:
6502fbfa 1147 case CHIP_RS880:
c05ce083
AD		 1148 case CHIP_RV620:
1149 tc_cntl = R600_TC_L2_SIZE(8);
1150 break;
1151 case CHIP_RV630:
1152 case CHIP_RV635:
1153 tc_cntl = R600_TC_L2_SIZE(4);
1154 break;
1155 case CHIP_R600:
1156 tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT;
1157 break;
1158 default:
1159 tc_cntl = R600_TC_L2_SIZE(0);
1160 break;
1161 }
1162
1163 RADEON_WRITE(R600_TC_CNTL, tc_cntl);
1164
1165 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1166 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1167
1168 arb_pop = RADEON_READ(R600_ARB_POP);
1169 arb_pop |= R600_ENABLE_TC128;
1170 RADEON_WRITE(R600_ARB_POP, arb_pop);
1171
1172 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1173 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1174 R600_NUM_CLIP_SEQ(3)));
1175 RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095));
1176
1177}
1178
d03f5d59
AD		 1179static u32 r700_get_tile_pipe_to_backend_map(drm_radeon_private_t *dev_priv,
1180 u32 num_tile_pipes,
c05ce083
AD		 1181 u32 num_backends,
1182 u32 backend_disable_mask)
1183{
1184 u32 backend_map = 0;
1185 u32 enabled_backends_mask;
1186 u32 enabled_backends_count;
1187 u32 cur_pipe;
1188 u32 swizzle_pipe[R7XX_MAX_PIPES];
1189 u32 cur_backend;
1190 u32 i;
d03f5d59 1191 bool force_no_swizzle;
c05ce083
AD		 1192
1193 if (num_tile_pipes > R7XX_MAX_PIPES)
1194 num_tile_pipes = R7XX_MAX_PIPES;
1195 if (num_tile_pipes < 1)
1196 num_tile_pipes = 1;
1197 if (num_backends > R7XX_MAX_BACKENDS)
1198 num_backends = R7XX_MAX_BACKENDS;
1199 if (num_backends < 1)
1200 num_backends = 1;
1201
1202 enabled_backends_mask = 0;
1203 enabled_backends_count = 0;
1204 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
1205 if (((backend_disable_mask >> i) & 1) == 0) {
1206 enabled_backends_mask |= (1 << i);
1207 ++enabled_backends_count;
1208 }
1209 if (enabled_backends_count == num_backends)
1210 break;
1211 }
1212
1213 if (enabled_backends_count == 0) {
1214 enabled_backends_mask = 1;
1215 enabled_backends_count = 1;
1216 }
1217
1218 if (enabled_backends_count != num_backends)
1219 num_backends = enabled_backends_count;
1220
d03f5d59
AD		 1221 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1222 case CHIP_RV770:
1223 case CHIP_RV730:
1224 force_no_swizzle = false;
1225 break;
1226 case CHIP_RV710:
1227 case CHIP_RV740:
1228 default:
1229 force_no_swizzle = true;
1230 break;
1231 }
1232
c05ce083
AD		 1233 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
1234 switch (num_tile_pipes) {
1235 case 1:
1236 swizzle_pipe[0] = 0;
1237 break;
1238 case 2:
1239 swizzle_pipe[0] = 0;
1240 swizzle_pipe[1] = 1;
1241 break;
1242 case 3:
d03f5d59
AD		 1243 if (force_no_swizzle) {
1244 swizzle_pipe[0] = 0;
1245 swizzle_pipe[1] = 1;
1246 swizzle_pipe[2] = 2;
1247 } else {
1248 swizzle_pipe[0] = 0;
1249 swizzle_pipe[1] = 2;
1250 swizzle_pipe[2] = 1;
1251 }
c05ce083
AD		 1252 break;
1253 case 4:
d03f5d59
AD		 1254 if (force_no_swizzle) {
1255 swizzle_pipe[0] = 0;
1256 swizzle_pipe[1] = 1;
1257 swizzle_pipe[2] = 2;
1258 swizzle_pipe[3] = 3;
1259 } else {
1260 swizzle_pipe[0] = 0;
1261 swizzle_pipe[1] = 2;
1262 swizzle_pipe[2] = 3;
1263 swizzle_pipe[3] = 1;
1264 }
c05ce083
AD		 1265 break;
1266 case 5:
d03f5d59
AD		 1267 if (force_no_swizzle) {
1268 swizzle_pipe[0] = 0;
1269 swizzle_pipe[1] = 1;
1270 swizzle_pipe[2] = 2;
1271 swizzle_pipe[3] = 3;
1272 swizzle_pipe[4] = 4;
1273 } else {
1274 swizzle_pipe[0] = 0;
1275 swizzle_pipe[1] = 2;
1276 swizzle_pipe[2] = 4;
1277 swizzle_pipe[3] = 1;
1278 swizzle_pipe[4] = 3;
1279 }
c05ce083
AD		 1280 break;
1281 case 6:
d03f5d59
AD		 1282 if (force_no_swizzle) {
1283 swizzle_pipe[0] = 0;
1284 swizzle_pipe[1] = 1;
1285 swizzle_pipe[2] = 2;
1286 swizzle_pipe[3] = 3;
1287 swizzle_pipe[4] = 4;
1288 swizzle_pipe[5] = 5;
1289 } else {
1290 swizzle_pipe[0] = 0;
1291 swizzle_pipe[1] = 2;
1292 swizzle_pipe[2] = 4;
1293 swizzle_pipe[3] = 5;
1294 swizzle_pipe[4] = 3;
1295 swizzle_pipe[5] = 1;
1296 }
c05ce083
AD		 1297 break;
1298 case 7:
d03f5d59
AD		 1299 if (force_no_swizzle) {
1300 swizzle_pipe[0] = 0;
1301 swizzle_pipe[1] = 1;
1302 swizzle_pipe[2] = 2;
1303 swizzle_pipe[3] = 3;
1304 swizzle_pipe[4] = 4;
1305 swizzle_pipe[5] = 5;
1306 swizzle_pipe[6] = 6;
1307 } else {
1308 swizzle_pipe[0] = 0;
1309 swizzle_pipe[1] = 2;
1310 swizzle_pipe[2] = 4;
1311 swizzle_pipe[3] = 6;
1312 swizzle_pipe[4] = 3;
1313 swizzle_pipe[5] = 1;
1314 swizzle_pipe[6] = 5;
1315 }
c05ce083
AD		 1316 break;
1317 case 8:
d03f5d59
AD		 1318 if (force_no_swizzle) {
1319 swizzle_pipe[0] = 0;
1320 swizzle_pipe[1] = 1;
1321 swizzle_pipe[2] = 2;
1322 swizzle_pipe[3] = 3;
1323 swizzle_pipe[4] = 4;
1324 swizzle_pipe[5] = 5;
1325 swizzle_pipe[6] = 6;
1326 swizzle_pipe[7] = 7;
1327 } else {
1328 swizzle_pipe[0] = 0;
1329 swizzle_pipe[1] = 2;
1330 swizzle_pipe[2] = 4;
1331 swizzle_pipe[3] = 6;
1332 swizzle_pipe[4] = 3;
1333 swizzle_pipe[5] = 1;
1334 swizzle_pipe[6] = 7;
1335 swizzle_pipe[7] = 5;
1336 }
c05ce083
AD		 1337 break;
1338 }
1339
1340 cur_backend = 0;
1341 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1342 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1343 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1344
1345 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1346
1347 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1348 }
1349
1350 return backend_map;
1351}
1352
1353static void r700_gfx_init(struct drm_device *dev,
1354 drm_radeon_private_t *dev_priv)
1355{
1356 int i, j, num_qd_pipes;
d03f5d59 1357 u32 ta_aux_cntl;
c05ce083
AD		 1358 u32 sx_debug_1;
1359 u32 smx_dc_ctl0;
d03f5d59 1360 u32 db_debug3;
c05ce083
AD		 1361 u32 num_gs_verts_per_thread;
1362 u32 vgt_gs_per_es;
1363 u32 gs_prim_buffer_depth = 0;
1364 u32 sq_ms_fifo_sizes;
1365 u32 sq_config;
1366 u32 sq_thread_resource_mgmt;
1367 u32 hdp_host_path_cntl;
1368 u32 sq_dyn_gpr_size_simd_ab_0;
1369 u32 backend_map;
1370 u32 gb_tiling_config = 0;
d03f5d59
AD		 1371 u32 cc_rb_backend_disable;
1372 u32 cc_gc_shader_pipe_config;
c05ce083
AD		 1373 u32 mc_arb_ramcfg;
1374 u32 db_debug4;
1375
1376 /* setup chip specs */
1377 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1378 case CHIP_RV770:
1379 dev_priv->r600_max_pipes = 4;
1380 dev_priv->r600_max_tile_pipes = 8;
1381 dev_priv->r600_max_simds = 10;
1382 dev_priv->r600_max_backends = 4;
1383 dev_priv->r600_max_gprs = 256;
1384 dev_priv->r600_max_threads = 248;
1385 dev_priv->r600_max_stack_entries = 512;
1386 dev_priv->r600_max_hw_contexts = 8;
1387 dev_priv->r600_max_gs_threads = 16 * 2;
1388 dev_priv->r600_sx_max_export_size = 128;
1389 dev_priv->r600_sx_max_export_pos_size = 16;
1390 dev_priv->r600_sx_max_export_smx_size = 112;
1391 dev_priv->r600_sq_num_cf_insts = 2;
1392
1393 dev_priv->r700_sx_num_of_sets = 7;
1394 dev_priv->r700_sc_prim_fifo_size = 0xF9;
1395 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1396 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1397 break;
1398 case CHIP_RV730:
1399 dev_priv->r600_max_pipes = 2;
1400 dev_priv->r600_max_tile_pipes = 4;
1401 dev_priv->r600_max_simds = 8;
1402 dev_priv->r600_max_backends = 2;
1403 dev_priv->r600_max_gprs = 128;
1404 dev_priv->r600_max_threads = 248;
1405 dev_priv->r600_max_stack_entries = 256;
1406 dev_priv->r600_max_hw_contexts = 8;
1407 dev_priv->r600_max_gs_threads = 16 * 2;
1408 dev_priv->r600_sx_max_export_size = 256;
1409 dev_priv->r600_sx_max_export_pos_size = 32;
1410 dev_priv->r600_sx_max_export_smx_size = 224;
1411 dev_priv->r600_sq_num_cf_insts = 2;
1412
1413 dev_priv->r700_sx_num_of_sets = 7;
1414 dev_priv->r700_sc_prim_fifo_size = 0xf9;
1415 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1416 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
2a71ebcd
AD		 1417 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1418 dev_priv->r600_sx_max_export_pos_size -= 16;
1419 dev_priv->r600_sx_max_export_smx_size += 16;
1420 }
c05ce083
AD		 1421 break;
1422 case CHIP_RV710:
1423 dev_priv->r600_max_pipes = 2;
1424 dev_priv->r600_max_tile_pipes = 2;
1425 dev_priv->r600_max_simds = 2;
1426 dev_priv->r600_max_backends = 1;
1427 dev_priv->r600_max_gprs = 256;
1428 dev_priv->r600_max_threads = 192;
1429 dev_priv->r600_max_stack_entries = 256;
1430 dev_priv->r600_max_hw_contexts = 4;
1431 dev_priv->r600_max_gs_threads = 8 * 2;
1432 dev_priv->r600_sx_max_export_size = 128;
1433 dev_priv->r600_sx_max_export_pos_size = 16;
1434 dev_priv->r600_sx_max_export_smx_size = 112;
1435 dev_priv->r600_sq_num_cf_insts = 1;
1436
1437 dev_priv->r700_sx_num_of_sets = 7;
1438 dev_priv->r700_sc_prim_fifo_size = 0x40;
1439 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1440 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1441 break;
2a71ebcd
AD		 1442 case CHIP_RV740:
1443 dev_priv->r600_max_pipes = 4;
1444 dev_priv->r600_max_tile_pipes = 4;
1445 dev_priv->r600_max_simds = 8;
1446 dev_priv->r600_max_backends = 4;
1447 dev_priv->r600_max_gprs = 256;
1448 dev_priv->r600_max_threads = 248;
1449 dev_priv->r600_max_stack_entries = 512;
1450 dev_priv->r600_max_hw_contexts = 8;
1451 dev_priv->r600_max_gs_threads = 16 * 2;
1452 dev_priv->r600_sx_max_export_size = 256;
1453 dev_priv->r600_sx_max_export_pos_size = 32;
1454 dev_priv->r600_sx_max_export_smx_size = 224;
1455 dev_priv->r600_sq_num_cf_insts = 2;
1456
1457 dev_priv->r700_sx_num_of_sets = 7;
1458 dev_priv->r700_sc_prim_fifo_size = 0x100;
1459 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1460 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1461
1462 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1463 dev_priv->r600_sx_max_export_pos_size -= 16;
1464 dev_priv->r600_sx_max_export_smx_size += 16;
1465 }
1466 break;
c05ce083
AD		 1467 default:
1468 break;
1469 }
1470
1471 /* Initialize HDP */
1472 j = 0;
1473 for (i = 0; i < 32; i++) {
1474 RADEON_WRITE((0x2c14 + j), 0x00000000);
1475 RADEON_WRITE((0x2c18 + j), 0x00000000);
1476 RADEON_WRITE((0x2c1c + j), 0x00000000);
1477 RADEON_WRITE((0x2c20 + j), 0x00000000);
1478 RADEON_WRITE((0x2c24 + j), 0x00000000);
1479 j += 0x18;
1480 }
1481
1482 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
1483
1484 /* setup tiling, simd, pipe config */
1485 mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG);
1486
1487 switch (dev_priv->r600_max_tile_pipes) {
1488 case 1:
1489 gb_tiling_config |= R600_PIPE_TILING(0);
1490 break;
1491 case 2:
1492 gb_tiling_config |= R600_PIPE_TILING(1);
1493 break;
1494 case 4:
1495 gb_tiling_config |= R600_PIPE_TILING(2);
1496 break;
1497 case 8:
1498 gb_tiling_config |= R600_PIPE_TILING(3);
1499 break;
1500 default:
1501 break;
1502 }
1503
1504 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1505 gb_tiling_config |= R600_BANK_TILING(1);
1506 else
1507 gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK);
1508
1509 gb_tiling_config |= R600_GROUP_SIZE(0);
1510
1511 if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) {
1512 gb_tiling_config |= R600_ROW_TILING(3);
1513 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
1514 } else {
1515 gb_tiling_config |=
1516 R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1517 gb_tiling_config |=
1518 R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1519 }
1520
1521 gb_tiling_config |= R600_BANK_SWAPS(1);
1522
d03f5d59
AD		 1523 cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1524 cc_rb_backend_disable |=
1525 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK);
c05ce083 1526
d03f5d59
AD		 1527 cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1528 cc_gc_shader_pipe_config |=
c05ce083
AD		 1529 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK);
1530 cc_gc_shader_pipe_config |=
1531 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK);
1532
d03f5d59
AD		 1533 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740)
1534 backend_map = 0x28;
1535 else
1536 backend_map = r700_get_tile_pipe_to_backend_map(dev_priv,
1537 dev_priv->r600_max_tile_pipes,
1538 (R7XX_MAX_BACKENDS -
1539 r600_count_pipe_bits((cc_rb_backend_disable &
1540 R7XX_MAX_BACKENDS_MASK) >> 16)),
1541 (cc_rb_backend_disable >> 16));
1542 gb_tiling_config |= R600_BACKEND_MAP(backend_map);
c05ce083
AD		 1543
1544 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config);
1545 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1546 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
961fb597
JG		 1547 if (gb_tiling_config & 0xc0) {
1548 dev_priv->r600_group_size = 512;
1549 } else {
1550 dev_priv->r600_group_size = 256;
1551 }
1552 dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7);
1553 if (gb_tiling_config & 0x30) {
1554 dev_priv->r600_nbanks = 8;
1555 } else {
1556 dev_priv->r600_nbanks = 4;
1557 }
c05ce083
AD		 1558
1559 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1560 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
f867c60d 1561 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
c05ce083
AD		 1562
1563 RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1564 RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0);
1565 RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0);
f867c60d
AD		 1566 RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0);
1567 RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0);
c05ce083
AD		 1568
1569 num_qd_pipes =
d03f5d59 1570 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8);
c05ce083
AD		 1571 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
1572 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
1573
1574 /* set HW defaults for 3D engine */
1575 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
1576 R600_ROQ_IB2_START(0x2b)));
1577
1578 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30));
1579
d03f5d59
AD		 1580 ta_aux_cntl = RADEON_READ(R600_TA_CNTL_AUX);
1581 RADEON_WRITE(R600_TA_CNTL_AUX, ta_aux_cntl | R600_DISABLE_CUBE_ANISO);
c05ce083
AD		 1582
1583 sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1);
1584 sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS;
1585 RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1);
1586
1587 smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0);
1588 smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff);
1589 smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1);
1590 RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0);
1591
d03f5d59
AD		 1592 if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV740)
1593 RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) |
1594 R700_GS_FLUSH_CTL(4) |
1595 R700_ACK_FLUSH_CTL(3) |
1596 R700_SYNC_FLUSH_CTL));
c05ce083 1597
d03f5d59
AD		 1598 db_debug3 = RADEON_READ(R700_DB_DEBUG3);
1599 db_debug3 &= ~R700_DB_CLK_OFF_DELAY(0x1f);
1600 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1601 case CHIP_RV770:
1602 case CHIP_RV740:
1603 db_debug3 |= R700_DB_CLK_OFF_DELAY(0x1f);
1604 break;
1605 case CHIP_RV710:
1606 case CHIP_RV730:
1607 default:
1608 db_debug3 |= R700_DB_CLK_OFF_DELAY(2);
1609 break;
1610 }
1611 RADEON_WRITE(R700_DB_DEBUG3, db_debug3);
1612
1613 if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV770) {
c05ce083
AD		 1614 db_debug4 = RADEON_READ(RV700_DB_DEBUG4);
1615 db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER;
1616 RADEON_WRITE(RV700_DB_DEBUG4, db_debug4);
1617 }
1618
1619 RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) |
1620 R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) |
1621 R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1)));
1622
1623 RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) |
1624 R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) |
1625 R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize)));
1626
1627 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1628
1629 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1);
1630
1631 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
1632
1633 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4));
1634
1635 RADEON_WRITE(R600_CP_PERFMON_CNTL, 0);
1636
1637 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) |
1638 R600_DONE_FIFO_HIWATER(0xe0) |
1639 R600_ALU_UPDATE_FIFO_HIWATER(0x8));
1640 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1641 case CHIP_RV770:
c05ce083
AD		 1642 case CHIP_RV730:
1643 case CHIP_RV710:
d03f5d59
AD		 1644 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1);
1645 break;
2a71ebcd 1646 case CHIP_RV740:
c05ce083
AD		 1647 default:
1648 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4);
1649 break;
1650 }
1651 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1652
1653 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1654 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1655 */
1656 sq_config = RADEON_READ(R600_SQ_CONFIG);
1657 sq_config &= ~(R600_PS_PRIO(3) |
1658 R600_VS_PRIO(3) |
1659 R600_GS_PRIO(3) |
1660 R600_ES_PRIO(3));
1661 sq_config |= (R600_DX9_CONSTS |
1662 R600_VC_ENABLE |
1663 R600_EXPORT_SRC_C |
1664 R600_PS_PRIO(0) |
1665 R600_VS_PRIO(1) |
1666 R600_GS_PRIO(2) |
1667 R600_ES_PRIO(3));
1668 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1669 /* no vertex cache */
1670 sq_config &= ~R600_VC_ENABLE;
1671
1672 RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1673
1674 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1675 R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1676 R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2)));
1677
1678 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) |
1679 R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64)));
1680
1681 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) |
1682 R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) |
1683 R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8));
1684 if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads)
1685 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads);
1686 else
1687 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8);
1688 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1689
1690 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1691 R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1692
1693 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1694 R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1695
1696 sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) |
1697 R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) |
1698 R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) |
1699 R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64));
1700
1701 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1702 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1703 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1704 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1705 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1706 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1707 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1708 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1709
1710 RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) |
1711 R700_FORCE_EOV_MAX_REZ_CNT(255)));
1712
1713 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1714 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) |
1715 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1716 else
1717 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) |
1718 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1719
1720 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1721 case CHIP_RV770:
1722 case CHIP_RV730:
2a71ebcd 1723 case CHIP_RV740:
c05ce083
AD		 1724 gs_prim_buffer_depth = 384;
1725 break;
1726 case CHIP_RV710:
1727 gs_prim_buffer_depth = 128;
1728 break;
1729 default:
1730 break;
1731 }
1732
1733 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1734 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1735 /* Max value for this is 256 */
1736 if (vgt_gs_per_es > 256)
1737 vgt_gs_per_es = 256;
1738
1739 RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1740 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1741 RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1742
1743 /* more default values. 2D/3D driver should adjust as needed */
1744 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1745 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1746 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1747 RADEON_WRITE(R600_SX_MISC, 0);
1748 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1749 RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa);
1750 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1751 RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff);
1752 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1753 RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1754 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1755 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1756
1757 /* clear render buffer base addresses */
1758 RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1759 RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1760 RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1761 RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1762 RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1763 RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1764 RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1765 RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1766
1767 RADEON_WRITE(R700_TCP_CNTL, 0);
1768
1769 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1770 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1771
1772 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1773
1774 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1775 R600_NUM_CLIP_SEQ(3)));
1776
1777}
1778
1779static void r600_cp_init_ring_buffer(struct drm_device *dev,
1780 drm_radeon_private_t *dev_priv,
1781 struct drm_file *file_priv)
1782{
1783 struct drm_radeon_master_private *master_priv;
1784 u32 ring_start;
6546bf6d 1785 u64 rptr_addr;
c05ce083
AD		 1786
1787 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
1788 r700_gfx_init(dev, dev_priv);
1789 else
1790 r600_gfx_init(dev, dev_priv);
1791
1792 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
1793 RADEON_READ(R600_GRBM_SOFT_RESET);
4de833c3 1794 mdelay(15);
c05ce083
AD		 1795 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
1796
1797
1798 /* Set ring buffer size */
1799#ifdef __BIG_ENDIAN
1800 RADEON_WRITE(R600_CP_RB_CNTL,
df07d699
BH		 1801 R600_BUF_SWAP_32BIT |
1802 R600_RB_NO_UPDATE |
c05ce083
AD		 1803 (dev_priv->ring.rptr_update_l2qw << 8) |
1804 dev_priv->ring.size_l2qw);
1805#else
1806 RADEON_WRITE(R600_CP_RB_CNTL,
1807 RADEON_RB_NO_UPDATE |
1808 (dev_priv->ring.rptr_update_l2qw << 8) |
1809 dev_priv->ring.size_l2qw);
1810#endif
1811
15d3332f 1812 RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x0);
c05ce083
AD		 1813
1814 /* Set the write pointer delay */
1815 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
1816
1817#ifdef __BIG_ENDIAN
1818 RADEON_WRITE(R600_CP_RB_CNTL,
df07d699
BH		 1819 R600_BUF_SWAP_32BIT |
1820 R600_RB_NO_UPDATE |
1821 R600_RB_RPTR_WR_ENA |
c05ce083
AD		 1822 (dev_priv->ring.rptr_update_l2qw << 8) |
1823 dev_priv->ring.size_l2qw);
1824#else
1825 RADEON_WRITE(R600_CP_RB_CNTL,
df07d699
BH		 1826 R600_RB_NO_UPDATE |
1827 R600_RB_RPTR_WR_ENA |
c05ce083
AD		 1828 (dev_priv->ring.rptr_update_l2qw << 8) |
1829 dev_priv->ring.size_l2qw);
1830#endif
1831
1832 /* Initialize the ring buffer's read and write pointers */
1833 RADEON_WRITE(R600_CP_RB_RPTR_WR, 0);
1834 RADEON_WRITE(R600_CP_RB_WPTR, 0);
1835 SET_RING_HEAD(dev_priv, 0);
1836 dev_priv->ring.tail = 0;
1837
1838#if __OS_HAS_AGP
1839 if (dev_priv->flags & RADEON_IS_AGP) {
6546bf6d
DA		 1840 rptr_addr = dev_priv->ring_rptr->offset
1841 - dev->agp->base +
1842 dev_priv->gart_vm_start;
c05ce083
AD		 1843 } else
1844#endif
1845 {
6546bf6d
DA		 1846 rptr_addr = dev_priv->ring_rptr->offset
1847 - ((unsigned long) dev->sg->virtual)
1848 + dev_priv->gart_vm_start;
c05ce083 1849 }
df07d699
BH		 1850 RADEON_WRITE(R600_CP_RB_RPTR_ADDR, (rptr_addr & 0xfffffffc));
1851 RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, upper_32_bits(rptr_addr));
c05ce083
AD		 1852
1853#ifdef __BIG_ENDIAN
1854 RADEON_WRITE(R600_CP_RB_CNTL,
1855 RADEON_BUF_SWAP_32BIT |
1856 (dev_priv->ring.rptr_update_l2qw << 8) |
1857 dev_priv->ring.size_l2qw);
1858#else
1859 RADEON_WRITE(R600_CP_RB_CNTL,
1860 (dev_priv->ring.rptr_update_l2qw << 8) |
1861 dev_priv->ring.size_l2qw);
1862#endif
1863
1864#if __OS_HAS_AGP
1865 if (dev_priv->flags & RADEON_IS_AGP) {
1866 /* XXX */
1867 radeon_write_agp_base(dev_priv, dev->agp->base);
1868
1869 /* XXX */
1870 radeon_write_agp_location(dev_priv,
1871 (((dev_priv->gart_vm_start - 1 +
1872 dev_priv->gart_size) & 0xffff0000) |
1873 (dev_priv->gart_vm_start >> 16)));
1874
1875 ring_start = (dev_priv->cp_ring->offset
1876 - dev->agp->base
1877 + dev_priv->gart_vm_start);
1878 } else
1879#endif
1880 ring_start = (dev_priv->cp_ring->offset
1881 - (unsigned long)dev->sg->virtual
1882 + dev_priv->gart_vm_start);
1883
1884 RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8);
1885
1886 RADEON_WRITE(R600_CP_ME_CNTL, 0xff);
1887
1888 RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28));
1889
c05ce083
AD		 1890 /* Initialize the scratch register pointer. This will cause
1891 * the scratch register values to be written out to memory
1892 * whenever they are updated.
1893 *
1894 * We simply put this behind the ring read pointer, this works
1895 * with PCI GART as well as (whatever kind of) AGP GART
1896 */
6546bf6d
DA		 1897 {
1898 u64 scratch_addr;
1899
dee54c40 1900 scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR) & 0xFFFFFFFC;
6546bf6d
DA		 1901 scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32;
1902 scratch_addr += R600_SCRATCH_REG_OFFSET;
1903 scratch_addr >>= 8;
1904 scratch_addr &= 0xffffffff;
1905
1906 RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr);
1907 }
c05ce083
AD		 1908
1909 RADEON_WRITE(R600_SCRATCH_UMSK, 0x7);
1910
1911 /* Turn on bus mastering */
1912 radeon_enable_bm(dev_priv);
1913
1914 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0);
1915 RADEON_WRITE(R600_LAST_FRAME_REG, 0);
1916
1917 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
1918 RADEON_WRITE(R600_LAST_DISPATCH_REG, 0);
1919
1920 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0);
1921 RADEON_WRITE(R600_LAST_CLEAR_REG, 0);
1922
1923 /* reset sarea copies of these */
1924 master_priv = file_priv->master->driver_priv;
1925 if (master_priv->sarea_priv) {
1926 master_priv->sarea_priv->last_frame = 0;
1927 master_priv->sarea_priv->last_dispatch = 0;
1928 master_priv->sarea_priv->last_clear = 0;
1929 }
1930
1931 r600_do_wait_for_idle(dev_priv);
1932
1933}
1934
1935int r600_do_cleanup_cp(struct drm_device *dev)
1936{
1937 drm_radeon_private_t *dev_priv = dev->dev_private;
1938 DRM_DEBUG("\n");
1939
1940 /* Make sure interrupts are disabled here because the uninstall ioctl
1941 * may not have been called from userspace and after dev_private
1942 * is freed, it's too late.
1943 */
1944 if (dev->irq_enabled)
1945 drm_irq_uninstall(dev);
1946
1947#if __OS_HAS_AGP
1948 if (dev_priv->flags & RADEON_IS_AGP) {
1949 if (dev_priv->cp_ring != NULL) {
1950 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1951 dev_priv->cp_ring = NULL;
1952 }
1953 if (dev_priv->ring_rptr != NULL) {
1954 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1955 dev_priv->ring_rptr = NULL;
1956 }
1957 if (dev->agp_buffer_map != NULL) {
1958 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1959 dev->agp_buffer_map = NULL;
1960 }
1961 } else
1962#endif
1963 {
1964
1965 if (dev_priv->gart_info.bus_addr)
1966 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1967
1968 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) {
1969 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
8f497aad 1970 dev_priv->gart_info.addr = NULL;
c05ce083
AD		 1971 }
1972 }
1973 /* only clear to the start of flags */
1974 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1975
1976 return 0;
1977}
1978
1979int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1980 struct drm_file *file_priv)
1981{
1982 drm_radeon_private_t *dev_priv = dev->dev_private;
1983 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1984
1985 DRM_DEBUG("\n");
1986
3ce0a23d
JG		 1987 mutex_init(&dev_priv->cs_mutex);
1988 r600_cs_legacy_init();
c05ce083
AD		 1989 /* if we require new memory map but we don't have it fail */
1990 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1991 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1992 r600_do_cleanup_cp(dev);
1993 return -EINVAL;
1994 }
1995
1996 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1997 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1998 dev_priv->flags &= ~RADEON_IS_AGP;
1999 /* The writeback test succeeds, but when writeback is enabled,
2000 * the ring buffer read ptr update fails after first 128 bytes.
2001 */
2002 radeon_no_wb = 1;
2003 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
2004 && !init->is_pci) {
2005 DRM_DEBUG("Restoring AGP flag\n");
2006 dev_priv->flags |= RADEON_IS_AGP;
2007 }
2008
2009 dev_priv->usec_timeout = init->usec_timeout;
2010 if (dev_priv->usec_timeout < 1 ||
2011 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
2012 DRM_DEBUG("TIMEOUT problem!\n");
2013 r600_do_cleanup_cp(dev);
2014 return -EINVAL;
2015 }
2016
2017 /* Enable vblank on CRTC1 for older X servers
2018 */
2019 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
3ce0a23d 2020 dev_priv->do_boxes = 0;
c05ce083
AD		 2021 dev_priv->cp_mode = init->cp_mode;
2022
2023 /* We don't support anything other than bus-mastering ring mode,
2024 * but the ring can be in either AGP or PCI space for the ring
2025 * read pointer.
2026 */
2027 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
2028 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
2029 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
2030 r600_do_cleanup_cp(dev);
2031 return -EINVAL;
2032 }
2033
2034 switch (init->fb_bpp) {
2035 case 16:
2036 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
2037 break;
2038 case 32:
2039 default:
2040 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
2041 break;
2042 }
2043 dev_priv->front_offset = init->front_offset;
2044 dev_priv->front_pitch = init->front_pitch;
2045 dev_priv->back_offset = init->back_offset;
2046 dev_priv->back_pitch = init->back_pitch;
2047
2048 dev_priv->ring_offset = init->ring_offset;
2049 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
2050 dev_priv->buffers_offset = init->buffers_offset;
2051 dev_priv->gart_textures_offset = init->gart_textures_offset;
2052
2053 master_priv->sarea = drm_getsarea(dev);
2054 if (!master_priv->sarea) {
2055 DRM_ERROR("could not find sarea!\n");
2056 r600_do_cleanup_cp(dev);
2057 return -EINVAL;
2058 }
2059
2060 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
2061 if (!dev_priv->cp_ring) {
2062 DRM_ERROR("could not find cp ring region!\n");
2063 r600_do_cleanup_cp(dev);
2064 return -EINVAL;
2065 }
2066 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
2067 if (!dev_priv->ring_rptr) {
2068 DRM_ERROR("could not find ring read pointer!\n");
2069 r600_do_cleanup_cp(dev);
2070 return -EINVAL;
2071 }
2072 dev->agp_buffer_token = init->buffers_offset;
2073 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
2074 if (!dev->agp_buffer_map) {
2075 DRM_ERROR("could not find dma buffer region!\n");
2076 r600_do_cleanup_cp(dev);
2077 return -EINVAL;
2078 }
2079
2080 if (init->gart_textures_offset) {
2081 dev_priv->gart_textures =
2082 drm_core_findmap(dev, init->gart_textures_offset);
2083 if (!dev_priv->gart_textures) {
2084 DRM_ERROR("could not find GART texture region!\n");
2085 r600_do_cleanup_cp(dev);
2086 return -EINVAL;
2087 }
2088 }
2089
2090#if __OS_HAS_AGP
2091 /* XXX */
2092 if (dev_priv->flags & RADEON_IS_AGP) {
7659e980
AD		 2093 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
2094 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
2095 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
c05ce083
AD		 2096 if (!dev_priv->cp_ring->handle ||
2097 !dev_priv->ring_rptr->handle ||
2098 !dev->agp_buffer_map->handle) {
2099 DRM_ERROR("could not find ioremap agp regions!\n");
2100 r600_do_cleanup_cp(dev);
2101 return -EINVAL;
2102 }
2103 } else
2104#endif
2105 {
3ce0a23d 2106 dev_priv->cp_ring->handle = (void *)(unsigned long)dev_priv->cp_ring->offset;
c05ce083 2107 dev_priv->ring_rptr->handle =
3ce0a23d 2108 (void *)(unsigned long)dev_priv->ring_rptr->offset;
c05ce083 2109 dev->agp_buffer_map->handle =
3ce0a23d 2110 (void *)(unsigned long)dev->agp_buffer_map->offset;
c05ce083
AD		 2111
2112 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
2113 dev_priv->cp_ring->handle);
2114 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
2115 dev_priv->ring_rptr->handle);
2116 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
2117 dev->agp_buffer_map->handle);
2118 }
2119
2120 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24;
2121 dev_priv->fb_size =
2122 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000)
2123 - dev_priv->fb_location;
2124
2125 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
2126 ((dev_priv->front_offset
2127 + dev_priv->fb_location) >> 10));
2128
2129 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
2130 ((dev_priv->back_offset
2131 + dev_priv->fb_location) >> 10));
2132
2133 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
2134 ((dev_priv->depth_offset
2135 + dev_priv->fb_location) >> 10));
2136
2137 dev_priv->gart_size = init->gart_size;
2138
2139 /* New let's set the memory map ... */
2140 if (dev_priv->new_memmap) {
2141 u32 base = 0;
2142
2143 DRM_INFO("Setting GART location based on new memory map\n");
2144
2145 /* If using AGP, try to locate the AGP aperture at the same
2146 * location in the card and on the bus, though we have to
2147 * align it down.
2148 */
2149#if __OS_HAS_AGP
2150 /* XXX */
2151 if (dev_priv->flags & RADEON_IS_AGP) {
2152 base = dev->agp->base;
2153 /* Check if valid */
2154 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
2155 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
2156 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
2157 dev->agp->base);
2158 base = 0;
2159 }
2160 }
2161#endif
2162 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
2163 if (base == 0) {
2164 base = dev_priv->fb_location + dev_priv->fb_size;
2165 if (base < dev_priv->fb_location ||
2166 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
2167 base = dev_priv->fb_location
2168 - dev_priv->gart_size;
2169 }
2170 dev_priv->gart_vm_start = base & 0xffc00000u;
2171 if (dev_priv->gart_vm_start != base)
2172 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
2173 base, dev_priv->gart_vm_start);
2174 }
2175
2176#if __OS_HAS_AGP
2177 /* XXX */
2178 if (dev_priv->flags & RADEON_IS_AGP)
2179 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2180 - dev->agp->base
2181 + dev_priv->gart_vm_start);
2182 else
2183#endif
2184 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2185 - (unsigned long)dev->sg->virtual
2186 + dev_priv->gart_vm_start);
2187
2188 DRM_DEBUG("fb 0x%08x size %d\n",
2189 (unsigned int) dev_priv->fb_location,
2190 (unsigned int) dev_priv->fb_size);
2191 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
2192 DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
2193 (unsigned int) dev_priv->gart_vm_start);
2194 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
2195 dev_priv->gart_buffers_offset);
2196
2197 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
2198 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
2199 + init->ring_size / sizeof(u32));
2200 dev_priv->ring.size = init->ring_size;
2201 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
2202
2203 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
2204 dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8);
2205
2206 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
2207 dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16);
2208
2209 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
2210
2211 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
2212
2213#if __OS_HAS_AGP
2214 if (dev_priv->flags & RADEON_IS_AGP) {
2215 /* XXX turn off pcie gart */
2216 } else
2217#endif
2218 {
2219 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
2220 /* if we have an offset set from userspace */
2221 if (!dev_priv->pcigart_offset_set) {
2222 DRM_ERROR("Need gart offset from userspace\n");
2223 r600_do_cleanup_cp(dev);
2224 return -EINVAL;
2225 }
2226
2227 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset);
2228
2229 dev_priv->gart_info.bus_addr =
2230 dev_priv->pcigart_offset + dev_priv->fb_location;
2231 dev_priv->gart_info.mapping.offset =
2232 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
2233 dev_priv->gart_info.mapping.size =
2234 dev_priv->gart_info.table_size;
2235
2236 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
2237 if (!dev_priv->gart_info.mapping.handle) {
2238 DRM_ERROR("ioremap failed.\n");
2239 r600_do_cleanup_cp(dev);
2240 return -EINVAL;
2241 }
2242
2243 dev_priv->gart_info.addr =
2244 dev_priv->gart_info.mapping.handle;
2245
2246 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
2247 dev_priv->gart_info.addr,
2248 dev_priv->pcigart_offset);
2249
41f13fe8 2250 if (!r600_page_table_init(dev)) {
c05ce083
AD		 2251 DRM_ERROR("Failed to init GART table\n");
2252 r600_do_cleanup_cp(dev);
2253 return -EINVAL;
2254 }
2255
2256 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2257 r700_vm_init(dev);
2258 else
2259 r600_vm_init(dev);
2260 }
2261
70967ab9
BH		 2262 if (!dev_priv->me_fw || !dev_priv->pfp_fw) {
2263 int err = r600_cp_init_microcode(dev_priv);
2264 if (err) {
2265 DRM_ERROR("Failed to load firmware!\n");
2266 r600_do_cleanup_cp(dev);
2267 return err;
2268 }
2269 }
c05ce083
AD		 2270 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2271 r700_cp_load_microcode(dev_priv);
2272 else
2273 r600_cp_load_microcode(dev_priv);
2274
2275 r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2276
2277 dev_priv->last_buf = 0;
2278
2279 r600_do_engine_reset(dev);
2280 r600_test_writeback(dev_priv);
2281
2282 return 0;
2283}
2284
2285int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
2286{
2287 drm_radeon_private_t *dev_priv = dev->dev_private;
2288
2289 DRM_DEBUG("\n");
2290 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) {
2291 r700_vm_init(dev);
2292 r700_cp_load_microcode(dev_priv);
2293 } else {
2294 r600_vm_init(dev);
2295 r600_cp_load_microcode(dev_priv);
2296 }
2297 r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2298 r600_do_engine_reset(dev);
2299
2300 return 0;
2301}
2302
2303/* Wait for the CP to go idle.
2304 */
2305int r600_do_cp_idle(drm_radeon_private_t *dev_priv)
2306{
2307 RING_LOCALS;
2308 DRM_DEBUG("\n");
2309
2310 BEGIN_RING(5);
2311 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
2312 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
2313 /* wait for 3D idle clean */
2314 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
2315 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
2316 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
2317
2318 ADVANCE_RING();
2319 COMMIT_RING();
2320
2321 return r600_do_wait_for_idle(dev_priv);
2322}
2323
2324/* Start the Command Processor.
2325 */
2326void r600_do_cp_start(drm_radeon_private_t *dev_priv)
2327{
2328 u32 cp_me;
2329 RING_LOCALS;
2330 DRM_DEBUG("\n");
2331
2332 BEGIN_RING(7);
2333 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5));
2334 OUT_RING(0x00000001);
2335 if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770))
2336 OUT_RING(0x00000003);
2337 else
2338 OUT_RING(0x00000000);
2339 OUT_RING((dev_priv->r600_max_hw_contexts - 1));
2340 OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1));
2341 OUT_RING(0x00000000);
2342 OUT_RING(0x00000000);
2343 ADVANCE_RING();
2344 COMMIT_RING();
2345
2346 /* set the mux and reset the halt bit */
2347 cp_me = 0xff;
2348 RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2349
2350 dev_priv->cp_running = 1;
2351
2352}
2353
2354void r600_do_cp_reset(drm_radeon_private_t *dev_priv)
2355{
2356 u32 cur_read_ptr;
2357 DRM_DEBUG("\n");
2358
2359 cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR);
2360 RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr);
2361 SET_RING_HEAD(dev_priv, cur_read_ptr);
2362 dev_priv->ring.tail = cur_read_ptr;
2363}
2364
2365void r600_do_cp_stop(drm_radeon_private_t *dev_priv)
2366{
2367 uint32_t cp_me;
2368
2369 DRM_DEBUG("\n");
2370
2371 cp_me = 0xff | R600_CP_ME_HALT;
2372
2373 RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2374
2375 dev_priv->cp_running = 0;
2376}
2377
2378int r600_cp_dispatch_indirect(struct drm_device *dev,
2379 struct drm_buf *buf, int start, int end)
2380{
2381 drm_radeon_private_t *dev_priv = dev->dev_private;
2382 RING_LOCALS;
2383
2384 if (start != end) {
2385 unsigned long offset = (dev_priv->gart_buffers_offset
2386 + buf->offset + start);
2387 int dwords = (end - start + 3) / sizeof(u32);
2388
2389 DRM_DEBUG("dwords:%d\n", dwords);
2390 DRM_DEBUG("offset 0x%lx\n", offset);
2391
2392
2393 /* Indirect buffer data must be a multiple of 16 dwords.
2394 * pad the data with a Type-2 CP packet.
2395 */
2396 while (dwords & 0xf) {
2397 u32 *data = (u32 *)
2398 ((char *)dev->agp_buffer_map->handle
2399 + buf->offset + start);
2400 data[dwords++] = RADEON_CP_PACKET2;
2401 }
2402
2403 /* Fire off the indirect buffer */
2404 BEGIN_RING(4);
2405 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2));
2406 OUT_RING((offset & 0xfffffffc));
2407 OUT_RING((upper_32_bits(offset) & 0xff));
2408 OUT_RING(dwords);
2409 ADVANCE_RING();
2410 }
2411
2412 return 0;
2413}
3ce0a23d
JG		 2414
2415void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv)
2416{
2417 drm_radeon_private_t *dev_priv = dev->dev_private;
2418 struct drm_master *master = file_priv->master;
2419 struct drm_radeon_master_private *master_priv = master->driver_priv;
2420 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
2421 int nbox = sarea_priv->nbox;
2422 struct drm_clip_rect *pbox = sarea_priv->boxes;
2423 int i, cpp, src_pitch, dst_pitch;
2424 uint64_t src, dst;
2425 RING_LOCALS;
2426 DRM_DEBUG("\n");
2427
2428 if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888)
2429 cpp = 4;
2430 else
2431 cpp = 2;
2432
2433 if (sarea_priv->pfCurrentPage == 0) {
2434 src_pitch = dev_priv->back_pitch;
2435 dst_pitch = dev_priv->front_pitch;
2436 src = dev_priv->back_offset + dev_priv->fb_location;
2437 dst = dev_priv->front_offset + dev_priv->fb_location;
2438 } else {
2439 src_pitch = dev_priv->front_pitch;
2440 dst_pitch = dev_priv->back_pitch;
2441 src = dev_priv->front_offset + dev_priv->fb_location;
2442 dst = dev_priv->back_offset + dev_priv->fb_location;
2443 }
2444
2445 if (r600_prepare_blit_copy(dev, file_priv)) {
2446 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
2447 return;
2448 }
2449 for (i = 0; i < nbox; i++) {
2450 int x = pbox[i].x1;
2451 int y = pbox[i].y1;
2452 int w = pbox[i].x2 - x;
2453 int h = pbox[i].y2 - y;
2454
2455 DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h);
2456
2457 r600_blit_swap(dev,
2458 src, dst,
2459 x, y, x, y, w, h,
2460 src_pitch, dst_pitch, cpp);
2461 }
2462 r600_done_blit_copy(dev);
2463
2464 /* Increment the frame counter. The client-side 3D driver must
2465 * throttle the framerate by waiting for this value before
2466 * performing the swapbuffer ioctl.
2467 */
2468 sarea_priv->last_frame++;
2469
2470 BEGIN_RING(3);
2471 R600_FRAME_AGE(sarea_priv->last_frame);
2472 ADVANCE_RING();
2473}
2474
2475int r600_cp_dispatch_texture(struct drm_device *dev,
2476 struct drm_file *file_priv,
2477 drm_radeon_texture_t *tex,
2478 drm_radeon_tex_image_t *image)
2479{
2480 drm_radeon_private_t *dev_priv = dev->dev_private;
2481 struct drm_buf *buf;
2482 u32 *buffer;
2483 const u8 __user *data;
2484 int size, pass_size;
2485 u64 src_offset, dst_offset;
2486
2487 if (!radeon_check_offset(dev_priv, tex->offset)) {
2488 DRM_ERROR("Invalid destination offset\n");
2489 return -EINVAL;
2490 }
2491
2492 /* this might fail for zero-sized uploads - are those illegal? */
2493 if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) {
2494 DRM_ERROR("Invalid final destination offset\n");
2495 return -EINVAL;
2496 }
2497
2498 size = tex->height * tex->pitch;
2499
2500 if (size == 0)
2501 return 0;
2502
2503 dst_offset = tex->offset;
2504
2505 if (r600_prepare_blit_copy(dev, file_priv)) {
2506 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
2507 return -EAGAIN;
2508 }
2509 do {
2510 data = (const u8 __user *)image->data;
2511 pass_size = size;
2512
2513 buf = radeon_freelist_get(dev);
2514 if (!buf) {
2515 DRM_DEBUG("EAGAIN\n");
2516 if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image)))
2517 return -EFAULT;
2518 return -EAGAIN;
2519 }
2520
2521 if (pass_size > buf->total)
2522 pass_size = buf->total;
2523
2524 /* Dispatch the indirect buffer.
2525 */
2526 buffer =
2527 (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
2528
2529 if (DRM_COPY_FROM_USER(buffer, data, pass_size)) {
2530 DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size);
2531 return -EFAULT;
2532 }
2533
2534 buf->file_priv = file_priv;
2535 buf->used = pass_size;
2536 src_offset = dev_priv->gart_buffers_offset + buf->offset;
2537
2538 r600_blit_copy(dev, src_offset, dst_offset, pass_size);
2539
2540 radeon_cp_discard_buffer(dev, file_priv->master, buf);
2541
2542 /* Update the input parameters for next time */
2543 image->data = (const u8 __user *)image->data + pass_size;
2544 dst_offset += pass_size;
2545 size -= pass_size;
2546 } while (size > 0);
2547 r600_done_blit_copy(dev);
2548
2549 return 0;
2550}
2551
2552/*
2553 * Legacy cs ioctl
2554 */
2555static u32 radeon_cs_id_get(struct drm_radeon_private *radeon)
2556{
2557 /* FIXME: check if wrap affect last reported wrap & sequence */
2558 radeon->cs_id_scnt = (radeon->cs_id_scnt + 1) & 0x00FFFFFF;
2559 if (!radeon->cs_id_scnt) {
2560 /* increment wrap counter */
2561 radeon->cs_id_wcnt += 0x01000000;
2562 /* valid sequence counter start at 1 */
2563 radeon->cs_id_scnt = 1;
2564 }
2565 return (radeon->cs_id_scnt | radeon->cs_id_wcnt);
2566}
2567
2568static void r600_cs_id_emit(drm_radeon_private_t *dev_priv, u32 *id)
2569{
2570 RING_LOCALS;
2571
2572 *id = radeon_cs_id_get(dev_priv);
2573
2574 /* SCRATCH 2 */
2575 BEGIN_RING(3);
2576 R600_CLEAR_AGE(*id);
2577 ADVANCE_RING();
2578 COMMIT_RING();
2579}
2580
2581static int r600_ib_get(struct drm_device *dev,
2582 struct drm_file *fpriv,
2583 struct drm_buf **buffer)
2584{
2585 struct drm_buf *buf;
2586
2587 *buffer = NULL;
2588 buf = radeon_freelist_get(dev);
2589 if (!buf) {
2590 return -EBUSY;
2591 }
2592 buf->file_priv = fpriv;
2593 *buffer = buf;
2594 return 0;
2595}
2596
2597static void r600_ib_free(struct drm_device *dev, struct drm_buf *buf,
2598 struct drm_file *fpriv, int l, int r)
2599{
2600 drm_radeon_private_t *dev_priv = dev->dev_private;
2601
2602 if (buf) {
2603 if (!r)
2604 r600_cp_dispatch_indirect(dev, buf, 0, l * 4);
2605 radeon_cp_discard_buffer(dev, fpriv->master, buf);
2606 COMMIT_RING();
2607 }
2608}
2609
2610int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
2611{
2612 struct drm_radeon_private *dev_priv = dev->dev_private;
2613 struct drm_radeon_cs *cs = data;
2614 struct drm_buf *buf;
2615 unsigned family;
2616 int l, r = 0;
2617 u32 *ib, cs_id = 0;
2618
2619 if (dev_priv == NULL) {
2620 DRM_ERROR("called with no initialization\n");
2621 return -EINVAL;
2622 }
2623 family = dev_priv->flags & RADEON_FAMILY_MASK;
2624 if (family < CHIP_R600) {
2625 DRM_ERROR("cs ioctl valid only for R6XX & R7XX in legacy mode\n");
2626 return -EINVAL;
2627 }
2628 mutex_lock(&dev_priv->cs_mutex);
2629 /* get ib */
2630 r = r600_ib_get(dev, fpriv, &buf);
2631 if (r) {
2632 DRM_ERROR("ib_get failed\n");
2633 goto out;
2634 }
2635 ib = dev->agp_buffer_map->handle + buf->offset;
2636 /* now parse command stream */
2637 r = r600_cs_legacy(dev, data, fpriv, family, ib, &l);
2638 if (r) {
2639 goto out;
2640 }
2641
2642out:
2643 r600_ib_free(dev, buf, fpriv, l, r);
2644 /* emit cs id sequence */
2645 r600_cs_id_emit(dev_priv, &cs_id);
2646 cs->cs_id = cs_id;
2647 mutex_unlock(&dev_priv->cs_mutex);
2648 return r;
2649}
961fb597
JG		 2650
2651void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size)
2652{
2653 struct drm_radeon_private *dev_priv = dev->dev_private;
2654
2655 *npipes = dev_priv->r600_npipes;
2656 *nbanks = dev_priv->r600_nbanks;
2657 *group_size = dev_priv->r600_group_size;
2658}
Linux kernel - Deliverables
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