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drm/radeon: factor out cs_next_is_pkt3_nop function
[deliverable/linux.git] / drivers / gpu / drm / radeon / r600_cs.c
CommitLineData
3ce0a23d
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
40e2a5c1 28#include <linux/kernel.h>
760285e7 29#include <drm/drmP.h>
3ce0a23d 30#include "radeon.h"
3ce0a23d 31#include "r600d.h"
961fb597 32#include "r600_reg_safe.h"
3ce0a23d
JG		 33
34static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
35 struct radeon_cs_reloc **cs_reloc);
36static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
37 struct radeon_cs_reloc **cs_reloc);
38typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
39static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
961fb597
JG		 40extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
41
3ce0a23d 42
c8c15ff1 43struct r600_cs_track {
961fb597
JG		 44 /* configuration we miror so that we use same code btw kms/ums */
45 u32 group_size;
46 u32 nbanks;
47 u32 npipes;
48 /* value we track */
5f77df36 49 u32 sq_config;
c116cc94 50 u32 log_nsamples;
961fb597
JG		 51 u32 nsamples;
52 u32 cb_color_base_last[8];
53 struct radeon_bo *cb_color_bo[8];
16790569 54 u64 cb_color_bo_mc[8];
c116cc94
MO		 55 u64 cb_color_bo_offset[8];
56 struct radeon_bo *cb_color_frag_bo[8];
57 u64 cb_color_frag_offset[8];
58 struct radeon_bo *cb_color_tile_bo[8];
59 u64 cb_color_tile_offset[8];
60 u32 cb_color_mask[8];
961fb597 61 u32 cb_color_info[8];
285484e2 62 u32 cb_color_view[8];
3c12513d 63 u32 cb_color_size_idx[8]; /* unused */
961fb597 64 u32 cb_target_mask;
3c12513d 65 u32 cb_shader_mask; /* unused */
523885de 66 bool is_resolve;
961fb597
JG		 67 u32 cb_color_size[8];
68 u32 vgt_strmout_en;
69 u32 vgt_strmout_buffer_en;
dd220a00 70 struct radeon_bo *vgt_strmout_bo[4];
3c12513d 71 u64 vgt_strmout_bo_mc[4]; /* unused */
dd220a00
MO		 72 u32 vgt_strmout_bo_offset[4];
73 u32 vgt_strmout_size[4];
961fb597
JG		 74 u32 db_depth_control;
75 u32 db_depth_info;
76 u32 db_depth_size_idx;
77 u32 db_depth_view;
78 u32 db_depth_size;
79 u32 db_offset;
80 struct radeon_bo *db_bo;
16790569 81 u64 db_bo_mc;
779923bc 82 bool sx_misc_kill_all_prims;
3c12513d
MO		 83 bool cb_dirty;
84 bool db_dirty;
85 bool streamout_dirty;
88f50c80
JG		 86 struct radeon_bo *htile_bo;
87 u64 htile_offset;
88 u32 htile_surface;
c8c15ff1
JG		 89};
90
fe6f0bd0
MO		 91#define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 }
92#define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc, CHIP_R600 }
285484e2 93#define FMT_24_BIT(fmt) [fmt] = { 1, 1, 4, 0, CHIP_R600 }
fe6f0bd0 94#define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc, CHIP_R600 }
285484e2 95#define FMT_48_BIT(fmt) [fmt] = { 1, 1, 8, 0, CHIP_R600 }
fe6f0bd0
MO		 96#define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 }
97#define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0, CHIP_R600 }
98#define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 }
60b212f8
DA		 99
100struct gpu_formats {
101 unsigned blockwidth;
102 unsigned blockheight;
103 unsigned blocksize;
104 unsigned valid_color;
fe6f0bd0 105 enum radeon_family min_family;
60b212f8
DA		 106};
107
108static const struct gpu_formats color_formats_table[] = {
109 /* 8 bit */
110 FMT_8_BIT(V_038004_COLOR_8, 1),
111 FMT_8_BIT(V_038004_COLOR_4_4, 1),
112 FMT_8_BIT(V_038004_COLOR_3_3_2, 1),
113 FMT_8_BIT(V_038004_FMT_1, 0),
114
115 /* 16-bit */
116 FMT_16_BIT(V_038004_COLOR_16, 1),
117 FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1),
118 FMT_16_BIT(V_038004_COLOR_8_8, 1),
119 FMT_16_BIT(V_038004_COLOR_5_6_5, 1),
120 FMT_16_BIT(V_038004_COLOR_6_5_5, 1),
121 FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1),
122 FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1),
123 FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1),
124
125 /* 24-bit */
126 FMT_24_BIT(V_038004_FMT_8_8_8),
285484e2 127
60b212f8
DA		 128 /* 32-bit */
129 FMT_32_BIT(V_038004_COLOR_32, 1),
130 FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1),
131 FMT_32_BIT(V_038004_COLOR_16_16, 1),
132 FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1),
133 FMT_32_BIT(V_038004_COLOR_8_24, 1),
134 FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1),
135 FMT_32_BIT(V_038004_COLOR_24_8, 1),
136 FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1),
137 FMT_32_BIT(V_038004_COLOR_10_11_11, 1),
138 FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1),
139 FMT_32_BIT(V_038004_COLOR_11_11_10, 1),
140 FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1),
141 FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1),
142 FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1),
143 FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1),
144 FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0),
145 FMT_32_BIT(V_038004_FMT_32_AS_8, 0),
146 FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0),
147
148 /* 48-bit */
149 FMT_48_BIT(V_038004_FMT_16_16_16),
150 FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT),
151
152 /* 64-bit */
153 FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1),
154 FMT_64_BIT(V_038004_COLOR_32_32, 1),
155 FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1),
156 FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1),
157 FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1),
158
159 FMT_96_BIT(V_038004_FMT_32_32_32),
160 FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT),
161
162 /* 128-bit */
163 FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1),
164 FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1),
165
166 [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 },
167 [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 },
168
169 /* block compressed formats */
170 [V_038004_FMT_BC1] = { 4, 4, 8, 0 },
171 [V_038004_FMT_BC2] = { 4, 4, 16, 0 },
172 [V_038004_FMT_BC3] = { 4, 4, 16, 0 },
173 [V_038004_FMT_BC4] = { 4, 4, 8, 0 },
174 [V_038004_FMT_BC5] = { 4, 4, 16, 0},
fe6f0bd0
MO		 175 [V_038004_FMT_BC6] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
176 [V_038004_FMT_BC7] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
60b212f8 177
fe6f0bd0
MO		 178 /* The other Evergreen formats */
179 [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR},
60b212f8
DA		 180};
181
285484e2 182bool r600_fmt_is_valid_color(u32 format)
60b212f8 183{
cf8a47d1 184 if (format >= ARRAY_SIZE(color_formats_table))
60b212f8 185 return false;
285484e2 186
60b212f8
DA		 187 if (color_formats_table[format].valid_color)
188 return true;
189
190 return false;
191}
192
285484e2 193bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family)
60b212f8 194{
cf8a47d1 195 if (format >= ARRAY_SIZE(color_formats_table))
60b212f8 196 return false;
285484e2 197
fe6f0bd0
MO		 198 if (family < color_formats_table[format].min_family)
199 return false;
200
60b212f8
DA		 201 if (color_formats_table[format].blockwidth > 0)
202 return true;
203
204 return false;
205}
206
285484e2 207int r600_fmt_get_blocksize(u32 format)
60b212f8 208{
cf8a47d1 209 if (format >= ARRAY_SIZE(color_formats_table))
60b212f8
DA		 210 return 0;
211
212 return color_formats_table[format].blocksize;
213}
214
285484e2 215int r600_fmt_get_nblocksx(u32 format, u32 w)
60b212f8
DA		 216{
217 unsigned bw;
cf8a47d1
DC		 218
219 if (format >= ARRAY_SIZE(color_formats_table))
60b212f8
DA		 220 return 0;
221
222 bw = color_formats_table[format].blockwidth;
223 if (bw == 0)
224 return 0;
225
226 return (w + bw - 1) / bw;
227}
228
285484e2 229int r600_fmt_get_nblocksy(u32 format, u32 h)
60b212f8
DA		 230{
231 unsigned bh;
cf8a47d1
DC		 232
233 if (format >= ARRAY_SIZE(color_formats_table))
60b212f8
DA		 234 return 0;
235
236 bh = color_formats_table[format].blockheight;
237 if (bh == 0)
238 return 0;
239
240 return (h + bh - 1) / bh;
241}
242
16790569
AD		 243struct array_mode_checker {
244 int array_mode;
245 u32 group_size;
246 u32 nbanks;
247 u32 npipes;
248 u32 nsamples;
60b212f8 249 u32 blocksize;
16790569
AD		 250};
251
252/* returns alignment in pixels for pitch/height/depth and bytes for base */
488479eb 253static int r600_get_array_mode_alignment(struct array_mode_checker *values,
16790569
AD		 254 u32 *pitch_align,
255 u32 *height_align,
256 u32 *depth_align,
257 u64 *base_align)
258{
259 u32 tile_width = 8;
260 u32 tile_height = 8;
261 u32 macro_tile_width = values->nbanks;
262 u32 macro_tile_height = values->npipes;
60b212f8 263 u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples;
16790569
AD		 264 u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes;
265
266 switch (values->array_mode) {
267 case ARRAY_LINEAR_GENERAL:
268 /* technically tile_width/_height for pitch/height */
269 *pitch_align = 1; /* tile_width */
270 *height_align = 1; /* tile_height */
271 *depth_align = 1;
272 *base_align = 1;
273 break;
274 case ARRAY_LINEAR_ALIGNED:
60b212f8 275 *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));
285484e2 276 *height_align = 1;
16790569
AD		 277 *depth_align = 1;
278 *base_align = values->group_size;
279 break;
280 case ARRAY_1D_TILED_THIN1:
281 *pitch_align = max((u32)tile_width,
282 (u32)(values->group_size /
60b212f8 283 (tile_height * values->blocksize * values->nsamples)));
16790569
AD		 284 *height_align = tile_height;
285 *depth_align = 1;
286 *base_align = values->group_size;
287 break;
288 case ARRAY_2D_TILED_THIN1:
285484e2
JG		 289 *pitch_align = max((u32)macro_tile_width * tile_width,
290 (u32)((values->group_size * values->nbanks) /
291 (values->blocksize * values->nsamples * tile_width)));
16790569
AD		 292 *height_align = macro_tile_height * tile_height;
293 *depth_align = 1;
294 *base_align = max(macro_tile_bytes,
60b212f8 295 (*pitch_align) * values->blocksize * (*height_align) * values->nsamples);
16790569
AD		 296 break;
297 default:
298 return -EINVAL;
299 }
300
301 return 0;
302}
303
961fb597
JG		 304static void r600_cs_track_init(struct r600_cs_track *track)
305{
306 int i;
307
5f77df36
AD		 308 /* assume DX9 mode */
309 track->sq_config = DX9_CONSTS;
961fb597
JG		 310 for (i = 0; i < 8; i++) {
311 track->cb_color_base_last[i] = 0;
312 track->cb_color_size[i] = 0;
313 track->cb_color_size_idx[i] = 0;
314 track->cb_color_info[i] = 0;
285484e2 315 track->cb_color_view[i] = 0xFFFFFFFF;
961fb597
JG		 316 track->cb_color_bo[i] = NULL;
317 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
16790569 318 track->cb_color_bo_mc[i] = 0xFFFFFFFF;
3b5ef597
MO		 319 track->cb_color_frag_bo[i] = NULL;
320 track->cb_color_frag_offset[i] = 0xFFFFFFFF;
321 track->cb_color_tile_bo[i] = NULL;
322 track->cb_color_tile_offset[i] = 0xFFFFFFFF;
323 track->cb_color_mask[i] = 0xFFFFFFFF;
961fb597 324 }
523885de 325 track->is_resolve = false;
3b5ef597
MO		 326 track->nsamples = 16;
327 track->log_nsamples = 4;
961fb597
JG		 328 track->cb_target_mask = 0xFFFFFFFF;
329 track->cb_shader_mask = 0xFFFFFFFF;
3c12513d 330 track->cb_dirty = true;
961fb597 331 track->db_bo = NULL;
16790569 332 track->db_bo_mc = 0xFFFFFFFF;
961fb597
JG		 333 /* assume the biggest format and that htile is enabled */
334 track->db_depth_info = 7 | (1 << 25);
335 track->db_depth_view = 0xFFFFC000;
336 track->db_depth_size = 0xFFFFFFFF;
337 track->db_depth_size_idx = 0;
338 track->db_depth_control = 0xFFFFFFFF;
3c12513d 339 track->db_dirty = true;
88f50c80
JG		 340 track->htile_bo = NULL;
341 track->htile_offset = 0xFFFFFFFF;
342 track->htile_surface = 0;
dd220a00
MO		 343
344 for (i = 0; i < 4; i++) {
345 track->vgt_strmout_size[i] = 0;
346 track->vgt_strmout_bo[i] = NULL;
347 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
348 track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF;
349 }
3c12513d 350 track->streamout_dirty = true;
779923bc 351 track->sx_misc_kill_all_prims = false;
961fb597
JG		 352}
353
488479eb 354static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
961fb597
JG		 355{
356 struct r600_cs_track *track = p->track;
60b212f8 357 u32 slice_tile_max, size, tmp;
16790569
AD		 358 u32 height, height_align, pitch, pitch_align, depth_align;
359 u64 base_offset, base_align;
360 struct array_mode_checker array_check;
f2e39221 361 volatile u32 *ib = p->ib.ptr;
f30df2fa 362 unsigned array_mode;
60b212f8 363 u32 format;
523885de
MO		 364 /* When resolve is used, the second colorbuffer has always 1 sample. */
365 unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples;
285484e2 366
1729dd33 367 size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
60b212f8 368 format = G_0280A0_FORMAT(track->cb_color_info[i]);
285484e2 369 if (!r600_fmt_is_valid_color(format)) {
961fb597 370 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
60b212f8 371 __func__, __LINE__, format,
961fb597
JG		 372 i, track->cb_color_info[i]);
373 return -EINVAL;
374 }
16790569
AD		 375 /* pitch in pixels */
376 pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8;
961fb597 377 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
f30df2fa 378 slice_tile_max *= 64;
16790569 379 height = slice_tile_max / pitch;
961fb597
JG		 380 if (height > 8192)
381 height = 8192;
f30df2fa 382 array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
16790569
AD		 383
384 base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i];
385 array_check.array_mode = array_mode;
386 array_check.group_size = track->group_size;
387 array_check.nbanks = track->nbanks;
388 array_check.npipes = track->npipes;
523885de 389 array_check.nsamples = nsamples;
285484e2 390 array_check.blocksize = r600_fmt_get_blocksize(format);
16790569
AD		 391 if (r600_get_array_mode_alignment(&array_check,
392 &pitch_align, &height_align, &depth_align, &base_align)) {
393 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
394 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
395 track->cb_color_info[i]);
396 return -EINVAL;
397 }
f30df2fa 398 switch (array_mode) {
961fb597 399 case V_0280A0_ARRAY_LINEAR_GENERAL:
40e2a5c1 400 break;
961fb597 401 case V_0280A0_ARRAY_LINEAR_ALIGNED:
961fb597
JG		 402 break;
403 case V_0280A0_ARRAY_1D_TILED_THIN1:
8f895da5
AD		 404 /* avoid breaking userspace */
405 if (height > 7)
406 height &= ~0x7;
961fb597
JG		 407 break;
408 case V_0280A0_ARRAY_2D_TILED_THIN1:
961fb597
JG		 409 break;
410 default:
411 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
412 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
413 track->cb_color_info[i]);
414 return -EINVAL;
415 }
16790569
AD		 416
417 if (!IS_ALIGNED(pitch, pitch_align)) {
c2049b3d
AD		 418 dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n",
419 __func__, __LINE__, pitch, pitch_align, array_mode);
16790569
AD		 420 return -EINVAL;
421 }
422 if (!IS_ALIGNED(height, height_align)) {
c2049b3d
AD		 423 dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n",
424 __func__, __LINE__, height, height_align, array_mode);
16790569
AD		 425 return -EINVAL;
426 }
427 if (!IS_ALIGNED(base_offset, base_align)) {
c2049b3d
AD		 428 dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i,
429 base_offset, base_align, array_mode);
16790569
AD		 430 return -EINVAL;
431 }
432
961fb597 433 /* check offset */
fcdeefe4 434 tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) *
523885de 435 r600_fmt_get_blocksize(format) * nsamples;
285484e2
JG		 436 switch (array_mode) {
437 default:
438 case V_0280A0_ARRAY_LINEAR_GENERAL:
439 case V_0280A0_ARRAY_LINEAR_ALIGNED:
440 tmp += track->cb_color_view[i] & 0xFF;
441 break;
442 case V_0280A0_ARRAY_1D_TILED_THIN1:
443 case V_0280A0_ARRAY_2D_TILED_THIN1:
444 tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp;
445 break;
446 }
961fb597 447 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
f30df2fa
DA		 448 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
449 /* the initial DDX does bad things with the CB size occasionally */
450 /* it rounds up height too far for slice tile max but the BO is smaller */
a1a82133
AD		 451 /* r600c,g also seem to flush at bad times in some apps resulting in
452 * bogus values here. So for linear just allow anything to avoid breaking
453 * broken userspace.
454 */
f30df2fa 455 } else {
c116cc94 456 dev_warn(p->dev, "%s offset[%d] %d %llu %d %lu too big (%d %d) (%d %d %d)\n",
285484e2 457 __func__, i, array_mode,
c2049b3d 458 track->cb_color_bo_offset[i], tmp,
285484e2
JG		 459 radeon_bo_size(track->cb_color_bo[i]),
460 pitch, height, r600_fmt_get_nblocksx(format, pitch),
461 r600_fmt_get_nblocksy(format, height),
462 r600_fmt_get_blocksize(format));
f30df2fa
DA		 463 return -EINVAL;
464 }
40e2a5c1 465 }
961fb597 466 /* limit max tile */
16790569 467 tmp = (height * pitch) >> 6;
961fb597
JG		 468 if (tmp < slice_tile_max)
469 slice_tile_max = tmp;
16790569 470 tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
961fb597
JG		 471 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
472 ib[track->cb_color_size_idx[i]] = tmp;
c116cc94
MO		 473
474 /* FMASK/CMASK */
475 switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
476 case V_0280A0_TILE_DISABLE:
477 break;
478 case V_0280A0_FRAG_ENABLE:
479 if (track->nsamples > 1) {
480 uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]);
481 /* the tile size is 8x8, but the size is in units of bits.
482 * for bytes, do just * 8. */
483 uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1);
484
485 if (bytes + track->cb_color_frag_offset[i] >
486 radeon_bo_size(track->cb_color_frag_bo[i])) {
487 dev_warn(p->dev, "%s FMASK_TILE_MAX too large "
488 "(tile_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
489 __func__, tile_max, bytes,
490 track->cb_color_frag_offset[i],
491 radeon_bo_size(track->cb_color_frag_bo[i]));
492 return -EINVAL;
493 }
494 }
495 /* fall through */
496 case V_0280A0_CLEAR_ENABLE:
497 {
498 uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]);
499 /* One block = 128x128 pixels, one 8x8 tile has 4 bits..
500 * (128*128) / (8*8) / 2 = 128 bytes per block. */
501 uint32_t bytes = (block_max + 1) * 128;
502
503 if (bytes + track->cb_color_tile_offset[i] >
504 radeon_bo_size(track->cb_color_tile_bo[i])) {
505 dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large "
506 "(block_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
507 __func__, block_max, bytes,
508 track->cb_color_tile_offset[i],
509 radeon_bo_size(track->cb_color_tile_bo[i]));
510 return -EINVAL;
511 }
512 break;
513 }
514 default:
515 dev_warn(p->dev, "%s invalid tile mode\n", __func__);
516 return -EINVAL;
517 }
961fb597
JG		 518 return 0;
519}
520
88f50c80
JG		 521static int r600_cs_track_validate_db(struct radeon_cs_parser *p)
522{
523 struct r600_cs_track *track = p->track;
524 u32 nviews, bpe, ntiles, size, slice_tile_max, tmp;
525 u32 height_align, pitch_align, depth_align;
526 u32 pitch = 8192;
527 u32 height = 8192;
528 u64 base_offset, base_align;
529 struct array_mode_checker array_check;
530 int array_mode;
f2e39221 531 volatile u32 *ib = p->ib.ptr;
88f50c80
JG		 532
533
534 if (track->db_bo == NULL) {
535 dev_warn(p->dev, "z/stencil with no depth buffer\n");
536 return -EINVAL;
537 }
538 switch (G_028010_FORMAT(track->db_depth_info)) {
539 case V_028010_DEPTH_16:
540 bpe = 2;
541 break;
542 case V_028010_DEPTH_X8_24:
543 case V_028010_DEPTH_8_24:
544 case V_028010_DEPTH_X8_24_FLOAT:
545 case V_028010_DEPTH_8_24_FLOAT:
546 case V_028010_DEPTH_32_FLOAT:
547 bpe = 4;
548 break;
549 case V_028010_DEPTH_X24_8_32_FLOAT:
550 bpe = 8;
551 break;
552 default:
553 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
554 return -EINVAL;
555 }
556 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
557 if (!track->db_depth_size_idx) {
558 dev_warn(p->dev, "z/stencil buffer size not set\n");
559 return -EINVAL;
560 }
561 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
562 tmp = (tmp / bpe) >> 6;
563 if (!tmp) {
564 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
565 track->db_depth_size, bpe, track->db_offset,
566 radeon_bo_size(track->db_bo));
567 return -EINVAL;
568 }
569 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
570 } else {
571 size = radeon_bo_size(track->db_bo);
572 /* pitch in pixels */
573 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
574 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
575 slice_tile_max *= 64;
576 height = slice_tile_max / pitch;
577 if (height > 8192)
578 height = 8192;
579 base_offset = track->db_bo_mc + track->db_offset;
580 array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
581 array_check.array_mode = array_mode;
582 array_check.group_size = track->group_size;
583 array_check.nbanks = track->nbanks;
584 array_check.npipes = track->npipes;
585 array_check.nsamples = track->nsamples;
586 array_check.blocksize = bpe;
587 if (r600_get_array_mode_alignment(&array_check,
588 &pitch_align, &height_align, &depth_align, &base_align)) {
589 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
590 G_028010_ARRAY_MODE(track->db_depth_info),
591 track->db_depth_info);
592 return -EINVAL;
593 }
594 switch (array_mode) {
595 case V_028010_ARRAY_1D_TILED_THIN1:
596 /* don't break userspace */
597 height &= ~0x7;
598 break;
599 case V_028010_ARRAY_2D_TILED_THIN1:
600 break;
601 default:
602 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
603 G_028010_ARRAY_MODE(track->db_depth_info),
604 track->db_depth_info);
605 return -EINVAL;
606 }
607
608 if (!IS_ALIGNED(pitch, pitch_align)) {
609 dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",
610 __func__, __LINE__, pitch, pitch_align, array_mode);
611 return -EINVAL;
612 }
613 if (!IS_ALIGNED(height, height_align)) {
614 dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n",
615 __func__, __LINE__, height, height_align, array_mode);
616 return -EINVAL;
617 }
618 if (!IS_ALIGNED(base_offset, base_align)) {
619 dev_warn(p->dev, "%s offset 0x%llx, 0x%llx, %d not aligned\n", __func__,
620 base_offset, base_align, array_mode);
621 return -EINVAL;
622 }
623
624 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
625 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
fcdeefe4 626 tmp = ntiles * bpe * 64 * nviews * track->nsamples;
88f50c80
JG		 627 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
628 dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
629 array_mode,
630 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
631 radeon_bo_size(track->db_bo));
632 return -EINVAL;
633 }
634 }
635
636 /* hyperz */
637 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
638 unsigned long size;
639 unsigned nbx, nby;
640
641 if (track->htile_bo == NULL) {
642 dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n",
643 __func__, __LINE__, track->db_depth_info);
644 return -EINVAL;
645 }
646 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
647 dev_warn(p->dev, "%s:%d htile can't be enabled with bogus db_depth_size 0x%08x\n",
648 __func__, __LINE__, track->db_depth_size);
649 return -EINVAL;
650 }
651
652 nbx = pitch;
653 nby = height;
654 if (G_028D24_LINEAR(track->htile_surface)) {
655 /* nbx must be 16 htiles aligned == 16 * 8 pixel aligned */
656 nbx = round_up(nbx, 16 * 8);
657 /* nby is npipes htiles aligned == npipes * 8 pixel aligned */
658 nby = round_up(nby, track->npipes * 8);
659 } else {
4ac0533a 660 /* always assume 8x8 htile */
88f50c80
JG		 661 /* align is htile align * 8, htile align vary according to
662 * number of pipe and tile width and nby
663 */
664 switch (track->npipes) {
665 case 8:
4ac0533a
JG		 666 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
667 nbx = round_up(nbx, 64 * 8);
668 nby = round_up(nby, 64 * 8);
88f50c80
JG		 669 break;
670 case 4:
4ac0533a
JG		 671 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
672 nbx = round_up(nbx, 64 * 8);
673 nby = round_up(nby, 32 * 8);
88f50c80
JG		 674 break;
675 case 2:
4ac0533a
JG		 676 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
677 nbx = round_up(nbx, 32 * 8);
678 nby = round_up(nby, 32 * 8);
88f50c80
JG		 679 break;
680 case 1:
4ac0533a
JG		 681 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
682 nbx = round_up(nbx, 32 * 8);
683 nby = round_up(nby, 16 * 8);
88f50c80
JG		 684 break;
685 default:
686 dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
687 __func__, __LINE__, track->npipes);
688 return -EINVAL;
689 }
690 }
691 /* compute number of htile */
4ac0533a
JG		 692 nbx = nbx >> 3;
693 nby = nby >> 3;
694 /* size must be aligned on npipes * 2K boundary */
695 size = roundup(nbx * nby * 4, track->npipes * (2 << 10));
88f50c80
JG		 696 size += track->htile_offset;
697
698 if (size > radeon_bo_size(track->htile_bo)) {
699 dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n",
700 __func__, __LINE__, radeon_bo_size(track->htile_bo),
701 size, nbx, nby);
702 return -EINVAL;
703 }
704 }
705
706 track->db_dirty = false;
707 return 0;
708}
709
961fb597
JG		 710static int r600_cs_track_check(struct radeon_cs_parser *p)
711{
712 struct r600_cs_track *track = p->track;
713 u32 tmp;
714 int r, i;
961fb597
JG		 715
716 /* on legacy kernel we don't perform advanced check */
717 if (p->rdev == NULL)
718 return 0;
dd220a00
MO		 719
720 /* check streamout */
3c12513d 721 if (track->streamout_dirty && track->vgt_strmout_en) {
dd220a00
MO		 722 for (i = 0; i < 4; i++) {
723 if (track->vgt_strmout_buffer_en & (1 << i)) {
724 if (track->vgt_strmout_bo[i]) {
725 u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
726 (u64)track->vgt_strmout_size[i];
727 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
728 DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n",
729 i, offset,
730 radeon_bo_size(track->vgt_strmout_bo[i]));
731 return -EINVAL;
732 }
733 } else {
734 dev_warn(p->dev, "No buffer for streamout %d\n", i);
735 return -EINVAL;
736 }
737 }
738 }
3c12513d 739 track->streamout_dirty = false;
961fb597 740 }
dd220a00 741
779923bc
MO		 742 if (track->sx_misc_kill_all_prims)
743 return 0;
744
961fb597
JG		 745 /* check that we have a cb for each enabled target, we don't check
746 * shader_mask because it seems mesa isn't always setting it :(
747 */
3c12513d
MO		 748 if (track->cb_dirty) {
749 tmp = track->cb_target_mask;
523885de
MO		 750
751 /* We must check both colorbuffers for RESOLVE. */
752 if (track->is_resolve) {
753 tmp |= 0xff;
754 }
755
3c12513d
MO		 756 for (i = 0; i < 8; i++) {
757 if ((tmp >> (i * 4)) & 0xF) {
758 /* at least one component is enabled */
759 if (track->cb_color_bo[i] == NULL) {
760 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
761 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
762 return -EINVAL;
763 }
764 /* perform rewrite of CB_COLOR[0-7]_SIZE */
765 r = r600_cs_track_validate_cb(p, i);
766 if (r)
767 return r;
961fb597 768 }
961fb597 769 }
3c12513d 770 track->cb_dirty = false;
961fb597 771 }
3c12513d 772
88f50c80 773 /* Check depth buffer */
0f457e48
MO		 774 if (track->db_dirty &&
775 G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID &&
776 (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
777 G_028800_Z_ENABLE(track->db_depth_control))) {
88f50c80
JG		 778 r = r600_cs_track_validate_db(p);
779 if (r)
780 return r;
961fb597 781 }
88f50c80 782
961fb597
JG		 783 return 0;
784}
785
3ce0a23d
JG		 786/**
787 * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
788 * @parser: parser structure holding parsing context.
789 * @data: pointer to relocation data
790 * @offset_start: starting offset
791 * @offset_mask: offset mask (to align start offset on)
792 * @reloc: reloc informations
793 *
794 * Check next packet is relocation packet3, do bo validation and compute
795 * GPU offset using the provided start.
796 **/
797static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
798 struct radeon_cs_reloc **cs_reloc)
799{
3ce0a23d
JG		 800 struct radeon_cs_chunk *relocs_chunk;
801 struct radeon_cs_packet p3reloc;
802 unsigned idx;
803 int r;
804
805 if (p->chunk_relocs_idx == -1) {
806 DRM_ERROR("No relocation chunk !\n");
807 return -EINVAL;
808 }
809 *cs_reloc = NULL;
3ce0a23d 810 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
c38f34b5 811 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
3ce0a23d
JG		 812 if (r) {
813 return r;
814 }
815 p->idx += p3reloc.count + 2;
816 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
817 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
818 p3reloc.idx);
819 return -EINVAL;
820 }
513bcb46 821 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
3ce0a23d
JG		 822 if (idx >= relocs_chunk->length_dw) {
823 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
824 idx, relocs_chunk->length_dw);
825 return -EINVAL;
826 }
827 /* FIXME: we assume reloc size is 4 dwords */
828 *cs_reloc = p->relocs_ptr[(idx / 4)];
829 return 0;
830}
831
832/**
833 * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
834 * @parser: parser structure holding parsing context.
835 * @data: pointer to relocation data
836 * @offset_start: starting offset
837 * @offset_mask: offset mask (to align start offset on)
838 * @reloc: reloc informations
839 *
840 * Check next packet is relocation packet3, do bo validation and compute
841 * GPU offset using the provided start.
842 **/
843static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
844 struct radeon_cs_reloc **cs_reloc)
845{
3ce0a23d
JG		 846 struct radeon_cs_chunk *relocs_chunk;
847 struct radeon_cs_packet p3reloc;
848 unsigned idx;
849 int r;
850
851 if (p->chunk_relocs_idx == -1) {
852 DRM_ERROR("No relocation chunk !\n");
853 return -EINVAL;
854 }
855 *cs_reloc = NULL;
3ce0a23d 856 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
c38f34b5 857 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
3ce0a23d
JG		 858 if (r) {
859 return r;
860 }
861 p->idx += p3reloc.count + 2;
862 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
863 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
864 p3reloc.idx);
865 return -EINVAL;
866 }
513bcb46 867 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
3ce0a23d
JG		 868 if (idx >= relocs_chunk->length_dw) {
869 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
870 idx, relocs_chunk->length_dw);
871 return -EINVAL;
872 }
e265f39e 873 *cs_reloc = p->relocs;
3ce0a23d
JG		 874 (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
875 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
876 return 0;
877}
878
2f67c6e0
AD		 879/**
880 * r600_cs_packet_next_vline() - parse userspace VLINE packet
881 * @parser: parser structure holding parsing context.
882 *
883 * Userspace sends a special sequence for VLINE waits.
884 * PACKET0 - VLINE_START_END + value
885 * PACKET3 - WAIT_REG_MEM poll vline status reg
886 * RELOC (P3) - crtc_id in reloc.
887 *
888 * This function parses this and relocates the VLINE START END
889 * and WAIT_REG_MEM packets to the correct crtc.
890 * It also detects a switched off crtc and nulls out the
891 * wait in that case.
892 */
893static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
894{
895 struct drm_mode_object *obj;
896 struct drm_crtc *crtc;
897 struct radeon_crtc *radeon_crtc;
898 struct radeon_cs_packet p3reloc, wait_reg_mem;
899 int crtc_id;
900 int r;
901 uint32_t header, h_idx, reg, wait_reg_mem_info;
902 volatile uint32_t *ib;
903
f2e39221 904 ib = p->ib.ptr;
2f67c6e0
AD		 905
906 /* parse the WAIT_REG_MEM */
c38f34b5 907 r = radeon_cs_packet_parse(p, &wait_reg_mem, p->idx);
2f67c6e0
AD		 908 if (r)
909 return r;
910
911 /* check its a WAIT_REG_MEM */
912 if (wait_reg_mem.type != PACKET_TYPE3 ||
913 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
914 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
a3a88a66 915 return -EINVAL;
2f67c6e0
AD		 916 }
917
918 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
919 /* bit 4 is reg (0) or mem (1) */
920 if (wait_reg_mem_info & 0x10) {
921 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
a3a88a66 922 return -EINVAL;
2f67c6e0
AD		 923 }
924 /* waiting for value to be equal */
925 if ((wait_reg_mem_info & 0x7) != 0x3) {
926 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
a3a88a66 927 return -EINVAL;
2f67c6e0
AD		 928 }
929 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
930 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
a3a88a66 931 return -EINVAL;
2f67c6e0
AD		 932 }
933
934 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
935 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
a3a88a66 936 return -EINVAL;
2f67c6e0
AD		 937 }
938
939 /* jump over the NOP */
c38f34b5 940 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
2f67c6e0
AD		 941 if (r)
942 return r;
943
944 h_idx = p->idx - 2;
945 p->idx += wait_reg_mem.count + 2;
946 p->idx += p3reloc.count + 2;
947
948 header = radeon_get_ib_value(p, h_idx);
949 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
d4ac6a05 950 reg = CP_PACKET0_GET_REG(header);
29508eb6 951
2f67c6e0
AD		 952 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
953 if (!obj) {
954 DRM_ERROR("cannot find crtc %d\n", crtc_id);
a3a88a66 955 return -EINVAL;
2f67c6e0
AD		 956 }
957 crtc = obj_to_crtc(obj);
958 radeon_crtc = to_radeon_crtc(crtc);
959 crtc_id = radeon_crtc->crtc_id;
960
961 if (!crtc->enabled) {
962 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
963 ib[h_idx + 2] = PACKET2(0);
964 ib[h_idx + 3] = PACKET2(0);
965 ib[h_idx + 4] = PACKET2(0);
966 ib[h_idx + 5] = PACKET2(0);
967 ib[h_idx + 6] = PACKET2(0);
968 ib[h_idx + 7] = PACKET2(0);
969 ib[h_idx + 8] = PACKET2(0);
970 } else if (crtc_id == 1) {
971 switch (reg) {
972 case AVIVO_D1MODE_VLINE_START_END:
973 header &= ~R600_CP_PACKET0_REG_MASK;
974 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
975 break;
976 default:
977 DRM_ERROR("unknown crtc reloc\n");
a3a88a66 978 return -EINVAL;
2f67c6e0
AD		 979 }
980 ib[h_idx] = header;
981 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
982 }
a3a88a66
PB		 983
984 return 0;
2f67c6e0
AD		 985}
986
3ce0a23d
JG		 987static int r600_packet0_check(struct radeon_cs_parser *p,
988 struct radeon_cs_packet *pkt,
989 unsigned idx, unsigned reg)
990{
2f67c6e0
AD		 991 int r;
992
3ce0a23d
JG		 993 switch (reg) {
994 case AVIVO_D1MODE_VLINE_START_END:
2f67c6e0
AD		 995 r = r600_cs_packet_parse_vline(p);
996 if (r) {
997 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
998 idx, reg);
999 return r;
1000 }
3ce0a23d
JG		 1001 break;
1002 default:
1003 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1004 reg, idx);
1005 return -EINVAL;
1006 }
1007 return 0;
1008}
1009
1010static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
1011 struct radeon_cs_packet *pkt)
1012{
1013 unsigned reg, i;
1014 unsigned idx;
1015 int r;
1016
1017 idx = pkt->idx + 1;
1018 reg = pkt->reg;
1019 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
1020 r = r600_packet0_check(p, pkt, idx, reg);
1021 if (r) {
1022 return r;
1023 }
1024 }
1025 return 0;
1026}
1027
961fb597
JG		 1028/**
1029 * r600_cs_check_reg() - check if register is authorized or not
1030 * @parser: parser structure holding parsing context
1031 * @reg: register we are testing
1032 * @idx: index into the cs buffer
1033 *
1034 * This function will test against r600_reg_safe_bm and return 0
1035 * if register is safe. If register is not flag as safe this function
1036 * will test it against a list of register needind special handling.
1037 */
488479eb 1038static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
961fb597
JG		 1039{
1040 struct r600_cs_track *track = (struct r600_cs_track *)p->track;
1041 struct radeon_cs_reloc *reloc;
961fb597
JG		 1042 u32 m, i, tmp, *ib;
1043 int r;
1044
1045 i = (reg >> 7);
88498839 1046 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
961fb597
JG		 1047 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1048 return -EINVAL;
1049 }
1050 m = 1 << ((reg >> 2) & 31);
1051 if (!(r600_reg_safe_bm[i] & m))
1052 return 0;
f2e39221 1053 ib = p->ib.ptr;
961fb597 1054 switch (reg) {
25985edc 1055 /* force following reg to 0 in an attempt to disable out buffer
961fb597
JG		 1056 * which will need us to better understand how it works to perform
1057 * security check on it (Jerome)
1058 */
1059 case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
1060 case R_008C44_SQ_ESGS_RING_SIZE:
1061 case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
1062 case R_008C54_SQ_ESTMP_RING_SIZE:
1063 case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
1064 case R_008C74_SQ_FBUF_RING_SIZE:
1065 case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
1066 case R_008C5C_SQ_GSTMP_RING_SIZE:
1067 case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
1068 case R_008C4C_SQ_GSVS_RING_SIZE:
1069 case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
1070 case R_008C6C_SQ_PSTMP_RING_SIZE:
1071 case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
1072 case R_008C7C_SQ_REDUC_RING_SIZE:
1073 case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
1074 case R_008C64_SQ_VSTMP_RING_SIZE:
1075 case R_0288C8_SQ_GS_VERT_ITEMSIZE:
1076 /* get value to populate the IB don't remove */
1077 tmp =radeon_get_ib_value(p, idx);
1078 ib[idx] = 0;
1079 break;
5f77df36
AD		 1080 case SQ_CONFIG:
1081 track->sq_config = radeon_get_ib_value(p, idx);
1082 break;
961fb597
JG		 1083 case R_028800_DB_DEPTH_CONTROL:
1084 track->db_depth_control = radeon_get_ib_value(p, idx);
3c12513d 1085 track->db_dirty = true;
961fb597
JG		 1086 break;
1087 case R_028010_DB_DEPTH_INFO:
721604a1 1088 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
9ffb7a6d 1089 radeon_cs_packet_next_is_pkt3_nop(p)) {
7f813377
AD		 1090 r = r600_cs_packet_next_reloc(p, &reloc);
1091 if (r) {
1092 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1093 "0x%04X\n", reg);
1094 return -EINVAL;
1095 }
1096 track->db_depth_info = radeon_get_ib_value(p, idx);
1097 ib[idx] &= C_028010_ARRAY_MODE;
1098 track->db_depth_info &= C_028010_ARRAY_MODE;
1099 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1100 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1101 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1102 } else {
1103 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1104 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1105 }
3c12513d 1106 } else {
7f813377 1107 track->db_depth_info = radeon_get_ib_value(p, idx);
3c12513d
MO		 1108 }
1109 track->db_dirty = true;
961fb597
JG		 1110 break;
1111 case R_028004_DB_DEPTH_VIEW:
1112 track->db_depth_view = radeon_get_ib_value(p, idx);
3c12513d 1113 track->db_dirty = true;
961fb597
JG		 1114 break;
1115 case R_028000_DB_DEPTH_SIZE:
1116 track->db_depth_size = radeon_get_ib_value(p, idx);
1117 track->db_depth_size_idx = idx;
3c12513d 1118 track->db_dirty = true;
961fb597
JG		 1119 break;
1120 case R_028AB0_VGT_STRMOUT_EN:
1121 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
3c12513d 1122 track->streamout_dirty = true;
961fb597
JG		 1123 break;
1124 case R_028B20_VGT_STRMOUT_BUFFER_EN:
1125 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
3c12513d 1126 track->streamout_dirty = true;
961fb597 1127 break;
dd220a00
MO		 1128 case VGT_STRMOUT_BUFFER_BASE_0:
1129 case VGT_STRMOUT_BUFFER_BASE_1:
1130 case VGT_STRMOUT_BUFFER_BASE_2:
1131 case VGT_STRMOUT_BUFFER_BASE_3:
1132 r = r600_cs_packet_next_reloc(p, &reloc);
1133 if (r) {
1134 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1135 "0x%04X\n", reg);
1136 return -EINVAL;
1137 }
1138 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
1139 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1140 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1141 track->vgt_strmout_bo[tmp] = reloc->robj;
1142 track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset;
3c12513d 1143 track->streamout_dirty = true;
dd220a00
MO		 1144 break;
1145 case VGT_STRMOUT_BUFFER_SIZE_0:
1146 case VGT_STRMOUT_BUFFER_SIZE_1:
1147 case VGT_STRMOUT_BUFFER_SIZE_2:
1148 case VGT_STRMOUT_BUFFER_SIZE_3:
1149 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
1150 /* size in register is DWs, convert to bytes */
1151 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
3c12513d 1152 track->streamout_dirty = true;
dd220a00
MO		 1153 break;
1154 case CP_COHER_BASE:
1155 r = r600_cs_packet_next_reloc(p, &reloc);
1156 if (r) {
1157 dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1158 "0x%04X\n", reg);
1159 return -EINVAL;
1160 }
1161 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1162 break;
961fb597
JG		 1163 case R_028238_CB_TARGET_MASK:
1164 track->cb_target_mask = radeon_get_ib_value(p, idx);
3c12513d 1165 track->cb_dirty = true;
961fb597
JG		 1166 break;
1167 case R_02823C_CB_SHADER_MASK:
1168 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1169 break;
1170 case R_028C04_PA_SC_AA_CONFIG:
1171 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
c116cc94 1172 track->log_nsamples = tmp;
961fb597 1173 track->nsamples = 1 << tmp;
3c12513d 1174 track->cb_dirty = true;
961fb597 1175 break;
523885de
MO		 1176 case R_028808_CB_COLOR_CONTROL:
1177 tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx));
1178 track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX;
1179 track->cb_dirty = true;
1180 break;
961fb597
JG		 1181 case R_0280A0_CB_COLOR0_INFO:
1182 case R_0280A4_CB_COLOR1_INFO:
1183 case R_0280A8_CB_COLOR2_INFO:
1184 case R_0280AC_CB_COLOR3_INFO:
1185 case R_0280B0_CB_COLOR4_INFO:
1186 case R_0280B4_CB_COLOR5_INFO:
1187 case R_0280B8_CB_COLOR6_INFO:
1188 case R_0280BC_CB_COLOR7_INFO:
721604a1 1189 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
9ffb7a6d 1190 radeon_cs_packet_next_is_pkt3_nop(p)) {
7f813377
AD		 1191 r = r600_cs_packet_next_reloc(p, &reloc);
1192 if (r) {
1193 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1194 return -EINVAL;
1195 }
1196 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1197 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1198 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1199 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1200 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1201 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1202 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1203 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1204 }
1205 } else {
1206 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1207 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1208 }
3c12513d 1209 track->cb_dirty = true;
961fb597 1210 break;
285484e2
JG		 1211 case R_028080_CB_COLOR0_VIEW:
1212 case R_028084_CB_COLOR1_VIEW:
1213 case R_028088_CB_COLOR2_VIEW:
1214 case R_02808C_CB_COLOR3_VIEW:
1215 case R_028090_CB_COLOR4_VIEW:
1216 case R_028094_CB_COLOR5_VIEW:
1217 case R_028098_CB_COLOR6_VIEW:
1218 case R_02809C_CB_COLOR7_VIEW:
1219 tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4;
1220 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
3c12513d 1221 track->cb_dirty = true;
285484e2 1222 break;
961fb597
JG		 1223 case R_028060_CB_COLOR0_SIZE:
1224 case R_028064_CB_COLOR1_SIZE:
1225 case R_028068_CB_COLOR2_SIZE:
1226 case R_02806C_CB_COLOR3_SIZE:
1227 case R_028070_CB_COLOR4_SIZE:
1228 case R_028074_CB_COLOR5_SIZE:
1229 case R_028078_CB_COLOR6_SIZE:
1230 case R_02807C_CB_COLOR7_SIZE:
1231 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
1232 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
1233 track->cb_color_size_idx[tmp] = idx;
3c12513d 1234 track->cb_dirty = true;
961fb597
JG		 1235 break;
1236 /* This register were added late, there is userspace
1237 * which does provide relocation for those but set
1238 * 0 offset. In order to avoid breaking old userspace
1239 * we detect this and set address to point to last
1240 * CB_COLOR0_BASE, note that if userspace doesn't set
1241 * CB_COLOR0_BASE before this register we will report
1242 * error. Old userspace always set CB_COLOR0_BASE
1243 * before any of this.
1244 */
1245 case R_0280E0_CB_COLOR0_FRAG:
1246 case R_0280E4_CB_COLOR1_FRAG:
1247 case R_0280E8_CB_COLOR2_FRAG:
1248 case R_0280EC_CB_COLOR3_FRAG:
1249 case R_0280F0_CB_COLOR4_FRAG:
1250 case R_0280F4_CB_COLOR5_FRAG:
1251 case R_0280F8_CB_COLOR6_FRAG:
1252 case R_0280FC_CB_COLOR7_FRAG:
1253 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
9ffb7a6d 1254 if (!radeon_cs_packet_next_is_pkt3_nop(p)) {
961fb597
JG		 1255 if (!track->cb_color_base_last[tmp]) {
1256 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1257 return -EINVAL;
1258 }
961fb597 1259 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
c116cc94
MO		 1260 track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp];
1261 ib[idx] = track->cb_color_base_last[tmp];
961fb597
JG		 1262 } else {
1263 r = r600_cs_packet_next_reloc(p, &reloc);
1264 if (r) {
1265 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1266 return -EINVAL;
1267 }
961fb597 1268 track->cb_color_frag_bo[tmp] = reloc->robj;
c116cc94
MO		 1269 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;
1270 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1271 }
1272 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1273 track->cb_dirty = true;
961fb597
JG		 1274 }
1275 break;
1276 case R_0280C0_CB_COLOR0_TILE:
1277 case R_0280C4_CB_COLOR1_TILE:
1278 case R_0280C8_CB_COLOR2_TILE:
1279 case R_0280CC_CB_COLOR3_TILE:
1280 case R_0280D0_CB_COLOR4_TILE:
1281 case R_0280D4_CB_COLOR5_TILE:
1282 case R_0280D8_CB_COLOR6_TILE:
1283 case R_0280DC_CB_COLOR7_TILE:
1284 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
9ffb7a6d 1285 if (!radeon_cs_packet_next_is_pkt3_nop(p)) {
961fb597
JG		 1286 if (!track->cb_color_base_last[tmp]) {
1287 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1288 return -EINVAL;
1289 }
961fb597 1290 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
c116cc94
MO		 1291 track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp];
1292 ib[idx] = track->cb_color_base_last[tmp];
961fb597
JG		 1293 } else {
1294 r = r600_cs_packet_next_reloc(p, &reloc);
1295 if (r) {
1296 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1297 return -EINVAL;
1298 }
961fb597 1299 track->cb_color_tile_bo[tmp] = reloc->robj;
c116cc94
MO		 1300 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;
1301 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1302 }
1303 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1304 track->cb_dirty = true;
1305 }
1306 break;
1307 case R_028100_CB_COLOR0_MASK:
1308 case R_028104_CB_COLOR1_MASK:
1309 case R_028108_CB_COLOR2_MASK:
1310 case R_02810C_CB_COLOR3_MASK:
1311 case R_028110_CB_COLOR4_MASK:
1312 case R_028114_CB_COLOR5_MASK:
1313 case R_028118_CB_COLOR6_MASK:
1314 case R_02811C_CB_COLOR7_MASK:
1315 tmp = (reg - R_028100_CB_COLOR0_MASK) / 4;
305a3d20 1316 track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);
c116cc94
MO		 1317 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1318 track->cb_dirty = true;
961fb597
JG		 1319 }
1320 break;
1321 case CB_COLOR0_BASE:
1322 case CB_COLOR1_BASE:
1323 case CB_COLOR2_BASE:
1324 case CB_COLOR3_BASE:
1325 case CB_COLOR4_BASE:
1326 case CB_COLOR5_BASE:
1327 case CB_COLOR6_BASE:
1328 case CB_COLOR7_BASE:
1329 r = r600_cs_packet_next_reloc(p, &reloc);
1330 if (r) {
1331 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1332 "0x%04X\n", reg);
1333 return -EINVAL;
1334 }
7cb72ef4 1335 tmp = (reg - CB_COLOR0_BASE) / 4;
1729dd33 1336 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
961fb597 1337 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
961fb597
JG		 1338 track->cb_color_base_last[tmp] = ib[idx];
1339 track->cb_color_bo[tmp] = reloc->robj;
16790569 1340 track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset;
3c12513d 1341 track->cb_dirty = true;
961fb597
JG		 1342 break;
1343 case DB_DEPTH_BASE:
1344 r = r600_cs_packet_next_reloc(p, &reloc);
1345 if (r) {
1346 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1347 "0x%04X\n", reg);
1348 return -EINVAL;
1349 }
1729dd33 1350 track->db_offset = radeon_get_ib_value(p, idx) << 8;
961fb597
JG		 1351 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1352 track->db_bo = reloc->robj;
16790569 1353 track->db_bo_mc = reloc->lobj.gpu_offset;
3c12513d 1354 track->db_dirty = true;
961fb597
JG		 1355 break;
1356 case DB_HTILE_DATA_BASE:
88f50c80
JG		 1357 r = r600_cs_packet_next_reloc(p, &reloc);
1358 if (r) {
1359 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1360 "0x%04X\n", reg);
1361 return -EINVAL;
1362 }
1363 track->htile_offset = radeon_get_ib_value(p, idx) << 8;
1364 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1365 track->htile_bo = reloc->robj;
1366 track->db_dirty = true;
1367 break;
1368 case DB_HTILE_SURFACE:
1369 track->htile_surface = radeon_get_ib_value(p, idx);
4ac0533a
JG		 1370 /* force 8x8 htile width and height */
1371 ib[idx] |= 3;
88f50c80
JG		 1372 track->db_dirty = true;
1373 break;
961fb597
JG		 1374 case SQ_PGM_START_FS:
1375 case SQ_PGM_START_ES:
1376 case SQ_PGM_START_VS:
1377 case SQ_PGM_START_GS:
1378 case SQ_PGM_START_PS:
5f77df36
AD		 1379 case SQ_ALU_CONST_CACHE_GS_0:
1380 case SQ_ALU_CONST_CACHE_GS_1:
1381 case SQ_ALU_CONST_CACHE_GS_2:
1382 case SQ_ALU_CONST_CACHE_GS_3:
1383 case SQ_ALU_CONST_CACHE_GS_4:
1384 case SQ_ALU_CONST_CACHE_GS_5:
1385 case SQ_ALU_CONST_CACHE_GS_6:
1386 case SQ_ALU_CONST_CACHE_GS_7:
1387 case SQ_ALU_CONST_CACHE_GS_8:
1388 case SQ_ALU_CONST_CACHE_GS_9:
1389 case SQ_ALU_CONST_CACHE_GS_10:
1390 case SQ_ALU_CONST_CACHE_GS_11:
1391 case SQ_ALU_CONST_CACHE_GS_12:
1392 case SQ_ALU_CONST_CACHE_GS_13:
1393 case SQ_ALU_CONST_CACHE_GS_14:
1394 case SQ_ALU_CONST_CACHE_GS_15:
1395 case SQ_ALU_CONST_CACHE_PS_0:
1396 case SQ_ALU_CONST_CACHE_PS_1:
1397 case SQ_ALU_CONST_CACHE_PS_2:
1398 case SQ_ALU_CONST_CACHE_PS_3:
1399 case SQ_ALU_CONST_CACHE_PS_4:
1400 case SQ_ALU_CONST_CACHE_PS_5:
1401 case SQ_ALU_CONST_CACHE_PS_6:
1402 case SQ_ALU_CONST_CACHE_PS_7:
1403 case SQ_ALU_CONST_CACHE_PS_8:
1404 case SQ_ALU_CONST_CACHE_PS_9:
1405 case SQ_ALU_CONST_CACHE_PS_10:
1406 case SQ_ALU_CONST_CACHE_PS_11:
1407 case SQ_ALU_CONST_CACHE_PS_12:
1408 case SQ_ALU_CONST_CACHE_PS_13:
1409 case SQ_ALU_CONST_CACHE_PS_14:
1410 case SQ_ALU_CONST_CACHE_PS_15:
1411 case SQ_ALU_CONST_CACHE_VS_0:
1412 case SQ_ALU_CONST_CACHE_VS_1:
1413 case SQ_ALU_CONST_CACHE_VS_2:
1414 case SQ_ALU_CONST_CACHE_VS_3:
1415 case SQ_ALU_CONST_CACHE_VS_4:
1416 case SQ_ALU_CONST_CACHE_VS_5:
1417 case SQ_ALU_CONST_CACHE_VS_6:
1418 case SQ_ALU_CONST_CACHE_VS_7:
1419 case SQ_ALU_CONST_CACHE_VS_8:
1420 case SQ_ALU_CONST_CACHE_VS_9:
1421 case SQ_ALU_CONST_CACHE_VS_10:
1422 case SQ_ALU_CONST_CACHE_VS_11:
1423 case SQ_ALU_CONST_CACHE_VS_12:
1424 case SQ_ALU_CONST_CACHE_VS_13:
1425 case SQ_ALU_CONST_CACHE_VS_14:
1426 case SQ_ALU_CONST_CACHE_VS_15:
961fb597
JG		 1427 r = r600_cs_packet_next_reloc(p, &reloc);
1428 if (r) {
1429 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1430 "0x%04X\n", reg);
1431 return -EINVAL;
033b5650
AD		 1432 }
1433 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1434 break;
1435 case SX_MEMORY_EXPORT_BASE:
1436 r = r600_cs_packet_next_reloc(p, &reloc);
1437 if (r) {
1438 dev_warn(p->dev, "bad SET_CONFIG_REG "
1439 "0x%04X\n", reg);
1440 return -EINVAL;
961fb597
JG		 1441 }
1442 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1443 break;
779923bc
MO		 1444 case SX_MISC:
1445 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1446 break;
961fb597
JG		 1447 default:
1448 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1449 return -EINVAL;
1450 }
1451 return 0;
1452}
1453
285484e2 1454unsigned r600_mip_minify(unsigned size, unsigned level)
961fb597 1455{
60b212f8
DA		 1456 unsigned val;
1457
1458 val = max(1U, size >> level);
1459 if (level > 0)
1460 val = roundup_pow_of_two(val);
1461 return val;
961fb597
JG		 1462}
1463
60b212f8 1464static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
fcdeefe4 1465 unsigned w0, unsigned h0, unsigned d0, unsigned nsamples, unsigned format,
60b212f8 1466 unsigned block_align, unsigned height_align, unsigned base_align,
40e2a5c1 1467 unsigned *l0_size, unsigned *mipmap_size)
961fb597 1468{
60b212f8
DA		 1469 unsigned offset, i, level;
1470 unsigned width, height, depth, size;
1471 unsigned blocksize;
1472 unsigned nbx, nby;
1473 unsigned nlevels = llevel - blevel + 1;
961fb597 1474
60b212f8 1475 *l0_size = -1;
285484e2 1476 blocksize = r600_fmt_get_blocksize(format);
60b212f8 1477
285484e2
JG		 1478 w0 = r600_mip_minify(w0, 0);
1479 h0 = r600_mip_minify(h0, 0);
1480 d0 = r600_mip_minify(d0, 0);
961fb597 1481 for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
285484e2
JG		 1482 width = r600_mip_minify(w0, i);
1483 nbx = r600_fmt_get_nblocksx(format, width);
60b212f8
DA		 1484
1485 nbx = round_up(nbx, block_align);
1486
285484e2
JG		 1487 height = r600_mip_minify(h0, i);
1488 nby = r600_fmt_get_nblocksy(format, height);
60b212f8
DA		 1489 nby = round_up(nby, height_align);
1490
285484e2 1491 depth = r600_mip_minify(d0, i);
60b212f8 1492
fcdeefe4 1493 size = nbx * nby * blocksize * nsamples;
60b212f8
DA		 1494 if (nfaces)
1495 size *= nfaces;
1496 else
1497 size *= depth;
1498
1499 if (i == 0)
1500 *l0_size = size;
1501
1502 if (i == 0 || i == 1)
1503 offset = round_up(offset, base_align);
1504
1505 offset += size;
961fb597 1506 }
961fb597 1507 *mipmap_size = offset;
60b212f8 1508 if (llevel == 0)
961fb597 1509 *mipmap_size = *l0_size;
1729dd33
AD		 1510 if (!blevel)
1511 *mipmap_size -= *l0_size;
961fb597
JG		 1512}
1513
1514/**
1515 * r600_check_texture_resource() - check if register is authorized or not
1516 * @p: parser structure holding parsing context
1517 * @idx: index into the cs buffer
1518 * @texture: texture's bo structure
1519 * @mipmap: mipmap's bo structure
1520 *
1521 * This function will check that the resource has valid field and that
1522 * the texture and mipmap bo object are big enough to cover this resource.
1523 */
488479eb 1524static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
7f813377
AD		 1525 struct radeon_bo *texture,
1526 struct radeon_bo *mipmap,
16790569
AD		 1527 u64 base_offset,
1528 u64 mip_offset,
7f813377 1529 u32 tiling_flags)
961fb597 1530{
40e2a5c1 1531 struct r600_cs_track *track = p->track;
f00245f1
MO		 1532 u32 dim, nfaces, llevel, blevel, w0, h0, d0;
1533 u32 word0, word1, l0_size, mipmap_size, word2, word3, word4, word5;
16790569 1534 u32 height_align, pitch, pitch_align, depth_align;
f00245f1 1535 u32 barray, larray;
16790569
AD		 1536 u64 base_align;
1537 struct array_mode_checker array_check;
60b212f8 1538 u32 format;
f00245f1 1539 bool is_array;
961fb597
JG		 1540
1541 /* on legacy kernel we don't perform advanced check */
1542 if (p->rdev == NULL)
1543 return 0;
7f813377 1544
16790569
AD		 1545 /* convert to bytes */
1546 base_offset <<= 8;
1547 mip_offset <<= 8;
1548
961fb597 1549 word0 = radeon_get_ib_value(p, idx + 0);
721604a1 1550 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
e70f224c
MO		 1551 if (tiling_flags & RADEON_TILING_MACRO)
1552 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1553 else if (tiling_flags & RADEON_TILING_MICRO)
1554 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1555 }
961fb597 1556 word1 = radeon_get_ib_value(p, idx + 1);
f00245f1
MO		 1557 word2 = radeon_get_ib_value(p, idx + 2) << 8;
1558 word3 = radeon_get_ib_value(p, idx + 3) << 8;
1559 word4 = radeon_get_ib_value(p, idx + 4);
1560 word5 = radeon_get_ib_value(p, idx + 5);
1561 dim = G_038000_DIM(word0);
961fb597 1562 w0 = G_038000_TEX_WIDTH(word0) + 1;
f00245f1 1563 pitch = (G_038000_PITCH(word0) + 1) * 8;
961fb597
JG		 1564 h0 = G_038004_TEX_HEIGHT(word1) + 1;
1565 d0 = G_038004_TEX_DEPTH(word1);
f00245f1
MO		 1566 format = G_038004_DATA_FORMAT(word1);
1567 blevel = G_038010_BASE_LEVEL(word4);
1568 llevel = G_038014_LAST_LEVEL(word5);
1569 /* pitch in texels */
1570 array_check.array_mode = G_038000_TILE_MODE(word0);
1571 array_check.group_size = track->group_size;
1572 array_check.nbanks = track->nbanks;
1573 array_check.npipes = track->npipes;
1574 array_check.nsamples = 1;
1575 array_check.blocksize = r600_fmt_get_blocksize(format);
961fb597 1576 nfaces = 1;
f00245f1
MO		 1577 is_array = false;
1578 switch (dim) {
961fb597
JG		 1579 case V_038000_SQ_TEX_DIM_1D:
1580 case V_038000_SQ_TEX_DIM_2D:
1581 case V_038000_SQ_TEX_DIM_3D:
1582 break;
1583 case V_038000_SQ_TEX_DIM_CUBEMAP:
60b212f8
DA		 1584 if (p->family >= CHIP_RV770)
1585 nfaces = 8;
1586 else
1587 nfaces = 6;
961fb597
JG		 1588 break;
1589 case V_038000_SQ_TEX_DIM_1D_ARRAY:
1590 case V_038000_SQ_TEX_DIM_2D_ARRAY:
f00245f1 1591 is_array = true;
60b212f8 1592 break;
961fb597 1593 case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
b51ad12a
MO		 1594 is_array = true;
1595 /* fall through */
1596 case V_038000_SQ_TEX_DIM_2D_MSAA:
1597 array_check.nsamples = 1 << llevel;
1598 llevel = 0;
1599 break;
961fb597
JG		 1600 default:
1601 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1602 return -EINVAL;
1603 }
285484e2 1604 if (!r600_fmt_is_valid_texture(format, p->family)) {
961fb597 1605 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
60b212f8 1606 __func__, __LINE__, format);
961fb597
JG		 1607 return -EINVAL;
1608 }
40e2a5c1 1609
16790569
AD		 1610 if (r600_get_array_mode_alignment(&array_check,
1611 &pitch_align, &height_align, &depth_align, &base_align)) {
1612 dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
1613 __func__, __LINE__, G_038000_TILE_MODE(word0));
1614 return -EINVAL;
1615 }
1616
1617 /* XXX check height as well... */
1618
1619 if (!IS_ALIGNED(pitch, pitch_align)) {
c2049b3d
AD		 1620 dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n",
1621 __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0));
16790569
AD		 1622 return -EINVAL;
1623 }
1624 if (!IS_ALIGNED(base_offset, base_align)) {
c2049b3d
AD		 1625 dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n",
1626 __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0));
16790569
AD		 1627 return -EINVAL;
1628 }
1629 if (!IS_ALIGNED(mip_offset, base_align)) {
c2049b3d
AD		 1630 dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n",
1631 __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0));
40e2a5c1
AD		 1632 return -EINVAL;
1633 }
40e2a5c1 1634
285484e2
JG		 1635 if (blevel > llevel) {
1636 dev_warn(p->dev, "texture blevel %d > llevel %d\n",
1637 blevel, llevel);
1638 }
f00245f1
MO		 1639 if (is_array) {
1640 barray = G_038014_BASE_ARRAY(word5);
1641 larray = G_038014_LAST_ARRAY(word5);
60b212f8
DA		 1642
1643 nfaces = larray - barray + 1;
1644 }
fcdeefe4 1645 r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, array_check.nsamples, format,
60b212f8 1646 pitch_align, height_align, base_align,
40e2a5c1 1647 &l0_size, &mipmap_size);
961fb597 1648 /* using get ib will give us the offset into the texture bo */
af50621a 1649 if ((l0_size + word2) > radeon_bo_size(texture)) {
285484e2
JG		 1650 dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n",
1651 w0, h0, pitch_align, height_align,
1652 array_check.array_mode, format, word2,
1653 l0_size, radeon_bo_size(texture));
60b212f8 1654 dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align);
961fb597
JG		 1655 return -EINVAL;
1656 }
1657 /* using get ib will give us the offset into the mipmap bo */
af50621a 1658 if ((mipmap_size + word3) > radeon_bo_size(mipmap)) {
fe725d4f 1659 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
af50621a 1660 w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/
961fb597
JG		 1661 }
1662 return 0;
1663}
1664
dd220a00
MO		 1665static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1666{
1667 u32 m, i;
1668
1669 i = (reg >> 7);
1670 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
1671 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1672 return false;
1673 }
1674 m = 1 << ((reg >> 2) & 31);
1675 if (!(r600_reg_safe_bm[i] & m))
1676 return true;
1677 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1678 return false;
1679}
1680
3ce0a23d
JG		 1681static int r600_packet3_check(struct radeon_cs_parser *p,
1682 struct radeon_cs_packet *pkt)
1683{
3ce0a23d 1684 struct radeon_cs_reloc *reloc;
c8c15ff1 1685 struct r600_cs_track *track;
3ce0a23d
JG		 1686 volatile u32 *ib;
1687 unsigned idx;
1688 unsigned i;
1689 unsigned start_reg, end_reg, reg;
1690 int r;
adea4796 1691 u32 idx_value;
3ce0a23d 1692
c8c15ff1 1693 track = (struct r600_cs_track *)p->track;
f2e39221 1694 ib = p->ib.ptr;
3ce0a23d 1695 idx = pkt->idx + 1;
adea4796 1696 idx_value = radeon_get_ib_value(p, idx);
513bcb46 1697
3ce0a23d 1698 switch (pkt->opcode) {
2a19cac8
DA		 1699 case PACKET3_SET_PREDICATION:
1700 {
1701 int pred_op;
1702 int tmp;
6333003b
MO		 1703 uint64_t offset;
1704
2a19cac8
DA		 1705 if (pkt->count != 1) {
1706 DRM_ERROR("bad SET PREDICATION\n");
1707 return -EINVAL;
1708 }
1709
1710 tmp = radeon_get_ib_value(p, idx + 1);
1711 pred_op = (tmp >> 16) & 0x7;
1712
1713 /* for the clear predicate operation */
1714 if (pred_op == 0)
1715 return 0;
1716
1717 if (pred_op > 2) {
1718 DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1719 return -EINVAL;
1720 }
1721
1722 r = r600_cs_packet_next_reloc(p, &reloc);
1723 if (r) {
1724 DRM_ERROR("bad SET PREDICATION\n");
1725 return -EINVAL;
1726 }
1727
6333003b
MO		 1728 offset = reloc->lobj.gpu_offset +
1729 (idx_value & 0xfffffff0) +
1730 ((u64)(tmp & 0xff) << 32);
1731
1732 ib[idx + 0] = offset;
1733 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2a19cac8
DA		 1734 }
1735 break;
1736
3ce0a23d
JG		 1737 case PACKET3_START_3D_CMDBUF:
1738 if (p->family >= CHIP_RV770 || pkt->count) {
1739 DRM_ERROR("bad START_3D\n");
1740 return -EINVAL;
1741 }
1742 break;
1743 case PACKET3_CONTEXT_CONTROL:
1744 if (pkt->count != 1) {
1745 DRM_ERROR("bad CONTEXT_CONTROL\n");
1746 return -EINVAL;
1747 }
1748 break;
1749 case PACKET3_INDEX_TYPE:
1750 case PACKET3_NUM_INSTANCES:
1751 if (pkt->count) {
1752 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1753 return -EINVAL;
1754 }
1755 break;
1756 case PACKET3_DRAW_INDEX:
6333003b
MO		 1757 {
1758 uint64_t offset;
3ce0a23d
JG		 1759 if (pkt->count != 3) {
1760 DRM_ERROR("bad DRAW_INDEX\n");
1761 return -EINVAL;
1762 }
1763 r = r600_cs_packet_next_reloc(p, &reloc);
1764 if (r) {
1765 DRM_ERROR("bad DRAW_INDEX\n");
1766 return -EINVAL;
1767 }
6333003b
MO		 1768
1769 offset = reloc->lobj.gpu_offset +
1770 idx_value +
1771 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1772
1773 ib[idx+0] = offset;
1774 ib[idx+1] = upper_32_bits(offset) & 0xff;
1775
961fb597
JG		 1776 r = r600_cs_track_check(p);
1777 if (r) {
1778 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1779 return r;
1780 }
3ce0a23d 1781 break;
6333003b 1782 }
3ce0a23d
JG		 1783 case PACKET3_DRAW_INDEX_AUTO:
1784 if (pkt->count != 1) {
1785 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1786 return -EINVAL;
1787 }
961fb597
JG		 1788 r = r600_cs_track_check(p);
1789 if (r) {
1790 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1791 return r;
1792 }
3ce0a23d
JG		 1793 break;
1794 case PACKET3_DRAW_INDEX_IMMD_BE:
1795 case PACKET3_DRAW_INDEX_IMMD:
1796 if (pkt->count < 2) {
1797 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1798 return -EINVAL;
1799 }
961fb597
JG		 1800 r = r600_cs_track_check(p);
1801 if (r) {
1802 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1803 return r;
1804 }
3ce0a23d
JG		 1805 break;
1806 case PACKET3_WAIT_REG_MEM:
1807 if (pkt->count != 5) {
1808 DRM_ERROR("bad WAIT_REG_MEM\n");
1809 return -EINVAL;
1810 }
1811 /* bit 4 is reg (0) or mem (1) */
adea4796 1812 if (idx_value & 0x10) {
6333003b
MO		 1813 uint64_t offset;
1814
3ce0a23d
JG		 1815 r = r600_cs_packet_next_reloc(p, &reloc);
1816 if (r) {
1817 DRM_ERROR("bad WAIT_REG_MEM\n");
1818 return -EINVAL;
1819 }
6333003b
MO		 1820
1821 offset = reloc->lobj.gpu_offset +
1822 (radeon_get_ib_value(p, idx+1) & 0xfffffff0) +
1823 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1824
1825 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0);
1826 ib[idx+2] = upper_32_bits(offset) & 0xff;
3ce0a23d
JG		 1827 }
1828 break;
6830f585
AD		 1829 case PACKET3_CP_DMA:
1830 {
1831 u32 command, size;
1832 u64 offset, tmp;
1833 if (pkt->count != 4) {
1834 DRM_ERROR("bad CP DMA\n");
1835 return -EINVAL;
1836 }
1837 command = radeon_get_ib_value(p, idx+4);
1838 size = command & 0x1fffff;
1839 if (command & PACKET3_CP_DMA_CMD_SAS) {
1840 /* src address space is register */
1841 DRM_ERROR("CP DMA SAS not supported\n");
1842 return -EINVAL;
1843 } else {
1844 if (command & PACKET3_CP_DMA_CMD_SAIC) {
1845 DRM_ERROR("CP DMA SAIC only supported for registers\n");
1846 return -EINVAL;
1847 }
1848 /* src address space is memory */
1849 r = r600_cs_packet_next_reloc(p, &reloc);
1850 if (r) {
1851 DRM_ERROR("bad CP DMA SRC\n");
1852 return -EINVAL;
1853 }
1854
1855 tmp = radeon_get_ib_value(p, idx) +
1856 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1857
1858 offset = reloc->lobj.gpu_offset + tmp;
1859
1860 if ((tmp + size) > radeon_bo_size(reloc->robj)) {
1861 dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n",
1862 tmp + size, radeon_bo_size(reloc->robj));
1863 return -EINVAL;
1864 }
1865
1866 ib[idx] = offset;
1867 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1868 }
1869 if (command & PACKET3_CP_DMA_CMD_DAS) {
1870 /* dst address space is register */
1871 DRM_ERROR("CP DMA DAS not supported\n");
1872 return -EINVAL;
1873 } else {
1874 /* dst address space is memory */
1875 if (command & PACKET3_CP_DMA_CMD_DAIC) {
1876 DRM_ERROR("CP DMA DAIC only supported for registers\n");
1877 return -EINVAL;
1878 }
1879 r = r600_cs_packet_next_reloc(p, &reloc);
1880 if (r) {
1881 DRM_ERROR("bad CP DMA DST\n");
1882 return -EINVAL;
1883 }
1884
1885 tmp = radeon_get_ib_value(p, idx+2) +
1886 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);
1887
1888 offset = reloc->lobj.gpu_offset + tmp;
1889
1890 if ((tmp + size) > radeon_bo_size(reloc->robj)) {
1891 dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n",
1892 tmp + size, radeon_bo_size(reloc->robj));
1893 return -EINVAL;
1894 }
1895
1896 ib[idx+2] = offset;
1897 ib[idx+3] = upper_32_bits(offset) & 0xff;
1898 }
1899 break;
1900 }
3ce0a23d
JG		 1901 case PACKET3_SURFACE_SYNC:
1902 if (pkt->count != 3) {
1903 DRM_ERROR("bad SURFACE_SYNC\n");
1904 return -EINVAL;
1905 }
1906 /* 0xffffffff/0x0 is flush all cache flag */
513bcb46
DA		 1907 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1908 radeon_get_ib_value(p, idx + 2) != 0) {
3ce0a23d
JG		 1909 r = r600_cs_packet_next_reloc(p, &reloc);
1910 if (r) {
1911 DRM_ERROR("bad SURFACE_SYNC\n");
1912 return -EINVAL;
1913 }
1914 ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1915 }
1916 break;
1917 case PACKET3_EVENT_WRITE:
1918 if (pkt->count != 2 && pkt->count != 0) {
1919 DRM_ERROR("bad EVENT_WRITE\n");
1920 return -EINVAL;
1921 }
1922 if (pkt->count) {
6333003b
MO		 1923 uint64_t offset;
1924
3ce0a23d
JG		 1925 r = r600_cs_packet_next_reloc(p, &reloc);
1926 if (r) {
1927 DRM_ERROR("bad EVENT_WRITE\n");
1928 return -EINVAL;
1929 }
6333003b
MO		 1930 offset = reloc->lobj.gpu_offset +
1931 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
1932 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1933
1934 ib[idx+1] = offset & 0xfffffff8;
1935 ib[idx+2] = upper_32_bits(offset) & 0xff;
3ce0a23d
JG		 1936 }
1937 break;
1938 case PACKET3_EVENT_WRITE_EOP:
6333003b
MO		 1939 {
1940 uint64_t offset;
1941
3ce0a23d
JG		 1942 if (pkt->count != 4) {
1943 DRM_ERROR("bad EVENT_WRITE_EOP\n");
1944 return -EINVAL;
1945 }
1946 r = r600_cs_packet_next_reloc(p, &reloc);
1947 if (r) {
1948 DRM_ERROR("bad EVENT_WRITE\n");
1949 return -EINVAL;
1950 }
6333003b
MO		 1951
1952 offset = reloc->lobj.gpu_offset +
1953 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
1954 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1955
1956 ib[idx+1] = offset & 0xfffffffc;
1957 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
3ce0a23d 1958 break;
6333003b 1959 }
3ce0a23d 1960 case PACKET3_SET_CONFIG_REG:
adea4796 1961 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
3ce0a23d
JG		 1962 end_reg = 4 * pkt->count + start_reg - 4;
1963 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
1964 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1965 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1966 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1967 return -EINVAL;
1968 }
1969 for (i = 0; i < pkt->count; i++) {
1970 reg = start_reg + (4 * i);
961fb597
JG		 1971 r = r600_cs_check_reg(p, reg, idx+1+i);
1972 if (r)
1973 return r;
3ce0a23d
JG		 1974 }
1975 break;
1976 case PACKET3_SET_CONTEXT_REG:
adea4796 1977 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
3ce0a23d
JG		 1978 end_reg = 4 * pkt->count + start_reg - 4;
1979 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
1980 (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
1981 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
1982 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
1983 return -EINVAL;
1984 }
1985 for (i = 0; i < pkt->count; i++) {
1986 reg = start_reg + (4 * i);
961fb597
JG		 1987 r = r600_cs_check_reg(p, reg, idx+1+i);
1988 if (r)
1989 return r;
3ce0a23d
JG		 1990 }
1991 break;
1992 case PACKET3_SET_RESOURCE:
1993 if (pkt->count % 7) {
1994 DRM_ERROR("bad SET_RESOURCE\n");
1995 return -EINVAL;
1996 }
adea4796 1997 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
3ce0a23d
JG		 1998 end_reg = 4 * pkt->count + start_reg - 4;
1999 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
2000 (start_reg >= PACKET3_SET_RESOURCE_END) ||
2001 (end_reg >= PACKET3_SET_RESOURCE_END)) {
2002 DRM_ERROR("bad SET_RESOURCE\n");
2003 return -EINVAL;
2004 }
2005 for (i = 0; i < (pkt->count / 7); i++) {
961fb597 2006 struct radeon_bo *texture, *mipmap;
1729dd33 2007 u32 size, offset, base_offset, mip_offset;
961fb597 2008
adea4796 2009 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
3ce0a23d
JG		 2010 case SQ_TEX_VTX_VALID_TEXTURE:
2011 /* tex base */
2012 r = r600_cs_packet_next_reloc(p, &reloc);
2013 if (r) {
2014 DRM_ERROR("bad SET_RESOURCE\n");
2015 return -EINVAL;
2016 }
1729dd33 2017 base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
721604a1 2018 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
e70f224c
MO		 2019 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
2020 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
2021 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
2022 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
2023 }
961fb597 2024 texture = reloc->robj;
3ce0a23d
JG		 2025 /* tex mip base */
2026 r = r600_cs_packet_next_reloc(p, &reloc);
2027 if (r) {
2028 DRM_ERROR("bad SET_RESOURCE\n");
2029 return -EINVAL;
2030 }
1729dd33 2031 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
961fb597
JG		 2032 mipmap = reloc->robj;
2033 r = r600_check_texture_resource(p, idx+(i*7)+1,
16790569
AD		 2034 texture, mipmap,
2035 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),
2036 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),
2037 reloc->lobj.tiling_flags);
961fb597
JG		 2038 if (r)
2039 return r;
1729dd33
AD		 2040 ib[idx+1+(i*7)+2] += base_offset;
2041 ib[idx+1+(i*7)+3] += mip_offset;
3ce0a23d
JG		 2042 break;
2043 case SQ_TEX_VTX_VALID_BUFFER:
6333003b
MO		 2044 {
2045 uint64_t offset64;
3ce0a23d
JG		 2046 /* vtx base */
2047 r = r600_cs_packet_next_reloc(p, &reloc);
2048 if (r) {
2049 DRM_ERROR("bad SET_RESOURCE\n");
2050 return -EINVAL;
2051 }
961fb597 2052 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
1729dd33 2053 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
961fb597
JG		 2054 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2055 /* force size to size of the buffer */
1729dd33
AD		 2056 dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
2057 size + offset, radeon_bo_size(reloc->robj));
6333003b 2058 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset;
961fb597 2059 }
6333003b
MO		 2060
2061 offset64 = reloc->lobj.gpu_offset + offset;
2062 ib[idx+1+(i*8)+0] = offset64;
2063 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |
2064 (upper_32_bits(offset64) & 0xff);
3ce0a23d 2065 break;
6333003b 2066 }
3ce0a23d
JG		 2067 case SQ_TEX_VTX_INVALID_TEXTURE:
2068 case SQ_TEX_VTX_INVALID_BUFFER:
2069 default:
2070 DRM_ERROR("bad SET_RESOURCE\n");
2071 return -EINVAL;
2072 }
2073 }
2074 break;
2075 case PACKET3_SET_ALU_CONST:
5f77df36
AD		 2076 if (track->sq_config & DX9_CONSTS) {
2077 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
2078 end_reg = 4 * pkt->count + start_reg - 4;
2079 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
2080 (start_reg >= PACKET3_SET_ALU_CONST_END) ||
2081 (end_reg >= PACKET3_SET_ALU_CONST_END)) {
2082 DRM_ERROR("bad SET_ALU_CONST\n");
2083 return -EINVAL;
2084 }
3ce0a23d
JG		 2085 }
2086 break;
2087 case PACKET3_SET_BOOL_CONST:
adea4796 2088 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
3ce0a23d
JG		 2089 end_reg = 4 * pkt->count + start_reg - 4;
2090 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
2091 (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
2092 (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
2093 DRM_ERROR("bad SET_BOOL_CONST\n");
2094 return -EINVAL;
2095 }
2096 break;
2097 case PACKET3_SET_LOOP_CONST:
adea4796 2098 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
3ce0a23d
JG		 2099 end_reg = 4 * pkt->count + start_reg - 4;
2100 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
2101 (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
2102 (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
2103 DRM_ERROR("bad SET_LOOP_CONST\n");
2104 return -EINVAL;
2105 }
2106 break;
2107 case PACKET3_SET_CTL_CONST:
adea4796 2108 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
3ce0a23d
JG		 2109 end_reg = 4 * pkt->count + start_reg - 4;
2110 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
2111 (start_reg >= PACKET3_SET_CTL_CONST_END) ||
2112 (end_reg >= PACKET3_SET_CTL_CONST_END)) {
2113 DRM_ERROR("bad SET_CTL_CONST\n");
2114 return -EINVAL;
2115 }
2116 break;
2117 case PACKET3_SET_SAMPLER:
2118 if (pkt->count % 3) {
2119 DRM_ERROR("bad SET_SAMPLER\n");
2120 return -EINVAL;
2121 }
adea4796 2122 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
3ce0a23d
JG		 2123 end_reg = 4 * pkt->count + start_reg - 4;
2124 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
2125 (start_reg >= PACKET3_SET_SAMPLER_END) ||
2126 (end_reg >= PACKET3_SET_SAMPLER_END)) {
2127 DRM_ERROR("bad SET_SAMPLER\n");
2128 return -EINVAL;
2129 }
2130 break;
7c77bf2a 2131 case PACKET3_STRMOUT_BASE_UPDATE:
46fc8781
MO		 2132 /* RS780 and RS880 also need this */
2133 if (p->family < CHIP_RS780) {
7c77bf2a
AD		 2134 DRM_ERROR("STRMOUT_BASE_UPDATE only supported on 7xx\n");
2135 return -EINVAL;
2136 }
2137 if (pkt->count != 1) {
2138 DRM_ERROR("bad STRMOUT_BASE_UPDATE packet count\n");
2139 return -EINVAL;
2140 }
2141 if (idx_value > 3) {
2142 DRM_ERROR("bad STRMOUT_BASE_UPDATE index\n");
2143 return -EINVAL;
2144 }
2145 {
2146 u64 offset;
2147
2148 r = r600_cs_packet_next_reloc(p, &reloc);
2149 if (r) {
2150 DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n");
2151 return -EINVAL;
2152 }
2153
2154 if (reloc->robj != track->vgt_strmout_bo[idx_value]) {
2155 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo does not match\n");
2156 return -EINVAL;
2157 }
2158
2159 offset = radeon_get_ib_value(p, idx+1) << 8;
2160 if (offset != track->vgt_strmout_bo_offset[idx_value]) {
2161 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%llx, 0x%x\n",
2162 offset, track->vgt_strmout_bo_offset[idx_value]);
2163 return -EINVAL;
2164 }
2165
2166 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2167 DRM_ERROR("bad STRMOUT_BASE_UPDATE bo too small: 0x%llx, 0x%lx\n",
2168 offset + 4, radeon_bo_size(reloc->robj));
2169 return -EINVAL;
2170 }
2171 ib[idx+1] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2172 }
2173 break;
3ce0a23d
JG		 2174 case PACKET3_SURFACE_BASE_UPDATE:
2175 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
2176 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
2177 return -EINVAL;
2178 }
2179 if (pkt->count) {
2180 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
2181 return -EINVAL;
2182 }
2183 break;
dd220a00
MO		 2184 case PACKET3_STRMOUT_BUFFER_UPDATE:
2185 if (pkt->count != 4) {
2186 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");
2187 return -EINVAL;
2188 }
2189 /* Updating memory at DST_ADDRESS. */
2190 if (idx_value & 0x1) {
2191 u64 offset;
2192 r = r600_cs_packet_next_reloc(p, &reloc);
2193 if (r) {
2194 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2195 return -EINVAL;
2196 }
2197 offset = radeon_get_ib_value(p, idx+1);
2198 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2199 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2200 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n",
2201 offset + 4, radeon_bo_size(reloc->robj));
2202 return -EINVAL;
2203 }
6333003b
MO		 2204 offset += reloc->lobj.gpu_offset;
2205 ib[idx+1] = offset;
2206 ib[idx+2] = upper_32_bits(offset) & 0xff;
dd220a00
MO		 2207 }
2208 /* Reading data from SRC_ADDRESS. */
2209 if (((idx_value >> 1) & 0x3) == 2) {
2210 u64 offset;
2211 r = r600_cs_packet_next_reloc(p, &reloc);
2212 if (r) {
2213 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2214 return -EINVAL;
2215 }
2216 offset = radeon_get_ib_value(p, idx+3);
2217 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2218 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2219 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n",
2220 offset + 4, radeon_bo_size(reloc->robj));
2221 return -EINVAL;
2222 }
6333003b
MO		 2223 offset += reloc->lobj.gpu_offset;
2224 ib[idx+3] = offset;
2225 ib[idx+4] = upper_32_bits(offset) & 0xff;
dd220a00
MO		 2226 }
2227 break;
4613ca14
JG		 2228 case PACKET3_MEM_WRITE:
2229 {
2230 u64 offset;
2231
2232 if (pkt->count != 3) {
2233 DRM_ERROR("bad MEM_WRITE (invalid count)\n");
2234 return -EINVAL;
2235 }
2236 r = r600_cs_packet_next_reloc(p, &reloc);
2237 if (r) {
2238 DRM_ERROR("bad MEM_WRITE (missing reloc)\n");
2239 return -EINVAL;
2240 }
2241 offset = radeon_get_ib_value(p, idx+0);
2242 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;
2243 if (offset & 0x7) {
2244 DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n");
2245 return -EINVAL;
2246 }
2247 if ((offset + 8) > radeon_bo_size(reloc->robj)) {
2248 DRM_ERROR("bad MEM_WRITE bo too small: 0x%llx, 0x%lx\n",
2249 offset + 8, radeon_bo_size(reloc->robj));
2250 return -EINVAL;
2251 }
2252 offset += reloc->lobj.gpu_offset;
2253 ib[idx+0] = offset;
2254 ib[idx+1] = upper_32_bits(offset) & 0xff;
2255 break;
2256 }
dd220a00
MO		 2257 case PACKET3_COPY_DW:
2258 if (pkt->count != 4) {
2259 DRM_ERROR("bad COPY_DW (invalid count)\n");
2260 return -EINVAL;
2261 }
2262 if (idx_value & 0x1) {
2263 u64 offset;
2264 /* SRC is memory. */
2265 r = r600_cs_packet_next_reloc(p, &reloc);
2266 if (r) {
2267 DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2268 return -EINVAL;
2269 }
2270 offset = radeon_get_ib_value(p, idx+1);
2271 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2272 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2273 DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n",
2274 offset + 4, radeon_bo_size(reloc->robj));
2275 return -EINVAL;
2276 }
6333003b
MO		 2277 offset += reloc->lobj.gpu_offset;
2278 ib[idx+1] = offset;
2279 ib[idx+2] = upper_32_bits(offset) & 0xff;
dd220a00
MO		 2280 } else {
2281 /* SRC is a reg. */
2282 reg = radeon_get_ib_value(p, idx+1) << 2;
2283 if (!r600_is_safe_reg(p, reg, idx+1))
2284 return -EINVAL;
2285 }
2286 if (idx_value & 0x2) {
2287 u64 offset;
2288 /* DST is memory. */
2289 r = r600_cs_packet_next_reloc(p, &reloc);
2290 if (r) {
2291 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2292 return -EINVAL;
2293 }
2294 offset = radeon_get_ib_value(p, idx+3);
2295 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2296 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2297 DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n",
2298 offset + 4, radeon_bo_size(reloc->robj));
2299 return -EINVAL;
2300 }
6333003b
MO		 2301 offset += reloc->lobj.gpu_offset;
2302 ib[idx+3] = offset;
2303 ib[idx+4] = upper_32_bits(offset) & 0xff;
dd220a00
MO		 2304 } else {
2305 /* DST is a reg. */
2306 reg = radeon_get_ib_value(p, idx+3) << 2;
2307 if (!r600_is_safe_reg(p, reg, idx+3))
2308 return -EINVAL;
2309 }
2310 break;
3ce0a23d
JG		 2311 case PACKET3_NOP:
2312 break;
2313 default:
2314 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2315 return -EINVAL;
2316 }
2317 return 0;
2318}
2319
2320int r600_cs_parse(struct radeon_cs_parser *p)
2321{
2322 struct radeon_cs_packet pkt;
c8c15ff1 2323 struct r600_cs_track *track;
3ce0a23d
JG		 2324 int r;
2325
961fb597
JG		 2326 if (p->track == NULL) {
2327 /* initialize tracker, we are in kms */
2328 track = kzalloc(sizeof(*track), GFP_KERNEL);
2329 if (track == NULL)
2330 return -ENOMEM;
2331 r600_cs_track_init(track);
2332 if (p->rdev->family < CHIP_RV770) {
2333 track->npipes = p->rdev->config.r600.tiling_npipes;
2334 track->nbanks = p->rdev->config.r600.tiling_nbanks;
2335 track->group_size = p->rdev->config.r600.tiling_group_size;
2336 } else if (p->rdev->family <= CHIP_RV740) {
2337 track->npipes = p->rdev->config.rv770.tiling_npipes;
2338 track->nbanks = p->rdev->config.rv770.tiling_nbanks;
2339 track->group_size = p->rdev->config.rv770.tiling_group_size;
2340 }
2341 p->track = track;
2342 }
3ce0a23d 2343 do {
c38f34b5 2344 r = radeon_cs_packet_parse(p, &pkt, p->idx);
3ce0a23d 2345 if (r) {
7cb72ef4
JG		 2346 kfree(p->track);
2347 p->track = NULL;
3ce0a23d
JG		 2348 return r;
2349 }
2350 p->idx += pkt.count + 2;
2351 switch (pkt.type) {
2352 case PACKET_TYPE0:
2353 r = r600_cs_parse_packet0(p, &pkt);
2354 break;
2355 case PACKET_TYPE2:
2356 break;
2357 case PACKET_TYPE3:
2358 r = r600_packet3_check(p, &pkt);
2359 break;
2360 default:
2361 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
961fb597 2362 kfree(p->track);
7cb72ef4 2363 p->track = NULL;
3ce0a23d
JG		 2364 return -EINVAL;
2365 }
2366 if (r) {
961fb597 2367 kfree(p->track);
7cb72ef4 2368 p->track = NULL;
3ce0a23d
JG		 2369 return r;
2370 }
2371 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2372#if 0
f2e39221
JG		 2373 for (r = 0; r < p->ib.length_dw; r++) {
2374 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]);
3ce0a23d
JG		 2375 mdelay(1);
2376 }
2377#endif
961fb597 2378 kfree(p->track);
7cb72ef4 2379 p->track = NULL;
3ce0a23d
JG		 2380 return 0;
2381}
2382
2383static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
2384{
2385 if (p->chunk_relocs_idx == -1) {
2386 return 0;
2387 }
e265f39e 2388 p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
3ce0a23d
JG		 2389 if (p->relocs == NULL) {
2390 return -ENOMEM;
2391 }
2392 return 0;
2393}
2394
2395/**
2396 * cs_parser_fini() - clean parser states
2397 * @parser: parser structure holding parsing context.
2398 * @error: error number
2399 *
2400 * If error is set than unvalidate buffer, otherwise just free memory
2401 * used by parsing context.
2402 **/
2403static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
2404{
2405 unsigned i;
2406
2407 kfree(parser->relocs);
2408 for (i = 0; i < parser->nchunks; i++) {
2409 kfree(parser->chunks[i].kdata);
a6b7e1a0
IH		 2410 if (parser->rdev && (parser->rdev->flags & RADEON_IS_AGP)) {
2411 kfree(parser->chunks[i].kpage[0]);
2412 kfree(parser->chunks[i].kpage[1]);
2413 }
3ce0a23d
JG		 2414 }
2415 kfree(parser->chunks);
2416 kfree(parser->chunks_array);
2417}
2418
2419int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
2420 unsigned family, u32 *ib, int *l)
2421{
2422 struct radeon_cs_parser parser;
2423 struct radeon_cs_chunk *ib_chunk;
961fb597 2424 struct r600_cs_track *track;
3ce0a23d
JG		 2425 int r;
2426
961fb597
JG		 2427 /* initialize tracker */
2428 track = kzalloc(sizeof(*track), GFP_KERNEL);
2429 if (track == NULL)
2430 return -ENOMEM;
2431 r600_cs_track_init(track);
2432 r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
3ce0a23d
JG		 2433 /* initialize parser */
2434 memset(&parser, 0, sizeof(struct radeon_cs_parser));
2435 parser.filp = filp;
c8c15ff1 2436 parser.dev = &dev->pdev->dev;
3ce0a23d
JG		 2437 parser.rdev = NULL;
2438 parser.family = family;
961fb597 2439 parser.track = track;
f2e39221 2440 parser.ib.ptr = ib;
3ce0a23d
JG		 2441 r = radeon_cs_parser_init(&parser, data);
2442 if (r) {
2443 DRM_ERROR("Failed to initialize parser !\n");
2444 r600_cs_parser_fini(&parser, r);
2445 return r;
2446 }
2447 r = r600_cs_parser_relocs_legacy(&parser);
2448 if (r) {
2449 DRM_ERROR("Failed to parse relocation !\n");
2450 r600_cs_parser_fini(&parser, r);
2451 return r;
2452 }
2453 /* Copy the packet into the IB, the parser will read from the
2454 * input memory (cached) and write to the IB (which can be
2455 * uncached). */
2456 ib_chunk = &parser.chunks[parser.chunk_ib_idx];
f2e39221
JG		 2457 parser.ib.length_dw = ib_chunk->length_dw;
2458 *l = parser.ib.length_dw;
3ce0a23d
JG		 2459 r = r600_cs_parse(&parser);
2460 if (r) {
2461 DRM_ERROR("Invalid command stream !\n");
2462 r600_cs_parser_fini(&parser, r);
2463 return r;
2464 }
513bcb46
DA		 2465 r = radeon_cs_finish_pages(&parser);
2466 if (r) {
2467 DRM_ERROR("Invalid command stream !\n");
2468 r600_cs_parser_fini(&parser, r);
2469 return r;
2470 }
3ce0a23d
JG		 2471 r600_cs_parser_fini(&parser, r);
2472 return r;
2473}
2474
2475void r600_cs_legacy_init(void)
2476{
2477 r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
2478}
cf4ccd01
AD		 2479
2480/*
2481 * DMA
2482 */
2483/**
2484 * r600_dma_cs_next_reloc() - parse next reloc
2485 * @p: parser structure holding parsing context.
2486 * @cs_reloc: reloc informations
2487 *
2488 * Return the next reloc, do bo validation and compute
2489 * GPU offset using the provided start.
2490 **/
2491int r600_dma_cs_next_reloc(struct radeon_cs_parser *p,
2492 struct radeon_cs_reloc **cs_reloc)
2493{
2494 struct radeon_cs_chunk *relocs_chunk;
2495 unsigned idx;
2496
9305ede6 2497 *cs_reloc = NULL;
cf4ccd01
AD		 2498 if (p->chunk_relocs_idx == -1) {
2499 DRM_ERROR("No relocation chunk !\n");
2500 return -EINVAL;
2501 }
cf4ccd01
AD		 2502 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
2503 idx = p->dma_reloc_idx;
9305ede6 2504 if (idx >= p->nrelocs) {
cf4ccd01 2505 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
9305ede6 2506 idx, p->nrelocs);
cf4ccd01
AD		 2507 return -EINVAL;
2508 }
2509 *cs_reloc = p->relocs_ptr[idx];
2510 p->dma_reloc_idx++;
2511 return 0;
2512}
2513
2514#define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28)
2515#define GET_DMA_COUNT(h) ((h) & 0x0000ffff)
2516#define GET_DMA_T(h) (((h) & 0x00800000) >> 23)
2517
2518/**
2519 * r600_dma_cs_parse() - parse the DMA IB
2520 * @p: parser structure holding parsing context.
2521 *
2522 * Parses the DMA IB from the CS ioctl and updates
2523 * the GPU addresses based on the reloc information and
2524 * checks for errors. (R6xx-R7xx)
2525 * Returns 0 for success and an error on failure.
2526 **/
2527int r600_dma_cs_parse(struct radeon_cs_parser *p)
2528{
2529 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
2530 struct radeon_cs_reloc *src_reloc, *dst_reloc;
2531 u32 header, cmd, count, tiled;
2532 volatile u32 *ib = p->ib.ptr;
2533 u32 idx, idx_value;
2534 u64 src_offset, dst_offset;
2535 int r;
2536
2537 do {
2538 if (p->idx >= ib_chunk->length_dw) {
2539 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
2540 p->idx, ib_chunk->length_dw);
2541 return -EINVAL;
2542 }
2543 idx = p->idx;
2544 header = radeon_get_ib_value(p, idx);
2545 cmd = GET_DMA_CMD(header);
2546 count = GET_DMA_COUNT(header);
2547 tiled = GET_DMA_T(header);
2548
2549 switch (cmd) {
2550 case DMA_PACKET_WRITE:
2551 r = r600_dma_cs_next_reloc(p, &dst_reloc);
2552 if (r) {
2553 DRM_ERROR("bad DMA_PACKET_WRITE\n");
2554 return -EINVAL;
2555 }
2556 if (tiled) {
2557 dst_offset = ib[idx+1];
2558 dst_offset <<= 8;
2559
2560 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2561 p->idx += count + 5;
2562 } else {
2563 dst_offset = ib[idx+1];
2564 dst_offset |= ((u64)(ib[idx+2] & 0xff)) << 32;
2565
2566 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2567 ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2568 p->idx += count + 3;
2569 }
2570 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2571 dev_warn(p->dev, "DMA write buffer too small (%llu %lu)\n",
2572 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2573 return -EINVAL;
2574 }
2575 break;
2576 case DMA_PACKET_COPY:
2577 r = r600_dma_cs_next_reloc(p, &src_reloc);
2578 if (r) {
2579 DRM_ERROR("bad DMA_PACKET_COPY\n");
2580 return -EINVAL;
2581 }
2582 r = r600_dma_cs_next_reloc(p, &dst_reloc);
2583 if (r) {
2584 DRM_ERROR("bad DMA_PACKET_COPY\n");
2585 return -EINVAL;
2586 }
2587 if (tiled) {
2588 idx_value = radeon_get_ib_value(p, idx + 2);
2589 /* detile bit */
2590 if (idx_value & (1 << 31)) {
2591 /* tiled src, linear dst */
2592 src_offset = ib[idx+1];
2593 src_offset <<= 8;
2594 ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
2595
2596 dst_offset = ib[idx+5];
2597 dst_offset |= ((u64)(ib[idx+6] & 0xff)) << 32;
2598 ib[idx+5] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2599 ib[idx+6] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2600 } else {
2601 /* linear src, tiled dst */
2602 src_offset = ib[idx+5];
2603 src_offset |= ((u64)(ib[idx+6] & 0xff)) << 32;
2604 ib[idx+5] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2605 ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2606
2607 dst_offset = ib[idx+1];
2608 dst_offset <<= 8;
2609 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2610 }
2611 p->idx += 7;
2612 } else {
a10fbb42
AD		 2613 if (p->family >= CHIP_RV770) {
2614 src_offset = ib[idx+2];
2615 src_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
2616 dst_offset = ib[idx+1];
2617 dst_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
cf4ccd01 2618
a10fbb42
AD		 2619 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2620 ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2621 ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2622 ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2623 p->idx += 5;
2624 } else {
2625 src_offset = ib[idx+2];
2626 src_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
2627 dst_offset = ib[idx+1];
2628 dst_offset |= ((u64)(ib[idx+3] & 0xff0000)) << 16;
2629
2630 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2631 ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2632 ib[idx+3] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2633 ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff) << 16;
2634 p->idx += 4;
2635 }
cf4ccd01
AD		 2636 }
2637 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2638 dev_warn(p->dev, "DMA copy src buffer too small (%llu %lu)\n",
2639 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2640 return -EINVAL;
2641 }
2642 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2643 dev_warn(p->dev, "DMA write dst buffer too small (%llu %lu)\n",
2644 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2645 return -EINVAL;
2646 }
2647 break;
2648 case DMA_PACKET_CONSTANT_FILL:
2649 if (p->family < CHIP_RV770) {
2650 DRM_ERROR("Constant Fill is 7xx only !\n");
2651 return -EINVAL;
2652 }
2653 r = r600_dma_cs_next_reloc(p, &dst_reloc);
2654 if (r) {
2655 DRM_ERROR("bad DMA_PACKET_WRITE\n");
2656 return -EINVAL;
2657 }
2658 dst_offset = ib[idx+1];
2659 dst_offset |= ((u64)(ib[idx+3] & 0x00ff0000)) << 16;
2660 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2661 dev_warn(p->dev, "DMA constant fill buffer too small (%llu %lu)\n",
2662 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2663 return -EINVAL;
2664 }
2665 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2666 ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) << 16) & 0x00ff0000;
2667 p->idx += 4;
2668 break;
2669 case DMA_PACKET_NOP:
2670 p->idx += 1;
2671 break;
2672 default:
2673 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx);
2674 return -EINVAL;
2675 }
2676 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2677#if 0
2678 for (r = 0; r < p->ib->length_dw; r++) {
2679 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]);
2680 mdelay(1);
2681 }
2682#endif
2683 return 0;
2684}
Linux kernel - Deliverables
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