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drm/radeon: use common cs packet parse function
[deliverable/linux.git] / drivers / gpu / drm / radeon / r600_cs.c
CommitLineData
3ce0a23d
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
40e2a5c1 28#include <linux/kernel.h>
760285e7 29#include <drm/drmP.h>
3ce0a23d 30#include "radeon.h"
3ce0a23d 31#include "r600d.h"
961fb597 32#include "r600_reg_safe.h"
3ce0a23d
JG		 33
34static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
35 struct radeon_cs_reloc **cs_reloc);
36static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
37 struct radeon_cs_reloc **cs_reloc);
38typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
39static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
961fb597
JG		 40extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
41
3ce0a23d 42
c8c15ff1 43struct r600_cs_track {
961fb597
JG		 44 /* configuration we miror so that we use same code btw kms/ums */
45 u32 group_size;
46 u32 nbanks;
47 u32 npipes;
48 /* value we track */
5f77df36 49 u32 sq_config;
c116cc94 50 u32 log_nsamples;
961fb597
JG		 51 u32 nsamples;
52 u32 cb_color_base_last[8];
53 struct radeon_bo *cb_color_bo[8];
16790569 54 u64 cb_color_bo_mc[8];
c116cc94
MO		 55 u64 cb_color_bo_offset[8];
56 struct radeon_bo *cb_color_frag_bo[8];
57 u64 cb_color_frag_offset[8];
58 struct radeon_bo *cb_color_tile_bo[8];
59 u64 cb_color_tile_offset[8];
60 u32 cb_color_mask[8];
961fb597 61 u32 cb_color_info[8];
285484e2 62 u32 cb_color_view[8];
3c12513d 63 u32 cb_color_size_idx[8]; /* unused */
961fb597 64 u32 cb_target_mask;
3c12513d 65 u32 cb_shader_mask; /* unused */
523885de 66 bool is_resolve;
961fb597
JG		 67 u32 cb_color_size[8];
68 u32 vgt_strmout_en;
69 u32 vgt_strmout_buffer_en;
dd220a00 70 struct radeon_bo *vgt_strmout_bo[4];
3c12513d 71 u64 vgt_strmout_bo_mc[4]; /* unused */
dd220a00
MO		 72 u32 vgt_strmout_bo_offset[4];
73 u32 vgt_strmout_size[4];
961fb597
JG		 74 u32 db_depth_control;
75 u32 db_depth_info;
76 u32 db_depth_size_idx;
77 u32 db_depth_view;
78 u32 db_depth_size;
79 u32 db_offset;
80 struct radeon_bo *db_bo;
16790569 81 u64 db_bo_mc;
779923bc 82 bool sx_misc_kill_all_prims;
3c12513d
MO		 83 bool cb_dirty;
84 bool db_dirty;
85 bool streamout_dirty;
88f50c80
JG		 86 struct radeon_bo *htile_bo;
87 u64 htile_offset;
88 u32 htile_surface;
c8c15ff1
JG		 89};
90
fe6f0bd0
MO		 91#define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 }
92#define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc, CHIP_R600 }
285484e2 93#define FMT_24_BIT(fmt) [fmt] = { 1, 1, 4, 0, CHIP_R600 }
fe6f0bd0 94#define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc, CHIP_R600 }
285484e2 95#define FMT_48_BIT(fmt) [fmt] = { 1, 1, 8, 0, CHIP_R600 }
fe6f0bd0
MO		 96#define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 }
97#define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0, CHIP_R600 }
98#define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 }
60b212f8
DA		 99
100struct gpu_formats {
101 unsigned blockwidth;
102 unsigned blockheight;
103 unsigned blocksize;
104 unsigned valid_color;
fe6f0bd0 105 enum radeon_family min_family;
60b212f8
DA		 106};
107
108static const struct gpu_formats color_formats_table[] = {
109 /* 8 bit */
110 FMT_8_BIT(V_038004_COLOR_8, 1),
111 FMT_8_BIT(V_038004_COLOR_4_4, 1),
112 FMT_8_BIT(V_038004_COLOR_3_3_2, 1),
113 FMT_8_BIT(V_038004_FMT_1, 0),
114
115 /* 16-bit */
116 FMT_16_BIT(V_038004_COLOR_16, 1),
117 FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1),
118 FMT_16_BIT(V_038004_COLOR_8_8, 1),
119 FMT_16_BIT(V_038004_COLOR_5_6_5, 1),
120 FMT_16_BIT(V_038004_COLOR_6_5_5, 1),
121 FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1),
122 FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1),
123 FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1),
124
125 /* 24-bit */
126 FMT_24_BIT(V_038004_FMT_8_8_8),
285484e2 127
60b212f8
DA		 128 /* 32-bit */
129 FMT_32_BIT(V_038004_COLOR_32, 1),
130 FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1),
131 FMT_32_BIT(V_038004_COLOR_16_16, 1),
132 FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1),
133 FMT_32_BIT(V_038004_COLOR_8_24, 1),
134 FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1),
135 FMT_32_BIT(V_038004_COLOR_24_8, 1),
136 FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1),
137 FMT_32_BIT(V_038004_COLOR_10_11_11, 1),
138 FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1),
139 FMT_32_BIT(V_038004_COLOR_11_11_10, 1),
140 FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1),
141 FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1),
142 FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1),
143 FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1),
144 FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0),
145 FMT_32_BIT(V_038004_FMT_32_AS_8, 0),
146 FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0),
147
148 /* 48-bit */
149 FMT_48_BIT(V_038004_FMT_16_16_16),
150 FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT),
151
152 /* 64-bit */
153 FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1),
154 FMT_64_BIT(V_038004_COLOR_32_32, 1),
155 FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1),
156 FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1),
157 FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1),
158
159 FMT_96_BIT(V_038004_FMT_32_32_32),
160 FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT),
161
162 /* 128-bit */
163 FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1),
164 FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1),
165
166 [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 },
167 [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 },
168
169 /* block compressed formats */
170 [V_038004_FMT_BC1] = { 4, 4, 8, 0 },
171 [V_038004_FMT_BC2] = { 4, 4, 16, 0 },
172 [V_038004_FMT_BC3] = { 4, 4, 16, 0 },
173 [V_038004_FMT_BC4] = { 4, 4, 8, 0 },
174 [V_038004_FMT_BC5] = { 4, 4, 16, 0},
fe6f0bd0
MO		 175 [V_038004_FMT_BC6] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
176 [V_038004_FMT_BC7] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
60b212f8 177
fe6f0bd0
MO		 178 /* The other Evergreen formats */
179 [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR},
60b212f8
DA		 180};
181
285484e2 182bool r600_fmt_is_valid_color(u32 format)
60b212f8 183{
cf8a47d1 184 if (format >= ARRAY_SIZE(color_formats_table))
60b212f8 185 return false;
285484e2 186
60b212f8
DA		 187 if (color_formats_table[format].valid_color)
188 return true;
189
190 return false;
191}
192
285484e2 193bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family)
60b212f8 194{
cf8a47d1 195 if (format >= ARRAY_SIZE(color_formats_table))
60b212f8 196 return false;
285484e2 197
fe6f0bd0
MO		 198 if (family < color_formats_table[format].min_family)
199 return false;
200
60b212f8
DA		 201 if (color_formats_table[format].blockwidth > 0)
202 return true;
203
204 return false;
205}
206
285484e2 207int r600_fmt_get_blocksize(u32 format)
60b212f8 208{
cf8a47d1 209 if (format >= ARRAY_SIZE(color_formats_table))
60b212f8
DA		 210 return 0;
211
212 return color_formats_table[format].blocksize;
213}
214
285484e2 215int r600_fmt_get_nblocksx(u32 format, u32 w)
60b212f8
DA		 216{
217 unsigned bw;
cf8a47d1
DC		 218
219 if (format >= ARRAY_SIZE(color_formats_table))
60b212f8
DA		 220 return 0;
221
222 bw = color_formats_table[format].blockwidth;
223 if (bw == 0)
224 return 0;
225
226 return (w + bw - 1) / bw;
227}
228
285484e2 229int r600_fmt_get_nblocksy(u32 format, u32 h)
60b212f8
DA		 230{
231 unsigned bh;
cf8a47d1
DC		 232
233 if (format >= ARRAY_SIZE(color_formats_table))
60b212f8
DA		 234 return 0;
235
236 bh = color_formats_table[format].blockheight;
237 if (bh == 0)
238 return 0;
239
240 return (h + bh - 1) / bh;
241}
242
16790569
AD		 243struct array_mode_checker {
244 int array_mode;
245 u32 group_size;
246 u32 nbanks;
247 u32 npipes;
248 u32 nsamples;
60b212f8 249 u32 blocksize;
16790569
AD		 250};
251
252/* returns alignment in pixels for pitch/height/depth and bytes for base */
488479eb 253static int r600_get_array_mode_alignment(struct array_mode_checker *values,
16790569
AD		 254 u32 *pitch_align,
255 u32 *height_align,
256 u32 *depth_align,
257 u64 *base_align)
258{
259 u32 tile_width = 8;
260 u32 tile_height = 8;
261 u32 macro_tile_width = values->nbanks;
262 u32 macro_tile_height = values->npipes;
60b212f8 263 u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples;
16790569
AD		 264 u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes;
265
266 switch (values->array_mode) {
267 case ARRAY_LINEAR_GENERAL:
268 /* technically tile_width/_height for pitch/height */
269 *pitch_align = 1; /* tile_width */
270 *height_align = 1; /* tile_height */
271 *depth_align = 1;
272 *base_align = 1;
273 break;
274 case ARRAY_LINEAR_ALIGNED:
60b212f8 275 *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));
285484e2 276 *height_align = 1;
16790569
AD		 277 *depth_align = 1;
278 *base_align = values->group_size;
279 break;
280 case ARRAY_1D_TILED_THIN1:
281 *pitch_align = max((u32)tile_width,
282 (u32)(values->group_size /
60b212f8 283 (tile_height * values->blocksize * values->nsamples)));
16790569
AD		 284 *height_align = tile_height;
285 *depth_align = 1;
286 *base_align = values->group_size;
287 break;
288 case ARRAY_2D_TILED_THIN1:
285484e2
JG		 289 *pitch_align = max((u32)macro_tile_width * tile_width,
290 (u32)((values->group_size * values->nbanks) /
291 (values->blocksize * values->nsamples * tile_width)));
16790569
AD		 292 *height_align = macro_tile_height * tile_height;
293 *depth_align = 1;
294 *base_align = max(macro_tile_bytes,
60b212f8 295 (*pitch_align) * values->blocksize * (*height_align) * values->nsamples);
16790569
AD		 296 break;
297 default:
298 return -EINVAL;
299 }
300
301 return 0;
302}
303
961fb597
JG		 304static void r600_cs_track_init(struct r600_cs_track *track)
305{
306 int i;
307
5f77df36
AD		 308 /* assume DX9 mode */
309 track->sq_config = DX9_CONSTS;
961fb597
JG		 310 for (i = 0; i < 8; i++) {
311 track->cb_color_base_last[i] = 0;
312 track->cb_color_size[i] = 0;
313 track->cb_color_size_idx[i] = 0;
314 track->cb_color_info[i] = 0;
285484e2 315 track->cb_color_view[i] = 0xFFFFFFFF;
961fb597
JG		 316 track->cb_color_bo[i] = NULL;
317 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
16790569 318 track->cb_color_bo_mc[i] = 0xFFFFFFFF;
3b5ef597
MO		 319 track->cb_color_frag_bo[i] = NULL;
320 track->cb_color_frag_offset[i] = 0xFFFFFFFF;
321 track->cb_color_tile_bo[i] = NULL;
322 track->cb_color_tile_offset[i] = 0xFFFFFFFF;
323 track->cb_color_mask[i] = 0xFFFFFFFF;
961fb597 324 }
523885de 325 track->is_resolve = false;
3b5ef597
MO		 326 track->nsamples = 16;
327 track->log_nsamples = 4;
961fb597
JG		 328 track->cb_target_mask = 0xFFFFFFFF;
329 track->cb_shader_mask = 0xFFFFFFFF;
3c12513d 330 track->cb_dirty = true;
961fb597 331 track->db_bo = NULL;
16790569 332 track->db_bo_mc = 0xFFFFFFFF;
961fb597
JG		 333 /* assume the biggest format and that htile is enabled */
334 track->db_depth_info = 7 | (1 << 25);
335 track->db_depth_view = 0xFFFFC000;
336 track->db_depth_size = 0xFFFFFFFF;
337 track->db_depth_size_idx = 0;
338 track->db_depth_control = 0xFFFFFFFF;
3c12513d 339 track->db_dirty = true;
88f50c80
JG		 340 track->htile_bo = NULL;
341 track->htile_offset = 0xFFFFFFFF;
342 track->htile_surface = 0;
dd220a00
MO		 343
344 for (i = 0; i < 4; i++) {
345 track->vgt_strmout_size[i] = 0;
346 track->vgt_strmout_bo[i] = NULL;
347 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
348 track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF;
349 }
3c12513d 350 track->streamout_dirty = true;
779923bc 351 track->sx_misc_kill_all_prims = false;
961fb597
JG		 352}
353
488479eb 354static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
961fb597
JG		 355{
356 struct r600_cs_track *track = p->track;
60b212f8 357 u32 slice_tile_max, size, tmp;
16790569
AD		 358 u32 height, height_align, pitch, pitch_align, depth_align;
359 u64 base_offset, base_align;
360 struct array_mode_checker array_check;
f2e39221 361 volatile u32 *ib = p->ib.ptr;
f30df2fa 362 unsigned array_mode;
60b212f8 363 u32 format;
523885de
MO		 364 /* When resolve is used, the second colorbuffer has always 1 sample. */
365 unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples;
285484e2 366
1729dd33 367 size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
60b212f8 368 format = G_0280A0_FORMAT(track->cb_color_info[i]);
285484e2 369 if (!r600_fmt_is_valid_color(format)) {
961fb597 370 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
60b212f8 371 __func__, __LINE__, format,
961fb597
JG		 372 i, track->cb_color_info[i]);
373 return -EINVAL;
374 }
16790569
AD		 375 /* pitch in pixels */
376 pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8;
961fb597 377 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
f30df2fa 378 slice_tile_max *= 64;
16790569 379 height = slice_tile_max / pitch;
961fb597
JG		 380 if (height > 8192)
381 height = 8192;
f30df2fa 382 array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
16790569
AD		 383
384 base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i];
385 array_check.array_mode = array_mode;
386 array_check.group_size = track->group_size;
387 array_check.nbanks = track->nbanks;
388 array_check.npipes = track->npipes;
523885de 389 array_check.nsamples = nsamples;
285484e2 390 array_check.blocksize = r600_fmt_get_blocksize(format);
16790569
AD		 391 if (r600_get_array_mode_alignment(&array_check,
392 &pitch_align, &height_align, &depth_align, &base_align)) {
393 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
394 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
395 track->cb_color_info[i]);
396 return -EINVAL;
397 }
f30df2fa 398 switch (array_mode) {
961fb597 399 case V_0280A0_ARRAY_LINEAR_GENERAL:
40e2a5c1 400 break;
961fb597 401 case V_0280A0_ARRAY_LINEAR_ALIGNED:
961fb597
JG		 402 break;
403 case V_0280A0_ARRAY_1D_TILED_THIN1:
8f895da5
AD		 404 /* avoid breaking userspace */
405 if (height > 7)
406 height &= ~0x7;
961fb597
JG		 407 break;
408 case V_0280A0_ARRAY_2D_TILED_THIN1:
961fb597
JG		 409 break;
410 default:
411 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
412 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
413 track->cb_color_info[i]);
414 return -EINVAL;
415 }
16790569
AD		 416
417 if (!IS_ALIGNED(pitch, pitch_align)) {
c2049b3d
AD		 418 dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n",
419 __func__, __LINE__, pitch, pitch_align, array_mode);
16790569
AD		 420 return -EINVAL;
421 }
422 if (!IS_ALIGNED(height, height_align)) {
c2049b3d
AD		 423 dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n",
424 __func__, __LINE__, height, height_align, array_mode);
16790569
AD		 425 return -EINVAL;
426 }
427 if (!IS_ALIGNED(base_offset, base_align)) {
c2049b3d
AD		 428 dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i,
429 base_offset, base_align, array_mode);
16790569
AD		 430 return -EINVAL;
431 }
432
961fb597 433 /* check offset */
fcdeefe4 434 tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) *
523885de 435 r600_fmt_get_blocksize(format) * nsamples;
285484e2
JG		 436 switch (array_mode) {
437 default:
438 case V_0280A0_ARRAY_LINEAR_GENERAL:
439 case V_0280A0_ARRAY_LINEAR_ALIGNED:
440 tmp += track->cb_color_view[i] & 0xFF;
441 break;
442 case V_0280A0_ARRAY_1D_TILED_THIN1:
443 case V_0280A0_ARRAY_2D_TILED_THIN1:
444 tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp;
445 break;
446 }
961fb597 447 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
f30df2fa
DA		 448 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
449 /* the initial DDX does bad things with the CB size occasionally */
450 /* it rounds up height too far for slice tile max but the BO is smaller */
a1a82133
AD		 451 /* r600c,g also seem to flush at bad times in some apps resulting in
452 * bogus values here. So for linear just allow anything to avoid breaking
453 * broken userspace.
454 */
f30df2fa 455 } else {
c116cc94 456 dev_warn(p->dev, "%s offset[%d] %d %llu %d %lu too big (%d %d) (%d %d %d)\n",
285484e2 457 __func__, i, array_mode,
c2049b3d 458 track->cb_color_bo_offset[i], tmp,
285484e2
JG		 459 radeon_bo_size(track->cb_color_bo[i]),
460 pitch, height, r600_fmt_get_nblocksx(format, pitch),
461 r600_fmt_get_nblocksy(format, height),
462 r600_fmt_get_blocksize(format));
f30df2fa
DA		 463 return -EINVAL;
464 }
40e2a5c1 465 }
961fb597 466 /* limit max tile */
16790569 467 tmp = (height * pitch) >> 6;
961fb597
JG		 468 if (tmp < slice_tile_max)
469 slice_tile_max = tmp;
16790569 470 tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
961fb597
JG		 471 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
472 ib[track->cb_color_size_idx[i]] = tmp;
c116cc94
MO		 473
474 /* FMASK/CMASK */
475 switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
476 case V_0280A0_TILE_DISABLE:
477 break;
478 case V_0280A0_FRAG_ENABLE:
479 if (track->nsamples > 1) {
480 uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]);
481 /* the tile size is 8x8, but the size is in units of bits.
482 * for bytes, do just * 8. */
483 uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1);
484
485 if (bytes + track->cb_color_frag_offset[i] >
486 radeon_bo_size(track->cb_color_frag_bo[i])) {
487 dev_warn(p->dev, "%s FMASK_TILE_MAX too large "
488 "(tile_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
489 __func__, tile_max, bytes,
490 track->cb_color_frag_offset[i],
491 radeon_bo_size(track->cb_color_frag_bo[i]));
492 return -EINVAL;
493 }
494 }
495 /* fall through */
496 case V_0280A0_CLEAR_ENABLE:
497 {
498 uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]);
499 /* One block = 128x128 pixels, one 8x8 tile has 4 bits..
500 * (128*128) / (8*8) / 2 = 128 bytes per block. */
501 uint32_t bytes = (block_max + 1) * 128;
502
503 if (bytes + track->cb_color_tile_offset[i] >
504 radeon_bo_size(track->cb_color_tile_bo[i])) {
505 dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large "
506 "(block_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
507 __func__, block_max, bytes,
508 track->cb_color_tile_offset[i],
509 radeon_bo_size(track->cb_color_tile_bo[i]));
510 return -EINVAL;
511 }
512 break;
513 }
514 default:
515 dev_warn(p->dev, "%s invalid tile mode\n", __func__);
516 return -EINVAL;
517 }
961fb597
JG		 518 return 0;
519}
520
88f50c80
JG		 521static int r600_cs_track_validate_db(struct radeon_cs_parser *p)
522{
523 struct r600_cs_track *track = p->track;
524 u32 nviews, bpe, ntiles, size, slice_tile_max, tmp;
525 u32 height_align, pitch_align, depth_align;
526 u32 pitch = 8192;
527 u32 height = 8192;
528 u64 base_offset, base_align;
529 struct array_mode_checker array_check;
530 int array_mode;
f2e39221 531 volatile u32 *ib = p->ib.ptr;
88f50c80
JG		 532
533
534 if (track->db_bo == NULL) {
535 dev_warn(p->dev, "z/stencil with no depth buffer\n");
536 return -EINVAL;
537 }
538 switch (G_028010_FORMAT(track->db_depth_info)) {
539 case V_028010_DEPTH_16:
540 bpe = 2;
541 break;
542 case V_028010_DEPTH_X8_24:
543 case V_028010_DEPTH_8_24:
544 case V_028010_DEPTH_X8_24_FLOAT:
545 case V_028010_DEPTH_8_24_FLOAT:
546 case V_028010_DEPTH_32_FLOAT:
547 bpe = 4;
548 break;
549 case V_028010_DEPTH_X24_8_32_FLOAT:
550 bpe = 8;
551 break;
552 default:
553 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
554 return -EINVAL;
555 }
556 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
557 if (!track->db_depth_size_idx) {
558 dev_warn(p->dev, "z/stencil buffer size not set\n");
559 return -EINVAL;
560 }
561 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
562 tmp = (tmp / bpe) >> 6;
563 if (!tmp) {
564 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
565 track->db_depth_size, bpe, track->db_offset,
566 radeon_bo_size(track->db_bo));
567 return -EINVAL;
568 }
569 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
570 } else {
571 size = radeon_bo_size(track->db_bo);
572 /* pitch in pixels */
573 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
574 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
575 slice_tile_max *= 64;
576 height = slice_tile_max / pitch;
577 if (height > 8192)
578 height = 8192;
579 base_offset = track->db_bo_mc + track->db_offset;
580 array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
581 array_check.array_mode = array_mode;
582 array_check.group_size = track->group_size;
583 array_check.nbanks = track->nbanks;
584 array_check.npipes = track->npipes;
585 array_check.nsamples = track->nsamples;
586 array_check.blocksize = bpe;
587 if (r600_get_array_mode_alignment(&array_check,
588 &pitch_align, &height_align, &depth_align, &base_align)) {
589 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
590 G_028010_ARRAY_MODE(track->db_depth_info),
591 track->db_depth_info);
592 return -EINVAL;
593 }
594 switch (array_mode) {
595 case V_028010_ARRAY_1D_TILED_THIN1:
596 /* don't break userspace */
597 height &= ~0x7;
598 break;
599 case V_028010_ARRAY_2D_TILED_THIN1:
600 break;
601 default:
602 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
603 G_028010_ARRAY_MODE(track->db_depth_info),
604 track->db_depth_info);
605 return -EINVAL;
606 }
607
608 if (!IS_ALIGNED(pitch, pitch_align)) {
609 dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",
610 __func__, __LINE__, pitch, pitch_align, array_mode);
611 return -EINVAL;
612 }
613 if (!IS_ALIGNED(height, height_align)) {
614 dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n",
615 __func__, __LINE__, height, height_align, array_mode);
616 return -EINVAL;
617 }
618 if (!IS_ALIGNED(base_offset, base_align)) {
619 dev_warn(p->dev, "%s offset 0x%llx, 0x%llx, %d not aligned\n", __func__,
620 base_offset, base_align, array_mode);
621 return -EINVAL;
622 }
623
624 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
625 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
fcdeefe4 626 tmp = ntiles * bpe * 64 * nviews * track->nsamples;
88f50c80
JG		 627 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
628 dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
629 array_mode,
630 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
631 radeon_bo_size(track->db_bo));
632 return -EINVAL;
633 }
634 }
635
636 /* hyperz */
637 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
638 unsigned long size;
639 unsigned nbx, nby;
640
641 if (track->htile_bo == NULL) {
642 dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n",
643 __func__, __LINE__, track->db_depth_info);
644 return -EINVAL;
645 }
646 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
647 dev_warn(p->dev, "%s:%d htile can't be enabled with bogus db_depth_size 0x%08x\n",
648 __func__, __LINE__, track->db_depth_size);
649 return -EINVAL;
650 }
651
652 nbx = pitch;
653 nby = height;
654 if (G_028D24_LINEAR(track->htile_surface)) {
655 /* nbx must be 16 htiles aligned == 16 * 8 pixel aligned */
656 nbx = round_up(nbx, 16 * 8);
657 /* nby is npipes htiles aligned == npipes * 8 pixel aligned */
658 nby = round_up(nby, track->npipes * 8);
659 } else {
4ac0533a 660 /* always assume 8x8 htile */
88f50c80
JG		 661 /* align is htile align * 8, htile align vary according to
662 * number of pipe and tile width and nby
663 */
664 switch (track->npipes) {
665 case 8:
4ac0533a
JG		 666 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
667 nbx = round_up(nbx, 64 * 8);
668 nby = round_up(nby, 64 * 8);
88f50c80
JG		 669 break;
670 case 4:
4ac0533a
JG		 671 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
672 nbx = round_up(nbx, 64 * 8);
673 nby = round_up(nby, 32 * 8);
88f50c80
JG		 674 break;
675 case 2:
4ac0533a
JG		 676 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
677 nbx = round_up(nbx, 32 * 8);
678 nby = round_up(nby, 32 * 8);
88f50c80
JG		 679 break;
680 case 1:
4ac0533a
JG		 681 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
682 nbx = round_up(nbx, 32 * 8);
683 nby = round_up(nby, 16 * 8);
88f50c80
JG		 684 break;
685 default:
686 dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
687 __func__, __LINE__, track->npipes);
688 return -EINVAL;
689 }
690 }
691 /* compute number of htile */
4ac0533a
JG		 692 nbx = nbx >> 3;
693 nby = nby >> 3;
694 /* size must be aligned on npipes * 2K boundary */
695 size = roundup(nbx * nby * 4, track->npipes * (2 << 10));
88f50c80
JG		 696 size += track->htile_offset;
697
698 if (size > radeon_bo_size(track->htile_bo)) {
699 dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n",
700 __func__, __LINE__, radeon_bo_size(track->htile_bo),
701 size, nbx, nby);
702 return -EINVAL;
703 }
704 }
705
706 track->db_dirty = false;
707 return 0;
708}
709
961fb597
JG		 710static int r600_cs_track_check(struct radeon_cs_parser *p)
711{
712 struct r600_cs_track *track = p->track;
713 u32 tmp;
714 int r, i;
961fb597
JG		 715
716 /* on legacy kernel we don't perform advanced check */
717 if (p->rdev == NULL)
718 return 0;
dd220a00
MO		 719
720 /* check streamout */
3c12513d 721 if (track->streamout_dirty && track->vgt_strmout_en) {
dd220a00
MO		 722 for (i = 0; i < 4; i++) {
723 if (track->vgt_strmout_buffer_en & (1 << i)) {
724 if (track->vgt_strmout_bo[i]) {
725 u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
726 (u64)track->vgt_strmout_size[i];
727 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
728 DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n",
729 i, offset,
730 radeon_bo_size(track->vgt_strmout_bo[i]));
731 return -EINVAL;
732 }
733 } else {
734 dev_warn(p->dev, "No buffer for streamout %d\n", i);
735 return -EINVAL;
736 }
737 }
738 }
3c12513d 739 track->streamout_dirty = false;
961fb597 740 }
dd220a00 741
779923bc
MO		 742 if (track->sx_misc_kill_all_prims)
743 return 0;
744
961fb597
JG		 745 /* check that we have a cb for each enabled target, we don't check
746 * shader_mask because it seems mesa isn't always setting it :(
747 */
3c12513d
MO		 748 if (track->cb_dirty) {
749 tmp = track->cb_target_mask;
523885de
MO		 750
751 /* We must check both colorbuffers for RESOLVE. */
752 if (track->is_resolve) {
753 tmp |= 0xff;
754 }
755
3c12513d
MO		 756 for (i = 0; i < 8; i++) {
757 if ((tmp >> (i * 4)) & 0xF) {
758 /* at least one component is enabled */
759 if (track->cb_color_bo[i] == NULL) {
760 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
761 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
762 return -EINVAL;
763 }
764 /* perform rewrite of CB_COLOR[0-7]_SIZE */
765 r = r600_cs_track_validate_cb(p, i);
766 if (r)
767 return r;
961fb597 768 }
961fb597 769 }
3c12513d 770 track->cb_dirty = false;
961fb597 771 }
3c12513d 772
88f50c80 773 /* Check depth buffer */
0f457e48
MO		 774 if (track->db_dirty &&
775 G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID &&
776 (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
777 G_028800_Z_ENABLE(track->db_depth_control))) {
88f50c80
JG		 778 r = r600_cs_track_validate_db(p);
779 if (r)
780 return r;
961fb597 781 }
88f50c80 782
961fb597
JG		 783 return 0;
784}
785
3ce0a23d
JG		 786/**
787 * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
788 * @parser: parser structure holding parsing context.
789 * @data: pointer to relocation data
790 * @offset_start: starting offset
791 * @offset_mask: offset mask (to align start offset on)
792 * @reloc: reloc informations
793 *
794 * Check next packet is relocation packet3, do bo validation and compute
795 * GPU offset using the provided start.
796 **/
797static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
798 struct radeon_cs_reloc **cs_reloc)
799{
3ce0a23d
JG		 800 struct radeon_cs_chunk *relocs_chunk;
801 struct radeon_cs_packet p3reloc;
802 unsigned idx;
803 int r;
804
805 if (p->chunk_relocs_idx == -1) {
806 DRM_ERROR("No relocation chunk !\n");
807 return -EINVAL;
808 }
809 *cs_reloc = NULL;
3ce0a23d 810 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
c38f34b5 811 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
3ce0a23d
JG		 812 if (r) {
813 return r;
814 }
815 p->idx += p3reloc.count + 2;
816 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
817 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
818 p3reloc.idx);
819 return -EINVAL;
820 }
513bcb46 821 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
3ce0a23d
JG		 822 if (idx >= relocs_chunk->length_dw) {
823 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
824 idx, relocs_chunk->length_dw);
825 return -EINVAL;
826 }
827 /* FIXME: we assume reloc size is 4 dwords */
828 *cs_reloc = p->relocs_ptr[(idx / 4)];
829 return 0;
830}
831
832/**
833 * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
834 * @parser: parser structure holding parsing context.
835 * @data: pointer to relocation data
836 * @offset_start: starting offset
837 * @offset_mask: offset mask (to align start offset on)
838 * @reloc: reloc informations
839 *
840 * Check next packet is relocation packet3, do bo validation and compute
841 * GPU offset using the provided start.
842 **/
843static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
844 struct radeon_cs_reloc **cs_reloc)
845{
3ce0a23d
JG		 846 struct radeon_cs_chunk *relocs_chunk;
847 struct radeon_cs_packet p3reloc;
848 unsigned idx;
849 int r;
850
851 if (p->chunk_relocs_idx == -1) {
852 DRM_ERROR("No relocation chunk !\n");
853 return -EINVAL;
854 }
855 *cs_reloc = NULL;
3ce0a23d 856 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
c38f34b5 857 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
3ce0a23d
JG		 858 if (r) {
859 return r;
860 }
861 p->idx += p3reloc.count + 2;
862 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
863 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
864 p3reloc.idx);
865 return -EINVAL;
866 }
513bcb46 867 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
3ce0a23d
JG		 868 if (idx >= relocs_chunk->length_dw) {
869 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
870 idx, relocs_chunk->length_dw);
871 return -EINVAL;
872 }
e265f39e 873 *cs_reloc = p->relocs;
3ce0a23d
JG		 874 (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
875 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
876 return 0;
877}
878
c8c15ff1
JG		 879/**
880 * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
881 * @parser: parser structure holding parsing context.
882 *
883 * Check next packet is relocation packet3, do bo validation and compute
884 * GPU offset using the provided start.
885 **/
488479eb 886static int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
c8c15ff1
JG		 887{
888 struct radeon_cs_packet p3reloc;
889 int r;
890
c38f34b5 891 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
c8c15ff1
JG		 892 if (r) {
893 return 0;
894 }
895 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
896 return 0;
897 }
898 return 1;
899}
900
2f67c6e0
AD		 901/**
902 * r600_cs_packet_next_vline() - parse userspace VLINE packet
903 * @parser: parser structure holding parsing context.
904 *
905 * Userspace sends a special sequence for VLINE waits.
906 * PACKET0 - VLINE_START_END + value
907 * PACKET3 - WAIT_REG_MEM poll vline status reg
908 * RELOC (P3) - crtc_id in reloc.
909 *
910 * This function parses this and relocates the VLINE START END
911 * and WAIT_REG_MEM packets to the correct crtc.
912 * It also detects a switched off crtc and nulls out the
913 * wait in that case.
914 */
915static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
916{
917 struct drm_mode_object *obj;
918 struct drm_crtc *crtc;
919 struct radeon_crtc *radeon_crtc;
920 struct radeon_cs_packet p3reloc, wait_reg_mem;
921 int crtc_id;
922 int r;
923 uint32_t header, h_idx, reg, wait_reg_mem_info;
924 volatile uint32_t *ib;
925
f2e39221 926 ib = p->ib.ptr;
2f67c6e0
AD		 927
928 /* parse the WAIT_REG_MEM */
c38f34b5 929 r = radeon_cs_packet_parse(p, &wait_reg_mem, p->idx);
2f67c6e0
AD		 930 if (r)
931 return r;
932
933 /* check its a WAIT_REG_MEM */
934 if (wait_reg_mem.type != PACKET_TYPE3 ||
935 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
936 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
a3a88a66 937 return -EINVAL;
2f67c6e0
AD		 938 }
939
940 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
941 /* bit 4 is reg (0) or mem (1) */
942 if (wait_reg_mem_info & 0x10) {
943 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
a3a88a66 944 return -EINVAL;
2f67c6e0
AD		 945 }
946 /* waiting for value to be equal */
947 if ((wait_reg_mem_info & 0x7) != 0x3) {
948 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
a3a88a66 949 return -EINVAL;
2f67c6e0
AD		 950 }
951 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
952 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
a3a88a66 953 return -EINVAL;
2f67c6e0
AD		 954 }
955
956 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
957 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
a3a88a66 958 return -EINVAL;
2f67c6e0
AD		 959 }
960
961 /* jump over the NOP */
c38f34b5 962 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
2f67c6e0
AD		 963 if (r)
964 return r;
965
966 h_idx = p->idx - 2;
967 p->idx += wait_reg_mem.count + 2;
968 p->idx += p3reloc.count + 2;
969
970 header = radeon_get_ib_value(p, h_idx);
971 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
d4ac6a05 972 reg = CP_PACKET0_GET_REG(header);
29508eb6 973
2f67c6e0
AD		 974 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
975 if (!obj) {
976 DRM_ERROR("cannot find crtc %d\n", crtc_id);
a3a88a66 977 return -EINVAL;
2f67c6e0
AD		 978 }
979 crtc = obj_to_crtc(obj);
980 radeon_crtc = to_radeon_crtc(crtc);
981 crtc_id = radeon_crtc->crtc_id;
982
983 if (!crtc->enabled) {
984 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
985 ib[h_idx + 2] = PACKET2(0);
986 ib[h_idx + 3] = PACKET2(0);
987 ib[h_idx + 4] = PACKET2(0);
988 ib[h_idx + 5] = PACKET2(0);
989 ib[h_idx + 6] = PACKET2(0);
990 ib[h_idx + 7] = PACKET2(0);
991 ib[h_idx + 8] = PACKET2(0);
992 } else if (crtc_id == 1) {
993 switch (reg) {
994 case AVIVO_D1MODE_VLINE_START_END:
995 header &= ~R600_CP_PACKET0_REG_MASK;
996 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
997 break;
998 default:
999 DRM_ERROR("unknown crtc reloc\n");
a3a88a66 1000 return -EINVAL;
2f67c6e0
AD		 1001 }
1002 ib[h_idx] = header;
1003 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
1004 }
a3a88a66
PB		 1005
1006 return 0;
2f67c6e0
AD		 1007}
1008
3ce0a23d
JG		 1009static int r600_packet0_check(struct radeon_cs_parser *p,
1010 struct radeon_cs_packet *pkt,
1011 unsigned idx, unsigned reg)
1012{
2f67c6e0
AD		 1013 int r;
1014
3ce0a23d
JG		 1015 switch (reg) {
1016 case AVIVO_D1MODE_VLINE_START_END:
2f67c6e0
AD		 1017 r = r600_cs_packet_parse_vline(p);
1018 if (r) {
1019 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1020 idx, reg);
1021 return r;
1022 }
3ce0a23d
JG		 1023 break;
1024 default:
1025 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1026 reg, idx);
1027 return -EINVAL;
1028 }
1029 return 0;
1030}
1031
1032static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
1033 struct radeon_cs_packet *pkt)
1034{
1035 unsigned reg, i;
1036 unsigned idx;
1037 int r;
1038
1039 idx = pkt->idx + 1;
1040 reg = pkt->reg;
1041 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
1042 r = r600_packet0_check(p, pkt, idx, reg);
1043 if (r) {
1044 return r;
1045 }
1046 }
1047 return 0;
1048}
1049
961fb597
JG		 1050/**
1051 * r600_cs_check_reg() - check if register is authorized or not
1052 * @parser: parser structure holding parsing context
1053 * @reg: register we are testing
1054 * @idx: index into the cs buffer
1055 *
1056 * This function will test against r600_reg_safe_bm and return 0
1057 * if register is safe. If register is not flag as safe this function
1058 * will test it against a list of register needind special handling.
1059 */
488479eb 1060static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
961fb597
JG		 1061{
1062 struct r600_cs_track *track = (struct r600_cs_track *)p->track;
1063 struct radeon_cs_reloc *reloc;
961fb597
JG		 1064 u32 m, i, tmp, *ib;
1065 int r;
1066
1067 i = (reg >> 7);
88498839 1068 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
961fb597
JG		 1069 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1070 return -EINVAL;
1071 }
1072 m = 1 << ((reg >> 2) & 31);
1073 if (!(r600_reg_safe_bm[i] & m))
1074 return 0;
f2e39221 1075 ib = p->ib.ptr;
961fb597 1076 switch (reg) {
25985edc 1077 /* force following reg to 0 in an attempt to disable out buffer
961fb597
JG		 1078 * which will need us to better understand how it works to perform
1079 * security check on it (Jerome)
1080 */
1081 case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
1082 case R_008C44_SQ_ESGS_RING_SIZE:
1083 case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
1084 case R_008C54_SQ_ESTMP_RING_SIZE:
1085 case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
1086 case R_008C74_SQ_FBUF_RING_SIZE:
1087 case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
1088 case R_008C5C_SQ_GSTMP_RING_SIZE:
1089 case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
1090 case R_008C4C_SQ_GSVS_RING_SIZE:
1091 case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
1092 case R_008C6C_SQ_PSTMP_RING_SIZE:
1093 case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
1094 case R_008C7C_SQ_REDUC_RING_SIZE:
1095 case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
1096 case R_008C64_SQ_VSTMP_RING_SIZE:
1097 case R_0288C8_SQ_GS_VERT_ITEMSIZE:
1098 /* get value to populate the IB don't remove */
1099 tmp =radeon_get_ib_value(p, idx);
1100 ib[idx] = 0;
1101 break;
5f77df36
AD		 1102 case SQ_CONFIG:
1103 track->sq_config = radeon_get_ib_value(p, idx);
1104 break;
961fb597
JG		 1105 case R_028800_DB_DEPTH_CONTROL:
1106 track->db_depth_control = radeon_get_ib_value(p, idx);
3c12513d 1107 track->db_dirty = true;
961fb597
JG		 1108 break;
1109 case R_028010_DB_DEPTH_INFO:
721604a1 1110 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
e70f224c 1111 r600_cs_packet_next_is_pkt3_nop(p)) {
7f813377
AD		 1112 r = r600_cs_packet_next_reloc(p, &reloc);
1113 if (r) {
1114 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1115 "0x%04X\n", reg);
1116 return -EINVAL;
1117 }
1118 track->db_depth_info = radeon_get_ib_value(p, idx);
1119 ib[idx] &= C_028010_ARRAY_MODE;
1120 track->db_depth_info &= C_028010_ARRAY_MODE;
1121 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1122 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1123 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1124 } else {
1125 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1126 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1127 }
3c12513d 1128 } else {
7f813377 1129 track->db_depth_info = radeon_get_ib_value(p, idx);
3c12513d
MO		 1130 }
1131 track->db_dirty = true;
961fb597
JG		 1132 break;
1133 case R_028004_DB_DEPTH_VIEW:
1134 track->db_depth_view = radeon_get_ib_value(p, idx);
3c12513d 1135 track->db_dirty = true;
961fb597
JG		 1136 break;
1137 case R_028000_DB_DEPTH_SIZE:
1138 track->db_depth_size = radeon_get_ib_value(p, idx);
1139 track->db_depth_size_idx = idx;
3c12513d 1140 track->db_dirty = true;
961fb597
JG		 1141 break;
1142 case R_028AB0_VGT_STRMOUT_EN:
1143 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
3c12513d 1144 track->streamout_dirty = true;
961fb597
JG		 1145 break;
1146 case R_028B20_VGT_STRMOUT_BUFFER_EN:
1147 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
3c12513d 1148 track->streamout_dirty = true;
961fb597 1149 break;
dd220a00
MO		 1150 case VGT_STRMOUT_BUFFER_BASE_0:
1151 case VGT_STRMOUT_BUFFER_BASE_1:
1152 case VGT_STRMOUT_BUFFER_BASE_2:
1153 case VGT_STRMOUT_BUFFER_BASE_3:
1154 r = r600_cs_packet_next_reloc(p, &reloc);
1155 if (r) {
1156 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1157 "0x%04X\n", reg);
1158 return -EINVAL;
1159 }
1160 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
1161 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1162 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1163 track->vgt_strmout_bo[tmp] = reloc->robj;
1164 track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset;
3c12513d 1165 track->streamout_dirty = true;
dd220a00
MO		 1166 break;
1167 case VGT_STRMOUT_BUFFER_SIZE_0:
1168 case VGT_STRMOUT_BUFFER_SIZE_1:
1169 case VGT_STRMOUT_BUFFER_SIZE_2:
1170 case VGT_STRMOUT_BUFFER_SIZE_3:
1171 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
1172 /* size in register is DWs, convert to bytes */
1173 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
3c12513d 1174 track->streamout_dirty = true;
dd220a00
MO		 1175 break;
1176 case CP_COHER_BASE:
1177 r = r600_cs_packet_next_reloc(p, &reloc);
1178 if (r) {
1179 dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1180 "0x%04X\n", reg);
1181 return -EINVAL;
1182 }
1183 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1184 break;
961fb597
JG		 1185 case R_028238_CB_TARGET_MASK:
1186 track->cb_target_mask = radeon_get_ib_value(p, idx);
3c12513d 1187 track->cb_dirty = true;
961fb597
JG		 1188 break;
1189 case R_02823C_CB_SHADER_MASK:
1190 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1191 break;
1192 case R_028C04_PA_SC_AA_CONFIG:
1193 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
c116cc94 1194 track->log_nsamples = tmp;
961fb597 1195 track->nsamples = 1 << tmp;
3c12513d 1196 track->cb_dirty = true;
961fb597 1197 break;
523885de
MO		 1198 case R_028808_CB_COLOR_CONTROL:
1199 tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx));
1200 track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX;
1201 track->cb_dirty = true;
1202 break;
961fb597
JG		 1203 case R_0280A0_CB_COLOR0_INFO:
1204 case R_0280A4_CB_COLOR1_INFO:
1205 case R_0280A8_CB_COLOR2_INFO:
1206 case R_0280AC_CB_COLOR3_INFO:
1207 case R_0280B0_CB_COLOR4_INFO:
1208 case R_0280B4_CB_COLOR5_INFO:
1209 case R_0280B8_CB_COLOR6_INFO:
1210 case R_0280BC_CB_COLOR7_INFO:
721604a1 1211 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
e70f224c 1212 r600_cs_packet_next_is_pkt3_nop(p)) {
7f813377
AD		 1213 r = r600_cs_packet_next_reloc(p, &reloc);
1214 if (r) {
1215 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1216 return -EINVAL;
1217 }
1218 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1219 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1220 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1221 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1222 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1223 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1224 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1225 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1226 }
1227 } else {
1228 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1229 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1230 }
3c12513d 1231 track->cb_dirty = true;
961fb597 1232 break;
285484e2
JG		 1233 case R_028080_CB_COLOR0_VIEW:
1234 case R_028084_CB_COLOR1_VIEW:
1235 case R_028088_CB_COLOR2_VIEW:
1236 case R_02808C_CB_COLOR3_VIEW:
1237 case R_028090_CB_COLOR4_VIEW:
1238 case R_028094_CB_COLOR5_VIEW:
1239 case R_028098_CB_COLOR6_VIEW:
1240 case R_02809C_CB_COLOR7_VIEW:
1241 tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4;
1242 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
3c12513d 1243 track->cb_dirty = true;
285484e2 1244 break;
961fb597
JG		 1245 case R_028060_CB_COLOR0_SIZE:
1246 case R_028064_CB_COLOR1_SIZE:
1247 case R_028068_CB_COLOR2_SIZE:
1248 case R_02806C_CB_COLOR3_SIZE:
1249 case R_028070_CB_COLOR4_SIZE:
1250 case R_028074_CB_COLOR5_SIZE:
1251 case R_028078_CB_COLOR6_SIZE:
1252 case R_02807C_CB_COLOR7_SIZE:
1253 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
1254 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
1255 track->cb_color_size_idx[tmp] = idx;
3c12513d 1256 track->cb_dirty = true;
961fb597
JG		 1257 break;
1258 /* This register were added late, there is userspace
1259 * which does provide relocation for those but set
1260 * 0 offset. In order to avoid breaking old userspace
1261 * we detect this and set address to point to last
1262 * CB_COLOR0_BASE, note that if userspace doesn't set
1263 * CB_COLOR0_BASE before this register we will report
1264 * error. Old userspace always set CB_COLOR0_BASE
1265 * before any of this.
1266 */
1267 case R_0280E0_CB_COLOR0_FRAG:
1268 case R_0280E4_CB_COLOR1_FRAG:
1269 case R_0280E8_CB_COLOR2_FRAG:
1270 case R_0280EC_CB_COLOR3_FRAG:
1271 case R_0280F0_CB_COLOR4_FRAG:
1272 case R_0280F4_CB_COLOR5_FRAG:
1273 case R_0280F8_CB_COLOR6_FRAG:
1274 case R_0280FC_CB_COLOR7_FRAG:
1275 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
1276 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1277 if (!track->cb_color_base_last[tmp]) {
1278 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1279 return -EINVAL;
1280 }
961fb597 1281 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
c116cc94
MO		 1282 track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp];
1283 ib[idx] = track->cb_color_base_last[tmp];
961fb597
JG		 1284 } else {
1285 r = r600_cs_packet_next_reloc(p, &reloc);
1286 if (r) {
1287 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1288 return -EINVAL;
1289 }
961fb597 1290 track->cb_color_frag_bo[tmp] = reloc->robj;
c116cc94
MO		 1291 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;
1292 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1293 }
1294 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1295 track->cb_dirty = true;
961fb597
JG		 1296 }
1297 break;
1298 case R_0280C0_CB_COLOR0_TILE:
1299 case R_0280C4_CB_COLOR1_TILE:
1300 case R_0280C8_CB_COLOR2_TILE:
1301 case R_0280CC_CB_COLOR3_TILE:
1302 case R_0280D0_CB_COLOR4_TILE:
1303 case R_0280D4_CB_COLOR5_TILE:
1304 case R_0280D8_CB_COLOR6_TILE:
1305 case R_0280DC_CB_COLOR7_TILE:
1306 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
1307 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1308 if (!track->cb_color_base_last[tmp]) {
1309 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1310 return -EINVAL;
1311 }
961fb597 1312 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
c116cc94
MO		 1313 track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp];
1314 ib[idx] = track->cb_color_base_last[tmp];
961fb597
JG		 1315 } else {
1316 r = r600_cs_packet_next_reloc(p, &reloc);
1317 if (r) {
1318 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1319 return -EINVAL;
1320 }
961fb597 1321 track->cb_color_tile_bo[tmp] = reloc->robj;
c116cc94
MO		 1322 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;
1323 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1324 }
1325 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1326 track->cb_dirty = true;
1327 }
1328 break;
1329 case R_028100_CB_COLOR0_MASK:
1330 case R_028104_CB_COLOR1_MASK:
1331 case R_028108_CB_COLOR2_MASK:
1332 case R_02810C_CB_COLOR3_MASK:
1333 case R_028110_CB_COLOR4_MASK:
1334 case R_028114_CB_COLOR5_MASK:
1335 case R_028118_CB_COLOR6_MASK:
1336 case R_02811C_CB_COLOR7_MASK:
1337 tmp = (reg - R_028100_CB_COLOR0_MASK) / 4;
305a3d20 1338 track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);
c116cc94
MO		 1339 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1340 track->cb_dirty = true;
961fb597
JG		 1341 }
1342 break;
1343 case CB_COLOR0_BASE:
1344 case CB_COLOR1_BASE:
1345 case CB_COLOR2_BASE:
1346 case CB_COLOR3_BASE:
1347 case CB_COLOR4_BASE:
1348 case CB_COLOR5_BASE:
1349 case CB_COLOR6_BASE:
1350 case CB_COLOR7_BASE:
1351 r = r600_cs_packet_next_reloc(p, &reloc);
1352 if (r) {
1353 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1354 "0x%04X\n", reg);
1355 return -EINVAL;
1356 }
7cb72ef4 1357 tmp = (reg - CB_COLOR0_BASE) / 4;
1729dd33 1358 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
961fb597 1359 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
961fb597
JG		 1360 track->cb_color_base_last[tmp] = ib[idx];
1361 track->cb_color_bo[tmp] = reloc->robj;
16790569 1362 track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset;
3c12513d 1363 track->cb_dirty = true;
961fb597
JG		 1364 break;
1365 case DB_DEPTH_BASE:
1366 r = r600_cs_packet_next_reloc(p, &reloc);
1367 if (r) {
1368 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1369 "0x%04X\n", reg);
1370 return -EINVAL;
1371 }
1729dd33 1372 track->db_offset = radeon_get_ib_value(p, idx) << 8;
961fb597
JG		 1373 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1374 track->db_bo = reloc->robj;
16790569 1375 track->db_bo_mc = reloc->lobj.gpu_offset;
3c12513d 1376 track->db_dirty = true;
961fb597
JG		 1377 break;
1378 case DB_HTILE_DATA_BASE:
88f50c80
JG		 1379 r = r600_cs_packet_next_reloc(p, &reloc);
1380 if (r) {
1381 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1382 "0x%04X\n", reg);
1383 return -EINVAL;
1384 }
1385 track->htile_offset = radeon_get_ib_value(p, idx) << 8;
1386 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1387 track->htile_bo = reloc->robj;
1388 track->db_dirty = true;
1389 break;
1390 case DB_HTILE_SURFACE:
1391 track->htile_surface = radeon_get_ib_value(p, idx);
4ac0533a
JG		 1392 /* force 8x8 htile width and height */
1393 ib[idx] |= 3;
88f50c80
JG		 1394 track->db_dirty = true;
1395 break;
961fb597
JG		 1396 case SQ_PGM_START_FS:
1397 case SQ_PGM_START_ES:
1398 case SQ_PGM_START_VS:
1399 case SQ_PGM_START_GS:
1400 case SQ_PGM_START_PS:
5f77df36
AD		 1401 case SQ_ALU_CONST_CACHE_GS_0:
1402 case SQ_ALU_CONST_CACHE_GS_1:
1403 case SQ_ALU_CONST_CACHE_GS_2:
1404 case SQ_ALU_CONST_CACHE_GS_3:
1405 case SQ_ALU_CONST_CACHE_GS_4:
1406 case SQ_ALU_CONST_CACHE_GS_5:
1407 case SQ_ALU_CONST_CACHE_GS_6:
1408 case SQ_ALU_CONST_CACHE_GS_7:
1409 case SQ_ALU_CONST_CACHE_GS_8:
1410 case SQ_ALU_CONST_CACHE_GS_9:
1411 case SQ_ALU_CONST_CACHE_GS_10:
1412 case SQ_ALU_CONST_CACHE_GS_11:
1413 case SQ_ALU_CONST_CACHE_GS_12:
1414 case SQ_ALU_CONST_CACHE_GS_13:
1415 case SQ_ALU_CONST_CACHE_GS_14:
1416 case SQ_ALU_CONST_CACHE_GS_15:
1417 case SQ_ALU_CONST_CACHE_PS_0:
1418 case SQ_ALU_CONST_CACHE_PS_1:
1419 case SQ_ALU_CONST_CACHE_PS_2:
1420 case SQ_ALU_CONST_CACHE_PS_3:
1421 case SQ_ALU_CONST_CACHE_PS_4:
1422 case SQ_ALU_CONST_CACHE_PS_5:
1423 case SQ_ALU_CONST_CACHE_PS_6:
1424 case SQ_ALU_CONST_CACHE_PS_7:
1425 case SQ_ALU_CONST_CACHE_PS_8:
1426 case SQ_ALU_CONST_CACHE_PS_9:
1427 case SQ_ALU_CONST_CACHE_PS_10:
1428 case SQ_ALU_CONST_CACHE_PS_11:
1429 case SQ_ALU_CONST_CACHE_PS_12:
1430 case SQ_ALU_CONST_CACHE_PS_13:
1431 case SQ_ALU_CONST_CACHE_PS_14:
1432 case SQ_ALU_CONST_CACHE_PS_15:
1433 case SQ_ALU_CONST_CACHE_VS_0:
1434 case SQ_ALU_CONST_CACHE_VS_1:
1435 case SQ_ALU_CONST_CACHE_VS_2:
1436 case SQ_ALU_CONST_CACHE_VS_3:
1437 case SQ_ALU_CONST_CACHE_VS_4:
1438 case SQ_ALU_CONST_CACHE_VS_5:
1439 case SQ_ALU_CONST_CACHE_VS_6:
1440 case SQ_ALU_CONST_CACHE_VS_7:
1441 case SQ_ALU_CONST_CACHE_VS_8:
1442 case SQ_ALU_CONST_CACHE_VS_9:
1443 case SQ_ALU_CONST_CACHE_VS_10:
1444 case SQ_ALU_CONST_CACHE_VS_11:
1445 case SQ_ALU_CONST_CACHE_VS_12:
1446 case SQ_ALU_CONST_CACHE_VS_13:
1447 case SQ_ALU_CONST_CACHE_VS_14:
1448 case SQ_ALU_CONST_CACHE_VS_15:
961fb597
JG		 1449 r = r600_cs_packet_next_reloc(p, &reloc);
1450 if (r) {
1451 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1452 "0x%04X\n", reg);
1453 return -EINVAL;
033b5650
AD		 1454 }
1455 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1456 break;
1457 case SX_MEMORY_EXPORT_BASE:
1458 r = r600_cs_packet_next_reloc(p, &reloc);
1459 if (r) {
1460 dev_warn(p->dev, "bad SET_CONFIG_REG "
1461 "0x%04X\n", reg);
1462 return -EINVAL;
961fb597
JG		 1463 }
1464 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1465 break;
779923bc
MO		 1466 case SX_MISC:
1467 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1468 break;
961fb597
JG		 1469 default:
1470 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1471 return -EINVAL;
1472 }
1473 return 0;
1474}
1475
285484e2 1476unsigned r600_mip_minify(unsigned size, unsigned level)
961fb597 1477{
60b212f8
DA		 1478 unsigned val;
1479
1480 val = max(1U, size >> level);
1481 if (level > 0)
1482 val = roundup_pow_of_two(val);
1483 return val;
961fb597
JG		 1484}
1485
60b212f8 1486static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
fcdeefe4 1487 unsigned w0, unsigned h0, unsigned d0, unsigned nsamples, unsigned format,
60b212f8 1488 unsigned block_align, unsigned height_align, unsigned base_align,
40e2a5c1 1489 unsigned *l0_size, unsigned *mipmap_size)
961fb597 1490{
60b212f8
DA		 1491 unsigned offset, i, level;
1492 unsigned width, height, depth, size;
1493 unsigned blocksize;
1494 unsigned nbx, nby;
1495 unsigned nlevels = llevel - blevel + 1;
961fb597 1496
60b212f8 1497 *l0_size = -1;
285484e2 1498 blocksize = r600_fmt_get_blocksize(format);
60b212f8 1499
285484e2
JG		 1500 w0 = r600_mip_minify(w0, 0);
1501 h0 = r600_mip_minify(h0, 0);
1502 d0 = r600_mip_minify(d0, 0);
961fb597 1503 for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
285484e2
JG		 1504 width = r600_mip_minify(w0, i);
1505 nbx = r600_fmt_get_nblocksx(format, width);
60b212f8
DA		 1506
1507 nbx = round_up(nbx, block_align);
1508
285484e2
JG		 1509 height = r600_mip_minify(h0, i);
1510 nby = r600_fmt_get_nblocksy(format, height);
60b212f8
DA		 1511 nby = round_up(nby, height_align);
1512
285484e2 1513 depth = r600_mip_minify(d0, i);
60b212f8 1514
fcdeefe4 1515 size = nbx * nby * blocksize * nsamples;
60b212f8
DA		 1516 if (nfaces)
1517 size *= nfaces;
1518 else
1519 size *= depth;
1520
1521 if (i == 0)
1522 *l0_size = size;
1523
1524 if (i == 0 || i == 1)
1525 offset = round_up(offset, base_align);
1526
1527 offset += size;
961fb597 1528 }
961fb597 1529 *mipmap_size = offset;
60b212f8 1530 if (llevel == 0)
961fb597 1531 *mipmap_size = *l0_size;
1729dd33
AD		 1532 if (!blevel)
1533 *mipmap_size -= *l0_size;
961fb597
JG		 1534}
1535
1536/**
1537 * r600_check_texture_resource() - check if register is authorized or not
1538 * @p: parser structure holding parsing context
1539 * @idx: index into the cs buffer
1540 * @texture: texture's bo structure
1541 * @mipmap: mipmap's bo structure
1542 *
1543 * This function will check that the resource has valid field and that
1544 * the texture and mipmap bo object are big enough to cover this resource.
1545 */
488479eb 1546static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
7f813377
AD		 1547 struct radeon_bo *texture,
1548 struct radeon_bo *mipmap,
16790569
AD		 1549 u64 base_offset,
1550 u64 mip_offset,
7f813377 1551 u32 tiling_flags)
961fb597 1552{
40e2a5c1 1553 struct r600_cs_track *track = p->track;
f00245f1
MO		 1554 u32 dim, nfaces, llevel, blevel, w0, h0, d0;
1555 u32 word0, word1, l0_size, mipmap_size, word2, word3, word4, word5;
16790569 1556 u32 height_align, pitch, pitch_align, depth_align;
f00245f1 1557 u32 barray, larray;
16790569
AD		 1558 u64 base_align;
1559 struct array_mode_checker array_check;
60b212f8 1560 u32 format;
f00245f1 1561 bool is_array;
961fb597
JG		 1562
1563 /* on legacy kernel we don't perform advanced check */
1564 if (p->rdev == NULL)
1565 return 0;
7f813377 1566
16790569
AD		 1567 /* convert to bytes */
1568 base_offset <<= 8;
1569 mip_offset <<= 8;
1570
961fb597 1571 word0 = radeon_get_ib_value(p, idx + 0);
721604a1 1572 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
e70f224c
MO		 1573 if (tiling_flags & RADEON_TILING_MACRO)
1574 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1575 else if (tiling_flags & RADEON_TILING_MICRO)
1576 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1577 }
961fb597 1578 word1 = radeon_get_ib_value(p, idx + 1);
f00245f1
MO		 1579 word2 = radeon_get_ib_value(p, idx + 2) << 8;
1580 word3 = radeon_get_ib_value(p, idx + 3) << 8;
1581 word4 = radeon_get_ib_value(p, idx + 4);
1582 word5 = radeon_get_ib_value(p, idx + 5);
1583 dim = G_038000_DIM(word0);
961fb597 1584 w0 = G_038000_TEX_WIDTH(word0) + 1;
f00245f1 1585 pitch = (G_038000_PITCH(word0) + 1) * 8;
961fb597
JG		 1586 h0 = G_038004_TEX_HEIGHT(word1) + 1;
1587 d0 = G_038004_TEX_DEPTH(word1);
f00245f1
MO		 1588 format = G_038004_DATA_FORMAT(word1);
1589 blevel = G_038010_BASE_LEVEL(word4);
1590 llevel = G_038014_LAST_LEVEL(word5);
1591 /* pitch in texels */
1592 array_check.array_mode = G_038000_TILE_MODE(word0);
1593 array_check.group_size = track->group_size;
1594 array_check.nbanks = track->nbanks;
1595 array_check.npipes = track->npipes;
1596 array_check.nsamples = 1;
1597 array_check.blocksize = r600_fmt_get_blocksize(format);
961fb597 1598 nfaces = 1;
f00245f1
MO		 1599 is_array = false;
1600 switch (dim) {
961fb597
JG		 1601 case V_038000_SQ_TEX_DIM_1D:
1602 case V_038000_SQ_TEX_DIM_2D:
1603 case V_038000_SQ_TEX_DIM_3D:
1604 break;
1605 case V_038000_SQ_TEX_DIM_CUBEMAP:
60b212f8
DA		 1606 if (p->family >= CHIP_RV770)
1607 nfaces = 8;
1608 else
1609 nfaces = 6;
961fb597
JG		 1610 break;
1611 case V_038000_SQ_TEX_DIM_1D_ARRAY:
1612 case V_038000_SQ_TEX_DIM_2D_ARRAY:
f00245f1 1613 is_array = true;
60b212f8 1614 break;
961fb597 1615 case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
b51ad12a
MO		 1616 is_array = true;
1617 /* fall through */
1618 case V_038000_SQ_TEX_DIM_2D_MSAA:
1619 array_check.nsamples = 1 << llevel;
1620 llevel = 0;
1621 break;
961fb597
JG		 1622 default:
1623 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1624 return -EINVAL;
1625 }
285484e2 1626 if (!r600_fmt_is_valid_texture(format, p->family)) {
961fb597 1627 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
60b212f8 1628 __func__, __LINE__, format);
961fb597
JG		 1629 return -EINVAL;
1630 }
40e2a5c1 1631
16790569
AD		 1632 if (r600_get_array_mode_alignment(&array_check,
1633 &pitch_align, &height_align, &depth_align, &base_align)) {
1634 dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
1635 __func__, __LINE__, G_038000_TILE_MODE(word0));
1636 return -EINVAL;
1637 }
1638
1639 /* XXX check height as well... */
1640
1641 if (!IS_ALIGNED(pitch, pitch_align)) {
c2049b3d
AD		 1642 dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n",
1643 __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0));
16790569
AD		 1644 return -EINVAL;
1645 }
1646 if (!IS_ALIGNED(base_offset, base_align)) {
c2049b3d
AD		 1647 dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n",
1648 __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0));
16790569
AD		 1649 return -EINVAL;
1650 }
1651 if (!IS_ALIGNED(mip_offset, base_align)) {
c2049b3d
AD		 1652 dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n",
1653 __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0));
40e2a5c1
AD		 1654 return -EINVAL;
1655 }
40e2a5c1 1656
285484e2
JG		 1657 if (blevel > llevel) {
1658 dev_warn(p->dev, "texture blevel %d > llevel %d\n",
1659 blevel, llevel);
1660 }
f00245f1
MO		 1661 if (is_array) {
1662 barray = G_038014_BASE_ARRAY(word5);
1663 larray = G_038014_LAST_ARRAY(word5);
60b212f8
DA		 1664
1665 nfaces = larray - barray + 1;
1666 }
fcdeefe4 1667 r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, array_check.nsamples, format,
60b212f8 1668 pitch_align, height_align, base_align,
40e2a5c1 1669 &l0_size, &mipmap_size);
961fb597 1670 /* using get ib will give us the offset into the texture bo */
af50621a 1671 if ((l0_size + word2) > radeon_bo_size(texture)) {
285484e2
JG		 1672 dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n",
1673 w0, h0, pitch_align, height_align,
1674 array_check.array_mode, format, word2,
1675 l0_size, radeon_bo_size(texture));
60b212f8 1676 dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align);
961fb597
JG		 1677 return -EINVAL;
1678 }
1679 /* using get ib will give us the offset into the mipmap bo */
af50621a 1680 if ((mipmap_size + word3) > radeon_bo_size(mipmap)) {
fe725d4f 1681 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
af50621a 1682 w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/
961fb597
JG		 1683 }
1684 return 0;
1685}
1686
dd220a00
MO		 1687static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1688{
1689 u32 m, i;
1690
1691 i = (reg >> 7);
1692 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
1693 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1694 return false;
1695 }
1696 m = 1 << ((reg >> 2) & 31);
1697 if (!(r600_reg_safe_bm[i] & m))
1698 return true;
1699 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1700 return false;
1701}
1702
3ce0a23d
JG		 1703static int r600_packet3_check(struct radeon_cs_parser *p,
1704 struct radeon_cs_packet *pkt)
1705{
3ce0a23d 1706 struct radeon_cs_reloc *reloc;
c8c15ff1 1707 struct r600_cs_track *track;
3ce0a23d
JG		 1708 volatile u32 *ib;
1709 unsigned idx;
1710 unsigned i;
1711 unsigned start_reg, end_reg, reg;
1712 int r;
adea4796 1713 u32 idx_value;
3ce0a23d 1714
c8c15ff1 1715 track = (struct r600_cs_track *)p->track;
f2e39221 1716 ib = p->ib.ptr;
3ce0a23d 1717 idx = pkt->idx + 1;
adea4796 1718 idx_value = radeon_get_ib_value(p, idx);
513bcb46 1719
3ce0a23d 1720 switch (pkt->opcode) {
2a19cac8
DA		 1721 case PACKET3_SET_PREDICATION:
1722 {
1723 int pred_op;
1724 int tmp;
6333003b
MO		 1725 uint64_t offset;
1726
2a19cac8
DA		 1727 if (pkt->count != 1) {
1728 DRM_ERROR("bad SET PREDICATION\n");
1729 return -EINVAL;
1730 }
1731
1732 tmp = radeon_get_ib_value(p, idx + 1);
1733 pred_op = (tmp >> 16) & 0x7;
1734
1735 /* for the clear predicate operation */
1736 if (pred_op == 0)
1737 return 0;
1738
1739 if (pred_op > 2) {
1740 DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1741 return -EINVAL;
1742 }
1743
1744 r = r600_cs_packet_next_reloc(p, &reloc);
1745 if (r) {
1746 DRM_ERROR("bad SET PREDICATION\n");
1747 return -EINVAL;
1748 }
1749
6333003b
MO		 1750 offset = reloc->lobj.gpu_offset +
1751 (idx_value & 0xfffffff0) +
1752 ((u64)(tmp & 0xff) << 32);
1753
1754 ib[idx + 0] = offset;
1755 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2a19cac8
DA		 1756 }
1757 break;
1758
3ce0a23d
JG		 1759 case PACKET3_START_3D_CMDBUF:
1760 if (p->family >= CHIP_RV770 || pkt->count) {
1761 DRM_ERROR("bad START_3D\n");
1762 return -EINVAL;
1763 }
1764 break;
1765 case PACKET3_CONTEXT_CONTROL:
1766 if (pkt->count != 1) {
1767 DRM_ERROR("bad CONTEXT_CONTROL\n");
1768 return -EINVAL;
1769 }
1770 break;
1771 case PACKET3_INDEX_TYPE:
1772 case PACKET3_NUM_INSTANCES:
1773 if (pkt->count) {
1774 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1775 return -EINVAL;
1776 }
1777 break;
1778 case PACKET3_DRAW_INDEX:
6333003b
MO		 1779 {
1780 uint64_t offset;
3ce0a23d
JG		 1781 if (pkt->count != 3) {
1782 DRM_ERROR("bad DRAW_INDEX\n");
1783 return -EINVAL;
1784 }
1785 r = r600_cs_packet_next_reloc(p, &reloc);
1786 if (r) {
1787 DRM_ERROR("bad DRAW_INDEX\n");
1788 return -EINVAL;
1789 }
6333003b
MO		 1790
1791 offset = reloc->lobj.gpu_offset +
1792 idx_value +
1793 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1794
1795 ib[idx+0] = offset;
1796 ib[idx+1] = upper_32_bits(offset) & 0xff;
1797
961fb597
JG		 1798 r = r600_cs_track_check(p);
1799 if (r) {
1800 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1801 return r;
1802 }
3ce0a23d 1803 break;
6333003b 1804 }
3ce0a23d
JG		 1805 case PACKET3_DRAW_INDEX_AUTO:
1806 if (pkt->count != 1) {
1807 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1808 return -EINVAL;
1809 }
961fb597
JG		 1810 r = r600_cs_track_check(p);
1811 if (r) {
1812 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1813 return r;
1814 }
3ce0a23d
JG		 1815 break;
1816 case PACKET3_DRAW_INDEX_IMMD_BE:
1817 case PACKET3_DRAW_INDEX_IMMD:
1818 if (pkt->count < 2) {
1819 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1820 return -EINVAL;
1821 }
961fb597
JG		 1822 r = r600_cs_track_check(p);
1823 if (r) {
1824 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1825 return r;
1826 }
3ce0a23d
JG		 1827 break;
1828 case PACKET3_WAIT_REG_MEM:
1829 if (pkt->count != 5) {
1830 DRM_ERROR("bad WAIT_REG_MEM\n");
1831 return -EINVAL;
1832 }
1833 /* bit 4 is reg (0) or mem (1) */
adea4796 1834 if (idx_value & 0x10) {
6333003b
MO		 1835 uint64_t offset;
1836
3ce0a23d
JG		 1837 r = r600_cs_packet_next_reloc(p, &reloc);
1838 if (r) {
1839 DRM_ERROR("bad WAIT_REG_MEM\n");
1840 return -EINVAL;
1841 }
6333003b
MO		 1842
1843 offset = reloc->lobj.gpu_offset +
1844 (radeon_get_ib_value(p, idx+1) & 0xfffffff0) +
1845 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1846
1847 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0);
1848 ib[idx+2] = upper_32_bits(offset) & 0xff;
3ce0a23d
JG		 1849 }
1850 break;
6830f585
AD		 1851 case PACKET3_CP_DMA:
1852 {
1853 u32 command, size;
1854 u64 offset, tmp;
1855 if (pkt->count != 4) {
1856 DRM_ERROR("bad CP DMA\n");
1857 return -EINVAL;
1858 }
1859 command = radeon_get_ib_value(p, idx+4);
1860 size = command & 0x1fffff;
1861 if (command & PACKET3_CP_DMA_CMD_SAS) {
1862 /* src address space is register */
1863 DRM_ERROR("CP DMA SAS not supported\n");
1864 return -EINVAL;
1865 } else {
1866 if (command & PACKET3_CP_DMA_CMD_SAIC) {
1867 DRM_ERROR("CP DMA SAIC only supported for registers\n");
1868 return -EINVAL;
1869 }
1870 /* src address space is memory */
1871 r = r600_cs_packet_next_reloc(p, &reloc);
1872 if (r) {
1873 DRM_ERROR("bad CP DMA SRC\n");
1874 return -EINVAL;
1875 }
1876
1877 tmp = radeon_get_ib_value(p, idx) +
1878 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1879
1880 offset = reloc->lobj.gpu_offset + tmp;
1881
1882 if ((tmp + size) > radeon_bo_size(reloc->robj)) {
1883 dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n",
1884 tmp + size, radeon_bo_size(reloc->robj));
1885 return -EINVAL;
1886 }
1887
1888 ib[idx] = offset;
1889 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1890 }
1891 if (command & PACKET3_CP_DMA_CMD_DAS) {
1892 /* dst address space is register */
1893 DRM_ERROR("CP DMA DAS not supported\n");
1894 return -EINVAL;
1895 } else {
1896 /* dst address space is memory */
1897 if (command & PACKET3_CP_DMA_CMD_DAIC) {
1898 DRM_ERROR("CP DMA DAIC only supported for registers\n");
1899 return -EINVAL;
1900 }
1901 r = r600_cs_packet_next_reloc(p, &reloc);
1902 if (r) {
1903 DRM_ERROR("bad CP DMA DST\n");
1904 return -EINVAL;
1905 }
1906
1907 tmp = radeon_get_ib_value(p, idx+2) +
1908 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);
1909
1910 offset = reloc->lobj.gpu_offset + tmp;
1911
1912 if ((tmp + size) > radeon_bo_size(reloc->robj)) {
1913 dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n",
1914 tmp + size, radeon_bo_size(reloc->robj));
1915 return -EINVAL;
1916 }
1917
1918 ib[idx+2] = offset;
1919 ib[idx+3] = upper_32_bits(offset) & 0xff;
1920 }
1921 break;
1922 }
3ce0a23d
JG		 1923 case PACKET3_SURFACE_SYNC:
1924 if (pkt->count != 3) {
1925 DRM_ERROR("bad SURFACE_SYNC\n");
1926 return -EINVAL;
1927 }
1928 /* 0xffffffff/0x0 is flush all cache flag */
513bcb46
DA		 1929 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1930 radeon_get_ib_value(p, idx + 2) != 0) {
3ce0a23d
JG		 1931 r = r600_cs_packet_next_reloc(p, &reloc);
1932 if (r) {
1933 DRM_ERROR("bad SURFACE_SYNC\n");
1934 return -EINVAL;
1935 }
1936 ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1937 }
1938 break;
1939 case PACKET3_EVENT_WRITE:
1940 if (pkt->count != 2 && pkt->count != 0) {
1941 DRM_ERROR("bad EVENT_WRITE\n");
1942 return -EINVAL;
1943 }
1944 if (pkt->count) {
6333003b
MO		 1945 uint64_t offset;
1946
3ce0a23d
JG		 1947 r = r600_cs_packet_next_reloc(p, &reloc);
1948 if (r) {
1949 DRM_ERROR("bad EVENT_WRITE\n");
1950 return -EINVAL;
1951 }
6333003b
MO		 1952 offset = reloc->lobj.gpu_offset +
1953 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
1954 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1955
1956 ib[idx+1] = offset & 0xfffffff8;
1957 ib[idx+2] = upper_32_bits(offset) & 0xff;
3ce0a23d
JG		 1958 }
1959 break;
1960 case PACKET3_EVENT_WRITE_EOP:
6333003b
MO		 1961 {
1962 uint64_t offset;
1963
3ce0a23d
JG		 1964 if (pkt->count != 4) {
1965 DRM_ERROR("bad EVENT_WRITE_EOP\n");
1966 return -EINVAL;
1967 }
1968 r = r600_cs_packet_next_reloc(p, &reloc);
1969 if (r) {
1970 DRM_ERROR("bad EVENT_WRITE\n");
1971 return -EINVAL;
1972 }
6333003b
MO		 1973
1974 offset = reloc->lobj.gpu_offset +
1975 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
1976 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1977
1978 ib[idx+1] = offset & 0xfffffffc;
1979 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
3ce0a23d 1980 break;
6333003b 1981 }
3ce0a23d 1982 case PACKET3_SET_CONFIG_REG:
adea4796 1983 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
3ce0a23d
JG		 1984 end_reg = 4 * pkt->count + start_reg - 4;
1985 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
1986 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1987 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1988 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1989 return -EINVAL;
1990 }
1991 for (i = 0; i < pkt->count; i++) {
1992 reg = start_reg + (4 * i);
961fb597
JG		 1993 r = r600_cs_check_reg(p, reg, idx+1+i);
1994 if (r)
1995 return r;
3ce0a23d
JG		 1996 }
1997 break;
1998 case PACKET3_SET_CONTEXT_REG:
adea4796 1999 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
3ce0a23d
JG		 2000 end_reg = 4 * pkt->count + start_reg - 4;
2001 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
2002 (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
2003 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
2004 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
2005 return -EINVAL;
2006 }
2007 for (i = 0; i < pkt->count; i++) {
2008 reg = start_reg + (4 * i);
961fb597
JG		 2009 r = r600_cs_check_reg(p, reg, idx+1+i);
2010 if (r)
2011 return r;
3ce0a23d
JG		 2012 }
2013 break;
2014 case PACKET3_SET_RESOURCE:
2015 if (pkt->count % 7) {
2016 DRM_ERROR("bad SET_RESOURCE\n");
2017 return -EINVAL;
2018 }
adea4796 2019 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
3ce0a23d
JG		 2020 end_reg = 4 * pkt->count + start_reg - 4;
2021 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
2022 (start_reg >= PACKET3_SET_RESOURCE_END) ||
2023 (end_reg >= PACKET3_SET_RESOURCE_END)) {
2024 DRM_ERROR("bad SET_RESOURCE\n");
2025 return -EINVAL;
2026 }
2027 for (i = 0; i < (pkt->count / 7); i++) {
961fb597 2028 struct radeon_bo *texture, *mipmap;
1729dd33 2029 u32 size, offset, base_offset, mip_offset;
961fb597 2030
adea4796 2031 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
3ce0a23d
JG		 2032 case SQ_TEX_VTX_VALID_TEXTURE:
2033 /* tex base */
2034 r = r600_cs_packet_next_reloc(p, &reloc);
2035 if (r) {
2036 DRM_ERROR("bad SET_RESOURCE\n");
2037 return -EINVAL;
2038 }
1729dd33 2039 base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
721604a1 2040 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
e70f224c
MO		 2041 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
2042 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
2043 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
2044 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
2045 }
961fb597 2046 texture = reloc->robj;
3ce0a23d
JG		 2047 /* tex mip base */
2048 r = r600_cs_packet_next_reloc(p, &reloc);
2049 if (r) {
2050 DRM_ERROR("bad SET_RESOURCE\n");
2051 return -EINVAL;
2052 }
1729dd33 2053 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
961fb597
JG		 2054 mipmap = reloc->robj;
2055 r = r600_check_texture_resource(p, idx+(i*7)+1,
16790569
AD		 2056 texture, mipmap,
2057 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),
2058 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),
2059 reloc->lobj.tiling_flags);
961fb597
JG		 2060 if (r)
2061 return r;
1729dd33
AD		 2062 ib[idx+1+(i*7)+2] += base_offset;
2063 ib[idx+1+(i*7)+3] += mip_offset;
3ce0a23d
JG		 2064 break;
2065 case SQ_TEX_VTX_VALID_BUFFER:
6333003b
MO		 2066 {
2067 uint64_t offset64;
3ce0a23d
JG		 2068 /* vtx base */
2069 r = r600_cs_packet_next_reloc(p, &reloc);
2070 if (r) {
2071 DRM_ERROR("bad SET_RESOURCE\n");
2072 return -EINVAL;
2073 }
961fb597 2074 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
1729dd33 2075 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
961fb597
JG		 2076 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2077 /* force size to size of the buffer */
1729dd33
AD		 2078 dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
2079 size + offset, radeon_bo_size(reloc->robj));
6333003b 2080 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset;
961fb597 2081 }
6333003b
MO		 2082
2083 offset64 = reloc->lobj.gpu_offset + offset;
2084 ib[idx+1+(i*8)+0] = offset64;
2085 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |
2086 (upper_32_bits(offset64) & 0xff);
3ce0a23d 2087 break;
6333003b 2088 }
3ce0a23d
JG		 2089 case SQ_TEX_VTX_INVALID_TEXTURE:
2090 case SQ_TEX_VTX_INVALID_BUFFER:
2091 default:
2092 DRM_ERROR("bad SET_RESOURCE\n");
2093 return -EINVAL;
2094 }
2095 }
2096 break;
2097 case PACKET3_SET_ALU_CONST:
5f77df36
AD		 2098 if (track->sq_config & DX9_CONSTS) {
2099 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
2100 end_reg = 4 * pkt->count + start_reg - 4;
2101 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
2102 (start_reg >= PACKET3_SET_ALU_CONST_END) ||
2103 (end_reg >= PACKET3_SET_ALU_CONST_END)) {
2104 DRM_ERROR("bad SET_ALU_CONST\n");
2105 return -EINVAL;
2106 }
3ce0a23d
JG		 2107 }
2108 break;
2109 case PACKET3_SET_BOOL_CONST:
adea4796 2110 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
3ce0a23d
JG		 2111 end_reg = 4 * pkt->count + start_reg - 4;
2112 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
2113 (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
2114 (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
2115 DRM_ERROR("bad SET_BOOL_CONST\n");
2116 return -EINVAL;
2117 }
2118 break;
2119 case PACKET3_SET_LOOP_CONST:
adea4796 2120 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
3ce0a23d
JG		 2121 end_reg = 4 * pkt->count + start_reg - 4;
2122 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
2123 (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
2124 (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
2125 DRM_ERROR("bad SET_LOOP_CONST\n");
2126 return -EINVAL;
2127 }
2128 break;
2129 case PACKET3_SET_CTL_CONST:
adea4796 2130 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
3ce0a23d
JG		 2131 end_reg = 4 * pkt->count + start_reg - 4;
2132 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
2133 (start_reg >= PACKET3_SET_CTL_CONST_END) ||
2134 (end_reg >= PACKET3_SET_CTL_CONST_END)) {
2135 DRM_ERROR("bad SET_CTL_CONST\n");
2136 return -EINVAL;
2137 }
2138 break;
2139 case PACKET3_SET_SAMPLER:
2140 if (pkt->count % 3) {
2141 DRM_ERROR("bad SET_SAMPLER\n");
2142 return -EINVAL;
2143 }
adea4796 2144 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
3ce0a23d
JG		 2145 end_reg = 4 * pkt->count + start_reg - 4;
2146 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
2147 (start_reg >= PACKET3_SET_SAMPLER_END) ||
2148 (end_reg >= PACKET3_SET_SAMPLER_END)) {
2149 DRM_ERROR("bad SET_SAMPLER\n");
2150 return -EINVAL;
2151 }
2152 break;
7c77bf2a 2153 case PACKET3_STRMOUT_BASE_UPDATE:
46fc8781
MO		 2154 /* RS780 and RS880 also need this */
2155 if (p->family < CHIP_RS780) {
7c77bf2a
AD		 2156 DRM_ERROR("STRMOUT_BASE_UPDATE only supported on 7xx\n");
2157 return -EINVAL;
2158 }
2159 if (pkt->count != 1) {
2160 DRM_ERROR("bad STRMOUT_BASE_UPDATE packet count\n");
2161 return -EINVAL;
2162 }
2163 if (idx_value > 3) {
2164 DRM_ERROR("bad STRMOUT_BASE_UPDATE index\n");
2165 return -EINVAL;
2166 }
2167 {
2168 u64 offset;
2169
2170 r = r600_cs_packet_next_reloc(p, &reloc);
2171 if (r) {
2172 DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n");
2173 return -EINVAL;
2174 }
2175
2176 if (reloc->robj != track->vgt_strmout_bo[idx_value]) {
2177 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo does not match\n");
2178 return -EINVAL;
2179 }
2180
2181 offset = radeon_get_ib_value(p, idx+1) << 8;
2182 if (offset != track->vgt_strmout_bo_offset[idx_value]) {
2183 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%llx, 0x%x\n",
2184 offset, track->vgt_strmout_bo_offset[idx_value]);
2185 return -EINVAL;
2186 }
2187
2188 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2189 DRM_ERROR("bad STRMOUT_BASE_UPDATE bo too small: 0x%llx, 0x%lx\n",
2190 offset + 4, radeon_bo_size(reloc->robj));
2191 return -EINVAL;
2192 }
2193 ib[idx+1] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2194 }
2195 break;
3ce0a23d
JG		 2196 case PACKET3_SURFACE_BASE_UPDATE:
2197 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
2198 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
2199 return -EINVAL;
2200 }
2201 if (pkt->count) {
2202 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
2203 return -EINVAL;
2204 }
2205 break;
dd220a00
MO		 2206 case PACKET3_STRMOUT_BUFFER_UPDATE:
2207 if (pkt->count != 4) {
2208 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");
2209 return -EINVAL;
2210 }
2211 /* Updating memory at DST_ADDRESS. */
2212 if (idx_value & 0x1) {
2213 u64 offset;
2214 r = r600_cs_packet_next_reloc(p, &reloc);
2215 if (r) {
2216 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2217 return -EINVAL;
2218 }
2219 offset = radeon_get_ib_value(p, idx+1);
2220 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2221 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2222 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n",
2223 offset + 4, radeon_bo_size(reloc->robj));
2224 return -EINVAL;
2225 }
6333003b
MO		 2226 offset += reloc->lobj.gpu_offset;
2227 ib[idx+1] = offset;
2228 ib[idx+2] = upper_32_bits(offset) & 0xff;
dd220a00
MO		 2229 }
2230 /* Reading data from SRC_ADDRESS. */
2231 if (((idx_value >> 1) & 0x3) == 2) {
2232 u64 offset;
2233 r = r600_cs_packet_next_reloc(p, &reloc);
2234 if (r) {
2235 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2236 return -EINVAL;
2237 }
2238 offset = radeon_get_ib_value(p, idx+3);
2239 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2240 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2241 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n",
2242 offset + 4, radeon_bo_size(reloc->robj));
2243 return -EINVAL;
2244 }
6333003b
MO		 2245 offset += reloc->lobj.gpu_offset;
2246 ib[idx+3] = offset;
2247 ib[idx+4] = upper_32_bits(offset) & 0xff;
dd220a00
MO		 2248 }
2249 break;
4613ca14
JG		 2250 case PACKET3_MEM_WRITE:
2251 {
2252 u64 offset;
2253
2254 if (pkt->count != 3) {
2255 DRM_ERROR("bad MEM_WRITE (invalid count)\n");
2256 return -EINVAL;
2257 }
2258 r = r600_cs_packet_next_reloc(p, &reloc);
2259 if (r) {
2260 DRM_ERROR("bad MEM_WRITE (missing reloc)\n");
2261 return -EINVAL;
2262 }
2263 offset = radeon_get_ib_value(p, idx+0);
2264 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;
2265 if (offset & 0x7) {
2266 DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n");
2267 return -EINVAL;
2268 }
2269 if ((offset + 8) > radeon_bo_size(reloc->robj)) {
2270 DRM_ERROR("bad MEM_WRITE bo too small: 0x%llx, 0x%lx\n",
2271 offset + 8, radeon_bo_size(reloc->robj));
2272 return -EINVAL;
2273 }
2274 offset += reloc->lobj.gpu_offset;
2275 ib[idx+0] = offset;
2276 ib[idx+1] = upper_32_bits(offset) & 0xff;
2277 break;
2278 }
dd220a00
MO		 2279 case PACKET3_COPY_DW:
2280 if (pkt->count != 4) {
2281 DRM_ERROR("bad COPY_DW (invalid count)\n");
2282 return -EINVAL;
2283 }
2284 if (idx_value & 0x1) {
2285 u64 offset;
2286 /* SRC is memory. */
2287 r = r600_cs_packet_next_reloc(p, &reloc);
2288 if (r) {
2289 DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2290 return -EINVAL;
2291 }
2292 offset = radeon_get_ib_value(p, idx+1);
2293 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2294 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2295 DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n",
2296 offset + 4, radeon_bo_size(reloc->robj));
2297 return -EINVAL;
2298 }
6333003b
MO		 2299 offset += reloc->lobj.gpu_offset;
2300 ib[idx+1] = offset;
2301 ib[idx+2] = upper_32_bits(offset) & 0xff;
dd220a00
MO		 2302 } else {
2303 /* SRC is a reg. */
2304 reg = radeon_get_ib_value(p, idx+1) << 2;
2305 if (!r600_is_safe_reg(p, reg, idx+1))
2306 return -EINVAL;
2307 }
2308 if (idx_value & 0x2) {
2309 u64 offset;
2310 /* DST is memory. */
2311 r = r600_cs_packet_next_reloc(p, &reloc);
2312 if (r) {
2313 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2314 return -EINVAL;
2315 }
2316 offset = radeon_get_ib_value(p, idx+3);
2317 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2318 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2319 DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n",
2320 offset + 4, radeon_bo_size(reloc->robj));
2321 return -EINVAL;
2322 }
6333003b
MO		 2323 offset += reloc->lobj.gpu_offset;
2324 ib[idx+3] = offset;
2325 ib[idx+4] = upper_32_bits(offset) & 0xff;
dd220a00
MO		 2326 } else {
2327 /* DST is a reg. */
2328 reg = radeon_get_ib_value(p, idx+3) << 2;
2329 if (!r600_is_safe_reg(p, reg, idx+3))
2330 return -EINVAL;
2331 }
2332 break;
3ce0a23d
JG		 2333 case PACKET3_NOP:
2334 break;
2335 default:
2336 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2337 return -EINVAL;
2338 }
2339 return 0;
2340}
2341
2342int r600_cs_parse(struct radeon_cs_parser *p)
2343{
2344 struct radeon_cs_packet pkt;
c8c15ff1 2345 struct r600_cs_track *track;
3ce0a23d
JG		 2346 int r;
2347
961fb597
JG		 2348 if (p->track == NULL) {
2349 /* initialize tracker, we are in kms */
2350 track = kzalloc(sizeof(*track), GFP_KERNEL);
2351 if (track == NULL)
2352 return -ENOMEM;
2353 r600_cs_track_init(track);
2354 if (p->rdev->family < CHIP_RV770) {
2355 track->npipes = p->rdev->config.r600.tiling_npipes;
2356 track->nbanks = p->rdev->config.r600.tiling_nbanks;
2357 track->group_size = p->rdev->config.r600.tiling_group_size;
2358 } else if (p->rdev->family <= CHIP_RV740) {
2359 track->npipes = p->rdev->config.rv770.tiling_npipes;
2360 track->nbanks = p->rdev->config.rv770.tiling_nbanks;
2361 track->group_size = p->rdev->config.rv770.tiling_group_size;
2362 }
2363 p->track = track;
2364 }
3ce0a23d 2365 do {
c38f34b5 2366 r = radeon_cs_packet_parse(p, &pkt, p->idx);
3ce0a23d 2367 if (r) {
7cb72ef4
JG		 2368 kfree(p->track);
2369 p->track = NULL;
3ce0a23d
JG		 2370 return r;
2371 }
2372 p->idx += pkt.count + 2;
2373 switch (pkt.type) {
2374 case PACKET_TYPE0:
2375 r = r600_cs_parse_packet0(p, &pkt);
2376 break;
2377 case PACKET_TYPE2:
2378 break;
2379 case PACKET_TYPE3:
2380 r = r600_packet3_check(p, &pkt);
2381 break;
2382 default:
2383 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
961fb597 2384 kfree(p->track);
7cb72ef4 2385 p->track = NULL;
3ce0a23d
JG		 2386 return -EINVAL;
2387 }
2388 if (r) {
961fb597 2389 kfree(p->track);
7cb72ef4 2390 p->track = NULL;
3ce0a23d
JG		 2391 return r;
2392 }
2393 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2394#if 0
f2e39221
JG		 2395 for (r = 0; r < p->ib.length_dw; r++) {
2396 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]);
3ce0a23d
JG		 2397 mdelay(1);
2398 }
2399#endif
961fb597 2400 kfree(p->track);
7cb72ef4 2401 p->track = NULL;
3ce0a23d
JG		 2402 return 0;
2403}
2404
2405static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
2406{
2407 if (p->chunk_relocs_idx == -1) {
2408 return 0;
2409 }
e265f39e 2410 p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
3ce0a23d
JG		 2411 if (p->relocs == NULL) {
2412 return -ENOMEM;
2413 }
2414 return 0;
2415}
2416
2417/**
2418 * cs_parser_fini() - clean parser states
2419 * @parser: parser structure holding parsing context.
2420 * @error: error number
2421 *
2422 * If error is set than unvalidate buffer, otherwise just free memory
2423 * used by parsing context.
2424 **/
2425static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
2426{
2427 unsigned i;
2428
2429 kfree(parser->relocs);
2430 for (i = 0; i < parser->nchunks; i++) {
2431 kfree(parser->chunks[i].kdata);
a6b7e1a0
IH		 2432 if (parser->rdev && (parser->rdev->flags & RADEON_IS_AGP)) {
2433 kfree(parser->chunks[i].kpage[0]);
2434 kfree(parser->chunks[i].kpage[1]);
2435 }
3ce0a23d
JG		 2436 }
2437 kfree(parser->chunks);
2438 kfree(parser->chunks_array);
2439}
2440
2441int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
2442 unsigned family, u32 *ib, int *l)
2443{
2444 struct radeon_cs_parser parser;
2445 struct radeon_cs_chunk *ib_chunk;
961fb597 2446 struct r600_cs_track *track;
3ce0a23d
JG		 2447 int r;
2448
961fb597
JG		 2449 /* initialize tracker */
2450 track = kzalloc(sizeof(*track), GFP_KERNEL);
2451 if (track == NULL)
2452 return -ENOMEM;
2453 r600_cs_track_init(track);
2454 r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
3ce0a23d
JG		 2455 /* initialize parser */
2456 memset(&parser, 0, sizeof(struct radeon_cs_parser));
2457 parser.filp = filp;
c8c15ff1 2458 parser.dev = &dev->pdev->dev;
3ce0a23d
JG		 2459 parser.rdev = NULL;
2460 parser.family = family;
961fb597 2461 parser.track = track;
f2e39221 2462 parser.ib.ptr = ib;
3ce0a23d
JG		 2463 r = radeon_cs_parser_init(&parser, data);
2464 if (r) {
2465 DRM_ERROR("Failed to initialize parser !\n");
2466 r600_cs_parser_fini(&parser, r);
2467 return r;
2468 }
2469 r = r600_cs_parser_relocs_legacy(&parser);
2470 if (r) {
2471 DRM_ERROR("Failed to parse relocation !\n");
2472 r600_cs_parser_fini(&parser, r);
2473 return r;
2474 }
2475 /* Copy the packet into the IB, the parser will read from the
2476 * input memory (cached) and write to the IB (which can be
2477 * uncached). */
2478 ib_chunk = &parser.chunks[parser.chunk_ib_idx];
f2e39221
JG		 2479 parser.ib.length_dw = ib_chunk->length_dw;
2480 *l = parser.ib.length_dw;
3ce0a23d
JG		 2481 r = r600_cs_parse(&parser);
2482 if (r) {
2483 DRM_ERROR("Invalid command stream !\n");
2484 r600_cs_parser_fini(&parser, r);
2485 return r;
2486 }
513bcb46
DA		 2487 r = radeon_cs_finish_pages(&parser);
2488 if (r) {
2489 DRM_ERROR("Invalid command stream !\n");
2490 r600_cs_parser_fini(&parser, r);
2491 return r;
2492 }
3ce0a23d
JG		 2493 r600_cs_parser_fini(&parser, r);
2494 return r;
2495}
2496
2497void r600_cs_legacy_init(void)
2498{
2499 r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
2500}
cf4ccd01
AD		 2501
2502/*
2503 * DMA
2504 */
2505/**
2506 * r600_dma_cs_next_reloc() - parse next reloc
2507 * @p: parser structure holding parsing context.
2508 * @cs_reloc: reloc informations
2509 *
2510 * Return the next reloc, do bo validation and compute
2511 * GPU offset using the provided start.
2512 **/
2513int r600_dma_cs_next_reloc(struct radeon_cs_parser *p,
2514 struct radeon_cs_reloc **cs_reloc)
2515{
2516 struct radeon_cs_chunk *relocs_chunk;
2517 unsigned idx;
2518
9305ede6 2519 *cs_reloc = NULL;
cf4ccd01
AD		 2520 if (p->chunk_relocs_idx == -1) {
2521 DRM_ERROR("No relocation chunk !\n");
2522 return -EINVAL;
2523 }
cf4ccd01
AD		 2524 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
2525 idx = p->dma_reloc_idx;
9305ede6 2526 if (idx >= p->nrelocs) {
cf4ccd01 2527 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
9305ede6 2528 idx, p->nrelocs);
cf4ccd01
AD		 2529 return -EINVAL;
2530 }
2531 *cs_reloc = p->relocs_ptr[idx];
2532 p->dma_reloc_idx++;
2533 return 0;
2534}
2535
2536#define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28)
2537#define GET_DMA_COUNT(h) ((h) & 0x0000ffff)
2538#define GET_DMA_T(h) (((h) & 0x00800000) >> 23)
2539
2540/**
2541 * r600_dma_cs_parse() - parse the DMA IB
2542 * @p: parser structure holding parsing context.
2543 *
2544 * Parses the DMA IB from the CS ioctl and updates
2545 * the GPU addresses based on the reloc information and
2546 * checks for errors. (R6xx-R7xx)
2547 * Returns 0 for success and an error on failure.
2548 **/
2549int r600_dma_cs_parse(struct radeon_cs_parser *p)
2550{
2551 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
2552 struct radeon_cs_reloc *src_reloc, *dst_reloc;
2553 u32 header, cmd, count, tiled;
2554 volatile u32 *ib = p->ib.ptr;
2555 u32 idx, idx_value;
2556 u64 src_offset, dst_offset;
2557 int r;
2558
2559 do {
2560 if (p->idx >= ib_chunk->length_dw) {
2561 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
2562 p->idx, ib_chunk->length_dw);
2563 return -EINVAL;
2564 }
2565 idx = p->idx;
2566 header = radeon_get_ib_value(p, idx);
2567 cmd = GET_DMA_CMD(header);
2568 count = GET_DMA_COUNT(header);
2569 tiled = GET_DMA_T(header);
2570
2571 switch (cmd) {
2572 case DMA_PACKET_WRITE:
2573 r = r600_dma_cs_next_reloc(p, &dst_reloc);
2574 if (r) {
2575 DRM_ERROR("bad DMA_PACKET_WRITE\n");
2576 return -EINVAL;
2577 }
2578 if (tiled) {
2579 dst_offset = ib[idx+1];
2580 dst_offset <<= 8;
2581
2582 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2583 p->idx += count + 5;
2584 } else {
2585 dst_offset = ib[idx+1];
2586 dst_offset |= ((u64)(ib[idx+2] & 0xff)) << 32;
2587
2588 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2589 ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2590 p->idx += count + 3;
2591 }
2592 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2593 dev_warn(p->dev, "DMA write buffer too small (%llu %lu)\n",
2594 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2595 return -EINVAL;
2596 }
2597 break;
2598 case DMA_PACKET_COPY:
2599 r = r600_dma_cs_next_reloc(p, &src_reloc);
2600 if (r) {
2601 DRM_ERROR("bad DMA_PACKET_COPY\n");
2602 return -EINVAL;
2603 }
2604 r = r600_dma_cs_next_reloc(p, &dst_reloc);
2605 if (r) {
2606 DRM_ERROR("bad DMA_PACKET_COPY\n");
2607 return -EINVAL;
2608 }
2609 if (tiled) {
2610 idx_value = radeon_get_ib_value(p, idx + 2);
2611 /* detile bit */
2612 if (idx_value & (1 << 31)) {
2613 /* tiled src, linear dst */
2614 src_offset = ib[idx+1];
2615 src_offset <<= 8;
2616 ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
2617
2618 dst_offset = ib[idx+5];
2619 dst_offset |= ((u64)(ib[idx+6] & 0xff)) << 32;
2620 ib[idx+5] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2621 ib[idx+6] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2622 } else {
2623 /* linear src, tiled dst */
2624 src_offset = ib[idx+5];
2625 src_offset |= ((u64)(ib[idx+6] & 0xff)) << 32;
2626 ib[idx+5] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2627 ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2628
2629 dst_offset = ib[idx+1];
2630 dst_offset <<= 8;
2631 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2632 }
2633 p->idx += 7;
2634 } else {
a10fbb42
AD		 2635 if (p->family >= CHIP_RV770) {
2636 src_offset = ib[idx+2];
2637 src_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
2638 dst_offset = ib[idx+1];
2639 dst_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
cf4ccd01 2640
a10fbb42
AD		 2641 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2642 ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2643 ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2644 ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2645 p->idx += 5;
2646 } else {
2647 src_offset = ib[idx+2];
2648 src_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
2649 dst_offset = ib[idx+1];
2650 dst_offset |= ((u64)(ib[idx+3] & 0xff0000)) << 16;
2651
2652 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2653 ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2654 ib[idx+3] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2655 ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff) << 16;
2656 p->idx += 4;
2657 }
cf4ccd01
AD		 2658 }
2659 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2660 dev_warn(p->dev, "DMA copy src buffer too small (%llu %lu)\n",
2661 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2662 return -EINVAL;
2663 }
2664 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2665 dev_warn(p->dev, "DMA write dst buffer too small (%llu %lu)\n",
2666 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2667 return -EINVAL;
2668 }
2669 break;
2670 case DMA_PACKET_CONSTANT_FILL:
2671 if (p->family < CHIP_RV770) {
2672 DRM_ERROR("Constant Fill is 7xx only !\n");
2673 return -EINVAL;
2674 }
2675 r = r600_dma_cs_next_reloc(p, &dst_reloc);
2676 if (r) {
2677 DRM_ERROR("bad DMA_PACKET_WRITE\n");
2678 return -EINVAL;
2679 }
2680 dst_offset = ib[idx+1];
2681 dst_offset |= ((u64)(ib[idx+3] & 0x00ff0000)) << 16;
2682 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2683 dev_warn(p->dev, "DMA constant fill buffer too small (%llu %lu)\n",
2684 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2685 return -EINVAL;
2686 }
2687 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2688 ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) << 16) & 0x00ff0000;
2689 p->idx += 4;
2690 break;
2691 case DMA_PACKET_NOP:
2692 p->idx += 1;
2693 break;
2694 default:
2695 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx);
2696 return -EINVAL;
2697 }
2698 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2699#if 0
2700 for (r = 0; r < p->ib->length_dw; r++) {
2701 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]);
2702 mdelay(1);
2703 }
2704#endif
2705 return 0;
2706}
Linux kernel - Deliverables
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