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drm/radeon: parse the uvd clock voltage deps table
[deliverable/linux.git] / drivers / gpu / drm / radeon / r600_dpm.c
CommitLineData
2e9d4c05
AD		 1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24
25#include "drmP.h"
26#include "radeon.h"
27#include "r600d.h"
28#include "r600_dpm.h"
29#include "atom.h"
30
31const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
32{
33 R600_UTC_DFLT_00,
34 R600_UTC_DFLT_01,
35 R600_UTC_DFLT_02,
36 R600_UTC_DFLT_03,
37 R600_UTC_DFLT_04,
38 R600_UTC_DFLT_05,
39 R600_UTC_DFLT_06,
40 R600_UTC_DFLT_07,
41 R600_UTC_DFLT_08,
42 R600_UTC_DFLT_09,
43 R600_UTC_DFLT_10,
44 R600_UTC_DFLT_11,
45 R600_UTC_DFLT_12,
46 R600_UTC_DFLT_13,
47 R600_UTC_DFLT_14,
48};
49
50const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
51{
52 R600_DTC_DFLT_00,
53 R600_DTC_DFLT_01,
54 R600_DTC_DFLT_02,
55 R600_DTC_DFLT_03,
56 R600_DTC_DFLT_04,
57 R600_DTC_DFLT_05,
58 R600_DTC_DFLT_06,
59 R600_DTC_DFLT_07,
60 R600_DTC_DFLT_08,
61 R600_DTC_DFLT_09,
62 R600_DTC_DFLT_10,
63 R600_DTC_DFLT_11,
64 R600_DTC_DFLT_12,
65 R600_DTC_DFLT_13,
66 R600_DTC_DFLT_14,
67};
68
69void r600_dpm_print_class_info(u32 class, u32 class2)
70{
71 printk("\tui class: ");
72 switch (class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
73 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
74 default:
75 printk("none\n");
76 break;
77 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
78 printk("battery\n");
79 break;
80 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
81 printk("balanced\n");
82 break;
83 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
84 printk("performance\n");
85 break;
86 }
87 printk("\tinternal class: ");
88 if (((class & ~ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 0) &&
89 (class2 == 0))
90 printk("none");
91 else {
92 if (class & ATOM_PPLIB_CLASSIFICATION_BOOT)
93 printk("boot ");
94 if (class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
95 printk("thermal ");
96 if (class & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE)
97 printk("limited_pwr ");
98 if (class & ATOM_PPLIB_CLASSIFICATION_REST)
99 printk("rest ");
100 if (class & ATOM_PPLIB_CLASSIFICATION_FORCED)
101 printk("forced ");
102 if (class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
103 printk("3d_perf ");
104 if (class & ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE)
105 printk("ovrdrv ");
106 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
107 printk("uvd ");
108 if (class & ATOM_PPLIB_CLASSIFICATION_3DLOW)
109 printk("3d_low ");
110 if (class & ATOM_PPLIB_CLASSIFICATION_ACPI)
111 printk("acpi ");
112 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
113 printk("uvd_hd2 ");
114 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
115 printk("uvd_hd ");
116 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
117 printk("uvd_sd ");
118 if (class2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2)
119 printk("limited_pwr2 ");
120 if (class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
121 printk("ulv ");
122 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
123 printk("uvd_mvc ");
124 }
125 printk("\n");
126}
127
128void r600_dpm_print_cap_info(u32 caps)
129{
130 printk("\tcaps: ");
131 if (caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
132 printk("single_disp ");
133 if (caps & ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK)
134 printk("video ");
135 if (caps & ATOM_PPLIB_DISALLOW_ON_DC)
136 printk("no_dc ");
137 printk("\n");
138}
139
140void r600_dpm_print_ps_status(struct radeon_device *rdev,
141 struct radeon_ps *rps)
142{
143 printk("\tstatus: ");
144 if (rps == rdev->pm.dpm.current_ps)
145 printk("c ");
146 if (rps == rdev->pm.dpm.requested_ps)
147 printk("r ");
148 if (rps == rdev->pm.dpm.boot_ps)
149 printk("b ");
150 printk("\n");
151}
152
66edc1c9
AD		 153u32 r600_dpm_get_vblank_time(struct radeon_device *rdev)
154{
155 struct drm_device *dev = rdev->ddev;
156 struct drm_crtc *crtc;
157 struct radeon_crtc *radeon_crtc;
158 u32 line_time_us, vblank_lines;
159 u32 vblank_time_us = 0xffffffff; /* if the displays are off, vblank time is max */
160
161 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
162 radeon_crtc = to_radeon_crtc(crtc);
163 if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {
164 line_time_us = (radeon_crtc->hw_mode.crtc_htotal * 1000) /
165 radeon_crtc->hw_mode.clock;
166 vblank_lines = radeon_crtc->hw_mode.crtc_vblank_end -
167 radeon_crtc->hw_mode.crtc_vdisplay +
168 (radeon_crtc->v_border * 2);
169 vblank_time_us = vblank_lines * line_time_us;
170 break;
171 }
172 }
173
174 return vblank_time_us;
175}
176
2e9d4c05
AD		 177void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
178 u32 *p, u32 *u)
179{
180 u32 b_c = 0;
181 u32 i_c;
182 u32 tmp;
183
184 i_c = (i * r_c) / 100;
185 tmp = i_c >> p_b;
186
187 while (tmp) {
188 b_c++;
189 tmp >>= 1;
190 }
191
192 *u = (b_c + 1) / 2;
193 *p = i_c / (1 << (2 * (*u)));
194}
195
196int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
197{
198 u32 k, a, ah, al;
199 u32 t1;
200
201 if ((fl == 0) || (fh == 0) || (fl > fh))
202 return -EINVAL;
203
204 k = (100 * fh) / fl;
205 t1 = (t * (k - 100));
206 a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
207 a = (a + 5) / 10;
208 ah = ((a * t) + 5000) / 10000;
209 al = a - ah;
210
211 *th = t - ah;
212 *tl = t + al;
213
214 return 0;
215}
216
217void r600_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)
218{
219 int i;
220
221 if (enable) {
222 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
223 } else {
224 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
225
226 WREG32(CG_RLC_REQ_AND_RSP, 0x2);
227
228 for (i = 0; i < rdev->usec_timeout; i++) {
229 if (((RREG32(CG_RLC_REQ_AND_RSP) & CG_RLC_RSP_TYPE_MASK) >> CG_RLC_RSP_TYPE_SHIFT) == 1)
230 break;
231 udelay(1);
232 }
233
234 WREG32(CG_RLC_REQ_AND_RSP, 0x0);
235
236 WREG32(GRBM_PWR_CNTL, 0x1);
237 RREG32(GRBM_PWR_CNTL);
238 }
239}
240
241void r600_dynamicpm_enable(struct radeon_device *rdev, bool enable)
242{
243 if (enable)
244 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
245 else
246 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
247}
248
249void r600_enable_thermal_protection(struct radeon_device *rdev, bool enable)
250{
251 if (enable)
252 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
253 else
254 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
255}
256
257void r600_enable_acpi_pm(struct radeon_device *rdev)
258{
259 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
260}
261
262void r600_enable_dynamic_pcie_gen2(struct radeon_device *rdev, bool enable)
263{
264 if (enable)
265 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
266 else
267 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
268}
269
270bool r600_dynamicpm_enabled(struct radeon_device *rdev)
271{
272 if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN)
273 return true;
274 else
275 return false;
276}
277
278void r600_enable_sclk_control(struct radeon_device *rdev, bool enable)
279{
280 if (enable)
f5d9b7f0 281 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
2e9d4c05 282 else
f5d9b7f0 283 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
2e9d4c05
AD		 284}
285
286void r600_enable_mclk_control(struct radeon_device *rdev, bool enable)
287{
288 if (enable)
289 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);
290 else
291 WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);
292}
293
294void r600_enable_spll_bypass(struct radeon_device *rdev, bool enable)
295{
296 if (enable)
297 WREG32_P(CG_SPLL_FUNC_CNTL, SPLL_BYPASS_EN, ~SPLL_BYPASS_EN);
298 else
299 WREG32_P(CG_SPLL_FUNC_CNTL, 0, ~SPLL_BYPASS_EN);
300}
301
302void r600_wait_for_spll_change(struct radeon_device *rdev)
303{
304 int i;
305
306 for (i = 0; i < rdev->usec_timeout; i++) {
307 if (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_CHG_STATUS)
308 break;
309 udelay(1);
310 }
311}
312
313void r600_set_bsp(struct radeon_device *rdev, u32 u, u32 p)
314{
315 WREG32(CG_BSP, BSP(p) | BSU(u));
316}
317
318void r600_set_at(struct radeon_device *rdev,
319 u32 l_to_m, u32 m_to_h,
320 u32 h_to_m, u32 m_to_l)
321{
322 WREG32(CG_RT, FLS(l_to_m) | FMS(m_to_h));
323 WREG32(CG_LT, FHS(h_to_m) | FMS(m_to_l));
324}
325
326void r600_set_tc(struct radeon_device *rdev,
327 u32 index, u32 u_t, u32 d_t)
328{
329 WREG32(CG_FFCT_0 + (index * 4), UTC_0(u_t) | DTC_0(d_t));
330}
331
332void r600_select_td(struct radeon_device *rdev,
333 enum r600_td td)
334{
335 if (td == R600_TD_AUTO)
336 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
337 else
338 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
339 if (td == R600_TD_UP)
340 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
341 if (td == R600_TD_DOWN)
342 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
343}
344
345void r600_set_vrc(struct radeon_device *rdev, u32 vrv)
346{
347 WREG32(CG_FTV, vrv);
348}
349
350void r600_set_tpu(struct radeon_device *rdev, u32 u)
351{
352 WREG32_P(CG_TPC, TPU(u), ~TPU_MASK);
353}
354
355void r600_set_tpc(struct radeon_device *rdev, u32 c)
356{
357 WREG32_P(CG_TPC, TPCC(c), ~TPCC_MASK);
358}
359
360void r600_set_sstu(struct radeon_device *rdev, u32 u)
361{
362 WREG32_P(CG_SSP, CG_SSTU(u), ~CG_SSTU_MASK);
363}
364
365void r600_set_sst(struct radeon_device *rdev, u32 t)
366{
367 WREG32_P(CG_SSP, CG_SST(t), ~CG_SST_MASK);
368}
369
370void r600_set_git(struct radeon_device *rdev, u32 t)
371{
372 WREG32_P(CG_GIT, CG_GICST(t), ~CG_GICST_MASK);
373}
374
375void r600_set_fctu(struct radeon_device *rdev, u32 u)
376{
377 WREG32_P(CG_FC_T, FC_TU(u), ~FC_TU_MASK);
378}
379
380void r600_set_fct(struct radeon_device *rdev, u32 t)
381{
382 WREG32_P(CG_FC_T, FC_T(t), ~FC_T_MASK);
383}
384
385void r600_set_ctxcgtt3d_rphc(struct radeon_device *rdev, u32 p)
386{
387 WREG32_P(CG_CTX_CGTT3D_R, PHC(p), ~PHC_MASK);
388}
389
390void r600_set_ctxcgtt3d_rsdc(struct radeon_device *rdev, u32 s)
391{
392 WREG32_P(CG_CTX_CGTT3D_R, SDC(s), ~SDC_MASK);
393}
394
395void r600_set_vddc3d_oorsu(struct radeon_device *rdev, u32 u)
396{
397 WREG32_P(CG_VDDC3D_OOR, SU(u), ~SU_MASK);
398}
399
400void r600_set_vddc3d_oorphc(struct radeon_device *rdev, u32 p)
401{
402 WREG32_P(CG_VDDC3D_OOR, PHC(p), ~PHC_MASK);
403}
404
405void r600_set_vddc3d_oorsdc(struct radeon_device *rdev, u32 s)
406{
407 WREG32_P(CG_VDDC3D_OOR, SDC(s), ~SDC_MASK);
408}
409
410void r600_set_mpll_lock_time(struct radeon_device *rdev, u32 lock_time)
411{
412 WREG32_P(MPLL_TIME, MPLL_LOCK_TIME(lock_time), ~MPLL_LOCK_TIME_MASK);
413}
414
415void r600_set_mpll_reset_time(struct radeon_device *rdev, u32 reset_time)
416{
417 WREG32_P(MPLL_TIME, MPLL_RESET_TIME(reset_time), ~MPLL_RESET_TIME_MASK);
418}
419
420void r600_engine_clock_entry_enable(struct radeon_device *rdev,
421 u32 index, bool enable)
422{
423 if (enable)
424 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
425 STEP_0_SPLL_ENTRY_VALID, ~STEP_0_SPLL_ENTRY_VALID);
426 else
427 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
428 0, ~STEP_0_SPLL_ENTRY_VALID);
429}
430
431void r600_engine_clock_entry_enable_pulse_skipping(struct radeon_device *rdev,
432 u32 index, bool enable)
433{
434 if (enable)
435 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
436 STEP_0_SPLL_STEP_ENABLE, ~STEP_0_SPLL_STEP_ENABLE);
437 else
438 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
439 0, ~STEP_0_SPLL_STEP_ENABLE);
440}
441
442void r600_engine_clock_entry_enable_post_divider(struct radeon_device *rdev,
443 u32 index, bool enable)
444{
445 if (enable)
446 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
447 STEP_0_POST_DIV_EN, ~STEP_0_POST_DIV_EN);
448 else
449 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART2 + (index * 4 * 2),
450 0, ~STEP_0_POST_DIV_EN);
451}
452
453void r600_engine_clock_entry_set_post_divider(struct radeon_device *rdev,
454 u32 index, u32 divider)
455{
456 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),
457 STEP_0_SPLL_POST_DIV(divider), ~STEP_0_SPLL_POST_DIV_MASK);
458}
459
460void r600_engine_clock_entry_set_reference_divider(struct radeon_device *rdev,
461 u32 index, u32 divider)
462{
463 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),
464 STEP_0_SPLL_REF_DIV(divider), ~STEP_0_SPLL_REF_DIV_MASK);
465}
466
467void r600_engine_clock_entry_set_feedback_divider(struct radeon_device *rdev,
468 u32 index, u32 divider)
469{
470 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),
471 STEP_0_SPLL_FB_DIV(divider), ~STEP_0_SPLL_FB_DIV_MASK);
472}
473
474void r600_engine_clock_entry_set_step_time(struct radeon_device *rdev,
475 u32 index, u32 step_time)
476{
477 WREG32_P(SCLK_FREQ_SETTING_STEP_0_PART1 + (index * 4 * 2),
478 STEP_0_SPLL_STEP_TIME(step_time), ~STEP_0_SPLL_STEP_TIME_MASK);
479}
480
481void r600_vid_rt_set_ssu(struct radeon_device *rdev, u32 u)
482{
483 WREG32_P(VID_RT, SSTU(u), ~SSTU_MASK);
484}
485
486void r600_vid_rt_set_vru(struct radeon_device *rdev, u32 u)
487{
488 WREG32_P(VID_RT, VID_CRTU(u), ~VID_CRTU_MASK);
489}
490
491void r600_vid_rt_set_vrt(struct radeon_device *rdev, u32 rt)
492{
493 WREG32_P(VID_RT, VID_CRT(rt), ~VID_CRT_MASK);
494}
495
496void r600_voltage_control_enable_pins(struct radeon_device *rdev,
497 u64 mask)
498{
499 WREG32(LOWER_GPIO_ENABLE, mask & 0xffffffff);
500 WREG32(UPPER_GPIO_ENABLE, upper_32_bits(mask));
501}
502
503
504void r600_voltage_control_program_voltages(struct radeon_device *rdev,
505 enum r600_power_level index, u64 pins)
506{
507 u32 tmp, mask;
508 u32 ix = 3 - (3 & index);
509
510 WREG32(CTXSW_VID_LOWER_GPIO_CNTL + (ix * 4), pins & 0xffffffff);
511
512 mask = 7 << (3 * ix);
513 tmp = RREG32(VID_UPPER_GPIO_CNTL);
514 tmp = (tmp & ~mask) | ((pins >> (32 - (3 * ix))) & mask);
515 WREG32(VID_UPPER_GPIO_CNTL, tmp);
516}
517
518void r600_voltage_control_deactivate_static_control(struct radeon_device *rdev,
519 u64 mask)
520{
521 u32 gpio;
522
523 gpio = RREG32(GPIOPAD_MASK);
524 gpio &= ~mask;
525 WREG32(GPIOPAD_MASK, gpio);
526
527 gpio = RREG32(GPIOPAD_EN);
528 gpio &= ~mask;
529 WREG32(GPIOPAD_EN, gpio);
530
531 gpio = RREG32(GPIOPAD_A);
532 gpio &= ~mask;
533 WREG32(GPIOPAD_A, gpio);
534}
535
536void r600_power_level_enable(struct radeon_device *rdev,
537 enum r600_power_level index, bool enable)
538{
539 u32 ix = 3 - (3 & index);
540
541 if (enable)
542 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), CTXSW_FREQ_STATE_ENABLE,
543 ~CTXSW_FREQ_STATE_ENABLE);
544 else
545 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), 0,
546 ~CTXSW_FREQ_STATE_ENABLE);
547}
548
549void r600_power_level_set_voltage_index(struct radeon_device *rdev,
550 enum r600_power_level index, u32 voltage_index)
551{
552 u32 ix = 3 - (3 & index);
553
554 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),
555 CTXSW_FREQ_VIDS_CFG_INDEX(voltage_index), ~CTXSW_FREQ_VIDS_CFG_INDEX_MASK);
556}
557
558void r600_power_level_set_mem_clock_index(struct radeon_device *rdev,
559 enum r600_power_level index, u32 mem_clock_index)
560{
561 u32 ix = 3 - (3 & index);
562
563 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),
564 CTXSW_FREQ_MCLK_CFG_INDEX(mem_clock_index), ~CTXSW_FREQ_MCLK_CFG_INDEX_MASK);
565}
566
567void r600_power_level_set_eng_clock_index(struct radeon_device *rdev,
568 enum r600_power_level index, u32 eng_clock_index)
569{
570 u32 ix = 3 - (3 & index);
571
572 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4),
573 CTXSW_FREQ_SCLK_CFG_INDEX(eng_clock_index), ~CTXSW_FREQ_SCLK_CFG_INDEX_MASK);
574}
575
576void r600_power_level_set_watermark_id(struct radeon_device *rdev,
577 enum r600_power_level index,
578 enum r600_display_watermark watermark_id)
579{
580 u32 ix = 3 - (3 & index);
581 u32 tmp = 0;
582
583 if (watermark_id == R600_DISPLAY_WATERMARK_HIGH)
584 tmp = CTXSW_FREQ_DISPLAY_WATERMARK;
585 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_DISPLAY_WATERMARK);
586}
587
588void r600_power_level_set_pcie_gen2(struct radeon_device *rdev,
589 enum r600_power_level index, bool compatible)
590{
591 u32 ix = 3 - (3 & index);
592 u32 tmp = 0;
593
594 if (compatible)
595 tmp = CTXSW_FREQ_GEN2PCIE_VOLT;
596 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), tmp, ~CTXSW_FREQ_GEN2PCIE_VOLT);
597}
598
599enum r600_power_level r600_power_level_get_current_index(struct radeon_device *rdev)
600{
601 u32 tmp;
602
603 tmp = RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK;
604 tmp >>= CURRENT_PROFILE_INDEX_SHIFT;
605 return tmp;
606}
607
608enum r600_power_level r600_power_level_get_target_index(struct radeon_device *rdev)
609{
610 u32 tmp;
611
612 tmp = RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_PROFILE_INDEX_MASK;
613 tmp >>= TARGET_PROFILE_INDEX_SHIFT;
614 return tmp;
615}
616
617void r600_power_level_set_enter_index(struct radeon_device *rdev,
618 enum r600_power_level index)
619{
620 WREG32_P(TARGET_AND_CURRENT_PROFILE_INDEX, DYN_PWR_ENTER_INDEX(index),
621 ~DYN_PWR_ENTER_INDEX_MASK);
622}
623
624void r600_wait_for_power_level_unequal(struct radeon_device *rdev,
625 enum r600_power_level index)
626{
627 int i;
628
629 for (i = 0; i < rdev->usec_timeout; i++) {
630 if (r600_power_level_get_target_index(rdev) != index)
631 break;
632 udelay(1);
633 }
634
635 for (i = 0; i < rdev->usec_timeout; i++) {
636 if (r600_power_level_get_current_index(rdev) != index)
637 break;
638 udelay(1);
639 }
640}
641
642void r600_wait_for_power_level(struct radeon_device *rdev,
643 enum r600_power_level index)
644{
645 int i;
646
647 for (i = 0; i < rdev->usec_timeout; i++) {
648 if (r600_power_level_get_target_index(rdev) == index)
649 break;
650 udelay(1);
651 }
652
653 for (i = 0; i < rdev->usec_timeout; i++) {
654 if (r600_power_level_get_current_index(rdev) == index)
655 break;
656 udelay(1);
657 }
658}
659
660void r600_start_dpm(struct radeon_device *rdev)
661{
662 r600_enable_sclk_control(rdev, false);
663 r600_enable_mclk_control(rdev, false);
664
665 r600_dynamicpm_enable(rdev, true);
666
667 radeon_wait_for_vblank(rdev, 0);
668 radeon_wait_for_vblank(rdev, 1);
669
670 r600_enable_spll_bypass(rdev, true);
671 r600_wait_for_spll_change(rdev);
672 r600_enable_spll_bypass(rdev, false);
673 r600_wait_for_spll_change(rdev);
674
675 r600_enable_spll_bypass(rdev, true);
676 r600_wait_for_spll_change(rdev);
677 r600_enable_spll_bypass(rdev, false);
678 r600_wait_for_spll_change(rdev);
679
680 r600_enable_sclk_control(rdev, true);
681 r600_enable_mclk_control(rdev, true);
682}
683
684void r600_stop_dpm(struct radeon_device *rdev)
685{
686 r600_dynamicpm_enable(rdev, false);
687}
688
98243917
AD		 689int r600_dpm_pre_set_power_state(struct radeon_device *rdev)
690{
691 return 0;
692}
693
694void r600_dpm_post_set_power_state(struct radeon_device *rdev)
695{
696
697}
698
2e9d4c05
AD		 699bool r600_is_uvd_state(u32 class, u32 class2)
700{
701 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
702 return true;
703 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
704 return true;
705 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
706 return true;
707 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
708 return true;
709 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
710 return true;
711 return false;
712}
4a6369e9
AD		 713
714int r600_set_thermal_temperature_range(struct radeon_device *rdev,
715 int min_temp, int max_temp)
716{
717 int low_temp = 0 * 1000;
718 int high_temp = 255 * 1000;
719
720 if (low_temp < min_temp)
721 low_temp = min_temp;
722 if (high_temp > max_temp)
723 high_temp = max_temp;
724 if (high_temp < low_temp) {
725 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
726 return -EINVAL;
727 }
728
729 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
730 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
731 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
732
733 rdev->pm.dpm.thermal.min_temp = low_temp;
734 rdev->pm.dpm.thermal.max_temp = high_temp;
735
736 return 0;
737}
738
739bool r600_is_internal_thermal_sensor(enum radeon_int_thermal_type sensor)
740{
741 switch (sensor) {
742 case THERMAL_TYPE_RV6XX:
743 case THERMAL_TYPE_RV770:
744 case THERMAL_TYPE_EVERGREEN:
745 case THERMAL_TYPE_SUMO:
746 case THERMAL_TYPE_NI:
ac163387 747 case THERMAL_TYPE_SI:
2aacd48f 748 case THERMAL_TYPE_CI:
12262906 749 case THERMAL_TYPE_KV:
4a6369e9
AD		 750 return true;
751 case THERMAL_TYPE_ADT7473_WITH_INTERNAL:
752 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
753 return false; /* need special handling */
754 case THERMAL_TYPE_NONE:
755 case THERMAL_TYPE_EXTERNAL:
756 case THERMAL_TYPE_EXTERNAL_GPIO:
757 default:
758 return false;
759 }
760}
61b7d601
AD		 761
762union power_info {
763 struct _ATOM_POWERPLAY_INFO info;
764 struct _ATOM_POWERPLAY_INFO_V2 info_2;
765 struct _ATOM_POWERPLAY_INFO_V3 info_3;
766 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
767 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
768 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
769 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
770 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
771};
772
773union fan_info {
774 struct _ATOM_PPLIB_FANTABLE fan;
775 struct _ATOM_PPLIB_FANTABLE2 fan2;
776};
777
778static int r600_parse_clk_voltage_dep_table(struct radeon_clock_voltage_dependency_table *radeon_table,
779 ATOM_PPLIB_Clock_Voltage_Dependency_Table *atom_table)
780{
781 u32 size = atom_table->ucNumEntries *
782 sizeof(struct radeon_clock_voltage_dependency_entry);
783 int i;
784
785 radeon_table->entries = kzalloc(size, GFP_KERNEL);
786 if (!radeon_table->entries)
787 return -ENOMEM;
788
789 for (i = 0; i < atom_table->ucNumEntries; i++) {
790 radeon_table->entries[i].clk = le16_to_cpu(atom_table->entries[i].usClockLow) |
791 (atom_table->entries[i].ucClockHigh << 16);
792 radeon_table->entries[i].v = le16_to_cpu(atom_table->entries[i].usVoltage);
793 }
794 radeon_table->count = atom_table->ucNumEntries;
795
796 return 0;
797}
798
a5cb318e
AD		 799/* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
800#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
801#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
802#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
803#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
804#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
805#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
806
61b7d601
AD		 807int r600_parse_extended_power_table(struct radeon_device *rdev)
808{
809 struct radeon_mode_info *mode_info = &rdev->mode_info;
810 union power_info *power_info;
811 union fan_info *fan_info;
812 ATOM_PPLIB_Clock_Voltage_Dependency_Table *dep_table;
813 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
814 u16 data_offset;
815 u8 frev, crev;
816 int ret, i;
817
818 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
819 &frev, &crev, &data_offset))
820 return -EINVAL;
821 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
822
823 /* fan table */
9985318b
AD		 824 if (le16_to_cpu(power_info->pplib.usTableSize) >=
825 sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE3)) {
61b7d601
AD		 826 if (power_info->pplib3.usFanTableOffset) {
827 fan_info = (union fan_info *)(mode_info->atom_context->bios + data_offset +
828 le16_to_cpu(power_info->pplib3.usFanTableOffset));
829 rdev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst;
830 rdev->pm.dpm.fan.t_min = le16_to_cpu(fan_info->fan.usTMin);
831 rdev->pm.dpm.fan.t_med = le16_to_cpu(fan_info->fan.usTMed);
832 rdev->pm.dpm.fan.t_high = le16_to_cpu(fan_info->fan.usTHigh);
833 rdev->pm.dpm.fan.pwm_min = le16_to_cpu(fan_info->fan.usPWMMin);
834 rdev->pm.dpm.fan.pwm_med = le16_to_cpu(fan_info->fan.usPWMMed);
835 rdev->pm.dpm.fan.pwm_high = le16_to_cpu(fan_info->fan.usPWMHigh);
836 if (fan_info->fan.ucFanTableFormat >= 2)
837 rdev->pm.dpm.fan.t_max = le16_to_cpu(fan_info->fan2.usTMax);
838 else
839 rdev->pm.dpm.fan.t_max = 10900;
840 rdev->pm.dpm.fan.cycle_delay = 100000;
841 rdev->pm.dpm.fan.ucode_fan_control = true;
842 }
843 }
844
929ee7a8 845 /* clock dependancy tables, shedding tables */
9985318b
AD		 846 if (le16_to_cpu(power_info->pplib.usTableSize) >=
847 sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE4)) {
61b7d601
AD		 848 if (power_info->pplib4.usVddcDependencyOnSCLKOffset) {
849 dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
850 (mode_info->atom_context->bios + data_offset +
851 le16_to_cpu(power_info->pplib4.usVddcDependencyOnSCLKOffset));
852 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
853 dep_table);
854 if (ret)
855 return ret;
856 }
857 if (power_info->pplib4.usVddciDependencyOnMCLKOffset) {
858 dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
859 (mode_info->atom_context->bios + data_offset +
860 le16_to_cpu(power_info->pplib4.usVddciDependencyOnMCLKOffset));
861 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
862 dep_table);
863 if (ret) {
864 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
865 return ret;
866 }
867 }
868 if (power_info->pplib4.usVddcDependencyOnMCLKOffset) {
869 dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
870 (mode_info->atom_context->bios + data_offset +
871 le16_to_cpu(power_info->pplib4.usVddcDependencyOnMCLKOffset));
872 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
873 dep_table);
874 if (ret) {
875 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
876 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries);
877 return ret;
878 }
879 }
dd621a22
AD		 880 if (power_info->pplib4.usMvddDependencyOnMCLKOffset) {
881 dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
882 (mode_info->atom_context->bios + data_offset +
883 le16_to_cpu(power_info->pplib4.usMvddDependencyOnMCLKOffset));
884 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
885 dep_table);
886 if (ret) {
887 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
888 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries);
889 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries);
890 return ret;
891 }
892 }
61b7d601
AD		 893 if (power_info->pplib4.usMaxClockVoltageOnDCOffset) {
894 ATOM_PPLIB_Clock_Voltage_Limit_Table *clk_v =
895 (ATOM_PPLIB_Clock_Voltage_Limit_Table *)
896 (mode_info->atom_context->bios + data_offset +
897 le16_to_cpu(power_info->pplib4.usMaxClockVoltageOnDCOffset));
898 if (clk_v->ucNumEntries) {
899 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk =
900 le16_to_cpu(clk_v->entries[0].usSclkLow) |
901 (clk_v->entries[0].ucSclkHigh << 16);
902 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk =
903 le16_to_cpu(clk_v->entries[0].usMclkLow) |
904 (clk_v->entries[0].ucMclkHigh << 16);
905 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc =
906 le16_to_cpu(clk_v->entries[0].usVddc);
907 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci =
908 le16_to_cpu(clk_v->entries[0].usVddci);
909 }
910 }
929ee7a8
AD		 911 if (power_info->pplib4.usVddcPhaseShedLimitsTableOffset) {
912 ATOM_PPLIB_PhaseSheddingLimits_Table *psl =
913 (ATOM_PPLIB_PhaseSheddingLimits_Table *)
914 (mode_info->atom_context->bios + data_offset +
915 le16_to_cpu(power_info->pplib4.usVddcPhaseShedLimitsTableOffset));
916
917 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries =
918 kzalloc(psl->ucNumEntries *
919 sizeof(struct radeon_phase_shedding_limits_entry),
920 GFP_KERNEL);
f907eec0
AD		 921 if (!rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries) {
922 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
923 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries);
924 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries);
dd621a22 925 kfree(rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries);
929ee7a8 926 return -ENOMEM;
f907eec0 927 }
929ee7a8
AD		 928
929 for (i = 0; i < psl->ucNumEntries; i++) {
930 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].sclk =
931 le16_to_cpu(psl->entries[i].usSclkLow) |
932 (psl->entries[i].ucSclkHigh << 16);
933 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].mclk =
934 le16_to_cpu(psl->entries[i].usMclkLow) |
935 (psl->entries[i].ucMclkHigh << 16);
936 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].voltage =
937 le16_to_cpu(psl->entries[i].usVoltage);
938 }
939 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.count =
940 psl->ucNumEntries;
941 }
61b7d601
AD		 942 }
943
944 /* cac data */
9985318b
AD		 945 if (le16_to_cpu(power_info->pplib.usTableSize) >=
946 sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE5)) {
61b7d601
AD		 947 rdev->pm.dpm.tdp_limit = le32_to_cpu(power_info->pplib5.ulTDPLimit);
948 rdev->pm.dpm.near_tdp_limit = le32_to_cpu(power_info->pplib5.ulNearTDPLimit);
a9e61410 949 rdev->pm.dpm.near_tdp_limit_adjusted = rdev->pm.dpm.near_tdp_limit;
61b7d601
AD		 950 rdev->pm.dpm.tdp_od_limit = le16_to_cpu(power_info->pplib5.usTDPODLimit);
951 if (rdev->pm.dpm.tdp_od_limit)
952 rdev->pm.dpm.power_control = true;
953 else
954 rdev->pm.dpm.power_control = false;
955 rdev->pm.dpm.tdp_adjustment = 0;
956 rdev->pm.dpm.sq_ramping_threshold = le32_to_cpu(power_info->pplib5.ulSQRampingThreshold);
957 rdev->pm.dpm.cac_leakage = le32_to_cpu(power_info->pplib5.ulCACLeakage);
958 rdev->pm.dpm.load_line_slope = le16_to_cpu(power_info->pplib5.usLoadLineSlope);
959 if (power_info->pplib5.usCACLeakageTableOffset) {
960 ATOM_PPLIB_CAC_Leakage_Table *cac_table =
961 (ATOM_PPLIB_CAC_Leakage_Table *)
962 (mode_info->atom_context->bios + data_offset +
963 le16_to_cpu(power_info->pplib5.usCACLeakageTableOffset));
964 u32 size = cac_table->ucNumEntries * sizeof(struct radeon_cac_leakage_table);
965 rdev->pm.dpm.dyn_state.cac_leakage_table.entries = kzalloc(size, GFP_KERNEL);
966 if (!rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
967 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
968 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries);
969 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries);
dd621a22 970 kfree(rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries);
61b7d601
AD		 971 return -ENOMEM;
972 }
973 for (i = 0; i < cac_table->ucNumEntries; i++) {
ef976ec4
AD		 974 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
975 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1 =
976 le16_to_cpu(cac_table->entries[i].usVddc1);
977 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2 =
978 le16_to_cpu(cac_table->entries[i].usVddc2);
979 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3 =
980 le16_to_cpu(cac_table->entries[i].usVddc3);
981 } else {
982 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc =
983 le16_to_cpu(cac_table->entries[i].usVddc);
984 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage =
985 le32_to_cpu(cac_table->entries[i].ulLeakageValue);
986 }
61b7d601
AD		 987 }
988 rdev->pm.dpm.dyn_state.cac_leakage_table.count = cac_table->ucNumEntries;
989 }
990 }
991
57ff4761 992 /* ext tables */
a5cb318e
AD		 993 if (le16_to_cpu(power_info->pplib.usTableSize) >=
994 sizeof(struct _ATOM_PPLIB_POWERPLAYTABLE3)) {
995 ATOM_PPLIB_EXTENDEDHEADER *ext_hdr = (ATOM_PPLIB_EXTENDEDHEADER *)
996 (mode_info->atom_context->bios + data_offset +
997 le16_to_cpu(power_info->pplib3.usExtendendedHeaderOffset));
57ff4761
AD		 998 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2) &&
999 ext_hdr->usVCETableOffset) {
1000 VCEClockInfoArray *array = (VCEClockInfoArray *)
1001 (mode_info->atom_context->bios + data_offset +
1002 le16_to_cpu(ext_hdr->usVCETableOffset) + 1);
1003 ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *limits =
1004 (ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table *)
1005 (mode_info->atom_context->bios + data_offset +
1006 le16_to_cpu(ext_hdr->usVCETableOffset) + 1 +
1007 1 + array->ucNumEntries * sizeof(VCEClockInfo));
1008 u32 size = limits->numEntries *
1009 sizeof(struct radeon_vce_clock_voltage_dependency_entry);
1010 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries =
1011 kzalloc(size, GFP_KERNEL);
1012 if (!rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) {
1013 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
1014 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries);
1015 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries);
1016 kfree(rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries);
1017 kfree(rdev->pm.dpm.dyn_state.cac_leakage_table.entries);
1018 return -ENOMEM;
1019 }
1020 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count =
1021 limits->numEntries;
1022 for (i = 0; i < limits->numEntries; i++) {
1023 VCEClockInfo *vce_clk =
1024 &array->entries[limits->entries[i].ucVCEClockInfoIndex];
1025 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk =
1026 le16_to_cpu(vce_clk->usEVClkLow) | (vce_clk->ucEVClkHigh << 16);
1027 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk =
1028 le16_to_cpu(vce_clk->usECClkLow) | (vce_clk->ucECClkHigh << 16);
1029 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v =
1030 le16_to_cpu(limits->entries[i].usVoltage);
1031 }
1032 }
018042b1
AD		 1033 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3) &&
1034 ext_hdr->usUVDTableOffset) {
1035 UVDClockInfoArray *array = (UVDClockInfoArray *)
1036 (mode_info->atom_context->bios + data_offset +
1037 le16_to_cpu(ext_hdr->usUVDTableOffset) + 1);
1038 ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *limits =
1039 (ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table *)
1040 (mode_info->atom_context->bios + data_offset +
1041 le16_to_cpu(ext_hdr->usUVDTableOffset) + 1 +
1042 1 + (array->ucNumEntries * sizeof (UVDClockInfo)));
1043 u32 size = limits->numEntries *
1044 sizeof(struct radeon_uvd_clock_voltage_dependency_entry);
1045 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries =
1046 kzalloc(size, GFP_KERNEL);
1047 if (!rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries) {
1048 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
1049 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries);
1050 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries);
1051 kfree(rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries);
1052 kfree(rdev->pm.dpm.dyn_state.cac_leakage_table.entries);
1053 kfree(rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries);
1054 return -ENOMEM;
1055 }
1056 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count =
1057 limits->numEntries;
1058 for (i = 0; i < limits->numEntries; i++) {
1059 UVDClockInfo *uvd_clk =
1060 &array->entries[limits->entries[i].ucUVDClockInfoIndex];
1061 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].vclk =
1062 le16_to_cpu(uvd_clk->usVClkLow) | (uvd_clk->ucVClkHigh << 16);
1063 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk =
1064 le16_to_cpu(uvd_clk->usDClkLow) | (uvd_clk->ucDClkHigh << 16);
1065 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v =
1066 le16_to_cpu(limits->entries[i].usVoltage);
1067 }
1068 }
a5cb318e
AD		 1069 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5) &&
1070 ext_hdr->usPPMTableOffset) {
1071 ATOM_PPLIB_PPM_Table *ppm = (ATOM_PPLIB_PPM_Table *)
1072 (mode_info->atom_context->bios + data_offset +
1073 le16_to_cpu(ext_hdr->usPPMTableOffset));
1074 rdev->pm.dpm.dyn_state.ppm_table =
1075 kzalloc(sizeof(struct radeon_ppm_table), GFP_KERNEL);
f907eec0
AD		 1076 if (!rdev->pm.dpm.dyn_state.ppm_table) {
1077 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
1078 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries);
1079 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries);
dd621a22 1080 kfree(rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries);
f907eec0 1081 kfree(rdev->pm.dpm.dyn_state.cac_leakage_table.entries);
57ff4761 1082 kfree(rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries);
018042b1 1083 kfree(rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries);
a5cb318e 1084 return -ENOMEM;
f907eec0 1085 }
a5cb318e
AD		 1086 rdev->pm.dpm.dyn_state.ppm_table->ppm_design = ppm->ucPpmDesign;
1087 rdev->pm.dpm.dyn_state.ppm_table->cpu_core_number =
1088 le16_to_cpu(ppm->usCpuCoreNumber);
1089 rdev->pm.dpm.dyn_state.ppm_table->platform_tdp =
1090 le32_to_cpu(ppm->ulPlatformTDP);
1091 rdev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdp =
1092 le32_to_cpu(ppm->ulSmallACPlatformTDP);
1093 rdev->pm.dpm.dyn_state.ppm_table->platform_tdc =
1094 le32_to_cpu(ppm->ulPlatformTDC);
1095 rdev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdc =
1096 le32_to_cpu(ppm->ulSmallACPlatformTDC);
1097 rdev->pm.dpm.dyn_state.ppm_table->apu_tdp =
1098 le32_to_cpu(ppm->ulApuTDP);
1099 rdev->pm.dpm.dyn_state.ppm_table->dgpu_tdp =
1100 le32_to_cpu(ppm->ulDGpuTDP);
1101 rdev->pm.dpm.dyn_state.ppm_table->dgpu_ulv_power =
1102 le32_to_cpu(ppm->ulDGpuUlvPower);
1103 rdev->pm.dpm.dyn_state.ppm_table->tj_max =
1104 le32_to_cpu(ppm->ulTjmax);
1105 }
58cb7632
AD		 1106 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7) &&
1107 ext_hdr->usPowerTuneTableOffset) {
1108 u8 rev = *(u8 *)(mode_info->atom_context->bios + data_offset +
1109 le16_to_cpu(ext_hdr->usPowerTuneTableOffset));
1110 ATOM_PowerTune_Table *pt;
1111 rdev->pm.dpm.dyn_state.cac_tdp_table =
1112 kzalloc(sizeof(struct radeon_cac_tdp_table), GFP_KERNEL);
1113 if (!rdev->pm.dpm.dyn_state.cac_tdp_table) {
1114 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
1115 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries);
1116 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries);
dd621a22 1117 kfree(rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries);
58cb7632
AD		 1118 kfree(rdev->pm.dpm.dyn_state.cac_leakage_table.entries);
1119 kfree(rdev->pm.dpm.dyn_state.ppm_table);
57ff4761 1120 kfree(rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries);
018042b1 1121 kfree(rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries);
58cb7632
AD		 1122 return -ENOMEM;
1123 }
1124 if (rev > 0) {
1125 ATOM_PPLIB_POWERTUNE_Table_V1 *ppt = (ATOM_PPLIB_POWERTUNE_Table_V1 *)
1126 (mode_info->atom_context->bios + data_offset +
1127 le16_to_cpu(ext_hdr->usPowerTuneTableOffset));
1128 rdev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit =
1129 ppt->usMaximumPowerDeliveryLimit;
1130 pt = &ppt->power_tune_table;
1131 } else {
1132 ATOM_PPLIB_POWERTUNE_Table *ppt = (ATOM_PPLIB_POWERTUNE_Table *)
1133 (mode_info->atom_context->bios + data_offset +
1134 le16_to_cpu(ext_hdr->usPowerTuneTableOffset));
1135 rdev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = 255;
1136 pt = &ppt->power_tune_table;
1137 }
1138 rdev->pm.dpm.dyn_state.cac_tdp_table->tdp = le16_to_cpu(pt->usTDP);
1139 rdev->pm.dpm.dyn_state.cac_tdp_table->configurable_tdp =
1140 le16_to_cpu(pt->usConfigurableTDP);
1141 rdev->pm.dpm.dyn_state.cac_tdp_table->tdc = le16_to_cpu(pt->usTDC);
1142 rdev->pm.dpm.dyn_state.cac_tdp_table->battery_power_limit =
1143 le16_to_cpu(pt->usBatteryPowerLimit);
1144 rdev->pm.dpm.dyn_state.cac_tdp_table->small_power_limit =
1145 le16_to_cpu(pt->usSmallPowerLimit);
1146 rdev->pm.dpm.dyn_state.cac_tdp_table->low_cac_leakage =
1147 le16_to_cpu(pt->usLowCACLeakage);
1148 rdev->pm.dpm.dyn_state.cac_tdp_table->high_cac_leakage =
1149 le16_to_cpu(pt->usHighCACLeakage);
1150 }
a5cb318e
AD		 1151 }
1152
61b7d601
AD		 1153 return 0;
1154}
1155
1156void r600_free_extended_power_table(struct radeon_device *rdev)
1157{
1158 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries)
1159 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries);
1160 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries)
1161 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries);
1162 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries)
1163 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries);
dd621a22
AD		 1164 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries)
1165 kfree(rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries);
61b7d601
AD		 1166 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries)
1167 kfree(rdev->pm.dpm.dyn_state.cac_leakage_table.entries);
929ee7a8
AD		 1168 if (rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries)
1169 kfree(rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries);
a5cb318e
AD		 1170 if (rdev->pm.dpm.dyn_state.ppm_table)
1171 kfree(rdev->pm.dpm.dyn_state.ppm_table);
58cb7632
AD		 1172 if (rdev->pm.dpm.dyn_state.cac_tdp_table)
1173 kfree(rdev->pm.dpm.dyn_state.cac_tdp_table);
57ff4761
AD		 1174 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries)
1175 kfree(rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries);
018042b1
AD		 1176 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries)
1177 kfree(rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries);
61b7d601 1178}
4bd9f516
AD		 1179
1180enum radeon_pcie_gen r600_get_pcie_gen_support(struct radeon_device *rdev,
1181 u32 sys_mask,
1182 enum radeon_pcie_gen asic_gen,
1183 enum radeon_pcie_gen default_gen)
1184{
1185 switch (asic_gen) {
1186 case RADEON_PCIE_GEN1:
1187 return RADEON_PCIE_GEN1;
1188 case RADEON_PCIE_GEN2:
1189 return RADEON_PCIE_GEN2;
1190 case RADEON_PCIE_GEN3:
1191 return RADEON_PCIE_GEN3;
1192 default:
1193 if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == RADEON_PCIE_GEN3))
1194 return RADEON_PCIE_GEN3;
1195 else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == RADEON_PCIE_GEN2))
1196 return RADEON_PCIE_GEN2;
1197 else
1198 return RADEON_PCIE_GEN1;
1199 }
1200 return RADEON_PCIE_GEN1;
1201}
Linux kernel - Deliverables
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