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dafc3bd5 CK |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Christian König. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Christian König | |
25 | */ | |
e3b2e034 | 26 | #include <linux/hdmi.h> |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/radeon_drm.h> | |
dafc3bd5 | 29 | #include "radeon.h" |
3574dda4 | 30 | #include "radeon_asic.h" |
c6543a6e | 31 | #include "r600d.h" |
dafc3bd5 CK |
32 | #include "atom.h" |
33 | ||
34 | /* | |
35 | * HDMI color format | |
36 | */ | |
37 | enum r600_hdmi_color_format { | |
38 | RGB = 0, | |
39 | YCC_422 = 1, | |
40 | YCC_444 = 2 | |
41 | }; | |
42 | ||
43 | /* | |
44 | * IEC60958 status bits | |
45 | */ | |
46 | enum r600_hdmi_iec_status_bits { | |
47 | AUDIO_STATUS_DIG_ENABLE = 0x01, | |
3fe373d9 RM |
48 | AUDIO_STATUS_V = 0x02, |
49 | AUDIO_STATUS_VCFG = 0x04, | |
dafc3bd5 CK |
50 | AUDIO_STATUS_EMPHASIS = 0x08, |
51 | AUDIO_STATUS_COPYRIGHT = 0x10, | |
52 | AUDIO_STATUS_NONAUDIO = 0x20, | |
53 | AUDIO_STATUS_PROFESSIONAL = 0x40, | |
3fe373d9 | 54 | AUDIO_STATUS_LEVEL = 0x80 |
dafc3bd5 CK |
55 | }; |
56 | ||
1109ca09 | 57 | static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = { |
dafc3bd5 CK |
58 | /* 32kHz 44.1kHz 48kHz */ |
59 | /* Clock N CTS N CTS N CTS */ | |
60 | { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */ | |
61 | { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ | |
62 | { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ | |
63 | { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ | |
64 | { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ | |
65 | { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ | |
66 | { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */ | |
67 | { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ | |
68 | { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */ | |
69 | { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ | |
70 | { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */ | |
71 | }; | |
72 | ||
73 | /* | |
74 | * calculate CTS value if it's not found in the table | |
75 | */ | |
1b688d08 | 76 | static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq) |
dafc3bd5 CK |
77 | { |
78 | if (*CTS == 0) | |
3fe373d9 | 79 | *CTS = clock * N / (128 * freq) * 1000; |
dafc3bd5 CK |
80 | DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n", |
81 | N, *CTS, freq); | |
82 | } | |
83 | ||
1b688d08 RM |
84 | struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock) |
85 | { | |
86 | struct radeon_hdmi_acr res; | |
87 | u8 i; | |
88 | ||
89 | for (i = 0; r600_hdmi_predefined_acr[i].clock != clock && | |
90 | r600_hdmi_predefined_acr[i].clock != 0; i++) | |
91 | ; | |
92 | res = r600_hdmi_predefined_acr[i]; | |
93 | ||
94 | /* In case some CTS are missing */ | |
95 | r600_hdmi_calc_cts(clock, &res.cts_32khz, res.n_32khz, 32000); | |
96 | r600_hdmi_calc_cts(clock, &res.cts_44_1khz, res.n_44_1khz, 44100); | |
97 | r600_hdmi_calc_cts(clock, &res.cts_48khz, res.n_48khz, 48000); | |
98 | ||
99 | return res; | |
100 | } | |
101 | ||
dafc3bd5 CK |
102 | /* |
103 | * update the N and CTS parameters for a given pixel clock rate | |
104 | */ | |
105 | static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) | |
106 | { | |
107 | struct drm_device *dev = encoder->dev; | |
108 | struct radeon_device *rdev = dev->dev_private; | |
1b688d08 | 109 | struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); |
cfcbd6d3 RM |
110 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
111 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
112 | uint32_t offset = dig->afmt->offset; | |
dafc3bd5 | 113 | |
1b688d08 RM |
114 | WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz)); |
115 | WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz); | |
dafc3bd5 | 116 | |
1b688d08 RM |
117 | WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz)); |
118 | WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz); | |
dafc3bd5 | 119 | |
1b688d08 RM |
120 | WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz)); |
121 | WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz); | |
dafc3bd5 CK |
122 | } |
123 | ||
dafc3bd5 CK |
124 | /* |
125 | * build a HDMI Video Info Frame | |
126 | */ | |
e3b2e034 TR |
127 | static void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, |
128 | void *buffer, size_t size) | |
dafc3bd5 CK |
129 | { |
130 | struct drm_device *dev = encoder->dev; | |
131 | struct radeon_device *rdev = dev->dev_private; | |
cfcbd6d3 RM |
132 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
133 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
134 | uint32_t offset = dig->afmt->offset; | |
e3b2e034 | 135 | uint8_t *frame = buffer + 3; |
f100380e | 136 | uint8_t *header = buffer; |
dafc3bd5 | 137 | |
c6543a6e | 138 | WREG32(HDMI0_AVI_INFO0 + offset, |
dafc3bd5 | 139 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
c6543a6e | 140 | WREG32(HDMI0_AVI_INFO1 + offset, |
dafc3bd5 | 141 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
c6543a6e | 142 | WREG32(HDMI0_AVI_INFO2 + offset, |
dafc3bd5 | 143 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
c6543a6e | 144 | WREG32(HDMI0_AVI_INFO3 + offset, |
f100380e | 145 | frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); |
dafc3bd5 CK |
146 | } |
147 | ||
148 | /* | |
149 | * build a Audio Info Frame | |
150 | */ | |
e3b2e034 TR |
151 | static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder, |
152 | const void *buffer, size_t size) | |
dafc3bd5 CK |
153 | { |
154 | struct drm_device *dev = encoder->dev; | |
155 | struct radeon_device *rdev = dev->dev_private; | |
cfcbd6d3 RM |
156 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
157 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
158 | uint32_t offset = dig->afmt->offset; | |
e3b2e034 | 159 | const u8 *frame = buffer + 3; |
dafc3bd5 | 160 | |
c6543a6e | 161 | WREG32(HDMI0_AUDIO_INFO0 + offset, |
dafc3bd5 | 162 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
c6543a6e | 163 | WREG32(HDMI0_AUDIO_INFO1 + offset, |
dafc3bd5 CK |
164 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24)); |
165 | } | |
166 | ||
167 | /* | |
168 | * test if audio buffer is filled enough to start playing | |
169 | */ | |
cfcbd6d3 | 170 | static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder) |
dafc3bd5 CK |
171 | { |
172 | struct drm_device *dev = encoder->dev; | |
173 | struct radeon_device *rdev = dev->dev_private; | |
cfcbd6d3 RM |
174 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
175 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
176 | uint32_t offset = dig->afmt->offset; | |
dafc3bd5 | 177 | |
c6543a6e | 178 | return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0; |
dafc3bd5 CK |
179 | } |
180 | ||
181 | /* | |
182 | * have buffer status changed since last call? | |
183 | */ | |
184 | int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder) | |
185 | { | |
186 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
cfcbd6d3 | 187 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
dafc3bd5 CK |
188 | int status, result; |
189 | ||
cfcbd6d3 | 190 | if (!dig->afmt || !dig->afmt->enabled) |
dafc3bd5 CK |
191 | return 0; |
192 | ||
193 | status = r600_hdmi_is_audio_buffer_filled(encoder); | |
cfcbd6d3 RM |
194 | result = dig->afmt->last_buffer_filled_status != status; |
195 | dig->afmt->last_buffer_filled_status = status; | |
dafc3bd5 CK |
196 | |
197 | return result; | |
198 | } | |
199 | ||
200 | /* | |
201 | * write the audio workaround status to the hardware | |
202 | */ | |
cfcbd6d3 | 203 | static void r600_hdmi_audio_workaround(struct drm_encoder *encoder) |
dafc3bd5 CK |
204 | { |
205 | struct drm_device *dev = encoder->dev; | |
206 | struct radeon_device *rdev = dev->dev_private; | |
207 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
cfcbd6d3 RM |
208 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
209 | uint32_t offset = dig->afmt->offset; | |
210 | bool hdmi_audio_workaround = false; /* FIXME */ | |
211 | u32 value; | |
212 | ||
213 | if (!hdmi_audio_workaround || | |
214 | r600_hdmi_is_audio_buffer_filled(encoder)) | |
215 | value = 0; /* disable workaround */ | |
216 | else | |
217 | value = HDMI0_AUDIO_TEST_EN; /* enable workaround */ | |
218 | WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, | |
219 | value, ~HDMI0_AUDIO_TEST_EN); | |
dafc3bd5 CK |
220 | } |
221 | ||
b1f6f47e AD |
222 | void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock) |
223 | { | |
224 | struct drm_device *dev = encoder->dev; | |
225 | struct radeon_device *rdev = dev->dev_private; | |
226 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
227 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
731da21b | 228 | u32 base_rate = 24000; |
b1f6f47e AD |
229 | |
230 | if (!dig || !dig->afmt) | |
231 | return; | |
232 | ||
233 | /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT. | |
234 | * doesn't matter which one you use. Just use the first one. | |
235 | */ | |
b1f6f47e AD |
236 | /* XXX two dtos; generally use dto0 for hdmi */ |
237 | /* Express [24MHz / target pixel clock] as an exact rational | |
238 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE | |
239 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator | |
240 | */ | |
1586505a AD |
241 | if (ASIC_IS_DCE3(rdev)) { |
242 | /* according to the reg specs, this should DCE3.2 only, but in | |
243 | * practice it seems to cover DCE3.0 as well. | |
244 | */ | |
731da21b | 245 | WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100); |
1586505a AD |
246 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); |
247 | WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ | |
248 | } else { | |
249 | /* according to the reg specs, this should be DCE2.0 and DCE3.0 */ | |
731da21b AD |
250 | WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) | |
251 | AUDIO_DTO_MODULE(clock / 10)); | |
1586505a | 252 | } |
b1f6f47e | 253 | } |
dafc3bd5 CK |
254 | |
255 | /* | |
256 | * update the info frames with the data from the current display mode | |
257 | */ | |
258 | void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) | |
259 | { | |
260 | struct drm_device *dev = encoder->dev; | |
261 | struct radeon_device *rdev = dev->dev_private; | |
cfcbd6d3 RM |
262 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
263 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
e3b2e034 TR |
264 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; |
265 | struct hdmi_avi_infoframe frame; | |
cfcbd6d3 | 266 | uint32_t offset; |
e3b2e034 | 267 | ssize_t err; |
dafc3bd5 | 268 | |
cfcbd6d3 RM |
269 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
270 | if (!dig->afmt->enabled) | |
dafc3bd5 | 271 | return; |
cfcbd6d3 | 272 | offset = dig->afmt->offset; |
dafc3bd5 | 273 | |
b1f6f47e | 274 | r600_audio_set_dto(encoder, mode->clock); |
dafc3bd5 | 275 | |
1c3439f2 RM |
276 | WREG32(HDMI0_VBI_PACKET_CONTROL + offset, |
277 | HDMI0_NULL_SEND); /* send null packets when required */ | |
278 | ||
c6543a6e | 279 | WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); |
a273a903 | 280 | |
1c3439f2 RM |
281 | if (ASIC_IS_DCE32(rdev)) { |
282 | WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, | |
283 | HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ | |
284 | HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ | |
285 | WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, | |
286 | AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */ | |
287 | AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ | |
288 | } else { | |
289 | WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, | |
290 | HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ | |
291 | HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ | |
1c3439f2 RM |
292 | HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */ |
293 | HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ | |
294 | } | |
a273a903 | 295 | |
1c3439f2 RM |
296 | WREG32(HDMI0_ACR_PACKET_CONTROL + offset, |
297 | HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ | |
298 | HDMI0_ACR_SOURCE); /* select SW CTS value */ | |
dafc3bd5 | 299 | |
1c3439f2 RM |
300 | WREG32(HDMI0_VBI_PACKET_CONTROL + offset, |
301 | HDMI0_NULL_SEND | /* send null packets when required */ | |
302 | HDMI0_GC_SEND | /* send general control packets */ | |
303 | HDMI0_GC_CONT); /* send general control packets every frame */ | |
dafc3bd5 | 304 | |
1c3439f2 RM |
305 | /* TODO: HDMI0_AUDIO_INFO_UPDATE */ |
306 | WREG32(HDMI0_INFOFRAME_CONTROL0 + offset, | |
307 | HDMI0_AVI_INFO_SEND | /* enable AVI info frames */ | |
308 | HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */ | |
309 | HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ | |
310 | HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */ | |
dafc3bd5 | 311 | |
1c3439f2 RM |
312 | WREG32(HDMI0_INFOFRAME_CONTROL1 + offset, |
313 | HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */ | |
314 | HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */ | |
315 | ||
316 | WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */ | |
dafc3bd5 | 317 | |
e3b2e034 TR |
318 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); |
319 | if (err < 0) { | |
320 | DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); | |
321 | return; | |
322 | } | |
dafc3bd5 | 323 | |
e3b2e034 TR |
324 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); |
325 | if (err < 0) { | |
326 | DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); | |
327 | return; | |
328 | } | |
329 | ||
330 | r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); | |
1c3439f2 RM |
331 | r600_hdmi_update_ACR(encoder, mode->clock); |
332 | ||
25985edc | 333 | /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ |
c6543a6e RM |
334 | WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF); |
335 | WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF); | |
336 | WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001); | |
337 | WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); | |
dafc3bd5 CK |
338 | |
339 | r600_hdmi_audio_workaround(encoder); | |
dafc3bd5 CK |
340 | } |
341 | ||
342 | /* | |
343 | * update settings with current parameters from audio engine | |
344 | */ | |
58bd0863 | 345 | void r600_hdmi_update_audio_settings(struct drm_encoder *encoder) |
dafc3bd5 CK |
346 | { |
347 | struct drm_device *dev = encoder->dev; | |
348 | struct radeon_device *rdev = dev->dev_private; | |
cfcbd6d3 RM |
349 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
350 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
3299de95 | 351 | struct r600_audio audio = r600_audio_status(rdev); |
e3b2e034 TR |
352 | uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; |
353 | struct hdmi_audio_infoframe frame; | |
cfcbd6d3 | 354 | uint32_t offset; |
dafc3bd5 | 355 | uint32_t iec; |
e3b2e034 | 356 | ssize_t err; |
dafc3bd5 | 357 | |
cfcbd6d3 | 358 | if (!dig->afmt || !dig->afmt->enabled) |
dafc3bd5 | 359 | return; |
cfcbd6d3 | 360 | offset = dig->afmt->offset; |
dafc3bd5 CK |
361 | |
362 | DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n", | |
363 | r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped", | |
3299de95 | 364 | audio.channels, audio.rate, audio.bits_per_sample); |
dafc3bd5 | 365 | DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n", |
3299de95 | 366 | (int)audio.status_bits, (int)audio.category_code); |
dafc3bd5 CK |
367 | |
368 | iec = 0; | |
3299de95 | 369 | if (audio.status_bits & AUDIO_STATUS_PROFESSIONAL) |
dafc3bd5 | 370 | iec |= 1 << 0; |
3299de95 | 371 | if (audio.status_bits & AUDIO_STATUS_NONAUDIO) |
dafc3bd5 | 372 | iec |= 1 << 1; |
3299de95 | 373 | if (audio.status_bits & AUDIO_STATUS_COPYRIGHT) |
dafc3bd5 | 374 | iec |= 1 << 2; |
3299de95 | 375 | if (audio.status_bits & AUDIO_STATUS_EMPHASIS) |
dafc3bd5 CK |
376 | iec |= 1 << 3; |
377 | ||
3299de95 | 378 | iec |= HDMI0_60958_CS_CATEGORY_CODE(audio.category_code); |
dafc3bd5 | 379 | |
3299de95 | 380 | switch (audio.rate) { |
a366e392 RM |
381 | case 32000: |
382 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3); | |
383 | break; | |
384 | case 44100: | |
385 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0); | |
386 | break; | |
387 | case 48000: | |
388 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2); | |
389 | break; | |
390 | case 88200: | |
391 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8); | |
392 | break; | |
393 | case 96000: | |
394 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa); | |
395 | break; | |
396 | case 176400: | |
397 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc); | |
398 | break; | |
399 | case 192000: | |
400 | iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe); | |
401 | break; | |
dafc3bd5 CK |
402 | } |
403 | ||
c6543a6e | 404 | WREG32(HDMI0_60958_0 + offset, iec); |
dafc3bd5 CK |
405 | |
406 | iec = 0; | |
3299de95 | 407 | switch (audio.bits_per_sample) { |
a366e392 RM |
408 | case 16: |
409 | iec |= HDMI0_60958_CS_WORD_LENGTH(0x2); | |
410 | break; | |
411 | case 20: | |
412 | iec |= HDMI0_60958_CS_WORD_LENGTH(0x3); | |
413 | break; | |
414 | case 24: | |
415 | iec |= HDMI0_60958_CS_WORD_LENGTH(0xb); | |
416 | break; | |
dafc3bd5 | 417 | } |
3299de95 | 418 | if (audio.status_bits & AUDIO_STATUS_V) |
dafc3bd5 | 419 | iec |= 0x5 << 16; |
c6543a6e | 420 | WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f); |
dafc3bd5 | 421 | |
e3b2e034 TR |
422 | err = hdmi_audio_infoframe_init(&frame); |
423 | if (err < 0) { | |
424 | DRM_ERROR("failed to setup audio infoframe\n"); | |
425 | return; | |
426 | } | |
427 | ||
428 | frame.channels = audio.channels; | |
429 | ||
430 | err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); | |
431 | if (err < 0) { | |
432 | DRM_ERROR("failed to pack audio infoframe\n"); | |
433 | return; | |
434 | } | |
dafc3bd5 | 435 | |
e3b2e034 | 436 | r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer)); |
dafc3bd5 | 437 | r600_hdmi_audio_workaround(encoder); |
dafc3bd5 CK |
438 | } |
439 | ||
dafc3bd5 | 440 | /* |
2cd6218c | 441 | * enable the HDMI engine |
dafc3bd5 | 442 | */ |
a973bea1 | 443 | void r600_hdmi_enable(struct drm_encoder *encoder, bool enable) |
dafc3bd5 | 444 | { |
2cd6218c RM |
445 | struct drm_device *dev = encoder->dev; |
446 | struct radeon_device *rdev = dev->dev_private; | |
dafc3bd5 | 447 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
cfcbd6d3 | 448 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
a973bea1 | 449 | u32 hdmi = HDMI0_ERROR_ACK; |
16823d16 | 450 | |
cfcbd6d3 | 451 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
a973bea1 AD |
452 | if (enable && dig->afmt->enabled) |
453 | return; | |
454 | if (!enable && !dig->afmt->enabled) | |
cfcbd6d3 | 455 | return; |
64fb4fb0 RM |
456 | |
457 | /* Older chipsets require setting HDMI and routing manually */ | |
a973bea1 AD |
458 | if (!ASIC_IS_DCE3(rdev)) { |
459 | if (enable) | |
460 | hdmi |= HDMI0_ENABLE; | |
5715f67c RM |
461 | switch (radeon_encoder->encoder_id) { |
462 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
a973bea1 AD |
463 | if (enable) { |
464 | WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN); | |
465 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA); | |
466 | } else { | |
467 | WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN); | |
468 | } | |
5715f67c RM |
469 | break; |
470 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
a973bea1 AD |
471 | if (enable) { |
472 | WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN); | |
473 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA); | |
474 | } else { | |
475 | WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN); | |
476 | } | |
64fb4fb0 RM |
477 | break; |
478 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
a973bea1 AD |
479 | if (enable) { |
480 | WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN); | |
481 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA); | |
482 | } else { | |
483 | WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN); | |
484 | } | |
64fb4fb0 RM |
485 | break; |
486 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
a973bea1 AD |
487 | if (enable) |
488 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA); | |
5715f67c RM |
489 | break; |
490 | default: | |
64fb4fb0 RM |
491 | dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n", |
492 | radeon_encoder->encoder_id); | |
5715f67c RM |
493 | break; |
494 | } | |
a973bea1 | 495 | WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi); |
5715f67c | 496 | } |
2cd6218c | 497 | |
f122c610 | 498 | if (rdev->irq.installed) { |
f2594933 | 499 | /* if irq is available use it */ |
9054ae1c | 500 | /* XXX: shouldn't need this on any asics. Double check DCE2/3 */ |
a973bea1 | 501 | if (enable) |
9054ae1c | 502 | radeon_irq_kms_enable_afmt(rdev, dig->afmt->id); |
a973bea1 AD |
503 | else |
504 | radeon_irq_kms_disable_afmt(rdev, dig->afmt->id); | |
f2594933 | 505 | } |
58bd0863 | 506 | |
a973bea1 | 507 | dig->afmt->enabled = enable; |
cfcbd6d3 | 508 | |
a973bea1 AD |
509 | DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
510 | enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); | |
2cd6218c | 511 | } |
dafc3bd5 | 512 |