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drm/radeon/hdmi: update modesetting
[deliverable/linux.git] / drivers / gpu / drm / radeon / r600_hdmi.c
CommitLineData
dafc3bd5
CK		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Christian König
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
3574dda4 29#include "radeon_asic.h"
c6543a6e 30#include "r600d.h"
dafc3bd5
CK		 31#include "atom.h"
32
33/*
34 * HDMI color format
35 */
36enum r600_hdmi_color_format {
37 RGB = 0,
38 YCC_422 = 1,
39 YCC_444 = 2
40};
41
42/*
43 * IEC60958 status bits
44 */
45enum r600_hdmi_iec_status_bits {
46 AUDIO_STATUS_DIG_ENABLE = 0x01,
3fe373d9
RM		 47 AUDIO_STATUS_V = 0x02,
48 AUDIO_STATUS_VCFG = 0x04,
dafc3bd5
CK		 49 AUDIO_STATUS_EMPHASIS = 0x08,
50 AUDIO_STATUS_COPYRIGHT = 0x10,
51 AUDIO_STATUS_NONAUDIO = 0x20,
52 AUDIO_STATUS_PROFESSIONAL = 0x40,
3fe373d9 53 AUDIO_STATUS_LEVEL = 0x80
dafc3bd5
CK		 54};
55
1b688d08 56struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
dafc3bd5
CK		 57 /* 32kHz 44.1kHz 48kHz */
58 /* Clock N CTS N CTS N CTS */
59 { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */
60 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
61 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
62 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
63 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
64 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
65 { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */
66 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
67 { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */
68 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
69 { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */
70};
71
72/*
73 * calculate CTS value if it's not found in the table
74 */
1b688d08 75static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq)
dafc3bd5
CK		 76{
77 if (*CTS == 0)
3fe373d9 78 *CTS = clock * N / (128 * freq) * 1000;
dafc3bd5
CK		 79 DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n",
80 N, *CTS, freq);
81}
82
1b688d08
RM		 83struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock)
84{
85 struct radeon_hdmi_acr res;
86 u8 i;
87
88 for (i = 0; r600_hdmi_predefined_acr[i].clock != clock &&
89 r600_hdmi_predefined_acr[i].clock != 0; i++)
90 ;
91 res = r600_hdmi_predefined_acr[i];
92
93 /* In case some CTS are missing */
94 r600_hdmi_calc_cts(clock, &res.cts_32khz, res.n_32khz, 32000);
95 r600_hdmi_calc_cts(clock, &res.cts_44_1khz, res.n_44_1khz, 44100);
96 r600_hdmi_calc_cts(clock, &res.cts_48khz, res.n_48khz, 48000);
97
98 return res;
99}
100
dafc3bd5
CK		 101/*
102 * update the N and CTS parameters for a given pixel clock rate
103 */
104static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
105{
106 struct drm_device *dev = encoder->dev;
107 struct radeon_device *rdev = dev->dev_private;
1b688d08 108 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
dafc3bd5 109 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
dafc3bd5 110
1b688d08
RM		 111 WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz));
112 WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz);
dafc3bd5 113
1b688d08
RM		 114 WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz));
115 WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz);
dafc3bd5 116
1b688d08
RM		 117 WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz));
118 WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz);
dafc3bd5
CK		 119}
120
121/*
122 * calculate the crc for a given info frame
123 */
124static void r600_hdmi_infoframe_checksum(uint8_t packetType,
125 uint8_t versionNumber,
126 uint8_t length,
127 uint8_t *frame)
128{
3fe373d9
RM		 129 int i;
130 frame[0] = packetType + versionNumber + length;
131 for (i = 1; i <= length; i++)
132 frame[0] += frame[i];
133 frame[0] = 0x100 - frame[0];
dafc3bd5
CK		 134}
135
136/*
137 * build a HDMI Video Info Frame
138 */
139static void r600_hdmi_videoinfoframe(
140 struct drm_encoder *encoder,
141 enum r600_hdmi_color_format color_format,
142 int active_information_present,
143 uint8_t active_format_aspect_ratio,
144 uint8_t scan_information,
145 uint8_t colorimetry,
146 uint8_t ex_colorimetry,
147 uint8_t quantization,
148 int ITC,
149 uint8_t picture_aspect_ratio,
150 uint8_t video_format_identification,
151 uint8_t pixel_repetition,
152 uint8_t non_uniform_picture_scaling,
153 uint8_t bar_info_data_valid,
154 uint16_t top_bar,
155 uint16_t bottom_bar,
156 uint16_t left_bar,
157 uint16_t right_bar
158)
159{
160 struct drm_device *dev = encoder->dev;
161 struct radeon_device *rdev = dev->dev_private;
162 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
163
164 uint8_t frame[14];
165
166 frame[0x0] = 0;
167 frame[0x1] =
168 (scan_information & 0x3) |
169 ((bar_info_data_valid & 0x3) << 2) |
170 ((active_information_present & 0x1) << 4) |
171 ((color_format & 0x3) << 5);
172 frame[0x2] =
173 (active_format_aspect_ratio & 0xF) |
174 ((picture_aspect_ratio & 0x3) << 4) |
175 ((colorimetry & 0x3) << 6);
176 frame[0x3] =
177 (non_uniform_picture_scaling & 0x3) |
178 ((quantization & 0x3) << 2) |
179 ((ex_colorimetry & 0x7) << 4) |
180 ((ITC & 0x1) << 7);
181 frame[0x4] = (video_format_identification & 0x7F);
182 frame[0x5] = (pixel_repetition & 0xF);
183 frame[0x6] = (top_bar & 0xFF);
184 frame[0x7] = (top_bar >> 8);
185 frame[0x8] = (bottom_bar & 0xFF);
186 frame[0x9] = (bottom_bar >> 8);
187 frame[0xA] = (left_bar & 0xFF);
188 frame[0xB] = (left_bar >> 8);
189 frame[0xC] = (right_bar & 0xFF);
190 frame[0xD] = (right_bar >> 8);
191
192 r600_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame);
92db7f6c
RM		 193 /* Our header values (type, version, length) should be alright, Intel
194 * is using the same. Checksum function also seems to be OK, it works
195 * fine for audio infoframe. However calculated value is always lower
196 * by 2 in comparison to fglrx. It breaks displaying anything in case
197 * of TVs that strictly check the checksum. Hack it manually here to
198 * workaround this issue. */
199 frame[0x0] += 2;
dafc3bd5 200
c6543a6e 201 WREG32(HDMI0_AVI_INFO0 + offset,
dafc3bd5 202 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
c6543a6e 203 WREG32(HDMI0_AVI_INFO1 + offset,
dafc3bd5 204 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
c6543a6e 205 WREG32(HDMI0_AVI_INFO2 + offset,
dafc3bd5 206 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
c6543a6e 207 WREG32(HDMI0_AVI_INFO3 + offset,
dafc3bd5
CK		 208 frame[0xC] | (frame[0xD] << 8));
209}
210
211/*
212 * build a Audio Info Frame
213 */
214static void r600_hdmi_audioinfoframe(
215 struct drm_encoder *encoder,
216 uint8_t channel_count,
217 uint8_t coding_type,
218 uint8_t sample_size,
219 uint8_t sample_frequency,
220 uint8_t format,
221 uint8_t channel_allocation,
222 uint8_t level_shift,
223 int downmix_inhibit
224)
225{
226 struct drm_device *dev = encoder->dev;
227 struct radeon_device *rdev = dev->dev_private;
228 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
229
230 uint8_t frame[11];
231
232 frame[0x0] = 0;
233 frame[0x1] = (channel_count & 0x7) | ((coding_type & 0xF) << 4);
234 frame[0x2] = (sample_size & 0x3) | ((sample_frequency & 0x7) << 2);
235 frame[0x3] = format;
236 frame[0x4] = channel_allocation;
237 frame[0x5] = ((level_shift & 0xF) << 3) | ((downmix_inhibit & 0x1) << 7);
238 frame[0x6] = 0;
239 frame[0x7] = 0;
240 frame[0x8] = 0;
241 frame[0x9] = 0;
242 frame[0xA] = 0;
243
244 r600_hdmi_infoframe_checksum(0x84, 0x01, 0x0A, frame);
245
c6543a6e 246 WREG32(HDMI0_AUDIO_INFO0 + offset,
dafc3bd5 247 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
c6543a6e 248 WREG32(HDMI0_AUDIO_INFO1 + offset,
dafc3bd5
CK		 249 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
250}
251
252/*
253 * test if audio buffer is filled enough to start playing
254 */
255static int r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
256{
257 struct drm_device *dev = encoder->dev;
258 struct radeon_device *rdev = dev->dev_private;
259 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
260
c6543a6e 261 return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
dafc3bd5
CK		 262}
263
264/*
265 * have buffer status changed since last call?
266 */
267int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
268{
269 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
270 int status, result;
271
af0b5743 272 if (!radeon_encoder->hdmi_enabled)
dafc3bd5
CK		 273 return 0;
274
275 status = r600_hdmi_is_audio_buffer_filled(encoder);
276 result = radeon_encoder->hdmi_buffer_status != status;
277 radeon_encoder->hdmi_buffer_status = status;
278
279 return result;
280}
281
282/*
283 * write the audio workaround status to the hardware
284 */
285void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
286{
287 struct drm_device *dev = encoder->dev;
288 struct radeon_device *rdev = dev->dev_private;
289 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
290 uint32_t offset = radeon_encoder->hdmi_offset;
291
af0b5743 292 if (!radeon_encoder->hdmi_enabled)
dafc3bd5
CK		 293 return;
294
f2594933
CK		 295 if (!radeon_encoder->hdmi_audio_workaround ||
296 r600_hdmi_is_audio_buffer_filled(encoder)) {
dafc3bd5 297
f2594933 298 /* disable audio workaround */
a273a903
RM		 299 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
300 0, ~HDMI0_AUDIO_TEST_EN);
dafc3bd5
CK		 301
302 } else {
f2594933 303 /* enable audio workaround */
a273a903
RM		 304 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
305 HDMI0_AUDIO_TEST_EN, ~HDMI0_AUDIO_TEST_EN);
dafc3bd5
CK		 306 }
307}
308
309
310/*
311 * update the info frames with the data from the current display mode
312 */
313void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
314{
315 struct drm_device *dev = encoder->dev;
316 struct radeon_device *rdev = dev->dev_private;
317 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
318
f83d926a 319 if (ASIC_IS_DCE5(rdev))
16823d16
AD		 320 return;
321
af0b5743 322 if (!to_radeon_encoder(encoder)->hdmi_enabled)
dafc3bd5
CK		 323 return;
324
325 r600_audio_set_clock(encoder, mode->clock);
326
1c3439f2
RM		 327 WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
328 HDMI0_NULL_SEND); /* send null packets when required */
329
c6543a6e 330 WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);
a273a903 331
1c3439f2
RM		 332 if (ASIC_IS_DCE32(rdev)) {
333 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
334 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
335 HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
336 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
337 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
338 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
339 } else {
340 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
341 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
342 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
343 HDMI0_AUDIO_SEND_MAX_PACKETS | /* send NULL packets if no audio is available */
344 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
345 HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
346 }
a273a903 347
1c3439f2
RM		 348 WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
349 HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
350 HDMI0_ACR_SOURCE); /* select SW CTS value */
dafc3bd5 351
1c3439f2
RM		 352 WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
353 HDMI0_NULL_SEND | /* send null packets when required */
354 HDMI0_GC_SEND | /* send general control packets */
355 HDMI0_GC_CONT); /* send general control packets every frame */
dafc3bd5 356
1c3439f2
RM		 357 /* TODO: HDMI0_AUDIO_INFO_UPDATE */
358 WREG32(HDMI0_INFOFRAME_CONTROL0 + offset,
359 HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
360 HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
361 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
362 HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */
dafc3bd5 363
1c3439f2
RM		 364 WREG32(HDMI0_INFOFRAME_CONTROL1 + offset,
365 HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
366 HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */
367
368 WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */
dafc3bd5
CK		 369
370 r600_hdmi_videoinfoframe(encoder, RGB, 0, 0, 0, 0,
371 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
372
1c3439f2
RM		 373 r600_hdmi_update_ACR(encoder, mode->clock);
374
25985edc 375 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
c6543a6e
RM		 376 WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
377 WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
378 WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
379 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
dafc3bd5
CK		 380
381 r600_hdmi_audio_workaround(encoder);
dafc3bd5
CK		 382}
383
384/*
385 * update settings with current parameters from audio engine
386 */
58bd0863 387void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
dafc3bd5
CK		 388{
389 struct drm_device *dev = encoder->dev;
390 struct radeon_device *rdev = dev->dev_private;
391 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
392
58bd0863
CK		 393 int channels = r600_audio_channels(rdev);
394 int rate = r600_audio_rate(rdev);
395 int bps = r600_audio_bits_per_sample(rdev);
396 uint8_t status_bits = r600_audio_status_bits(rdev);
397 uint8_t category_code = r600_audio_category_code(rdev);
398
dafc3bd5
CK		 399 uint32_t iec;
400
af0b5743 401 if (!to_radeon_encoder(encoder)->hdmi_enabled)
dafc3bd5
CK		 402 return;
403
404 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
405 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
406 channels, rate, bps);
407 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
408 (int)status_bits, (int)category_code);
409
410 iec = 0;
411 if (status_bits & AUDIO_STATUS_PROFESSIONAL)
412 iec |= 1 << 0;
413 if (status_bits & AUDIO_STATUS_NONAUDIO)
414 iec |= 1 << 1;
415 if (status_bits & AUDIO_STATUS_COPYRIGHT)
416 iec |= 1 << 2;
417 if (status_bits & AUDIO_STATUS_EMPHASIS)
418 iec |= 1 << 3;
419
420 iec |= category_code << 8;
421
422 switch (rate) {
423 case 32000: iec |= 0x3 << 24; break;
424 case 44100: iec |= 0x0 << 24; break;
425 case 88200: iec |= 0x8 << 24; break;
426 case 176400: iec |= 0xc << 24; break;
427 case 48000: iec |= 0x2 << 24; break;
428 case 96000: iec |= 0xa << 24; break;
429 case 192000: iec |= 0xe << 24; break;
430 }
431
c6543a6e 432 WREG32(HDMI0_60958_0 + offset, iec);
dafc3bd5
CK		 433
434 iec = 0;
435 switch (bps) {
436 case 16: iec |= 0x2; break;
437 case 20: iec |= 0x3; break;
438 case 24: iec |= 0xb; break;
439 }
440 if (status_bits & AUDIO_STATUS_V)
441 iec |= 0x5 << 16;
442
c6543a6e 443 WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f);
dafc3bd5
CK		 444
445 /* 0x021 or 0x031 sets the audio frame length */
c6543a6e 446 WREG32(HDMI0_VBI_PACKET_CONTROL + offset, 0x31);
dafc3bd5
CK		 447 r600_hdmi_audioinfoframe(encoder, channels-1, 0, 0, 0, 0, 0, 0, 0);
448
449 r600_hdmi_audio_workaround(encoder);
dafc3bd5
CK		 450}
451
2cd6218c 452static void r600_hdmi_assign_block(struct drm_encoder *encoder)
dafc3bd5
CK		 453{
454 struct drm_device *dev = encoder->dev;
455 struct radeon_device *rdev = dev->dev_private;
456 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2cd6218c 457 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
dafc3bd5 458
f83d926a
RM		 459 u16 eg_offsets[] = {
460 EVERGREEN_CRTC0_REGISTER_OFFSET,
461 EVERGREEN_CRTC1_REGISTER_OFFSET,
462 EVERGREEN_CRTC2_REGISTER_OFFSET,
463 EVERGREEN_CRTC3_REGISTER_OFFSET,
464 EVERGREEN_CRTC4_REGISTER_OFFSET,
465 EVERGREEN_CRTC5_REGISTER_OFFSET,
466 };
467
2cd6218c
RM		 468 if (!dig) {
469 dev_err(rdev->dev, "Enabling HDMI on non-dig encoder\n");
dafc3bd5 470 return;
2cd6218c 471 }
dafc3bd5 472
ebcb796f
RM		 473 if (ASIC_IS_DCE5(rdev)) {
474 /* TODO */
475 } else if (ASIC_IS_DCE4(rdev)) {
f83d926a
RM		 476 if (dig->dig_encoder >= ARRAY_SIZE(eg_offsets)) {
477 dev_err(rdev->dev, "Enabling HDMI on unknown dig\n");
478 return;
479 }
c6543a6e 480 radeon_encoder->hdmi_offset = eg_offsets[dig->dig_encoder];
2cd6218c
RM		 481 } else if (ASIC_IS_DCE3(rdev)) {
482 radeon_encoder->hdmi_offset = dig->dig_encoder ?
c6543a6e 483 DCE3_HDMI_OFFSET1 : DCE3_HDMI_OFFSET0;
816ce437
RM		 484 } else if (rdev->family >= CHIP_R600) {
485 /* 2 routable blocks, but using dig_encoder should be fine */
486 radeon_encoder->hdmi_offset = dig->dig_encoder ?
c6543a6e 487 DCE2_HDMI_OFFSET1 : DCE2_HDMI_OFFSET0;
816ce437
RM		 488 } else if (rdev->family == CHIP_RS600 || rdev->family == CHIP_RS690 ||
489 rdev->family == CHIP_RS740) {
490 /* Only 1 routable block */
c6543a6e 491 radeon_encoder->hdmi_offset = DCE2_HDMI_OFFSET0;
dafc3bd5 492 }
af0b5743 493 radeon_encoder->hdmi_enabled = true;
dafc3bd5
CK		 494}
495
496/*
2cd6218c 497 * enable the HDMI engine
dafc3bd5 498 */
2cd6218c 499void r600_hdmi_enable(struct drm_encoder *encoder)
dafc3bd5 500{
2cd6218c
RM		 501 struct drm_device *dev = encoder->dev;
502 struct radeon_device *rdev = dev->dev_private;
dafc3bd5 503 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
f2594933 504 uint32_t offset;
64fb4fb0 505 u32 hdmi;
dafc3bd5 506
f83d926a 507 if (ASIC_IS_DCE5(rdev))
16823d16
AD		 508 return;
509
af0b5743 510 if (!radeon_encoder->hdmi_enabled) {
2cd6218c 511 r600_hdmi_assign_block(encoder);
af0b5743 512 if (!radeon_encoder->hdmi_enabled) {
2cd6218c
RM		 513 dev_warn(rdev->dev, "Could not find HDMI block for "
514 "0x%x encoder\n", radeon_encoder->encoder_id);
515 return;
dafc3bd5 516 }
2cd6218c 517 }
dafc3bd5 518
f2594933 519 offset = radeon_encoder->hdmi_offset;
64fb4fb0
RM		 520
521 /* Older chipsets require setting HDMI and routing manually */
522 if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
523 hdmi = HDMI0_ERROR_ACK | HDMI0_ENABLE;
5715f67c
RM		 524 switch (radeon_encoder->encoder_id) {
525 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
93a4ed87
RM		 526 WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN,
527 ~AVIVO_TMDSA_CNTL_HDMI_EN);
64fb4fb0 528 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
5715f67c
RM		 529 break;
530 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
93a4ed87
RM		 531 WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN,
532 ~AVIVO_LVTMA_CNTL_HDMI_EN);
64fb4fb0
RM		 533 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
534 break;
535 case ENCODER_OBJECT_ID_INTERNAL_DDI:
536 WREG32_P(DDIA_CNTL, DDIA_HDMI_EN, ~DDIA_HDMI_EN);
537 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
538 break;
539 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
540 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
5715f67c
RM		 541 break;
542 default:
64fb4fb0
RM		 543 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
544 radeon_encoder->encoder_id);
5715f67c
RM		 545 break;
546 }
64fb4fb0 547 WREG32(HDMI0_CONTROL + offset, hdmi);
5715f67c 548 }
2cd6218c 549
f122c610 550 if (rdev->irq.installed) {
f2594933 551 /* if irq is available use it */
c6543a6e 552 rdev->irq.afmt[offset == 0 ? 0 : 1] = true;
f2594933 553 radeon_irq_set(rdev);
f2594933 554 }
58bd0863 555
2cd6218c
RM		 556 DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n",
557 radeon_encoder->hdmi_offset, radeon_encoder->encoder_id);
558}
dafc3bd5 559
2cd6218c
RM		 560/*
561 * disable the HDMI engine
562 */
563void r600_hdmi_disable(struct drm_encoder *encoder)
564{
565 struct drm_device *dev = encoder->dev;
566 struct radeon_device *rdev = dev->dev_private;
567 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
66989987 568 uint32_t offset;
2cd6218c 569
f83d926a 570 if (ASIC_IS_DCE5(rdev))
16823d16
AD		 571 return;
572
f2594933 573 offset = radeon_encoder->hdmi_offset;
af0b5743 574 if (!radeon_encoder->hdmi_enabled) {
2cd6218c
RM		 575 dev_err(rdev->dev, "Disabling not enabled HDMI\n");
576 return;
dafc3bd5
CK		 577 }
578
2cd6218c 579 DRM_DEBUG("Disabling HDMI interface @ 0x%04X for encoder 0x%x\n",
f2594933
CK		 580 offset, radeon_encoder->encoder_id);
581
582 /* disable irq */
c6543a6e 583 rdev->irq.afmt[offset == 0 ? 0 : 1] = false;
f2594933
CK		 584 radeon_irq_set(rdev);
585
64fb4fb0
RM		 586 /* Older chipsets not handled by AtomBIOS */
587 if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
5715f67c
RM		 588 switch (radeon_encoder->encoder_id) {
589 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
93a4ed87
RM		 590 WREG32_P(AVIVO_TMDSA_CNTL, 0,
591 ~AVIVO_TMDSA_CNTL_HDMI_EN);
5715f67c
RM		 592 break;
593 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
93a4ed87
RM		 594 WREG32_P(AVIVO_LVTMA_CNTL, 0,
595 ~AVIVO_LVTMA_CNTL_HDMI_EN);
64fb4fb0
RM		 596 break;
597 case ENCODER_OBJECT_ID_INTERNAL_DDI:
598 WREG32_P(DDIA_CNTL, 0, ~DDIA_HDMI_EN);
599 break;
600 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
5715f67c
RM		 601 break;
602 default:
64fb4fb0
RM		 603 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
604 radeon_encoder->encoder_id);
5715f67c
RM		 605 break;
606 }
64fb4fb0 607 WREG32(HDMI0_CONTROL + offset, HDMI0_ERROR_ACK);
5715f67c 608 }
dafc3bd5 609
af0b5743 610 radeon_encoder->hdmi_enabled = false;
2cd6218c 611 radeon_encoder->hdmi_offset = 0;
dafc3bd5 612}
Linux kernel - Deliverables
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