[deliverable/linux.git] / drivers / gpu / drm / radeon / r600_hdmi.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Christian König.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Christian König
 */
#include <linux/hdmi.h>
#include <drm/drmP.h>
#include <drm/radeon_drm.h>
#include "radeon.h"
#include "radeon_asic.h"
#include "r600d.h"
#include "atom.h"

/*
 * HDMI color format
 */
enum r600_hdmi_color_format {
	RGB = 0,
	YCC_422 = 1,
	YCC_444 = 2
};

/*
 * IEC60958 status bits
 */
enum r600_hdmi_iec_status_bits {
	AUDIO_STATUS_DIG_ENABLE   = 0x01,
	AUDIO_STATUS_V            = 0x02,
	AUDIO_STATUS_VCFG         = 0x04,
	AUDIO_STATUS_EMPHASIS     = 0x08,
	AUDIO_STATUS_COPYRIGHT    = 0x10,
	AUDIO_STATUS_NONAUDIO     = 0x20,
	AUDIO_STATUS_PROFESSIONAL = 0x40,
	AUDIO_STATUS_LEVEL        = 0x80
};

static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
    /*	     32kHz	  44.1kHz	48kHz    */
    /* Clock      N     CTS      N     CTS      N     CTS */
    {  25174,  4576,  28125,  7007,  31250,  6864,  28125 }, /*  25,20/1.001 MHz */
    {  25200,  4096,  25200,  6272,  28000,  6144,  25200 }, /*  25.20       MHz */
    {  27000,  4096,  27000,  6272,  30000,  6144,  27000 }, /*  27.00       MHz */
    {  27027,  4096,  27027,  6272,  30030,  6144,  27027 }, /*  27.00*1.001 MHz */
    {  54000,  4096,  54000,  6272,  60000,  6144,  54000 }, /*  54.00       MHz */
    {  54054,  4096,  54054,  6272,  60060,  6144,  54054 }, /*  54.00*1.001 MHz */
    {  74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /*  74.25/1.001 MHz */
    {  74250,  4096,  74250,  6272,  82500,  6144,  74250 }, /*  74.25       MHz */
    { 148351, 11648, 421875,  8918, 234375,  5824, 140625 }, /* 148.50/1.001 MHz */
    { 148500,  4096, 148500,  6272, 165000,  6144, 148500 }, /* 148.50       MHz */
    {      0,  4096,      0,  6272,      0,  6144,      0 }  /* Other */
};

/*
 * calculate CTS value if it's not found in the table
 */
static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq)
{
	if (*CTS == 0)
		*CTS = clock * N / (128 * freq) * 1000;
	DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n",
		  N, *CTS, freq);
}

struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock)
{
	struct radeon_hdmi_acr res;
	u8 i;

	for (i = 0; r600_hdmi_predefined_acr[i].clock != clock &&
	     r600_hdmi_predefined_acr[i].clock != 0; i++)
		;
	res = r600_hdmi_predefined_acr[i];

	/* In case some CTS are missing */
	r600_hdmi_calc_cts(clock, &res.cts_32khz, res.n_32khz, 32000);
	r600_hdmi_calc_cts(clock, &res.cts_44_1khz, res.n_44_1khz, 44100);
	r600_hdmi_calc_cts(clock, &res.cts_48khz, res.n_48khz, 48000);

	return res;
}

/*
 * update the N and CTS parameters for a given pixel clock rate
 */
static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	uint32_t offset = dig->afmt->offset;

	WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz));
	WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz);

	WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz));
	WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz);

	WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz));
	WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz);
}

/*
 * build a HDMI Video Info Frame
 */
static void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
					   void *buffer, size_t size)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	uint32_t offset = dig->afmt->offset;
	uint8_t *frame = buffer + 3;

	/* Our header values (type, version, length) should be alright, Intel
	 * is using the same. Checksum function also seems to be OK, it works
	 * fine for audio infoframe. However calculated value is always lower
	 * by 2 in comparison to fglrx. It breaks displaying anything in case
	 * of TVs that strictly check the checksum. Hack it manually here to
	 * workaround this issue. */
	frame[0x0] += 2;

	WREG32(HDMI0_AVI_INFO0 + offset,
		frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
	WREG32(HDMI0_AVI_INFO1 + offset,
		frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
	WREG32(HDMI0_AVI_INFO2 + offset,
		frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
	WREG32(HDMI0_AVI_INFO3 + offset,
		frame[0xC] | (frame[0xD] << 8));
}

/*
 * build a Audio Info Frame
 */
static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder,
					     const void *buffer, size_t size)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	uint32_t offset = dig->afmt->offset;
	const u8 *frame = buffer + 3;

	WREG32(HDMI0_AUDIO_INFO0 + offset,
		frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
	WREG32(HDMI0_AUDIO_INFO1 + offset,
		frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
}

/*
 * test if audio buffer is filled enough to start playing
 */
static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	uint32_t offset = dig->afmt->offset;

	return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
}

/*
 * have buffer status changed since last call?
 */
int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
{
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	int status, result;

	if (!dig->afmt || !dig->afmt->enabled)
		return 0;

	status = r600_hdmi_is_audio_buffer_filled(encoder);
	result = dig->afmt->last_buffer_filled_status != status;
	dig->afmt->last_buffer_filled_status = status;

	return result;
}

/*
 * write the audio workaround status to the hardware
 */
static void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	uint32_t offset = dig->afmt->offset;
	bool hdmi_audio_workaround = false; /* FIXME */
	u32 value;

	if (!hdmi_audio_workaround ||
	    r600_hdmi_is_audio_buffer_filled(encoder))
		value = 0; /* disable workaround */
	else
		value = HDMI0_AUDIO_TEST_EN; /* enable workaround */
	WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
		 value, ~HDMI0_AUDIO_TEST_EN);
}

void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	u32 base_rate = 48000;

	if (!dig || !dig->afmt)
		return;

	/* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT.
	 * doesn't matter which one you use.  Just use the first one.
	 */
	/* XXX: properly calculate this */
	/* XXX two dtos; generally use dto0 for hdmi */
	/* Express [24MHz / target pixel clock] as an exact rational
	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	 */
	WREG32(DCCG_AUDIO_DTO0_PHASE, (base_rate*50) & 0xffffff);
	WREG32(DCCG_AUDIO_DTO0_MODULE, (clock*100) & 0xffffff);
	WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
}

/*
 * update the info frames with the data from the current display mode
 */
void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
	struct hdmi_avi_infoframe frame;
	uint32_t offset;
	ssize_t err;

	/* Silent, r600_hdmi_enable will raise WARN for us */
	if (!dig->afmt->enabled)
		return;
	offset = dig->afmt->offset;

	r600_audio_set_dto(encoder, mode->clock);

	WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
	       HDMI0_NULL_SEND); /* send null packets when required */

	WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);

	if (ASIC_IS_DCE32(rdev)) {
		WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
		       HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
		       HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
		WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
		       AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
		       AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
	} else {
		WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
		       HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
		       HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
		       HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
		       HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
	}

	WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
	       HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
	       HDMI0_ACR_SOURCE); /* select SW CTS value */

	WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
	       HDMI0_NULL_SEND | /* send null packets when required */
	       HDMI0_GC_SEND | /* send general control packets */
	       HDMI0_GC_CONT); /* send general control packets every frame */

	/* TODO: HDMI0_AUDIO_INFO_UPDATE */
	WREG32(HDMI0_INFOFRAME_CONTROL0 + offset,
	       HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
	       HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
	       HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
	       HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */

	WREG32(HDMI0_INFOFRAME_CONTROL1 + offset,
	       HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
	       HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */

	WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */

	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
	if (err < 0) {
		DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
		return;
	}

	err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
	if (err < 0) {
		DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
		return;
	}

	r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
	r600_hdmi_update_ACR(encoder, mode->clock);

	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
	WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
	WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
	WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
	WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);

	r600_hdmi_audio_workaround(encoder);
}

/*
 * update settings with current parameters from audio engine
 */
void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	struct r600_audio audio = r600_audio_status(rdev);
	uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
	struct hdmi_audio_infoframe frame;
	uint32_t offset;
	uint32_t iec;
	ssize_t err;

	if (!dig->afmt || !dig->afmt->enabled)
		return;
	offset = dig->afmt->offset;

	DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
		 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
		  audio.channels, audio.rate, audio.bits_per_sample);
	DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
		  (int)audio.status_bits, (int)audio.category_code);

	iec = 0;
	if (audio.status_bits & AUDIO_STATUS_PROFESSIONAL)
		iec |= 1 << 0;
	if (audio.status_bits & AUDIO_STATUS_NONAUDIO)
		iec |= 1 << 1;
	if (audio.status_bits & AUDIO_STATUS_COPYRIGHT)
		iec |= 1 << 2;
	if (audio.status_bits & AUDIO_STATUS_EMPHASIS)
		iec |= 1 << 3;

	iec |= HDMI0_60958_CS_CATEGORY_CODE(audio.category_code);

	switch (audio.rate) {
	case 32000:
		iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3);
		break;
	case 44100:
		iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0);
		break;
	case 48000:
		iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2);
		break;
	case 88200:
		iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8);
		break;
	case 96000:
		iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa);
		break;
	case 176400:
		iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc);
		break;
	case 192000:
		iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe);
		break;
	}

	WREG32(HDMI0_60958_0 + offset, iec);

	iec = 0;
	switch (audio.bits_per_sample) {
	case 16:
		iec |= HDMI0_60958_CS_WORD_LENGTH(0x2);
		break;
	case 20:
		iec |= HDMI0_60958_CS_WORD_LENGTH(0x3);
		break;
	case 24:
		iec |= HDMI0_60958_CS_WORD_LENGTH(0xb);
		break;
	}
	if (audio.status_bits & AUDIO_STATUS_V)
		iec |= 0x5 << 16;
	WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f);

	err = hdmi_audio_infoframe_init(&frame);
	if (err < 0) {
		DRM_ERROR("failed to setup audio infoframe\n");
		return;
	}

	frame.channels = audio.channels;

	err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
	if (err < 0) {
		DRM_ERROR("failed to pack audio infoframe\n");
		return;
	}

	r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer));
	r600_hdmi_audio_workaround(encoder);
}

/*
 * enable the HDMI engine
 */
void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	u32 hdmi = HDMI0_ERROR_ACK;

	/* Silent, r600_hdmi_enable will raise WARN for us */
	if (enable && dig->afmt->enabled)
		return;
	if (!enable && !dig->afmt->enabled)
		return;

	/* Older chipsets require setting HDMI and routing manually */
	if (!ASIC_IS_DCE3(rdev)) {
		if (enable)
			hdmi |= HDMI0_ENABLE;
		switch (radeon_encoder->encoder_id) {
		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
			if (enable) {
				WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
				hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
			} else {
				WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
			}
			break;
		case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
			if (enable) {
				WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
				hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
			} else {
				WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
			}
			break;
		case ENCODER_OBJECT_ID_INTERNAL_DDI:
			if (enable) {
				WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
				hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
			} else {
				WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
			}
			break;
		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
			if (enable)
				hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
			break;
		default:
			dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
				radeon_encoder->encoder_id);
			break;
		}
		WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);
	}

	if (rdev->irq.installed) {
		/* if irq is available use it */
		/* XXX: shouldn't need this on any asics.  Double check DCE2/3 */
		if (enable)
			radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
		else
			radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
	}

	dig->afmt->enabled = enable;

	DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
		  enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
}
Commit	Line	Data
dafc3bd5 CK	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Christian König.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Christian König
	25	*/
e3b2e034	26	#include <linux/hdmi.h>
760285e7 DH	27	#include <drm/drmP.h>
760285e7 DH	28	#include <drm/radeon_drm.h>
dafc3bd5	29	#include "radeon.h"
3574dda4	30	#include "radeon_asic.h"
c6543a6e	31	#include "r600d.h"
dafc3bd5 CK	32	#include "atom.h"
	33
	34	/*
	35	* HDMI color format
	36	*/
	37	enum r600_hdmi_color_format {
	38	RGB = 0,
	39	YCC_422 = 1,
	40	YCC_444 = 2
	41	};
	42
	43	/*
	44	* IEC60958 status bits
	45	*/
	46	enum r600_hdmi_iec_status_bits {
	47	AUDIO_STATUS_DIG_ENABLE = 0x01,
3fe373d9 RM	48	AUDIO_STATUS_V = 0x02,
3fe373d9 RM	49	AUDIO_STATUS_VCFG = 0x04,
dafc3bd5 CK	50	AUDIO_STATUS_EMPHASIS = 0x08,
	51	AUDIO_STATUS_COPYRIGHT = 0x10,
	52	AUDIO_STATUS_NONAUDIO = 0x20,
	53	AUDIO_STATUS_PROFESSIONAL = 0x40,
3fe373d9	54	AUDIO_STATUS_LEVEL = 0x80
dafc3bd5 CK	55	};
dafc3bd5 CK	56
1109ca09	57	static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
dafc3bd5 CK	58	/* 32kHz 44.1kHz 48kHz */
	59	/* Clock N CTS N CTS N CTS */
	60	{ 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */
	61	{ 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
	62	{ 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
	63	{ 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.001.001 MHz /
	64	{ 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
	65	{ 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.001.001 MHz /
	66	{ 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */
	67	{ 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
	68	{ 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */
	69	{ 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
	70	{ 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */
	71	};
	72
	73	/*
	74	* calculate CTS value if it's not found in the table
	75	*/
1b688d08	76	static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq)
dafc3bd5 CK	77	{
dafc3bd5 CK	78	if (*CTS == 0)
3fe373d9	79	CTS = clock N / (128 * freq) * 1000;
dafc3bd5 CK	80	DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n",
	81	N, *CTS, freq);
	82	}
	83
1b688d08 RM	84	struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock)
	85	{
	86	struct radeon_hdmi_acr res;
	87	u8 i;
	88
	89	for (i = 0; r600_hdmi_predefined_acr[i].clock != clock &&
	90	r600_hdmi_predefined_acr[i].clock != 0; i++)
	91	;
	92	res = r600_hdmi_predefined_acr[i];
	93
	94	/* In case some CTS are missing */
	95	r600_hdmi_calc_cts(clock, &res.cts_32khz, res.n_32khz, 32000);
	96	r600_hdmi_calc_cts(clock, &res.cts_44_1khz, res.n_44_1khz, 44100);
	97	r600_hdmi_calc_cts(clock, &res.cts_48khz, res.n_48khz, 48000);
	98
	99	return res;
	100	}
	101
dafc3bd5 CK	102	/*
	103	* update the N and CTS parameters for a given pixel clock rate
	104	*/
	105	static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
	106	{
	107	struct drm_device *dev = encoder->dev;
	108	struct radeon_device *rdev = dev->dev_private;
1b688d08	109	struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
cfcbd6d3 RM	110	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	111	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	112	uint32_t offset = dig->afmt->offset;
dafc3bd5	113
1b688d08 RM	114	WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz));
1b688d08 RM	115	WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz);
dafc3bd5	116
1b688d08 RM	117	WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz));
1b688d08 RM	118	WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz);
dafc3bd5	119
1b688d08 RM	120	WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz));
1b688d08 RM	121	WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz);
dafc3bd5 CK	122	}
dafc3bd5 CK	123
dafc3bd5 CK	124	/*
	125	* build a HDMI Video Info Frame
	126	*/
e3b2e034 TR	127	static void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
e3b2e034 TR	128	void *buffer, size_t size)
dafc3bd5 CK	129	{
	130	struct drm_device *dev = encoder->dev;
	131	struct radeon_device *rdev = dev->dev_private;
cfcbd6d3 RM	132	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	133	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	134	uint32_t offset = dig->afmt->offset;
e3b2e034	135	uint8_t *frame = buffer + 3;
dafc3bd5	136
92db7f6c RM	137	/* Our header values (type, version, length) should be alright, Intel
	138	* is using the same. Checksum function also seems to be OK, it works
	139	* fine for audio infoframe. However calculated value is always lower
	140	* by 2 in comparison to fglrx. It breaks displaying anything in case
	141	* of TVs that strictly check the checksum. Hack it manually here to
	142	* workaround this issue. */
	143	frame[0x0] += 2;
dafc3bd5	144
c6543a6e	145	WREG32(HDMI0_AVI_INFO0 + offset,
dafc3bd5	146	frame[0x0] \| (frame[0x1] << 8) \| (frame[0x2] << 16) \| (frame[0x3] << 24));
c6543a6e	147	WREG32(HDMI0_AVI_INFO1 + offset,
dafc3bd5	148	frame[0x4] \| (frame[0x5] << 8) \| (frame[0x6] << 16) \| (frame[0x7] << 24));
c6543a6e	149	WREG32(HDMI0_AVI_INFO2 + offset,
dafc3bd5	150	frame[0x8] \| (frame[0x9] << 8) \| (frame[0xA] << 16) \| (frame[0xB] << 24));
c6543a6e	151	WREG32(HDMI0_AVI_INFO3 + offset,
dafc3bd5 CK	152	frame[0xC] \| (frame[0xD] << 8));
	153	}
	154
	155	/*
	156	* build a Audio Info Frame
	157	*/
e3b2e034 TR	158	static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder,
e3b2e034 TR	159	const void *buffer, size_t size)
dafc3bd5 CK	160	{
	161	struct drm_device *dev = encoder->dev;
	162	struct radeon_device *rdev = dev->dev_private;
cfcbd6d3 RM	163	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	164	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	165	uint32_t offset = dig->afmt->offset;
e3b2e034	166	const u8 *frame = buffer + 3;
dafc3bd5	167
c6543a6e	168	WREG32(HDMI0_AUDIO_INFO0 + offset,
dafc3bd5	169	frame[0x0] \| (frame[0x1] << 8) \| (frame[0x2] << 16) \| (frame[0x3] << 24));
c6543a6e	170	WREG32(HDMI0_AUDIO_INFO1 + offset,
dafc3bd5 CK	171	frame[0x4] \| (frame[0x5] << 8) \| (frame[0x6] << 16) \| (frame[0x8] << 24));
	172	}
	173
	174	/*
	175	* test if audio buffer is filled enough to start playing
	176	*/
cfcbd6d3	177	static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
dafc3bd5 CK	178	{
	179	struct drm_device *dev = encoder->dev;
	180	struct radeon_device *rdev = dev->dev_private;
cfcbd6d3 RM	181	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	182	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	183	uint32_t offset = dig->afmt->offset;
dafc3bd5	184
c6543a6e	185	return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
dafc3bd5 CK	186	}
	187
	188	/*
	189	* have buffer status changed since last call?
	190	*/
	191	int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
	192	{
	193	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
cfcbd6d3	194	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
dafc3bd5 CK	195	int status, result;
dafc3bd5 CK	196
cfcbd6d3	197	if (!dig->afmt \|\| !dig->afmt->enabled)
dafc3bd5 CK	198	return 0;
	199
	200	status = r600_hdmi_is_audio_buffer_filled(encoder);
cfcbd6d3 RM	201	result = dig->afmt->last_buffer_filled_status != status;
cfcbd6d3 RM	202	dig->afmt->last_buffer_filled_status = status;
dafc3bd5 CK	203
	204	return result;
	205	}
	206
	207	/*
	208	* write the audio workaround status to the hardware
	209	*/
cfcbd6d3	210	static void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
dafc3bd5 CK	211	{
	212	struct drm_device *dev = encoder->dev;
	213	struct radeon_device *rdev = dev->dev_private;
	214	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
cfcbd6d3 RM	215	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	216	uint32_t offset = dig->afmt->offset;
	217	bool hdmi_audio_workaround = false; /* FIXME */
	218	u32 value;
	219
	220	if (!hdmi_audio_workaround \|\|
	221	r600_hdmi_is_audio_buffer_filled(encoder))
	222	value = 0; /* disable workaround */
	223	else
	224	value = HDMI0_AUDIO_TEST_EN; /* enable workaround */
	225	WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
	226	value, ~HDMI0_AUDIO_TEST_EN);
dafc3bd5 CK	227	}
dafc3bd5 CK	228
b1f6f47e AD	229	void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
	230	{
	231	struct drm_device *dev = encoder->dev;
	232	struct radeon_device *rdev = dev->dev_private;
	233	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	234	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
	235	u32 base_rate = 48000;
	236
	237	if (!dig \|\| !dig->afmt)
	238	return;
	239
	240	/* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT.
	241	* doesn't matter which one you use. Just use the first one.
	242	*/
	243	/* XXX: properly calculate this */
	244	/* XXX two dtos; generally use dto0 for hdmi */
	245	/* Express [24MHz / target pixel clock] as an exact rational
	246	* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
	247	* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
	248	*/
	249	WREG32(DCCG_AUDIO_DTO0_PHASE, (base_rate*50) & 0xffffff);
	250	WREG32(DCCG_AUDIO_DTO0_MODULE, (clock*100) & 0xffffff);
	251	WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
	252	}
dafc3bd5 CK	253
	254	/*
	255	* update the info frames with the data from the current display mode
	256	*/
	257	void r600_hdmi_setmode(struct drm_encoder encoder, struct drm_display_mode mode)
	258	{
	259	struct drm_device *dev = encoder->dev;
	260	struct radeon_device *rdev = dev->dev_private;
cfcbd6d3 RM	261	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
cfcbd6d3 RM	262	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
e3b2e034 TR	263	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
e3b2e034 TR	264	struct hdmi_avi_infoframe frame;
cfcbd6d3	265	uint32_t offset;
e3b2e034	266	ssize_t err;
dafc3bd5	267
cfcbd6d3 RM	268	/* Silent, r600_hdmi_enable will raise WARN for us */
cfcbd6d3 RM	269	if (!dig->afmt->enabled)
dafc3bd5	270	return;
cfcbd6d3	271	offset = dig->afmt->offset;
dafc3bd5	272
b1f6f47e	273	r600_audio_set_dto(encoder, mode->clock);
dafc3bd5	274
1c3439f2 RM	275	WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
	276	HDMI0_NULL_SEND); /* send null packets when required */
	277
c6543a6e	278	WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);
a273a903	279
1c3439f2 RM	280	if (ASIC_IS_DCE32(rdev)) {
	281	WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
	282	HDMI0_AUDIO_DELAY_EN(1) \| /* default audio delay */
	283	HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
	284	WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
	285	AFMT_AUDIO_SAMPLE_SEND \| /* send audio packets */
	286	AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
	287	} else {
	288	WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
	289	HDMI0_AUDIO_SAMPLE_SEND \| /* send audio packets */
	290	HDMI0_AUDIO_DELAY_EN(1) \| /* default audio delay */
1c3439f2 RM	291	HDMI0_AUDIO_PACKETS_PER_LINE(3) \| /* should be suffient for all audio modes and small enough for all hblanks */
	292	HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
	293	}
a273a903	294
1c3439f2 RM	295	WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
	296	HDMI0_ACR_AUTO_SEND \| /* allow hw to sent ACR packets when required */
	297	HDMI0_ACR_SOURCE); /* select SW CTS value */
dafc3bd5	298
1c3439f2 RM	299	WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
	300	HDMI0_NULL_SEND \| /* send null packets when required */
	301	HDMI0_GC_SEND \| /* send general control packets */
	302	HDMI0_GC_CONT); /* send general control packets every frame */
dafc3bd5	303
1c3439f2 RM	304	/* TODO: HDMI0_AUDIO_INFO_UPDATE */
	305	WREG32(HDMI0_INFOFRAME_CONTROL0 + offset,
	306	HDMI0_AVI_INFO_SEND \| /* enable AVI info frames */
	307	HDMI0_AVI_INFO_CONT \| /* send AVI info frames every frame/field */
	308	HDMI0_AUDIO_INFO_SEND \| /* enable audio info frames (frames won't be set until audio is enabled) */
	309	HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */
dafc3bd5	310
1c3439f2 RM	311	WREG32(HDMI0_INFOFRAME_CONTROL1 + offset,
	312	HDMI0_AVI_INFO_LINE(2) \| /* anything other than 0 */
	313	HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */
	314
	315	WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */
dafc3bd5	316
e3b2e034 TR	317	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
	318	if (err < 0) {
	319	DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
	320	return;
	321	}
dafc3bd5	322
e3b2e034 TR	323	err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
	324	if (err < 0) {
	325	DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
	326	return;
	327	}
	328
	329	r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1c3439f2 RM	330	r600_hdmi_update_ACR(encoder, mode->clock);
1c3439f2 RM	331
25985edc	332	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
c6543a6e RM	333	WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
	334	WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
	335	WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
	336	WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
dafc3bd5 CK	337
dafc3bd5 CK	338	r600_hdmi_audio_workaround(encoder);
dafc3bd5 CK	339	}
	340
	341	/*
	342	* update settings with current parameters from audio engine
	343	*/
58bd0863	344	void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
dafc3bd5 CK	345	{
	346	struct drm_device *dev = encoder->dev;
	347	struct radeon_device *rdev = dev->dev_private;
cfcbd6d3 RM	348	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
cfcbd6d3 RM	349	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
3299de95	350	struct r600_audio audio = r600_audio_status(rdev);
e3b2e034 TR	351	uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
e3b2e034 TR	352	struct hdmi_audio_infoframe frame;
cfcbd6d3	353	uint32_t offset;
dafc3bd5	354	uint32_t iec;
e3b2e034	355	ssize_t err;
dafc3bd5	356
cfcbd6d3	357	if (!dig->afmt \|\| !dig->afmt->enabled)
dafc3bd5	358	return;
cfcbd6d3	359	offset = dig->afmt->offset;
dafc3bd5 CK	360
	361	DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
	362	r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
3299de95	363	audio.channels, audio.rate, audio.bits_per_sample);
dafc3bd5	364	DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
3299de95	365	(int)audio.status_bits, (int)audio.category_code);
dafc3bd5 CK	366
dafc3bd5 CK	367	iec = 0;
3299de95	368	if (audio.status_bits & AUDIO_STATUS_PROFESSIONAL)
dafc3bd5	369	iec \|= 1 << 0;
3299de95	370	if (audio.status_bits & AUDIO_STATUS_NONAUDIO)
dafc3bd5	371	iec \|= 1 << 1;
3299de95	372	if (audio.status_bits & AUDIO_STATUS_COPYRIGHT)
dafc3bd5	373	iec \|= 1 << 2;
3299de95	374	if (audio.status_bits & AUDIO_STATUS_EMPHASIS)
dafc3bd5 CK	375	iec \|= 1 << 3;
dafc3bd5 CK	376
3299de95	377	iec \|= HDMI0_60958_CS_CATEGORY_CODE(audio.category_code);
dafc3bd5	378
3299de95	379	switch (audio.rate) {
a366e392 RM	380	case 32000:
	381	iec \|= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3);
	382	break;
	383	case 44100:
	384	iec \|= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0);
	385	break;
	386	case 48000:
	387	iec \|= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2);
	388	break;
	389	case 88200:
	390	iec \|= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8);
	391	break;
	392	case 96000:
	393	iec \|= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa);
	394	break;
	395	case 176400:
	396	iec \|= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc);
	397	break;
	398	case 192000:
	399	iec \|= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe);
	400	break;
dafc3bd5 CK	401	}
dafc3bd5 CK	402
c6543a6e	403	WREG32(HDMI0_60958_0 + offset, iec);
dafc3bd5 CK	404
dafc3bd5 CK	405	iec = 0;
3299de95	406	switch (audio.bits_per_sample) {
a366e392 RM	407	case 16:
	408	iec \|= HDMI0_60958_CS_WORD_LENGTH(0x2);
	409	break;
	410	case 20:
	411	iec \|= HDMI0_60958_CS_WORD_LENGTH(0x3);
	412	break;
	413	case 24:
	414	iec \|= HDMI0_60958_CS_WORD_LENGTH(0xb);
	415	break;
dafc3bd5	416	}
3299de95	417	if (audio.status_bits & AUDIO_STATUS_V)
dafc3bd5	418	iec \|= 0x5 << 16;
c6543a6e	419	WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f);
dafc3bd5	420
e3b2e034 TR	421	err = hdmi_audio_infoframe_init(&frame);
	422	if (err < 0) {
	423	DRM_ERROR("failed to setup audio infoframe\n");
	424	return;
	425	}
	426
	427	frame.channels = audio.channels;
	428
	429	err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
	430	if (err < 0) {
	431	DRM_ERROR("failed to pack audio infoframe\n");
	432	return;
	433	}
dafc3bd5	434
e3b2e034	435	r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer));
dafc3bd5	436	r600_hdmi_audio_workaround(encoder);
dafc3bd5 CK	437	}
dafc3bd5 CK	438
dafc3bd5	439	/*
2cd6218c	440	* enable the HDMI engine
dafc3bd5	441	*/
a973bea1	442	void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
dafc3bd5	443	{
2cd6218c RM	444	struct drm_device *dev = encoder->dev;
2cd6218c RM	445	struct radeon_device *rdev = dev->dev_private;
dafc3bd5	446	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
cfcbd6d3	447	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
a973bea1	448	u32 hdmi = HDMI0_ERROR_ACK;
16823d16	449
cfcbd6d3	450	/* Silent, r600_hdmi_enable will raise WARN for us */
a973bea1 AD	451	if (enable && dig->afmt->enabled)
	452	return;
	453	if (!enable && !dig->afmt->enabled)
cfcbd6d3	454	return;
64fb4fb0 RM	455
64fb4fb0 RM	456	/* Older chipsets require setting HDMI and routing manually */
a973bea1 AD	457	if (!ASIC_IS_DCE3(rdev)) {
	458	if (enable)
	459	hdmi \|= HDMI0_ENABLE;
5715f67c RM	460	switch (radeon_encoder->encoder_id) {
5715f67c RM	461	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
a973bea1 AD	462	if (enable) {
	463	WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
	464	hdmi \|= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
	465	} else {
	466	WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
	467	}
5715f67c RM	468	break;
5715f67c RM	469	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
a973bea1 AD	470	if (enable) {
	471	WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
	472	hdmi \|= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
	473	} else {
	474	WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
	475	}
64fb4fb0 RM	476	break;
64fb4fb0 RM	477	case ENCODER_OBJECT_ID_INTERNAL_DDI:
a973bea1 AD	478	if (enable) {
	479	WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
	480	hdmi \|= HDMI0_STREAM(HDMI0_STREAM_DDIA);
	481	} else {
	482	WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
	483	}
64fb4fb0 RM	484	break;
64fb4fb0 RM	485	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
a973bea1 AD	486	if (enable)
a973bea1 AD	487	hdmi \|= HDMI0_STREAM(HDMI0_STREAM_DVOA);
5715f67c RM	488	break;
5715f67c RM	489	default:
64fb4fb0 RM	490	dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
64fb4fb0 RM	491	radeon_encoder->encoder_id);
5715f67c RM	492	break;
5715f67c RM	493	}
a973bea1	494	WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);
5715f67c	495	}
2cd6218c	496
f122c610	497	if (rdev->irq.installed) {
f2594933	498	/* if irq is available use it */
9054ae1c	499	/* XXX: shouldn't need this on any asics. Double check DCE2/3 */
a973bea1	500	if (enable)
9054ae1c	501	radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
a973bea1 AD	502	else
a973bea1 AD	503	radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
f2594933	504	}
58bd0863	505
a973bea1	506	dig->afmt->enabled = enable;
cfcbd6d3	507
a973bea1 AD	508	DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
a973bea1 AD	509	enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
2cd6218c	510	}
dafc3bd5	511