Commit | Line | Data |
---|---|---|
dafc3bd5 CK |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Christian König. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Christian König | |
25 | */ | |
e3b2e034 | 26 | #include <linux/hdmi.h> |
a2098250 | 27 | #include <linux/gcd.h> |
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/radeon_drm.h> | |
dafc3bd5 | 30 | #include "radeon.h" |
3574dda4 | 31 | #include "radeon_asic.h" |
3cdde027 | 32 | #include "radeon_audio.h" |
c6543a6e | 33 | #include "r600d.h" |
dafc3bd5 CK |
34 | #include "atom.h" |
35 | ||
36 | /* | |
37 | * HDMI color format | |
38 | */ | |
39 | enum r600_hdmi_color_format { | |
40 | RGB = 0, | |
41 | YCC_422 = 1, | |
42 | YCC_444 = 2 | |
43 | }; | |
44 | ||
45 | /* | |
46 | * IEC60958 status bits | |
47 | */ | |
48 | enum r600_hdmi_iec_status_bits { | |
49 | AUDIO_STATUS_DIG_ENABLE = 0x01, | |
3fe373d9 RM |
50 | AUDIO_STATUS_V = 0x02, |
51 | AUDIO_STATUS_VCFG = 0x04, | |
dafc3bd5 CK |
52 | AUDIO_STATUS_EMPHASIS = 0x08, |
53 | AUDIO_STATUS_COPYRIGHT = 0x10, | |
54 | AUDIO_STATUS_NONAUDIO = 0x20, | |
55 | AUDIO_STATUS_PROFESSIONAL = 0x40, | |
3fe373d9 | 56 | AUDIO_STATUS_LEVEL = 0x80 |
dafc3bd5 CK |
57 | }; |
58 | ||
72156676 AD |
59 | static struct r600_audio_pin r600_audio_status(struct radeon_device *rdev) |
60 | { | |
61 | struct r600_audio_pin status; | |
62 | uint32_t value; | |
63 | ||
64 | value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL); | |
65 | ||
66 | /* number of channels */ | |
67 | status.channels = (value & 0x7) + 1; | |
68 | ||
69 | /* bits per sample */ | |
70 | switch ((value & 0xF0) >> 4) { | |
71 | case 0x0: | |
72 | status.bits_per_sample = 8; | |
73 | break; | |
74 | case 0x1: | |
75 | status.bits_per_sample = 16; | |
76 | break; | |
77 | case 0x2: | |
78 | status.bits_per_sample = 20; | |
79 | break; | |
80 | case 0x3: | |
81 | status.bits_per_sample = 24; | |
82 | break; | |
83 | case 0x4: | |
84 | status.bits_per_sample = 32; | |
85 | break; | |
86 | default: | |
87 | dev_err(rdev->dev, "Unknown bits per sample 0x%x, using 16\n", | |
88 | (int)value); | |
89 | status.bits_per_sample = 16; | |
90 | } | |
91 | ||
92 | /* current sampling rate in HZ */ | |
93 | if (value & 0x4000) | |
94 | status.rate = 44100; | |
95 | else | |
96 | status.rate = 48000; | |
97 | status.rate *= ((value >> 11) & 0x7) + 1; | |
98 | status.rate /= ((value >> 8) & 0x7) + 1; | |
99 | ||
100 | value = RREG32(R600_AUDIO_STATUS_BITS); | |
101 | ||
102 | /* iec 60958 status bits */ | |
103 | status.status_bits = value & 0xff; | |
104 | ||
105 | /* iec 60958 category code */ | |
106 | status.category_code = (value >> 8) & 0xff; | |
107 | ||
108 | return status; | |
109 | } | |
110 | ||
111 | /* | |
112 | * update all hdmi interfaces with current audio parameters | |
113 | */ | |
114 | void r600_audio_update_hdmi(struct work_struct *work) | |
115 | { | |
116 | struct radeon_device *rdev = container_of(work, struct radeon_device, | |
117 | audio_work); | |
118 | struct drm_device *dev = rdev->ddev; | |
119 | struct r600_audio_pin audio_status = r600_audio_status(rdev); | |
120 | struct drm_encoder *encoder; | |
121 | bool changed = false; | |
122 | ||
123 | if (rdev->audio.pin[0].channels != audio_status.channels || | |
124 | rdev->audio.pin[0].rate != audio_status.rate || | |
125 | rdev->audio.pin[0].bits_per_sample != audio_status.bits_per_sample || | |
126 | rdev->audio.pin[0].status_bits != audio_status.status_bits || | |
127 | rdev->audio.pin[0].category_code != audio_status.category_code) { | |
128 | rdev->audio.pin[0] = audio_status; | |
129 | changed = true; | |
130 | } | |
131 | ||
132 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
133 | if (!radeon_encoder_is_digital(encoder)) | |
134 | continue; | |
135 | if (changed || r600_hdmi_buffer_status_changed(encoder)) | |
136 | r600_hdmi_update_audio_settings(encoder); | |
137 | } | |
138 | } | |
139 | ||
140 | /* enable the audio stream */ | |
141 | void r600_audio_enable(struct radeon_device *rdev, | |
142 | struct r600_audio_pin *pin, | |
d3d8c141 | 143 | u8 enable_mask) |
72156676 | 144 | { |
d3d8c141 | 145 | u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL); |
72156676 AD |
146 | |
147 | if (!pin) | |
148 | return; | |
149 | ||
d3d8c141 AD |
150 | if (enable_mask) { |
151 | tmp |= AUDIO_ENABLED; | |
152 | if (enable_mask & 1) | |
153 | tmp |= PIN0_AUDIO_ENABLED; | |
154 | if (enable_mask & 2) | |
155 | tmp |= PIN1_AUDIO_ENABLED; | |
156 | if (enable_mask & 4) | |
157 | tmp |= PIN2_AUDIO_ENABLED; | |
158 | if (enable_mask & 8) | |
159 | tmp |= PIN3_AUDIO_ENABLED; | |
72156676 | 160 | } else { |
d3d8c141 AD |
161 | tmp &= ~(AUDIO_ENABLED | |
162 | PIN0_AUDIO_ENABLED | | |
163 | PIN1_AUDIO_ENABLED | | |
164 | PIN2_AUDIO_ENABLED | | |
165 | PIN3_AUDIO_ENABLED); | |
72156676 | 166 | } |
d3d8c141 AD |
167 | |
168 | WREG32(AZ_HOT_PLUG_CONTROL, tmp); | |
72156676 AD |
169 | } |
170 | ||
72156676 AD |
171 | struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev) |
172 | { | |
173 | /* only one pin on 6xx-NI */ | |
174 | return &rdev->audio.pin[0]; | |
175 | } | |
176 | ||
64424d6e SG |
177 | void r600_hdmi_update_acr(struct drm_encoder *encoder, long offset, |
178 | const struct radeon_hdmi_acr *acr) | |
dafc3bd5 CK |
179 | { |
180 | struct drm_device *dev = encoder->dev; | |
181 | struct radeon_device *rdev = dev->dev_private; | |
64424d6e SG |
182 | |
183 | /* DCE 3.0 uses register that's normally for CRC_CONTROL */ | |
184 | uint32_t acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL : | |
185 | HDMI0_ACR_PACKET_CONTROL; | |
186 | WREG32_P(acr_ctl + offset, | |
187 | HDMI0_ACR_SOURCE | /* select SW CTS value */ | |
188 | HDMI0_ACR_AUTO_SEND, /* allow hw to sent ACR packets when required */ | |
189 | ~(HDMI0_ACR_SOURCE | | |
190 | HDMI0_ACR_AUTO_SEND)); | |
dafc3bd5 | 191 | |
68706337 | 192 | WREG32_P(HDMI0_ACR_32_0 + offset, |
64424d6e SG |
193 | HDMI0_ACR_CTS_32(acr->cts_32khz), |
194 | ~HDMI0_ACR_CTS_32_MASK); | |
68706337 | 195 | WREG32_P(HDMI0_ACR_32_1 + offset, |
64424d6e SG |
196 | HDMI0_ACR_N_32(acr->n_32khz), |
197 | ~HDMI0_ACR_N_32_MASK); | |
68706337 RM |
198 | |
199 | WREG32_P(HDMI0_ACR_44_0 + offset, | |
64424d6e SG |
200 | HDMI0_ACR_CTS_44(acr->cts_44_1khz), |
201 | ~HDMI0_ACR_CTS_44_MASK); | |
68706337 | 202 | WREG32_P(HDMI0_ACR_44_1 + offset, |
64424d6e SG |
203 | HDMI0_ACR_N_44(acr->n_44_1khz), |
204 | ~HDMI0_ACR_N_44_MASK); | |
68706337 RM |
205 | |
206 | WREG32_P(HDMI0_ACR_48_0 + offset, | |
64424d6e SG |
207 | HDMI0_ACR_CTS_48(acr->cts_48khz), |
208 | ~HDMI0_ACR_CTS_48_MASK); | |
68706337 | 209 | WREG32_P(HDMI0_ACR_48_1 + offset, |
64424d6e SG |
210 | HDMI0_ACR_N_48(acr->n_48khz), |
211 | ~HDMI0_ACR_N_48_MASK); | |
dafc3bd5 CK |
212 | } |
213 | ||
dafc3bd5 CK |
214 | /* |
215 | * build a HDMI Video Info Frame | |
216 | */ | |
96ea7afb SG |
217 | void r600_update_avi_infoframe(struct radeon_device *rdev, u32 offset, |
218 | unsigned char *buffer, size_t size) | |
dafc3bd5 | 219 | { |
e3b2e034 | 220 | uint8_t *frame = buffer + 3; |
dafc3bd5 | 221 | |
c6543a6e | 222 | WREG32(HDMI0_AVI_INFO0 + offset, |
dafc3bd5 | 223 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
c6543a6e | 224 | WREG32(HDMI0_AVI_INFO1 + offset, |
dafc3bd5 | 225 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
c6543a6e | 226 | WREG32(HDMI0_AVI_INFO2 + offset, |
dafc3bd5 | 227 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
c6543a6e | 228 | WREG32(HDMI0_AVI_INFO3 + offset, |
96ea7afb | 229 | frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24)); |
dafc3bd5 CK |
230 | } |
231 | ||
232 | /* | |
233 | * build a Audio Info Frame | |
234 | */ | |
e3b2e034 TR |
235 | static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder, |
236 | const void *buffer, size_t size) | |
dafc3bd5 CK |
237 | { |
238 | struct drm_device *dev = encoder->dev; | |
239 | struct radeon_device *rdev = dev->dev_private; | |
cfcbd6d3 RM |
240 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
241 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
242 | uint32_t offset = dig->afmt->offset; | |
e3b2e034 | 243 | const u8 *frame = buffer + 3; |
dafc3bd5 | 244 | |
c6543a6e | 245 | WREG32(HDMI0_AUDIO_INFO0 + offset, |
dafc3bd5 | 246 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
c6543a6e | 247 | WREG32(HDMI0_AUDIO_INFO1 + offset, |
dafc3bd5 CK |
248 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24)); |
249 | } | |
250 | ||
251 | /* | |
252 | * test if audio buffer is filled enough to start playing | |
253 | */ | |
cfcbd6d3 | 254 | static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder) |
dafc3bd5 CK |
255 | { |
256 | struct drm_device *dev = encoder->dev; | |
257 | struct radeon_device *rdev = dev->dev_private; | |
cfcbd6d3 RM |
258 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
259 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
260 | uint32_t offset = dig->afmt->offset; | |
dafc3bd5 | 261 | |
c6543a6e | 262 | return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0; |
dafc3bd5 CK |
263 | } |
264 | ||
265 | /* | |
266 | * have buffer status changed since last call? | |
267 | */ | |
268 | int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder) | |
269 | { | |
270 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
cfcbd6d3 | 271 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
dafc3bd5 CK |
272 | int status, result; |
273 | ||
cfcbd6d3 | 274 | if (!dig->afmt || !dig->afmt->enabled) |
dafc3bd5 CK |
275 | return 0; |
276 | ||
277 | status = r600_hdmi_is_audio_buffer_filled(encoder); | |
cfcbd6d3 RM |
278 | result = dig->afmt->last_buffer_filled_status != status; |
279 | dig->afmt->last_buffer_filled_status = status; | |
dafc3bd5 CK |
280 | |
281 | return result; | |
282 | } | |
283 | ||
284 | /* | |
285 | * write the audio workaround status to the hardware | |
286 | */ | |
8f33a156 | 287 | void r600_hdmi_audio_workaround(struct drm_encoder *encoder) |
dafc3bd5 CK |
288 | { |
289 | struct drm_device *dev = encoder->dev; | |
290 | struct radeon_device *rdev = dev->dev_private; | |
291 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | |
cfcbd6d3 RM |
292 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
293 | uint32_t offset = dig->afmt->offset; | |
294 | bool hdmi_audio_workaround = false; /* FIXME */ | |
295 | u32 value; | |
296 | ||
297 | if (!hdmi_audio_workaround || | |
298 | r600_hdmi_is_audio_buffer_filled(encoder)) | |
299 | value = 0; /* disable workaround */ | |
300 | else | |
301 | value = HDMI0_AUDIO_TEST_EN; /* enable workaround */ | |
302 | WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, | |
303 | value, ~HDMI0_AUDIO_TEST_EN); | |
dafc3bd5 CK |
304 | } |
305 | ||
a85d682a SG |
306 | void r600_hdmi_audio_set_dto(struct radeon_device *rdev, |
307 | struct radeon_crtc *crtc, unsigned int clock) | |
b1f6f47e | 308 | { |
a85d682a SG |
309 | struct radeon_encoder *radeon_encoder; |
310 | struct radeon_encoder_atom_dig *dig; | |
b1f6f47e | 311 | |
a85d682a | 312 | if (!crtc) |
b1f6f47e AD |
313 | return; |
314 | ||
a85d682a SG |
315 | radeon_encoder = to_radeon_encoder(crtc->encoder); |
316 | dig = radeon_encoder->enc_priv; | |
1518dd8e | 317 | |
a85d682a SG |
318 | if (!dig) |
319 | return; | |
320 | ||
321 | if (dig->dig_encoder == 0) { | |
322 | WREG32(DCCG_AUDIO_DTO0_PHASE, 24000 * 100); | |
323 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); | |
324 | WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ | |
55d4e020 | 325 | } else { |
a85d682a SG |
326 | WREG32(DCCG_AUDIO_DTO1_PHASE, 24000 * 100); |
327 | WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100); | |
328 | WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ | |
1586505a | 329 | } |
b1f6f47e | 330 | } |
dafc3bd5 | 331 | |
930a9785 AD |
332 | void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset) |
333 | { | |
334 | struct drm_device *dev = encoder->dev; | |
335 | struct radeon_device *rdev = dev->dev_private; | |
336 | ||
337 | WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset, | |
338 | HDMI0_NULL_SEND | /* send null packets when required */ | |
339 | HDMI0_GC_SEND | /* send general control packets */ | |
340 | HDMI0_GC_CONT); /* send general control packets every frame */ | |
341 | } | |
342 | ||
dafc3bd5 CK |
343 | /* |
344 | * update the info frames with the data from the current display mode | |
345 | */ | |
346 | void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) | |
347 | { | |
348 | struct drm_device *dev = encoder->dev; | |
349 | struct radeon_device *rdev = dev->dev_private; | |
cfcbd6d3 RM |
350 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
351 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
e3b2e034 TR |
352 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; |
353 | struct hdmi_avi_infoframe frame; | |
cfcbd6d3 | 354 | uint32_t offset; |
e3b2e034 | 355 | ssize_t err; |
dafc3bd5 | 356 | |
c2b4cacf AD |
357 | if (!dig || !dig->afmt) |
358 | return; | |
359 | ||
cfcbd6d3 RM |
360 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
361 | if (!dig->afmt->enabled) | |
dafc3bd5 | 362 | return; |
cfcbd6d3 | 363 | offset = dig->afmt->offset; |
dafc3bd5 | 364 | |
832eafaf | 365 | /* disable audio prior to setting up hw */ |
3cdde027 | 366 | dig->afmt->pin = radeon_audio_get_pin(encoder); |
8bf59820 | 367 | radeon_audio_enable(rdev, dig->afmt->pin, 0); |
832eafaf | 368 | |
a85d682a | 369 | radeon_audio_set_dto(encoder, mode->clock); |
930a9785 | 370 | radeon_audio_set_vbi_packet(encoder); |
be273e58 | 371 | radeon_hdmi_set_color_depth(encoder); |
dafc3bd5 | 372 | |
68706337 RM |
373 | WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, |
374 | HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ | |
375 | HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ | |
376 | HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */ | |
377 | HDMI0_60958_CS_UPDATE, /* allow 60958 channel status fields to be updated */ | |
378 | ~(HDMI0_AUDIO_SAMPLE_SEND | | |
379 | HDMI0_AUDIO_DELAY_EN_MASK | | |
380 | HDMI0_AUDIO_PACKETS_PER_LINE_MASK | | |
381 | HDMI0_60958_CS_UPDATE)); | |
0ffae60c | 382 | |
68706337 RM |
383 | WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, |
384 | HDMI0_AVI_INFO_SEND | /* enable AVI info frames */ | |
385 | HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */ | |
386 | HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ | |
387 | HDMI0_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ | |
388 | ||
389 | WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset, | |
390 | HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */ | |
391 | HDMI0_AUDIO_INFO_LINE(2), /* anything other than 0 */ | |
392 | ~(HDMI0_AVI_INFO_LINE_MASK | | |
393 | HDMI0_AUDIO_INFO_LINE_MASK)); | |
394 | ||
395 | WREG32_AND(HDMI0_GC + offset, | |
396 | ~HDMI0_GC_AVMUTE); /* unset HDMI0_GC_AVMUTE */ | |
dafc3bd5 | 397 | |
e3b2e034 TR |
398 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); |
399 | if (err < 0) { | |
400 | DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); | |
401 | return; | |
402 | } | |
dafc3bd5 | 403 | |
e3b2e034 TR |
404 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); |
405 | if (err < 0) { | |
406 | DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); | |
407 | return; | |
408 | } | |
409 | ||
96ea7afb | 410 | radeon_update_avi_infoframe(encoder, buffer, sizeof(buffer)); |
68706337 RM |
411 | |
412 | /* fglrx duplicates INFOFRAME_CONTROL0 & INFOFRAME_CONTROL1 ops here */ | |
413 | ||
414 | WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset, | |
415 | ~(HDMI0_GENERIC0_SEND | | |
416 | HDMI0_GENERIC0_CONT | | |
417 | HDMI0_GENERIC0_UPDATE | | |
418 | HDMI0_GENERIC1_SEND | | |
419 | HDMI0_GENERIC1_CONT | | |
420 | HDMI0_GENERIC0_LINE_MASK | | |
421 | HDMI0_GENERIC1_LINE_MASK)); | |
422 | ||
64424d6e | 423 | radeon_audio_update_acr(encoder, mode->clock); |
1c3439f2 | 424 | |
68706337 RM |
425 | WREG32_P(HDMI0_60958_0 + offset, |
426 | HDMI0_60958_CS_CHANNEL_NUMBER_L(1), | |
427 | ~(HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK | | |
428 | HDMI0_60958_CS_CLOCK_ACCURACY_MASK)); | |
429 | ||
430 | WREG32_P(HDMI0_60958_1 + offset, | |
431 | HDMI0_60958_CS_CHANNEL_NUMBER_R(2), | |
432 | ~HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK); | |
433 | ||
25985edc | 434 | /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ |
c6543a6e RM |
435 | WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF); |
436 | WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF); | |
437 | WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001); | |
438 | WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); | |
dafc3bd5 | 439 | |
832eafaf | 440 | /* enable audio after to setting up hw */ |
8bf59820 | 441 | radeon_audio_enable(rdev, dig->afmt->pin, 0xf); |
dafc3bd5 CK |
442 | } |
443 | ||
8e4d9f81 RM |
444 | /** |
445 | * r600_hdmi_update_audio_settings - Update audio infoframe | |
446 | * | |
447 | * @encoder: drm encoder | |
448 | * | |
449 | * Gets info about current audio stream and updates audio infoframe. | |
dafc3bd5 | 450 | */ |
58bd0863 | 451 | void r600_hdmi_update_audio_settings(struct drm_encoder *encoder) |
dafc3bd5 CK |
452 | { |
453 | struct drm_device *dev = encoder->dev; | |
454 | struct radeon_device *rdev = dev->dev_private; | |
cfcbd6d3 RM |
455 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
456 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | |
b530602f | 457 | struct r600_audio_pin audio = r600_audio_status(rdev); |
e3b2e034 TR |
458 | uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; |
459 | struct hdmi_audio_infoframe frame; | |
cfcbd6d3 | 460 | uint32_t offset; |
8e4d9f81 | 461 | uint32_t value; |
e3b2e034 | 462 | ssize_t err; |
dafc3bd5 | 463 | |
cfcbd6d3 | 464 | if (!dig->afmt || !dig->afmt->enabled) |
dafc3bd5 | 465 | return; |
cfcbd6d3 | 466 | offset = dig->afmt->offset; |
dafc3bd5 CK |
467 | |
468 | DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n", | |
469 | r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped", | |
3299de95 | 470 | audio.channels, audio.rate, audio.bits_per_sample); |
dafc3bd5 | 471 | DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n", |
3299de95 | 472 | (int)audio.status_bits, (int)audio.category_code); |
dafc3bd5 | 473 | |
e3b2e034 TR |
474 | err = hdmi_audio_infoframe_init(&frame); |
475 | if (err < 0) { | |
476 | DRM_ERROR("failed to setup audio infoframe\n"); | |
477 | return; | |
478 | } | |
479 | ||
480 | frame.channels = audio.channels; | |
481 | ||
482 | err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); | |
483 | if (err < 0) { | |
484 | DRM_ERROR("failed to pack audio infoframe\n"); | |
485 | return; | |
486 | } | |
dafc3bd5 | 487 | |
8e4d9f81 RM |
488 | value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset); |
489 | if (value & HDMI0_AUDIO_TEST_EN) | |
490 | WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, | |
491 | value & ~HDMI0_AUDIO_TEST_EN); | |
492 | ||
493 | WREG32_OR(HDMI0_CONTROL + offset, | |
494 | HDMI0_ERROR_ACK); | |
495 | ||
496 | WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset, | |
497 | ~HDMI0_AUDIO_INFO_SOURCE); | |
498 | ||
e3b2e034 | 499 | r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer)); |
8e4d9f81 RM |
500 | |
501 | WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, | |
502 | HDMI0_AUDIO_INFO_CONT | | |
503 | HDMI0_AUDIO_INFO_UPDATE); | |
dafc3bd5 CK |
504 | } |
505 | ||
dafc3bd5 | 506 | /* |
2cd6218c | 507 | * enable the HDMI engine |
dafc3bd5 | 508 | */ |
a973bea1 | 509 | void r600_hdmi_enable(struct drm_encoder *encoder, bool enable) |
dafc3bd5 | 510 | { |
2cd6218c RM |
511 | struct drm_device *dev = encoder->dev; |
512 | struct radeon_device *rdev = dev->dev_private; | |
dafc3bd5 | 513 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
cfcbd6d3 | 514 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
a973bea1 | 515 | u32 hdmi = HDMI0_ERROR_ACK; |
16823d16 | 516 | |
c2b4cacf AD |
517 | if (!dig || !dig->afmt) |
518 | return; | |
519 | ||
cfcbd6d3 | 520 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
a973bea1 AD |
521 | if (enable && dig->afmt->enabled) |
522 | return; | |
523 | if (!enable && !dig->afmt->enabled) | |
cfcbd6d3 | 524 | return; |
64fb4fb0 | 525 | |
4adb34ef | 526 | if (!enable && dig->afmt->pin) { |
8bf59820 | 527 | radeon_audio_enable(rdev, dig->afmt->pin, 0); |
4adb34ef AD |
528 | dig->afmt->pin = NULL; |
529 | } | |
530 | ||
64fb4fb0 | 531 | /* Older chipsets require setting HDMI and routing manually */ |
a973bea1 AD |
532 | if (!ASIC_IS_DCE3(rdev)) { |
533 | if (enable) | |
534 | hdmi |= HDMI0_ENABLE; | |
5715f67c RM |
535 | switch (radeon_encoder->encoder_id) { |
536 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: | |
a973bea1 AD |
537 | if (enable) { |
538 | WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN); | |
539 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA); | |
540 | } else { | |
541 | WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN); | |
542 | } | |
5715f67c RM |
543 | break; |
544 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: | |
a973bea1 AD |
545 | if (enable) { |
546 | WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN); | |
547 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA); | |
548 | } else { | |
549 | WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN); | |
550 | } | |
64fb4fb0 RM |
551 | break; |
552 | case ENCODER_OBJECT_ID_INTERNAL_DDI: | |
a973bea1 AD |
553 | if (enable) { |
554 | WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN); | |
555 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA); | |
556 | } else { | |
557 | WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN); | |
558 | } | |
64fb4fb0 RM |
559 | break; |
560 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: | |
a973bea1 AD |
561 | if (enable) |
562 | hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA); | |
5715f67c RM |
563 | break; |
564 | default: | |
64fb4fb0 RM |
565 | dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n", |
566 | radeon_encoder->encoder_id); | |
5715f67c RM |
567 | break; |
568 | } | |
a973bea1 | 569 | WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi); |
5715f67c | 570 | } |
2cd6218c | 571 | |
f122c610 | 572 | if (rdev->irq.installed) { |
f2594933 | 573 | /* if irq is available use it */ |
9054ae1c | 574 | /* XXX: shouldn't need this on any asics. Double check DCE2/3 */ |
a973bea1 | 575 | if (enable) |
9054ae1c | 576 | radeon_irq_kms_enable_afmt(rdev, dig->afmt->id); |
a973bea1 AD |
577 | else |
578 | radeon_irq_kms_disable_afmt(rdev, dig->afmt->id); | |
f2594933 | 579 | } |
58bd0863 | 580 | |
a973bea1 | 581 | dig->afmt->enabled = enable; |
cfcbd6d3 | 582 | |
a973bea1 AD |
583 | DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
584 | enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); | |
2cd6218c | 585 | } |
dafc3bd5 | 586 |