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radeon/audio: consolidate audio_set_dto() functions
[deliverable/linux.git] / drivers / gpu / drm / radeon / r600_hdmi.c
CommitLineData
dafc3bd5
CK		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Christian König
25 */
e3b2e034 26#include <linux/hdmi.h>
a2098250 27#include <linux/gcd.h>
760285e7
DH		 28#include <drm/drmP.h>
29#include <drm/radeon_drm.h>
dafc3bd5 30#include "radeon.h"
3574dda4 31#include "radeon_asic.h"
3cdde027 32#include "radeon_audio.h"
c6543a6e 33#include "r600d.h"
dafc3bd5
CK		 34#include "atom.h"
35
36/*
37 * HDMI color format
38 */
39enum r600_hdmi_color_format {
40 RGB = 0,
41 YCC_422 = 1,
42 YCC_444 = 2
43};
44
45/*
46 * IEC60958 status bits
47 */
48enum r600_hdmi_iec_status_bits {
49 AUDIO_STATUS_DIG_ENABLE = 0x01,
3fe373d9
RM		 50 AUDIO_STATUS_V = 0x02,
51 AUDIO_STATUS_VCFG = 0x04,
dafc3bd5
CK		 52 AUDIO_STATUS_EMPHASIS = 0x08,
53 AUDIO_STATUS_COPYRIGHT = 0x10,
54 AUDIO_STATUS_NONAUDIO = 0x20,
55 AUDIO_STATUS_PROFESSIONAL = 0x40,
3fe373d9 56 AUDIO_STATUS_LEVEL = 0x80
dafc3bd5
CK		 57};
58
1109ca09 59static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
dafc3bd5
CK		 60 /* 32kHz 44.1kHz 48kHz */
61 /* Clock N CTS N CTS N CTS */
3e71985f 62 { 25175, 4096, 25175, 28224, 125875, 6144, 25175 }, /* 25,20/1.001 MHz */
dafc3bd5
CK		 63 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
64 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
65 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
66 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
67 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
3e71985f 68 { 74176, 4096, 74176, 5733, 75335, 6144, 74176 }, /* 74.25/1.001 MHz */
dafc3bd5 69 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
3e71985f 70 { 148352, 4096, 148352, 5733, 150670, 6144, 148352 }, /* 148.50/1.001 MHz */
dafc3bd5 71 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
dafc3bd5
CK		 72};
73
72156676
AD		 74static struct r600_audio_pin r600_audio_status(struct radeon_device *rdev)
75{
76 struct r600_audio_pin status;
77 uint32_t value;
78
79 value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL);
80
81 /* number of channels */
82 status.channels = (value & 0x7) + 1;
83
84 /* bits per sample */
85 switch ((value & 0xF0) >> 4) {
86 case 0x0:
87 status.bits_per_sample = 8;
88 break;
89 case 0x1:
90 status.bits_per_sample = 16;
91 break;
92 case 0x2:
93 status.bits_per_sample = 20;
94 break;
95 case 0x3:
96 status.bits_per_sample = 24;
97 break;
98 case 0x4:
99 status.bits_per_sample = 32;
100 break;
101 default:
102 dev_err(rdev->dev, "Unknown bits per sample 0x%x, using 16\n",
103 (int)value);
104 status.bits_per_sample = 16;
105 }
106
107 /* current sampling rate in HZ */
108 if (value & 0x4000)
109 status.rate = 44100;
110 else
111 status.rate = 48000;
112 status.rate *= ((value >> 11) & 0x7) + 1;
113 status.rate /= ((value >> 8) & 0x7) + 1;
114
115 value = RREG32(R600_AUDIO_STATUS_BITS);
116
117 /* iec 60958 status bits */
118 status.status_bits = value & 0xff;
119
120 /* iec 60958 category code */
121 status.category_code = (value >> 8) & 0xff;
122
123 return status;
124}
125
126/*
127 * update all hdmi interfaces with current audio parameters
128 */
129void r600_audio_update_hdmi(struct work_struct *work)
130{
131 struct radeon_device *rdev = container_of(work, struct radeon_device,
132 audio_work);
133 struct drm_device *dev = rdev->ddev;
134 struct r600_audio_pin audio_status = r600_audio_status(rdev);
135 struct drm_encoder *encoder;
136 bool changed = false;
137
138 if (rdev->audio.pin[0].channels != audio_status.channels ||
139 rdev->audio.pin[0].rate != audio_status.rate ||
140 rdev->audio.pin[0].bits_per_sample != audio_status.bits_per_sample ||
141 rdev->audio.pin[0].status_bits != audio_status.status_bits ||
142 rdev->audio.pin[0].category_code != audio_status.category_code) {
143 rdev->audio.pin[0] = audio_status;
144 changed = true;
145 }
146
147 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
148 if (!radeon_encoder_is_digital(encoder))
149 continue;
150 if (changed || r600_hdmi_buffer_status_changed(encoder))
151 r600_hdmi_update_audio_settings(encoder);
152 }
153}
154
155/* enable the audio stream */
156void r600_audio_enable(struct radeon_device *rdev,
157 struct r600_audio_pin *pin,
d3d8c141 158 u8 enable_mask)
72156676 159{
d3d8c141 160 u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
72156676
AD		 161
162 if (!pin)
163 return;
164
d3d8c141
AD		 165 if (enable_mask) {
166 tmp |= AUDIO_ENABLED;
167 if (enable_mask & 1)
168 tmp |= PIN0_AUDIO_ENABLED;
169 if (enable_mask & 2)
170 tmp |= PIN1_AUDIO_ENABLED;
171 if (enable_mask & 4)
172 tmp |= PIN2_AUDIO_ENABLED;
173 if (enable_mask & 8)
174 tmp |= PIN3_AUDIO_ENABLED;
72156676 175 } else {
d3d8c141
AD		 176 tmp &= ~(AUDIO_ENABLED |
177 PIN0_AUDIO_ENABLED |
178 PIN1_AUDIO_ENABLED |
179 PIN2_AUDIO_ENABLED |
180 PIN3_AUDIO_ENABLED);
72156676 181 }
d3d8c141
AD		 182
183 WREG32(AZ_HOT_PLUG_CONTROL, tmp);
72156676
AD		 184}
185
72156676
AD		 186struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev)
187{
188 /* only one pin on 6xx-NI */
189 return &rdev->audio.pin[0];
190}
191
dafc3bd5 192/*
a2098250 193 * calculate CTS and N values if they are not found in the table
dafc3bd5 194 */
a2098250 195static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int *N, int freq)
dafc3bd5 196{
a2098250
PO		 197 int n, cts;
198 unsigned long div, mul;
199
200 /* Safe, but overly large values */
201 n = 128 * freq;
202 cts = clock * 1000;
203
204 /* Smallest valid fraction */
205 div = gcd(n, cts);
206
207 n /= div;
208 cts /= div;
209
210 /*
211 * The optimal N is 128*freq/1000. Calculate the closest larger
212 * value that doesn't truncate any bits.
213 */
214 mul = ((128*freq/1000) + (n-1))/n;
215
216 n *= mul;
217 cts *= mul;
218
219 /* Check that we are in spec (not always possible) */
220 if (n < (128*freq/1500))
221 printk(KERN_WARNING "Calculated ACR N value is too small. You may experience audio problems.\n");
222 if (n > (128*freq/300))
223 printk(KERN_WARNING "Calculated ACR N value is too large. You may experience audio problems.\n");
224
225 *N = n;
226 *CTS = cts;
227
228 DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n",
229 *N, *CTS, freq);
dafc3bd5
CK		 230}
231
1b688d08
RM		 232struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock)
233{
234 struct radeon_hdmi_acr res;
235 u8 i;
236
a2098250
PO		 237 /* Precalculated values for common clocks */
238 for (i = 0; i < ARRAY_SIZE(r600_hdmi_predefined_acr); i++) {
239 if (r600_hdmi_predefined_acr[i].clock == clock)
240 return r600_hdmi_predefined_acr[i];
241 }
1b688d08 242
a2098250
PO		 243 /* And odd clocks get manually calculated */
244 r600_hdmi_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000);
245 r600_hdmi_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100);
246 r600_hdmi_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000);
1b688d08
RM		 247
248 return res;
249}
250
dafc3bd5
CK		 251/*
252 * update the N and CTS parameters for a given pixel clock rate
253 */
8f33a156 254void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
dafc3bd5
CK		 255{
256 struct drm_device *dev = encoder->dev;
257 struct radeon_device *rdev = dev->dev_private;
1b688d08 258 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
cfcbd6d3
RM		 259 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
260 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
261 uint32_t offset = dig->afmt->offset;
dafc3bd5 262
68706337
RM		 263 WREG32_P(HDMI0_ACR_32_0 + offset,
264 HDMI0_ACR_CTS_32(acr.cts_32khz),
265 ~HDMI0_ACR_CTS_32_MASK);
266 WREG32_P(HDMI0_ACR_32_1 + offset,
267 HDMI0_ACR_N_32(acr.n_32khz),
268 ~HDMI0_ACR_N_32_MASK);
269
270 WREG32_P(HDMI0_ACR_44_0 + offset,
271 HDMI0_ACR_CTS_44(acr.cts_44_1khz),
272 ~HDMI0_ACR_CTS_44_MASK);
273 WREG32_P(HDMI0_ACR_44_1 + offset,
274 HDMI0_ACR_N_44(acr.n_44_1khz),
275 ~HDMI0_ACR_N_44_MASK);
276
277 WREG32_P(HDMI0_ACR_48_0 + offset,
278 HDMI0_ACR_CTS_48(acr.cts_48khz),
279 ~HDMI0_ACR_CTS_48_MASK);
280 WREG32_P(HDMI0_ACR_48_1 + offset,
281 HDMI0_ACR_N_48(acr.n_48khz),
282 ~HDMI0_ACR_N_48_MASK);
dafc3bd5
CK		 283}
284
dafc3bd5
CK		 285/*
286 * build a HDMI Video Info Frame
287 */
8f33a156
RM		 288void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer,
289 size_t size)
dafc3bd5
CK		 290{
291 struct drm_device *dev = encoder->dev;
292 struct radeon_device *rdev = dev->dev_private;
cfcbd6d3
RM		 293 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
294 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
295 uint32_t offset = dig->afmt->offset;
e3b2e034 296 uint8_t *frame = buffer + 3;
f100380e 297 uint8_t *header = buffer;
dafc3bd5 298
c6543a6e 299 WREG32(HDMI0_AVI_INFO0 + offset,
dafc3bd5 300 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
c6543a6e 301 WREG32(HDMI0_AVI_INFO1 + offset,
dafc3bd5 302 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
c6543a6e 303 WREG32(HDMI0_AVI_INFO2 + offset,
dafc3bd5 304 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
c6543a6e 305 WREG32(HDMI0_AVI_INFO3 + offset,
f100380e 306 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
dafc3bd5
CK		 307}
308
309/*
310 * build a Audio Info Frame
311 */
e3b2e034
TR		 312static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder,
313 const void *buffer, size_t size)
dafc3bd5
CK		 314{
315 struct drm_device *dev = encoder->dev;
316 struct radeon_device *rdev = dev->dev_private;
cfcbd6d3
RM		 317 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
318 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
319 uint32_t offset = dig->afmt->offset;
e3b2e034 320 const u8 *frame = buffer + 3;
dafc3bd5 321
c6543a6e 322 WREG32(HDMI0_AUDIO_INFO0 + offset,
dafc3bd5 323 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
c6543a6e 324 WREG32(HDMI0_AUDIO_INFO1 + offset,
dafc3bd5
CK		 325 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
326}
327
328/*
329 * test if audio buffer is filled enough to start playing
330 */
cfcbd6d3 331static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
dafc3bd5
CK		 332{
333 struct drm_device *dev = encoder->dev;
334 struct radeon_device *rdev = dev->dev_private;
cfcbd6d3
RM		 335 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
336 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
337 uint32_t offset = dig->afmt->offset;
dafc3bd5 338
c6543a6e 339 return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
dafc3bd5
CK		 340}
341
342/*
343 * have buffer status changed since last call?
344 */
345int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
346{
347 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
cfcbd6d3 348 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
dafc3bd5
CK		 349 int status, result;
350
cfcbd6d3 351 if (!dig->afmt || !dig->afmt->enabled)
dafc3bd5
CK		 352 return 0;
353
354 status = r600_hdmi_is_audio_buffer_filled(encoder);
cfcbd6d3
RM		 355 result = dig->afmt->last_buffer_filled_status != status;
356 dig->afmt->last_buffer_filled_status = status;
dafc3bd5
CK		 357
358 return result;
359}
360
361/*
362 * write the audio workaround status to the hardware
363 */
8f33a156 364void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
dafc3bd5
CK		 365{
366 struct drm_device *dev = encoder->dev;
367 struct radeon_device *rdev = dev->dev_private;
368 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
cfcbd6d3
RM		 369 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
370 uint32_t offset = dig->afmt->offset;
371 bool hdmi_audio_workaround = false; /* FIXME */
372 u32 value;
373
374 if (!hdmi_audio_workaround ||
375 r600_hdmi_is_audio_buffer_filled(encoder))
376 value = 0; /* disable workaround */
377 else
378 value = HDMI0_AUDIO_TEST_EN; /* enable workaround */
379 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
380 value, ~HDMI0_AUDIO_TEST_EN);
dafc3bd5
CK		 381}
382
a85d682a
SG		 383void r600_hdmi_audio_set_dto(struct radeon_device *rdev,
384 struct radeon_crtc *crtc, unsigned int clock)
b1f6f47e 385{
a85d682a
SG		 386 struct radeon_encoder *radeon_encoder;
387 struct radeon_encoder_atom_dig *dig;
b1f6f47e 388
a85d682a 389 if (!crtc)
b1f6f47e
AD		 390 return;
391
a85d682a
SG		 392 radeon_encoder = to_radeon_encoder(crtc->encoder);
393 dig = radeon_encoder->enc_priv;
1518dd8e 394
a85d682a
SG		 395 if (!dig)
396 return;
397
398 if (dig->dig_encoder == 0) {
399 WREG32(DCCG_AUDIO_DTO0_PHASE, 24000 * 100);
400 WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
401 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
55d4e020 402 } else {
a85d682a
SG		 403 WREG32(DCCG_AUDIO_DTO1_PHASE, 24000 * 100);
404 WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);
405 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
1586505a 406 }
b1f6f47e 407}
dafc3bd5
CK		 408
409/*
410 * update the info frames with the data from the current display mode
411 */
412void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
413{
414 struct drm_device *dev = encoder->dev;
415 struct radeon_device *rdev = dev->dev_private;
cfcbd6d3
RM		 416 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
417 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
e3b2e034
TR		 418 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
419 struct hdmi_avi_infoframe frame;
cfcbd6d3 420 uint32_t offset;
2e93cac9 421 uint32_t acr_ctl;
e3b2e034 422 ssize_t err;
dafc3bd5 423
c2b4cacf
AD		 424 if (!dig || !dig->afmt)
425 return;
426
cfcbd6d3
RM		 427 /* Silent, r600_hdmi_enable will raise WARN for us */
428 if (!dig->afmt->enabled)
dafc3bd5 429 return;
cfcbd6d3 430 offset = dig->afmt->offset;
dafc3bd5 431
832eafaf 432 /* disable audio prior to setting up hw */
3cdde027 433 dig->afmt->pin = radeon_audio_get_pin(encoder);
8bf59820 434 radeon_audio_enable(rdev, dig->afmt->pin, 0);
832eafaf 435
a85d682a 436 radeon_audio_set_dto(encoder, mode->clock);
dafc3bd5 437
68706337
RM		 438 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
439 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
440 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
441 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
442 HDMI0_60958_CS_UPDATE, /* allow 60958 channel status fields to be updated */
443 ~(HDMI0_AUDIO_SAMPLE_SEND |
444 HDMI0_AUDIO_DELAY_EN_MASK |
445 HDMI0_AUDIO_PACKETS_PER_LINE_MASK |
446 HDMI0_60958_CS_UPDATE));
0ffae60c 447
2e93cac9
RM		 448 /* DCE 3.0 uses register that's normally for CRC_CONTROL */
449 acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL :
450 HDMI0_ACR_PACKET_CONTROL;
68706337
RM		 451 WREG32_P(acr_ctl + offset,
452 HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */
453 HDMI0_ACR_AUTO_SEND, /* allow hw to sent ACR packets when required */
454 ~(HDMI0_ACR_SOURCE |
455 HDMI0_ACR_AUTO_SEND));
456
457 WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset,
458 HDMI0_NULL_SEND | /* send null packets when required */
459 HDMI0_GC_SEND | /* send general control packets */
460 HDMI0_GC_CONT); /* send general control packets every frame */
461
462 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
463 HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
464 HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
465 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
466 HDMI0_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
467
468 WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset,
469 HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
470 HDMI0_AUDIO_INFO_LINE(2), /* anything other than 0 */
471 ~(HDMI0_AVI_INFO_LINE_MASK |
472 HDMI0_AUDIO_INFO_LINE_MASK));
473
474 WREG32_AND(HDMI0_GC + offset,
475 ~HDMI0_GC_AVMUTE); /* unset HDMI0_GC_AVMUTE */
dafc3bd5 476
e3b2e034
TR		 477 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
478 if (err < 0) {
479 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
480 return;
481 }
dafc3bd5 482
e3b2e034
TR		 483 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
484 if (err < 0) {
485 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
486 return;
487 }
488
489 r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
68706337
RM		 490
491 /* fglrx duplicates INFOFRAME_CONTROL0 & INFOFRAME_CONTROL1 ops here */
492
493 WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset,
494 ~(HDMI0_GENERIC0_SEND |
495 HDMI0_GENERIC0_CONT |
496 HDMI0_GENERIC0_UPDATE |
497 HDMI0_GENERIC1_SEND |
498 HDMI0_GENERIC1_CONT |
499 HDMI0_GENERIC0_LINE_MASK |
500 HDMI0_GENERIC1_LINE_MASK));
501
1c3439f2
RM		 502 r600_hdmi_update_ACR(encoder, mode->clock);
503
68706337
RM		 504 WREG32_P(HDMI0_60958_0 + offset,
505 HDMI0_60958_CS_CHANNEL_NUMBER_L(1),
506 ~(HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK |
507 HDMI0_60958_CS_CLOCK_ACCURACY_MASK));
508
509 WREG32_P(HDMI0_60958_1 + offset,
510 HDMI0_60958_CS_CHANNEL_NUMBER_R(2),
511 ~HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK);
512
25985edc 513 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
c6543a6e
RM		 514 WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
515 WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
516 WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
517 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
dafc3bd5 518
832eafaf 519 /* enable audio after to setting up hw */
8bf59820 520 radeon_audio_enable(rdev, dig->afmt->pin, 0xf);
dafc3bd5
CK		 521}
522
8e4d9f81
RM		 523/**
524 * r600_hdmi_update_audio_settings - Update audio infoframe
525 *
526 * @encoder: drm encoder
527 *
528 * Gets info about current audio stream and updates audio infoframe.
dafc3bd5 529 */
58bd0863 530void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
dafc3bd5
CK		 531{
532 struct drm_device *dev = encoder->dev;
533 struct radeon_device *rdev = dev->dev_private;
cfcbd6d3
RM		 534 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
535 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
b530602f 536 struct r600_audio_pin audio = r600_audio_status(rdev);
e3b2e034
TR		 537 uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
538 struct hdmi_audio_infoframe frame;
cfcbd6d3 539 uint32_t offset;
8e4d9f81 540 uint32_t value;
e3b2e034 541 ssize_t err;
dafc3bd5 542
cfcbd6d3 543 if (!dig->afmt || !dig->afmt->enabled)
dafc3bd5 544 return;
cfcbd6d3 545 offset = dig->afmt->offset;
dafc3bd5
CK		 546
547 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
548 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
3299de95 549 audio.channels, audio.rate, audio.bits_per_sample);
dafc3bd5 550 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
3299de95 551 (int)audio.status_bits, (int)audio.category_code);
dafc3bd5 552
e3b2e034
TR		 553 err = hdmi_audio_infoframe_init(&frame);
554 if (err < 0) {
555 DRM_ERROR("failed to setup audio infoframe\n");
556 return;
557 }
558
559 frame.channels = audio.channels;
560
561 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
562 if (err < 0) {
563 DRM_ERROR("failed to pack audio infoframe\n");
564 return;
565 }
dafc3bd5 566
8e4d9f81
RM		 567 value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset);
568 if (value & HDMI0_AUDIO_TEST_EN)
569 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
570 value & ~HDMI0_AUDIO_TEST_EN);
571
572 WREG32_OR(HDMI0_CONTROL + offset,
573 HDMI0_ERROR_ACK);
574
575 WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset,
576 ~HDMI0_AUDIO_INFO_SOURCE);
577
e3b2e034 578 r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer));
8e4d9f81
RM		 579
580 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
581 HDMI0_AUDIO_INFO_CONT |
582 HDMI0_AUDIO_INFO_UPDATE);
dafc3bd5
CK		 583}
584
dafc3bd5 585/*
2cd6218c 586 * enable the HDMI engine
dafc3bd5 587 */
a973bea1 588void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
dafc3bd5 589{
2cd6218c
RM		 590 struct drm_device *dev = encoder->dev;
591 struct radeon_device *rdev = dev->dev_private;
dafc3bd5 592 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
cfcbd6d3 593 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
a973bea1 594 u32 hdmi = HDMI0_ERROR_ACK;
16823d16 595
c2b4cacf
AD		 596 if (!dig || !dig->afmt)
597 return;
598
cfcbd6d3 599 /* Silent, r600_hdmi_enable will raise WARN for us */
a973bea1
AD		 600 if (enable && dig->afmt->enabled)
601 return;
602 if (!enable && !dig->afmt->enabled)
cfcbd6d3 603 return;
64fb4fb0 604
4adb34ef 605 if (!enable && dig->afmt->pin) {
8bf59820 606 radeon_audio_enable(rdev, dig->afmt->pin, 0);
4adb34ef
AD		 607 dig->afmt->pin = NULL;
608 }
609
64fb4fb0 610 /* Older chipsets require setting HDMI and routing manually */
a973bea1
AD		 611 if (!ASIC_IS_DCE3(rdev)) {
612 if (enable)
613 hdmi |= HDMI0_ENABLE;
5715f67c
RM		 614 switch (radeon_encoder->encoder_id) {
615 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
a973bea1
AD		 616 if (enable) {
617 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
618 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
619 } else {
620 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
621 }
5715f67c
RM		 622 break;
623 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
a973bea1
AD		 624 if (enable) {
625 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
626 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
627 } else {
628 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
629 }
64fb4fb0
RM		 630 break;
631 case ENCODER_OBJECT_ID_INTERNAL_DDI:
a973bea1
AD		 632 if (enable) {
633 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
634 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
635 } else {
636 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
637 }
64fb4fb0
RM		 638 break;
639 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
a973bea1
AD		 640 if (enable)
641 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
5715f67c
RM		 642 break;
643 default:
64fb4fb0
RM		 644 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
645 radeon_encoder->encoder_id);
5715f67c
RM		 646 break;
647 }
a973bea1 648 WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);
5715f67c 649 }
2cd6218c 650
f122c610 651 if (rdev->irq.installed) {
f2594933 652 /* if irq is available use it */
9054ae1c 653 /* XXX: shouldn't need this on any asics. Double check DCE2/3 */
a973bea1 654 if (enable)
9054ae1c 655 radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
a973bea1
AD		 656 else
657 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
f2594933 658 }
58bd0863 659
a973bea1 660 dig->afmt->enabled = enable;
cfcbd6d3 661
a973bea1
AD		 662 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
663 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
2cd6218c 664}
dafc3bd5 665
Linux kernel - Deliverables
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