[deliverable/linux.git] / drivers / gpu / drm / radeon / r600_hdmi.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Christian König.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Christian König
 */
#include "drmP.h"
#include "radeon_drm.h"
#include "radeon.h"
#include "radeon_asic.h"
#include "atom.h"

/*
 * HDMI color format
 */
enum r600_hdmi_color_format {
	RGB = 0,
	YCC_422 = 1,
	YCC_444 = 2
};

/*
 * IEC60958 status bits
 */
enum r600_hdmi_iec_status_bits {
	AUDIO_STATUS_DIG_ENABLE   = 0x01,
	AUDIO_STATUS_V            = 0x02,
	AUDIO_STATUS_VCFG         = 0x04,
	AUDIO_STATUS_EMPHASIS     = 0x08,
	AUDIO_STATUS_COPYRIGHT    = 0x10,
	AUDIO_STATUS_NONAUDIO     = 0x20,
	AUDIO_STATUS_PROFESSIONAL = 0x40,
	AUDIO_STATUS_LEVEL        = 0x80
};

struct {
	uint32_t Clock;

	int N_32kHz;
	int CTS_32kHz;

	int N_44_1kHz;
	int CTS_44_1kHz;

	int N_48kHz;
	int CTS_48kHz;

} r600_hdmi_ACR[] = {
    /*	     32kHz	  44.1kHz	48kHz    */
    /* Clock      N     CTS      N     CTS      N     CTS */
    {  25174,  4576,  28125,  7007,  31250,  6864,  28125 }, /*  25,20/1.001 MHz */
    {  25200,  4096,  25200,  6272,  28000,  6144,  25200 }, /*  25.20       MHz */
    {  27000,  4096,  27000,  6272,  30000,  6144,  27000 }, /*  27.00       MHz */
    {  27027,  4096,  27027,  6272,  30030,  6144,  27027 }, /*  27.00*1.001 MHz */
    {  54000,  4096,  54000,  6272,  60000,  6144,  54000 }, /*  54.00       MHz */
    {  54054,  4096,  54054,  6272,  60060,  6144,  54054 }, /*  54.00*1.001 MHz */
    {  74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /*  74.25/1.001 MHz */
    {  74250,  4096,  74250,  6272,  82500,  6144,  74250 }, /*  74.25       MHz */
    { 148351, 11648, 421875,  8918, 234375,  5824, 140625 }, /* 148.50/1.001 MHz */
    { 148500,  4096, 148500,  6272, 165000,  6144, 148500 }, /* 148.50       MHz */
    {      0,  4096,      0,  6272,      0,  6144,      0 }  /* Other */
};

/*
 * calculate CTS value if it's not found in the table
 */
static void r600_hdmi_calc_CTS(uint32_t clock, int *CTS, int N, int freq)
{
	if (*CTS == 0)
		*CTS = clock * N / (128 * freq) * 1000;
	DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n",
		  N, *CTS, freq);
}

/*
 * update the N and CTS parameters for a given pixel clock rate
 */
static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
	int CTS;
	int N;
	int i;

	for (i = 0; r600_hdmi_ACR[i].Clock != clock && r600_hdmi_ACR[i].Clock != 0; i++);

	CTS = r600_hdmi_ACR[i].CTS_32kHz;
	N = r600_hdmi_ACR[i].N_32kHz;
	r600_hdmi_calc_CTS(clock, &CTS, N, 32000);
	WREG32(offset+R600_HDMI_32kHz_CTS, CTS << 12);
	WREG32(offset+R600_HDMI_32kHz_N, N);

	CTS = r600_hdmi_ACR[i].CTS_44_1kHz;
	N = r600_hdmi_ACR[i].N_44_1kHz;
	r600_hdmi_calc_CTS(clock, &CTS, N, 44100);
	WREG32(offset+R600_HDMI_44_1kHz_CTS, CTS << 12);
	WREG32(offset+R600_HDMI_44_1kHz_N, N);

	CTS = r600_hdmi_ACR[i].CTS_48kHz;
	N = r600_hdmi_ACR[i].N_48kHz;
	r600_hdmi_calc_CTS(clock, &CTS, N, 48000);
	WREG32(offset+R600_HDMI_48kHz_CTS, CTS << 12);
	WREG32(offset+R600_HDMI_48kHz_N, N);
}

/*
 * calculate the crc for a given info frame
 */
static void r600_hdmi_infoframe_checksum(uint8_t packetType,
					 uint8_t versionNumber,
					 uint8_t length,
					 uint8_t *frame)
{
	int i;
	frame[0] = packetType + versionNumber + length;
	for (i = 1; i <= length; i++)
		frame[0] += frame[i];
	frame[0] = 0x100 - frame[0];
}

/*
 * build a HDMI Video Info Frame
 */
static void r600_hdmi_videoinfoframe(
	struct drm_encoder *encoder,
	enum r600_hdmi_color_format color_format,
	int active_information_present,
	uint8_t active_format_aspect_ratio,
	uint8_t scan_information,
	uint8_t colorimetry,
	uint8_t ex_colorimetry,
	uint8_t quantization,
	int ITC,
	uint8_t picture_aspect_ratio,
	uint8_t video_format_identification,
	uint8_t pixel_repetition,
	uint8_t non_uniform_picture_scaling,
	uint8_t bar_info_data_valid,
	uint16_t top_bar,
	uint16_t bottom_bar,
	uint16_t left_bar,
	uint16_t right_bar
)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;

	uint8_t frame[14];

	frame[0x0] = 0;
	frame[0x1] =
		(scan_information & 0x3) |
		((bar_info_data_valid & 0x3) << 2) |
		((active_information_present & 0x1) << 4) |
		((color_format & 0x3) << 5);
	frame[0x2] =
		(active_format_aspect_ratio & 0xF) |
		((picture_aspect_ratio & 0x3) << 4) |
		((colorimetry & 0x3) << 6);
	frame[0x3] =
		(non_uniform_picture_scaling & 0x3) |
		((quantization & 0x3) << 2) |
		((ex_colorimetry & 0x7) << 4) |
		((ITC & 0x1) << 7);
	frame[0x4] = (video_format_identification & 0x7F);
	frame[0x5] = (pixel_repetition & 0xF);
	frame[0x6] = (top_bar & 0xFF);
	frame[0x7] = (top_bar >> 8);
	frame[0x8] = (bottom_bar & 0xFF);
	frame[0x9] = (bottom_bar >> 8);
	frame[0xA] = (left_bar & 0xFF);
	frame[0xB] = (left_bar >> 8);
	frame[0xC] = (right_bar & 0xFF);
	frame[0xD] = (right_bar >> 8);

	r600_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame);
	/* Our header values (type, version, length) should be alright, Intel
	 * is using the same. Checksum function also seems to be OK, it works
	 * fine for audio infoframe. However calculated value is always lower
	 * by 2 in comparison to fglrx. It breaks displaying anything in case
	 * of TVs that strictly check the checksum. Hack it manually here to
	 * workaround this issue. */
	frame[0x0] += 2;

	WREG32(offset+R600_HDMI_VIDEOINFOFRAME_0,
		frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
	WREG32(offset+R600_HDMI_VIDEOINFOFRAME_1,
		frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
	WREG32(offset+R600_HDMI_VIDEOINFOFRAME_2,
		frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
	WREG32(offset+R600_HDMI_VIDEOINFOFRAME_3,
		frame[0xC] | (frame[0xD] << 8));
}

/*
 * build a Audio Info Frame
 */
static void r600_hdmi_audioinfoframe(
	struct drm_encoder *encoder,
	uint8_t channel_count,
	uint8_t coding_type,
	uint8_t sample_size,
	uint8_t sample_frequency,
	uint8_t format,
	uint8_t channel_allocation,
	uint8_t level_shift,
	int downmix_inhibit
)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;

	uint8_t frame[11];

	frame[0x0] = 0;
	frame[0x1] = (channel_count & 0x7) | ((coding_type & 0xF) << 4);
	frame[0x2] = (sample_size & 0x3) | ((sample_frequency & 0x7) << 2);
	frame[0x3] = format;
	frame[0x4] = channel_allocation;
	frame[0x5] = ((level_shift & 0xF) << 3) | ((downmix_inhibit & 0x1) << 7);
	frame[0x6] = 0;
	frame[0x7] = 0;
	frame[0x8] = 0;
	frame[0x9] = 0;
	frame[0xA] = 0;

	r600_hdmi_infoframe_checksum(0x84, 0x01, 0x0A, frame);

	WREG32(offset+R600_HDMI_AUDIOINFOFRAME_0,
		frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
	WREG32(offset+R600_HDMI_AUDIOINFOFRAME_1,
		frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
}

/*
 * test if audio buffer is filled enough to start playing
 */
static int r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;

	return (RREG32(offset+R600_HDMI_STATUS) & 0x10) != 0;
}

/*
 * have buffer status changed since last call?
 */
int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
{
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	int status, result;

	if (!radeon_encoder->hdmi_enabled)
		return 0;

	status = r600_hdmi_is_audio_buffer_filled(encoder);
	result = radeon_encoder->hdmi_buffer_status != status;
	radeon_encoder->hdmi_buffer_status = status;

	return result;
}

/*
 * write the audio workaround status to the hardware
 */
void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	uint32_t offset = radeon_encoder->hdmi_offset;

	if (!radeon_encoder->hdmi_enabled)
		return;

	if (!radeon_encoder->hdmi_audio_workaround ||
		r600_hdmi_is_audio_buffer_filled(encoder)) {

		/* disable audio workaround */
		WREG32_P(offset+R600_HDMI_CNTL, 0x00000001, ~0x00001001);

	} else {
		/* enable audio workaround */
		WREG32_P(offset+R600_HDMI_CNTL, 0x00001001, ~0x00001001);
	}
}


/*
 * update the info frames with the data from the current display mode
 */
void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;

	if (ASIC_IS_DCE5(rdev))
		return;

	if (!to_radeon_encoder(encoder)->hdmi_enabled)
		return;

	r600_audio_set_clock(encoder, mode->clock);

	WREG32(offset+R600_HDMI_UNKNOWN_0, 0x1000);
	WREG32(offset+R600_HDMI_UNKNOWN_1, 0x0);
	WREG32(offset+R600_HDMI_UNKNOWN_2, 0x1000);

	r600_hdmi_update_ACR(encoder, mode->clock);

	WREG32(offset+R600_HDMI_VIDEOCNTL, 0x13);

	WREG32(offset+R600_HDMI_VERSION, 0x202);

	r600_hdmi_videoinfoframe(encoder, RGB, 0, 0, 0, 0,
		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);

	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
	WREG32(offset+R600_HDMI_AUDIO_DEBUG_0, 0x00FFFFFF);
	WREG32(offset+R600_HDMI_AUDIO_DEBUG_1, 0x007FFFFF);
	WREG32(offset+R600_HDMI_AUDIO_DEBUG_2, 0x00000001);
	WREG32(offset+R600_HDMI_AUDIO_DEBUG_3, 0x00000001);

	r600_hdmi_audio_workaround(encoder);

	/* audio packets per line, does anyone know how to calc this ? */
	WREG32_P(offset+R600_HDMI_CNTL, 0x00040000, ~0x001F0000);
}

/*
 * update settings with current parameters from audio engine
 */
void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;

	int channels = r600_audio_channels(rdev);
	int rate = r600_audio_rate(rdev);
	int bps = r600_audio_bits_per_sample(rdev);
	uint8_t status_bits = r600_audio_status_bits(rdev);
	uint8_t category_code = r600_audio_category_code(rdev);

	uint32_t iec;

	if (!to_radeon_encoder(encoder)->hdmi_enabled)
		return;

	DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
		 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
		channels, rate, bps);
	DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
		  (int)status_bits, (int)category_code);

	iec = 0;
	if (status_bits & AUDIO_STATUS_PROFESSIONAL)
		iec |= 1 << 0;
	if (status_bits & AUDIO_STATUS_NONAUDIO)
		iec |= 1 << 1;
	if (status_bits & AUDIO_STATUS_COPYRIGHT)
		iec |= 1 << 2;
	if (status_bits & AUDIO_STATUS_EMPHASIS)
		iec |= 1 << 3;

	iec |= category_code << 8;

	switch (rate) {
	case  32000: iec |= 0x3 << 24; break;
	case  44100: iec |= 0x0 << 24; break;
	case  88200: iec |= 0x8 << 24; break;
	case 176400: iec |= 0xc << 24; break;
	case  48000: iec |= 0x2 << 24; break;
	case  96000: iec |= 0xa << 24; break;
	case 192000: iec |= 0xe << 24; break;
	}

	WREG32(offset+R600_HDMI_IEC60958_1, iec);

	iec = 0;
	switch (bps) {
	case 16: iec |= 0x2; break;
	case 20: iec |= 0x3; break;
	case 24: iec |= 0xb; break;
	}
	if (status_bits & AUDIO_STATUS_V)
		iec |= 0x5 << 16;

	WREG32_P(offset+R600_HDMI_IEC60958_2, iec, ~0x5000f);

	/* 0x021 or 0x031 sets the audio frame length */
	WREG32(offset+R600_HDMI_AUDIOCNTL, 0x31);
	r600_hdmi_audioinfoframe(encoder, channels-1, 0, 0, 0, 0, 0, 0, 0);

	r600_hdmi_audio_workaround(encoder);
}

static void r600_hdmi_assign_block(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

	u16 eg_offsets[] = {
		EVERGREEN_CRTC0_REGISTER_OFFSET,
		EVERGREEN_CRTC1_REGISTER_OFFSET,
		EVERGREEN_CRTC2_REGISTER_OFFSET,
		EVERGREEN_CRTC3_REGISTER_OFFSET,
		EVERGREEN_CRTC4_REGISTER_OFFSET,
		EVERGREEN_CRTC5_REGISTER_OFFSET,
	};

	if (!dig) {
		dev_err(rdev->dev, "Enabling HDMI on non-dig encoder\n");
		return;
	}

	if (ASIC_IS_DCE5(rdev)) {
		/* TODO */
	} else if (ASIC_IS_DCE4(rdev)) {
		if (dig->dig_encoder >= ARRAY_SIZE(eg_offsets)) {
			dev_err(rdev->dev, "Enabling HDMI on unknown dig\n");
			return;
		}
		radeon_encoder->hdmi_offset = EVERGREEN_HDMI_BASE +
						eg_offsets[dig->dig_encoder];
	} else if (ASIC_IS_DCE3(rdev)) {
		radeon_encoder->hdmi_offset = dig->dig_encoder ?
			R600_HDMI_BLOCK3 : R600_HDMI_BLOCK1;
	} else if (rdev->family >= CHIP_R600) {
		/* 2 routable blocks, but using dig_encoder should be fine */
		radeon_encoder->hdmi_offset = dig->dig_encoder ?
			R600_HDMI_BLOCK2 : R600_HDMI_BLOCK1;
	} else if (rdev->family == CHIP_RS600 || rdev->family == CHIP_RS690 ||
		   rdev->family == CHIP_RS740) {
		/* Only 1 routable block */
		radeon_encoder->hdmi_offset = R600_HDMI_BLOCK1;
	}
	radeon_encoder->hdmi_enabled = true;
}

/*
 * enable the HDMI engine
 */
void r600_hdmi_enable(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	uint32_t offset;

	if (ASIC_IS_DCE5(rdev))
		return;

	if (!radeon_encoder->hdmi_enabled) {
		r600_hdmi_assign_block(encoder);
		if (!radeon_encoder->hdmi_enabled) {
			dev_warn(rdev->dev, "Could not find HDMI block for "
				"0x%x encoder\n", radeon_encoder->encoder_id);
			return;
		}
	}

	offset = radeon_encoder->hdmi_offset;
	if (ASIC_IS_DCE5(rdev)) {
		/* TODO */
	} else if (ASIC_IS_DCE4(rdev)) {
		WREG32_P(radeon_encoder->hdmi_offset + EVERGREEN_AUDIO_PACKET_CNTL, 0x1, ~0x1);
	} else if (ASIC_IS_DCE32(rdev)) {
		WREG32_P(radeon_encoder->hdmi_offset + R600_HDMI_AUDIO_PACKET_CNTL, 0x1, ~0x1);
	} else if (ASIC_IS_DCE3(rdev)) {
		/* TODO */
	} else if (rdev->family >= CHIP_R600) {
		switch (radeon_encoder->encoder_id) {
		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
			WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN,
				 ~AVIVO_TMDSA_CNTL_HDMI_EN);
			WREG32(offset + R600_HDMI_ENABLE, 0x101);
			break;
		case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
			WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN,
				 ~AVIVO_LVTMA_CNTL_HDMI_EN);
			WREG32(offset + R600_HDMI_ENABLE, 0x105);
			break;
		default:
			dev_err(rdev->dev, "Unknown HDMI output type\n");
			break;
		}
	}

	if (rdev->irq.installed) {
		/* if irq is available use it */
		rdev->irq.afmt[offset == R600_HDMI_BLOCK1 ? 0 : 1] = true;
		radeon_irq_set(rdev);
	}

	DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n",
		radeon_encoder->hdmi_offset, radeon_encoder->encoder_id);
}

/*
 * disable the HDMI engine
 */
void r600_hdmi_disable(struct drm_encoder *encoder)
{
	struct drm_device *dev = encoder->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	uint32_t offset;

	if (ASIC_IS_DCE5(rdev))
		return;

	offset = radeon_encoder->hdmi_offset;
	if (!radeon_encoder->hdmi_enabled) {
		dev_err(rdev->dev, "Disabling not enabled HDMI\n");
		return;
	}

	DRM_DEBUG("Disabling HDMI interface @ 0x%04X for encoder 0x%x\n",
		offset, radeon_encoder->encoder_id);

	/* disable irq */
	rdev->irq.afmt[offset == R600_HDMI_BLOCK1 ? 0 : 1] = false;
	radeon_irq_set(rdev);


	if (ASIC_IS_DCE5(rdev)) {
		/* TODO */
	} else if (ASIC_IS_DCE4(rdev)) {
		WREG32_P(radeon_encoder->hdmi_offset + EVERGREEN_AUDIO_PACKET_CNTL, 0, ~0x1);
	} else if (ASIC_IS_DCE32(rdev)) {
		WREG32_P(radeon_encoder->hdmi_offset + R600_HDMI_AUDIO_PACKET_CNTL, 0, ~0x1);
	} else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
		switch (radeon_encoder->encoder_id) {
		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
			WREG32_P(AVIVO_TMDSA_CNTL, 0,
				 ~AVIVO_TMDSA_CNTL_HDMI_EN);
			WREG32(offset + R600_HDMI_ENABLE, 0);
			break;
		case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
			WREG32_P(AVIVO_LVTMA_CNTL, 0,
				 ~AVIVO_LVTMA_CNTL_HDMI_EN);
			WREG32(offset + R600_HDMI_ENABLE, 0);
			break;
		default:
			dev_err(rdev->dev, "Unknown HDMI output type\n");
			break;
		}
	}

	radeon_encoder->hdmi_enabled = false;
	radeon_encoder->hdmi_offset = 0;
}
Commit	Line	Data
dafc3bd5 CK	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Christian König.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Christian König
	25	*/
	26	#include "drmP.h"
	27	#include "radeon_drm.h"
	28	#include "radeon.h"
3574dda4	29	#include "radeon_asic.h"
dafc3bd5 CK	30	#include "atom.h"
	31
	32	/*
	33	* HDMI color format
	34	*/
	35	enum r600_hdmi_color_format {
	36	RGB = 0,
	37	YCC_422 = 1,
	38	YCC_444 = 2
	39	};
	40
	41	/*
	42	* IEC60958 status bits
	43	*/
	44	enum r600_hdmi_iec_status_bits {
	45	AUDIO_STATUS_DIG_ENABLE = 0x01,
3fe373d9 RM	46	AUDIO_STATUS_V = 0x02,
3fe373d9 RM	47	AUDIO_STATUS_VCFG = 0x04,
dafc3bd5 CK	48	AUDIO_STATUS_EMPHASIS = 0x08,
	49	AUDIO_STATUS_COPYRIGHT = 0x10,
	50	AUDIO_STATUS_NONAUDIO = 0x20,
	51	AUDIO_STATUS_PROFESSIONAL = 0x40,
3fe373d9	52	AUDIO_STATUS_LEVEL = 0x80
dafc3bd5 CK	53	};
	54
	55	struct {
	56	uint32_t Clock;
	57
	58	int N_32kHz;
	59	int CTS_32kHz;
	60
	61	int N_44_1kHz;
	62	int CTS_44_1kHz;
	63
	64	int N_48kHz;
	65	int CTS_48kHz;
	66
	67	} r600_hdmi_ACR[] = {
	68	/* 32kHz 44.1kHz 48kHz */
	69	/* Clock N CTS N CTS N CTS */
	70	{ 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */
	71	{ 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
	72	{ 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
	73	{ 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.001.001 MHz /
	74	{ 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
	75	{ 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.001.001 MHz /
	76	{ 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */
	77	{ 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
	78	{ 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */
	79	{ 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
	80	{ 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */
	81	};
	82
	83	/*
	84	* calculate CTS value if it's not found in the table
	85	*/
	86	static void r600_hdmi_calc_CTS(uint32_t clock, int *CTS, int N, int freq)
	87	{
	88	if (*CTS == 0)
3fe373d9	89	CTS = clock N / (128 * freq) * 1000;
dafc3bd5 CK	90	DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n",
	91	N, *CTS, freq);
	92	}
	93
	94	/*
	95	* update the N and CTS parameters for a given pixel clock rate
	96	*/
	97	static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
	98	{
	99	struct drm_device *dev = encoder->dev;
	100	struct radeon_device *rdev = dev->dev_private;
	101	uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
	102	int CTS;
	103	int N;
	104	int i;
	105
	106	for (i = 0; r600_hdmi_ACR[i].Clock != clock && r600_hdmi_ACR[i].Clock != 0; i++);
	107
	108	CTS = r600_hdmi_ACR[i].CTS_32kHz;
	109	N = r600_hdmi_ACR[i].N_32kHz;
	110	r600_hdmi_calc_CTS(clock, &CTS, N, 32000);
	111	WREG32(offset+R600_HDMI_32kHz_CTS, CTS << 12);
	112	WREG32(offset+R600_HDMI_32kHz_N, N);
	113
	114	CTS = r600_hdmi_ACR[i].CTS_44_1kHz;
	115	N = r600_hdmi_ACR[i].N_44_1kHz;
	116	r600_hdmi_calc_CTS(clock, &CTS, N, 44100);
	117	WREG32(offset+R600_HDMI_44_1kHz_CTS, CTS << 12);
	118	WREG32(offset+R600_HDMI_44_1kHz_N, N);
	119
	120	CTS = r600_hdmi_ACR[i].CTS_48kHz;
	121	N = r600_hdmi_ACR[i].N_48kHz;
	122	r600_hdmi_calc_CTS(clock, &CTS, N, 48000);
	123	WREG32(offset+R600_HDMI_48kHz_CTS, CTS << 12);
	124	WREG32(offset+R600_HDMI_48kHz_N, N);
	125	}
	126
	127	/*
	128	* calculate the crc for a given info frame
	129	*/
	130	static void r600_hdmi_infoframe_checksum(uint8_t packetType,
	131	uint8_t versionNumber,
	132	uint8_t length,
	133	uint8_t *frame)
	134	{
3fe373d9 RM	135	int i;
	136	frame[0] = packetType + versionNumber + length;
	137	for (i = 1; i <= length; i++)
	138	frame[0] += frame[i];
	139	frame[0] = 0x100 - frame[0];
dafc3bd5 CK	140	}
	141
	142	/*
	143	* build a HDMI Video Info Frame
	144	*/
	145	static void r600_hdmi_videoinfoframe(
	146	struct drm_encoder *encoder,
	147	enum r600_hdmi_color_format color_format,
	148	int active_information_present,
	149	uint8_t active_format_aspect_ratio,
	150	uint8_t scan_information,
	151	uint8_t colorimetry,
	152	uint8_t ex_colorimetry,
	153	uint8_t quantization,
	154	int ITC,
	155	uint8_t picture_aspect_ratio,
	156	uint8_t video_format_identification,
	157	uint8_t pixel_repetition,
	158	uint8_t non_uniform_picture_scaling,
	159	uint8_t bar_info_data_valid,
	160	uint16_t top_bar,
	161	uint16_t bottom_bar,
	162	uint16_t left_bar,
	163	uint16_t right_bar
	164	)
	165	{
	166	struct drm_device *dev = encoder->dev;
	167	struct radeon_device *rdev = dev->dev_private;
	168	uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
	169
	170	uint8_t frame[14];
	171
	172	frame[0x0] = 0;
	173	frame[0x1] =
	174	(scan_information & 0x3) \|
	175	((bar_info_data_valid & 0x3) << 2) \|
	176	((active_information_present & 0x1) << 4) \|
	177	((color_format & 0x3) << 5);
	178	frame[0x2] =
	179	(active_format_aspect_ratio & 0xF) \|
	180	((picture_aspect_ratio & 0x3) << 4) \|
	181	((colorimetry & 0x3) << 6);
	182	frame[0x3] =
	183	(non_uniform_picture_scaling & 0x3) \|
	184	((quantization & 0x3) << 2) \|
	185	((ex_colorimetry & 0x7) << 4) \|
	186	((ITC & 0x1) << 7);
	187	frame[0x4] = (video_format_identification & 0x7F);
	188	frame[0x5] = (pixel_repetition & 0xF);
	189	frame[0x6] = (top_bar & 0xFF);
	190	frame[0x7] = (top_bar >> 8);
	191	frame[0x8] = (bottom_bar & 0xFF);
	192	frame[0x9] = (bottom_bar >> 8);
	193	frame[0xA] = (left_bar & 0xFF);
	194	frame[0xB] = (left_bar >> 8);
	195	frame[0xC] = (right_bar & 0xFF);
	196	frame[0xD] = (right_bar >> 8);
	197
	198	r600_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame);
92db7f6c RM	199	/* Our header values (type, version, length) should be alright, Intel
	200	* is using the same. Checksum function also seems to be OK, it works
	201	* fine for audio infoframe. However calculated value is always lower
	202	* by 2 in comparison to fglrx. It breaks displaying anything in case
	203	* of TVs that strictly check the checksum. Hack it manually here to
	204	* workaround this issue. */
	205	frame[0x0] += 2;
dafc3bd5 CK	206
	207	WREG32(offset+R600_HDMI_VIDEOINFOFRAME_0,
	208	frame[0x0] \| (frame[0x1] << 8) \| (frame[0x2] << 16) \| (frame[0x3] << 24));
	209	WREG32(offset+R600_HDMI_VIDEOINFOFRAME_1,
	210	frame[0x4] \| (frame[0x5] << 8) \| (frame[0x6] << 16) \| (frame[0x7] << 24));
	211	WREG32(offset+R600_HDMI_VIDEOINFOFRAME_2,
	212	frame[0x8] \| (frame[0x9] << 8) \| (frame[0xA] << 16) \| (frame[0xB] << 24));
	213	WREG32(offset+R600_HDMI_VIDEOINFOFRAME_3,
	214	frame[0xC] \| (frame[0xD] << 8));
	215	}
	216
	217	/*
	218	* build a Audio Info Frame
	219	*/
	220	static void r600_hdmi_audioinfoframe(
	221	struct drm_encoder *encoder,
	222	uint8_t channel_count,
	223	uint8_t coding_type,
	224	uint8_t sample_size,
	225	uint8_t sample_frequency,
	226	uint8_t format,
	227	uint8_t channel_allocation,
	228	uint8_t level_shift,
	229	int downmix_inhibit
	230	)
	231	{
	232	struct drm_device *dev = encoder->dev;
	233	struct radeon_device *rdev = dev->dev_private;
	234	uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
	235
	236	uint8_t frame[11];
	237
	238	frame[0x0] = 0;
	239	frame[0x1] = (channel_count & 0x7) \| ((coding_type & 0xF) << 4);
	240	frame[0x2] = (sample_size & 0x3) \| ((sample_frequency & 0x7) << 2);
	241	frame[0x3] = format;
	242	frame[0x4] = channel_allocation;
	243	frame[0x5] = ((level_shift & 0xF) << 3) \| ((downmix_inhibit & 0x1) << 7);
	244	frame[0x6] = 0;
	245	frame[0x7] = 0;
	246	frame[0x8] = 0;
	247	frame[0x9] = 0;
	248	frame[0xA] = 0;
	249
	250	r600_hdmi_infoframe_checksum(0x84, 0x01, 0x0A, frame);
	251
	252	WREG32(offset+R600_HDMI_AUDIOINFOFRAME_0,
	253	frame[0x0] \| (frame[0x1] << 8) \| (frame[0x2] << 16) \| (frame[0x3] << 24));
	254	WREG32(offset+R600_HDMI_AUDIOINFOFRAME_1,
	255	frame[0x4] \| (frame[0x5] << 8) \| (frame[0x6] << 16) \| (frame[0x8] << 24));
	256	}
	257
	258	/*
	259	* test if audio buffer is filled enough to start playing
	260	*/
	261	static int r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
	262	{
	263	struct drm_device *dev = encoder->dev;
	264	struct radeon_device *rdev = dev->dev_private;
	265	uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
	266
	267	return (RREG32(offset+R600_HDMI_STATUS) & 0x10) != 0;
	268	}
	269
270	/*
271	* have buffer status changed since last call?
272	*/
273	int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
274	{
275	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
276	int status, result;
277
af0b5743	278	if (!radeon_encoder->hdmi_enabled)
dafc3bd5 CK	279	return 0;
	280
	281	status = r600_hdmi_is_audio_buffer_filled(encoder);
	282	result = radeon_encoder->hdmi_buffer_status != status;
	283	radeon_encoder->hdmi_buffer_status = status;
	284
	285	return result;
	286	}
	287
	288	/*
	289	* write the audio workaround status to the hardware
	290	*/
	291	void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
	292	{
	293	struct drm_device *dev = encoder->dev;
	294	struct radeon_device *rdev = dev->dev_private;
	295	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	296	uint32_t offset = radeon_encoder->hdmi_offset;
	297
af0b5743	298	if (!radeon_encoder->hdmi_enabled)
dafc3bd5 CK	299	return;
dafc3bd5 CK	300
f2594933 CK	301	if (!radeon_encoder->hdmi_audio_workaround \|\|
f2594933 CK	302	r600_hdmi_is_audio_buffer_filled(encoder)) {
dafc3bd5	303
f2594933 CK	304	/* disable audio workaround */
f2594933 CK	305	WREG32_P(offset+R600_HDMI_CNTL, 0x00000001, ~0x00001001);
dafc3bd5 CK	306
dafc3bd5 CK	307	} else {
f2594933 CK	308	/* enable audio workaround */
f2594933 CK	309	WREG32_P(offset+R600_HDMI_CNTL, 0x00001001, ~0x00001001);
dafc3bd5 CK	310	}
	311	}
	312
	313
	314	/*
	315	* update the info frames with the data from the current display mode
	316	*/
	317	void r600_hdmi_setmode(struct drm_encoder encoder, struct drm_display_mode mode)
	318	{
	319	struct drm_device *dev = encoder->dev;
	320	struct radeon_device *rdev = dev->dev_private;
	321	uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
	322
f83d926a	323	if (ASIC_IS_DCE5(rdev))
16823d16 AD	324	return;
16823d16 AD	325
af0b5743	326	if (!to_radeon_encoder(encoder)->hdmi_enabled)
dafc3bd5 CK	327	return;
	328
	329	r600_audio_set_clock(encoder, mode->clock);
	330
	331	WREG32(offset+R600_HDMI_UNKNOWN_0, 0x1000);
	332	WREG32(offset+R600_HDMI_UNKNOWN_1, 0x0);
	333	WREG32(offset+R600_HDMI_UNKNOWN_2, 0x1000);
	334
	335	r600_hdmi_update_ACR(encoder, mode->clock);
	336
	337	WREG32(offset+R600_HDMI_VIDEOCNTL, 0x13);
	338
	339	WREG32(offset+R600_HDMI_VERSION, 0x202);
	340
	341	r600_hdmi_videoinfoframe(encoder, RGB, 0, 0, 0, 0,
	342	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
	343
25985edc	344	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
dafc3bd5 CK	345	WREG32(offset+R600_HDMI_AUDIO_DEBUG_0, 0x00FFFFFF);
	346	WREG32(offset+R600_HDMI_AUDIO_DEBUG_1, 0x007FFFFF);
	347	WREG32(offset+R600_HDMI_AUDIO_DEBUG_2, 0x00000001);
	348	WREG32(offset+R600_HDMI_AUDIO_DEBUG_3, 0x00000001);
	349
	350	r600_hdmi_audio_workaround(encoder);
	351
	352	/* audio packets per line, does anyone know how to calc this ? */
	353	WREG32_P(offset+R600_HDMI_CNTL, 0x00040000, ~0x001F0000);
dafc3bd5 CK	354	}
	355
	356	/*
	357	* update settings with current parameters from audio engine
	358	*/
58bd0863	359	void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
dafc3bd5 CK	360	{
	361	struct drm_device *dev = encoder->dev;
	362	struct radeon_device *rdev = dev->dev_private;
	363	uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
	364
58bd0863 CK	365	int channels = r600_audio_channels(rdev);
	366	int rate = r600_audio_rate(rdev);
	367	int bps = r600_audio_bits_per_sample(rdev);
	368	uint8_t status_bits = r600_audio_status_bits(rdev);
	369	uint8_t category_code = r600_audio_category_code(rdev);
	370
dafc3bd5 CK	371	uint32_t iec;
dafc3bd5 CK	372
af0b5743	373	if (!to_radeon_encoder(encoder)->hdmi_enabled)
dafc3bd5 CK	374	return;
	375
	376	DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
	377	r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
	378	channels, rate, bps);
	379	DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
	380	(int)status_bits, (int)category_code);
	381
	382	iec = 0;
	383	if (status_bits & AUDIO_STATUS_PROFESSIONAL)
	384	iec \|= 1 << 0;
	385	if (status_bits & AUDIO_STATUS_NONAUDIO)
	386	iec \|= 1 << 1;
	387	if (status_bits & AUDIO_STATUS_COPYRIGHT)
	388	iec \|= 1 << 2;
	389	if (status_bits & AUDIO_STATUS_EMPHASIS)
	390	iec \|= 1 << 3;
	391
	392	iec \|= category_code << 8;
	393
	394	switch (rate) {
	395	case 32000: iec \|= 0x3 << 24; break;
	396	case 44100: iec \|= 0x0 << 24; break;
	397	case 88200: iec \|= 0x8 << 24; break;
	398	case 176400: iec \|= 0xc << 24; break;
	399	case 48000: iec \|= 0x2 << 24; break;
	400	case 96000: iec \|= 0xa << 24; break;
	401	case 192000: iec \|= 0xe << 24; break;
	402	}
	403
	404	WREG32(offset+R600_HDMI_IEC60958_1, iec);
	405
	406	iec = 0;
	407	switch (bps) {
	408	case 16: iec \|= 0x2; break;
	409	case 20: iec \|= 0x3; break;
	410	case 24: iec \|= 0xb; break;
	411	}
	412	if (status_bits & AUDIO_STATUS_V)
	413	iec \|= 0x5 << 16;
	414
	415	WREG32_P(offset+R600_HDMI_IEC60958_2, iec, ~0x5000f);
	416
	417	/* 0x021 or 0x031 sets the audio frame length */
	418	WREG32(offset+R600_HDMI_AUDIOCNTL, 0x31);
	419	r600_hdmi_audioinfoframe(encoder, channels-1, 0, 0, 0, 0, 0, 0, 0);
	420
	421	r600_hdmi_audio_workaround(encoder);
dafc3bd5 CK	422	}
dafc3bd5 CK	423
2cd6218c	424	static void r600_hdmi_assign_block(struct drm_encoder *encoder)
dafc3bd5 CK	425	{
	426	struct drm_device *dev = encoder->dev;
	427	struct radeon_device *rdev = dev->dev_private;
	428	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2cd6218c	429	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
dafc3bd5	430
f83d926a RM	431	u16 eg_offsets[] = {
	432	EVERGREEN_CRTC0_REGISTER_OFFSET,
	433	EVERGREEN_CRTC1_REGISTER_OFFSET,
	434	EVERGREEN_CRTC2_REGISTER_OFFSET,
	435	EVERGREEN_CRTC3_REGISTER_OFFSET,
	436	EVERGREEN_CRTC4_REGISTER_OFFSET,
	437	EVERGREEN_CRTC5_REGISTER_OFFSET,
	438	};
	439
2cd6218c RM	440	if (!dig) {
2cd6218c RM	441	dev_err(rdev->dev, "Enabling HDMI on non-dig encoder\n");
dafc3bd5	442	return;
2cd6218c	443	}
dafc3bd5	444
ebcb796f RM	445	if (ASIC_IS_DCE5(rdev)) {
	446	/* TODO */
	447	} else if (ASIC_IS_DCE4(rdev)) {
f83d926a RM	448	if (dig->dig_encoder >= ARRAY_SIZE(eg_offsets)) {
	449	dev_err(rdev->dev, "Enabling HDMI on unknown dig\n");
	450	return;
	451	}
	452	radeon_encoder->hdmi_offset = EVERGREEN_HDMI_BASE +
	453	eg_offsets[dig->dig_encoder];
2cd6218c RM	454	} else if (ASIC_IS_DCE3(rdev)) {
	455	radeon_encoder->hdmi_offset = dig->dig_encoder ?
	456	R600_HDMI_BLOCK3 : R600_HDMI_BLOCK1;
816ce437 RM	457	} else if (rdev->family >= CHIP_R600) {
	458	/* 2 routable blocks, but using dig_encoder should be fine */
	459	radeon_encoder->hdmi_offset = dig->dig_encoder ?
	460	R600_HDMI_BLOCK2 : R600_HDMI_BLOCK1;
	461	} else if (rdev->family == CHIP_RS600 \|\| rdev->family == CHIP_RS690 \|\|
	462	rdev->family == CHIP_RS740) {
	463	/* Only 1 routable block */
	464	radeon_encoder->hdmi_offset = R600_HDMI_BLOCK1;
dafc3bd5	465	}
af0b5743	466	radeon_encoder->hdmi_enabled = true;
dafc3bd5 CK	467	}
	468
	469	/*
2cd6218c	470	* enable the HDMI engine
dafc3bd5	471	*/
2cd6218c	472	void r600_hdmi_enable(struct drm_encoder *encoder)
dafc3bd5	473	{
2cd6218c RM	474	struct drm_device *dev = encoder->dev;
2cd6218c RM	475	struct radeon_device *rdev = dev->dev_private;
dafc3bd5	476	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
f2594933	477	uint32_t offset;
dafc3bd5	478
f83d926a	479	if (ASIC_IS_DCE5(rdev))
16823d16 AD	480	return;
16823d16 AD	481
af0b5743	482	if (!radeon_encoder->hdmi_enabled) {
2cd6218c	483	r600_hdmi_assign_block(encoder);
af0b5743	484	if (!radeon_encoder->hdmi_enabled) {
2cd6218c RM	485	dev_warn(rdev->dev, "Could not find HDMI block for "
	486	"0x%x encoder\n", radeon_encoder->encoder_id);
	487	return;
dafc3bd5	488	}
2cd6218c	489	}
dafc3bd5	490
f2594933	491	offset = radeon_encoder->hdmi_offset;
ebcb796f RM	492	if (ASIC_IS_DCE5(rdev)) {
	493	/* TODO */
	494	} else if (ASIC_IS_DCE4(rdev)) {
a010fb1a	495	WREG32_P(radeon_encoder->hdmi_offset + EVERGREEN_AUDIO_PACKET_CNTL, 0x1, ~0x1);
ebcb796f	496	} else if (ASIC_IS_DCE32(rdev)) {
a010fb1a	497	WREG32_P(radeon_encoder->hdmi_offset + R600_HDMI_AUDIO_PACKET_CNTL, 0x1, ~0x1);
ebcb796f RM	498	} else if (ASIC_IS_DCE3(rdev)) {
	499	/* TODO */
	500	} else if (rdev->family >= CHIP_R600) {
5715f67c RM	501	switch (radeon_encoder->encoder_id) {
5715f67c RM	502	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
93a4ed87 RM	503	WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN,
93a4ed87 RM	504	~AVIVO_TMDSA_CNTL_HDMI_EN);
5715f67c RM	505	WREG32(offset + R600_HDMI_ENABLE, 0x101);
	506	break;
	507	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
93a4ed87 RM	508	WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN,
93a4ed87 RM	509	~AVIVO_LVTMA_CNTL_HDMI_EN);
5715f67c RM	510	WREG32(offset + R600_HDMI_ENABLE, 0x105);
	511	break;
	512	default:
	513	dev_err(rdev->dev, "Unknown HDMI output type\n");
	514	break;
	515	}
	516	}
2cd6218c	517
f122c610	518	if (rdev->irq.installed) {
f2594933	519	/* if irq is available use it */
f122c610	520	rdev->irq.afmt[offset == R600_HDMI_BLOCK1 ? 0 : 1] = true;
f2594933	521	radeon_irq_set(rdev);
f2594933	522	}
58bd0863	523
2cd6218c RM	524	DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n",
	525	radeon_encoder->hdmi_offset, radeon_encoder->encoder_id);
	526	}
dafc3bd5	527
2cd6218c RM	528	/*
	529	* disable the HDMI engine
	530	*/
	531	void r600_hdmi_disable(struct drm_encoder *encoder)
	532	{
	533	struct drm_device *dev = encoder->dev;
	534	struct radeon_device *rdev = dev->dev_private;
	535	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
66989987	536	uint32_t offset;
2cd6218c	537
f83d926a	538	if (ASIC_IS_DCE5(rdev))
16823d16 AD	539	return;
16823d16 AD	540
f2594933	541	offset = radeon_encoder->hdmi_offset;
af0b5743	542	if (!radeon_encoder->hdmi_enabled) {
2cd6218c RM	543	dev_err(rdev->dev, "Disabling not enabled HDMI\n");
2cd6218c RM	544	return;
dafc3bd5 CK	545	}
dafc3bd5 CK	546
2cd6218c	547	DRM_DEBUG("Disabling HDMI interface @ 0x%04X for encoder 0x%x\n",
f2594933 CK	548	offset, radeon_encoder->encoder_id);
	549
	550	/* disable irq */
f122c610	551	rdev->irq.afmt[offset == R600_HDMI_BLOCK1 ? 0 : 1] = false;
f2594933 CK	552	radeon_irq_set(rdev);
f2594933 CK	553
2cd6218c	554
f83d926a RM	555	if (ASIC_IS_DCE5(rdev)) {
	556	/* TODO */
	557	} else if (ASIC_IS_DCE4(rdev)) {
a010fb1a	558	WREG32_P(radeon_encoder->hdmi_offset + EVERGREEN_AUDIO_PACKET_CNTL, 0, ~0x1);
f83d926a	559	} else if (ASIC_IS_DCE32(rdev)) {
a010fb1a	560	WREG32_P(radeon_encoder->hdmi_offset + R600_HDMI_AUDIO_PACKET_CNTL, 0, ~0x1);
5715f67c	561	} else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
5715f67c RM	562	switch (radeon_encoder->encoder_id) {
5715f67c RM	563	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
93a4ed87 RM	564	WREG32_P(AVIVO_TMDSA_CNTL, 0,
93a4ed87 RM	565	~AVIVO_TMDSA_CNTL_HDMI_EN);
5715f67c RM	566	WREG32(offset + R600_HDMI_ENABLE, 0);
	567	break;
	568	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
93a4ed87 RM	569	WREG32_P(AVIVO_LVTMA_CNTL, 0,
93a4ed87 RM	570	~AVIVO_LVTMA_CNTL_HDMI_EN);
5715f67c RM	571	WREG32(offset + R600_HDMI_ENABLE, 0);
	572	break;
	573	default:
	574	dev_err(rdev->dev, "Unknown HDMI output type\n");
	575	break;
	576	}
	577	}
dafc3bd5	578
af0b5743	579	radeon_encoder->hdmi_enabled = false;
2cd6218c	580	radeon_encoder->hdmi_offset = 0;
dafc3bd5	581	}