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3ce0a23d JG |
1 | /* |
2 | * Copyright 2009 Advanced Micro Devices, Inc. | |
3 | * Copyright 2009 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice shall be included in | |
13 | * all copies or substantial portions of the Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
21 | * OTHER DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: Dave Airlie | |
24 | * Alex Deucher | |
25 | * Jerome Glisse | |
26 | */ | |
27 | #ifndef R600D_H | |
28 | #define R600D_H | |
29 | ||
30 | #define CP_PACKET2 0x80000000 | |
31 | #define PACKET2_PAD_SHIFT 0 | |
32 | #define PACKET2_PAD_MASK (0x3fffffff << 0) | |
33 | ||
34 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) | |
35 | ||
36 | #define R6XX_MAX_SH_GPRS 256 | |
37 | #define R6XX_MAX_TEMP_GPRS 16 | |
38 | #define R6XX_MAX_SH_THREADS 256 | |
39 | #define R6XX_MAX_SH_STACK_ENTRIES 4096 | |
40 | #define R6XX_MAX_BACKENDS 8 | |
41 | #define R6XX_MAX_BACKENDS_MASK 0xff | |
42 | #define R6XX_MAX_SIMDS 8 | |
43 | #define R6XX_MAX_SIMDS_MASK 0xff | |
44 | #define R6XX_MAX_PIPES 8 | |
45 | #define R6XX_MAX_PIPES_MASK 0xff | |
46 | ||
47 | /* PTE flags */ | |
48 | #define PTE_VALID (1 << 0) | |
49 | #define PTE_SYSTEM (1 << 1) | |
50 | #define PTE_SNOOPED (1 << 2) | |
51 | #define PTE_READABLE (1 << 5) | |
52 | #define PTE_WRITEABLE (1 << 6) | |
53 | ||
16790569 AD |
54 | /* tiling bits */ |
55 | #define ARRAY_LINEAR_GENERAL 0x00000000 | |
56 | #define ARRAY_LINEAR_ALIGNED 0x00000001 | |
57 | #define ARRAY_1D_TILED_THIN1 0x00000002 | |
58 | #define ARRAY_2D_TILED_THIN1 0x00000004 | |
59 | ||
3ce0a23d JG |
60 | /* Registers */ |
61 | #define ARB_POP 0x2418 | |
62 | #define ENABLE_TC128 (1 << 30) | |
63 | #define ARB_GDEC_RD_CNTL 0x246C | |
64 | ||
65 | #define CC_GC_SHADER_PIPE_CONFIG 0x8950 | |
66 | #define CC_RB_BACKEND_DISABLE 0x98F4 | |
67 | #define BACKEND_DISABLE(x) ((x) << 16) | |
68 | ||
523885de MO |
69 | #define R_028808_CB_COLOR_CONTROL 0x28808 |
70 | #define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4) | |
71 | #define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7) | |
72 | #define C_028808_SPECIAL_OP 0xFFFFFF8F | |
73 | #define V_028808_SPECIAL_NORMAL 0x00 | |
74 | #define V_028808_SPECIAL_DISABLE 0x01 | |
75 | #define V_028808_SPECIAL_RESOLVE_BOX 0x07 | |
76 | ||
3ce0a23d JG |
77 | #define CB_COLOR0_BASE 0x28040 |
78 | #define CB_COLOR1_BASE 0x28044 | |
79 | #define CB_COLOR2_BASE 0x28048 | |
80 | #define CB_COLOR3_BASE 0x2804C | |
81 | #define CB_COLOR4_BASE 0x28050 | |
82 | #define CB_COLOR5_BASE 0x28054 | |
83 | #define CB_COLOR6_BASE 0x28058 | |
84 | #define CB_COLOR7_BASE 0x2805C | |
85 | #define CB_COLOR7_FRAG 0x280FC | |
86 | ||
87 | #define CB_COLOR0_SIZE 0x28060 | |
88 | #define CB_COLOR0_VIEW 0x28080 | |
285484e2 JG |
89 | #define R_028080_CB_COLOR0_VIEW 0x028080 |
90 | #define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0) | |
91 | #define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF) | |
92 | #define C_028080_SLICE_START 0xFFFFF800 | |
93 | #define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13) | |
94 | #define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF) | |
95 | #define C_028080_SLICE_MAX 0xFF001FFF | |
96 | #define R_028084_CB_COLOR1_VIEW 0x028084 | |
97 | #define R_028088_CB_COLOR2_VIEW 0x028088 | |
98 | #define R_02808C_CB_COLOR3_VIEW 0x02808C | |
99 | #define R_028090_CB_COLOR4_VIEW 0x028090 | |
100 | #define R_028094_CB_COLOR5_VIEW 0x028094 | |
101 | #define R_028098_CB_COLOR6_VIEW 0x028098 | |
102 | #define R_02809C_CB_COLOR7_VIEW 0x02809C | |
c116cc94 MO |
103 | #define R_028100_CB_COLOR0_MASK 0x028100 |
104 | #define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0) | |
105 | #define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF) | |
106 | #define C_028100_CMASK_BLOCK_MAX 0xFFFFF000 | |
107 | #define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12) | |
108 | #define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF) | |
109 | #define C_028100_FMASK_TILE_MAX 0x00000FFF | |
110 | #define R_028104_CB_COLOR1_MASK 0x028104 | |
111 | #define R_028108_CB_COLOR2_MASK 0x028108 | |
112 | #define R_02810C_CB_COLOR3_MASK 0x02810C | |
113 | #define R_028110_CB_COLOR4_MASK 0x028110 | |
114 | #define R_028114_CB_COLOR5_MASK 0x028114 | |
115 | #define R_028118_CB_COLOR6_MASK 0x028118 | |
116 | #define R_02811C_CB_COLOR7_MASK 0x02811C | |
3ce0a23d | 117 | #define CB_COLOR0_INFO 0x280a0 |
3a38612e IH |
118 | # define CB_FORMAT(x) ((x) << 2) |
119 | # define CB_ARRAY_MODE(x) ((x) << 8) | |
120 | # define CB_SOURCE_FORMAT(x) ((x) << 27) | |
121 | # define CB_SF_EXPORT_FULL 0 | |
122 | # define CB_SF_EXPORT_NORM 1 | |
3ce0a23d JG |
123 | #define CB_COLOR0_TILE 0x280c0 |
124 | #define CB_COLOR0_FRAG 0x280e0 | |
125 | #define CB_COLOR0_MASK 0x28100 | |
126 | ||
5f77df36 AD |
127 | #define SQ_ALU_CONST_CACHE_PS_0 0x28940 |
128 | #define SQ_ALU_CONST_CACHE_PS_1 0x28944 | |
129 | #define SQ_ALU_CONST_CACHE_PS_2 0x28948 | |
130 | #define SQ_ALU_CONST_CACHE_PS_3 0x2894c | |
131 | #define SQ_ALU_CONST_CACHE_PS_4 0x28950 | |
132 | #define SQ_ALU_CONST_CACHE_PS_5 0x28954 | |
133 | #define SQ_ALU_CONST_CACHE_PS_6 0x28958 | |
134 | #define SQ_ALU_CONST_CACHE_PS_7 0x2895c | |
135 | #define SQ_ALU_CONST_CACHE_PS_8 0x28960 | |
136 | #define SQ_ALU_CONST_CACHE_PS_9 0x28964 | |
137 | #define SQ_ALU_CONST_CACHE_PS_10 0x28968 | |
138 | #define SQ_ALU_CONST_CACHE_PS_11 0x2896c | |
139 | #define SQ_ALU_CONST_CACHE_PS_12 0x28970 | |
140 | #define SQ_ALU_CONST_CACHE_PS_13 0x28974 | |
141 | #define SQ_ALU_CONST_CACHE_PS_14 0x28978 | |
142 | #define SQ_ALU_CONST_CACHE_PS_15 0x2897c | |
143 | #define SQ_ALU_CONST_CACHE_VS_0 0x28980 | |
144 | #define SQ_ALU_CONST_CACHE_VS_1 0x28984 | |
145 | #define SQ_ALU_CONST_CACHE_VS_2 0x28988 | |
146 | #define SQ_ALU_CONST_CACHE_VS_3 0x2898c | |
147 | #define SQ_ALU_CONST_CACHE_VS_4 0x28990 | |
148 | #define SQ_ALU_CONST_CACHE_VS_5 0x28994 | |
149 | #define SQ_ALU_CONST_CACHE_VS_6 0x28998 | |
150 | #define SQ_ALU_CONST_CACHE_VS_7 0x2899c | |
151 | #define SQ_ALU_CONST_CACHE_VS_8 0x289a0 | |
152 | #define SQ_ALU_CONST_CACHE_VS_9 0x289a4 | |
153 | #define SQ_ALU_CONST_CACHE_VS_10 0x289a8 | |
154 | #define SQ_ALU_CONST_CACHE_VS_11 0x289ac | |
155 | #define SQ_ALU_CONST_CACHE_VS_12 0x289b0 | |
156 | #define SQ_ALU_CONST_CACHE_VS_13 0x289b4 | |
157 | #define SQ_ALU_CONST_CACHE_VS_14 0x289b8 | |
158 | #define SQ_ALU_CONST_CACHE_VS_15 0x289bc | |
159 | #define SQ_ALU_CONST_CACHE_GS_0 0x289c0 | |
160 | #define SQ_ALU_CONST_CACHE_GS_1 0x289c4 | |
161 | #define SQ_ALU_CONST_CACHE_GS_2 0x289c8 | |
162 | #define SQ_ALU_CONST_CACHE_GS_3 0x289cc | |
163 | #define SQ_ALU_CONST_CACHE_GS_4 0x289d0 | |
164 | #define SQ_ALU_CONST_CACHE_GS_5 0x289d4 | |
165 | #define SQ_ALU_CONST_CACHE_GS_6 0x289d8 | |
166 | #define SQ_ALU_CONST_CACHE_GS_7 0x289dc | |
167 | #define SQ_ALU_CONST_CACHE_GS_8 0x289e0 | |
168 | #define SQ_ALU_CONST_CACHE_GS_9 0x289e4 | |
169 | #define SQ_ALU_CONST_CACHE_GS_10 0x289e8 | |
170 | #define SQ_ALU_CONST_CACHE_GS_11 0x289ec | |
171 | #define SQ_ALU_CONST_CACHE_GS_12 0x289f0 | |
172 | #define SQ_ALU_CONST_CACHE_GS_13 0x289f4 | |
173 | #define SQ_ALU_CONST_CACHE_GS_14 0x289f8 | |
174 | #define SQ_ALU_CONST_CACHE_GS_15 0x289fc | |
175 | ||
3ce0a23d | 176 | #define CONFIG_MEMSIZE 0x5428 |
28d52043 | 177 | #define CONFIG_CNTL 0x5424 |
440a7cd8 JG |
178 | #define CP_STALLED_STAT1 0x8674 |
179 | #define CP_STALLED_STAT2 0x8678 | |
180 | #define CP_BUSY_STAT 0x867C | |
3ce0a23d JG |
181 | #define CP_STAT 0x8680 |
182 | #define CP_COHER_BASE 0x85F8 | |
183 | #define CP_DEBUG 0xC1FC | |
184 | #define R_0086D8_CP_ME_CNTL 0x86D8 | |
d3cb781e AD |
185 | #define S_0086D8_CP_PFP_HALT(x) (((x) & 1)<<26) |
186 | #define C_0086D8_CP_PFP_HALT(x) ((x) & 0xFBFFFFFF) | |
3ce0a23d JG |
187 | #define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28) |
188 | #define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF) | |
189 | #define CP_ME_RAM_DATA 0xC160 | |
190 | #define CP_ME_RAM_RADDR 0xC158 | |
191 | #define CP_ME_RAM_WADDR 0xC15C | |
192 | #define CP_MEQ_THRESHOLDS 0x8764 | |
193 | #define MEQ_END(x) ((x) << 16) | |
194 | #define ROQ_END(x) ((x) << 24) | |
195 | #define CP_PERFMON_CNTL 0x87FC | |
196 | #define CP_PFP_UCODE_ADDR 0xC150 | |
197 | #define CP_PFP_UCODE_DATA 0xC154 | |
198 | #define CP_QUEUE_THRESHOLDS 0x8760 | |
199 | #define ROQ_IB1_START(x) ((x) << 0) | |
200 | #define ROQ_IB2_START(x) ((x) << 8) | |
201 | #define CP_RB_BASE 0xC100 | |
202 | #define CP_RB_CNTL 0xC104 | |
4eace7fd CC |
203 | #define RB_BUFSZ(x) ((x) << 0) |
204 | #define RB_BLKSZ(x) ((x) << 8) | |
205 | #define RB_NO_UPDATE (1 << 27) | |
206 | #define RB_RPTR_WR_ENA (1 << 31) | |
3ce0a23d JG |
207 | #define BUF_SWAP_32BIT (2 << 16) |
208 | #define CP_RB_RPTR 0x8700 | |
209 | #define CP_RB_RPTR_ADDR 0xC10C | |
4eace7fd | 210 | #define RB_RPTR_SWAP(x) ((x) << 0) |
3ce0a23d JG |
211 | #define CP_RB_RPTR_ADDR_HI 0xC110 |
212 | #define CP_RB_RPTR_WR 0xC108 | |
213 | #define CP_RB_WPTR 0xC114 | |
214 | #define CP_RB_WPTR_ADDR 0xC118 | |
215 | #define CP_RB_WPTR_ADDR_HI 0xC11C | |
216 | #define CP_RB_WPTR_DELAY 0x8704 | |
217 | #define CP_ROQ_IB1_STAT 0x8784 | |
218 | #define CP_ROQ_IB2_STAT 0x8788 | |
219 | #define CP_SEM_WAIT_TIMER 0x85BC | |
220 | ||
221 | #define DB_DEBUG 0x9830 | |
222 | #define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) | |
223 | #define DB_DEPTH_BASE 0x2800C | |
a39533b4 | 224 | #define DB_HTILE_DATA_BASE 0x28014 |
88f50c80 JG |
225 | #define DB_HTILE_SURFACE 0x28D24 |
226 | #define S_028D24_HTILE_WIDTH(x) (((x) & 0x1) << 0) | |
227 | #define G_028D24_HTILE_WIDTH(x) (((x) >> 0) & 0x1) | |
228 | #define C_028D24_HTILE_WIDTH 0xFFFFFFFE | |
229 | #define S_028D24_HTILE_HEIGHT(x) (((x) & 0x1) << 1) | |
230 | #define G_028D24_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) | |
231 | #define C_028D24_HTILE_HEIGHT 0xFFFFFFFD | |
232 | #define G_028D24_LINEAR(x) (((x) >> 2) & 0x1) | |
3ce0a23d JG |
233 | #define DB_WATERMARKS 0x9838 |
234 | #define DEPTH_FREE(x) ((x) << 0) | |
235 | #define DEPTH_FLUSH(x) ((x) << 5) | |
236 | #define DEPTH_PENDING_FREE(x) ((x) << 15) | |
237 | #define DEPTH_CACHELINE_FREE(x) ((x) << 20) | |
238 | ||
239 | #define DCP_TILING_CONFIG 0x6CA0 | |
240 | #define PIPE_TILING(x) ((x) << 1) | |
241 | #define BANK_TILING(x) ((x) << 4) | |
242 | #define GROUP_SIZE(x) ((x) << 6) | |
243 | #define ROW_TILING(x) ((x) << 8) | |
244 | #define BANK_SWAPS(x) ((x) << 11) | |
245 | #define SAMPLE_SPLIT(x) ((x) << 14) | |
246 | #define BACKEND_MAP(x) ((x) << 16) | |
247 | ||
248 | #define GB_TILING_CONFIG 0x98F0 | |
416a2bd2 AD |
249 | #define PIPE_TILING__SHIFT 1 |
250 | #define PIPE_TILING__MASK 0x0000000e | |
3ce0a23d JG |
251 | |
252 | #define GC_USER_SHADER_PIPE_CONFIG 0x8954 | |
253 | #define INACTIVE_QD_PIPES(x) ((x) << 8) | |
254 | #define INACTIVE_QD_PIPES_MASK 0x0000FF00 | |
255 | #define INACTIVE_SIMDS(x) ((x) << 16) | |
256 | #define INACTIVE_SIMDS_MASK 0x00FF0000 | |
257 | ||
258 | #define SQ_CONFIG 0x8c00 | |
259 | # define VC_ENABLE (1 << 0) | |
260 | # define EXPORT_SRC_C (1 << 1) | |
261 | # define DX9_CONSTS (1 << 2) | |
262 | # define ALU_INST_PREFER_VECTOR (1 << 3) | |
263 | # define DX10_CLAMP (1 << 4) | |
264 | # define CLAUSE_SEQ_PRIO(x) ((x) << 8) | |
265 | # define PS_PRIO(x) ((x) << 24) | |
266 | # define VS_PRIO(x) ((x) << 26) | |
267 | # define GS_PRIO(x) ((x) << 28) | |
268 | # define ES_PRIO(x) ((x) << 30) | |
269 | #define SQ_GPR_RESOURCE_MGMT_1 0x8c04 | |
270 | # define NUM_PS_GPRS(x) ((x) << 0) | |
271 | # define NUM_VS_GPRS(x) ((x) << 16) | |
272 | # define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) | |
273 | #define SQ_GPR_RESOURCE_MGMT_2 0x8c08 | |
274 | # define NUM_GS_GPRS(x) ((x) << 0) | |
275 | # define NUM_ES_GPRS(x) ((x) << 16) | |
276 | #define SQ_THREAD_RESOURCE_MGMT 0x8c0c | |
277 | # define NUM_PS_THREADS(x) ((x) << 0) | |
278 | # define NUM_VS_THREADS(x) ((x) << 8) | |
279 | # define NUM_GS_THREADS(x) ((x) << 16) | |
280 | # define NUM_ES_THREADS(x) ((x) << 24) | |
281 | #define SQ_STACK_RESOURCE_MGMT_1 0x8c10 | |
282 | # define NUM_PS_STACK_ENTRIES(x) ((x) << 0) | |
283 | # define NUM_VS_STACK_ENTRIES(x) ((x) << 16) | |
284 | #define SQ_STACK_RESOURCE_MGMT_2 0x8c14 | |
285 | # define NUM_GS_STACK_ENTRIES(x) ((x) << 0) | |
286 | # define NUM_ES_STACK_ENTRIES(x) ((x) << 16) | |
a39533b4 AD |
287 | #define SQ_ESGS_RING_BASE 0x8c40 |
288 | #define SQ_GSVS_RING_BASE 0x8c48 | |
289 | #define SQ_ESTMP_RING_BASE 0x8c50 | |
290 | #define SQ_GSTMP_RING_BASE 0x8c58 | |
291 | #define SQ_VSTMP_RING_BASE 0x8c60 | |
292 | #define SQ_PSTMP_RING_BASE 0x8c68 | |
293 | #define SQ_FBUF_RING_BASE 0x8c70 | |
294 | #define SQ_REDUC_RING_BASE 0x8c78 | |
3ce0a23d JG |
295 | |
296 | #define GRBM_CNTL 0x8000 | |
297 | # define GRBM_READ_TIMEOUT(x) ((x) << 0) | |
298 | #define GRBM_STATUS 0x8010 | |
299 | #define CMDFIFO_AVAIL_MASK 0x0000001F | |
300 | #define GUI_ACTIVE (1<<31) | |
301 | #define GRBM_STATUS2 0x8014 | |
302 | #define GRBM_SOFT_RESET 0x8020 | |
303 | #define SOFT_RESET_CP (1<<0) | |
304 | ||
4a6369e9 AD |
305 | #define CG_THERMAL_CTRL 0x7F0 |
306 | #define DIG_THERM_DPM(x) ((x) << 12) | |
307 | #define DIG_THERM_DPM_MASK 0x000FF000 | |
308 | #define DIG_THERM_DPM_SHIFT 12 | |
21a8122a AD |
309 | #define CG_THERMAL_STATUS 0x7F4 |
310 | #define ASIC_T(x) ((x) << 0) | |
311 | #define ASIC_T_MASK 0x1FF | |
312 | #define ASIC_T_SHIFT 0 | |
4a6369e9 AD |
313 | #define CG_THERMAL_INT 0x7F8 |
314 | #define DIG_THERM_INTH(x) ((x) << 8) | |
315 | #define DIG_THERM_INTH_MASK 0x0000FF00 | |
316 | #define DIG_THERM_INTH_SHIFT 8 | |
317 | #define DIG_THERM_INTL(x) ((x) << 16) | |
318 | #define DIG_THERM_INTL_MASK 0x00FF0000 | |
319 | #define DIG_THERM_INTL_SHIFT 16 | |
320 | #define THERM_INT_MASK_HIGH (1 << 24) | |
321 | #define THERM_INT_MASK_LOW (1 << 25) | |
21a8122a | 322 | |
66229b20 AD |
323 | #define RV770_CG_THERMAL_INT 0x734 |
324 | ||
3ce0a23d JG |
325 | #define HDP_HOST_PATH_CNTL 0x2C00 |
326 | #define HDP_NONSURFACE_BASE 0x2C04 | |
327 | #define HDP_NONSURFACE_INFO 0x2C08 | |
328 | #define HDP_NONSURFACE_SIZE 0x2C0C | |
329 | #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 | |
330 | #define HDP_TILING_CONFIG 0x2F3C | |
812d0469 | 331 | #define HDP_DEBUG1 0x2F34 |
3ce0a23d JG |
332 | |
333 | #define MC_VM_AGP_TOP 0x2184 | |
334 | #define MC_VM_AGP_BOT 0x2188 | |
335 | #define MC_VM_AGP_BASE 0x218C | |
336 | #define MC_VM_FB_LOCATION 0x2180 | |
337 | #define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C | |
338 | #define ENABLE_L1_TLB (1 << 0) | |
339 | #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) | |
340 | #define ENABLE_L1_STRICT_ORDERING (1 << 2) | |
341 | #define SYSTEM_ACCESS_MODE_MASK 0x000000C0 | |
342 | #define SYSTEM_ACCESS_MODE_SHIFT 6 | |
343 | #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) | |
344 | #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) | |
345 | #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) | |
346 | #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) | |
347 | #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) | |
348 | #define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) | |
349 | #define ENABLE_SEMAPHORE_MODE (1 << 10) | |
350 | #define ENABLE_WAIT_L2_QUERY (1 << 11) | |
351 | #define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12) | |
352 | #define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000 | |
353 | #define EFFECTIVE_L1_TLB_SIZE_SHIFT 12 | |
354 | #define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15) | |
355 | #define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000 | |
356 | #define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15 | |
357 | #define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0 | |
358 | #define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC | |
359 | #define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204 | |
360 | #define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208 | |
361 | #define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C | |
362 | #define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200 | |
363 | #define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4 | |
364 | #define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8 | |
365 | #define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210 | |
366 | #define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218 | |
367 | #define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C | |
368 | #define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220 | |
369 | #define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214 | |
370 | #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 | |
371 | #define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF | |
372 | #define LOGICAL_PAGE_NUMBER_SHIFT 0 | |
373 | #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 | |
374 | #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 | |
375 | ||
376 | #define PA_CL_ENHANCE 0x8A14 | |
377 | #define CLIP_VTX_REORDER_ENA (1 << 0) | |
378 | #define NUM_CLIP_SEQ(x) ((x) << 1) | |
379 | #define PA_SC_AA_CONFIG 0x28C04 | |
380 | #define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40 | |
381 | #define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44 | |
382 | #define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48 | |
383 | #define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C | |
384 | #define S0_X(x) ((x) << 0) | |
385 | #define S0_Y(x) ((x) << 4) | |
386 | #define S1_X(x) ((x) << 8) | |
387 | #define S1_Y(x) ((x) << 12) | |
388 | #define S2_X(x) ((x) << 16) | |
389 | #define S2_Y(x) ((x) << 20) | |
390 | #define S3_X(x) ((x) << 24) | |
391 | #define S3_Y(x) ((x) << 28) | |
392 | #define S4_X(x) ((x) << 0) | |
393 | #define S4_Y(x) ((x) << 4) | |
394 | #define S5_X(x) ((x) << 8) | |
395 | #define S5_Y(x) ((x) << 12) | |
396 | #define S6_X(x) ((x) << 16) | |
397 | #define S6_Y(x) ((x) << 20) | |
398 | #define S7_X(x) ((x) << 24) | |
399 | #define S7_Y(x) ((x) << 28) | |
400 | #define PA_SC_CLIPRECT_RULE 0x2820c | |
401 | #define PA_SC_ENHANCE 0x8BF0 | |
402 | #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) | |
403 | #define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) | |
404 | #define PA_SC_LINE_STIPPLE 0x28A0C | |
405 | #define PA_SC_LINE_STIPPLE_STATE 0x8B10 | |
406 | #define PA_SC_MODE_CNTL 0x28A4C | |
407 | #define PA_SC_MULTI_CHIP_CNTL 0x8B20 | |
408 | ||
409 | #define PA_SC_SCREEN_SCISSOR_TL 0x28030 | |
410 | #define PA_SC_GENERIC_SCISSOR_TL 0x28240 | |
411 | #define PA_SC_WINDOW_SCISSOR_TL 0x28204 | |
412 | ||
413 | #define PCIE_PORT_INDEX 0x0038 | |
414 | #define PCIE_PORT_DATA 0x003C | |
415 | ||
5885b7a9 AD |
416 | #define CHMAP 0x2004 |
417 | #define NOOFCHAN_SHIFT 12 | |
418 | #define NOOFCHAN_MASK 0x00003000 | |
419 | ||
3ce0a23d JG |
420 | #define RAMCFG 0x2408 |
421 | #define NOOFBANK_SHIFT 0 | |
422 | #define NOOFBANK_MASK 0x00000001 | |
423 | #define NOOFRANK_SHIFT 1 | |
424 | #define NOOFRANK_MASK 0x00000002 | |
425 | #define NOOFROWS_SHIFT 2 | |
426 | #define NOOFROWS_MASK 0x0000001C | |
427 | #define NOOFCOLS_SHIFT 5 | |
428 | #define NOOFCOLS_MASK 0x00000060 | |
429 | #define CHANSIZE_SHIFT 7 | |
430 | #define CHANSIZE_MASK 0x00000080 | |
431 | #define BURSTLENGTH_SHIFT 8 | |
432 | #define BURSTLENGTH_MASK 0x00000100 | |
433 | #define CHANSIZE_OVERRIDE (1 << 10) | |
434 | ||
435 | #define SCRATCH_REG0 0x8500 | |
436 | #define SCRATCH_REG1 0x8504 | |
437 | #define SCRATCH_REG2 0x8508 | |
438 | #define SCRATCH_REG3 0x850C | |
439 | #define SCRATCH_REG4 0x8510 | |
440 | #define SCRATCH_REG5 0x8514 | |
441 | #define SCRATCH_REG6 0x8518 | |
442 | #define SCRATCH_REG7 0x851C | |
443 | #define SCRATCH_UMSK 0x8540 | |
444 | #define SCRATCH_ADDR 0x8544 | |
445 | ||
446 | #define SPI_CONFIG_CNTL 0x9100 | |
447 | #define GPR_WRITE_PRIORITY(x) ((x) << 0) | |
448 | #define DISABLE_INTERP_1 (1 << 5) | |
449 | #define SPI_CONFIG_CNTL_1 0x913C | |
450 | #define VTX_DONE_DELAY(x) ((x) << 0) | |
451 | #define INTERP_ONE_PRIM_PER_ROW (1 << 4) | |
452 | #define SPI_INPUT_Z 0x286D8 | |
453 | #define SPI_PS_IN_CONTROL_0 0x286CC | |
454 | #define NUM_INTERP(x) ((x)<<0) | |
455 | #define POSITION_ENA (1<<8) | |
456 | #define POSITION_CENTROID (1<<9) | |
457 | #define POSITION_ADDR(x) ((x)<<10) | |
458 | #define PARAM_GEN(x) ((x)<<15) | |
459 | #define PARAM_GEN_ADDR(x) ((x)<<19) | |
460 | #define BARYC_SAMPLE_CNTL(x) ((x)<<26) | |
461 | #define PERSP_GRADIENT_ENA (1<<28) | |
462 | #define LINEAR_GRADIENT_ENA (1<<29) | |
463 | #define POSITION_SAMPLE (1<<30) | |
464 | #define BARYC_AT_SAMPLE_ENA (1<<31) | |
465 | #define SPI_PS_IN_CONTROL_1 0x286D0 | |
466 | #define GEN_INDEX_PIX (1<<0) | |
467 | #define GEN_INDEX_PIX_ADDR(x) ((x)<<1) | |
468 | #define FRONT_FACE_ENA (1<<8) | |
469 | #define FRONT_FACE_CHAN(x) ((x)<<9) | |
470 | #define FRONT_FACE_ALL_BITS (1<<11) | |
471 | #define FRONT_FACE_ADDR(x) ((x)<<12) | |
472 | #define FOG_ADDR(x) ((x)<<17) | |
473 | #define FIXED_PT_POSITION_ENA (1<<24) | |
474 | #define FIXED_PT_POSITION_ADDR(x) ((x)<<25) | |
475 | ||
476 | #define SQ_MS_FIFO_SIZES 0x8CF0 | |
477 | #define CACHE_FIFO_SIZE(x) ((x) << 0) | |
478 | #define FETCH_FIFO_HIWATER(x) ((x) << 8) | |
479 | #define DONE_FIFO_HIWATER(x) ((x) << 16) | |
480 | #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) | |
481 | #define SQ_PGM_START_ES 0x28880 | |
482 | #define SQ_PGM_START_FS 0x28894 | |
483 | #define SQ_PGM_START_GS 0x2886C | |
484 | #define SQ_PGM_START_PS 0x28840 | |
485 | #define SQ_PGM_RESOURCES_PS 0x28850 | |
486 | #define SQ_PGM_EXPORTS_PS 0x28854 | |
487 | #define SQ_PGM_CF_OFFSET_PS 0x288cc | |
488 | #define SQ_PGM_START_VS 0x28858 | |
489 | #define SQ_PGM_RESOURCES_VS 0x28868 | |
490 | #define SQ_PGM_CF_OFFSET_VS 0x288d0 | |
3a38612e IH |
491 | |
492 | #define SQ_VTX_CONSTANT_WORD0_0 0x30000 | |
493 | #define SQ_VTX_CONSTANT_WORD1_0 0x30004 | |
494 | #define SQ_VTX_CONSTANT_WORD2_0 0x30008 | |
495 | # define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0) | |
496 | # define SQ_VTXC_STRIDE(x) ((x) << 8) | |
497 | # define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30) | |
498 | # define SQ_ENDIAN_NONE 0 | |
499 | # define SQ_ENDIAN_8IN16 1 | |
500 | # define SQ_ENDIAN_8IN32 2 | |
501 | #define SQ_VTX_CONSTANT_WORD3_0 0x3000c | |
3ce0a23d JG |
502 | #define SQ_VTX_CONSTANT_WORD6_0 0x38018 |
503 | #define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30) | |
504 | #define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3) | |
505 | #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 | |
506 | #define SQ_TEX_VTX_INVALID_BUFFER 0x1 | |
507 | #define SQ_TEX_VTX_VALID_TEXTURE 0x2 | |
508 | #define SQ_TEX_VTX_VALID_BUFFER 0x3 | |
509 | ||
510 | ||
511 | #define SX_MISC 0x28350 | |
a39533b4 | 512 | #define SX_MEMORY_EXPORT_BASE 0x9010 |
3ce0a23d JG |
513 | #define SX_DEBUG_1 0x9054 |
514 | #define SMX_EVENT_RELEASE (1 << 0) | |
515 | #define ENABLE_NEW_SMX_ADDRESS (1 << 16) | |
516 | ||
517 | #define TA_CNTL_AUX 0x9508 | |
518 | #define DISABLE_CUBE_WRAP (1 << 0) | |
519 | #define DISABLE_CUBE_ANISO (1 << 1) | |
520 | #define SYNC_GRADIENT (1 << 24) | |
521 | #define SYNC_WALKER (1 << 25) | |
522 | #define SYNC_ALIGNER (1 << 26) | |
523 | #define BILINEAR_PRECISION_6_BIT (0 << 31) | |
524 | #define BILINEAR_PRECISION_8_BIT (1 << 31) | |
525 | ||
526 | #define TC_CNTL 0x9608 | |
527 | #define TC_L2_SIZE(x) ((x)<<5) | |
528 | #define L2_DISABLE_LATE_HIT (1<<9) | |
529 | ||
b866d133 | 530 | #define VC_ENHANCE 0x9714 |
3ce0a23d JG |
531 | |
532 | #define VGT_CACHE_INVALIDATION 0x88C4 | |
533 | #define CACHE_INVALIDATION(x) ((x)<<0) | |
534 | #define VC_ONLY 0 | |
535 | #define TC_ONLY 1 | |
536 | #define VC_AND_TC 2 | |
537 | #define VGT_DMA_BASE 0x287E8 | |
538 | #define VGT_DMA_BASE_HI 0x287E4 | |
539 | #define VGT_ES_PER_GS 0x88CC | |
540 | #define VGT_GS_PER_ES 0x88C8 | |
541 | #define VGT_GS_PER_VS 0x88E8 | |
542 | #define VGT_GS_VERTEX_REUSE 0x88D4 | |
543 | #define VGT_PRIMITIVE_TYPE 0x8958 | |
544 | #define VGT_NUM_INSTANCES 0x8974 | |
545 | #define VGT_OUT_DEALLOC_CNTL 0x28C5C | |
546 | #define DEALLOC_DIST_MASK 0x0000007F | |
547 | #define VGT_STRMOUT_BASE_OFFSET_0 0x28B10 | |
548 | #define VGT_STRMOUT_BASE_OFFSET_1 0x28B14 | |
549 | #define VGT_STRMOUT_BASE_OFFSET_2 0x28B18 | |
550 | #define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c | |
551 | #define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44 | |
552 | #define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48 | |
553 | #define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c | |
554 | #define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50 | |
555 | #define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 | |
556 | #define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 | |
557 | #define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 | |
558 | #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 | |
559 | #define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC | |
560 | #define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC | |
561 | #define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC | |
562 | #define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C | |
dd220a00 MO |
563 | #define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0 |
564 | #define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0 | |
565 | #define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0 | |
566 | #define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00 | |
567 | ||
3ce0a23d JG |
568 | #define VGT_STRMOUT_EN 0x28AB0 |
569 | #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 | |
570 | #define VTX_REUSE_DEPTH_MASK 0x000000FF | |
571 | #define VGT_EVENT_INITIATOR 0x28a90 | |
d0f8a854 | 572 | # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) |
3ce0a23d JG |
573 | # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) |
574 | ||
575 | #define VM_CONTEXT0_CNTL 0x1410 | |
576 | #define ENABLE_CONTEXT (1 << 0) | |
577 | #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) | |
578 | #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) | |
579 | #define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 | |
580 | #define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0 | |
581 | #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 | |
582 | #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 | |
583 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4 | |
584 | #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554 | |
585 | #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 | |
586 | #define REQUEST_TYPE(x) (((x) & 0xf) << 0) | |
587 | #define RESPONSE_TYPE_MASK 0x000000F0 | |
588 | #define RESPONSE_TYPE_SHIFT 4 | |
589 | #define VM_L2_CNTL 0x1400 | |
590 | #define ENABLE_L2_CACHE (1 << 0) | |
591 | #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) | |
592 | #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) | |
593 | #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13) | |
594 | #define VM_L2_CNTL2 0x1404 | |
595 | #define INVALIDATE_ALL_L1_TLBS (1 << 0) | |
596 | #define INVALIDATE_L2_CACHE (1 << 1) | |
597 | #define VM_L2_CNTL3 0x1408 | |
598 | #define BANK_SELECT_0(x) (((x) & 0x1f) << 0) | |
599 | #define BANK_SELECT_1(x) (((x) & 0x1f) << 5) | |
600 | #define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10) | |
601 | #define VM_L2_STATUS 0x140C | |
602 | #define L2_BUSY (1 << 0) | |
603 | ||
604 | #define WAIT_UNTIL 0x8040 | |
072b5acc | 605 | #define WAIT_CP_DMA_IDLE_bit (1 << 8) |
3ce0a23d JG |
606 | #define WAIT_2D_IDLE_bit (1 << 14) |
607 | #define WAIT_3D_IDLE_bit (1 << 15) | |
608 | #define WAIT_2D_IDLECLEAN_bit (1 << 16) | |
609 | #define WAIT_3D_IDLECLEAN_bit (1 << 17) | |
610 | ||
4d75658b AD |
611 | /* async DMA */ |
612 | #define DMA_TILING_CONFIG 0x3ec4 | |
613 | #define DMA_CONFIG 0x3e4c | |
614 | ||
615 | #define DMA_RB_CNTL 0xd000 | |
616 | # define DMA_RB_ENABLE (1 << 0) | |
617 | # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ | |
618 | # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ | |
619 | # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) | |
620 | # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ | |
621 | # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ | |
622 | #define DMA_RB_BASE 0xd004 | |
623 | #define DMA_RB_RPTR 0xd008 | |
624 | #define DMA_RB_WPTR 0xd00c | |
625 | ||
626 | #define DMA_RB_RPTR_ADDR_HI 0xd01c | |
627 | #define DMA_RB_RPTR_ADDR_LO 0xd020 | |
628 | ||
629 | #define DMA_IB_CNTL 0xd024 | |
630 | # define DMA_IB_ENABLE (1 << 0) | |
631 | # define DMA_IB_SWAP_ENABLE (1 << 4) | |
632 | #define DMA_IB_RPTR 0xd028 | |
633 | #define DMA_CNTL 0xd02c | |
634 | # define TRAP_ENABLE (1 << 0) | |
635 | # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) | |
636 | # define SEM_WAIT_INT_ENABLE (1 << 2) | |
637 | # define DATA_SWAP_ENABLE (1 << 3) | |
638 | # define FENCE_SWAP_ENABLE (1 << 4) | |
639 | # define CTXEMPTY_INT_ENABLE (1 << 28) | |
640 | #define DMA_STATUS_REG 0xd034 | |
641 | # define DMA_IDLE (1 << 0) | |
642 | #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044 | |
643 | #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048 | |
644 | #define DMA_MODE 0xd0bc | |
645 | ||
646 | /* async DMA packets */ | |
647 | #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ | |
648 | (((t) & 0x1) << 23) | \ | |
649 | (((s) & 0x1) << 22) | \ | |
650 | (((n) & 0xFFFF) << 0)) | |
651 | /* async DMA Packet types */ | |
652 | #define DMA_PACKET_WRITE 0x2 | |
653 | #define DMA_PACKET_COPY 0x3 | |
654 | #define DMA_PACKET_INDIRECT_BUFFER 0x4 | |
655 | #define DMA_PACKET_SEMAPHORE 0x5 | |
656 | #define DMA_PACKET_FENCE 0x6 | |
657 | #define DMA_PACKET_TRAP 0x7 | |
658 | #define DMA_PACKET_CONSTANT_FILL 0xd /* 7xx only */ | |
659 | #define DMA_PACKET_NOP 0xf | |
660 | ||
d8f60cfc AD |
661 | #define IH_RB_CNTL 0x3e00 |
662 | # define IH_RB_ENABLE (1 << 0) | |
4d75658b | 663 | # define IH_RB_SIZE(x) ((x) << 1) /* log2 */ |
d8f60cfc AD |
664 | # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) |
665 | # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) | |
666 | # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ | |
667 | # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) | |
668 | # define IH_WPTR_OVERFLOW_CLEAR (1 << 31) | |
669 | #define IH_RB_BASE 0x3e04 | |
670 | #define IH_RB_RPTR 0x3e08 | |
671 | #define IH_RB_WPTR 0x3e0c | |
672 | # define RB_OVERFLOW (1 << 0) | |
673 | # define WPTR_OFFSET_MASK 0x3fffc | |
674 | #define IH_RB_WPTR_ADDR_HI 0x3e10 | |
675 | #define IH_RB_WPTR_ADDR_LO 0x3e14 | |
676 | #define IH_CNTL 0x3e18 | |
677 | # define ENABLE_INTR (1 << 0) | |
fcb857ab | 678 | # define IH_MC_SWAP(x) ((x) << 1) |
d8f60cfc AD |
679 | # define IH_MC_SWAP_NONE 0 |
680 | # define IH_MC_SWAP_16BIT 1 | |
681 | # define IH_MC_SWAP_32BIT 2 | |
682 | # define IH_MC_SWAP_64BIT 3 | |
683 | # define RPTR_REARM (1 << 4) | |
684 | # define MC_WRREQ_CREDIT(x) ((x) << 15) | |
685 | # define MC_WR_CLEAN_CNT(x) ((x) << 20) | |
686 | ||
687 | #define RLC_CNTL 0x3f00 | |
688 | # define RLC_ENABLE (1 << 0) | |
689 | #define RLC_HB_BASE 0x3f10 | |
690 | #define RLC_HB_CNTL 0x3f0c | |
691 | #define RLC_HB_RPTR 0x3f20 | |
692 | #define RLC_HB_WPTR 0x3f1c | |
693 | #define RLC_HB_WPTR_LSB_ADDR 0x3f14 | |
694 | #define RLC_HB_WPTR_MSB_ADDR 0x3f18 | |
6759a0a7 MO |
695 | #define RLC_GPU_CLOCK_COUNT_LSB 0x3f38 |
696 | #define RLC_GPU_CLOCK_COUNT_MSB 0x3f3c | |
697 | #define RLC_CAPTURE_GPU_CLOCK_COUNT 0x3f40 | |
d8f60cfc AD |
698 | #define RLC_MC_CNTL 0x3f44 |
699 | #define RLC_UCODE_CNTL 0x3f48 | |
700 | #define RLC_UCODE_ADDR 0x3f2c | |
701 | #define RLC_UCODE_DATA 0x3f30 | |
702 | ||
703 | #define SRBM_SOFT_RESET 0xe60 | |
4d75658b | 704 | # define SOFT_RESET_DMA (1 << 12) |
d8f60cfc | 705 | # define SOFT_RESET_RLC (1 << 13) |
f2ba57b5 | 706 | # define SOFT_RESET_UVD (1 << 18) |
4d75658b | 707 | # define RV770_SOFT_RESET_DMA (1 << 20) |
d8f60cfc AD |
708 | |
709 | #define CP_INT_CNTL 0xc124 | |
710 | # define CNTX_BUSY_INT_ENABLE (1 << 19) | |
711 | # define CNTX_EMPTY_INT_ENABLE (1 << 20) | |
712 | # define SCRATCH_INT_ENABLE (1 << 25) | |
713 | # define TIME_STAMP_INT_ENABLE (1 << 26) | |
714 | # define IB2_INT_ENABLE (1 << 29) | |
715 | # define IB1_INT_ENABLE (1 << 30) | |
716 | # define RB_INT_ENABLE (1 << 31) | |
717 | #define CP_INT_STATUS 0xc128 | |
718 | # define SCRATCH_INT_STAT (1 << 25) | |
719 | # define TIME_STAMP_INT_STAT (1 << 26) | |
720 | # define IB2_INT_STAT (1 << 29) | |
721 | # define IB1_INT_STAT (1 << 30) | |
722 | # define RB_INT_STAT (1 << 31) | |
723 | ||
724 | #define GRBM_INT_CNTL 0x8060 | |
725 | # define RDERR_INT_ENABLE (1 << 0) | |
726 | # define WAIT_COUNT_TIMEOUT_INT_ENABLE (1 << 1) | |
727 | # define GUI_IDLE_INT_ENABLE (1 << 19) | |
728 | ||
729 | #define INTERRUPT_CNTL 0x5468 | |
730 | # define IH_DUMMY_RD_OVERRIDE (1 << 0) | |
731 | # define IH_DUMMY_RD_EN (1 << 1) | |
732 | # define IH_REQ_NONSNOOP_EN (1 << 3) | |
733 | # define GEN_IH_INT_EN (1 << 8) | |
734 | #define INTERRUPT_CNTL2 0x546c | |
735 | ||
736 | #define D1MODE_VBLANK_STATUS 0x6534 | |
737 | #define D2MODE_VBLANK_STATUS 0x6d34 | |
738 | # define DxMODE_VBLANK_OCCURRED (1 << 0) | |
739 | # define DxMODE_VBLANK_ACK (1 << 4) | |
740 | # define DxMODE_VBLANK_STAT (1 << 12) | |
741 | # define DxMODE_VBLANK_INTERRUPT (1 << 16) | |
742 | # define DxMODE_VBLANK_INTERRUPT_TYPE (1 << 17) | |
743 | #define D1MODE_VLINE_STATUS 0x653c | |
744 | #define D2MODE_VLINE_STATUS 0x6d3c | |
745 | # define DxMODE_VLINE_OCCURRED (1 << 0) | |
746 | # define DxMODE_VLINE_ACK (1 << 4) | |
747 | # define DxMODE_VLINE_STAT (1 << 12) | |
748 | # define DxMODE_VLINE_INTERRUPT (1 << 16) | |
749 | # define DxMODE_VLINE_INTERRUPT_TYPE (1 << 17) | |
750 | #define DxMODE_INT_MASK 0x6540 | |
751 | # define D1MODE_VBLANK_INT_MASK (1 << 0) | |
752 | # define D1MODE_VLINE_INT_MASK (1 << 4) | |
753 | # define D2MODE_VBLANK_INT_MASK (1 << 8) | |
754 | # define D2MODE_VLINE_INT_MASK (1 << 12) | |
755 | #define DCE3_DISP_INTERRUPT_STATUS 0x7ddc | |
756 | # define DC_HPD1_INTERRUPT (1 << 18) | |
757 | # define DC_HPD2_INTERRUPT (1 << 19) | |
758 | #define DISP_INTERRUPT_STATUS 0x7edc | |
759 | # define LB_D1_VLINE_INTERRUPT (1 << 2) | |
760 | # define LB_D2_VLINE_INTERRUPT (1 << 3) | |
761 | # define LB_D1_VBLANK_INTERRUPT (1 << 4) | |
762 | # define LB_D2_VBLANK_INTERRUPT (1 << 5) | |
763 | # define DACA_AUTODETECT_INTERRUPT (1 << 16) | |
764 | # define DACB_AUTODETECT_INTERRUPT (1 << 17) | |
765 | # define DC_HOT_PLUG_DETECT1_INTERRUPT (1 << 18) | |
766 | # define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19) | |
767 | # define DC_I2C_SW_DONE_INTERRUPT (1 << 20) | |
768 | # define DC_I2C_HW_DONE_INTERRUPT (1 << 21) | |
b500f680 | 769 | #define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8 |
d8f60cfc AD |
770 | #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8 |
771 | # define DC_HPD4_INTERRUPT (1 << 14) | |
772 | # define DC_HPD4_RX_INTERRUPT (1 << 15) | |
773 | # define DC_HPD3_INTERRUPT (1 << 28) | |
774 | # define DC_HPD1_RX_INTERRUPT (1 << 29) | |
775 | # define DC_HPD2_RX_INTERRUPT (1 << 30) | |
776 | #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE2 0x7dec | |
777 | # define DC_HPD3_RX_INTERRUPT (1 << 0) | |
778 | # define DIGA_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 1) | |
779 | # define DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 2) | |
780 | # define DIGB_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 3) | |
781 | # define DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 4) | |
782 | # define AUX1_SW_DONE_INTERRUPT (1 << 5) | |
783 | # define AUX1_LS_DONE_INTERRUPT (1 << 6) | |
784 | # define AUX2_SW_DONE_INTERRUPT (1 << 7) | |
785 | # define AUX2_LS_DONE_INTERRUPT (1 << 8) | |
786 | # define AUX3_SW_DONE_INTERRUPT (1 << 9) | |
787 | # define AUX3_LS_DONE_INTERRUPT (1 << 10) | |
788 | # define AUX4_SW_DONE_INTERRUPT (1 << 11) | |
789 | # define AUX4_LS_DONE_INTERRUPT (1 << 12) | |
790 | # define DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 13) | |
791 | # define DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 14) | |
792 | /* DCE 3.2 */ | |
793 | # define AUX5_SW_DONE_INTERRUPT (1 << 15) | |
794 | # define AUX5_LS_DONE_INTERRUPT (1 << 16) | |
795 | # define AUX6_SW_DONE_INTERRUPT (1 << 17) | |
796 | # define AUX6_LS_DONE_INTERRUPT (1 << 18) | |
797 | # define DC_HPD5_INTERRUPT (1 << 19) | |
798 | # define DC_HPD5_RX_INTERRUPT (1 << 20) | |
799 | # define DC_HPD6_INTERRUPT (1 << 21) | |
800 | # define DC_HPD6_RX_INTERRUPT (1 << 22) | |
801 | ||
b500f680 AD |
802 | #define DACA_AUTO_DETECT_CONTROL 0x7828 |
803 | #define DACB_AUTO_DETECT_CONTROL 0x7a28 | |
804 | #define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028 | |
805 | #define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128 | |
806 | # define DACx_AUTODETECT_MODE(x) ((x) << 0) | |
807 | # define DACx_AUTODETECT_MODE_NONE 0 | |
808 | # define DACx_AUTODETECT_MODE_CONNECT 1 | |
809 | # define DACx_AUTODETECT_MODE_DISCONNECT 2 | |
810 | # define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8) | |
811 | /* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */ | |
812 | # define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16) | |
813 | ||
d8f60cfc AD |
814 | #define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038 |
815 | #define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138 | |
816 | #define DACA_AUTODETECT_INT_CONTROL 0x7838 | |
817 | #define DACB_AUTODETECT_INT_CONTROL 0x7a38 | |
818 | # define DACx_AUTODETECT_ACK (1 << 0) | |
819 | # define DACx_AUTODETECT_INT_ENABLE (1 << 16) | |
820 | ||
b500f680 AD |
821 | #define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00 |
822 | #define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10 | |
823 | #define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24 | |
824 | # define DC_HOT_PLUG_DETECTx_EN (1 << 0) | |
825 | ||
826 | #define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04 | |
827 | #define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14 | |
828 | #define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28 | |
829 | # define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0) | |
830 | # define DC_HOT_PLUG_DETECTx_SENSE (1 << 1) | |
831 | ||
832 | /* DCE 3.0 */ | |
833 | #define DC_HPD1_INT_STATUS 0x7d00 | |
834 | #define DC_HPD2_INT_STATUS 0x7d0c | |
835 | #define DC_HPD3_INT_STATUS 0x7d18 | |
836 | #define DC_HPD4_INT_STATUS 0x7d24 | |
837 | /* DCE 3.2 */ | |
838 | #define DC_HPD5_INT_STATUS 0x7dc0 | |
839 | #define DC_HPD6_INT_STATUS 0x7df4 | |
840 | # define DC_HPDx_INT_STATUS (1 << 0) | |
841 | # define DC_HPDx_SENSE (1 << 1) | |
842 | # define DC_HPDx_RX_INT_STATUS (1 << 8) | |
843 | ||
d8f60cfc AD |
844 | #define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08 |
845 | #define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18 | |
846 | #define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c | |
847 | # define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0) | |
848 | # define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8) | |
849 | # define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16) | |
b500f680 | 850 | /* DCE 3.0 */ |
d8f60cfc AD |
851 | #define DC_HPD1_INT_CONTROL 0x7d04 |
852 | #define DC_HPD2_INT_CONTROL 0x7d10 | |
853 | #define DC_HPD3_INT_CONTROL 0x7d1c | |
854 | #define DC_HPD4_INT_CONTROL 0x7d28 | |
b500f680 AD |
855 | /* DCE 3.2 */ |
856 | #define DC_HPD5_INT_CONTROL 0x7dc4 | |
857 | #define DC_HPD6_INT_CONTROL 0x7df8 | |
d8f60cfc AD |
858 | # define DC_HPDx_INT_ACK (1 << 0) |
859 | # define DC_HPDx_INT_POLARITY (1 << 8) | |
860 | # define DC_HPDx_INT_EN (1 << 16) | |
861 | # define DC_HPDx_RX_INT_ACK (1 << 20) | |
862 | # define DC_HPDx_RX_INT_EN (1 << 24) | |
3ce0a23d | 863 | |
b500f680 AD |
864 | /* DCE 3.0 */ |
865 | #define DC_HPD1_CONTROL 0x7d08 | |
866 | #define DC_HPD2_CONTROL 0x7d14 | |
867 | #define DC_HPD3_CONTROL 0x7d20 | |
868 | #define DC_HPD4_CONTROL 0x7d2c | |
869 | /* DCE 3.2 */ | |
870 | #define DC_HPD5_CONTROL 0x7dc8 | |
871 | #define DC_HPD6_CONTROL 0x7dfc | |
872 | # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) | |
873 | # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) | |
874 | /* DCE 3.2 */ | |
875 | # define DC_HPDx_EN (1 << 28) | |
876 | ||
6f34be50 AD |
877 | #define D1GRPH_INTERRUPT_STATUS 0x6158 |
878 | #define D2GRPH_INTERRUPT_STATUS 0x6958 | |
879 | # define DxGRPH_PFLIP_INT_OCCURRED (1 << 0) | |
880 | # define DxGRPH_PFLIP_INT_CLEAR (1 << 8) | |
881 | #define D1GRPH_INTERRUPT_CONTROL 0x615c | |
882 | #define D2GRPH_INTERRUPT_CONTROL 0x695c | |
883 | # define DxGRPH_PFLIP_INT_MASK (1 << 0) | |
884 | # define DxGRPH_PFLIP_INT_TYPE (1 << 8) | |
885 | ||
9e46a48d AD |
886 | /* PCIE link stuff */ |
887 | #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ | |
888 | # define LC_POINT_7_PLUS_EN (1 << 6) | |
889 | #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ | |
890 | # define LC_LINK_WIDTH_SHIFT 0 | |
891 | # define LC_LINK_WIDTH_MASK 0x7 | |
892 | # define LC_LINK_WIDTH_X0 0 | |
893 | # define LC_LINK_WIDTH_X1 1 | |
894 | # define LC_LINK_WIDTH_X2 2 | |
895 | # define LC_LINK_WIDTH_X4 3 | |
896 | # define LC_LINK_WIDTH_X8 4 | |
897 | # define LC_LINK_WIDTH_X16 6 | |
898 | # define LC_LINK_WIDTH_RD_SHIFT 4 | |
899 | # define LC_LINK_WIDTH_RD_MASK 0x70 | |
900 | # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) | |
901 | # define LC_RECONFIG_NOW (1 << 8) | |
902 | # define LC_RENEGOTIATION_SUPPORT (1 << 9) | |
903 | # define LC_RENEGOTIATE_EN (1 << 10) | |
904 | # define LC_SHORT_RECONFIG_EN (1 << 11) | |
905 | # define LC_UPCONFIGURE_SUPPORT (1 << 12) | |
906 | # define LC_UPCONFIGURE_DIS (1 << 13) | |
907 | #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ | |
908 | # define LC_GEN2_EN_STRAP (1 << 0) | |
909 | # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) | |
910 | # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) | |
911 | # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) | |
912 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) | |
913 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 | |
914 | # define LC_CURRENT_DATA_RATE (1 << 11) | |
915 | # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) | |
916 | # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) | |
917 | # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) | |
918 | # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) | |
919 | #define MM_CFGREGS_CNTL 0x544c | |
920 | # define MM_WR_TO_CFG_EN (1 << 3) | |
921 | #define LINK_CNTL2 0x88 /* F0 */ | |
922 | # define TARGET_LINK_SPEED_MASK (0xf << 0) | |
923 | # define SELECTABLE_DEEMPHASIS (1 << 6) | |
924 | ||
1586505a AD |
925 | /* Audio clocks DCE 2.0/3.0 */ |
926 | #define AUDIO_DTO 0x7340 | |
927 | # define AUDIO_DTO_PHASE(x) (((x) & 0xffff) << 0) | |
928 | # define AUDIO_DTO_MODULE(x) (((x) & 0xffff) << 16) | |
929 | ||
930 | /* Audio clocks DCE 3.2 */ | |
3a2a67aa AD |
931 | #define DCCG_AUDIO_DTO0_PHASE 0x0514 |
932 | #define DCCG_AUDIO_DTO0_MODULE 0x0518 | |
933 | #define DCCG_AUDIO_DTO0_LOAD 0x051c | |
934 | # define DTO_LOAD (1 << 31) | |
935 | #define DCCG_AUDIO_DTO0_CNTL 0x0520 | |
1518dd8e AD |
936 | # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO(x) (((x) & 7) << 0) |
937 | # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK 7 | |
938 | # define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_SHIFT 0 | |
3a2a67aa AD |
939 | |
940 | #define DCCG_AUDIO_DTO1_PHASE 0x0524 | |
941 | #define DCCG_AUDIO_DTO1_MODULE 0x0528 | |
942 | #define DCCG_AUDIO_DTO1_LOAD 0x052c | |
943 | #define DCCG_AUDIO_DTO1_CNTL 0x0530 | |
944 | ||
945 | #define DCCG_AUDIO_DTO_SELECT 0x0534 | |
946 | ||
947 | /* digital blocks */ | |
948 | #define TMDSA_CNTL 0x7880 | |
949 | # define TMDSA_HDMI_EN (1 << 2) | |
950 | #define LVTMA_CNTL 0x7a80 | |
951 | # define LVTMA_HDMI_EN (1 << 2) | |
952 | #define DDIA_CNTL 0x7200 | |
953 | # define DDIA_HDMI_EN (1 << 2) | |
954 | #define DIG0_CNTL 0x75a0 | |
955 | # define DIG_MODE(x) (((x) & 7) << 8) | |
956 | # define DIG_MODE_DP 0 | |
957 | # define DIG_MODE_LVDS 1 | |
958 | # define DIG_MODE_TMDS_DVI 2 | |
959 | # define DIG_MODE_TMDS_HDMI 3 | |
960 | # define DIG_MODE_SDVO 4 | |
961 | #define DIG1_CNTL 0x79a0 | |
962 | ||
0ffae60c AD |
963 | #define AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER 0x71bc |
964 | #define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0) | |
965 | #define SPEAKER_ALLOCATION_MASK (0x7f << 0) | |
966 | #define SPEAKER_ALLOCATION_SHIFT 0 | |
967 | #define HDMI_CONNECTION (1 << 16) | |
968 | #define DP_CONNECTION (1 << 17) | |
969 | ||
c1cbee0e AD |
970 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x71c8 /* LPCM */ |
971 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x71cc /* AC3 */ | |
972 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x71d0 /* MPEG1 */ | |
973 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x71d4 /* MP3 */ | |
974 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x71d8 /* MPEG2 */ | |
975 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x71dc /* AAC */ | |
976 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x71e0 /* DTS */ | |
977 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x71e4 /* ATRAC */ | |
978 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x71e8 /* one bit audio - leave at 0 (default) */ | |
979 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x71ec /* Dolby Digital */ | |
980 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x71f0 /* DTS-HD */ | |
981 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x71f4 /* MAT-MLP */ | |
982 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x71f8 /* DTS */ | |
983 | #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x71fc /* WMA Pro */ | |
984 | # define MAX_CHANNELS(x) (((x) & 0x7) << 0) | |
985 | /* max channels minus one. 7 = 8 channels */ | |
986 | # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) | |
987 | # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) | |
988 | # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ | |
989 | /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO | |
990 | * bit0 = 32 kHz | |
991 | * bit1 = 44.1 kHz | |
992 | * bit2 = 48 kHz | |
993 | * bit3 = 88.2 kHz | |
994 | * bit4 = 96 kHz | |
995 | * bit5 = 176.4 kHz | |
996 | * bit6 = 192 kHz | |
997 | */ | |
998 | ||
3a2a67aa AD |
999 | /* rs6xx/rs740 and r6xx share the same HDMI blocks, however, rs6xx has only one |
1000 | * instance of the blocks while r6xx has 2. DCE 3.0 cards are slightly | |
1001 | * different due to the new DIG blocks, but also have 2 instances. | |
1002 | * DCE 3.0 HDMI blocks are part of each DIG encoder. | |
1003 | */ | |
1004 | ||
1005 | /* rs6xx/rs740/r6xx/dce3 */ | |
1006 | #define HDMI0_CONTROL 0x7400 | |
1007 | /* rs6xx/rs740/r6xx */ | |
1008 | # define HDMI0_ENABLE (1 << 0) | |
1009 | # define HDMI0_STREAM(x) (((x) & 3) << 2) | |
1010 | # define HDMI0_STREAM_TMDSA 0 | |
1011 | # define HDMI0_STREAM_LVTMA 1 | |
1012 | # define HDMI0_STREAM_DVOA 2 | |
1013 | # define HDMI0_STREAM_DDIA 3 | |
1014 | /* rs6xx/r6xx/dce3 */ | |
1015 | # define HDMI0_ERROR_ACK (1 << 8) | |
1016 | # define HDMI0_ERROR_MASK (1 << 9) | |
1017 | #define HDMI0_STATUS 0x7404 | |
1018 | # define HDMI0_ACTIVE_AVMUTE (1 << 0) | |
1019 | # define HDMI0_AUDIO_ENABLE (1 << 4) | |
1020 | # define HDMI0_AZ_FORMAT_WTRIG (1 << 28) | |
1021 | # define HDMI0_AZ_FORMAT_WTRIG_INT (1 << 29) | |
1022 | #define HDMI0_AUDIO_PACKET_CONTROL 0x7408 | |
1023 | # define HDMI0_AUDIO_SAMPLE_SEND (1 << 0) | |
1024 | # define HDMI0_AUDIO_DELAY_EN(x) (((x) & 3) << 4) | |
1025 | # define HDMI0_AUDIO_SEND_MAX_PACKETS (1 << 8) | |
1026 | # define HDMI0_AUDIO_TEST_EN (1 << 12) | |
1027 | # define HDMI0_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) | |
1028 | # define HDMI0_AUDIO_CHANNEL_SWAP (1 << 24) | |
1029 | # define HDMI0_60958_CS_UPDATE (1 << 26) | |
1030 | # define HDMI0_AZ_FORMAT_WTRIG_MASK (1 << 28) | |
1031 | # define HDMI0_AZ_FORMAT_WTRIG_ACK (1 << 29) | |
1032 | #define HDMI0_AUDIO_CRC_CONTROL 0x740c | |
1033 | # define HDMI0_AUDIO_CRC_EN (1 << 0) | |
1034 | #define HDMI0_VBI_PACKET_CONTROL 0x7410 | |
1035 | # define HDMI0_NULL_SEND (1 << 0) | |
1036 | # define HDMI0_GC_SEND (1 << 4) | |
1037 | # define HDMI0_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ | |
1038 | #define HDMI0_INFOFRAME_CONTROL0 0x7414 | |
1039 | # define HDMI0_AVI_INFO_SEND (1 << 0) | |
1040 | # define HDMI0_AVI_INFO_CONT (1 << 1) | |
1041 | # define HDMI0_AUDIO_INFO_SEND (1 << 4) | |
1042 | # define HDMI0_AUDIO_INFO_CONT (1 << 5) | |
d592fca9 | 1043 | # define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hdmi regs */ |
3a2a67aa AD |
1044 | # define HDMI0_AUDIO_INFO_UPDATE (1 << 7) |
1045 | # define HDMI0_MPEG_INFO_SEND (1 << 8) | |
1046 | # define HDMI0_MPEG_INFO_CONT (1 << 9) | |
1047 | # define HDMI0_MPEG_INFO_UPDATE (1 << 10) | |
1048 | #define HDMI0_INFOFRAME_CONTROL1 0x7418 | |
1049 | # define HDMI0_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) | |
1050 | # define HDMI0_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) | |
1051 | # define HDMI0_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) | |
1052 | #define HDMI0_GENERIC_PACKET_CONTROL 0x741c | |
1053 | # define HDMI0_GENERIC0_SEND (1 << 0) | |
1054 | # define HDMI0_GENERIC0_CONT (1 << 1) | |
1055 | # define HDMI0_GENERIC0_UPDATE (1 << 2) | |
1056 | # define HDMI0_GENERIC1_SEND (1 << 4) | |
1057 | # define HDMI0_GENERIC1_CONT (1 << 5) | |
1058 | # define HDMI0_GENERIC0_LINE(x) (((x) & 0x3f) << 16) | |
1059 | # define HDMI0_GENERIC1_LINE(x) (((x) & 0x3f) << 24) | |
1060 | #define HDMI0_GC 0x7428 | |
1061 | # define HDMI0_GC_AVMUTE (1 << 0) | |
1062 | #define HDMI0_AVI_INFO0 0x7454 | |
1063 | # define HDMI0_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) | |
1064 | # define HDMI0_AVI_INFO_S(x) (((x) & 3) << 8) | |
1065 | # define HDMI0_AVI_INFO_B(x) (((x) & 3) << 10) | |
1066 | # define HDMI0_AVI_INFO_A(x) (((x) & 1) << 12) | |
1067 | # define HDMI0_AVI_INFO_Y(x) (((x) & 3) << 13) | |
1068 | # define HDMI0_AVI_INFO_Y_RGB 0 | |
1069 | # define HDMI0_AVI_INFO_Y_YCBCR422 1 | |
1070 | # define HDMI0_AVI_INFO_Y_YCBCR444 2 | |
1071 | # define HDMI0_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) | |
1072 | # define HDMI0_AVI_INFO_R(x) (((x) & 0xf) << 16) | |
1073 | # define HDMI0_AVI_INFO_M(x) (((x) & 0x3) << 20) | |
1074 | # define HDMI0_AVI_INFO_C(x) (((x) & 0x3) << 22) | |
1075 | # define HDMI0_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) | |
1076 | # define HDMI0_AVI_INFO_SC(x) (((x) & 0x3) << 24) | |
1077 | # define HDMI0_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) | |
1078 | #define HDMI0_AVI_INFO1 0x7458 | |
1079 | # define HDMI0_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ | |
1080 | # define HDMI0_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ | |
1081 | # define HDMI0_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) | |
1082 | #define HDMI0_AVI_INFO2 0x745c | |
1083 | # define HDMI0_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) | |
1084 | # define HDMI0_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) | |
1085 | #define HDMI0_AVI_INFO3 0x7460 | |
1086 | # define HDMI0_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) | |
1087 | # define HDMI0_AVI_INFO_VERSION(x) (((x) & 3) << 24) | |
1088 | #define HDMI0_MPEG_INFO0 0x7464 | |
1089 | # define HDMI0_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) | |
1090 | # define HDMI0_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) | |
1091 | # define HDMI0_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) | |
1092 | # define HDMI0_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) | |
1093 | #define HDMI0_MPEG_INFO1 0x7468 | |
1094 | # define HDMI0_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) | |
1095 | # define HDMI0_MPEG_INFO_MF(x) (((x) & 3) << 8) | |
1096 | # define HDMI0_MPEG_INFO_FR(x) (((x) & 1) << 12) | |
1097 | #define HDMI0_GENERIC0_HDR 0x746c | |
1098 | #define HDMI0_GENERIC0_0 0x7470 | |
1099 | #define HDMI0_GENERIC0_1 0x7474 | |
1100 | #define HDMI0_GENERIC0_2 0x7478 | |
1101 | #define HDMI0_GENERIC0_3 0x747c | |
1102 | #define HDMI0_GENERIC0_4 0x7480 | |
1103 | #define HDMI0_GENERIC0_5 0x7484 | |
1104 | #define HDMI0_GENERIC0_6 0x7488 | |
1105 | #define HDMI0_GENERIC1_HDR 0x748c | |
1106 | #define HDMI0_GENERIC1_0 0x7490 | |
1107 | #define HDMI0_GENERIC1_1 0x7494 | |
1108 | #define HDMI0_GENERIC1_2 0x7498 | |
1109 | #define HDMI0_GENERIC1_3 0x749c | |
1110 | #define HDMI0_GENERIC1_4 0x74a0 | |
1111 | #define HDMI0_GENERIC1_5 0x74a4 | |
1112 | #define HDMI0_GENERIC1_6 0x74a8 | |
1113 | #define HDMI0_ACR_32_0 0x74ac | |
1114 | # define HDMI0_ACR_CTS_32(x) (((x) & 0xfffff) << 12) | |
1115 | #define HDMI0_ACR_32_1 0x74b0 | |
1116 | # define HDMI0_ACR_N_32(x) (((x) & 0xfffff) << 0) | |
1117 | #define HDMI0_ACR_44_0 0x74b4 | |
1118 | # define HDMI0_ACR_CTS_44(x) (((x) & 0xfffff) << 12) | |
1119 | #define HDMI0_ACR_44_1 0x74b8 | |
1120 | # define HDMI0_ACR_N_44(x) (((x) & 0xfffff) << 0) | |
1121 | #define HDMI0_ACR_48_0 0x74bc | |
1122 | # define HDMI0_ACR_CTS_48(x) (((x) & 0xfffff) << 12) | |
1123 | #define HDMI0_ACR_48_1 0x74c0 | |
1124 | # define HDMI0_ACR_N_48(x) (((x) & 0xfffff) << 0) | |
1125 | #define HDMI0_ACR_STATUS_0 0x74c4 | |
1126 | #define HDMI0_ACR_STATUS_1 0x74c8 | |
1127 | #define HDMI0_AUDIO_INFO0 0x74cc | |
1128 | # define HDMI0_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) | |
1129 | # define HDMI0_AUDIO_INFO_CC(x) (((x) & 7) << 8) | |
1130 | #define HDMI0_AUDIO_INFO1 0x74d0 | |
1131 | # define HDMI0_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) | |
1132 | # define HDMI0_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) | |
1133 | # define HDMI0_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) | |
1134 | # define HDMI0_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) | |
1135 | #define HDMI0_60958_0 0x74d4 | |
1136 | # define HDMI0_60958_CS_A(x) (((x) & 1) << 0) | |
1137 | # define HDMI0_60958_CS_B(x) (((x) & 1) << 1) | |
1138 | # define HDMI0_60958_CS_C(x) (((x) & 1) << 2) | |
1139 | # define HDMI0_60958_CS_D(x) (((x) & 3) << 3) | |
1140 | # define HDMI0_60958_CS_MODE(x) (((x) & 3) << 6) | |
1141 | # define HDMI0_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) | |
1142 | # define HDMI0_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) | |
1143 | # define HDMI0_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) | |
1144 | # define HDMI0_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) | |
1145 | # define HDMI0_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) | |
1146 | #define HDMI0_60958_1 0x74d8 | |
1147 | # define HDMI0_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) | |
1148 | # define HDMI0_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) | |
1149 | # define HDMI0_60958_CS_VALID_L(x) (((x) & 1) << 16) | |
1150 | # define HDMI0_60958_CS_VALID_R(x) (((x) & 1) << 18) | |
1151 | # define HDMI0_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) | |
1152 | #define HDMI0_ACR_PACKET_CONTROL 0x74dc | |
1153 | # define HDMI0_ACR_SEND (1 << 0) | |
1154 | # define HDMI0_ACR_CONT (1 << 1) | |
1155 | # define HDMI0_ACR_SELECT(x) (((x) & 3) << 4) | |
1156 | # define HDMI0_ACR_HW 0 | |
1157 | # define HDMI0_ACR_32 1 | |
1158 | # define HDMI0_ACR_44 2 | |
1159 | # define HDMI0_ACR_48 3 | |
1160 | # define HDMI0_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ | |
1161 | # define HDMI0_ACR_AUTO_SEND (1 << 12) | |
1162 | #define HDMI0_RAMP_CONTROL0 0x74e0 | |
1163 | # define HDMI0_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) | |
1164 | #define HDMI0_RAMP_CONTROL1 0x74e4 | |
1165 | # define HDMI0_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) | |
1166 | #define HDMI0_RAMP_CONTROL2 0x74e8 | |
1167 | # define HDMI0_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) | |
1168 | #define HDMI0_RAMP_CONTROL3 0x74ec | |
1169 | # define HDMI0_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) | |
1170 | /* HDMI0_60958_2 is r7xx only */ | |
1171 | #define HDMI0_60958_2 0x74f0 | |
1172 | # define HDMI0_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) | |
1173 | # define HDMI0_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) | |
1174 | # define HDMI0_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) | |
1175 | # define HDMI0_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) | |
1176 | # define HDMI0_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) | |
1177 | # define HDMI0_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) | |
1178 | /* r6xx only; second instance starts at 0x7700 */ | |
1179 | #define HDMI1_CONTROL 0x7700 | |
1180 | #define HDMI1_STATUS 0x7704 | |
1181 | #define HDMI1_AUDIO_PACKET_CONTROL 0x7708 | |
1182 | /* DCE3; second instance starts at 0x7800 NOT 0x7700 */ | |
1183 | #define DCE3_HDMI1_CONTROL 0x7800 | |
1184 | #define DCE3_HDMI1_STATUS 0x7804 | |
1185 | #define DCE3_HDMI1_AUDIO_PACKET_CONTROL 0x7808 | |
1186 | /* DCE3.2 (for interrupts) */ | |
1187 | #define AFMT_STATUS 0x7600 | |
1188 | # define AFMT_AUDIO_ENABLE (1 << 4) | |
1189 | # define AFMT_AZ_FORMAT_WTRIG (1 << 28) | |
1190 | # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) | |
1191 | # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) | |
1192 | #define AFMT_AUDIO_PACKET_CONTROL 0x7604 | |
1193 | # define AFMT_AUDIO_SAMPLE_SEND (1 << 0) | |
1194 | # define AFMT_AUDIO_TEST_EN (1 << 12) | |
1195 | # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) | |
1196 | # define AFMT_60958_CS_UPDATE (1 << 26) | |
1197 | # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) | |
1198 | # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) | |
1199 | # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) | |
1200 | # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) | |
c6543a6e | 1201 | |
2e9d4c05 AD |
1202 | /* Power management */ |
1203 | #define CG_SPLL_FUNC_CNTL 0x600 | |
1204 | # define SPLL_RESET (1 << 0) | |
1205 | # define SPLL_SLEEP (1 << 1) | |
1206 | # define SPLL_REF_DIV(x) ((x) << 2) | |
1207 | # define SPLL_REF_DIV_MASK (7 << 2) | |
1208 | # define SPLL_FB_DIV(x) ((x) << 5) | |
1209 | # define SPLL_FB_DIV_MASK (0xff << 5) | |
1210 | # define SPLL_PULSEEN (1 << 13) | |
1211 | # define SPLL_PULSENUM(x) ((x) << 14) | |
1212 | # define SPLL_PULSENUM_MASK (3 << 14) | |
1213 | # define SPLL_SW_HILEN(x) ((x) << 16) | |
1214 | # define SPLL_SW_HILEN_MASK (0xf << 16) | |
1215 | # define SPLL_SW_LOLEN(x) ((x) << 20) | |
1216 | # define SPLL_SW_LOLEN_MASK (0xf << 20) | |
1217 | # define SPLL_DIVEN (1 << 24) | |
1218 | # define SPLL_BYPASS_EN (1 << 25) | |
1219 | # define SPLL_CHG_STATUS (1 << 29) | |
1220 | # define SPLL_CTLREQ (1 << 30) | |
1221 | # define SPLL_CTLACK (1 << 31) | |
1222 | ||
1223 | #define GENERAL_PWRMGT 0x618 | |
1224 | # define GLOBAL_PWRMGT_EN (1 << 0) | |
1225 | # define STATIC_PM_EN (1 << 1) | |
1226 | # define MOBILE_SU (1 << 2) | |
1227 | # define THERMAL_PROTECTION_DIS (1 << 3) | |
1228 | # define THERMAL_PROTECTION_TYPE (1 << 4) | |
1229 | # define ENABLE_GEN2PCIE (1 << 5) | |
1230 | # define SW_GPIO_INDEX(x) ((x) << 6) | |
1231 | # define SW_GPIO_INDEX_MASK (3 << 6) | |
1232 | # define LOW_VOLT_D2_ACPI (1 << 8) | |
1233 | # define LOW_VOLT_D3_ACPI (1 << 9) | |
1234 | # define VOLT_PWRMGT_EN (1 << 10) | |
1235 | #define CG_TPC 0x61c | |
1236 | # define TPCC(x) ((x) << 0) | |
1237 | # define TPCC_MASK (0x7fffff << 0) | |
1238 | # define TPU(x) ((x) << 23) | |
1239 | # define TPU_MASK (0x1f << 23) | |
1240 | #define SCLK_PWRMGT_CNTL 0x620 | |
1241 | # define SCLK_PWRMGT_OFF (1 << 0) | |
1242 | # define SCLK_TURNOFF (1 << 1) | |
1243 | # define SPLL_TURNOFF (1 << 2) | |
1244 | # define SU_SCLK_USE_BCLK (1 << 3) | |
1245 | # define DYNAMIC_GFX_ISLAND_PWR_DOWN (1 << 4) | |
1246 | # define DYNAMIC_GFX_ISLAND_PWR_LP (1 << 5) | |
1247 | # define CLK_TURN_ON_STAGGER (1 << 6) | |
1248 | # define CLK_TURN_OFF_STAGGER (1 << 7) | |
1249 | # define FIR_FORCE_TREND_SEL (1 << 8) | |
1250 | # define FIR_TREND_MODE (1 << 9) | |
1251 | # define DYN_GFX_CLK_OFF_EN (1 << 10) | |
1252 | # define VDDC3D_TURNOFF_D1 (1 << 11) | |
1253 | # define VDDC3D_TURNOFF_D2 (1 << 12) | |
1254 | # define VDDC3D_TURNOFF_D3 (1 << 13) | |
1255 | # define SPLL_TURNOFF_D2 (1 << 14) | |
1256 | # define SCLK_LOW_D1 (1 << 15) | |
1257 | # define DYN_GFX_CLK_OFF_MC_EN (1 << 16) | |
1258 | #define MCLK_PWRMGT_CNTL 0x624 | |
1259 | # define MPLL_PWRMGT_OFF (1 << 0) | |
1260 | # define YCLK_TURNOFF (1 << 1) | |
1261 | # define MPLL_TURNOFF (1 << 2) | |
1262 | # define SU_MCLK_USE_BCLK (1 << 3) | |
1263 | # define DLL_READY (1 << 4) | |
1264 | # define MC_BUSY (1 << 5) | |
1265 | # define MC_INT_CNTL (1 << 7) | |
1266 | # define MRDCKA_SLEEP (1 << 8) | |
1267 | # define MRDCKB_SLEEP (1 << 9) | |
1268 | # define MRDCKC_SLEEP (1 << 10) | |
1269 | # define MRDCKD_SLEEP (1 << 11) | |
1270 | # define MRDCKE_SLEEP (1 << 12) | |
1271 | # define MRDCKF_SLEEP (1 << 13) | |
1272 | # define MRDCKG_SLEEP (1 << 14) | |
1273 | # define MRDCKH_SLEEP (1 << 15) | |
1274 | # define MRDCKA_RESET (1 << 16) | |
1275 | # define MRDCKB_RESET (1 << 17) | |
1276 | # define MRDCKC_RESET (1 << 18) | |
1277 | # define MRDCKD_RESET (1 << 19) | |
1278 | # define MRDCKE_RESET (1 << 20) | |
1279 | # define MRDCKF_RESET (1 << 21) | |
1280 | # define MRDCKG_RESET (1 << 22) | |
1281 | # define MRDCKH_RESET (1 << 23) | |
1282 | # define DLL_READY_READ (1 << 24) | |
1283 | # define USE_DISPLAY_GAP (1 << 25) | |
1284 | # define USE_DISPLAY_URGENT_NORMAL (1 << 26) | |
1285 | # define USE_DISPLAY_GAP_CTXSW (1 << 27) | |
1286 | # define MPLL_TURNOFF_D2 (1 << 28) | |
1287 | # define USE_DISPLAY_URGENT_CTXSW (1 << 29) | |
1288 | ||
1289 | #define MPLL_TIME 0x634 | |
1290 | # define MPLL_LOCK_TIME(x) ((x) << 0) | |
1291 | # define MPLL_LOCK_TIME_MASK (0xffff << 0) | |
1292 | # define MPLL_RESET_TIME(x) ((x) << 16) | |
1293 | # define MPLL_RESET_TIME_MASK (0xffff << 16) | |
1294 | ||
1295 | #define SCLK_FREQ_SETTING_STEP_0_PART1 0x648 | |
1296 | # define STEP_0_SPLL_POST_DIV(x) ((x) << 0) | |
1297 | # define STEP_0_SPLL_POST_DIV_MASK (0xff << 0) | |
1298 | # define STEP_0_SPLL_FB_DIV(x) ((x) << 8) | |
1299 | # define STEP_0_SPLL_FB_DIV_MASK (0xff << 8) | |
1300 | # define STEP_0_SPLL_REF_DIV(x) ((x) << 16) | |
1301 | # define STEP_0_SPLL_REF_DIV_MASK (7 << 16) | |
1302 | # define STEP_0_SPLL_STEP_TIME(x) ((x) << 19) | |
1303 | # define STEP_0_SPLL_STEP_TIME_MASK (0x1fff << 19) | |
1304 | #define SCLK_FREQ_SETTING_STEP_0_PART2 0x64c | |
1305 | # define STEP_0_PULSE_HIGH_CNT(x) ((x) << 0) | |
1306 | # define STEP_0_PULSE_HIGH_CNT_MASK (0x1ff << 0) | |
1307 | # define STEP_0_POST_DIV_EN (1 << 9) | |
1308 | # define STEP_0_SPLL_STEP_ENABLE (1 << 30) | |
1309 | # define STEP_0_SPLL_ENTRY_VALID (1 << 31) | |
1310 | ||
1311 | #define VID_RT 0x6f8 | |
1312 | # define VID_CRT(x) ((x) << 0) | |
1313 | # define VID_CRT_MASK (0x1fff << 0) | |
1314 | # define VID_CRTU(x) ((x) << 13) | |
1315 | # define VID_CRTU_MASK (7 << 13) | |
1316 | # define SSTU(x) ((x) << 16) | |
1317 | # define SSTU_MASK (7 << 16) | |
1318 | #define CTXSW_PROFILE_INDEX 0x6fc | |
1319 | # define CTXSW_FREQ_VIDS_CFG_INDEX(x) ((x) << 0) | |
1320 | # define CTXSW_FREQ_VIDS_CFG_INDEX_MASK (3 << 0) | |
1321 | # define CTXSW_FREQ_VIDS_CFG_INDEX_SHIFT 0 | |
1322 | # define CTXSW_FREQ_MCLK_CFG_INDEX(x) ((x) << 2) | |
1323 | # define CTXSW_FREQ_MCLK_CFG_INDEX_MASK (3 << 2) | |
1324 | # define CTXSW_FREQ_MCLK_CFG_INDEX_SHIFT 2 | |
1325 | # define CTXSW_FREQ_SCLK_CFG_INDEX(x) ((x) << 4) | |
1326 | # define CTXSW_FREQ_SCLK_CFG_INDEX_MASK (0x1f << 4) | |
1327 | # define CTXSW_FREQ_SCLK_CFG_INDEX_SHIFT 4 | |
1328 | # define CTXSW_FREQ_STATE_SPLL_RESET_EN (1 << 9) | |
1329 | # define CTXSW_FREQ_STATE_ENABLE (1 << 10) | |
1330 | # define CTXSW_FREQ_DISPLAY_WATERMARK (1 << 11) | |
1331 | # define CTXSW_FREQ_GEN2PCIE_VOLT (1 << 12) | |
1332 | ||
1333 | #define TARGET_AND_CURRENT_PROFILE_INDEX 0x70c | |
1334 | # define TARGET_PROFILE_INDEX_MASK (3 << 0) | |
1335 | # define TARGET_PROFILE_INDEX_SHIFT 0 | |
1336 | # define CURRENT_PROFILE_INDEX_MASK (3 << 2) | |
1337 | # define CURRENT_PROFILE_INDEX_SHIFT 2 | |
1338 | # define DYN_PWR_ENTER_INDEX(x) ((x) << 4) | |
1339 | # define DYN_PWR_ENTER_INDEX_MASK (3 << 4) | |
1340 | # define DYN_PWR_ENTER_INDEX_SHIFT 4 | |
1341 | # define CURR_MCLK_INDEX_MASK (3 << 6) | |
1342 | # define CURR_MCLK_INDEX_SHIFT 6 | |
1343 | # define CURR_SCLK_INDEX_MASK (0x1f << 8) | |
1344 | # define CURR_SCLK_INDEX_SHIFT 8 | |
1345 | # define CURR_VID_INDEX_MASK (3 << 13) | |
1346 | # define CURR_VID_INDEX_SHIFT 13 | |
1347 | ||
1348 | #define LOWER_GPIO_ENABLE 0x710 | |
1349 | #define UPPER_GPIO_ENABLE 0x714 | |
1350 | #define CTXSW_VID_LOWER_GPIO_CNTL 0x718 | |
1351 | ||
1352 | #define VID_UPPER_GPIO_CNTL 0x740 | |
1353 | #define CG_CTX_CGTT3D_R 0x744 | |
1354 | # define PHC(x) ((x) << 0) | |
1355 | # define PHC_MASK (0x1ff << 0) | |
1356 | # define SDC(x) ((x) << 9) | |
1357 | # define SDC_MASK (0x3fff << 9) | |
1358 | #define CG_VDDC3D_OOR 0x748 | |
1359 | # define SU(x) ((x) << 23) | |
1360 | # define SU_MASK (0xf << 23) | |
1361 | #define CG_FTV 0x74c | |
1362 | #define CG_FFCT_0 0x750 | |
1363 | # define UTC_0(x) ((x) << 0) | |
1364 | # define UTC_0_MASK (0x3ff << 0) | |
1365 | # define DTC_0(x) ((x) << 10) | |
1366 | # define DTC_0_MASK (0x3ff << 10) | |
1367 | ||
1368 | #define CG_BSP 0x78c | |
1369 | # define BSP(x) ((x) << 0) | |
1370 | # define BSP_MASK (0xffff << 0) | |
1371 | # define BSU(x) ((x) << 16) | |
1372 | # define BSU_MASK (0xf << 16) | |
1373 | #define CG_RT 0x790 | |
1374 | # define FLS(x) ((x) << 0) | |
1375 | # define FLS_MASK (0xffff << 0) | |
1376 | # define FMS(x) ((x) << 16) | |
1377 | # define FMS_MASK (0xffff << 16) | |
1378 | #define CG_LT 0x794 | |
1379 | # define FHS(x) ((x) << 0) | |
1380 | # define FHS_MASK (0xffff << 0) | |
1381 | #define CG_GIT 0x798 | |
1382 | # define CG_GICST(x) ((x) << 0) | |
1383 | # define CG_GICST_MASK (0xffff << 0) | |
1384 | # define CG_GIPOT(x) ((x) << 16) | |
1385 | # define CG_GIPOT_MASK (0xffff << 16) | |
1386 | ||
1387 | #define CG_SSP 0x7a8 | |
1388 | # define CG_SST(x) ((x) << 0) | |
1389 | # define CG_SST_MASK (0xffff << 0) | |
1390 | # define CG_SSTU(x) ((x) << 16) | |
1391 | # define CG_SSTU_MASK (0xf << 16) | |
1392 | ||
1393 | #define CG_RLC_REQ_AND_RSP 0x7c4 | |
1394 | # define RLC_CG_REQ_TYPE_MASK 0xf | |
1395 | # define RLC_CG_REQ_TYPE_SHIFT 0 | |
1396 | # define CG_RLC_RSP_TYPE_MASK 0xf0 | |
1397 | # define CG_RLC_RSP_TYPE_SHIFT 4 | |
1398 | ||
1399 | #define CG_FC_T 0x7cc | |
1400 | # define FC_T(x) ((x) << 0) | |
1401 | # define FC_T_MASK (0xffff << 0) | |
1402 | # define FC_TU(x) ((x) << 16) | |
1403 | # define FC_TU_MASK (0x1f << 16) | |
1404 | ||
1405 | #define GPIOPAD_MASK 0x1798 | |
1406 | #define GPIOPAD_A 0x179c | |
1407 | #define GPIOPAD_EN 0x17a0 | |
1408 | ||
1409 | #define GRBM_PWR_CNTL 0x800c | |
1410 | # define REQ_TYPE_MASK 0xf | |
1411 | # define REQ_TYPE_SHIFT 0 | |
1412 | # define RSP_TYPE_MASK 0xf0 | |
1413 | # define RSP_TYPE_SHIFT 4 | |
1414 | ||
f2ba57b5 CK |
1415 | /* |
1416 | * UVD | |
1417 | */ | |
1418 | #define UVD_SEMA_ADDR_LOW 0xef00 | |
1419 | #define UVD_SEMA_ADDR_HIGH 0xef04 | |
1420 | #define UVD_SEMA_CMD 0xef08 | |
1421 | ||
1422 | #define UVD_GPCOM_VCPU_CMD 0xef0c | |
1423 | #define UVD_GPCOM_VCPU_DATA0 0xef10 | |
1424 | #define UVD_GPCOM_VCPU_DATA1 0xef14 | |
1425 | #define UVD_ENGINE_CNTL 0xef18 | |
1426 | ||
1427 | #define UVD_SEMA_CNTL 0xf400 | |
1428 | #define UVD_RB_ARB_CTRL 0xf480 | |
1429 | ||
1430 | #define UVD_LMI_EXT40_ADDR 0xf498 | |
1431 | #define UVD_CGC_GATE 0xf4a8 | |
1432 | #define UVD_LMI_CTRL2 0xf4f4 | |
1433 | #define UVD_MASTINT_EN 0xf500 | |
1434 | #define UVD_LMI_ADDR_EXT 0xf594 | |
1435 | #define UVD_LMI_CTRL 0xf598 | |
1436 | #define UVD_LMI_SWAP_CNTL 0xf5b4 | |
1437 | #define UVD_MP_SWAP_CNTL 0xf5bC | |
1438 | #define UVD_MPC_CNTL 0xf5dC | |
1439 | #define UVD_MPC_SET_MUXA0 0xf5e4 | |
1440 | #define UVD_MPC_SET_MUXA1 0xf5e8 | |
1441 | #define UVD_MPC_SET_MUXB0 0xf5eC | |
1442 | #define UVD_MPC_SET_MUXB1 0xf5f0 | |
1443 | #define UVD_MPC_SET_MUX 0xf5f4 | |
1444 | #define UVD_MPC_SET_ALU 0xf5f8 | |
1445 | ||
1446 | #define UVD_VCPU_CNTL 0xf660 | |
1447 | #define UVD_SOFT_RESET 0xf680 | |
1448 | #define RBC_SOFT_RESET (1<<0) | |
1449 | #define LBSI_SOFT_RESET (1<<1) | |
1450 | #define LMI_SOFT_RESET (1<<2) | |
1451 | #define VCPU_SOFT_RESET (1<<3) | |
1452 | #define CSM_SOFT_RESET (1<<5) | |
1453 | #define CXW_SOFT_RESET (1<<6) | |
1454 | #define TAP_SOFT_RESET (1<<7) | |
1455 | #define LMI_UMC_SOFT_RESET (1<<13) | |
1456 | #define UVD_RBC_IB_BASE 0xf684 | |
1457 | #define UVD_RBC_IB_SIZE 0xf688 | |
1458 | #define UVD_RBC_RB_BASE 0xf68c | |
1459 | #define UVD_RBC_RB_RPTR 0xf690 | |
1460 | #define UVD_RBC_RB_WPTR 0xf694 | |
1461 | #define UVD_RBC_RB_WPTR_CNTL 0xf698 | |
1462 | ||
1463 | #define UVD_STATUS 0xf6bc | |
1464 | ||
1465 | #define UVD_SEMA_TIMEOUT_STATUS 0xf6c0 | |
1466 | #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0xf6c4 | |
1467 | #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0xf6c8 | |
1468 | #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0xf6cc | |
1469 | ||
1470 | #define UVD_RBC_RB_CNTL 0xf6a4 | |
1471 | #define UVD_RBC_RB_RPTR_ADDR 0xf6a8 | |
1472 | ||
1473 | #define UVD_CONTEXT_ID 0xf6f4 | |
1474 | ||
facd112d CK |
1475 | # define UPLL_CTLREQ_MASK 0x00000008 |
1476 | # define UPLL_CTLACK_MASK 0x40000000 | |
1477 | # define UPLL_CTLACK2_MASK 0x80000000 | |
1478 | ||
3ce0a23d JG |
1479 | /* |
1480 | * PM4 | |
1481 | */ | |
4e872ae2 | 1482 | #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ |
3ce0a23d JG |
1483 | (((reg) >> 2) & 0xFFFF) | \ |
1484 | ((n) & 0x3FFF) << 16) | |
4e872ae2 | 1485 | #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ |
3ce0a23d JG |
1486 | (((op) & 0xFF) << 8) | \ |
1487 | ((n) & 0x3FFF) << 16) | |
1488 | ||
1489 | /* Packet 3 types */ | |
1490 | #define PACKET3_NOP 0x10 | |
1491 | #define PACKET3_INDIRECT_BUFFER_END 0x17 | |
1492 | #define PACKET3_SET_PREDICATION 0x20 | |
1493 | #define PACKET3_REG_RMW 0x21 | |
1494 | #define PACKET3_COND_EXEC 0x22 | |
1495 | #define PACKET3_PRED_EXEC 0x23 | |
1496 | #define PACKET3_START_3D_CMDBUF 0x24 | |
1497 | #define PACKET3_DRAW_INDEX_2 0x27 | |
1498 | #define PACKET3_CONTEXT_CONTROL 0x28 | |
1499 | #define PACKET3_DRAW_INDEX_IMMD_BE 0x29 | |
1500 | #define PACKET3_INDEX_TYPE 0x2A | |
1501 | #define PACKET3_DRAW_INDEX 0x2B | |
1502 | #define PACKET3_DRAW_INDEX_AUTO 0x2D | |
1503 | #define PACKET3_DRAW_INDEX_IMMD 0x2E | |
1504 | #define PACKET3_NUM_INSTANCES 0x2F | |
1505 | #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 | |
1506 | #define PACKET3_INDIRECT_BUFFER_MP 0x38 | |
1507 | #define PACKET3_MEM_SEMAPHORE 0x39 | |
0be70439 | 1508 | # define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) |
15d3332f CK |
1509 | # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) |
1510 | # define PACKET3_SEM_SEL_WAIT (0x7 << 29) | |
3ce0a23d | 1511 | #define PACKET3_MPEG_INDEX 0x3A |
dd220a00 | 1512 | #define PACKET3_COPY_DW 0x3B |
3ce0a23d JG |
1513 | #define PACKET3_WAIT_REG_MEM 0x3C |
1514 | #define PACKET3_MEM_WRITE 0x3D | |
1515 | #define PACKET3_INDIRECT_BUFFER 0x32 | |
b997a8ba AD |
1516 | #define PACKET3_CP_DMA 0x41 |
1517 | /* 1. header | |
1518 | * 2. SRC_ADDR_LO [31:0] | |
1519 | * 3. CP_SYNC [31] | SRC_ADDR_HI [7:0] | |
1520 | * 4. DST_ADDR_LO [31:0] | |
1521 | * 5. DST_ADDR_HI [7:0] | |
1522 | * 6. COMMAND [29:22] | BYTE_COUNT [20:0] | |
1523 | */ | |
1524 | # define PACKET3_CP_DMA_CP_SYNC (1 << 31) | |
1525 | /* COMMAND */ | |
1526 | # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) | |
1527 | /* 0 - none | |
1528 | * 1 - 8 in 16 | |
1529 | * 2 - 8 in 32 | |
1530 | * 3 - 8 in 64 | |
1531 | */ | |
1532 | # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) | |
1533 | /* 0 - none | |
1534 | * 1 - 8 in 16 | |
1535 | * 2 - 8 in 32 | |
1536 | * 3 - 8 in 64 | |
1537 | */ | |
1538 | # define PACKET3_CP_DMA_CMD_SAS (1 << 26) | |
1539 | /* 0 - memory | |
1540 | * 1 - register | |
1541 | */ | |
1542 | # define PACKET3_CP_DMA_CMD_DAS (1 << 27) | |
1543 | /* 0 - memory | |
1544 | * 1 - register | |
1545 | */ | |
1546 | # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) | |
1547 | # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) | |
3ce0a23d JG |
1548 | #define PACKET3_SURFACE_SYNC 0x43 |
1549 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) | |
1550 | # define PACKET3_TC_ACTION_ENA (1 << 23) | |
1551 | # define PACKET3_VC_ACTION_ENA (1 << 24) | |
1552 | # define PACKET3_CB_ACTION_ENA (1 << 25) | |
1553 | # define PACKET3_DB_ACTION_ENA (1 << 26) | |
1554 | # define PACKET3_SH_ACTION_ENA (1 << 27) | |
1555 | # define PACKET3_SMX_ACTION_ENA (1 << 28) | |
1556 | #define PACKET3_ME_INITIALIZE 0x44 | |
1557 | #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) | |
1558 | #define PACKET3_COND_WRITE 0x45 | |
1559 | #define PACKET3_EVENT_WRITE 0x46 | |
d0f8a854 AD |
1560 | #define EVENT_TYPE(x) ((x) << 0) |
1561 | #define EVENT_INDEX(x) ((x) << 8) | |
1562 | /* 0 - any non-TS event | |
1563 | * 1 - ZPASS_DONE | |
1564 | * 2 - SAMPLE_PIPELINESTAT | |
1565 | * 3 - SAMPLE_STREAMOUTSTAT* | |
1566 | * 4 - *S_PARTIAL_FLUSH | |
1567 | * 5 - TS events | |
1568 | */ | |
3ce0a23d | 1569 | #define PACKET3_EVENT_WRITE_EOP 0x47 |
d0f8a854 AD |
1570 | #define DATA_SEL(x) ((x) << 29) |
1571 | /* 0 - discard | |
1572 | * 1 - send low 32bit data | |
1573 | * 2 - send 64bit data | |
1574 | * 3 - send 64bit counter value | |
1575 | */ | |
1576 | #define INT_SEL(x) ((x) << 24) | |
1577 | /* 0 - none | |
1578 | * 1 - interrupt only (DATA_SEL = 0) | |
1579 | * 2 - interrupt when data write is confirmed | |
1580 | */ | |
3ce0a23d JG |
1581 | #define PACKET3_ONE_REG_WRITE 0x57 |
1582 | #define PACKET3_SET_CONFIG_REG 0x68 | |
1583 | #define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000 | |
1584 | #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 | |
1585 | #define PACKET3_SET_CONTEXT_REG 0x69 | |
1586 | #define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000 | |
1587 | #define PACKET3_SET_CONTEXT_REG_END 0x00029000 | |
1588 | #define PACKET3_SET_ALU_CONST 0x6A | |
1589 | #define PACKET3_SET_ALU_CONST_OFFSET 0x00030000 | |
1590 | #define PACKET3_SET_ALU_CONST_END 0x00032000 | |
1591 | #define PACKET3_SET_BOOL_CONST 0x6B | |
1592 | #define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380 | |
1593 | #define PACKET3_SET_BOOL_CONST_END 0x00040000 | |
1594 | #define PACKET3_SET_LOOP_CONST 0x6C | |
1595 | #define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200 | |
1596 | #define PACKET3_SET_LOOP_CONST_END 0x0003e380 | |
1597 | #define PACKET3_SET_RESOURCE 0x6D | |
1598 | #define PACKET3_SET_RESOURCE_OFFSET 0x00038000 | |
1599 | #define PACKET3_SET_RESOURCE_END 0x0003c000 | |
1600 | #define PACKET3_SET_SAMPLER 0x6E | |
1601 | #define PACKET3_SET_SAMPLER_OFFSET 0x0003c000 | |
1602 | #define PACKET3_SET_SAMPLER_END 0x0003cff0 | |
1603 | #define PACKET3_SET_CTL_CONST 0x6F | |
1604 | #define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0 | |
1605 | #define PACKET3_SET_CTL_CONST_END 0x0003e200 | |
7c77bf2a | 1606 | #define PACKET3_STRMOUT_BASE_UPDATE 0x72 /* r7xx */ |
3ce0a23d JG |
1607 | #define PACKET3_SURFACE_BASE_UPDATE 0x73 |
1608 | ||
65337e60 SL |
1609 | #define R_000011_K8_FB_LOCATION 0x11 |
1610 | #define R_000012_MC_MISC_UMA_CNTL 0x12 | |
1611 | #define G_000012_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF) | |
1612 | #define R_0028F8_MC_INDEX 0x28F8 | |
1613 | #define S_0028F8_MC_IND_ADDR(x) (((x) & 0x1FF) << 0) | |
1614 | #define C_0028F8_MC_IND_ADDR 0xFFFFFE00 | |
1615 | #define S_0028F8_MC_IND_WR_EN(x) (((x) & 0x1) << 9) | |
1616 | #define R_0028FC_MC_DATA 0x28FC | |
3ce0a23d JG |
1617 | |
1618 | #define R_008020_GRBM_SOFT_RESET 0x8020 | |
1619 | #define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0) | |
1620 | #define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1) | |
1621 | #define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2) | |
1622 | #define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3) | |
1623 | #define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5) | |
1624 | #define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6) | |
1625 | #define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7) | |
1626 | #define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8) | |
1627 | #define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9) | |
1628 | #define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10) | |
1629 | #define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11) | |
1630 | #define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12) | |
1631 | #define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13) | |
1632 | #define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14) | |
1633 | #define R_008010_GRBM_STATUS 0x8010 | |
1634 | #define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0) | |
1635 | #define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6) | |
1636 | #define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7) | |
1637 | #define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8) | |
1638 | #define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10) | |
1639 | #define S_008010_VC_BUSY(x) (((x) & 1) << 11) | |
1640 | #define S_008010_DB03_CLEAN(x) (((x) & 1) << 12) | |
1641 | #define S_008010_CB03_CLEAN(x) (((x) & 1) << 13) | |
1642 | #define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16) | |
1643 | #define S_008010_VGT_BUSY(x) (((x) & 1) << 17) | |
1644 | #define S_008010_TA03_BUSY(x) (((x) & 1) << 18) | |
1645 | #define S_008010_TC_BUSY(x) (((x) & 1) << 19) | |
1646 | #define S_008010_SX_BUSY(x) (((x) & 1) << 20) | |
1647 | #define S_008010_SH_BUSY(x) (((x) & 1) << 21) | |
1648 | #define S_008010_SPI03_BUSY(x) (((x) & 1) << 22) | |
1649 | #define S_008010_SMX_BUSY(x) (((x) & 1) << 23) | |
1650 | #define S_008010_SC_BUSY(x) (((x) & 1) << 24) | |
1651 | #define S_008010_PA_BUSY(x) (((x) & 1) << 25) | |
1652 | #define S_008010_DB03_BUSY(x) (((x) & 1) << 26) | |
1653 | #define S_008010_CR_BUSY(x) (((x) & 1) << 27) | |
1654 | #define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28) | |
1655 | #define S_008010_CP_BUSY(x) (((x) & 1) << 29) | |
1656 | #define S_008010_CB03_BUSY(x) (((x) & 1) << 30) | |
1657 | #define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31) | |
1658 | #define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F) | |
1659 | #define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1) | |
1660 | #define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1) | |
1661 | #define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1) | |
1662 | #define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1) | |
1663 | #define G_008010_VC_BUSY(x) (((x) >> 11) & 1) | |
1664 | #define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1) | |
1665 | #define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1) | |
f13f7731 | 1666 | #define G_008010_TA_BUSY(x) (((x) >> 14) & 1) |
3ce0a23d JG |
1667 | #define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1) |
1668 | #define G_008010_VGT_BUSY(x) (((x) >> 17) & 1) | |
1669 | #define G_008010_TA03_BUSY(x) (((x) >> 18) & 1) | |
1670 | #define G_008010_TC_BUSY(x) (((x) >> 19) & 1) | |
1671 | #define G_008010_SX_BUSY(x) (((x) >> 20) & 1) | |
1672 | #define G_008010_SH_BUSY(x) (((x) >> 21) & 1) | |
1673 | #define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1) | |
1674 | #define G_008010_SMX_BUSY(x) (((x) >> 23) & 1) | |
1675 | #define G_008010_SC_BUSY(x) (((x) >> 24) & 1) | |
1676 | #define G_008010_PA_BUSY(x) (((x) >> 25) & 1) | |
1677 | #define G_008010_DB03_BUSY(x) (((x) >> 26) & 1) | |
1678 | #define G_008010_CR_BUSY(x) (((x) >> 27) & 1) | |
1679 | #define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1) | |
1680 | #define G_008010_CP_BUSY(x) (((x) >> 29) & 1) | |
1681 | #define G_008010_CB03_BUSY(x) (((x) >> 30) & 1) | |
1682 | #define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1) | |
1683 | #define R_008014_GRBM_STATUS2 0x8014 | |
1684 | #define S_008014_CR_CLEAN(x) (((x) & 1) << 0) | |
1685 | #define S_008014_SMX_CLEAN(x) (((x) & 1) << 1) | |
1686 | #define S_008014_SPI0_BUSY(x) (((x) & 1) << 8) | |
1687 | #define S_008014_SPI1_BUSY(x) (((x) & 1) << 9) | |
1688 | #define S_008014_SPI2_BUSY(x) (((x) & 1) << 10) | |
1689 | #define S_008014_SPI3_BUSY(x) (((x) & 1) << 11) | |
1690 | #define S_008014_TA0_BUSY(x) (((x) & 1) << 12) | |
1691 | #define S_008014_TA1_BUSY(x) (((x) & 1) << 13) | |
1692 | #define S_008014_TA2_BUSY(x) (((x) & 1) << 14) | |
1693 | #define S_008014_TA3_BUSY(x) (((x) & 1) << 15) | |
1694 | #define S_008014_DB0_BUSY(x) (((x) & 1) << 16) | |
1695 | #define S_008014_DB1_BUSY(x) (((x) & 1) << 17) | |
1696 | #define S_008014_DB2_BUSY(x) (((x) & 1) << 18) | |
1697 | #define S_008014_DB3_BUSY(x) (((x) & 1) << 19) | |
1698 | #define S_008014_CB0_BUSY(x) (((x) & 1) << 20) | |
1699 | #define S_008014_CB1_BUSY(x) (((x) & 1) << 21) | |
1700 | #define S_008014_CB2_BUSY(x) (((x) & 1) << 22) | |
1701 | #define S_008014_CB3_BUSY(x) (((x) & 1) << 23) | |
1702 | #define G_008014_CR_CLEAN(x) (((x) >> 0) & 1) | |
1703 | #define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1) | |
1704 | #define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1) | |
1705 | #define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1) | |
1706 | #define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1) | |
1707 | #define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1) | |
1708 | #define G_008014_TA0_BUSY(x) (((x) >> 12) & 1) | |
1709 | #define G_008014_TA1_BUSY(x) (((x) >> 13) & 1) | |
1710 | #define G_008014_TA2_BUSY(x) (((x) >> 14) & 1) | |
1711 | #define G_008014_TA3_BUSY(x) (((x) >> 15) & 1) | |
1712 | #define G_008014_DB0_BUSY(x) (((x) >> 16) & 1) | |
1713 | #define G_008014_DB1_BUSY(x) (((x) >> 17) & 1) | |
1714 | #define G_008014_DB2_BUSY(x) (((x) >> 18) & 1) | |
1715 | #define G_008014_DB3_BUSY(x) (((x) >> 19) & 1) | |
1716 | #define G_008014_CB0_BUSY(x) (((x) >> 20) & 1) | |
1717 | #define G_008014_CB1_BUSY(x) (((x) >> 21) & 1) | |
1718 | #define G_008014_CB2_BUSY(x) (((x) >> 22) & 1) | |
1719 | #define G_008014_CB3_BUSY(x) (((x) >> 23) & 1) | |
1720 | #define R_000E50_SRBM_STATUS 0x0E50 | |
1721 | #define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1) | |
1722 | #define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1) | |
1723 | #define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1) | |
1724 | #define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1) | |
1725 | #define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1) | |
1726 | #define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1) | |
1727 | #define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1) | |
1728 | #define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1) | |
1729 | #define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1) | |
1730 | #define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1) | |
1731 | #define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1) | |
1732 | #define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1) | |
1733 | #define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1) | |
f13f7731 | 1734 | #define G_000E50_IH_BUSY(x) (((x) >> 17) & 1) |
1a029b76 | 1735 | #define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1) |
3ce0a23d JG |
1736 | #define R_000E60_SRBM_SOFT_RESET 0x0E60 |
1737 | #define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1) | |
1738 | #define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2) | |
1739 | #define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3) | |
1740 | #define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4) | |
1741 | #define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5) | |
1742 | #define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8) | |
1743 | #define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9) | |
1744 | #define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10) | |
1745 | #define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11) | |
1746 | #define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13) | |
1747 | #define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14) | |
1748 | #define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15) | |
1749 | #define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16) | |
1750 | #define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17) | |
1751 | ||
23956dfa | 1752 | #define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 |
c8c15ff1 | 1753 | |
961fb597 JG |
1754 | #define R_028C04_PA_SC_AA_CONFIG 0x028C04 |
1755 | #define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0) | |
1756 | #define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3) | |
1757 | #define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC | |
1758 | #define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4) | |
1759 | #define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1) | |
1760 | #define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF | |
1761 | #define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13) | |
1762 | #define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF) | |
1763 | #define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF | |
c8c15ff1 JG |
1764 | #define R_0280E0_CB_COLOR0_FRAG 0x0280E0 |
1765 | #define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) | |
1766 | #define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) | |
1767 | #define C_0280E0_BASE_256B 0x00000000 | |
1768 | #define R_0280E4_CB_COLOR1_FRAG 0x0280E4 | |
1769 | #define R_0280E8_CB_COLOR2_FRAG 0x0280E8 | |
1770 | #define R_0280EC_CB_COLOR3_FRAG 0x0280EC | |
1771 | #define R_0280F0_CB_COLOR4_FRAG 0x0280F0 | |
1772 | #define R_0280F4_CB_COLOR5_FRAG 0x0280F4 | |
1773 | #define R_0280F8_CB_COLOR6_FRAG 0x0280F8 | |
1774 | #define R_0280FC_CB_COLOR7_FRAG 0x0280FC | |
1775 | #define R_0280C0_CB_COLOR0_TILE 0x0280C0 | |
1776 | #define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) | |
1777 | #define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) | |
1778 | #define C_0280C0_BASE_256B 0x00000000 | |
1779 | #define R_0280C4_CB_COLOR1_TILE 0x0280C4 | |
1780 | #define R_0280C8_CB_COLOR2_TILE 0x0280C8 | |
1781 | #define R_0280CC_CB_COLOR3_TILE 0x0280CC | |
1782 | #define R_0280D0_CB_COLOR4_TILE 0x0280D0 | |
1783 | #define R_0280D4_CB_COLOR5_TILE 0x0280D4 | |
1784 | #define R_0280D8_CB_COLOR6_TILE 0x0280D8 | |
1785 | #define R_0280DC_CB_COLOR7_TILE 0x0280DC | |
961fb597 JG |
1786 | #define R_0280A0_CB_COLOR0_INFO 0x0280A0 |
1787 | #define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0) | |
1788 | #define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3) | |
1789 | #define C_0280A0_ENDIAN 0xFFFFFFFC | |
1790 | #define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2) | |
1791 | #define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F) | |
1792 | #define C_0280A0_FORMAT 0xFFFFFF03 | |
1793 | #define V_0280A0_COLOR_INVALID 0x00000000 | |
1794 | #define V_0280A0_COLOR_8 0x00000001 | |
1795 | #define V_0280A0_COLOR_4_4 0x00000002 | |
1796 | #define V_0280A0_COLOR_3_3_2 0x00000003 | |
1797 | #define V_0280A0_COLOR_16 0x00000005 | |
1798 | #define V_0280A0_COLOR_16_FLOAT 0x00000006 | |
1799 | #define V_0280A0_COLOR_8_8 0x00000007 | |
1800 | #define V_0280A0_COLOR_5_6_5 0x00000008 | |
1801 | #define V_0280A0_COLOR_6_5_5 0x00000009 | |
1802 | #define V_0280A0_COLOR_1_5_5_5 0x0000000A | |
1803 | #define V_0280A0_COLOR_4_4_4_4 0x0000000B | |
1804 | #define V_0280A0_COLOR_5_5_5_1 0x0000000C | |
1805 | #define V_0280A0_COLOR_32 0x0000000D | |
1806 | #define V_0280A0_COLOR_32_FLOAT 0x0000000E | |
1807 | #define V_0280A0_COLOR_16_16 0x0000000F | |
1808 | #define V_0280A0_COLOR_16_16_FLOAT 0x00000010 | |
1809 | #define V_0280A0_COLOR_8_24 0x00000011 | |
1810 | #define V_0280A0_COLOR_8_24_FLOAT 0x00000012 | |
1811 | #define V_0280A0_COLOR_24_8 0x00000013 | |
1812 | #define V_0280A0_COLOR_24_8_FLOAT 0x00000014 | |
1813 | #define V_0280A0_COLOR_10_11_11 0x00000015 | |
1814 | #define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016 | |
1815 | #define V_0280A0_COLOR_11_11_10 0x00000017 | |
1816 | #define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018 | |
1817 | #define V_0280A0_COLOR_2_10_10_10 0x00000019 | |
1818 | #define V_0280A0_COLOR_8_8_8_8 0x0000001A | |
1819 | #define V_0280A0_COLOR_10_10_10_2 0x0000001B | |
1820 | #define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C | |
1821 | #define V_0280A0_COLOR_32_32 0x0000001D | |
1822 | #define V_0280A0_COLOR_32_32_FLOAT 0x0000001E | |
1823 | #define V_0280A0_COLOR_16_16_16_16 0x0000001F | |
1824 | #define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020 | |
1825 | #define V_0280A0_COLOR_32_32_32_32 0x00000022 | |
1826 | #define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023 | |
1827 | #define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8) | |
1828 | #define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF) | |
1829 | #define C_0280A0_ARRAY_MODE 0xFFFFF0FF | |
1830 | #define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000 | |
1831 | #define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001 | |
1832 | #define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002 | |
1833 | #define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004 | |
1834 | #define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12) | |
1835 | #define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7) | |
1836 | #define C_0280A0_NUMBER_TYPE 0xFFFF8FFF | |
1837 | #define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15) | |
1838 | #define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1) | |
1839 | #define C_0280A0_READ_SIZE 0xFFFF7FFF | |
1840 | #define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16) | |
1841 | #define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3) | |
1842 | #define C_0280A0_COMP_SWAP 0xFFFCFFFF | |
1843 | #define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18) | |
1844 | #define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3) | |
1845 | #define C_0280A0_TILE_MODE 0xFFF3FFFF | |
c116cc94 MO |
1846 | #define V_0280A0_TILE_DISABLE 0 |
1847 | #define V_0280A0_CLEAR_ENABLE 1 | |
1848 | #define V_0280A0_FRAG_ENABLE 2 | |
961fb597 JG |
1849 | #define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20) |
1850 | #define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1) | |
1851 | #define C_0280A0_BLEND_CLAMP 0xFFEFFFFF | |
1852 | #define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21) | |
1853 | #define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1) | |
1854 | #define C_0280A0_CLEAR_COLOR 0xFFDFFFFF | |
1855 | #define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22) | |
1856 | #define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1) | |
1857 | #define C_0280A0_BLEND_BYPASS 0xFFBFFFFF | |
1858 | #define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23) | |
1859 | #define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1) | |
1860 | #define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF | |
1861 | #define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24) | |
1862 | #define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1) | |
1863 | #define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF | |
1864 | #define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25) | |
1865 | #define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1) | |
1866 | #define C_0280A0_ROUND_MODE 0xFDFFFFFF | |
1867 | #define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26) | |
1868 | #define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1) | |
1869 | #define C_0280A0_TILE_COMPACT 0xFBFFFFFF | |
1870 | #define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27) | |
1871 | #define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1) | |
1872 | #define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF | |
1873 | #define R_0280A4_CB_COLOR1_INFO 0x0280A4 | |
1874 | #define R_0280A8_CB_COLOR2_INFO 0x0280A8 | |
1875 | #define R_0280AC_CB_COLOR3_INFO 0x0280AC | |
1876 | #define R_0280B0_CB_COLOR4_INFO 0x0280B0 | |
1877 | #define R_0280B4_CB_COLOR5_INFO 0x0280B4 | |
1878 | #define R_0280B8_CB_COLOR6_INFO 0x0280B8 | |
1879 | #define R_0280BC_CB_COLOR7_INFO 0x0280BC | |
1880 | #define R_028060_CB_COLOR0_SIZE 0x028060 | |
1881 | #define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) | |
1882 | #define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) | |
1883 | #define C_028060_PITCH_TILE_MAX 0xFFFFFC00 | |
1884 | #define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) | |
1885 | #define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) | |
1886 | #define C_028060_SLICE_TILE_MAX 0xC00003FF | |
1887 | #define R_028064_CB_COLOR1_SIZE 0x028064 | |
1888 | #define R_028068_CB_COLOR2_SIZE 0x028068 | |
1889 | #define R_02806C_CB_COLOR3_SIZE 0x02806C | |
1890 | #define R_028070_CB_COLOR4_SIZE 0x028070 | |
1891 | #define R_028074_CB_COLOR5_SIZE 0x028074 | |
1892 | #define R_028078_CB_COLOR6_SIZE 0x028078 | |
1893 | #define R_02807C_CB_COLOR7_SIZE 0x02807C | |
1894 | #define R_028238_CB_TARGET_MASK 0x028238 | |
1895 | #define S_028238_TARGET0_ENABLE(x) (((x) & 0xF) << 0) | |
1896 | #define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0xF) | |
1897 | #define C_028238_TARGET0_ENABLE 0xFFFFFFF0 | |
1898 | #define S_028238_TARGET1_ENABLE(x) (((x) & 0xF) << 4) | |
1899 | #define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0xF) | |
1900 | #define C_028238_TARGET1_ENABLE 0xFFFFFF0F | |
1901 | #define S_028238_TARGET2_ENABLE(x) (((x) & 0xF) << 8) | |
1902 | #define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0xF) | |
1903 | #define C_028238_TARGET2_ENABLE 0xFFFFF0FF | |
1904 | #define S_028238_TARGET3_ENABLE(x) (((x) & 0xF) << 12) | |
1905 | #define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0xF) | |
1906 | #define C_028238_TARGET3_ENABLE 0xFFFF0FFF | |
1907 | #define S_028238_TARGET4_ENABLE(x) (((x) & 0xF) << 16) | |
1908 | #define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0xF) | |
1909 | #define C_028238_TARGET4_ENABLE 0xFFF0FFFF | |
1910 | #define S_028238_TARGET5_ENABLE(x) (((x) & 0xF) << 20) | |
1911 | #define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0xF) | |
1912 | #define C_028238_TARGET5_ENABLE 0xFF0FFFFF | |
1913 | #define S_028238_TARGET6_ENABLE(x) (((x) & 0xF) << 24) | |
1914 | #define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0xF) | |
1915 | #define C_028238_TARGET6_ENABLE 0xF0FFFFFF | |
1916 | #define S_028238_TARGET7_ENABLE(x) (((x) & 0xF) << 28) | |
1917 | #define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0xF) | |
1918 | #define C_028238_TARGET7_ENABLE 0x0FFFFFFF | |
1919 | #define R_02823C_CB_SHADER_MASK 0x02823C | |
1920 | #define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0xF) << 0) | |
1921 | #define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0xF) | |
1922 | #define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0 | |
1923 | #define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0xF) << 4) | |
1924 | #define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0xF) | |
1925 | #define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F | |
1926 | #define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0xF) << 8) | |
1927 | #define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0xF) | |
1928 | #define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF | |
1929 | #define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0xF) << 12) | |
1930 | #define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0xF) | |
1931 | #define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF | |
1932 | #define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0xF) << 16) | |
1933 | #define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0xF) | |
1934 | #define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF | |
1935 | #define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0xF) << 20) | |
1936 | #define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0xF) | |
1937 | #define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF | |
1938 | #define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0xF) << 24) | |
1939 | #define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0xF) | |
1940 | #define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF | |
1941 | #define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0xF) << 28) | |
1942 | #define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0xF) | |
1943 | #define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF | |
1944 | #define R_028AB0_VGT_STRMOUT_EN 0x028AB0 | |
1945 | #define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0) | |
1946 | #define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1) | |
1947 | #define C_028AB0_STREAMOUT 0xFFFFFFFE | |
1948 | #define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20 | |
1949 | #define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0) | |
1950 | #define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1) | |
1951 | #define C_028B20_BUFFER_0_EN 0xFFFFFFFE | |
1952 | #define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1) | |
1953 | #define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1) | |
1954 | #define C_028B20_BUFFER_1_EN 0xFFFFFFFD | |
1955 | #define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2) | |
1956 | #define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1) | |
1957 | #define C_028B20_BUFFER_2_EN 0xFFFFFFFB | |
1958 | #define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3) | |
1959 | #define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1) | |
1960 | #define C_028B20_BUFFER_3_EN 0xFFFFFFF7 | |
1961 | #define S_028B20_SIZE(x) (((x) & 0xFFFFFFFF) << 0) | |
1962 | #define G_028B20_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) | |
1963 | #define C_028B20_SIZE 0x00000000 | |
1964 | #define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000 | |
1965 | #define S_038000_DIM(x) (((x) & 0x7) << 0) | |
1966 | #define G_038000_DIM(x) (((x) >> 0) & 0x7) | |
1967 | #define C_038000_DIM 0xFFFFFFF8 | |
1968 | #define V_038000_SQ_TEX_DIM_1D 0x00000000 | |
1969 | #define V_038000_SQ_TEX_DIM_2D 0x00000001 | |
1970 | #define V_038000_SQ_TEX_DIM_3D 0x00000002 | |
1971 | #define V_038000_SQ_TEX_DIM_CUBEMAP 0x00000003 | |
1972 | #define V_038000_SQ_TEX_DIM_1D_ARRAY 0x00000004 | |
1973 | #define V_038000_SQ_TEX_DIM_2D_ARRAY 0x00000005 | |
1974 | #define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006 | |
1975 | #define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 | |
1976 | #define S_038000_TILE_MODE(x) (((x) & 0xF) << 3) | |
1977 | #define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF) | |
1978 | #define C_038000_TILE_MODE 0xFFFFFF87 | |
7f813377 AD |
1979 | #define V_038000_ARRAY_LINEAR_GENERAL 0x00000000 |
1980 | #define V_038000_ARRAY_LINEAR_ALIGNED 0x00000001 | |
1981 | #define V_038000_ARRAY_1D_TILED_THIN1 0x00000002 | |
1982 | #define V_038000_ARRAY_2D_TILED_THIN1 0x00000004 | |
961fb597 JG |
1983 | #define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7) |
1984 | #define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1) | |
1985 | #define C_038000_TILE_TYPE 0xFFFFFF7F | |
1986 | #define S_038000_PITCH(x) (((x) & 0x7FF) << 8) | |
1987 | #define G_038000_PITCH(x) (((x) >> 8) & 0x7FF) | |
1988 | #define C_038000_PITCH 0xFFF800FF | |
1989 | #define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19) | |
1990 | #define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF) | |
1991 | #define C_038000_TEX_WIDTH 0x0007FFFF | |
1992 | #define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004 | |
1993 | #define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0) | |
1994 | #define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF) | |
1995 | #define C_038004_TEX_HEIGHT 0xFFFFE000 | |
1996 | #define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13) | |
1997 | #define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF) | |
1998 | #define C_038004_TEX_DEPTH 0xFC001FFF | |
1999 | #define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26) | |
2000 | #define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F) | |
2001 | #define C_038004_DATA_FORMAT 0x03FFFFFF | |
2002 | #define V_038004_COLOR_INVALID 0x00000000 | |
2003 | #define V_038004_COLOR_8 0x00000001 | |
2004 | #define V_038004_COLOR_4_4 0x00000002 | |
2005 | #define V_038004_COLOR_3_3_2 0x00000003 | |
2006 | #define V_038004_COLOR_16 0x00000005 | |
2007 | #define V_038004_COLOR_16_FLOAT 0x00000006 | |
2008 | #define V_038004_COLOR_8_8 0x00000007 | |
2009 | #define V_038004_COLOR_5_6_5 0x00000008 | |
2010 | #define V_038004_COLOR_6_5_5 0x00000009 | |
2011 | #define V_038004_COLOR_1_5_5_5 0x0000000A | |
2012 | #define V_038004_COLOR_4_4_4_4 0x0000000B | |
2013 | #define V_038004_COLOR_5_5_5_1 0x0000000C | |
2014 | #define V_038004_COLOR_32 0x0000000D | |
2015 | #define V_038004_COLOR_32_FLOAT 0x0000000E | |
2016 | #define V_038004_COLOR_16_16 0x0000000F | |
2017 | #define V_038004_COLOR_16_16_FLOAT 0x00000010 | |
2018 | #define V_038004_COLOR_8_24 0x00000011 | |
2019 | #define V_038004_COLOR_8_24_FLOAT 0x00000012 | |
2020 | #define V_038004_COLOR_24_8 0x00000013 | |
2021 | #define V_038004_COLOR_24_8_FLOAT 0x00000014 | |
2022 | #define V_038004_COLOR_10_11_11 0x00000015 | |
2023 | #define V_038004_COLOR_10_11_11_FLOAT 0x00000016 | |
2024 | #define V_038004_COLOR_11_11_10 0x00000017 | |
2025 | #define V_038004_COLOR_11_11_10_FLOAT 0x00000018 | |
2026 | #define V_038004_COLOR_2_10_10_10 0x00000019 | |
2027 | #define V_038004_COLOR_8_8_8_8 0x0000001A | |
2028 | #define V_038004_COLOR_10_10_10_2 0x0000001B | |
2029 | #define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C | |
2030 | #define V_038004_COLOR_32_32 0x0000001D | |
2031 | #define V_038004_COLOR_32_32_FLOAT 0x0000001E | |
2032 | #define V_038004_COLOR_16_16_16_16 0x0000001F | |
2033 | #define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020 | |
2034 | #define V_038004_COLOR_32_32_32_32 0x00000022 | |
2035 | #define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023 | |
2036 | #define V_038004_FMT_1 0x00000025 | |
2037 | #define V_038004_FMT_GB_GR 0x00000027 | |
2038 | #define V_038004_FMT_BG_RG 0x00000028 | |
2039 | #define V_038004_FMT_32_AS_8 0x00000029 | |
2040 | #define V_038004_FMT_32_AS_8_8 0x0000002A | |
2041 | #define V_038004_FMT_5_9_9_9_SHAREDEXP 0x0000002B | |
2042 | #define V_038004_FMT_8_8_8 0x0000002C | |
2043 | #define V_038004_FMT_16_16_16 0x0000002D | |
2044 | #define V_038004_FMT_16_16_16_FLOAT 0x0000002E | |
2045 | #define V_038004_FMT_32_32_32 0x0000002F | |
2046 | #define V_038004_FMT_32_32_32_FLOAT 0x00000030 | |
60b212f8 DA |
2047 | #define V_038004_FMT_BC1 0x00000031 |
2048 | #define V_038004_FMT_BC2 0x00000032 | |
2049 | #define V_038004_FMT_BC3 0x00000033 | |
2050 | #define V_038004_FMT_BC4 0x00000034 | |
2051 | #define V_038004_FMT_BC5 0x00000035 | |
fe6f0bd0 MO |
2052 | #define V_038004_FMT_BC6 0x00000036 |
2053 | #define V_038004_FMT_BC7 0x00000037 | |
2054 | #define V_038004_FMT_32_AS_32_32_32_32 0x00000038 | |
961fb597 JG |
2055 | #define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010 |
2056 | #define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) | |
2057 | #define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) | |
2058 | #define C_038010_FORMAT_COMP_X 0xFFFFFFFC | |
2059 | #define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) | |
2060 | #define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) | |
2061 | #define C_038010_FORMAT_COMP_Y 0xFFFFFFF3 | |
2062 | #define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) | |
2063 | #define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) | |
2064 | #define C_038010_FORMAT_COMP_Z 0xFFFFFFCF | |
2065 | #define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) | |
2066 | #define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) | |
2067 | #define C_038010_FORMAT_COMP_W 0xFFFFFF3F | |
2068 | #define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) | |
2069 | #define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) | |
2070 | #define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF | |
2071 | #define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) | |
2072 | #define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) | |
2073 | #define C_038010_SRF_MODE_ALL 0xFFFFFBFF | |
2074 | #define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) | |
2075 | #define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) | |
2076 | #define C_038010_FORCE_DEGAMMA 0xFFFFF7FF | |
2077 | #define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) | |
2078 | #define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) | |
2079 | #define C_038010_ENDIAN_SWAP 0xFFFFCFFF | |
2080 | #define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14) | |
2081 | #define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3) | |
2082 | #define C_038010_REQUEST_SIZE 0xFFFF3FFF | |
2083 | #define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16) | |
2084 | #define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7) | |
2085 | #define C_038010_DST_SEL_X 0xFFF8FFFF | |
2086 | #define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19) | |
2087 | #define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7) | |
2088 | #define C_038010_DST_SEL_Y 0xFFC7FFFF | |
2089 | #define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22) | |
2090 | #define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7) | |
2091 | #define C_038010_DST_SEL_Z 0xFE3FFFFF | |
2092 | #define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25) | |
2093 | #define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7) | |
2094 | #define C_038010_DST_SEL_W 0xF1FFFFFF | |
3a38612e IH |
2095 | # define SQ_SEL_X 0 |
2096 | # define SQ_SEL_Y 1 | |
2097 | # define SQ_SEL_Z 2 | |
2098 | # define SQ_SEL_W 3 | |
2099 | # define SQ_SEL_0 4 | |
2100 | # define SQ_SEL_1 5 | |
961fb597 JG |
2101 | #define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28) |
2102 | #define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF) | |
2103 | #define C_038010_BASE_LEVEL 0x0FFFFFFF | |
2104 | #define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014 | |
2105 | #define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0) | |
2106 | #define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF) | |
2107 | #define C_038014_LAST_LEVEL 0xFFFFFFF0 | |
2108 | #define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) | |
2109 | #define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) | |
2110 | #define C_038014_BASE_ARRAY 0xFFFE000F | |
2111 | #define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) | |
2112 | #define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) | |
2113 | #define C_038014_LAST_ARRAY 0xC001FFFF | |
2114 | #define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8 | |
2115 | #define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) | |
2116 | #define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) | |
2117 | #define C_0288A8_ITEMSIZE 0xFFFF8000 | |
2118 | #define R_008C44_SQ_ESGS_RING_SIZE 0x008C44 | |
2119 | #define S_008C44_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) | |
2120 | #define G_008C44_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) | |
2121 | #define C_008C44_MEM_SIZE 0x00000000 | |
2122 | #define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0 | |
2123 | #define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) | |
2124 | #define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) | |
2125 | #define C_0288B0_ITEMSIZE 0xFFFF8000 | |
2126 | #define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54 | |
2127 | #define S_008C54_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) | |
2128 | #define G_008C54_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) | |
2129 | #define C_008C54_MEM_SIZE 0x00000000 | |
2130 | #define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0 | |
2131 | #define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) | |
2132 | #define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) | |
2133 | #define C_0288C0_ITEMSIZE 0xFFFF8000 | |
2134 | #define R_008C74_SQ_FBUF_RING_SIZE 0x008C74 | |
2135 | #define S_008C74_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) | |
2136 | #define G_008C74_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) | |
2137 | #define C_008C74_MEM_SIZE 0x00000000 | |
2138 | #define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4 | |
2139 | #define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) | |
2140 | #define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) | |
2141 | #define C_0288B4_ITEMSIZE 0xFFFF8000 | |
2142 | #define R_008C5C_SQ_GSTMP_RING_SIZE 0x008C5C | |
2143 | #define S_008C5C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) | |
2144 | #define G_008C5C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) | |
2145 | #define C_008C5C_MEM_SIZE 0x00000000 | |
2146 | #define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC | |
2147 | #define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) | |
2148 | #define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) | |
2149 | #define C_0288AC_ITEMSIZE 0xFFFF8000 | |
2150 | #define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C | |
2151 | #define S_008C4C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) | |
2152 | #define G_008C4C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) | |
2153 | #define C_008C4C_MEM_SIZE 0x00000000 | |
2154 | #define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC | |
2155 | #define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) | |
2156 | #define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) | |
2157 | #define C_0288BC_ITEMSIZE 0xFFFF8000 | |
2158 | #define R_008C6C_SQ_PSTMP_RING_SIZE 0x008C6C | |
2159 | #define S_008C6C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) | |
2160 | #define G_008C6C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) | |
2161 | #define C_008C6C_MEM_SIZE 0x00000000 | |
2162 | #define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4 | |
2163 | #define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) | |
2164 | #define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) | |
2165 | #define C_0288C4_ITEMSIZE 0xFFFF8000 | |
2166 | #define R_008C7C_SQ_REDUC_RING_SIZE 0x008C7C | |
2167 | #define S_008C7C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) | |
2168 | #define G_008C7C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) | |
2169 | #define C_008C7C_MEM_SIZE 0x00000000 | |
2170 | #define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8 | |
2171 | #define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) | |
2172 | #define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) | |
2173 | #define C_0288B8_ITEMSIZE 0xFFFF8000 | |
2174 | #define R_008C64_SQ_VSTMP_RING_SIZE 0x008C64 | |
2175 | #define S_008C64_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) | |
2176 | #define G_008C64_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) | |
2177 | #define C_008C64_MEM_SIZE 0x00000000 | |
2178 | #define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8 | |
2179 | #define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) | |
2180 | #define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) | |
2181 | #define C_0288C8_ITEMSIZE 0xFFFF8000 | |
2182 | #define R_028010_DB_DEPTH_INFO 0x028010 | |
2183 | #define S_028010_FORMAT(x) (((x) & 0x7) << 0) | |
2184 | #define G_028010_FORMAT(x) (((x) >> 0) & 0x7) | |
2185 | #define C_028010_FORMAT 0xFFFFFFF8 | |
2186 | #define V_028010_DEPTH_INVALID 0x00000000 | |
2187 | #define V_028010_DEPTH_16 0x00000001 | |
2188 | #define V_028010_DEPTH_X8_24 0x00000002 | |
2189 | #define V_028010_DEPTH_8_24 0x00000003 | |
2190 | #define V_028010_DEPTH_X8_24_FLOAT 0x00000004 | |
2191 | #define V_028010_DEPTH_8_24_FLOAT 0x00000005 | |
2192 | #define V_028010_DEPTH_32_FLOAT 0x00000006 | |
2193 | #define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007 | |
2194 | #define S_028010_READ_SIZE(x) (((x) & 0x1) << 3) | |
2195 | #define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1) | |
2196 | #define C_028010_READ_SIZE 0xFFFFFFF7 | |
2197 | #define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15) | |
2198 | #define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF) | |
2199 | #define C_028010_ARRAY_MODE 0xFFF87FFF | |
7f813377 AD |
2200 | #define V_028010_ARRAY_1D_TILED_THIN1 0x00000002 |
2201 | #define V_028010_ARRAY_2D_TILED_THIN1 0x00000004 | |
961fb597 JG |
2202 | #define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25) |
2203 | #define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1) | |
2204 | #define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF | |
2205 | #define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26) | |
2206 | #define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1) | |
2207 | #define C_028010_TILE_COMPACT 0xFBFFFFFF | |
2208 | #define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) | |
2209 | #define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) | |
2210 | #define C_028010_ZRANGE_PRECISION 0x7FFFFFFF | |
2211 | #define R_028000_DB_DEPTH_SIZE 0x028000 | |
2212 | #define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) | |
2213 | #define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) | |
2214 | #define C_028000_PITCH_TILE_MAX 0xFFFFFC00 | |
2215 | #define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) | |
2216 | #define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) | |
2217 | #define C_028000_SLICE_TILE_MAX 0xC00003FF | |
2218 | #define R_028004_DB_DEPTH_VIEW 0x028004 | |
2219 | #define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0) | |
2220 | #define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF) | |
2221 | #define C_028004_SLICE_START 0xFFFFF800 | |
2222 | #define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13) | |
2223 | #define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF) | |
2224 | #define C_028004_SLICE_MAX 0xFF001FFF | |
2225 | #define R_028800_DB_DEPTH_CONTROL 0x028800 | |
2226 | #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) | |
2227 | #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) | |
2228 | #define C_028800_STENCIL_ENABLE 0xFFFFFFFE | |
2229 | #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) | |
2230 | #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) | |
2231 | #define C_028800_Z_ENABLE 0xFFFFFFFD | |
2232 | #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) | |
2233 | #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) | |
2234 | #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB | |
2235 | #define S_028800_ZFUNC(x) (((x) & 0x7) << 4) | |
2236 | #define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) | |
2237 | #define C_028800_ZFUNC 0xFFFFFF8F | |
2238 | #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) | |
2239 | #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) | |
2240 | #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F | |
2241 | #define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) | |
2242 | #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) | |
2243 | #define C_028800_STENCILFUNC 0xFFFFF8FF | |
2244 | #define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) | |
2245 | #define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) | |
2246 | #define C_028800_STENCILFAIL 0xFFFFC7FF | |
2247 | #define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) | |
2248 | #define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) | |
2249 | #define C_028800_STENCILZPASS 0xFFFE3FFF | |
2250 | #define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) | |
2251 | #define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) | |
2252 | #define C_028800_STENCILZFAIL 0xFFF1FFFF | |
2253 | #define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) | |
2254 | #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) | |
2255 | #define C_028800_STENCILFUNC_BF 0xFF8FFFFF | |
2256 | #define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) | |
2257 | #define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) | |
2258 | #define C_028800_STENCILFAIL_BF 0xFC7FFFFF | |
2259 | #define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) | |
2260 | #define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) | |
2261 | #define C_028800_STENCILZPASS_BF 0xE3FFFFFF | |
2262 | #define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) | |
2263 | #define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) | |
2264 | #define C_028800_STENCILZFAIL_BF 0x1FFFFFFF | |
c8c15ff1 | 2265 | |
3ce0a23d | 2266 | #endif |