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[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
0aea5e4a 67#include <linux/interval_tree.h>
341cb9e4 68#include <linux/hashtable.h>
954605ca 69#include <linux/fence.h>
771fe6b9 70
4c788679
JG		 71#include <ttm/ttm_bo_api.h>
72#include <ttm/ttm_bo_driver.h>
73#include <ttm/ttm_placement.h>
74#include <ttm/ttm_module.h>
147666fb 75#include <ttm/ttm_execbuf_util.h>
4c788679 76
d9fc9413
DV		 77#include <drm/drm_gem.h>
78
c2142715 79#include "radeon_family.h"
771fe6b9
JG		 80#include "radeon_mode.h"
81#include "radeon_reg.h"
771fe6b9
JG		 82
83/*
84 * Modules parameters.
85 */
86extern int radeon_no_wb;
87extern int radeon_modeset;
88extern int radeon_dynclks;
89extern int radeon_r4xx_atom;
90extern int radeon_agpmode;
91extern int radeon_vram_limit;
92extern int radeon_gart_size;
93extern int radeon_benchmarking;
ecc0b326 94extern int radeon_testing;
771fe6b9 95extern int radeon_connector_table;
4ce001ab 96extern int radeon_tv;
dafc3bd5 97extern int radeon_audio;
f46c0120 98extern int radeon_disp_priority;
e2b0a8e1 99extern int radeon_hw_i2c;
d42dd579 100extern int radeon_pcie_gen2;
a18cee15 101extern int radeon_msi;
3368ff0c 102extern int radeon_lockup_timeout;
a0a53aa8 103extern int radeon_fastfb;
da321c8a 104extern int radeon_dpm;
1294d4a3 105extern int radeon_aspm;
10ebc0bc 106extern int radeon_runtime_pm;
363eb0b4 107extern int radeon_hard_reset;
c1c44132 108extern int radeon_vm_size;
4510fb98 109extern int radeon_vm_block_size;
a624f429 110extern int radeon_deep_color;
39dc5454 111extern int radeon_use_pflipirq;
6e909f74 112extern int radeon_bapm;
bc13018b 113extern int radeon_backlight;
875711f0 114extern int radeon_auxch;
9843ead0 115extern int radeon_mst;
771fe6b9
JG		 116
117/*
118 * Copy from radeon_drv.h so we don't have to include both and have conflicting
119 * symbol;
120 */
bb635567
JG		 121#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
122#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
04db4caf 123#define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */
e821767b 124/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 125#define RADEON_IB_POOL_SIZE 16
126#define RADEON_DEBUGFS_MAX_COMPONENTS 32
127#define RADEONFB_CONN_LIMIT 4
128#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 129
1b37078b
AD		 130/* internal ring indices */
131/* r1xx+ has gfx CP ring */
d93f7937 132#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 133
134/* cayman has 2 compute CP rings */
d93f7937
CK		 135#define CAYMAN_RING_TYPE_CP1_INDEX 1
136#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 137
4d75658b
AD		 138/* R600+ has an async dma ring */
139#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 140/* cayman add a second async dma ring */
141#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 142
f2ba57b5 143/* R600+ */
d93f7937
CK		 144#define R600_RING_TYPE_UVD_INDEX 5
145
146/* TN+ */
147#define TN_RING_TYPE_VCE1_INDEX 6
148#define TN_RING_TYPE_VCE2_INDEX 7
149
150/* max number of rings */
151#define RADEON_NUM_RINGS 8
f2ba57b5 152
1c61eae4
CK		 153/* number of hw syncs before falling back on blocking */
154#define RADEON_NUM_SYNCS 4
f2ba57b5 155
721604a1 156/* hardcode those limit for now */
ca19f21e 157#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 158#define RADEON_VA_RESERVED_SIZE (8 << 20)
159#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 160
1a0041b8
AD		 161/* hard reset data */
162#define RADEON_ASIC_RESET_DATA 0x39d5e86b
163
ec46c76d
AD		 164/* reset flags */
165#define RADEON_RESET_GFX (1 << 0)
166#define RADEON_RESET_COMPUTE (1 << 1)
167#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 168#define RADEON_RESET_CP (1 << 3)
169#define RADEON_RESET_GRBM (1 << 4)
170#define RADEON_RESET_DMA1 (1 << 5)
171#define RADEON_RESET_RLC (1 << 6)
172#define RADEON_RESET_SEM (1 << 7)
173#define RADEON_RESET_IH (1 << 8)
174#define RADEON_RESET_VMC (1 << 9)
175#define RADEON_RESET_MC (1 << 10)
176#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 177
22c775ce
AD		 178/* CG block flags */
179#define RADEON_CG_BLOCK_GFX (1 << 0)
180#define RADEON_CG_BLOCK_MC (1 << 1)
181#define RADEON_CG_BLOCK_SDMA (1 << 2)
182#define RADEON_CG_BLOCK_UVD (1 << 3)
183#define RADEON_CG_BLOCK_VCE (1 << 4)
184#define RADEON_CG_BLOCK_HDP (1 << 5)
e16866ec 185#define RADEON_CG_BLOCK_BIF (1 << 6)
22c775ce 186
64d8a728
AD		 187/* CG flags */
188#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
189#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
190#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
191#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
192#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
193#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
194#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
195#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
196#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
197#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
198#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
199#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
200#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
201#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
202#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
203#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
204#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
205
206/* PG flags */
2b19d17f 207#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
64d8a728
AD		 208#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
209#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
210#define RADEON_PG_SUPPORT_UVD (1 << 3)
211#define RADEON_PG_SUPPORT_VCE (1 << 4)
212#define RADEON_PG_SUPPORT_CP (1 << 5)
213#define RADEON_PG_SUPPORT_GDS (1 << 6)
214#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
215#define RADEON_PG_SUPPORT_SDMA (1 << 8)
216#define RADEON_PG_SUPPORT_ACP (1 << 9)
217#define RADEON_PG_SUPPORT_SAMU (1 << 10)
218
9e05fa1d
AD		 219/* max cursor sizes (in pixels) */
220#define CURSOR_WIDTH 64
221#define CURSOR_HEIGHT 64
222
223#define CIK_CURSOR_WIDTH 128
224#define CIK_CURSOR_HEIGHT 128
225
771fe6b9
JG		 226/*
227 * Errata workarounds.
228 */
229enum radeon_pll_errata {
230 CHIP_ERRATA_R300_CG = 0x00000001,
231 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
232 CHIP_ERRATA_PLL_DELAY = 0x00000004
233};
234
235
236struct radeon_device;
237
238
239/*
240 * BIOS.
241 */
242bool radeon_get_bios(struct radeon_device *rdev);
243
244/*
3ce0a23d 245 * Dummy page
771fe6b9 246 */
3ce0a23d 247struct radeon_dummy_page {
cb658906 248 uint64_t entry;
3ce0a23d
JG		 249 struct page *page;
250 dma_addr_t addr;
251};
252int radeon_dummy_page_init(struct radeon_device *rdev);
253void radeon_dummy_page_fini(struct radeon_device *rdev);
254
771fe6b9 255
3ce0a23d
JG		 256/*
257 * Clocks
258 */
771fe6b9
JG		 259struct radeon_clock {
260 struct radeon_pll p1pll;
261 struct radeon_pll p2pll;
bcc1c2a1 262 struct radeon_pll dcpll;
771fe6b9
JG		 263 struct radeon_pll spll;
264 struct radeon_pll mpll;
265 /* 10 Khz units */
266 uint32_t default_mclk;
267 uint32_t default_sclk;
bcc1c2a1 268 uint32_t default_dispclk;
4489cd62 269 uint32_t current_dispclk;
bcc1c2a1 270 uint32_t dp_extclk;
b20f9bef 271 uint32_t max_pixel_clock;
c9a392ea 272 uint32_t vco_freq;
771fe6b9
JG		 273};
274
7433874e
RM		 275/*
276 * Power management
277 */
278int radeon_pm_init(struct radeon_device *rdev);
914a8987 279int radeon_pm_late_init(struct radeon_device *rdev);
29fb52ca 280void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 281void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 282void radeon_pm_suspend(struct radeon_device *rdev);
283void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 284void radeon_combios_get_power_modes(struct radeon_device *rdev);
285void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 286int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
287 u8 clock_type,
288 u32 clock,
289 bool strobe_mode,
290 struct atom_clock_dividers *dividers);
eaa778af
AD		 291int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
292 u32 clock,
293 bool strobe_mode,
294 struct atom_mpll_param *mpll_param);
8a83ec5e 295void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 296int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
297 u16 voltage_level, u8 voltage_type,
298 u32 *gpio_value, u32 *gpio_mask);
299void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
300 u32 eng_clock, u32 mem_clock);
301int radeon_atom_get_voltage_step(struct radeon_device *rdev,
302 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 303int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
304 u16 voltage_id, u16 *voltage);
beb79f40
AD		 305int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
306 u16 *voltage,
307 u16 leakage_idx);
cc8dbbb4
AD		 308int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
309 u16 *leakage_id);
310int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
311 u16 *vddc, u16 *vddci,
312 u16 virtual_voltage_id,
313 u16 vbios_voltage_id);
e9f274b2
AD		 314int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
315 u16 virtual_voltage_id,
316 u16 *voltage);
ae5b0abb
AD		 317int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
318 u8 voltage_type,
319 u16 nominal_voltage,
320 u16 *true_voltage);
321int radeon_atom_get_min_voltage(struct radeon_device *rdev,
322 u8 voltage_type, u16 *min_voltage);
323int radeon_atom_get_max_voltage(struct radeon_device *rdev,
324 u8 voltage_type, u16 *max_voltage);
325int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 326 u8 voltage_type, u8 voltage_mode,
ae5b0abb 327 struct atom_voltage_table *voltage_table);
58653abd
AD		 328bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
329 u8 voltage_type, u8 voltage_mode);
636e2582
AD		 330int radeon_atom_get_svi2_info(struct radeon_device *rdev,
331 u8 voltage_type,
332 u8 *svd_gpio_id, u8 *svc_gpio_id);
ae5b0abb
AD		 333void radeon_atom_update_memory_dll(struct radeon_device *rdev,
334 u32 mem_clock);
335void radeon_atom_set_ac_timing(struct radeon_device *rdev,
336 u32 mem_clock);
337int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
338 u8 module_index,
339 struct atom_mc_reg_table *reg_table);
340int radeon_atom_get_memory_info(struct radeon_device *rdev,
341 u8 module_index, struct atom_memory_info *mem_info);
342int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
343 bool gddr5, u8 module_index,
344 struct atom_memory_clock_range_table *mclk_range_table);
345int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
346 u16 voltage_id, u16 *voltage);
f892034a 347void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 348extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
349 unsigned *bankh, unsigned *mtaspect,
350 unsigned *tile_split);
3ce0a23d 351
771fe6b9
JG		 352/*
353 * Fences.
354 */
355struct radeon_fence_driver {
0bfa4b41 356 struct radeon_device *rdev;
771fe6b9 357 uint32_t scratch_reg;
30eb77f4
JG		 358 uint64_t gpu_addr;
359 volatile uint32_t *cpu_addr;
68e250b7
CK		 360 /* sync_seq is protected by ring emission lock */
361 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 362 atomic64_t last_seq;
954605ca 363 bool initialized, delayed_irq;
0bfa4b41 364 struct delayed_work lockup_work;
771fe6b9
JG		 365};
366
367struct radeon_fence {
ad1a58a4 368 struct fence base;
954605ca 369
ad1a58a4
CK		 370 struct radeon_device *rdev;
371 uint64_t seq;
7465280c 372 /* RB, DMA, etc. */
ad1a58a4
CK		 373 unsigned ring;
374 bool is_vm_update;
954605ca 375
ad1a58a4 376 wait_queue_t fence_wake;
771fe6b9
JG		 377};
378
30eb77f4
JG		 379int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
380int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 381void radeon_fence_driver_fini(struct radeon_device *rdev);
eb98c709 382void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
876dc9f3 383int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 384void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9 385bool radeon_fence_signaled(struct radeon_fence *fence);
04db4caf 386long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);
771fe6b9 387int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
37615527
CK		 388int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
389int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
0085c950
JG		 390int radeon_fence_wait_any(struct radeon_device *rdev,
391 struct radeon_fence **fences,
392 bool intr);
771fe6b9
JG		 393struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
394void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 395unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 396bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
397void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
398static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
399 struct radeon_fence *b)
400{
401 if (!a) {
402 return b;
403 }
404
405 if (!b) {
406 return a;
407 }
408
409 BUG_ON(a->ring != b->ring);
410
411 if (a->seq > b->seq) {
412 return a;
413 } else {
414 return b;
415 }
416}
771fe6b9 417
ee60e29f
CK		 418static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
419 struct radeon_fence *b)
420{
421 if (!a) {
422 return false;
423 }
424
425 if (!b) {
426 return true;
427 }
428
429 BUG_ON(a->ring != b->ring);
430
431 return a->seq < b->seq;
432}
433
e024e110
DA		 434/*
435 * Tiling registers
436 */
437struct radeon_surface_reg {
4c788679 438 struct radeon_bo *bo;
e024e110
DA		 439};
440
441#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 442
443/*
4c788679 444 * TTM.
771fe6b9 445 */
4c788679
JG		 446struct radeon_mman {
447 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 448 struct drm_global_reference mem_global_ref;
4c788679 449 struct ttm_bo_device bdev;
0a0c7596
JG		 450 bool mem_global_referenced;
451 bool initialized;
2014b569
CK		 452
453#if defined(CONFIG_DEBUG_FS)
454 struct dentry *vram;
dd66d20e 455 struct dentry *gtt;
2014b569 456#endif
4c788679
JG		 457};
458
1d0c0942
CK		 459struct radeon_bo_list {
460 struct radeon_bo *robj;
461 struct ttm_validate_buffer tv;
462 uint64_t gpu_offset;
463 unsigned prefered_domains;
464 unsigned allowed_domains;
465 uint32_t tiling_flags;
466};
467
721604a1
JG		 468/* bo virtual address in a specific vm */
469struct radeon_bo_va {
e971bd5e 470 /* protected by bo being reserved */
721604a1 471 struct list_head bo_list;
721604a1 472 uint32_t flags;
94214635 473 struct radeon_fence *last_pt_update;
e971bd5e
CK		 474 unsigned ref_count;
475
476 /* protected by vm mutex */
0aea5e4a 477 struct interval_tree_node it;
036bf46a 478 struct list_head vm_status;
e971bd5e
CK		 479
480 /* constant after initialization */
481 struct radeon_vm *vm;
482 struct radeon_bo *bo;
721604a1
JG		 483};
484
4c788679
JG		 485struct radeon_bo {
486 /* Protected by gem.mutex */
487 struct list_head list;
488 /* Protected by tbo.reserved */
bda72d58 489 u32 initial_domain;
c9da4a4b 490 struct ttm_place placements[4];
312ea8da 491 struct ttm_placement placement;
4c788679
JG		 492 struct ttm_buffer_object tbo;
493 struct ttm_bo_kmap_obj kmap;
02376d82 494 u32 flags;
4c788679
JG		 495 unsigned pin_count;
496 void *kptr;
497 u32 tiling_flags;
498 u32 pitch;
499 int surface_reg;
721604a1
JG		 500 /* list of all virtual address to which this bo
501 * is associated to
502 */
503 struct list_head va;
4c788679
JG		 504 /* Constant after initialization */
505 struct radeon_device *rdev;
441921d5 506 struct drm_gem_object gem_base;
63bc620b 507
409851f4
JG		 508 struct ttm_bo_kmap_obj dma_buf_vmap;
509 pid_t pid;
341cb9e4
CK		 510
511 struct radeon_mn *mn;
49ecb10e 512 struct list_head mn_list;
4c788679 513};
7e4d15d9 514#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 515
409851f4
JG		 516int radeon_gem_debugfs_init(struct radeon_device *rdev);
517
b15ba512
JG		 518/* sub-allocation manager, it has to be protected by another lock.
519 * By conception this is an helper for other part of the driver
520 * like the indirect buffer or semaphore, which both have their
521 * locking.
522 *
523 * Principe is simple, we keep a list of sub allocation in offset
524 * order (first entry has offset == 0, last entry has the highest
525 * offset).
526 *
527 * When allocating new object we first check if there is room at
528 * the end total_size - (last_object_offset + last_object_size) >=
529 * alloc_size. If so we allocate new object there.
530 *
531 * When there is not enough room at the end, we start waiting for
532 * each sub object until we reach object_offset+object_size >=
533 * alloc_size, this object then become the sub object we return.
534 *
535 * Alignment can't be bigger than page size.
536 *
537 * Hole are not considered for allocation to keep things simple.
538 * Assumption is that there won't be hole (all object on same
539 * alignment).
540 */
541struct radeon_sa_manager {
bfb38d35 542 wait_queue_head_t wq;
b15ba512 543 struct radeon_bo *bo;
c3b7fe8b
CK		 544 struct list_head *hole;
545 struct list_head flist[RADEON_NUM_RINGS];
546 struct list_head olist;
b15ba512
JG		 547 unsigned size;
548 uint64_t gpu_addr;
549 void *cpu_ptr;
550 uint32_t domain;
6c4f978b 551 uint32_t align;
b15ba512
JG		 552};
553
554struct radeon_sa_bo;
555
556/* sub-allocation buffer */
557struct radeon_sa_bo {
c3b7fe8b
CK		 558 struct list_head olist;
559 struct list_head flist;
b15ba512 560 struct radeon_sa_manager *manager;
e6661a96
CK		 561 unsigned soffset;
562 unsigned eoffset;
557017a0 563 struct radeon_fence *fence;
b15ba512
JG		 564};
565
771fe6b9
JG		 566/*
567 * GEM objects.
568 */
569struct radeon_gem {
4c788679 570 struct mutex mutex;
771fe6b9
JG		 571 struct list_head objects;
572};
573
574int radeon_gem_init(struct radeon_device *rdev);
575void radeon_gem_fini(struct radeon_device *rdev);
391bfec3 576int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
4c788679 577 int alignment, int initial_domain,
ed5cb43f 578 u32 flags, bool kernel,
4c788679 579 struct drm_gem_object **obj);
771fe6b9 580
ff72145b
DA		 581int radeon_mode_dumb_create(struct drm_file *file_priv,
582 struct drm_device *dev,
583 struct drm_mode_create_dumb *args);
584int radeon_mode_dumb_mmap(struct drm_file *filp,
585 struct drm_device *dev,
586 uint32_t handle, uint64_t *offset_p);
771fe6b9 587
c1341e52
JG		 588/*
589 * Semaphores.
590 */
c1341e52 591struct radeon_semaphore {
975700d2
CK		 592 struct radeon_sa_bo *sa_bo;
593 signed waiters;
594 uint64_t gpu_addr;
c1341e52
JG		 595};
596
c1341e52
JG		 597int radeon_semaphore_create(struct radeon_device *rdev,
598 struct radeon_semaphore **semaphore);
1654b817 599bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
c1341e52 600 struct radeon_semaphore *semaphore);
1654b817 601bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
c1341e52
JG		 602 struct radeon_semaphore *semaphore);
603void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 604 struct radeon_semaphore **semaphore,
a8c05940 605 struct radeon_fence *fence);
c1341e52 606
975700d2
CK		 607/*
608 * Synchronization
609 */
610struct radeon_sync {
611 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
612 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
ad1a58a4 613 struct radeon_fence *last_vm_update;
975700d2
CK		 614};
615
616void radeon_sync_create(struct radeon_sync *sync);
617void radeon_sync_fence(struct radeon_sync *sync,
618 struct radeon_fence *fence);
619int radeon_sync_resv(struct radeon_device *rdev,
620 struct radeon_sync *sync,
621 struct reservation_object *resv,
622 bool shared);
623int radeon_sync_rings(struct radeon_device *rdev,
624 struct radeon_sync *sync,
625 int waiting_ring);
626void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
627 struct radeon_fence *fence);
628
771fe6b9
JG		 629/*
630 * GART structures, functions & helpers
631 */
632struct radeon_mc;
633
a77f1718 634#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 635#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 636#define RADEON_GPU_PAGE_SHIFT 12
721604a1 637#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 638
77497f27
MD		 639#define RADEON_GART_PAGE_DUMMY 0
640#define RADEON_GART_PAGE_VALID (1 << 0)
641#define RADEON_GART_PAGE_READ (1 << 1)
642#define RADEON_GART_PAGE_WRITE (1 << 2)
643#define RADEON_GART_PAGE_SNOOP (1 << 3)
644
771fe6b9
JG		 645struct radeon_gart {
646 dma_addr_t table_addr;
c9a1be96
JG		 647 struct radeon_bo *robj;
648 void *ptr;
771fe6b9
JG		 649 unsigned num_gpu_pages;
650 unsigned num_cpu_pages;
651 unsigned table_size;
771fe6b9 652 struct page **pages;
cb658906 653 uint64_t *pages_entry;
771fe6b9
JG		 654 bool ready;
655};
656
657int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
658void radeon_gart_table_ram_free(struct radeon_device *rdev);
659int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
660void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 661int radeon_gart_table_vram_pin(struct radeon_device *rdev);
662void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 663int radeon_gart_init(struct radeon_device *rdev);
664void radeon_gart_fini(struct radeon_device *rdev);
665void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
666 int pages);
667int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516 668 int pages, struct page **pagelist,
77497f27 669 dma_addr_t *dma_addr, uint32_t flags);
771fe6b9
JG		 670
671
672/*
673 * GPU MC structures, functions & helpers
674 */
675struct radeon_mc {
676 resource_size_t aper_size;
677 resource_size_t aper_base;
678 resource_size_t agp_base;
7a50f01a
DA		 679 /* for some chips with <= 32MB we need to lie
680 * about vram size near mc fb location */
3ce0a23d 681 u64 mc_vram_size;
d594e46a 682 u64 visible_vram_size;
3ce0a23d
JG		 683 u64 gtt_size;
684 u64 gtt_start;
685 u64 gtt_end;
3ce0a23d
JG		 686 u64 vram_start;
687 u64 vram_end;
771fe6b9 688 unsigned vram_width;
3ce0a23d 689 u64 real_vram_size;
771fe6b9
JG		 690 int vram_mtrr;
691 bool vram_is_ddr;
d594e46a 692 bool igp_sideport_enabled;
8d369bb1 693 u64 gtt_base_align;
9ed8b1f9 694 u64 mc_mask;
771fe6b9
JG		 695};
696
06b6476d
AD		 697bool radeon_combios_sideport_present(struct radeon_device *rdev);
698bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 699
700/*
701 * GPU scratch registers structures, functions & helpers
702 */
703struct radeon_scratch {
704 unsigned num_reg;
724c80e1 705 uint32_t reg_base;
771fe6b9
JG		 706 bool free[32];
707 uint32_t reg[32];
708};
709
710int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
711void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
712
75efdee1
AD		 713/*
714 * GPU doorbell structures, functions & helpers
715 */
d5754ab8
AL		 716#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
717
75efdee1 718struct radeon_doorbell {
75efdee1 719 /* doorbell mmio */
d5754ab8
AL		 720 resource_size_t base;
721 resource_size_t size;
722 u32 __iomem *ptr;
723 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
a10e04f4 724 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
75efdee1
AD		 725};
726
727int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
728void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
ebff8453
OG		 729void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
730 phys_addr_t *aperture_base,
731 size_t *aperture_size,
732 size_t *start_offset);
771fe6b9
JG		 733
734/*
735 * IRQS.
736 */
6f34be50 737
fa7f517c
CK		 738struct radeon_flip_work {
739 struct work_struct flip_work;
740 struct work_struct unpin_work;
741 struct radeon_device *rdev;
742 int crtc_id;
c60381bd 743 uint64_t base;
6f34be50 744 struct drm_pending_vblank_event *event;
fa7f517c 745 struct radeon_bo *old_rbo;
a0e84764 746 struct fence *fence;
6f34be50
AD		 747};
748
749struct r500_irq_stat_regs {
750 u32 disp_int;
f122c610 751 u32 hdmi0_status;
6f34be50
AD		 752};
753
754struct r600_irq_stat_regs {
755 u32 disp_int;
756 u32 disp_int_cont;
757 u32 disp_int_cont2;
758 u32 d1grph_int;
759 u32 d2grph_int;
f122c610
AD		 760 u32 hdmi0_status;
761 u32 hdmi1_status;
6f34be50
AD		 762};
763
764struct evergreen_irq_stat_regs {
765 u32 disp_int;
766 u32 disp_int_cont;
767 u32 disp_int_cont2;
768 u32 disp_int_cont3;
769 u32 disp_int_cont4;
770 u32 disp_int_cont5;
771 u32 d1grph_int;
772 u32 d2grph_int;
773 u32 d3grph_int;
774 u32 d4grph_int;
775 u32 d5grph_int;
776 u32 d6grph_int;
f122c610
AD		 777 u32 afmt_status1;
778 u32 afmt_status2;
779 u32 afmt_status3;
780 u32 afmt_status4;
781 u32 afmt_status5;
782 u32 afmt_status6;
6f34be50
AD		 783};
784
a59781bb
AD		 785struct cik_irq_stat_regs {
786 u32 disp_int;
787 u32 disp_int_cont;
788 u32 disp_int_cont2;
789 u32 disp_int_cont3;
790 u32 disp_int_cont4;
791 u32 disp_int_cont5;
792 u32 disp_int_cont6;
f5d636d2
CK		 793 u32 d1grph_int;
794 u32 d2grph_int;
795 u32 d3grph_int;
796 u32 d4grph_int;
797 u32 d5grph_int;
798 u32 d6grph_int;
a59781bb
AD		 799};
800
6f34be50
AD		 801union radeon_irq_stat_regs {
802 struct r500_irq_stat_regs r500;
803 struct r600_irq_stat_regs r600;
804 struct evergreen_irq_stat_regs evergreen;
a59781bb 805 struct cik_irq_stat_regs cik;
6f34be50
AD		 806};
807
771fe6b9 808struct radeon_irq {
fb98257a
CK		 809 bool installed;
810 spinlock_t lock;
736fc37f 811 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 812 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 813 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 814 wait_queue_head_t vblank_queue;
815 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 816 bool afmt[RADEON_MAX_AFMT_BLOCKS];
817 union radeon_irq_stat_regs stat_regs;
4a6369e9 818 bool dpm_thermal;
771fe6b9
JG		 819};
820
821int radeon_irq_kms_init(struct radeon_device *rdev);
822void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b 823void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
954605ca 824bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
1b37078b 825void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 826void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
827void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 828void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
829void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
830void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
831void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 832
833/*
e32eb50d 834 * CP & rings.
771fe6b9 835 */
7465280c 836
771fe6b9 837struct radeon_ib {
68470ae7
JG		 838 struct radeon_sa_bo *sa_bo;
839 uint32_t length_dw;
840 uint64_t gpu_addr;
841 uint32_t *ptr;
876dc9f3 842 int ring;
68470ae7 843 struct radeon_fence *fence;
4bf3dd92 844 struct radeon_vm *vm;
68470ae7 845 bool is_const_ib;
975700d2 846 struct radeon_sync sync;
771fe6b9
JG		 847};
848
e32eb50d 849struct radeon_ring {
4c788679 850 struct radeon_bo *ring_obj;
771fe6b9 851 volatile uint32_t *ring;
5596a9db 852 unsigned rptr_offs;
45df6803 853 unsigned rptr_save_reg;
89d35807
AD		 854 u64 next_rptr_gpu_addr;
855 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 856 unsigned wptr;
857 unsigned wptr_old;
858 unsigned ring_size;
859 unsigned ring_free_dw;
860 int count_dw;
aee4aa73
CK		 861 atomic_t last_rptr;
862 atomic64_t last_activity;
771fe6b9
JG		 863 uint64_t gpu_addr;
864 uint32_t align_mask;
865 uint32_t ptr_mask;
771fe6b9 866 bool ready;
78c5560a 867 u32 nop;
8b25ed34 868 u32 idx;
5f0839c1
JG		 869 u64 last_semaphore_signal_addr;
870 u64 last_semaphore_wait_addr;
963e81f9
AD		 871 /* for CIK queues */
872 u32 me;
873 u32 pipe;
874 u32 queue;
875 struct radeon_bo *mqd_obj;
d5754ab8 876 u32 doorbell_index;
963e81f9
AD		 877 unsigned wptr_offs;
878};
879
880struct radeon_mec {
881 struct radeon_bo *hpd_eop_obj;
882 u64 hpd_eop_gpu_addr;
883 u32 num_pipe;
884 u32 num_mec;
885 u32 num_queue;
771fe6b9
JG		 886};
887
721604a1
JG		 888/*
889 * VM
890 */
ee60e29f 891
fa87e62d 892/* maximum number of VMIDs */
ee60e29f
CK		 893#define RADEON_NUM_VM 16
894
fa87e62d 895/* number of entries in page table */
4510fb98 896#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
fa87e62d 897
1c01103c
AD		 898/* PTBs (Page Table Blocks) need to be aligned to 32K */
899#define RADEON_VM_PTB_ALIGN_SIZE 32768
900#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
901#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
902
24c16439
CK		 903#define R600_PTE_VALID (1 << 0)
904#define R600_PTE_SYSTEM (1 << 1)
905#define R600_PTE_SNOOPED (1 << 2)
906#define R600_PTE_READABLE (1 << 5)
907#define R600_PTE_WRITEABLE (1 << 6)
908
ec3dbbcb
CK		 909/* PTE (Page Table Entry) fragment field for different page sizes */
910#define R600_PTE_FRAG_4KB (0 << 7)
911#define R600_PTE_FRAG_64KB (4 << 7)
912#define R600_PTE_FRAG_256KB (6 << 7)
913
33fa9fe3
CK		 914/* flags needed to be set so we can copy directly from the GART table */
915#define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
916 R600_PTE_SYSTEM | R600_PTE_VALID )
0e97703c 917
6d2f2944
CK		 918struct radeon_vm_pt {
919 struct radeon_bo *bo;
920 uint64_t addr;
921};
922
7c42bc1a
CK		 923struct radeon_vm_id {
924 unsigned id;
925 uint64_t pd_gpu_addr;
926 /* last flushed PD/PT update */
927 struct radeon_fence *flushed_updates;
928 /* last use of vmid */
929 struct radeon_fence *last_id_use;
930};
931
721604a1 932struct radeon_vm {
94214635
CK		 933 struct mutex mutex;
934
7c42bc1a 935 struct rb_root va;
90a51a32 936
f7a3db75
CK		 937 /* protecting invalidated and freed */
938 spinlock_t status_lock;
939
e31ad969 940 /* BOs moved, but not yet updated in the PT */
7c42bc1a 941 struct list_head invalidated;
e31ad969 942
036bf46a 943 /* BOs freed, but not yet updated in the PT */
7c42bc1a 944 struct list_head freed;
036bf46a 945
161ab658
CK		 946 /* BOs cleared in the PT */
947 struct list_head cleared;
948
90a51a32 949 /* contains the page directory */
7c42bc1a
CK		 950 struct radeon_bo *page_directory;
951 unsigned max_pde_used;
90a51a32
CK		 952
953 /* array of page tables, one for each page directory entry */
7c42bc1a 954 struct radeon_vm_pt *page_tables;
90a51a32 955
7c42bc1a 956 struct radeon_bo_va *ib_bo_va;
cc9e67e3 957
7c42bc1a
CK		 958 /* for id and flush management per ring */
959 struct radeon_vm_id ids[RADEON_NUM_RINGS];
721604a1
JG		 960};
961
721604a1 962struct radeon_vm_manager {
ee60e29f 963 struct radeon_fence *active[RADEON_NUM_VM];
721604a1 964 uint32_t max_pfn;
721604a1
JG		 965 /* number of VMIDs */
966 unsigned nvm;
967 /* vram base address for page table entry */
968 u64 vram_base_offset;
67e915e4
AD		 969 /* is vm enabled? */
970 bool enabled;
054e01d6
CK		 971 /* for hw to save the PD addr on suspend/resume */
972 uint32_t saved_table_addr[RADEON_NUM_VM];
721604a1
JG		 973};
974
975/*
976 * file private structure
977 */
978struct radeon_fpriv {
979 struct radeon_vm vm;
980};
981
d8f60cfc
AD		 982/*
983 * R6xx+ IH ring
984 */
985struct r600_ih {
4c788679 986 struct radeon_bo *ring_obj;
d8f60cfc
AD		 987 volatile uint32_t *ring;
988 unsigned rptr;
d8f60cfc
AD		 989 unsigned ring_size;
990 uint64_t gpu_addr;
d8f60cfc 991 uint32_t ptr_mask;
c20dc369 992 atomic_t lock;
d8f60cfc
AD		 993 bool enabled;
994};
995
347e7592 996/*
2948f5e6 997 * RLC stuff
347e7592 998 */
2948f5e6
AD		 999#include "clearstate_defs.h"
1000
1001struct radeon_rlc {
347e7592
AD		 1002 /* for power gating */
1003 struct radeon_bo *save_restore_obj;
1004 uint64_t save_restore_gpu_addr;
2948f5e6 1005 volatile uint32_t *sr_ptr;
1fd11777 1006 const u32 *reg_list;
2948f5e6 1007 u32 reg_list_size;
347e7592
AD		 1008 /* for clear state */
1009 struct radeon_bo *clear_state_obj;
1010 uint64_t clear_state_gpu_addr;
2948f5e6 1011 volatile uint32_t *cs_ptr;
1fd11777 1012 const struct cs_section_def *cs_data;
22c775ce
AD		 1013 u32 clear_state_size;
1014 /* for cp tables */
1015 struct radeon_bo *cp_table_obj;
1016 uint64_t cp_table_gpu_addr;
1017 volatile uint32_t *cp_table_ptr;
1018 u32 cp_table_size;
347e7592
AD		 1019};
1020
69e130a6 1021int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 1022 struct radeon_ib *ib, struct radeon_vm *vm,
1023 unsigned size);
f2e39221 1024void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
4ef72566 1025int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1538a9e0 1026 struct radeon_ib *const_ib, bool hdp_flush);
771fe6b9
JG		 1027int radeon_ib_pool_init(struct radeon_device *rdev);
1028void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 1029int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 1030/* Ring access between begin & end cannot sleep */
89d35807
AD		 1031bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1032 struct radeon_ring *ring);
e32eb50d
CK		 1033void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1034int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1035int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1538a9e0
MD		 1036void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1037 bool hdp_flush);
1038void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1039 bool hdp_flush);
d6999bc7 1040void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 1041void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1042int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
ff212f25
CK		 1043void radeon_ring_lockup_update(struct radeon_device *rdev,
1044 struct radeon_ring *ring);
069211e5 1045bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 1046unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1047 uint32_t **data);
1048int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1049 unsigned size, uint32_t *data);
e32eb50d 1050int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
ea31bf69 1051 unsigned rptr_offs, u32 nop);
e32eb50d 1052void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 1053
1054
4d75658b
AD		 1055/* r600 async dma */
1056void r600_dma_stop(struct radeon_device *rdev);
1057int r600_dma_resume(struct radeon_device *rdev);
1058void r600_dma_fini(struct radeon_device *rdev);
1059
8c5fd7ef
AD		 1060void cayman_dma_stop(struct radeon_device *rdev);
1061int cayman_dma_resume(struct radeon_device *rdev);
1062void cayman_dma_fini(struct radeon_device *rdev);
1063
771fe6b9
JG		 1064/*
1065 * CS.
1066 */
771fe6b9 1067struct radeon_cs_chunk {
771fe6b9
JG		 1068 uint32_t length_dw;
1069 uint32_t *kdata;
721604a1 1070 void __user *user_ptr;
771fe6b9
JG		 1071};
1072
1073struct radeon_cs_parser {
c8c15ff1 1074 struct device *dev;
771fe6b9
JG		 1075 struct radeon_device *rdev;
1076 struct drm_file *filp;
1077 /* chunks */
1078 unsigned nchunks;
1079 struct radeon_cs_chunk *chunks;
1080 uint64_t *chunks_array;
1081 /* IB */
1082 unsigned idx;
1083 /* relocations */
1084 unsigned nrelocs;
1d0c0942 1085 struct radeon_bo_list *relocs;
1d0c0942 1086 struct radeon_bo_list *vm_bos;
771fe6b9 1087 struct list_head validated;
cf4ccd01 1088 unsigned dma_reloc_idx;
771fe6b9 1089 /* indices of various chunks */
6d2d13dd
CK		 1090 struct radeon_cs_chunk *chunk_ib;
1091 struct radeon_cs_chunk *chunk_relocs;
1092 struct radeon_cs_chunk *chunk_flags;
1093 struct radeon_cs_chunk *chunk_const_ib;
f2e39221
JG		 1094 struct radeon_ib ib;
1095 struct radeon_ib const_ib;
771fe6b9 1096 void *track;
3ce0a23d 1097 unsigned family;
e70f224c 1098 int parser_error;
721604a1
JG		 1099 u32 cs_flags;
1100 u32 ring;
1101 s32 priority;
ecff665f 1102 struct ww_acquire_ctx ticket;
771fe6b9
JG		 1103};
1104
28a326c5
ML		 1105static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1106{
6d2d13dd 1107 struct radeon_cs_chunk *ibc = p->chunk_ib;
28a326c5
ML		 1108
1109 if (ibc->kdata)
1110 return ibc->kdata[idx];
1111 return p->ib.ptr[idx];
1112}
1113
513bcb46 1114
771fe6b9
JG		 1115struct radeon_cs_packet {
1116 unsigned idx;
1117 unsigned type;
1118 unsigned reg;
1119 unsigned opcode;
1120 int count;
1121 unsigned one_reg_wr;
1122};
1123
1124typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1125 struct radeon_cs_packet *pkt,
1126 unsigned idx, unsigned reg);
1127typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1128 struct radeon_cs_packet *pkt);
1129
1130
1131/*
1132 * AGP
1133 */
1134int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1135void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1136void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1137void radeon_agp_fini(struct radeon_device *rdev);
1138
1139
1140/*
1141 * Writeback
1142 */
1143struct radeon_wb {
4c788679 1144 struct radeon_bo *wb_obj;
771fe6b9
JG		 1145 volatile uint32_t *wb;
1146 uint64_t gpu_addr;
724c80e1 1147 bool enabled;
d0f8a854 1148 bool use_event;
771fe6b9
JG		 1149};
1150
724c80e1 1151#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1152#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1153#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1154#define RADEON_WB_CP1_RPTR_OFFSET 1280
1155#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1156#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1157#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1158#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1159#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1160#define CIK_WB_CP1_WPTR_OFFSET 3328
1161#define CIK_WB_CP2_WPTR_OFFSET 3584
adfed2b0
AD		 1162#define R600_WB_DMA_RING_TEST_OFFSET 3588
1163#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
724c80e1 1164
c93bb85b
JG		 1165/**
1166 * struct radeon_pm - power management datas
1167 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1168 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1169 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1170 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1171 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1172 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1173 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1174 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1175 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1176 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1177 * @needed_bandwidth: current bandwidth needs
1178 *
1179 * It keeps track of various data needed to take powermanagement decision.
25985edc 1180 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1181 * Equation between gpu/memory clock and available bandwidth is hw dependent
1182 * (type of memory, bus size, efficiency, ...)
1183 */
ce8f5370
AD		 1184
1185enum radeon_pm_method {
1186 PM_METHOD_PROFILE,
1187 PM_METHOD_DYNPM,
da321c8a 1188 PM_METHOD_DPM,
ce8f5370
AD		 1189};
1190
1191enum radeon_dynpm_state {
1192 DYNPM_STATE_DISABLED,
1193 DYNPM_STATE_MINIMUM,
1194 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1195 DYNPM_STATE_ACTIVE,
1196 DYNPM_STATE_SUSPENDED,
c913e23a 1197};
ce8f5370
AD		 1198enum radeon_dynpm_action {
1199 DYNPM_ACTION_NONE,
1200 DYNPM_ACTION_MINIMUM,
1201 DYNPM_ACTION_DOWNCLOCK,
1202 DYNPM_ACTION_UPCLOCK,
1203 DYNPM_ACTION_DEFAULT
c913e23a 1204};
56278a8e
AD		 1205
1206enum radeon_voltage_type {
1207 VOLTAGE_NONE = 0,
1208 VOLTAGE_GPIO,
1209 VOLTAGE_VDDC,
1210 VOLTAGE_SW
1211};
1212
0ec0e74f 1213enum radeon_pm_state_type {
da321c8a 1214 /* not used for dpm */
0ec0e74f
AD		 1215 POWER_STATE_TYPE_DEFAULT,
1216 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1217 /* user selectable states */
0ec0e74f
AD		 1218 POWER_STATE_TYPE_BATTERY,
1219 POWER_STATE_TYPE_BALANCED,
1220 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1221 /* internal states */
1222 POWER_STATE_TYPE_INTERNAL_UVD,
1223 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1224 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1225 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1226 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1227 POWER_STATE_TYPE_INTERNAL_BOOT,
1228 POWER_STATE_TYPE_INTERNAL_THERMAL,
1229 POWER_STATE_TYPE_INTERNAL_ACPI,
1230 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1231 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1232};
1233
ce8f5370
AD		 1234enum radeon_pm_profile_type {
1235 PM_PROFILE_DEFAULT,
1236 PM_PROFILE_AUTO,
1237 PM_PROFILE_LOW,
c9e75b21 1238 PM_PROFILE_MID,
ce8f5370
AD		 1239 PM_PROFILE_HIGH,
1240};
1241
1242#define PM_PROFILE_DEFAULT_IDX 0
1243#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1244#define PM_PROFILE_MID_SH_IDX 2
1245#define PM_PROFILE_HIGH_SH_IDX 3
1246#define PM_PROFILE_LOW_MH_IDX 4
1247#define PM_PROFILE_MID_MH_IDX 5
1248#define PM_PROFILE_HIGH_MH_IDX 6
1249#define PM_PROFILE_MAX 7
ce8f5370
AD		 1250
1251struct radeon_pm_profile {
1252 int dpms_off_ps_idx;
1253 int dpms_on_ps_idx;
1254 int dpms_off_cm_idx;
1255 int dpms_on_cm_idx;
516d0e46
AD		 1256};
1257
21a8122a
AD		 1258enum radeon_int_thermal_type {
1259 THERMAL_TYPE_NONE,
da321c8a
AD		 1260 THERMAL_TYPE_EXTERNAL,
1261 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1262 THERMAL_TYPE_RV6XX,
1263 THERMAL_TYPE_RV770,
da321c8a 1264 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1265 THERMAL_TYPE_EVERGREEN,
e33df25f 1266 THERMAL_TYPE_SUMO,
4fddba1f 1267 THERMAL_TYPE_NI,
14607d08 1268 THERMAL_TYPE_SI,
da321c8a 1269 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1270 THERMAL_TYPE_CI,
16fbe00d 1271 THERMAL_TYPE_KV,
21a8122a
AD		 1272};
1273
56278a8e
AD		 1274struct radeon_voltage {
1275 enum radeon_voltage_type type;
1276 /* gpio voltage */
1277 struct radeon_gpio_rec gpio;
1278 u32 delay; /* delay in usec from voltage drop to sclk change */
1279 bool active_high; /* voltage drop is active when bit is high */
1280 /* VDDC voltage */
1281 u8 vddc_id; /* index into vddc voltage table */
1282 u8 vddci_id; /* index into vddci voltage table */
1283 bool vddci_enabled;
1284 /* r6xx+ sw */
2feea49a
AD		 1285 u16 voltage;
1286 /* evergreen+ vddci */
1287 u16 vddci;
56278a8e
AD		 1288};
1289
d7311171
AD		 1290/* clock mode flags */
1291#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1292
56278a8e
AD		 1293struct radeon_pm_clock_info {
1294 /* memory clock */
1295 u32 mclk;
1296 /* engine clock */
1297 u32 sclk;
1298 /* voltage info */
1299 struct radeon_voltage voltage;
d7311171 1300 /* standardized clock flags */
56278a8e
AD		 1301 u32 flags;
1302};
1303
a48b9b4e 1304/* state flags */
d7311171 1305#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1306
56278a8e 1307struct radeon_power_state {
0ec0e74f 1308 enum radeon_pm_state_type type;
8f3f1c9a 1309 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1310 /* number of valid clock modes in this power state */
1311 int num_clock_modes;
56278a8e 1312 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1313 /* standardized state flags */
1314 u32 flags;
79daedc9
AD		 1315 u32 misc; /* vbios specific flags */
1316 u32 misc2; /* vbios specific flags */
1317 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1318};
1319
27459324
RM		 1320/*
1321 * Some modes are overclocked by very low value, accept them
1322 */
1323#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1324
2e9d4c05
AD		 1325enum radeon_dpm_auto_throttle_src {
1326 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1327 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1328};
1329
1330enum radeon_dpm_event_src {
1331 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1332 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1333 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1334 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1335 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1336};
1337
58bd2a88
AD		 1338#define RADEON_MAX_VCE_LEVELS 6
1339
b62d628b
AD		 1340enum radeon_vce_level {
1341 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1342 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1343 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1344 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1345 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1346 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1347};
1348
da321c8a
AD		 1349struct radeon_ps {
1350 u32 caps; /* vbios flags */
1351 u32 class; /* vbios flags */
1352 u32 class2; /* vbios flags */
1353 /* UVD clocks */
1354 u32 vclk;
1355 u32 dclk;
c4453e66
AD		 1356 /* VCE clocks */
1357 u32 evclk;
1358 u32 ecclk;
b62d628b
AD		 1359 bool vce_active;
1360 enum radeon_vce_level vce_level;
da321c8a
AD		 1361 /* asic priv */
1362 void *ps_priv;
1363};
1364
1365struct radeon_dpm_thermal {
1366 /* thermal interrupt work */
1367 struct work_struct work;
1368 /* low temperature threshold */
1369 int min_temp;
1370 /* high temperature threshold */
1371 int max_temp;
1372 /* was interrupt low to high or high to low */
1373 bool high_to_low;
1374};
1375
d22b7e40
AD		 1376enum radeon_clk_action
1377{
1378 RADEON_SCLK_UP = 1,
1379 RADEON_SCLK_DOWN
1380};
1381
1382struct radeon_blacklist_clocks
1383{
1384 u32 sclk;
1385 u32 mclk;
1386 enum radeon_clk_action action;
1387};
1388
61b7d601
AD		 1389struct radeon_clock_and_voltage_limits {
1390 u32 sclk;
1391 u32 mclk;
cdf6e805
AD		 1392 u16 vddc;
1393 u16 vddci;
61b7d601
AD		 1394};
1395
1396struct radeon_clock_array {
1397 u32 count;
1398 u32 *values;
1399};
1400
1401struct radeon_clock_voltage_dependency_entry {
1402 u32 clk;
1403 u16 v;
1404};
1405
1406struct radeon_clock_voltage_dependency_table {
1407 u32 count;
1408 struct radeon_clock_voltage_dependency_entry *entries;
1409};
1410
ef976ec4
AD		 1411union radeon_cac_leakage_entry {
1412 struct {
1413 u16 vddc;
1414 u32 leakage;
1415 };
1416 struct {
1417 u16 vddc1;
1418 u16 vddc2;
1419 u16 vddc3;
1420 };
61b7d601
AD		 1421};
1422
1423struct radeon_cac_leakage_table {
1424 u32 count;
ef976ec4 1425 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1426};
1427
929ee7a8
AD		 1428struct radeon_phase_shedding_limits_entry {
1429 u16 voltage;
1430 u32 sclk;
1431 u32 mclk;
1432};
1433
1434struct radeon_phase_shedding_limits_table {
1435 u32 count;
1436 struct radeon_phase_shedding_limits_entry *entries;
1437};
1438
84a9d9ee
AD		 1439struct radeon_uvd_clock_voltage_dependency_entry {
1440 u32 vclk;
1441 u32 dclk;
1442 u16 v;
1443};
1444
1445struct radeon_uvd_clock_voltage_dependency_table {
1446 u8 count;
1447 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1448};
1449
d29f013b
AD		 1450struct radeon_vce_clock_voltage_dependency_entry {
1451 u32 ecclk;
1452 u32 evclk;
1453 u16 v;
1454};
1455
1456struct radeon_vce_clock_voltage_dependency_table {
1457 u8 count;
1458 struct radeon_vce_clock_voltage_dependency_entry *entries;
1459};
1460
a5cb318e
AD		 1461struct radeon_ppm_table {
1462 u8 ppm_design;
1463 u16 cpu_core_number;
1464 u32 platform_tdp;
1465 u32 small_ac_platform_tdp;
1466 u32 platform_tdc;
1467 u32 small_ac_platform_tdc;
1468 u32 apu_tdp;
1469 u32 dgpu_tdp;
1470 u32 dgpu_ulv_power;
1471 u32 tj_max;
1472};
1473
58cb7632
AD		 1474struct radeon_cac_tdp_table {
1475 u16 tdp;
1476 u16 configurable_tdp;
1477 u16 tdc;
1478 u16 battery_power_limit;
1479 u16 small_power_limit;
1480 u16 low_cac_leakage;
1481 u16 high_cac_leakage;
1482 u16 maximum_power_delivery_limit;
1483};
1484
61b7d601
AD		 1485struct radeon_dpm_dynamic_state {
1486 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1487 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1488 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1489 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1490 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1491 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1492 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1493 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1494 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1495 struct radeon_clock_array valid_sclk_values;
1496 struct radeon_clock_array valid_mclk_values;
1497 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1498 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1499 u32 mclk_sclk_ratio;
1500 u32 sclk_mclk_delta;
1501 u16 vddc_vddci_delta;
1502 u16 min_vddc_for_pcie_gen2;
1503 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1504 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1505 struct radeon_ppm_table *ppm_table;
58cb7632 1506 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1507};
1508
1509struct radeon_dpm_fan {
1510 u16 t_min;
1511 u16 t_med;
1512 u16 t_high;
1513 u16 pwm_min;
1514 u16 pwm_med;
1515 u16 pwm_high;
1516 u8 t_hyst;
1517 u32 cycle_delay;
1518 u16 t_max;
e03cea36
AD		 1519 u8 control_mode;
1520 u16 default_max_fan_pwm;
1521 u16 default_fan_output_sensitivity;
1522 u16 fan_output_sensitivity;
61b7d601
AD		 1523 bool ucode_fan_control;
1524};
1525
32ce4652
AD		 1526enum radeon_pcie_gen {
1527 RADEON_PCIE_GEN1 = 0,
1528 RADEON_PCIE_GEN2 = 1,
1529 RADEON_PCIE_GEN3 = 2,
1530 RADEON_PCIE_GEN_INVALID = 0xffff
1531};
1532
70d01a5e
AD		 1533enum radeon_dpm_forced_level {
1534 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1535 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1536 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1537};
1538
58bd2a88
AD		 1539struct radeon_vce_state {
1540 /* vce clocks */
1541 u32 evclk;
1542 u32 ecclk;
1543 /* gpu clocks */
1544 u32 sclk;
1545 u32 mclk;
1546 u8 clk_idx;
1547 u8 pstate;
1548};
1549
da321c8a
AD		 1550struct radeon_dpm {
1551 struct radeon_ps *ps;
1552 /* number of valid power states */
1553 int num_ps;
1554 /* current power state that is active */
1555 struct radeon_ps *current_ps;
1556 /* requested power state */
1557 struct radeon_ps *requested_ps;
1558 /* boot up power state */
1559 struct radeon_ps *boot_ps;
1560 /* default uvd power state */
1561 struct radeon_ps *uvd_ps;
58bd2a88
AD		 1562 /* vce requirements */
1563 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1564 enum radeon_vce_level vce_level;
da321c8a
AD		 1565 enum radeon_pm_state_type state;
1566 enum radeon_pm_state_type user_state;
1567 u32 platform_caps;
1568 u32 voltage_response_time;
1569 u32 backbias_response_time;
1570 void *priv;
1571 u32 new_active_crtcs;
1572 int new_active_crtc_count;
1573 u32 current_active_crtcs;
1574 int current_active_crtc_count;
3899ca84 1575 bool single_display;
61b7d601
AD		 1576 struct radeon_dpm_dynamic_state dyn_state;
1577 struct radeon_dpm_fan fan;
1578 u32 tdp_limit;
1579 u32 near_tdp_limit;
a9e61410 1580 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1581 u32 sq_ramping_threshold;
1582 u32 cac_leakage;
1583 u16 tdp_od_limit;
1584 u32 tdp_adjustment;
1585 u16 load_line_slope;
1586 bool power_control;
5ca302f7 1587 bool ac_power;
da321c8a
AD		 1588 /* special states active */
1589 bool thermal_active;
8a227555 1590 bool uvd_active;
b62d628b 1591 bool vce_active;
da321c8a
AD		 1592 /* thermal handling */
1593 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1594 /* forced levels */
1595 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1596 /* track UVD streams */
1597 unsigned sd;
1598 unsigned hd;
da321c8a
AD		 1599};
1600
ce3537d5 1601void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
03afe6f6 1602void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
da321c8a 1603
c93bb85b 1604struct radeon_pm {
c913e23a 1605 struct mutex mutex;
db7fce39
CK		 1606 /* write locked while reprogramming mclk */
1607 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1608 u32 active_crtcs;
1609 int active_crtc_count;
c913e23a 1610 int req_vblank;
839461d3 1611 bool vblank_sync;
c93bb85b
JG		 1612 fixed20_12 max_bandwidth;
1613 fixed20_12 igp_sideport_mclk;
1614 fixed20_12 igp_system_mclk;
1615 fixed20_12 igp_ht_link_clk;
1616 fixed20_12 igp_ht_link_width;
1617 fixed20_12 k8_bandwidth;
1618 fixed20_12 sideport_bandwidth;
1619 fixed20_12 ht_bandwidth;
1620 fixed20_12 core_bandwidth;
1621 fixed20_12 sclk;
f47299c5 1622 fixed20_12 mclk;
c93bb85b 1623 fixed20_12 needed_bandwidth;
0975b162 1624 struct radeon_power_state *power_state;
56278a8e
AD		 1625 /* number of valid power states */
1626 int num_power_states;
a48b9b4e
AD		 1627 int current_power_state_index;
1628 int current_clock_mode_index;
1629 int requested_power_state_index;
1630 int requested_clock_mode_index;
1631 int default_power_state_index;
1632 u32 current_sclk;
1633 u32 current_mclk;
2feea49a
AD		 1634 u16 current_vddc;
1635 u16 current_vddci;
9ace9f7b
AD		 1636 u32 default_sclk;
1637 u32 default_mclk;
2feea49a
AD		 1638 u16 default_vddc;
1639 u16 default_vddci;
29fb52ca 1640 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1641 /* selected pm method */
1642 enum radeon_pm_method pm_method;
1643 /* dynpm power management */
1644 struct delayed_work dynpm_idle_work;
1645 enum radeon_dynpm_state dynpm_state;
1646 enum radeon_dynpm_action dynpm_planned_action;
1647 unsigned long dynpm_action_timeout;
1648 bool dynpm_can_upclock;
1649 bool dynpm_can_downclock;
1650 /* profile-based power management */
1651 enum radeon_pm_profile_type profile;
1652 int profile_index;
1653 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1654 /* internal thermal controller on rv6xx+ */
1655 enum radeon_int_thermal_type int_thermal_type;
1656 struct device *int_hwmon_dev;
9b92d1ec
AD		 1657 /* fan control parameters */
1658 bool no_fan;
1659 u8 fan_pulses_per_revolution;
1660 u8 fan_min_rpm;
1661 u8 fan_max_rpm;
da321c8a
AD		 1662 /* dpm */
1663 bool dpm_enabled;
49abb266 1664 bool sysfs_initialized;
da321c8a 1665 struct radeon_dpm dpm;
c93bb85b
JG		 1666};
1667
a4c9e2ee
AD		 1668int radeon_pm_get_type_index(struct radeon_device *rdev,
1669 enum radeon_pm_state_type ps_type,
1670 int instance);
f2ba57b5
CK		 1671/*
1672 * UVD
1673 */
1674#define RADEON_MAX_UVD_HANDLES 10
1675#define RADEON_UVD_STACK_SIZE (1024*1024)
1676#define RADEON_UVD_HEAP_SIZE (1024*1024)
1677
1678struct radeon_uvd {
1679 struct radeon_bo *vcpu_bo;
1680 void *cpu_addr;
1681 uint64_t gpu_addr;
1682 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1683 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1684 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1685 struct delayed_work idle_work;
f2ba57b5
CK		 1686};
1687
1688int radeon_uvd_init(struct radeon_device *rdev);
1689void radeon_uvd_fini(struct radeon_device *rdev);
1690int radeon_uvd_suspend(struct radeon_device *rdev);
1691int radeon_uvd_resume(struct radeon_device *rdev);
1692int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1693 uint32_t handle, struct radeon_fence **fence);
1694int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1695 uint32_t handle, struct radeon_fence **fence);
3852752c
CK		 1696void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1697 uint32_t allowed_domains);
f2ba57b5
CK		 1698void radeon_uvd_free_handles(struct radeon_device *rdev,
1699 struct drm_file *filp);
1700int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1701void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1702int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1703 unsigned vclk, unsigned dclk,
1704 unsigned vco_min, unsigned vco_max,
1705 unsigned fb_factor, unsigned fb_mask,
1706 unsigned pd_min, unsigned pd_max,
1707 unsigned pd_even,
1708 unsigned *optimal_fb_div,
1709 unsigned *optimal_vclk_div,
1710 unsigned *optimal_dclk_div);
1711int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1712 unsigned cg_upll_func_cntl);
771fe6b9 1713
d93f7937
CK		 1714/*
1715 * VCE
1716 */
1717#define RADEON_MAX_VCE_HANDLES 16
d93f7937
CK		 1718
1719struct radeon_vce {
1720 struct radeon_bo *vcpu_bo;
d93f7937 1721 uint64_t gpu_addr;
98ccc291
CK		 1722 unsigned fw_version;
1723 unsigned fb_version;
d93f7937
CK		 1724 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1725 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
2fc5703a 1726 unsigned img_size[RADEON_MAX_VCE_HANDLES];
03afe6f6 1727 struct delayed_work idle_work;
a918efab 1728 uint32_t keyselect;
d93f7937
CK		 1729};
1730
1731int radeon_vce_init(struct radeon_device *rdev);
1732void radeon_vce_fini(struct radeon_device *rdev);
1733int radeon_vce_suspend(struct radeon_device *rdev);
1734int radeon_vce_resume(struct radeon_device *rdev);
1735int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1736 uint32_t handle, struct radeon_fence **fence);
1737int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1738 uint32_t handle, struct radeon_fence **fence);
1739void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
03afe6f6 1740void radeon_vce_note_usage(struct radeon_device *rdev);
2fc5703a 1741int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
d93f7937
CK		 1742int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1743bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1744 struct radeon_ring *ring,
1745 struct radeon_semaphore *semaphore,
1746 bool emit_wait);
1747void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1748void radeon_vce_fence_emit(struct radeon_device *rdev,
1749 struct radeon_fence *fence);
1750int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1751int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1752
b530602f 1753struct r600_audio_pin {
a92553ab
RM		 1754 int channels;
1755 int rate;
1756 int bits_per_sample;
1757 u8 status_bits;
1758 u8 category_code;
b530602f
AD		 1759 u32 offset;
1760 bool connected;
1761 u32 id;
1762};
1763
1764struct r600_audio {
1765 bool enabled;
1766 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1767 int num_pins;
1a626b68
SG		 1768 struct radeon_audio_funcs *hdmi_funcs;
1769 struct radeon_audio_funcs *dp_funcs;
1770 struct radeon_audio_basic_funcs *funcs;
a92553ab
RM		 1771};
1772
771fe6b9
JG		 1773/*
1774 * Benchmarking
1775 */
638dd7db 1776void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1777
1778
ecc0b326
MD		 1779/*
1780 * Testing
1781 */
1782void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1783void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1784 struct radeon_ring *cpA,
1785 struct radeon_ring *cpB);
60a7e396 1786void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326 1787
341cb9e4
CK		 1788/*
1789 * MMU Notifier
1790 */
5a1aa4b4 1791#if defined(CONFIG_MMU_NOTIFIER)
341cb9e4
CK		 1792int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1793void radeon_mn_unregister(struct radeon_bo *bo);
5a1aa4b4
RC		 1794#else
1795static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1796{
1797 return -ENODEV;
1798}
1799static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1800#endif
ecc0b326 1801
771fe6b9
JG		 1802/*
1803 * Debugfs
1804 */
4d8bf9ae
CK		 1805struct radeon_debugfs {
1806 struct drm_info_list *files;
1807 unsigned num_files;
1808};
1809
771fe6b9
JG		 1810int radeon_debugfs_add_files(struct radeon_device *rdev,
1811 struct drm_info_list *files,
1812 unsigned nfiles);
1813int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1814
76a0df85
CK		 1815/*
1816 * ASIC ring specific functions.
1817 */
1818struct radeon_asic_ring {
1819 /* ring read/write ptr handling */
1820 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1821 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1822 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1823
1824 /* validating and patching of IBs */
1825 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1826 int (*cs_parse)(struct radeon_cs_parser *p);
1827
1828 /* command emmit functions */
1829 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1830 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
72a9987e 1831 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1654b817 1832 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
76a0df85 1833 struct radeon_semaphore *semaphore, bool emit_wait);
faffaf62
CK		 1834 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1835 unsigned vm_id, uint64_t pd_addr);
76a0df85
CK		 1836
1837 /* testing functions */
1838 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1839 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1840 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1841
1842 /* deprecated */
1843 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1844};
771fe6b9
JG		 1845
1846/*
1847 * ASIC specific functions.
1848 */
1849struct radeon_asic {
068a117c 1850 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1851 void (*fini)(struct radeon_device *rdev);
1852 int (*resume)(struct radeon_device *rdev);
1853 int (*suspend)(struct radeon_device *rdev);
28d52043 1854 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1855 int (*asic_reset)(struct radeon_device *rdev);
124764f1
MD		 1856 /* Flush the HDP cache via MMIO */
1857 void (*mmio_hdp_flush)(struct radeon_device *rdev);
54e88e06
AD		 1858 /* check if 3D engine is idle */
1859 bool (*gui_idle)(struct radeon_device *rdev);
1860 /* wait for mc_idle */
1861 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1862 /* get the reference clock */
1863 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1864 /* get the gpu clock counter */
1865 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
4ce4728b
AD		 1866 /* get register for info ioctl */
1867 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
54e88e06 1868 /* gart */
c5b3b850
AD		 1869 struct {
1870 void (*tlb_flush)(struct radeon_device *rdev);
cb658906 1871 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
7f90fc96 1872 void (*set_page)(struct radeon_device *rdev, unsigned i,
cb658906 1873 uint64_t entry);
c5b3b850 1874 } gart;
05b07147
CK		 1875 struct {
1876 int (*init)(struct radeon_device *rdev);
1877 void (*fini)(struct radeon_device *rdev);
03f62abd
CK		 1878 void (*copy_pages)(struct radeon_device *rdev,
1879 struct radeon_ib *ib,
1880 uint64_t pe, uint64_t src,
1881 unsigned count);
1882 void (*write_pages)(struct radeon_device *rdev,
1883 struct radeon_ib *ib,
1884 uint64_t pe,
1885 uint64_t addr, unsigned count,
1886 uint32_t incr, uint32_t flags);
1887 void (*set_pages)(struct radeon_device *rdev,
1888 struct radeon_ib *ib,
1889 uint64_t pe,
1890 uint64_t addr, unsigned count,
1891 uint32_t incr, uint32_t flags);
1892 void (*pad_ib)(struct radeon_ib *ib);
05b07147 1893 } vm;
54e88e06 1894 /* ring specific callbacks */
d26678da 1895 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1896 /* irqs */
b35ea4ab
AD		 1897 struct {
1898 int (*set)(struct radeon_device *rdev);
1899 int (*process)(struct radeon_device *rdev);
1900 } irq;
54e88e06 1901 /* displays */
c79a49ca
AD		 1902 struct {
1903 /* display watermarks */
1904 void (*bandwidth_update)(struct radeon_device *rdev);
1905 /* get frame count */
1906 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1907 /* wait for vblank */
1908 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1909 /* set backlight level */
1910 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1911 /* get backlight level */
1912 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1913 /* audio callbacks */
1914 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1915 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1916 } display;
54e88e06 1917 /* copy functions for bo handling */
27cd7769 1918 struct {
57d20a43
CK		 1919 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1920 uint64_t src_offset,
1921 uint64_t dst_offset,
1922 unsigned num_gpu_pages,
1923 struct reservation_object *resv);
27cd7769 1924 u32 blit_ring_index;
57d20a43
CK		 1925 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1926 uint64_t src_offset,
1927 uint64_t dst_offset,
1928 unsigned num_gpu_pages,
1929 struct reservation_object *resv);
27cd7769
AD		 1930 u32 dma_ring_index;
1931 /* method used for bo copy */
57d20a43
CK		 1932 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1933 uint64_t src_offset,
1934 uint64_t dst_offset,
1935 unsigned num_gpu_pages,
1936 struct reservation_object *resv);
27cd7769
AD		 1937 /* ring used for bo copies */
1938 u32 copy_ring_index;
1939 } copy;
54e88e06 1940 /* surfaces */
9e6f3d02
AD		 1941 struct {
1942 int (*set_reg)(struct radeon_device *rdev, int reg,
1943 uint32_t tiling_flags, uint32_t pitch,
1944 uint32_t offset, uint32_t obj_size);
1945 void (*clear_reg)(struct radeon_device *rdev, int reg);
1946 } surface;
54e88e06 1947 /* hotplug detect */
901ea57d
AD		 1948 struct {
1949 void (*init)(struct radeon_device *rdev);
1950 void (*fini)(struct radeon_device *rdev);
1951 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1952 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1953 } hpd;
da321c8a 1954 /* static power management */
a02fa397
AD		 1955 struct {
1956 void (*misc)(struct radeon_device *rdev);
1957 void (*prepare)(struct radeon_device *rdev);
1958 void (*finish)(struct radeon_device *rdev);
1959 void (*init_profile)(struct radeon_device *rdev);
1960 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1961 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1962 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1963 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1964 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1965 int (*get_pcie_lanes)(struct radeon_device *rdev);
1966 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1967 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1968 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
b59b7333 1969 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
6bd1c385 1970 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1971 } pm;
da321c8a
AD		 1972 /* dynamic power management */
1973 struct {
1974 int (*init)(struct radeon_device *rdev);
1975 void (*setup_asic)(struct radeon_device *rdev);
1976 int (*enable)(struct radeon_device *rdev);
914a8987 1977 int (*late_enable)(struct radeon_device *rdev);
da321c8a 1978 void (*disable)(struct radeon_device *rdev);
84dd1928 1979 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1980 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1981 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1982 void (*display_configuration_changed)(struct radeon_device *rdev);
1983 void (*fini)(struct radeon_device *rdev);
1984 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1985 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1986 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1987 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1988 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1989 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1990 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1c71bda0 1991 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
a35a4b2b
OC		 1992 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
1993 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
1994 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
1995 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
d7dbce09
AD		 1996 u32 (*get_current_sclk)(struct radeon_device *rdev);
1997 u32 (*get_current_mclk)(struct radeon_device *rdev);
da321c8a 1998 } dpm;
6f34be50 1999 /* pageflipping */
0f9e006c 2000 struct {
157fa14d
CK		 2001 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
2002 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
0f9e006c 2003 } pflip;
771fe6b9
JG		 2004};
2005
21f9a437
JG		 2006/*
2007 * Asic structures
2008 */
551ebd83 2009struct r100_asic {
225758d8
JG		 2010 const unsigned *reg_safe_bm;
2011 unsigned reg_safe_bm_size;
2012 u32 hdp_cntl;
551ebd83
DA		 2013};
2014
21f9a437 2015struct r300_asic {
225758d8
JG		 2016 const unsigned *reg_safe_bm;
2017 unsigned reg_safe_bm_size;
2018 u32 resync_scratch;
2019 u32 hdp_cntl;
21f9a437
JG		 2020};
2021
2022struct r600_asic {
225758d8
JG		 2023 unsigned max_pipes;
2024 unsigned max_tile_pipes;
2025 unsigned max_simds;
2026 unsigned max_backends;
2027 unsigned max_gprs;
2028 unsigned max_threads;
2029 unsigned max_stack_entries;
2030 unsigned max_hw_contexts;
2031 unsigned max_gs_threads;
2032 unsigned sx_max_export_size;
2033 unsigned sx_max_export_pos_size;
2034 unsigned sx_max_export_smx_size;
2035 unsigned sq_num_cf_insts;
2036 unsigned tiling_nbanks;
2037 unsigned tiling_npipes;
2038 unsigned tiling_group_size;
e7aeeba6 2039 unsigned tile_config;
e55b9422 2040 unsigned backend_map;
65fcf668 2041 unsigned active_simds;
21f9a437
JG		 2042};
2043
2044struct rv770_asic {
225758d8
JG		 2045 unsigned max_pipes;
2046 unsigned max_tile_pipes;
2047 unsigned max_simds;
2048 unsigned max_backends;
2049 unsigned max_gprs;
2050 unsigned max_threads;
2051 unsigned max_stack_entries;
2052 unsigned max_hw_contexts;
2053 unsigned max_gs_threads;
2054 unsigned sx_max_export_size;
2055 unsigned sx_max_export_pos_size;
2056 unsigned sx_max_export_smx_size;
2057 unsigned sq_num_cf_insts;
2058 unsigned sx_num_of_sets;
2059 unsigned sc_prim_fifo_size;
2060 unsigned sc_hiz_tile_fifo_size;
2061 unsigned sc_earlyz_tile_fifo_fize;
2062 unsigned tiling_nbanks;
2063 unsigned tiling_npipes;
2064 unsigned tiling_group_size;
e7aeeba6 2065 unsigned tile_config;
e55b9422 2066 unsigned backend_map;
65fcf668 2067 unsigned active_simds;
21f9a437
JG		 2068};
2069
32fcdbf4
AD		 2070struct evergreen_asic {
2071 unsigned num_ses;
2072 unsigned max_pipes;
2073 unsigned max_tile_pipes;
2074 unsigned max_simds;
2075 unsigned max_backends;
2076 unsigned max_gprs;
2077 unsigned max_threads;
2078 unsigned max_stack_entries;
2079 unsigned max_hw_contexts;
2080 unsigned max_gs_threads;
2081 unsigned sx_max_export_size;
2082 unsigned sx_max_export_pos_size;
2083 unsigned sx_max_export_smx_size;
2084 unsigned sq_num_cf_insts;
2085 unsigned sx_num_of_sets;
2086 unsigned sc_prim_fifo_size;
2087 unsigned sc_hiz_tile_fifo_size;
2088 unsigned sc_earlyz_tile_fifo_size;
2089 unsigned tiling_nbanks;
2090 unsigned tiling_npipes;
2091 unsigned tiling_group_size;
e7aeeba6 2092 unsigned tile_config;
e55b9422 2093 unsigned backend_map;
65fcf668 2094 unsigned active_simds;
32fcdbf4
AD		 2095};
2096
fecf1d07
AD		 2097struct cayman_asic {
2098 unsigned max_shader_engines;
2099 unsigned max_pipes_per_simd;
2100 unsigned max_tile_pipes;
2101 unsigned max_simds_per_se;
2102 unsigned max_backends_per_se;
2103 unsigned max_texture_channel_caches;
2104 unsigned max_gprs;
2105 unsigned max_threads;
2106 unsigned max_gs_threads;
2107 unsigned max_stack_entries;
2108 unsigned sx_num_of_sets;
2109 unsigned sx_max_export_size;
2110 unsigned sx_max_export_pos_size;
2111 unsigned sx_max_export_smx_size;
2112 unsigned max_hw_contexts;
2113 unsigned sq_num_cf_insts;
2114 unsigned sc_prim_fifo_size;
2115 unsigned sc_hiz_tile_fifo_size;
2116 unsigned sc_earlyz_tile_fifo_size;
2117
2118 unsigned num_shader_engines;
2119 unsigned num_shader_pipes_per_simd;
2120 unsigned num_tile_pipes;
2121 unsigned num_simds_per_se;
2122 unsigned num_backends_per_se;
2123 unsigned backend_disable_mask_per_asic;
2124 unsigned backend_map;
2125 unsigned num_texture_channel_caches;
2126 unsigned mem_max_burst_length_bytes;
2127 unsigned mem_row_size_in_kb;
2128 unsigned shader_engine_tile_size;
2129 unsigned num_gpus;
2130 unsigned multi_gpu_tile_size;
2131
2132 unsigned tile_config;
65fcf668 2133 unsigned active_simds;
fecf1d07
AD		 2134};
2135
0a96d72b
AD		 2136struct si_asic {
2137 unsigned max_shader_engines;
0a96d72b 2138 unsigned max_tile_pipes;
1a8ca750
AD		 2139 unsigned max_cu_per_sh;
2140 unsigned max_sh_per_se;
0a96d72b
AD		 2141 unsigned max_backends_per_se;
2142 unsigned max_texture_channel_caches;
2143 unsigned max_gprs;
2144 unsigned max_gs_threads;
2145 unsigned max_hw_contexts;
2146 unsigned sc_prim_fifo_size_frontend;
2147 unsigned sc_prim_fifo_size_backend;
2148 unsigned sc_hiz_tile_fifo_size;
2149 unsigned sc_earlyz_tile_fifo_size;
2150
0a96d72b 2151 unsigned num_tile_pipes;
439a1cff 2152 unsigned backend_enable_mask;
0a96d72b
AD		 2153 unsigned backend_disable_mask_per_asic;
2154 unsigned backend_map;
2155 unsigned num_texture_channel_caches;
2156 unsigned mem_max_burst_length_bytes;
2157 unsigned mem_row_size_in_kb;
2158 unsigned shader_engine_tile_size;
2159 unsigned num_gpus;
2160 unsigned multi_gpu_tile_size;
2161
2162 unsigned tile_config;
64d7b8be 2163 uint32_t tile_mode_array[32];
65fcf668 2164 uint32_t active_cus;
0a96d72b
AD		 2165};
2166
8cc1a532
AD		 2167struct cik_asic {
2168 unsigned max_shader_engines;
2169 unsigned max_tile_pipes;
2170 unsigned max_cu_per_sh;
2171 unsigned max_sh_per_se;
2172 unsigned max_backends_per_se;
2173 unsigned max_texture_channel_caches;
2174 unsigned max_gprs;
2175 unsigned max_gs_threads;
2176 unsigned max_hw_contexts;
2177 unsigned sc_prim_fifo_size_frontend;
2178 unsigned sc_prim_fifo_size_backend;
2179 unsigned sc_hiz_tile_fifo_size;
2180 unsigned sc_earlyz_tile_fifo_size;
2181
2182 unsigned num_tile_pipes;
439a1cff 2183 unsigned backend_enable_mask;
8cc1a532
AD		 2184 unsigned backend_disable_mask_per_asic;
2185 unsigned backend_map;
2186 unsigned num_texture_channel_caches;
2187 unsigned mem_max_burst_length_bytes;
2188 unsigned mem_row_size_in_kb;
2189 unsigned shader_engine_tile_size;
2190 unsigned num_gpus;
2191 unsigned multi_gpu_tile_size;
2192
2193 unsigned tile_config;
39aee490 2194 uint32_t tile_mode_array[32];
32f79a8a 2195 uint32_t macrotile_mode_array[16];
65fcf668 2196 uint32_t active_cus;
8cc1a532
AD		 2197};
2198
068a117c
JG		 2199union radeon_asic_config {
2200 struct r300_asic r300;
551ebd83 2201 struct r100_asic r100;
3ce0a23d
JG		 2202 struct r600_asic r600;
2203 struct rv770_asic rv770;
32fcdbf4 2204 struct evergreen_asic evergreen;
fecf1d07 2205 struct cayman_asic cayman;
0a96d72b 2206 struct si_asic si;
8cc1a532 2207 struct cik_asic cik;
068a117c
JG		 2208};
2209
0a10c851
DV		 2210/*
2211 * asic initizalization from radeon_asic.c
2212 */
2213void radeon_agp_disable(struct radeon_device *rdev);
2214int radeon_asic_init(struct radeon_device *rdev);
2215
771fe6b9
JG		 2216
2217/*
2218 * IOCTL.
2219 */
2220int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2221 struct drm_file *filp);
2222int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2223 struct drm_file *filp);
f72a113a
CK		 2224int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2225 struct drm_file *filp);
771fe6b9
JG		 2226int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2227 struct drm_file *file_priv);
2228int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2229 struct drm_file *file_priv);
2230int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2231 struct drm_file *file_priv);
2232int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2233 struct drm_file *file_priv);
2234int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2235 struct drm_file *filp);
2236int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2237 struct drm_file *filp);
2238int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2239 struct drm_file *filp);
2240int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2241 struct drm_file *filp);
721604a1
JG		 2242int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2243 struct drm_file *filp);
bda72d58
MO		 2244int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2245 struct drm_file *filp);
771fe6b9 2246int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 2247int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2248 struct drm_file *filp);
2249int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2250 struct drm_file *filp);
771fe6b9 2251
16cdf04d
AD		 2252/* VRAM scratch page for HDP bug, default vram page */
2253struct r600_vram_scratch {
87cbf8f2
AD		 2254 struct radeon_bo *robj;
2255 volatile uint32_t *ptr;
16cdf04d 2256 u64 gpu_addr;
87cbf8f2 2257};
771fe6b9 2258
fd64ca8a
LT		 2259/*
2260 * ACPI
2261 */
2262struct radeon_atif_notification_cfg {
2263 bool enabled;
2264 int command_code;
2265};
2266
2267struct radeon_atif_notifications {
2268 bool display_switch;
2269 bool expansion_mode_change;
2270 bool thermal_state;
2271 bool forced_power_state;
2272 bool system_power_state;
2273 bool display_conf_change;
2274 bool px_gfx_switch;
2275 bool brightness_change;
2276 bool dgpu_display_event;
2277};
2278
2279struct radeon_atif_functions {
2280 bool system_params;
2281 bool sbios_requests;
2282 bool select_active_disp;
2283 bool lid_state;
2284 bool get_tv_standard;
2285 bool set_tv_standard;
2286 bool get_panel_expansion_mode;
2287 bool set_panel_expansion_mode;
2288 bool temperature_change;
2289 bool graphics_device_types;
2290};
2291
2292struct radeon_atif {
2293 struct radeon_atif_notifications notifications;
2294 struct radeon_atif_functions functions;
2295 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2296 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2297};
7a1619b9 2298
e3a15920
AD		 2299struct radeon_atcs_functions {
2300 bool get_ext_state;
2301 bool pcie_perf_req;
2302 bool pcie_dev_rdy;
2303 bool pcie_bus_width;
2304};
2305
2306struct radeon_atcs {
2307 struct radeon_atcs_functions functions;
2308};
2309
771fe6b9
JG		 2310/*
2311 * Core structure, functions and helpers.
2312 */
2313typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2314typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2315
2316struct radeon_device {
9f022ddf 2317 struct device *dev;
771fe6b9
JG		 2318 struct drm_device *ddev;
2319 struct pci_dev *pdev;
dee53e7f 2320 struct rw_semaphore exclusive_lock;
771fe6b9 2321 /* ASIC */
068a117c 2322 union radeon_asic_config config;
771fe6b9
JG		 2323 enum radeon_family family;
2324 unsigned long flags;
2325 int usec_timeout;
2326 enum radeon_pll_errata pll_errata;
2327 int num_gb_pipes;
f779b3e5 2328 int num_z_pipes;
771fe6b9
JG		 2329 int disp_priority;
2330 /* BIOS */
2331 uint8_t *bios;
2332 bool is_atom_bios;
2333 uint16_t bios_header_start;
4c788679 2334 struct radeon_bo *stollen_vga_memory;
771fe6b9 2335 /* Register mmio */
4c9bc75c
DA		 2336 resource_size_t rmmio_base;
2337 resource_size_t rmmio_size;
2c385151
DV		 2338 /* protects concurrent MM_INDEX/DATA based register access */
2339 spinlock_t mmio_idx_lock;
fe78118c
AD		 2340 /* protects concurrent SMC based register access */
2341 spinlock_t smc_idx_lock;
0a5b7b0b
AD		 2342 /* protects concurrent PLL register access */
2343 spinlock_t pll_idx_lock;
2344 /* protects concurrent MC register access */
2345 spinlock_t mc_idx_lock;
2346 /* protects concurrent PCIE register access */
2347 spinlock_t pcie_idx_lock;
2348 /* protects concurrent PCIE_PORT register access */
2349 spinlock_t pciep_idx_lock;
2350 /* protects concurrent PIF register access */
2351 spinlock_t pif_idx_lock;
2352 /* protects concurrent CG register access */
2353 spinlock_t cg_idx_lock;
2354 /* protects concurrent UVD register access */
2355 spinlock_t uvd_idx_lock;
2356 /* protects concurrent RCU register access */
2357 spinlock_t rcu_idx_lock;
2358 /* protects concurrent DIDT register access */
2359 spinlock_t didt_idx_lock;
2360 /* protects concurrent ENDPOINT (audio) register access */
2361 spinlock_t end_idx_lock;
a0533fbf 2362 void __iomem *rmmio;
771fe6b9
JG		 2363 radeon_rreg_t mc_rreg;
2364 radeon_wreg_t mc_wreg;
2365 radeon_rreg_t pll_rreg;
2366 radeon_wreg_t pll_wreg;
de1b2898 2367 uint32_t pcie_reg_mask;
771fe6b9
JG		 2368 radeon_rreg_t pciep_rreg;
2369 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2370 /* io port */
2371 void __iomem *rio_mem;
2372 resource_size_t rio_mem_size;
771fe6b9
JG		 2373 struct radeon_clock clock;
2374 struct radeon_mc mc;
2375 struct radeon_gart gart;
2376 struct radeon_mode_info mode_info;
2377 struct radeon_scratch scratch;
75efdee1 2378 struct radeon_doorbell doorbell;
771fe6b9 2379 struct radeon_mman mman;
7465280c 2380 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2381 wait_queue_head_t fence_queue;
954605ca 2382 unsigned fence_context;
d6999bc7 2383 struct mutex ring_lock;
e32eb50d 2384 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2385 bool ib_pool_ready;
2386 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2387 struct radeon_irq irq;
2388 struct radeon_asic *asic;
2389 struct radeon_gem gem;
c93bb85b 2390 struct radeon_pm pm;
f2ba57b5 2391 struct radeon_uvd uvd;
d93f7937 2392 struct radeon_vce vce;
f657c2a7 2393 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2394 struct radeon_wb wb;
3ce0a23d 2395 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2396 bool shutdown;
2397 bool suspend;
ad49f501 2398 bool need_dma32;
733289c2 2399 bool accel_working;
a0a53aa8 2400 bool fastfb_working; /* IGP feature*/
9bb39ff4 2401 bool needs_reset, in_reset;
e024e110 2402 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2403 const struct firmware *me_fw; /* all family ME firmware */
2404 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2405 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2406 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2407 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2408 const struct firmware *mec_fw; /* CIK MEC firmware */
f2c6b0f4 2409 const struct firmware *mec2_fw; /* KV MEC2 firmware */
21a93e13 2410 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2411 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2412 const struct firmware *uvd_fw; /* UVD firmware */
d93f7937 2413 const struct firmware *vce_fw; /* VCE firmware */
629bd33c 2414 bool new_fw;
16cdf04d 2415 struct r600_vram_scratch vram_scratch;
3e5cb98d 2416 int msi_enabled; /* msi enabled */
d8f60cfc 2417 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2418 struct radeon_rlc rlc;
963e81f9 2419 struct radeon_mec mec;
cb5d4166 2420 struct delayed_work hotplug_work;
de6284aa 2421 struct work_struct dp_work;
f122c610 2422 struct work_struct audio_work;
18917b60 2423 int num_crtc; /* number of crtcs */
40bacf16 2424 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
948bee3f 2425 bool has_uvd;
b530602f 2426 struct r600_audio audio; /* audio stuff */
ce8f5370 2427 struct notifier_block acpi_nb;
9eba4a93 2428 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2429 struct drm_file *hyperz_filp;
9eba4a93 2430 struct drm_file *cmask_filp;
f376b94f
AD		 2431 /* i2c buses */
2432 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2433 /* debugfs */
2434 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2435 unsigned debugfs_count;
721604a1
JG		 2436 /* virtual memory */
2437 struct radeon_vm_manager vm_manager;
6759a0a7 2438 struct mutex gpu_clock_mutex;
67e8e3f9
MO		 2439 /* memory stats */
2440 atomic64_t vram_usage;
2441 atomic64_t gtt_usage;
2442 atomic64_t num_bytes_moved;
72b9076b 2443 atomic_t gpu_reset_counter;
fd64ca8a
LT		 2444 /* ACPI interface */
2445 struct radeon_atif atif;
e3a15920 2446 struct radeon_atcs atcs;
f61d5b46
AD		 2447 /* srbm instance registers */
2448 struct mutex srbm_mutex;
1c0a4625
OG		 2449 /* GRBM index mutex. Protects concurrents access to GRBM index */
2450 struct mutex grbm_idx_mutex;
64d8a728
AD		 2451 /* clock, powergating flags */
2452 u32 cg_flags;
2453 u32 pg_flags;
10ebc0bc
DA		 2454
2455 struct dev_pm_domain vga_pm_domain;
2456 bool have_disp_power_ref;
4807c5a8 2457 u32 px_quirk_flags;
71ecc97e
AD		 2458
2459 /* tracking pinned memory */
2460 u64 vram_pin_size;
2461 u64 gart_pin_size;
341cb9e4 2462
e28740ec
OG		 2463 /* amdkfd interface */
2464 struct kfd_dev *kfd;
e28740ec 2465
341cb9e4
CK		 2466 struct mutex mn_lock;
2467 DECLARE_HASHTABLE(mn_hash, 7);
771fe6b9
JG		 2468};
2469
90c4cde9 2470bool radeon_is_px(struct drm_device *dev);
771fe6b9
JG		 2471int radeon_device_init(struct radeon_device *rdev,
2472 struct drm_device *ddev,
2473 struct pci_dev *pdev,
2474 uint32_t flags);
2475void radeon_device_fini(struct radeon_device *rdev);
2476int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2477
59bc1d89
LK		 2478#define RADEON_MIN_MMIO_SIZE 0x10000
2479
9e5acbc2
DV		 2480uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2481void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
59bc1d89
LK		 2482static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2483 bool always_indirect)
2484{
2485 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2486 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2487 return readl(((void __iomem *)rdev->rmmio) + reg);
9e5acbc2
DV		 2488 else
2489 return r100_mm_rreg_slow(rdev, reg);
59bc1d89 2490}
59bc1d89
LK		 2491static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2492 bool always_indirect)
2493{
2494 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2495 writel(v, ((void __iomem *)rdev->rmmio) + reg);
9e5acbc2
DV		 2496 else
2497 r100_mm_wreg_slow(rdev, reg, v);
59bc1d89
LK		 2498}
2499
6fcbef7a
AK		 2500u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2501void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2502
d5754ab8
AL		 2503u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2504void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
75efdee1 2505
4c788679
JG		 2506/*
2507 * Cast helper
2508 */
954605ca
ML		 2509extern const struct fence_ops radeon_fence_ops;
2510
2511static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2512{
2513 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2514
2515 if (__f->base.ops == &radeon_fence_ops)
2516 return __f;
2517
2518 return NULL;
2519}
771fe6b9
JG		 2520
2521/*
2522 * Registers read & write functions.
2523 */
a0533fbf
BH		 2524#define RREG8(reg) readb((rdev->rmmio) + (reg))
2525#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2526#define RREG16(reg) readw((rdev->rmmio) + (reg))
2527#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2528#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2529#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2530#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2531#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2532#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2533#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2534#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2535#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2536#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2537#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2538#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2539#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2540#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2541#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2542#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2543#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2544#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2545#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2546#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2547#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2548#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2549#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2550#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2551#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2552#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2553#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2554#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2555#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2556#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2557#define WREG32_P(reg, val, mask) \
2558 do { \
2559 uint32_t tmp_ = RREG32(reg); \
2560 tmp_ &= (mask); \
2561 tmp_ |= ((val) & ~(mask)); \
2562 WREG32(reg, tmp_); \
2563 } while (0)
d5169fc4 2564#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2565#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2566#define WREG32_PLL_P(reg, val, mask) \
2567 do { \
2568 uint32_t tmp_ = RREG32_PLL(reg); \
2569 tmp_ &= (mask); \
2570 tmp_ |= ((val) & ~(mask)); \
2571 WREG32_PLL(reg, tmp_); \
2572 } while (0)
b7af630c
CK		 2573#define WREG32_SMC_P(reg, val, mask) \
2574 do { \
2575 uint32_t tmp_ = RREG32_SMC(reg); \
2576 tmp_ &= (mask); \
2577 tmp_ |= ((val) & ~(mask)); \
2578 WREG32_SMC(reg, tmp_); \
2579 } while (0)
2ef9bdfe 2580#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2581#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2582#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2583
d5754ab8
AL		 2584#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2585#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
75efdee1 2586
de1b2898 2587/*
9e5acbc2
DV		 2588 * Indirect registers accessors.
2589 * They used to be inlined, but this increases code size by ~65 kbytes.
2590 * Since each performs a pair of MMIO ops
2591 * within a spin_lock_irqsave/spin_unlock_irqrestore region,
2592 * the cost of call+ret is almost negligible. MMIO and locking
2593 * costs several dozens of cycles each at best, call+ret is ~5 cycles.
de1b2898 2594 */
9e5acbc2
DV		 2595uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2596void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2597u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2598void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2599u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2600void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2601u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2602void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2603u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2604void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2605u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2606void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2607u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2608void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2609u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2610void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1d58234d 2611
771fe6b9
JG		 2612void r100_pll_errata_after_index(struct radeon_device *rdev);
2613
2614
2615/*
2616 * ASICs helpers.
2617 */
b995e433
DA		 2618#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2619 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2620#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2621 (rdev->family == CHIP_RV200) || \
2622 (rdev->family == CHIP_RS100) || \
2623 (rdev->family == CHIP_RS200) || \
2624 (rdev->family == CHIP_RV250) || \
2625 (rdev->family == CHIP_RV280) || \
2626 (rdev->family == CHIP_RS300))
2627#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2628 (rdev->family == CHIP_RV350) || \
2629 (rdev->family == CHIP_R350) || \
2630 (rdev->family == CHIP_RV380) || \
2631 (rdev->family == CHIP_R420) || \
2632 (rdev->family == CHIP_R423) || \
2633 (rdev->family == CHIP_RV410) || \
2634 (rdev->family == CHIP_RS400) || \
2635 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2636#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2637 (rdev->ddev->pdev->device == 0x9443) || \
2638 (rdev->ddev->pdev->device == 0x944B) || \
2639 (rdev->ddev->pdev->device == 0x9506) || \
2640 (rdev->ddev->pdev->device == 0x9509) || \
2641 (rdev->ddev->pdev->device == 0x950F) || \
2642 (rdev->ddev->pdev->device == 0x689C) || \
2643 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2644#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2645#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2646 (rdev->family == CHIP_RS690) || \
2647 (rdev->family == CHIP_RS740) || \
2648 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2649#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2650#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2651#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2652#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2653 (rdev->flags & RADEON_IS_IGP))
1fe18305 2654#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2655#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2656#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2657 (rdev->flags & RADEON_IS_IGP))
624d3524 2658#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2659#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2660#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
be0949f5
AD		 2661#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2662#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
89d2618d
AD		 2663#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2664 (rdev->family == CHIP_MULLINS))
771fe6b9 2665
dc50ba7f
AD		 2666#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2667 (rdev->ddev->pdev->device == 0x6850) || \
2668 (rdev->ddev->pdev->device == 0x6858) || \
2669 (rdev->ddev->pdev->device == 0x6859) || \
2670 (rdev->ddev->pdev->device == 0x6840) || \
2671 (rdev->ddev->pdev->device == 0x6841) || \
2672 (rdev->ddev->pdev->device == 0x6842) || \
2673 (rdev->ddev->pdev->device == 0x6843))
2674
771fe6b9
JG		 2675/*
2676 * BIOS helpers.
2677 */
2678#define RBIOS8(i) (rdev->bios[i])
2679#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2680#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2681
2682int radeon_combios_init(struct radeon_device *rdev);
2683void radeon_combios_fini(struct radeon_device *rdev);
2684int radeon_atombios_init(struct radeon_device *rdev);
2685void radeon_atombios_fini(struct radeon_device *rdev);
2686
2687
2688/*
2689 * RING helpers.
2690 */
edf0ac7c
DH		 2691
2692/**
2693 * radeon_ring_write - write a value to the ring
2694 *
2695 * @ring: radeon_ring structure holding ring information
2696 * @v: dword (dw) value to write
2697 *
2698 * Write a value to the requested ring buffer (all asics).
2699 */
e32eb50d 2700static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2701{
edf0ac7c
DH		 2702 if (ring->count_dw <= 0)
2703 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2704
e32eb50d
CK		 2705 ring->ring[ring->wptr++] = v;
2706 ring->wptr &= ring->ptr_mask;
2707 ring->count_dw--;
2708 ring->ring_free_dw--;
771fe6b9 2709}
771fe6b9
JG		 2710
2711/*
2712 * ASICs macro.
2713 */
068a117c 2714#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2715#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2716#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2717#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2718#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2719#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2720#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850 2721#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
cb658906
MD		 2722#define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2723#define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
05b07147
CK		 2724#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2725#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
03f62abd
CK		 2726#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2727#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2728#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2729#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
76a0df85
CK		 2730#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2731#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2732#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2733#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2734#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2735#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
faffaf62 2736#define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
76a0df85
CK		 2737#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2738#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2739#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2740#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2741#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2742#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2743#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2744#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2745#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2746#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2747#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2748#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
57d20a43
CK		 2749#define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2750#define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2751#define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
27cd7769
AD		 2752#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2753#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2754#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2755#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2756#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2757#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2758#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2759#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2760#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2761#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2762#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
b59b7333 2763#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
6bd1c385 2764#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2765#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2766#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2767#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2768#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2769#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2770#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2771#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2772#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2773#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2774#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2775#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2776#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2777#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8 2778#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
157fa14d 2779#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
69b62ad8
AD		 2780#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2781#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2782#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2783#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
4ce4728b 2784#define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
da321c8a
AD		 2785#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2786#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2787#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
914a8987 2788#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
da321c8a 2789#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2790#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2791#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2792#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2793#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2794#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2795#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2796#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2797#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2798#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2799#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2800#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2801#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
1c71bda0 2802#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
d7dbce09
AD		 2803#define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2804#define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
771fe6b9 2805
6cf8a3f5 2806/* Common functions */
700a0cc0 2807/* AGP */
90aca4d2 2808extern int radeon_gpu_reset(struct radeon_device *rdev);
1a0041b8 2809extern void radeon_pci_config_reset(struct radeon_device *rdev);
410a3418 2810extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2811extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2812extern int radeon_modeset_init(struct radeon_device *rdev);
2813extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2814extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2815extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2816extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2817extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2818extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2819extern void radeon_wb_fini(struct radeon_device *rdev);
2820extern int radeon_wb_init(struct radeon_device *rdev);
2821extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2822extern void radeon_surface_init(struct radeon_device *rdev);
2823extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2824extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2825extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2826extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2827extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
f72a113a
CK		 2828extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2829 uint32_t flags);
2830extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2831extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
d594e46a
JG		 2832extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2833extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
10ebc0bc
DA		 2834extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2835extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
53595338 2836extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2837extern void radeon_program_register_sequence(struct radeon_device *rdev,
2838 const u32 *registers,
2839 const u32 array_size);
6cf8a3f5 2840
721604a1
JG		 2841/*
2842 * vm
2843 */
2844int radeon_vm_manager_init(struct radeon_device *rdev);
2845void radeon_vm_manager_fini(struct radeon_device *rdev);
6d2f2944 2846int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2847void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1d0c0942 2848struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
df0af440
CK		 2849 struct radeon_vm *vm,
2850 struct list_head *head);
ee60e29f
CK		 2851struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2852 struct radeon_vm *vm, int ring);
fa688343
CK		 2853void radeon_vm_flush(struct radeon_device *rdev,
2854 struct radeon_vm *vm,
ad1a58a4 2855 int ring, struct radeon_fence *fence);
ee60e29f
CK		 2856void radeon_vm_fence(struct radeon_device *rdev,
2857 struct radeon_vm *vm,
2858 struct radeon_fence *fence);
dce34bfd 2859uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
6d2f2944
CK		 2860int radeon_vm_update_page_directory(struct radeon_device *rdev,
2861 struct radeon_vm *vm);
036bf46a
CK		 2862int radeon_vm_clear_freed(struct radeon_device *rdev,
2863 struct radeon_vm *vm);
e31ad969
CK		 2864int radeon_vm_clear_invalids(struct radeon_device *rdev,
2865 struct radeon_vm *vm);
9c57a6bd 2866int radeon_vm_bo_update(struct radeon_device *rdev,
036bf46a 2867 struct radeon_bo_va *bo_va,
9c57a6bd 2868 struct ttm_mem_reg *mem);
721604a1
JG		 2869void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2870 struct radeon_bo *bo);
421ca7ab
CK		 2871struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2872 struct radeon_bo *bo);
e971bd5e
CK		 2873struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2874 struct radeon_vm *vm,
2875 struct radeon_bo *bo);
2876int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2877 struct radeon_bo_va *bo_va,
2878 uint64_t offset,
2879 uint32_t flags);
036bf46a
CK		 2880void radeon_vm_bo_rmv(struct radeon_device *rdev,
2881 struct radeon_bo_va *bo_va);
721604a1 2882
f122c610
AD		 2883/* audio */
2884void r600_audio_update_hdmi(struct work_struct *work);
b530602f
AD		 2885struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2886struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
832eafaf
AD		 2887void r600_audio_enable(struct radeon_device *rdev,
2888 struct r600_audio_pin *pin,
d3d8c141 2889 u8 enable_mask);
832eafaf
AD		 2890void dce6_audio_enable(struct radeon_device *rdev,
2891 struct r600_audio_pin *pin,
d3d8c141 2892 u8 enable_mask);
721604a1 2893
16cdf04d
AD		 2894/*
2895 * R600 vram scratch functions
2896 */
2897int r600_vram_scratch_init(struct radeon_device *rdev);
2898void r600_vram_scratch_fini(struct radeon_device *rdev);
2899
285484e2
JG		 2900/*
2901 * r600 cs checking helper
2902 */
2903unsigned r600_mip_minify(unsigned size, unsigned level);
2904bool r600_fmt_is_valid_color(u32 format);
2905bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2906int r600_fmt_get_blocksize(u32 format);
2907int r600_fmt_get_nblocksx(u32 format, u32 w);
2908int r600_fmt_get_nblocksy(u32 format, u32 h);
2909
3574dda4
DV		 2910/*
2911 * r600 functions used by radeon_encoder.c
2912 */
1b688d08
RM		 2913struct radeon_hdmi_acr {
2914 u32 clock;
2915
2916 int n_32khz;
2917 int cts_32khz;
2918
2919 int n_44_1khz;
2920 int cts_44_1khz;
2921
2922 int n_48khz;
2923 int cts_48khz;
2924
2925};
2926
e55d3e6c
RM		 2927extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2928
416a2bd2
AD		 2929extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2930 u32 tiling_pipe_num,
2931 u32 max_rb_num,
2932 u32 total_max_rb_num,
2933 u32 enabled_rb_mask);
fe251e2f 2934
e55d3e6c
RM		 2935/*
2936 * evergreen functions used by radeon_encoder.c
2937 */
2938
0af62b01 2939extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2940extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2941
c4917074
AD		 2942/* radeon_acpi.c */
2943#if defined(CONFIG_ACPI)
2944extern int radeon_acpi_init(struct radeon_device *rdev);
2945extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2946extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2947extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2948 u8 perf_req, bool advertise);
dc50ba7f 2949extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2950#else
2951static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2952static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2953#endif
d7a2952f 2954
c38f34b5
IH		 2955int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2956 struct radeon_cs_packet *pkt,
2957 unsigned idx);
9ffb7a6d 2958bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2959void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2960 struct radeon_cs_packet *pkt);
e9716993 2961int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
1d0c0942 2962 struct radeon_bo_list **cs_reloc,
e9716993 2963 int nomm);
40592a17
IH		 2964int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2965 uint32_t *vline_start_end,
2966 uint32_t *vline_status);
c38f34b5 2967
4c788679
JG		 2968#include "radeon_object.h"
2969
771fe6b9 2970#endif
Linux kernel - Deliverables
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