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drm/radeon: rework UVD writeback & [rw]ptr handling
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
a18cee15 96extern int radeon_msi;
3368ff0c 97extern int radeon_lockup_timeout;
a0a53aa8 98extern int radeon_fastfb;
da321c8a 99extern int radeon_dpm;
1294d4a3 100extern int radeon_aspm;
771fe6b9
JG		 101
102/*
103 * Copy from radeon_drv.h so we don't have to include both and have conflicting
104 * symbol;
105 */
bb635567
JG		 106#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
107#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 108/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 109#define RADEON_IB_POOL_SIZE 16
110#define RADEON_DEBUGFS_MAX_COMPONENTS 32
111#define RADEONFB_CONN_LIMIT 4
112#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 113
1b37078b 114/* max number of rings */
f2ba57b5 115#define RADEON_NUM_RINGS 6
bb635567
JG		 116
117/* fence seq are set to this number when signaled */
118#define RADEON_FENCE_SIGNALED_SEQ 0LL
1b37078b
AD		 119
120/* internal ring indices */
121/* r1xx+ has gfx CP ring */
f2ba57b5 122#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 123
124/* cayman has 2 compute CP rings */
f2ba57b5
CK		 125#define CAYMAN_RING_TYPE_CP1_INDEX 1
126#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 127
4d75658b
AD		 128/* R600+ has an async dma ring */
129#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 130/* cayman add a second async dma ring */
131#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 132
f2ba57b5
CK		 133/* R600+ */
134#define R600_RING_TYPE_UVD_INDEX 5
135
721604a1 136/* hardcode those limit for now */
ca19f21e 137#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 138#define RADEON_VA_RESERVED_SIZE (8 << 20)
139#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 140
ec46c76d
AD		 141/* reset flags */
142#define RADEON_RESET_GFX (1 << 0)
143#define RADEON_RESET_COMPUTE (1 << 1)
144#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 145#define RADEON_RESET_CP (1 << 3)
146#define RADEON_RESET_GRBM (1 << 4)
147#define RADEON_RESET_DMA1 (1 << 5)
148#define RADEON_RESET_RLC (1 << 6)
149#define RADEON_RESET_SEM (1 << 7)
150#define RADEON_RESET_IH (1 << 8)
151#define RADEON_RESET_VMC (1 << 9)
152#define RADEON_RESET_MC (1 << 10)
153#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 154
22c775ce
AD		 155/* CG block flags */
156#define RADEON_CG_BLOCK_GFX (1 << 0)
157#define RADEON_CG_BLOCK_MC (1 << 1)
158#define RADEON_CG_BLOCK_SDMA (1 << 2)
159#define RADEON_CG_BLOCK_UVD (1 << 3)
160#define RADEON_CG_BLOCK_VCE (1 << 4)
161#define RADEON_CG_BLOCK_HDP (1 << 5)
162
9e05fa1d
AD		 163/* max cursor sizes (in pixels) */
164#define CURSOR_WIDTH 64
165#define CURSOR_HEIGHT 64
166
167#define CIK_CURSOR_WIDTH 128
168#define CIK_CURSOR_HEIGHT 128
169
771fe6b9
JG		 170/*
171 * Errata workarounds.
172 */
173enum radeon_pll_errata {
174 CHIP_ERRATA_R300_CG = 0x00000001,
175 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
176 CHIP_ERRATA_PLL_DELAY = 0x00000004
177};
178
179
180struct radeon_device;
181
182
183/*
184 * BIOS.
185 */
186bool radeon_get_bios(struct radeon_device *rdev);
187
188/*
3ce0a23d 189 * Dummy page
771fe6b9 190 */
3ce0a23d
JG		 191struct radeon_dummy_page {
192 struct page *page;
193 dma_addr_t addr;
194};
195int radeon_dummy_page_init(struct radeon_device *rdev);
196void radeon_dummy_page_fini(struct radeon_device *rdev);
197
771fe6b9 198
3ce0a23d
JG		 199/*
200 * Clocks
201 */
771fe6b9
JG		 202struct radeon_clock {
203 struct radeon_pll p1pll;
204 struct radeon_pll p2pll;
bcc1c2a1 205 struct radeon_pll dcpll;
771fe6b9
JG		 206 struct radeon_pll spll;
207 struct radeon_pll mpll;
208 /* 10 Khz units */
209 uint32_t default_mclk;
210 uint32_t default_sclk;
bcc1c2a1 211 uint32_t default_dispclk;
4489cd62 212 uint32_t current_dispclk;
bcc1c2a1 213 uint32_t dp_extclk;
b20f9bef 214 uint32_t max_pixel_clock;
771fe6b9
JG		 215};
216
7433874e
RM		 217/*
218 * Power management
219 */
220int radeon_pm_init(struct radeon_device *rdev);
29fb52ca 221void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 222void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 223void radeon_pm_suspend(struct radeon_device *rdev);
224void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 225void radeon_combios_get_power_modes(struct radeon_device *rdev);
226void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 227int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
228 u8 clock_type,
229 u32 clock,
230 bool strobe_mode,
231 struct atom_clock_dividers *dividers);
eaa778af
AD		 232int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
233 u32 clock,
234 bool strobe_mode,
235 struct atom_mpll_param *mpll_param);
8a83ec5e 236void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 237int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
238 u16 voltage_level, u8 voltage_type,
239 u32 *gpio_value, u32 *gpio_mask);
240void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
241 u32 eng_clock, u32 mem_clock);
242int radeon_atom_get_voltage_step(struct radeon_device *rdev,
243 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 244int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
245 u16 voltage_id, u16 *voltage);
beb79f40
AD		 246int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
247 u16 *voltage,
248 u16 leakage_idx);
cc8dbbb4
AD		 249int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
250 u16 *leakage_id);
251int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
252 u16 *vddc, u16 *vddci,
253 u16 virtual_voltage_id,
254 u16 vbios_voltage_id);
ae5b0abb
AD		 255int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
256 u8 voltage_type,
257 u16 nominal_voltage,
258 u16 *true_voltage);
259int radeon_atom_get_min_voltage(struct radeon_device *rdev,
260 u8 voltage_type, u16 *min_voltage);
261int radeon_atom_get_max_voltage(struct radeon_device *rdev,
262 u8 voltage_type, u16 *max_voltage);
263int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 264 u8 voltage_type, u8 voltage_mode,
ae5b0abb 265 struct atom_voltage_table *voltage_table);
58653abd
AD		 266bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
267 u8 voltage_type, u8 voltage_mode);
ae5b0abb
AD		 268void radeon_atom_update_memory_dll(struct radeon_device *rdev,
269 u32 mem_clock);
270void radeon_atom_set_ac_timing(struct radeon_device *rdev,
271 u32 mem_clock);
272int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
273 u8 module_index,
274 struct atom_mc_reg_table *reg_table);
275int radeon_atom_get_memory_info(struct radeon_device *rdev,
276 u8 module_index, struct atom_memory_info *mem_info);
277int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
278 bool gddr5, u8 module_index,
279 struct atom_memory_clock_range_table *mclk_range_table);
280int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
281 u16 voltage_id, u16 *voltage);
f892034a 282void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 283extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
284 unsigned *bankh, unsigned *mtaspect,
285 unsigned *tile_split);
3ce0a23d 286
771fe6b9
JG		 287/*
288 * Fences.
289 */
290struct radeon_fence_driver {
291 uint32_t scratch_reg;
30eb77f4
JG		 292 uint64_t gpu_addr;
293 volatile uint32_t *cpu_addr;
68e250b7
CK		 294 /* sync_seq is protected by ring emission lock */
295 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 296 atomic64_t last_seq;
36abacae 297 unsigned long last_activity;
0a0c7596 298 bool initialized;
771fe6b9
JG		 299};
300
301struct radeon_fence {
302 struct radeon_device *rdev;
303 struct kref kref;
771fe6b9 304 /* protected by radeon_fence.lock */
bb635567 305 uint64_t seq;
7465280c 306 /* RB, DMA, etc. */
bb635567 307 unsigned ring;
771fe6b9
JG		 308};
309
30eb77f4
JG		 310int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
311int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 312void radeon_fence_driver_fini(struct radeon_device *rdev);
76903b96 313void radeon_fence_driver_force_completion(struct radeon_device *rdev);
876dc9f3 314int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 315void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 316bool radeon_fence_signaled(struct radeon_fence *fence);
317int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
8a47cc9e 318int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
5f8f635e 319int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
0085c950
JG		 320int radeon_fence_wait_any(struct radeon_device *rdev,
321 struct radeon_fence **fences,
322 bool intr);
771fe6b9
JG		 323struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
324void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 325unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 326bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
327void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
328static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
329 struct radeon_fence *b)
330{
331 if (!a) {
332 return b;
333 }
334
335 if (!b) {
336 return a;
337 }
338
339 BUG_ON(a->ring != b->ring);
340
341 if (a->seq > b->seq) {
342 return a;
343 } else {
344 return b;
345 }
346}
771fe6b9 347
ee60e29f
CK		 348static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
349 struct radeon_fence *b)
350{
351 if (!a) {
352 return false;
353 }
354
355 if (!b) {
356 return true;
357 }
358
359 BUG_ON(a->ring != b->ring);
360
361 return a->seq < b->seq;
362}
363
e024e110
DA		 364/*
365 * Tiling registers
366 */
367struct radeon_surface_reg {
4c788679 368 struct radeon_bo *bo;
e024e110
DA		 369};
370
371#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 372
373/*
4c788679 374 * TTM.
771fe6b9 375 */
4c788679
JG		 376struct radeon_mman {
377 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 378 struct drm_global_reference mem_global_ref;
4c788679 379 struct ttm_bo_device bdev;
0a0c7596
JG		 380 bool mem_global_referenced;
381 bool initialized;
4c788679
JG		 382};
383
721604a1
JG		 384/* bo virtual address in a specific vm */
385struct radeon_bo_va {
e971bd5e 386 /* protected by bo being reserved */
721604a1 387 struct list_head bo_list;
721604a1
JG		 388 uint64_t soffset;
389 uint64_t eoffset;
390 uint32_t flags;
391 bool valid;
e971bd5e
CK		 392 unsigned ref_count;
393
394 /* protected by vm mutex */
395 struct list_head vm_list;
396
397 /* constant after initialization */
398 struct radeon_vm *vm;
399 struct radeon_bo *bo;
721604a1
JG		 400};
401
4c788679
JG		 402struct radeon_bo {
403 /* Protected by gem.mutex */
404 struct list_head list;
405 /* Protected by tbo.reserved */
312ea8da
JG		 406 u32 placements[3];
407 struct ttm_placement placement;
4c788679
JG		 408 struct ttm_buffer_object tbo;
409 struct ttm_bo_kmap_obj kmap;
410 unsigned pin_count;
411 void *kptr;
412 u32 tiling_flags;
413 u32 pitch;
414 int surface_reg;
721604a1
JG		 415 /* list of all virtual address to which this bo
416 * is associated to
417 */
418 struct list_head va;
4c788679
JG		 419 /* Constant after initialization */
420 struct radeon_device *rdev;
441921d5 421 struct drm_gem_object gem_base;
63bc620b 422
409851f4
JG		 423 struct ttm_bo_kmap_obj dma_buf_vmap;
424 pid_t pid;
4c788679 425};
7e4d15d9 426#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 427
4c788679 428struct radeon_bo_list {
147666fb 429 struct ttm_validate_buffer tv;
4c788679 430 struct radeon_bo *bo;
771fe6b9 431 uint64_t gpu_offset;
4474f3a9
CK		 432 bool written;
433 unsigned domain;
434 unsigned alt_domain;
4c788679 435 u32 tiling_flags;
771fe6b9
JG		 436};
437
409851f4
JG		 438int radeon_gem_debugfs_init(struct radeon_device *rdev);
439
b15ba512
JG		 440/* sub-allocation manager, it has to be protected by another lock.
441 * By conception this is an helper for other part of the driver
442 * like the indirect buffer or semaphore, which both have their
443 * locking.
444 *
445 * Principe is simple, we keep a list of sub allocation in offset
446 * order (first entry has offset == 0, last entry has the highest
447 * offset).
448 *
449 * When allocating new object we first check if there is room at
450 * the end total_size - (last_object_offset + last_object_size) >=
451 * alloc_size. If so we allocate new object there.
452 *
453 * When there is not enough room at the end, we start waiting for
454 * each sub object until we reach object_offset+object_size >=
455 * alloc_size, this object then become the sub object we return.
456 *
457 * Alignment can't be bigger than page size.
458 *
459 * Hole are not considered for allocation to keep things simple.
460 * Assumption is that there won't be hole (all object on same
461 * alignment).
462 */
463struct radeon_sa_manager {
bfb38d35 464 wait_queue_head_t wq;
b15ba512 465 struct radeon_bo *bo;
c3b7fe8b
CK		 466 struct list_head *hole;
467 struct list_head flist[RADEON_NUM_RINGS];
468 struct list_head olist;
b15ba512
JG		 469 unsigned size;
470 uint64_t gpu_addr;
471 void *cpu_ptr;
472 uint32_t domain;
6c4f978b 473 uint32_t align;
b15ba512
JG		 474};
475
476struct radeon_sa_bo;
477
478/* sub-allocation buffer */
479struct radeon_sa_bo {
c3b7fe8b
CK		 480 struct list_head olist;
481 struct list_head flist;
b15ba512 482 struct radeon_sa_manager *manager;
e6661a96
CK		 483 unsigned soffset;
484 unsigned eoffset;
557017a0 485 struct radeon_fence *fence;
b15ba512
JG		 486};
487
771fe6b9
JG		 488/*
489 * GEM objects.
490 */
491struct radeon_gem {
4c788679 492 struct mutex mutex;
771fe6b9
JG		 493 struct list_head objects;
494};
495
496int radeon_gem_init(struct radeon_device *rdev);
497void radeon_gem_fini(struct radeon_device *rdev);
498int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 499 int alignment, int initial_domain,
500 bool discardable, bool kernel,
501 struct drm_gem_object **obj);
771fe6b9 502
ff72145b
DA		 503int radeon_mode_dumb_create(struct drm_file *file_priv,
504 struct drm_device *dev,
505 struct drm_mode_create_dumb *args);
506int radeon_mode_dumb_mmap(struct drm_file *filp,
507 struct drm_device *dev,
508 uint32_t handle, uint64_t *offset_p);
509int radeon_mode_dumb_destroy(struct drm_file *file_priv,
510 struct drm_device *dev,
511 uint32_t handle);
771fe6b9 512
c1341e52
JG		 513/*
514 * Semaphores.
515 */
c1341e52
JG		 516/* everything here is constant */
517struct radeon_semaphore {
a8c05940
JG		 518 struct radeon_sa_bo *sa_bo;
519 signed waiters;
c1341e52 520 uint64_t gpu_addr;
c1341e52
JG		 521};
522
c1341e52
JG		 523int radeon_semaphore_create(struct radeon_device *rdev,
524 struct radeon_semaphore **semaphore);
525void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
526 struct radeon_semaphore *semaphore);
527void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
528 struct radeon_semaphore *semaphore);
8f676c4c
CK		 529int radeon_semaphore_sync_rings(struct radeon_device *rdev,
530 struct radeon_semaphore *semaphore,
220907d9 531 int signaler, int waiter);
c1341e52 532void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 533 struct radeon_semaphore **semaphore,
a8c05940 534 struct radeon_fence *fence);
c1341e52 535
771fe6b9
JG		 536/*
537 * GART structures, functions & helpers
538 */
539struct radeon_mc;
540
a77f1718 541#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 542#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 543#define RADEON_GPU_PAGE_SHIFT 12
721604a1 544#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 545
771fe6b9
JG		 546struct radeon_gart {
547 dma_addr_t table_addr;
c9a1be96
JG		 548 struct radeon_bo *robj;
549 void *ptr;
771fe6b9
JG		 550 unsigned num_gpu_pages;
551 unsigned num_cpu_pages;
552 unsigned table_size;
771fe6b9
JG		 553 struct page **pages;
554 dma_addr_t *pages_addr;
555 bool ready;
556};
557
558int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
559void radeon_gart_table_ram_free(struct radeon_device *rdev);
560int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
561void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 562int radeon_gart_table_vram_pin(struct radeon_device *rdev);
563void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 564int radeon_gart_init(struct radeon_device *rdev);
565void radeon_gart_fini(struct radeon_device *rdev);
566void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
567 int pages);
568int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516
KRW		 569 int pages, struct page **pagelist,
570 dma_addr_t *dma_addr);
c9a1be96 571void radeon_gart_restore(struct radeon_device *rdev);
771fe6b9
JG		 572
573
574/*
575 * GPU MC structures, functions & helpers
576 */
577struct radeon_mc {
578 resource_size_t aper_size;
579 resource_size_t aper_base;
580 resource_size_t agp_base;
7a50f01a
DA		 581 /* for some chips with <= 32MB we need to lie
582 * about vram size near mc fb location */
3ce0a23d 583 u64 mc_vram_size;
d594e46a 584 u64 visible_vram_size;
3ce0a23d
JG		 585 u64 gtt_size;
586 u64 gtt_start;
587 u64 gtt_end;
3ce0a23d
JG		 588 u64 vram_start;
589 u64 vram_end;
771fe6b9 590 unsigned vram_width;
3ce0a23d 591 u64 real_vram_size;
771fe6b9
JG		 592 int vram_mtrr;
593 bool vram_is_ddr;
d594e46a 594 bool igp_sideport_enabled;
8d369bb1 595 u64 gtt_base_align;
9ed8b1f9 596 u64 mc_mask;
771fe6b9
JG		 597};
598
06b6476d
AD		 599bool radeon_combios_sideport_present(struct radeon_device *rdev);
600bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 601
602/*
603 * GPU scratch registers structures, functions & helpers
604 */
605struct radeon_scratch {
606 unsigned num_reg;
724c80e1 607 uint32_t reg_base;
771fe6b9
JG		 608 bool free[32];
609 uint32_t reg[32];
610};
611
612int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
613void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
614
75efdee1
AD		 615/*
616 * GPU doorbell structures, functions & helpers
617 */
618struct radeon_doorbell {
619 u32 num_pages;
620 bool free[1024];
621 /* doorbell mmio */
622 resource_size_t base;
623 resource_size_t size;
624 void __iomem *ptr;
625};
626
627int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
628void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771fe6b9
JG		 629
630/*
631 * IRQS.
632 */
6f34be50
AD		 633
634struct radeon_unpin_work {
635 struct work_struct work;
636 struct radeon_device *rdev;
637 int crtc_id;
638 struct radeon_fence *fence;
639 struct drm_pending_vblank_event *event;
640 struct radeon_bo *old_rbo;
641 u64 new_crtc_base;
642};
643
644struct r500_irq_stat_regs {
645 u32 disp_int;
f122c610 646 u32 hdmi0_status;
6f34be50
AD		 647};
648
649struct r600_irq_stat_regs {
650 u32 disp_int;
651 u32 disp_int_cont;
652 u32 disp_int_cont2;
653 u32 d1grph_int;
654 u32 d2grph_int;
f122c610
AD		 655 u32 hdmi0_status;
656 u32 hdmi1_status;
6f34be50
AD		 657};
658
659struct evergreen_irq_stat_regs {
660 u32 disp_int;
661 u32 disp_int_cont;
662 u32 disp_int_cont2;
663 u32 disp_int_cont3;
664 u32 disp_int_cont4;
665 u32 disp_int_cont5;
666 u32 d1grph_int;
667 u32 d2grph_int;
668 u32 d3grph_int;
669 u32 d4grph_int;
670 u32 d5grph_int;
671 u32 d6grph_int;
f122c610
AD		 672 u32 afmt_status1;
673 u32 afmt_status2;
674 u32 afmt_status3;
675 u32 afmt_status4;
676 u32 afmt_status5;
677 u32 afmt_status6;
6f34be50
AD		 678};
679
a59781bb
AD		 680struct cik_irq_stat_regs {
681 u32 disp_int;
682 u32 disp_int_cont;
683 u32 disp_int_cont2;
684 u32 disp_int_cont3;
685 u32 disp_int_cont4;
686 u32 disp_int_cont5;
687 u32 disp_int_cont6;
688};
689
6f34be50
AD		 690union radeon_irq_stat_regs {
691 struct r500_irq_stat_regs r500;
692 struct r600_irq_stat_regs r600;
693 struct evergreen_irq_stat_regs evergreen;
a59781bb 694 struct cik_irq_stat_regs cik;
6f34be50
AD		 695};
696
54bd5206
IH		 697#define RADEON_MAX_HPD_PINS 6
698#define RADEON_MAX_CRTCS 6
f122c610 699#define RADEON_MAX_AFMT_BLOCKS 6
54bd5206 700
771fe6b9 701struct radeon_irq {
fb98257a
CK		 702 bool installed;
703 spinlock_t lock;
736fc37f 704 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 705 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 706 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 707 wait_queue_head_t vblank_queue;
708 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 709 bool afmt[RADEON_MAX_AFMT_BLOCKS];
710 union radeon_irq_stat_regs stat_regs;
4a6369e9 711 bool dpm_thermal;
771fe6b9
JG		 712};
713
714int radeon_irq_kms_init(struct radeon_device *rdev);
715void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b
AD		 716void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
717void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 718void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
719void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 720void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
721void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
722void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
723void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 724
725/*
e32eb50d 726 * CP & rings.
771fe6b9 727 */
7465280c 728
771fe6b9 729struct radeon_ib {
68470ae7
JG		 730 struct radeon_sa_bo *sa_bo;
731 uint32_t length_dw;
732 uint64_t gpu_addr;
733 uint32_t *ptr;
876dc9f3 734 int ring;
68470ae7 735 struct radeon_fence *fence;
4bf3dd92 736 struct radeon_vm *vm;
68470ae7 737 bool is_const_ib;
220907d9 738 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
68470ae7 739 struct radeon_semaphore *semaphore;
771fe6b9
JG		 740};
741
e32eb50d 742struct radeon_ring {
4c788679 743 struct radeon_bo *ring_obj;
771fe6b9
JG		 744 volatile uint32_t *ring;
745 unsigned rptr;
5596a9db
CK		 746 unsigned rptr_offs;
747 unsigned rptr_reg;
45df6803 748 unsigned rptr_save_reg;
89d35807
AD		 749 u64 next_rptr_gpu_addr;
750 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 751 unsigned wptr;
752 unsigned wptr_old;
5596a9db 753 unsigned wptr_reg;
771fe6b9
JG		 754 unsigned ring_size;
755 unsigned ring_free_dw;
756 int count_dw;
069211e5
CK		 757 unsigned long last_activity;
758 unsigned last_rptr;
771fe6b9
JG		 759 uint64_t gpu_addr;
760 uint32_t align_mask;
761 uint32_t ptr_mask;
771fe6b9 762 bool ready;
78c5560a
AD		 763 u32 ptr_reg_shift;
764 u32 ptr_reg_mask;
765 u32 nop;
8b25ed34 766 u32 idx;
5f0839c1
JG		 767 u64 last_semaphore_signal_addr;
768 u64 last_semaphore_wait_addr;
963e81f9
AD		 769 /* for CIK queues */
770 u32 me;
771 u32 pipe;
772 u32 queue;
773 struct radeon_bo *mqd_obj;
774 u32 doorbell_page_num;
775 u32 doorbell_offset;
776 unsigned wptr_offs;
777};
778
779struct radeon_mec {
780 struct radeon_bo *hpd_eop_obj;
781 u64 hpd_eop_gpu_addr;
782 u32 num_pipe;
783 u32 num_mec;
784 u32 num_queue;
771fe6b9
JG		 785};
786
721604a1
JG		 787/*
788 * VM
789 */
ee60e29f 790
fa87e62d 791/* maximum number of VMIDs */
ee60e29f
CK		 792#define RADEON_NUM_VM 16
793
fa87e62d
DC		 794/* defines number of bits in page table versus page directory,
795 * a page is 4KB so we have 12 bits offset, 9 bits in the page
796 * table and the remaining 19 bits are in the page directory */
797#define RADEON_VM_BLOCK_SIZE 9
798
799/* number of entries in page table */
800#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
801
1c01103c
AD		 802/* PTBs (Page Table Blocks) need to be aligned to 32K */
803#define RADEON_VM_PTB_ALIGN_SIZE 32768
804#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
805#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
806
721604a1
JG		 807struct radeon_vm {
808 struct list_head list;
809 struct list_head va;
ee60e29f 810 unsigned id;
90a51a32
CK		 811
812 /* contains the page directory */
813 struct radeon_sa_bo *page_directory;
814 uint64_t pd_gpu_addr;
815
816 /* array of page tables, one for each page directory entry */
817 struct radeon_sa_bo **page_tables;
818
721604a1
JG		 819 struct mutex mutex;
820 /* last fence for cs using this vm */
821 struct radeon_fence *fence;
9b40e5d8
CK		 822 /* last flush or NULL if we still need to flush */
823 struct radeon_fence *last_flush;
721604a1
JG		 824};
825
721604a1 826struct radeon_vm_manager {
36ff39c4 827 struct mutex lock;
721604a1 828 struct list_head lru_vm;
ee60e29f 829 struct radeon_fence *active[RADEON_NUM_VM];
721604a1
JG		 830 struct radeon_sa_manager sa_manager;
831 uint32_t max_pfn;
721604a1
JG		 832 /* number of VMIDs */
833 unsigned nvm;
834 /* vram base address for page table entry */
835 u64 vram_base_offset;
67e915e4
AD		 836 /* is vm enabled? */
837 bool enabled;
721604a1
JG		 838};
839
840/*
841 * file private structure
842 */
843struct radeon_fpriv {
844 struct radeon_vm vm;
845};
846
d8f60cfc
AD		 847/*
848 * R6xx+ IH ring
849 */
850struct r600_ih {
4c788679 851 struct radeon_bo *ring_obj;
d8f60cfc
AD		 852 volatile uint32_t *ring;
853 unsigned rptr;
d8f60cfc
AD		 854 unsigned ring_size;
855 uint64_t gpu_addr;
d8f60cfc 856 uint32_t ptr_mask;
c20dc369 857 atomic_t lock;
d8f60cfc
AD		 858 bool enabled;
859};
860
347e7592 861/*
2948f5e6 862 * RLC stuff
347e7592 863 */
2948f5e6
AD		 864#include "clearstate_defs.h"
865
866struct radeon_rlc {
347e7592
AD		 867 /* for power gating */
868 struct radeon_bo *save_restore_obj;
869 uint64_t save_restore_gpu_addr;
2948f5e6 870 volatile uint32_t *sr_ptr;
1fd11777 871 const u32 *reg_list;
2948f5e6 872 u32 reg_list_size;
347e7592
AD		 873 /* for clear state */
874 struct radeon_bo *clear_state_obj;
875 uint64_t clear_state_gpu_addr;
2948f5e6 876 volatile uint32_t *cs_ptr;
1fd11777 877 const struct cs_section_def *cs_data;
22c775ce
AD		 878 u32 clear_state_size;
879 /* for cp tables */
880 struct radeon_bo *cp_table_obj;
881 uint64_t cp_table_gpu_addr;
882 volatile uint32_t *cp_table_ptr;
883 u32 cp_table_size;
347e7592
AD		 884};
885
69e130a6 886int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 887 struct radeon_ib *ib, struct radeon_vm *vm,
888 unsigned size);
f2e39221 889void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
43f1214a 890void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
4ef72566
CK		 891int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
892 struct radeon_ib *const_ib);
771fe6b9
JG		 893int radeon_ib_pool_init(struct radeon_device *rdev);
894void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 895int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 896/* Ring access between begin & end cannot sleep */
89d35807
AD		 897bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
898 struct radeon_ring *ring);
e32eb50d
CK		 899void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
900int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
901int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
902void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
903void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
d6999bc7 904void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 905void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
906int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
7b9ef16b 907void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
069211e5
CK		 908void radeon_ring_lockup_update(struct radeon_ring *ring);
909bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 910unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
911 uint32_t **data);
912int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
913 unsigned size, uint32_t *data);
e32eb50d 914int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
78c5560a
AD		 915 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
916 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
e32eb50d 917void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 918
919
4d75658b
AD		 920/* r600 async dma */
921void r600_dma_stop(struct radeon_device *rdev);
922int r600_dma_resume(struct radeon_device *rdev);
923void r600_dma_fini(struct radeon_device *rdev);
924
8c5fd7ef
AD		 925void cayman_dma_stop(struct radeon_device *rdev);
926int cayman_dma_resume(struct radeon_device *rdev);
927void cayman_dma_fini(struct radeon_device *rdev);
928
771fe6b9
JG		 929/*
930 * CS.
931 */
932struct radeon_cs_reloc {
933 struct drm_gem_object *gobj;
4c788679
JG		 934 struct radeon_bo *robj;
935 struct radeon_bo_list lobj;
771fe6b9
JG		 936 uint32_t handle;
937 uint32_t flags;
938};
939
940struct radeon_cs_chunk {
941 uint32_t chunk_id;
942 uint32_t length_dw;
721604a1
JG		 943 int kpage_idx[2];
944 uint32_t *kpage[2];
771fe6b9 945 uint32_t *kdata;
721604a1
JG		 946 void __user *user_ptr;
947 int last_copied_page;
948 int last_page_index;
771fe6b9
JG		 949};
950
951struct radeon_cs_parser {
c8c15ff1 952 struct device *dev;
771fe6b9
JG		 953 struct radeon_device *rdev;
954 struct drm_file *filp;
955 /* chunks */
956 unsigned nchunks;
957 struct radeon_cs_chunk *chunks;
958 uint64_t *chunks_array;
959 /* IB */
960 unsigned idx;
961 /* relocations */
962 unsigned nrelocs;
963 struct radeon_cs_reloc *relocs;
964 struct radeon_cs_reloc **relocs_ptr;
965 struct list_head validated;
cf4ccd01 966 unsigned dma_reloc_idx;
771fe6b9
JG		 967 /* indices of various chunks */
968 int chunk_ib_idx;
969 int chunk_relocs_idx;
721604a1 970 int chunk_flags_idx;
dfcf5f36 971 int chunk_const_ib_idx;
f2e39221
JG		 972 struct radeon_ib ib;
973 struct radeon_ib const_ib;
771fe6b9 974 void *track;
3ce0a23d 975 unsigned family;
e70f224c 976 int parser_error;
721604a1
JG		 977 u32 cs_flags;
978 u32 ring;
979 s32 priority;
ecff665f 980 struct ww_acquire_ctx ticket;
771fe6b9
JG		 981};
982
513bcb46 983extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
ce580fab 984extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
513bcb46 985
771fe6b9
JG		 986struct radeon_cs_packet {
987 unsigned idx;
988 unsigned type;
989 unsigned reg;
990 unsigned opcode;
991 int count;
992 unsigned one_reg_wr;
993};
994
995typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
996 struct radeon_cs_packet *pkt,
997 unsigned idx, unsigned reg);
998typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
999 struct radeon_cs_packet *pkt);
1000
1001
1002/*
1003 * AGP
1004 */
1005int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1006void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1007void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1008void radeon_agp_fini(struct radeon_device *rdev);
1009
1010
1011/*
1012 * Writeback
1013 */
1014struct radeon_wb {
4c788679 1015 struct radeon_bo *wb_obj;
771fe6b9
JG		 1016 volatile uint32_t *wb;
1017 uint64_t gpu_addr;
724c80e1 1018 bool enabled;
d0f8a854 1019 bool use_event;
771fe6b9
JG		 1020};
1021
724c80e1 1022#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1023#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1024#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1025#define RADEON_WB_CP1_RPTR_OFFSET 1280
1026#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1027#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1028#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1029#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1030#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1031#define CIK_WB_CP1_WPTR_OFFSET 3328
1032#define CIK_WB_CP2_WPTR_OFFSET 3584
724c80e1 1033
c93bb85b
JG		 1034/**
1035 * struct radeon_pm - power management datas
1036 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1037 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1038 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1039 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1040 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1041 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1042 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1043 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1044 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1045 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1046 * @needed_bandwidth: current bandwidth needs
1047 *
1048 * It keeps track of various data needed to take powermanagement decision.
25985edc 1049 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1050 * Equation between gpu/memory clock and available bandwidth is hw dependent
1051 * (type of memory, bus size, efficiency, ...)
1052 */
ce8f5370
AD		 1053
1054enum radeon_pm_method {
1055 PM_METHOD_PROFILE,
1056 PM_METHOD_DYNPM,
da321c8a 1057 PM_METHOD_DPM,
ce8f5370
AD		 1058};
1059
1060enum radeon_dynpm_state {
1061 DYNPM_STATE_DISABLED,
1062 DYNPM_STATE_MINIMUM,
1063 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1064 DYNPM_STATE_ACTIVE,
1065 DYNPM_STATE_SUSPENDED,
c913e23a 1066};
ce8f5370
AD		 1067enum radeon_dynpm_action {
1068 DYNPM_ACTION_NONE,
1069 DYNPM_ACTION_MINIMUM,
1070 DYNPM_ACTION_DOWNCLOCK,
1071 DYNPM_ACTION_UPCLOCK,
1072 DYNPM_ACTION_DEFAULT
c913e23a 1073};
56278a8e
AD		 1074
1075enum radeon_voltage_type {
1076 VOLTAGE_NONE = 0,
1077 VOLTAGE_GPIO,
1078 VOLTAGE_VDDC,
1079 VOLTAGE_SW
1080};
1081
0ec0e74f 1082enum radeon_pm_state_type {
da321c8a 1083 /* not used for dpm */
0ec0e74f
AD		 1084 POWER_STATE_TYPE_DEFAULT,
1085 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1086 /* user selectable states */
0ec0e74f
AD		 1087 POWER_STATE_TYPE_BATTERY,
1088 POWER_STATE_TYPE_BALANCED,
1089 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1090 /* internal states */
1091 POWER_STATE_TYPE_INTERNAL_UVD,
1092 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1093 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1094 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1095 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1096 POWER_STATE_TYPE_INTERNAL_BOOT,
1097 POWER_STATE_TYPE_INTERNAL_THERMAL,
1098 POWER_STATE_TYPE_INTERNAL_ACPI,
1099 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1100 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1101};
1102
ce8f5370
AD		 1103enum radeon_pm_profile_type {
1104 PM_PROFILE_DEFAULT,
1105 PM_PROFILE_AUTO,
1106 PM_PROFILE_LOW,
c9e75b21 1107 PM_PROFILE_MID,
ce8f5370
AD		 1108 PM_PROFILE_HIGH,
1109};
1110
1111#define PM_PROFILE_DEFAULT_IDX 0
1112#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1113#define PM_PROFILE_MID_SH_IDX 2
1114#define PM_PROFILE_HIGH_SH_IDX 3
1115#define PM_PROFILE_LOW_MH_IDX 4
1116#define PM_PROFILE_MID_MH_IDX 5
1117#define PM_PROFILE_HIGH_MH_IDX 6
1118#define PM_PROFILE_MAX 7
ce8f5370
AD		 1119
1120struct radeon_pm_profile {
1121 int dpms_off_ps_idx;
1122 int dpms_on_ps_idx;
1123 int dpms_off_cm_idx;
1124 int dpms_on_cm_idx;
516d0e46
AD		 1125};
1126
21a8122a
AD		 1127enum radeon_int_thermal_type {
1128 THERMAL_TYPE_NONE,
da321c8a
AD		 1129 THERMAL_TYPE_EXTERNAL,
1130 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1131 THERMAL_TYPE_RV6XX,
1132 THERMAL_TYPE_RV770,
da321c8a 1133 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1134 THERMAL_TYPE_EVERGREEN,
e33df25f 1135 THERMAL_TYPE_SUMO,
4fddba1f 1136 THERMAL_TYPE_NI,
14607d08 1137 THERMAL_TYPE_SI,
da321c8a 1138 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1139 THERMAL_TYPE_CI,
16fbe00d 1140 THERMAL_TYPE_KV,
21a8122a
AD		 1141};
1142
56278a8e
AD		 1143struct radeon_voltage {
1144 enum radeon_voltage_type type;
1145 /* gpio voltage */
1146 struct radeon_gpio_rec gpio;
1147 u32 delay; /* delay in usec from voltage drop to sclk change */
1148 bool active_high; /* voltage drop is active when bit is high */
1149 /* VDDC voltage */
1150 u8 vddc_id; /* index into vddc voltage table */
1151 u8 vddci_id; /* index into vddci voltage table */
1152 bool vddci_enabled;
1153 /* r6xx+ sw */
2feea49a
AD		 1154 u16 voltage;
1155 /* evergreen+ vddci */
1156 u16 vddci;
56278a8e
AD		 1157};
1158
d7311171
AD		 1159/* clock mode flags */
1160#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1161
56278a8e
AD		 1162struct radeon_pm_clock_info {
1163 /* memory clock */
1164 u32 mclk;
1165 /* engine clock */
1166 u32 sclk;
1167 /* voltage info */
1168 struct radeon_voltage voltage;
d7311171 1169 /* standardized clock flags */
56278a8e
AD		 1170 u32 flags;
1171};
1172
a48b9b4e 1173/* state flags */
d7311171 1174#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1175
56278a8e 1176struct radeon_power_state {
0ec0e74f 1177 enum radeon_pm_state_type type;
8f3f1c9a 1178 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1179 /* number of valid clock modes in this power state */
1180 int num_clock_modes;
56278a8e 1181 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1182 /* standardized state flags */
1183 u32 flags;
79daedc9
AD		 1184 u32 misc; /* vbios specific flags */
1185 u32 misc2; /* vbios specific flags */
1186 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1187};
1188
27459324
RM		 1189/*
1190 * Some modes are overclocked by very low value, accept them
1191 */
1192#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1193
2e9d4c05
AD		 1194enum radeon_dpm_auto_throttle_src {
1195 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1196 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1197};
1198
1199enum radeon_dpm_event_src {
1200 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1201 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1202 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1203 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1204 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1205};
1206
da321c8a
AD		 1207struct radeon_ps {
1208 u32 caps; /* vbios flags */
1209 u32 class; /* vbios flags */
1210 u32 class2; /* vbios flags */
1211 /* UVD clocks */
1212 u32 vclk;
1213 u32 dclk;
c4453e66
AD		 1214 /* VCE clocks */
1215 u32 evclk;
1216 u32 ecclk;
da321c8a
AD		 1217 /* asic priv */
1218 void *ps_priv;
1219};
1220
1221struct radeon_dpm_thermal {
1222 /* thermal interrupt work */
1223 struct work_struct work;
1224 /* low temperature threshold */
1225 int min_temp;
1226 /* high temperature threshold */
1227 int max_temp;
1228 /* was interrupt low to high or high to low */
1229 bool high_to_low;
1230};
1231
d22b7e40
AD		 1232enum radeon_clk_action
1233{
1234 RADEON_SCLK_UP = 1,
1235 RADEON_SCLK_DOWN
1236};
1237
1238struct radeon_blacklist_clocks
1239{
1240 u32 sclk;
1241 u32 mclk;
1242 enum radeon_clk_action action;
1243};
1244
61b7d601
AD		 1245struct radeon_clock_and_voltage_limits {
1246 u32 sclk;
1247 u32 mclk;
1248 u32 vddc;
1249 u32 vddci;
1250};
1251
1252struct radeon_clock_array {
1253 u32 count;
1254 u32 *values;
1255};
1256
1257struct radeon_clock_voltage_dependency_entry {
1258 u32 clk;
1259 u16 v;
1260};
1261
1262struct radeon_clock_voltage_dependency_table {
1263 u32 count;
1264 struct radeon_clock_voltage_dependency_entry *entries;
1265};
1266
ef976ec4
AD		 1267union radeon_cac_leakage_entry {
1268 struct {
1269 u16 vddc;
1270 u32 leakage;
1271 };
1272 struct {
1273 u16 vddc1;
1274 u16 vddc2;
1275 u16 vddc3;
1276 };
61b7d601
AD		 1277};
1278
1279struct radeon_cac_leakage_table {
1280 u32 count;
ef976ec4 1281 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1282};
1283
929ee7a8
AD		 1284struct radeon_phase_shedding_limits_entry {
1285 u16 voltage;
1286 u32 sclk;
1287 u32 mclk;
1288};
1289
1290struct radeon_phase_shedding_limits_table {
1291 u32 count;
1292 struct radeon_phase_shedding_limits_entry *entries;
1293};
1294
84a9d9ee
AD		 1295struct radeon_uvd_clock_voltage_dependency_entry {
1296 u32 vclk;
1297 u32 dclk;
1298 u16 v;
1299};
1300
1301struct radeon_uvd_clock_voltage_dependency_table {
1302 u8 count;
1303 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1304};
1305
d29f013b
AD		 1306struct radeon_vce_clock_voltage_dependency_entry {
1307 u32 ecclk;
1308 u32 evclk;
1309 u16 v;
1310};
1311
1312struct radeon_vce_clock_voltage_dependency_table {
1313 u8 count;
1314 struct radeon_vce_clock_voltage_dependency_entry *entries;
1315};
1316
a5cb318e
AD		 1317struct radeon_ppm_table {
1318 u8 ppm_design;
1319 u16 cpu_core_number;
1320 u32 platform_tdp;
1321 u32 small_ac_platform_tdp;
1322 u32 platform_tdc;
1323 u32 small_ac_platform_tdc;
1324 u32 apu_tdp;
1325 u32 dgpu_tdp;
1326 u32 dgpu_ulv_power;
1327 u32 tj_max;
1328};
1329
58cb7632
AD		 1330struct radeon_cac_tdp_table {
1331 u16 tdp;
1332 u16 configurable_tdp;
1333 u16 tdc;
1334 u16 battery_power_limit;
1335 u16 small_power_limit;
1336 u16 low_cac_leakage;
1337 u16 high_cac_leakage;
1338 u16 maximum_power_delivery_limit;
1339};
1340
61b7d601
AD		 1341struct radeon_dpm_dynamic_state {
1342 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1343 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1344 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1345 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1346 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1347 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1348 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1349 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1350 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1351 struct radeon_clock_array valid_sclk_values;
1352 struct radeon_clock_array valid_mclk_values;
1353 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1354 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1355 u32 mclk_sclk_ratio;
1356 u32 sclk_mclk_delta;
1357 u16 vddc_vddci_delta;
1358 u16 min_vddc_for_pcie_gen2;
1359 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1360 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1361 struct radeon_ppm_table *ppm_table;
58cb7632 1362 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1363};
1364
1365struct radeon_dpm_fan {
1366 u16 t_min;
1367 u16 t_med;
1368 u16 t_high;
1369 u16 pwm_min;
1370 u16 pwm_med;
1371 u16 pwm_high;
1372 u8 t_hyst;
1373 u32 cycle_delay;
1374 u16 t_max;
1375 bool ucode_fan_control;
1376};
1377
32ce4652
AD		 1378enum radeon_pcie_gen {
1379 RADEON_PCIE_GEN1 = 0,
1380 RADEON_PCIE_GEN2 = 1,
1381 RADEON_PCIE_GEN3 = 2,
1382 RADEON_PCIE_GEN_INVALID = 0xffff
1383};
1384
70d01a5e
AD		 1385enum radeon_dpm_forced_level {
1386 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1387 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1388 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1389};
1390
da321c8a
AD		 1391struct radeon_dpm {
1392 struct radeon_ps *ps;
1393 /* number of valid power states */
1394 int num_ps;
1395 /* current power state that is active */
1396 struct radeon_ps *current_ps;
1397 /* requested power state */
1398 struct radeon_ps *requested_ps;
1399 /* boot up power state */
1400 struct radeon_ps *boot_ps;
1401 /* default uvd power state */
1402 struct radeon_ps *uvd_ps;
1403 enum radeon_pm_state_type state;
1404 enum radeon_pm_state_type user_state;
1405 u32 platform_caps;
1406 u32 voltage_response_time;
1407 u32 backbias_response_time;
1408 void *priv;
1409 u32 new_active_crtcs;
1410 int new_active_crtc_count;
1411 u32 current_active_crtcs;
1412 int current_active_crtc_count;
61b7d601
AD		 1413 struct radeon_dpm_dynamic_state dyn_state;
1414 struct radeon_dpm_fan fan;
1415 u32 tdp_limit;
1416 u32 near_tdp_limit;
a9e61410 1417 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1418 u32 sq_ramping_threshold;
1419 u32 cac_leakage;
1420 u16 tdp_od_limit;
1421 u32 tdp_adjustment;
1422 u16 load_line_slope;
1423 bool power_control;
5ca302f7 1424 bool ac_power;
da321c8a
AD		 1425 /* special states active */
1426 bool thermal_active;
8a227555 1427 bool uvd_active;
da321c8a
AD		 1428 /* thermal handling */
1429 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1430 /* forced levels */
1431 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1432 /* track UVD streams */
1433 unsigned sd;
1434 unsigned hd;
da321c8a
AD		 1435};
1436
ce3537d5 1437void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
da321c8a 1438
c93bb85b 1439struct radeon_pm {
c913e23a 1440 struct mutex mutex;
db7fce39
CK		 1441 /* write locked while reprogramming mclk */
1442 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1443 u32 active_crtcs;
1444 int active_crtc_count;
c913e23a 1445 int req_vblank;
839461d3 1446 bool vblank_sync;
c93bb85b
JG		 1447 fixed20_12 max_bandwidth;
1448 fixed20_12 igp_sideport_mclk;
1449 fixed20_12 igp_system_mclk;
1450 fixed20_12 igp_ht_link_clk;
1451 fixed20_12 igp_ht_link_width;
1452 fixed20_12 k8_bandwidth;
1453 fixed20_12 sideport_bandwidth;
1454 fixed20_12 ht_bandwidth;
1455 fixed20_12 core_bandwidth;
1456 fixed20_12 sclk;
f47299c5 1457 fixed20_12 mclk;
c93bb85b 1458 fixed20_12 needed_bandwidth;
0975b162 1459 struct radeon_power_state *power_state;
56278a8e
AD		 1460 /* number of valid power states */
1461 int num_power_states;
a48b9b4e
AD		 1462 int current_power_state_index;
1463 int current_clock_mode_index;
1464 int requested_power_state_index;
1465 int requested_clock_mode_index;
1466 int default_power_state_index;
1467 u32 current_sclk;
1468 u32 current_mclk;
2feea49a
AD		 1469 u16 current_vddc;
1470 u16 current_vddci;
9ace9f7b
AD		 1471 u32 default_sclk;
1472 u32 default_mclk;
2feea49a
AD		 1473 u16 default_vddc;
1474 u16 default_vddci;
29fb52ca 1475 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1476 /* selected pm method */
1477 enum radeon_pm_method pm_method;
1478 /* dynpm power management */
1479 struct delayed_work dynpm_idle_work;
1480 enum radeon_dynpm_state dynpm_state;
1481 enum radeon_dynpm_action dynpm_planned_action;
1482 unsigned long dynpm_action_timeout;
1483 bool dynpm_can_upclock;
1484 bool dynpm_can_downclock;
1485 /* profile-based power management */
1486 enum radeon_pm_profile_type profile;
1487 int profile_index;
1488 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1489 /* internal thermal controller on rv6xx+ */
1490 enum radeon_int_thermal_type int_thermal_type;
1491 struct device *int_hwmon_dev;
da321c8a
AD		 1492 /* dpm */
1493 bool dpm_enabled;
1494 struct radeon_dpm dpm;
c93bb85b
JG		 1495};
1496
a4c9e2ee
AD		 1497int radeon_pm_get_type_index(struct radeon_device *rdev,
1498 enum radeon_pm_state_type ps_type,
1499 int instance);
f2ba57b5
CK		 1500/*
1501 * UVD
1502 */
1503#define RADEON_MAX_UVD_HANDLES 10
1504#define RADEON_UVD_STACK_SIZE (1024*1024)
1505#define RADEON_UVD_HEAP_SIZE (1024*1024)
1506
1507struct radeon_uvd {
1508 struct radeon_bo *vcpu_bo;
1509 void *cpu_addr;
1510 uint64_t gpu_addr;
9cc2e0e9 1511 void *saved_bo;
f2ba57b5
CK		 1512 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1513 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1514 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1515 struct delayed_work idle_work;
f2ba57b5
CK		 1516};
1517
1518int radeon_uvd_init(struct radeon_device *rdev);
1519void radeon_uvd_fini(struct radeon_device *rdev);
1520int radeon_uvd_suspend(struct radeon_device *rdev);
1521int radeon_uvd_resume(struct radeon_device *rdev);
1522int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1523 uint32_t handle, struct radeon_fence **fence);
1524int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1525 uint32_t handle, struct radeon_fence **fence);
1526void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1527void radeon_uvd_free_handles(struct radeon_device *rdev,
1528 struct drm_file *filp);
1529int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1530void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1531int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1532 unsigned vclk, unsigned dclk,
1533 unsigned vco_min, unsigned vco_max,
1534 unsigned fb_factor, unsigned fb_mask,
1535 unsigned pd_min, unsigned pd_max,
1536 unsigned pd_even,
1537 unsigned *optimal_fb_div,
1538 unsigned *optimal_vclk_div,
1539 unsigned *optimal_dclk_div);
1540int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1541 unsigned cg_upll_func_cntl);
771fe6b9 1542
a92553ab 1543struct r600_audio {
a92553ab
RM		 1544 int channels;
1545 int rate;
1546 int bits_per_sample;
1547 u8 status_bits;
1548 u8 category_code;
1549};
1550
771fe6b9
JG		 1551/*
1552 * Benchmarking
1553 */
638dd7db 1554void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1555
1556
ecc0b326
MD		 1557/*
1558 * Testing
1559 */
1560void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1561void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1562 struct radeon_ring *cpA,
1563 struct radeon_ring *cpB);
60a7e396 1564void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326
MD		 1565
1566
771fe6b9
JG		 1567/*
1568 * Debugfs
1569 */
4d8bf9ae
CK		 1570struct radeon_debugfs {
1571 struct drm_info_list *files;
1572 unsigned num_files;
1573};
1574
771fe6b9
JG		 1575int radeon_debugfs_add_files(struct radeon_device *rdev,
1576 struct drm_info_list *files,
1577 unsigned nfiles);
1578int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1579
76a0df85
CK		 1580/*
1581 * ASIC ring specific functions.
1582 */
1583struct radeon_asic_ring {
1584 /* ring read/write ptr handling */
1585 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1586 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1587 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1588
1589 /* validating and patching of IBs */
1590 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1591 int (*cs_parse)(struct radeon_cs_parser *p);
1592
1593 /* command emmit functions */
1594 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1595 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1596 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1597 struct radeon_semaphore *semaphore, bool emit_wait);
1598 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1599
1600 /* testing functions */
1601 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1602 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1603 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1604
1605 /* deprecated */
1606 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1607};
771fe6b9
JG		 1608
1609/*
1610 * ASIC specific functions.
1611 */
1612struct radeon_asic {
068a117c 1613 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1614 void (*fini)(struct radeon_device *rdev);
1615 int (*resume)(struct radeon_device *rdev);
1616 int (*suspend)(struct radeon_device *rdev);
28d52043 1617 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1618 int (*asic_reset)(struct radeon_device *rdev);
54e88e06
AD		 1619 /* ioctl hw specific callback. Some hw might want to perform special
1620 * operation on specific ioctl. For instance on wait idle some hw
1621 * might want to perform and HDP flush through MMIO as it seems that
1622 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1623 * through ring.
1624 */
1625 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1626 /* check if 3D engine is idle */
1627 bool (*gui_idle)(struct radeon_device *rdev);
1628 /* wait for mc_idle */
1629 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1630 /* get the reference clock */
1631 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1632 /* get the gpu clock counter */
1633 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1634 /* gart */
c5b3b850
AD		 1635 struct {
1636 void (*tlb_flush)(struct radeon_device *rdev);
1637 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1638 } gart;
05b07147
CK		 1639 struct {
1640 int (*init)(struct radeon_device *rdev);
1641 void (*fini)(struct radeon_device *rdev);
2a6f1abb
CK		 1642
1643 u32 pt_ring_index;
43f1214a
AD		 1644 void (*set_page)(struct radeon_device *rdev,
1645 struct radeon_ib *ib,
1646 uint64_t pe,
dce34bfd
CK		 1647 uint64_t addr, unsigned count,
1648 uint32_t incr, uint32_t flags);
05b07147 1649 } vm;
54e88e06 1650 /* ring specific callbacks */
76a0df85 1651 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1652 /* irqs */
b35ea4ab
AD		 1653 struct {
1654 int (*set)(struct radeon_device *rdev);
1655 int (*process)(struct radeon_device *rdev);
1656 } irq;
54e88e06 1657 /* displays */
c79a49ca
AD		 1658 struct {
1659 /* display watermarks */
1660 void (*bandwidth_update)(struct radeon_device *rdev);
1661 /* get frame count */
1662 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1663 /* wait for vblank */
1664 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1665 /* set backlight level */
1666 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1667 /* get backlight level */
1668 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1669 /* audio callbacks */
1670 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1671 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1672 } display;
54e88e06 1673 /* copy functions for bo handling */
27cd7769
AD		 1674 struct {
1675 int (*blit)(struct radeon_device *rdev,
1676 uint64_t src_offset,
1677 uint64_t dst_offset,
1678 unsigned num_gpu_pages,
876dc9f3 1679 struct radeon_fence **fence);
27cd7769
AD		 1680 u32 blit_ring_index;
1681 int (*dma)(struct radeon_device *rdev,
1682 uint64_t src_offset,
1683 uint64_t dst_offset,
1684 unsigned num_gpu_pages,
876dc9f3 1685 struct radeon_fence **fence);
27cd7769
AD		 1686 u32 dma_ring_index;
1687 /* method used for bo copy */
1688 int (*copy)(struct radeon_device *rdev,
1689 uint64_t src_offset,
1690 uint64_t dst_offset,
1691 unsigned num_gpu_pages,
876dc9f3 1692 struct radeon_fence **fence);
27cd7769
AD		 1693 /* ring used for bo copies */
1694 u32 copy_ring_index;
1695 } copy;
54e88e06 1696 /* surfaces */
9e6f3d02
AD		 1697 struct {
1698 int (*set_reg)(struct radeon_device *rdev, int reg,
1699 uint32_t tiling_flags, uint32_t pitch,
1700 uint32_t offset, uint32_t obj_size);
1701 void (*clear_reg)(struct radeon_device *rdev, int reg);
1702 } surface;
54e88e06 1703 /* hotplug detect */
901ea57d
AD		 1704 struct {
1705 void (*init)(struct radeon_device *rdev);
1706 void (*fini)(struct radeon_device *rdev);
1707 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1708 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1709 } hpd;
da321c8a 1710 /* static power management */
a02fa397
AD		 1711 struct {
1712 void (*misc)(struct radeon_device *rdev);
1713 void (*prepare)(struct radeon_device *rdev);
1714 void (*finish)(struct radeon_device *rdev);
1715 void (*init_profile)(struct radeon_device *rdev);
1716 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1717 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1718 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1719 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1720 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1721 int (*get_pcie_lanes)(struct radeon_device *rdev);
1722 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1723 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1724 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
6bd1c385 1725 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1726 } pm;
da321c8a
AD		 1727 /* dynamic power management */
1728 struct {
1729 int (*init)(struct radeon_device *rdev);
1730 void (*setup_asic)(struct radeon_device *rdev);
1731 int (*enable)(struct radeon_device *rdev);
1732 void (*disable)(struct radeon_device *rdev);
84dd1928 1733 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1734 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1735 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1736 void (*display_configuration_changed)(struct radeon_device *rdev);
1737 void (*fini)(struct radeon_device *rdev);
1738 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1739 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1740 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1741 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1742 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1743 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1744 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
da321c8a 1745 } dpm;
6f34be50 1746 /* pageflipping */
0f9e006c
AD		 1747 struct {
1748 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1749 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1750 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1751 } pflip;
771fe6b9
JG		 1752};
1753
21f9a437
JG		 1754/*
1755 * Asic structures
1756 */
551ebd83 1757struct r100_asic {
225758d8
JG		 1758 const unsigned *reg_safe_bm;
1759 unsigned reg_safe_bm_size;
1760 u32 hdp_cntl;
551ebd83
DA		 1761};
1762
21f9a437 1763struct r300_asic {
225758d8
JG		 1764 const unsigned *reg_safe_bm;
1765 unsigned reg_safe_bm_size;
1766 u32 resync_scratch;
1767 u32 hdp_cntl;
21f9a437
JG		 1768};
1769
1770struct r600_asic {
225758d8
JG		 1771 unsigned max_pipes;
1772 unsigned max_tile_pipes;
1773 unsigned max_simds;
1774 unsigned max_backends;
1775 unsigned max_gprs;
1776 unsigned max_threads;
1777 unsigned max_stack_entries;
1778 unsigned max_hw_contexts;
1779 unsigned max_gs_threads;
1780 unsigned sx_max_export_size;
1781 unsigned sx_max_export_pos_size;
1782 unsigned sx_max_export_smx_size;
1783 unsigned sq_num_cf_insts;
1784 unsigned tiling_nbanks;
1785 unsigned tiling_npipes;
1786 unsigned tiling_group_size;
e7aeeba6 1787 unsigned tile_config;
e55b9422 1788 unsigned backend_map;
21f9a437
JG		 1789};
1790
1791struct rv770_asic {
225758d8
JG		 1792 unsigned max_pipes;
1793 unsigned max_tile_pipes;
1794 unsigned max_simds;
1795 unsigned max_backends;
1796 unsigned max_gprs;
1797 unsigned max_threads;
1798 unsigned max_stack_entries;
1799 unsigned max_hw_contexts;
1800 unsigned max_gs_threads;
1801 unsigned sx_max_export_size;
1802 unsigned sx_max_export_pos_size;
1803 unsigned sx_max_export_smx_size;
1804 unsigned sq_num_cf_insts;
1805 unsigned sx_num_of_sets;
1806 unsigned sc_prim_fifo_size;
1807 unsigned sc_hiz_tile_fifo_size;
1808 unsigned sc_earlyz_tile_fifo_fize;
1809 unsigned tiling_nbanks;
1810 unsigned tiling_npipes;
1811 unsigned tiling_group_size;
e7aeeba6 1812 unsigned tile_config;
e55b9422 1813 unsigned backend_map;
21f9a437
JG		 1814};
1815
32fcdbf4
AD		 1816struct evergreen_asic {
1817 unsigned num_ses;
1818 unsigned max_pipes;
1819 unsigned max_tile_pipes;
1820 unsigned max_simds;
1821 unsigned max_backends;
1822 unsigned max_gprs;
1823 unsigned max_threads;
1824 unsigned max_stack_entries;
1825 unsigned max_hw_contexts;
1826 unsigned max_gs_threads;
1827 unsigned sx_max_export_size;
1828 unsigned sx_max_export_pos_size;
1829 unsigned sx_max_export_smx_size;
1830 unsigned sq_num_cf_insts;
1831 unsigned sx_num_of_sets;
1832 unsigned sc_prim_fifo_size;
1833 unsigned sc_hiz_tile_fifo_size;
1834 unsigned sc_earlyz_tile_fifo_size;
1835 unsigned tiling_nbanks;
1836 unsigned tiling_npipes;
1837 unsigned tiling_group_size;
e7aeeba6 1838 unsigned tile_config;
e55b9422 1839 unsigned backend_map;
32fcdbf4
AD		 1840};
1841
fecf1d07
AD		 1842struct cayman_asic {
1843 unsigned max_shader_engines;
1844 unsigned max_pipes_per_simd;
1845 unsigned max_tile_pipes;
1846 unsigned max_simds_per_se;
1847 unsigned max_backends_per_se;
1848 unsigned max_texture_channel_caches;
1849 unsigned max_gprs;
1850 unsigned max_threads;
1851 unsigned max_gs_threads;
1852 unsigned max_stack_entries;
1853 unsigned sx_num_of_sets;
1854 unsigned sx_max_export_size;
1855 unsigned sx_max_export_pos_size;
1856 unsigned sx_max_export_smx_size;
1857 unsigned max_hw_contexts;
1858 unsigned sq_num_cf_insts;
1859 unsigned sc_prim_fifo_size;
1860 unsigned sc_hiz_tile_fifo_size;
1861 unsigned sc_earlyz_tile_fifo_size;
1862
1863 unsigned num_shader_engines;
1864 unsigned num_shader_pipes_per_simd;
1865 unsigned num_tile_pipes;
1866 unsigned num_simds_per_se;
1867 unsigned num_backends_per_se;
1868 unsigned backend_disable_mask_per_asic;
1869 unsigned backend_map;
1870 unsigned num_texture_channel_caches;
1871 unsigned mem_max_burst_length_bytes;
1872 unsigned mem_row_size_in_kb;
1873 unsigned shader_engine_tile_size;
1874 unsigned num_gpus;
1875 unsigned multi_gpu_tile_size;
1876
1877 unsigned tile_config;
fecf1d07
AD		 1878};
1879
0a96d72b
AD		 1880struct si_asic {
1881 unsigned max_shader_engines;
0a96d72b 1882 unsigned max_tile_pipes;
1a8ca750
AD		 1883 unsigned max_cu_per_sh;
1884 unsigned max_sh_per_se;
0a96d72b
AD		 1885 unsigned max_backends_per_se;
1886 unsigned max_texture_channel_caches;
1887 unsigned max_gprs;
1888 unsigned max_gs_threads;
1889 unsigned max_hw_contexts;
1890 unsigned sc_prim_fifo_size_frontend;
1891 unsigned sc_prim_fifo_size_backend;
1892 unsigned sc_hiz_tile_fifo_size;
1893 unsigned sc_earlyz_tile_fifo_size;
1894
0a96d72b
AD		 1895 unsigned num_tile_pipes;
1896 unsigned num_backends_per_se;
1897 unsigned backend_disable_mask_per_asic;
1898 unsigned backend_map;
1899 unsigned num_texture_channel_caches;
1900 unsigned mem_max_burst_length_bytes;
1901 unsigned mem_row_size_in_kb;
1902 unsigned shader_engine_tile_size;
1903 unsigned num_gpus;
1904 unsigned multi_gpu_tile_size;
1905
1906 unsigned tile_config;
64d7b8be 1907 uint32_t tile_mode_array[32];
0a96d72b
AD		 1908};
1909
8cc1a532
AD		 1910struct cik_asic {
1911 unsigned max_shader_engines;
1912 unsigned max_tile_pipes;
1913 unsigned max_cu_per_sh;
1914 unsigned max_sh_per_se;
1915 unsigned max_backends_per_se;
1916 unsigned max_texture_channel_caches;
1917 unsigned max_gprs;
1918 unsigned max_gs_threads;
1919 unsigned max_hw_contexts;
1920 unsigned sc_prim_fifo_size_frontend;
1921 unsigned sc_prim_fifo_size_backend;
1922 unsigned sc_hiz_tile_fifo_size;
1923 unsigned sc_earlyz_tile_fifo_size;
1924
1925 unsigned num_tile_pipes;
1926 unsigned num_backends_per_se;
1927 unsigned backend_disable_mask_per_asic;
1928 unsigned backend_map;
1929 unsigned num_texture_channel_caches;
1930 unsigned mem_max_burst_length_bytes;
1931 unsigned mem_row_size_in_kb;
1932 unsigned shader_engine_tile_size;
1933 unsigned num_gpus;
1934 unsigned multi_gpu_tile_size;
1935
1936 unsigned tile_config;
39aee490 1937 uint32_t tile_mode_array[32];
8cc1a532
AD		 1938};
1939
068a117c
JG		 1940union radeon_asic_config {
1941 struct r300_asic r300;
551ebd83 1942 struct r100_asic r100;
3ce0a23d
JG		 1943 struct r600_asic r600;
1944 struct rv770_asic rv770;
32fcdbf4 1945 struct evergreen_asic evergreen;
fecf1d07 1946 struct cayman_asic cayman;
0a96d72b 1947 struct si_asic si;
8cc1a532 1948 struct cik_asic cik;
068a117c
JG		 1949};
1950
0a10c851
DV		 1951/*
1952 * asic initizalization from radeon_asic.c
1953 */
1954void radeon_agp_disable(struct radeon_device *rdev);
1955int radeon_asic_init(struct radeon_device *rdev);
1956
771fe6b9
JG		 1957
1958/*
1959 * IOCTL.
1960 */
1961int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1962 struct drm_file *filp);
1963int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1964 struct drm_file *filp);
1965int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1966 struct drm_file *file_priv);
1967int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1968 struct drm_file *file_priv);
1969int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1970 struct drm_file *file_priv);
1971int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1972 struct drm_file *file_priv);
1973int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1974 struct drm_file *filp);
1975int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1976 struct drm_file *filp);
1977int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1978 struct drm_file *filp);
1979int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1980 struct drm_file *filp);
721604a1
JG		 1981int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1982 struct drm_file *filp);
771fe6b9 1983int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 1984int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1985 struct drm_file *filp);
1986int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1987 struct drm_file *filp);
771fe6b9 1988
16cdf04d
AD		 1989/* VRAM scratch page for HDP bug, default vram page */
1990struct r600_vram_scratch {
87cbf8f2
AD		 1991 struct radeon_bo *robj;
1992 volatile uint32_t *ptr;
16cdf04d 1993 u64 gpu_addr;
87cbf8f2 1994};
771fe6b9 1995
fd64ca8a
LT		 1996/*
1997 * ACPI
1998 */
1999struct radeon_atif_notification_cfg {
2000 bool enabled;
2001 int command_code;
2002};
2003
2004struct radeon_atif_notifications {
2005 bool display_switch;
2006 bool expansion_mode_change;
2007 bool thermal_state;
2008 bool forced_power_state;
2009 bool system_power_state;
2010 bool display_conf_change;
2011 bool px_gfx_switch;
2012 bool brightness_change;
2013 bool dgpu_display_event;
2014};
2015
2016struct radeon_atif_functions {
2017 bool system_params;
2018 bool sbios_requests;
2019 bool select_active_disp;
2020 bool lid_state;
2021 bool get_tv_standard;
2022 bool set_tv_standard;
2023 bool get_panel_expansion_mode;
2024 bool set_panel_expansion_mode;
2025 bool temperature_change;
2026 bool graphics_device_types;
2027};
2028
2029struct radeon_atif {
2030 struct radeon_atif_notifications notifications;
2031 struct radeon_atif_functions functions;
2032 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2033 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2034};
7a1619b9 2035
e3a15920
AD		 2036struct radeon_atcs_functions {
2037 bool get_ext_state;
2038 bool pcie_perf_req;
2039 bool pcie_dev_rdy;
2040 bool pcie_bus_width;
2041};
2042
2043struct radeon_atcs {
2044 struct radeon_atcs_functions functions;
2045};
2046
771fe6b9
JG		 2047/*
2048 * Core structure, functions and helpers.
2049 */
2050typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2051typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2052
2053struct radeon_device {
9f022ddf 2054 struct device *dev;
771fe6b9
JG		 2055 struct drm_device *ddev;
2056 struct pci_dev *pdev;
dee53e7f 2057 struct rw_semaphore exclusive_lock;
771fe6b9 2058 /* ASIC */
068a117c 2059 union radeon_asic_config config;
771fe6b9
JG		 2060 enum radeon_family family;
2061 unsigned long flags;
2062 int usec_timeout;
2063 enum radeon_pll_errata pll_errata;
2064 int num_gb_pipes;
f779b3e5 2065 int num_z_pipes;
771fe6b9
JG		 2066 int disp_priority;
2067 /* BIOS */
2068 uint8_t *bios;
2069 bool is_atom_bios;
2070 uint16_t bios_header_start;
4c788679 2071 struct radeon_bo *stollen_vga_memory;
771fe6b9 2072 /* Register mmio */
4c9bc75c
DA		 2073 resource_size_t rmmio_base;
2074 resource_size_t rmmio_size;
2c385151
DV		 2075 /* protects concurrent MM_INDEX/DATA based register access */
2076 spinlock_t mmio_idx_lock;
a0533fbf 2077 void __iomem *rmmio;
771fe6b9
JG		 2078 radeon_rreg_t mc_rreg;
2079 radeon_wreg_t mc_wreg;
2080 radeon_rreg_t pll_rreg;
2081 radeon_wreg_t pll_wreg;
de1b2898 2082 uint32_t pcie_reg_mask;
771fe6b9
JG		 2083 radeon_rreg_t pciep_rreg;
2084 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2085 /* io port */
2086 void __iomem *rio_mem;
2087 resource_size_t rio_mem_size;
771fe6b9
JG		 2088 struct radeon_clock clock;
2089 struct radeon_mc mc;
2090 struct radeon_gart gart;
2091 struct radeon_mode_info mode_info;
2092 struct radeon_scratch scratch;
75efdee1 2093 struct radeon_doorbell doorbell;
771fe6b9 2094 struct radeon_mman mman;
7465280c 2095 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2096 wait_queue_head_t fence_queue;
d6999bc7 2097 struct mutex ring_lock;
e32eb50d 2098 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2099 bool ib_pool_ready;
2100 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2101 struct radeon_irq irq;
2102 struct radeon_asic *asic;
2103 struct radeon_gem gem;
c93bb85b 2104 struct radeon_pm pm;
f2ba57b5 2105 struct radeon_uvd uvd;
f657c2a7 2106 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2107 struct radeon_wb wb;
3ce0a23d 2108 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2109 bool shutdown;
2110 bool suspend;
ad49f501 2111 bool need_dma32;
733289c2 2112 bool accel_working;
a0a53aa8 2113 bool fastfb_working; /* IGP feature*/
e024e110 2114 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2115 const struct firmware *me_fw; /* all family ME firmware */
2116 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2117 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2118 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2119 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2120 const struct firmware *mec_fw; /* CIK MEC firmware */
21a93e13 2121 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2122 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2123 const struct firmware *uvd_fw; /* UVD firmware */
16cdf04d 2124 struct r600_vram_scratch vram_scratch;
3e5cb98d 2125 int msi_enabled; /* msi enabled */
d8f60cfc 2126 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2127 struct radeon_rlc rlc;
963e81f9 2128 struct radeon_mec mec;
d4877cf2 2129 struct work_struct hotplug_work;
f122c610 2130 struct work_struct audio_work;
8f61b34c 2131 struct work_struct reset_work;
18917b60 2132 int num_crtc; /* number of crtcs */
40bacf16 2133 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
3299de95 2134 bool audio_enabled;
948bee3f 2135 bool has_uvd;
3299de95 2136 struct r600_audio audio_status; /* audio stuff */
ce8f5370 2137 struct notifier_block acpi_nb;
9eba4a93 2138 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2139 struct drm_file *hyperz_filp;
9eba4a93 2140 struct drm_file *cmask_filp;
f376b94f
AD		 2141 /* i2c buses */
2142 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2143 /* debugfs */
2144 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2145 unsigned debugfs_count;
721604a1
JG		 2146 /* virtual memory */
2147 struct radeon_vm_manager vm_manager;
6759a0a7 2148 struct mutex gpu_clock_mutex;
fd64ca8a
LT		 2149 /* ACPI interface */
2150 struct radeon_atif atif;
e3a15920 2151 struct radeon_atcs atcs;
f61d5b46
AD		 2152 /* srbm instance registers */
2153 struct mutex srbm_mutex;
771fe6b9
JG		 2154};
2155
2156int radeon_device_init(struct radeon_device *rdev,
2157 struct drm_device *ddev,
2158 struct pci_dev *pdev,
2159 uint32_t flags);
2160void radeon_device_fini(struct radeon_device *rdev);
2161int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2162
2ef9bdfe
DV		 2163uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2164 bool always_indirect);
2165void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2166 bool always_indirect);
6fcbef7a
AK		 2167u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2168void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2169
75efdee1
AD		 2170u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset);
2171void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
2172
4c788679
JG		 2173/*
2174 * Cast helper
2175 */
2176#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 2177
2178/*
2179 * Registers read & write functions.
2180 */
a0533fbf
BH		 2181#define RREG8(reg) readb((rdev->rmmio) + (reg))
2182#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2183#define RREG16(reg) readw((rdev->rmmio) + (reg))
2184#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2185#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2186#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2187#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2188#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2189#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2190#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2191#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2192#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2193#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2194#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2195#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2196#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2197#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2198#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2199#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2200#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2201#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2202#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2203#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2204#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2205#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2206#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2207#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2208#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2209#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2210#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2211#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2212#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2213#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2214#define WREG32_P(reg, val, mask) \
2215 do { \
2216 uint32_t tmp_ = RREG32(reg); \
2217 tmp_ &= (mask); \
2218 tmp_ |= ((val) & ~(mask)); \
2219 WREG32(reg, tmp_); \
2220 } while (0)
d5169fc4 2221#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2222#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2223#define WREG32_PLL_P(reg, val, mask) \
2224 do { \
2225 uint32_t tmp_ = RREG32_PLL(reg); \
2226 tmp_ &= (mask); \
2227 tmp_ |= ((val) & ~(mask)); \
2228 WREG32_PLL(reg, tmp_); \
2229 } while (0)
2ef9bdfe 2230#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2231#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2232#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2233
75efdee1
AD		 2234#define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset))
2235#define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v))
2236
de1b2898
DA		 2237/*
2238 * Indirect registers accessor
2239 */
2240static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2241{
2242 uint32_t r;
2243
2244 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2245 r = RREG32(RADEON_PCIE_DATA);
2246 return r;
2247}
2248
2249static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2250{
2251 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2252 WREG32(RADEON_PCIE_DATA, (v));
2253}
2254
1d5d0c34
AD		 2255static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2256{
2257 u32 r;
2258
2259 WREG32(TN_SMC_IND_INDEX_0, (reg));
2260 r = RREG32(TN_SMC_IND_DATA_0);
2261 return r;
2262}
2263
2264static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2265{
2266 WREG32(TN_SMC_IND_INDEX_0, (reg));
2267 WREG32(TN_SMC_IND_DATA_0, (v));
2268}
2269
ff82bbc4
AD		 2270static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2271{
2272 u32 r;
2273
2274 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2275 r = RREG32(R600_RCU_DATA);
2276 return r;
2277}
2278
2279static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2280{
2281 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2282 WREG32(R600_RCU_DATA, (v));
2283}
2284
46f9564a
AD		 2285static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2286{
2287 u32 r;
2288
2289 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2290 r = RREG32(EVERGREEN_CG_IND_DATA);
2291 return r;
2292}
2293
2294static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2295{
2296 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2297 WREG32(EVERGREEN_CG_IND_DATA, (v));
2298}
2299
792edd69
AD		 2300static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2301{
2302 u32 r;
2303
2304 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2305 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2306 return r;
2307}
2308
2309static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2310{
2311 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2312 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2313}
2314
2315static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2316{
2317 u32 r;
2318
2319 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2320 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2321 return r;
2322}
2323
2324static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2325{
2326 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2327 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2328}
2329
93656cdd
AD		 2330static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2331{
2332 u32 r;
2333
2334 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2335 r = RREG32(R600_UVD_CTX_DATA);
2336 return r;
2337}
2338
2339static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2340{
2341 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2342 WREG32(R600_UVD_CTX_DATA, (v));
2343}
2344
1d58234d
AD		 2345
2346static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2347{
2348 u32 r;
2349
2350 WREG32(CIK_DIDT_IND_INDEX, (reg));
2351 r = RREG32(CIK_DIDT_IND_DATA);
2352 return r;
2353}
2354
2355static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2356{
2357 WREG32(CIK_DIDT_IND_INDEX, (reg));
2358 WREG32(CIK_DIDT_IND_DATA, (v));
2359}
2360
771fe6b9
JG		 2361void r100_pll_errata_after_index(struct radeon_device *rdev);
2362
2363
2364/*
2365 * ASICs helpers.
2366 */
b995e433
DA		 2367#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2368 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2369#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2370 (rdev->family == CHIP_RV200) || \
2371 (rdev->family == CHIP_RS100) || \
2372 (rdev->family == CHIP_RS200) || \
2373 (rdev->family == CHIP_RV250) || \
2374 (rdev->family == CHIP_RV280) || \
2375 (rdev->family == CHIP_RS300))
2376#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2377 (rdev->family == CHIP_RV350) || \
2378 (rdev->family == CHIP_R350) || \
2379 (rdev->family == CHIP_RV380) || \
2380 (rdev->family == CHIP_R420) || \
2381 (rdev->family == CHIP_R423) || \
2382 (rdev->family == CHIP_RV410) || \
2383 (rdev->family == CHIP_RS400) || \
2384 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2385#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2386 (rdev->ddev->pdev->device == 0x9443) || \
2387 (rdev->ddev->pdev->device == 0x944B) || \
2388 (rdev->ddev->pdev->device == 0x9506) || \
2389 (rdev->ddev->pdev->device == 0x9509) || \
2390 (rdev->ddev->pdev->device == 0x950F) || \
2391 (rdev->ddev->pdev->device == 0x689C) || \
2392 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2393#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2394#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2395 (rdev->family == CHIP_RS690) || \
2396 (rdev->family == CHIP_RS740) || \
2397 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2398#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2399#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2400#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2401#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2402 (rdev->flags & RADEON_IS_IGP))
1fe18305 2403#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2404#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2405#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2406 (rdev->flags & RADEON_IS_IGP))
624d3524 2407#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2408#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2409#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
771fe6b9 2410
dc50ba7f
AD		 2411#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2412 (rdev->ddev->pdev->device == 0x6850) || \
2413 (rdev->ddev->pdev->device == 0x6858) || \
2414 (rdev->ddev->pdev->device == 0x6859) || \
2415 (rdev->ddev->pdev->device == 0x6840) || \
2416 (rdev->ddev->pdev->device == 0x6841) || \
2417 (rdev->ddev->pdev->device == 0x6842) || \
2418 (rdev->ddev->pdev->device == 0x6843))
2419
771fe6b9
JG		 2420/*
2421 * BIOS helpers.
2422 */
2423#define RBIOS8(i) (rdev->bios[i])
2424#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2425#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2426
2427int radeon_combios_init(struct radeon_device *rdev);
2428void radeon_combios_fini(struct radeon_device *rdev);
2429int radeon_atombios_init(struct radeon_device *rdev);
2430void radeon_atombios_fini(struct radeon_device *rdev);
2431
2432
2433/*
2434 * RING helpers.
2435 */
ce580fab 2436#if DRM_DEBUG_CODE == 0
e32eb50d 2437static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2438{
e32eb50d
CK		 2439 ring->ring[ring->wptr++] = v;
2440 ring->wptr &= ring->ptr_mask;
2441 ring->count_dw--;
2442 ring->ring_free_dw--;
771fe6b9 2443}
ce580fab
AK		 2444#else
2445/* With debugging this is just too big to inline */
e32eb50d 2446void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
ce580fab 2447#endif
771fe6b9
JG		 2448
2449/*
2450 * ASICs macro.
2451 */
068a117c 2452#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2453#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2454#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2455#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2456#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2457#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2458#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850
AD		 2459#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2460#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
05b07147
CK		 2461#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2462#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
43f1214a 2463#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
76a0df85
CK		 2464#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2465#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2466#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2467#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2468#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2469#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2470#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2471#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2472#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2473#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2474#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2475#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2476#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2477#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2478#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2479#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2480#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2481#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2482#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
27cd7769
AD		 2483#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2484#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2485#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2486#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2487#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2488#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2489#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2490#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2491#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2492#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2493#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2494#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2495#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2496#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
6bd1c385 2497#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2498#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2499#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2500#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2501#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2502#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2503#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2504#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2505#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2506#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2507#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2508#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2509#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2510#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8
AD		 2511#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2512#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2513#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2514#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2515#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2516#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2517#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2518#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2519#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2520#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2521#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2522#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2523#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2524#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2525#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2526#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2527#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2528#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2529#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2530#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2531#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2532#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2533#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
771fe6b9 2534
6cf8a3f5 2535/* Common functions */
700a0cc0 2536/* AGP */
90aca4d2 2537extern int radeon_gpu_reset(struct radeon_device *rdev);
410a3418 2538extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2539extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2540extern int radeon_modeset_init(struct radeon_device *rdev);
2541extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2542extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2543extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2544extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2545extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2546extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2547extern void radeon_wb_fini(struct radeon_device *rdev);
2548extern int radeon_wb_init(struct radeon_device *rdev);
2549extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2550extern void radeon_surface_init(struct radeon_device *rdev);
2551extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2552extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2553extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2554extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2555extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 2556extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2557extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
6a9ee8af
DA		 2558extern int radeon_resume_kms(struct drm_device *dev);
2559extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
53595338 2560extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2561extern void radeon_program_register_sequence(struct radeon_device *rdev,
2562 const u32 *registers,
2563 const u32 array_size);
6cf8a3f5 2564
721604a1
JG		 2565/*
2566 * vm
2567 */
2568int radeon_vm_manager_init(struct radeon_device *rdev);
2569void radeon_vm_manager_fini(struct radeon_device *rdev);
d72d43cf 2570void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2571void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
ddf03f5c 2572int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
13e55c38 2573void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
ee60e29f
CK		 2574struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2575 struct radeon_vm *vm, int ring);
2576void radeon_vm_fence(struct radeon_device *rdev,
2577 struct radeon_vm *vm,
2578 struct radeon_fence *fence);
dce34bfd 2579uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
721604a1
JG		 2580int radeon_vm_bo_update_pte(struct radeon_device *rdev,
2581 struct radeon_vm *vm,
2582 struct radeon_bo *bo,
2583 struct ttm_mem_reg *mem);
2584void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2585 struct radeon_bo *bo);
421ca7ab
CK		 2586struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2587 struct radeon_bo *bo);
e971bd5e
CK		 2588struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2589 struct radeon_vm *vm,
2590 struct radeon_bo *bo);
2591int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2592 struct radeon_bo_va *bo_va,
2593 uint64_t offset,
2594 uint32_t flags);
721604a1 2595int radeon_vm_bo_rmv(struct radeon_device *rdev,
e971bd5e 2596 struct radeon_bo_va *bo_va);
721604a1 2597
f122c610
AD		 2598/* audio */
2599void r600_audio_update_hdmi(struct work_struct *work);
721604a1 2600
16cdf04d
AD		 2601/*
2602 * R600 vram scratch functions
2603 */
2604int r600_vram_scratch_init(struct radeon_device *rdev);
2605void r600_vram_scratch_fini(struct radeon_device *rdev);
2606
285484e2
JG		 2607/*
2608 * r600 cs checking helper
2609 */
2610unsigned r600_mip_minify(unsigned size, unsigned level);
2611bool r600_fmt_is_valid_color(u32 format);
2612bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2613int r600_fmt_get_blocksize(u32 format);
2614int r600_fmt_get_nblocksx(u32 format, u32 w);
2615int r600_fmt_get_nblocksy(u32 format, u32 h);
2616
3574dda4
DV		 2617/*
2618 * r600 functions used by radeon_encoder.c
2619 */
1b688d08
RM		 2620struct radeon_hdmi_acr {
2621 u32 clock;
2622
2623 int n_32khz;
2624 int cts_32khz;
2625
2626 int n_44_1khz;
2627 int cts_44_1khz;
2628
2629 int n_48khz;
2630 int cts_48khz;
2631
2632};
2633
e55d3e6c
RM		 2634extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2635
416a2bd2
AD		 2636extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2637 u32 tiling_pipe_num,
2638 u32 max_rb_num,
2639 u32 total_max_rb_num,
2640 u32 enabled_rb_mask);
fe251e2f 2641
e55d3e6c
RM		 2642/*
2643 * evergreen functions used by radeon_encoder.c
2644 */
2645
0af62b01 2646extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2647extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2648
c4917074
AD		 2649/* radeon_acpi.c */
2650#if defined(CONFIG_ACPI)
2651extern int radeon_acpi_init(struct radeon_device *rdev);
2652extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2653extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2654extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2655 u8 perf_req, bool advertise);
dc50ba7f 2656extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2657#else
2658static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2659static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2660#endif
d7a2952f 2661
c38f34b5
IH		 2662int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2663 struct radeon_cs_packet *pkt,
2664 unsigned idx);
9ffb7a6d 2665bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2666void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2667 struct radeon_cs_packet *pkt);
e9716993
IH		 2668int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2669 struct radeon_cs_reloc **cs_reloc,
2670 int nomm);
40592a17
IH		 2671int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2672 uint32_t *vline_start_end,
2673 uint32_t *vline_status);
c38f34b5 2674
4c788679
JG		 2675#include "radeon_object.h"
2676
771fe6b9 2677#endif
Linux kernel - Deliverables
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