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drm/radeon: make VM size a module parameter (v2)
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
a18cee15 96extern int radeon_msi;
3368ff0c 97extern int radeon_lockup_timeout;
a0a53aa8 98extern int radeon_fastfb;
da321c8a 99extern int radeon_dpm;
1294d4a3 100extern int radeon_aspm;
10ebc0bc 101extern int radeon_runtime_pm;
363eb0b4 102extern int radeon_hard_reset;
c1c44132 103extern int radeon_vm_size;
771fe6b9
JG		 104
105/*
106 * Copy from radeon_drv.h so we don't have to include both and have conflicting
107 * symbol;
108 */
bb635567
JG		 109#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
110#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 111/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 112#define RADEON_IB_POOL_SIZE 16
113#define RADEON_DEBUGFS_MAX_COMPONENTS 32
114#define RADEONFB_CONN_LIMIT 4
115#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 116
bb635567
JG		 117/* fence seq are set to this number when signaled */
118#define RADEON_FENCE_SIGNALED_SEQ 0LL
1b37078b
AD		 119
120/* internal ring indices */
121/* r1xx+ has gfx CP ring */
d93f7937 122#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 123
124/* cayman has 2 compute CP rings */
d93f7937
CK		 125#define CAYMAN_RING_TYPE_CP1_INDEX 1
126#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 127
4d75658b
AD		 128/* R600+ has an async dma ring */
129#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 130/* cayman add a second async dma ring */
131#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 132
f2ba57b5 133/* R600+ */
d93f7937
CK		 134#define R600_RING_TYPE_UVD_INDEX 5
135
136/* TN+ */
137#define TN_RING_TYPE_VCE1_INDEX 6
138#define TN_RING_TYPE_VCE2_INDEX 7
139
140/* max number of rings */
141#define RADEON_NUM_RINGS 8
f2ba57b5 142
1c61eae4
CK		 143/* number of hw syncs before falling back on blocking */
144#define RADEON_NUM_SYNCS 4
f2ba57b5 145
8f53492f
CK		 146/* number of hw syncs before falling back on blocking */
147#define RADEON_NUM_SYNCS 4
148
721604a1 149/* hardcode those limit for now */
ca19f21e 150#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 151#define RADEON_VA_RESERVED_SIZE (8 << 20)
152#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 153
1a0041b8
AD		 154/* hard reset data */
155#define RADEON_ASIC_RESET_DATA 0x39d5e86b
156
ec46c76d
AD		 157/* reset flags */
158#define RADEON_RESET_GFX (1 << 0)
159#define RADEON_RESET_COMPUTE (1 << 1)
160#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 161#define RADEON_RESET_CP (1 << 3)
162#define RADEON_RESET_GRBM (1 << 4)
163#define RADEON_RESET_DMA1 (1 << 5)
164#define RADEON_RESET_RLC (1 << 6)
165#define RADEON_RESET_SEM (1 << 7)
166#define RADEON_RESET_IH (1 << 8)
167#define RADEON_RESET_VMC (1 << 9)
168#define RADEON_RESET_MC (1 << 10)
169#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 170
22c775ce
AD		 171/* CG block flags */
172#define RADEON_CG_BLOCK_GFX (1 << 0)
173#define RADEON_CG_BLOCK_MC (1 << 1)
174#define RADEON_CG_BLOCK_SDMA (1 << 2)
175#define RADEON_CG_BLOCK_UVD (1 << 3)
176#define RADEON_CG_BLOCK_VCE (1 << 4)
177#define RADEON_CG_BLOCK_HDP (1 << 5)
e16866ec 178#define RADEON_CG_BLOCK_BIF (1 << 6)
22c775ce 179
64d8a728
AD		 180/* CG flags */
181#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
182#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
183#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
184#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
185#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
186#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
187#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
188#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
189#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
190#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
191#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
192#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
193#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
194#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
195#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
196#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
197#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
198
199/* PG flags */
2b19d17f 200#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
64d8a728
AD		 201#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
202#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
203#define RADEON_PG_SUPPORT_UVD (1 << 3)
204#define RADEON_PG_SUPPORT_VCE (1 << 4)
205#define RADEON_PG_SUPPORT_CP (1 << 5)
206#define RADEON_PG_SUPPORT_GDS (1 << 6)
207#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
208#define RADEON_PG_SUPPORT_SDMA (1 << 8)
209#define RADEON_PG_SUPPORT_ACP (1 << 9)
210#define RADEON_PG_SUPPORT_SAMU (1 << 10)
211
9e05fa1d
AD		 212/* max cursor sizes (in pixels) */
213#define CURSOR_WIDTH 64
214#define CURSOR_HEIGHT 64
215
216#define CIK_CURSOR_WIDTH 128
217#define CIK_CURSOR_HEIGHT 128
218
771fe6b9
JG		 219/*
220 * Errata workarounds.
221 */
222enum radeon_pll_errata {
223 CHIP_ERRATA_R300_CG = 0x00000001,
224 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
225 CHIP_ERRATA_PLL_DELAY = 0x00000004
226};
227
228
229struct radeon_device;
230
231
232/*
233 * BIOS.
234 */
235bool radeon_get_bios(struct radeon_device *rdev);
236
237/*
3ce0a23d 238 * Dummy page
771fe6b9 239 */
3ce0a23d
JG		 240struct radeon_dummy_page {
241 struct page *page;
242 dma_addr_t addr;
243};
244int radeon_dummy_page_init(struct radeon_device *rdev);
245void radeon_dummy_page_fini(struct radeon_device *rdev);
246
771fe6b9 247
3ce0a23d
JG		 248/*
249 * Clocks
250 */
771fe6b9
JG		 251struct radeon_clock {
252 struct radeon_pll p1pll;
253 struct radeon_pll p2pll;
bcc1c2a1 254 struct radeon_pll dcpll;
771fe6b9
JG		 255 struct radeon_pll spll;
256 struct radeon_pll mpll;
257 /* 10 Khz units */
258 uint32_t default_mclk;
259 uint32_t default_sclk;
bcc1c2a1 260 uint32_t default_dispclk;
4489cd62 261 uint32_t current_dispclk;
bcc1c2a1 262 uint32_t dp_extclk;
b20f9bef 263 uint32_t max_pixel_clock;
771fe6b9
JG		 264};
265
7433874e
RM		 266/*
267 * Power management
268 */
269int radeon_pm_init(struct radeon_device *rdev);
914a8987 270int radeon_pm_late_init(struct radeon_device *rdev);
29fb52ca 271void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 272void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 273void radeon_pm_suspend(struct radeon_device *rdev);
274void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 275void radeon_combios_get_power_modes(struct radeon_device *rdev);
276void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 277int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
278 u8 clock_type,
279 u32 clock,
280 bool strobe_mode,
281 struct atom_clock_dividers *dividers);
eaa778af
AD		 282int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
283 u32 clock,
284 bool strobe_mode,
285 struct atom_mpll_param *mpll_param);
8a83ec5e 286void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 287int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
288 u16 voltage_level, u8 voltage_type,
289 u32 *gpio_value, u32 *gpio_mask);
290void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
291 u32 eng_clock, u32 mem_clock);
292int radeon_atom_get_voltage_step(struct radeon_device *rdev,
293 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 294int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
295 u16 voltage_id, u16 *voltage);
beb79f40
AD		 296int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
297 u16 *voltage,
298 u16 leakage_idx);
cc8dbbb4
AD		 299int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
300 u16 *leakage_id);
301int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
302 u16 *vddc, u16 *vddci,
303 u16 virtual_voltage_id,
304 u16 vbios_voltage_id);
ae5b0abb
AD		 305int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
306 u8 voltage_type,
307 u16 nominal_voltage,
308 u16 *true_voltage);
309int radeon_atom_get_min_voltage(struct radeon_device *rdev,
310 u8 voltage_type, u16 *min_voltage);
311int radeon_atom_get_max_voltage(struct radeon_device *rdev,
312 u8 voltage_type, u16 *max_voltage);
313int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 314 u8 voltage_type, u8 voltage_mode,
ae5b0abb 315 struct atom_voltage_table *voltage_table);
58653abd
AD		 316bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
317 u8 voltage_type, u8 voltage_mode);
ae5b0abb
AD		 318void radeon_atom_update_memory_dll(struct radeon_device *rdev,
319 u32 mem_clock);
320void radeon_atom_set_ac_timing(struct radeon_device *rdev,
321 u32 mem_clock);
322int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
323 u8 module_index,
324 struct atom_mc_reg_table *reg_table);
325int radeon_atom_get_memory_info(struct radeon_device *rdev,
326 u8 module_index, struct atom_memory_info *mem_info);
327int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
328 bool gddr5, u8 module_index,
329 struct atom_memory_clock_range_table *mclk_range_table);
330int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
331 u16 voltage_id, u16 *voltage);
f892034a 332void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 333extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
334 unsigned *bankh, unsigned *mtaspect,
335 unsigned *tile_split);
3ce0a23d 336
771fe6b9
JG		 337/*
338 * Fences.
339 */
340struct radeon_fence_driver {
341 uint32_t scratch_reg;
30eb77f4
JG		 342 uint64_t gpu_addr;
343 volatile uint32_t *cpu_addr;
68e250b7
CK		 344 /* sync_seq is protected by ring emission lock */
345 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 346 atomic64_t last_seq;
0a0c7596 347 bool initialized;
771fe6b9
JG		 348};
349
350struct radeon_fence {
351 struct radeon_device *rdev;
352 struct kref kref;
771fe6b9 353 /* protected by radeon_fence.lock */
bb635567 354 uint64_t seq;
7465280c 355 /* RB, DMA, etc. */
bb635567 356 unsigned ring;
771fe6b9
JG		 357};
358
30eb77f4
JG		 359int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
360int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 361void radeon_fence_driver_fini(struct radeon_device *rdev);
76903b96 362void radeon_fence_driver_force_completion(struct radeon_device *rdev);
876dc9f3 363int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 364void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 365bool radeon_fence_signaled(struct radeon_fence *fence);
366int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
37615527
CK		 367int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
368int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
0085c950
JG		 369int radeon_fence_wait_any(struct radeon_device *rdev,
370 struct radeon_fence **fences,
371 bool intr);
771fe6b9
JG		 372struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
373void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 374unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 375bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
376void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
377static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
378 struct radeon_fence *b)
379{
380 if (!a) {
381 return b;
382 }
383
384 if (!b) {
385 return a;
386 }
387
388 BUG_ON(a->ring != b->ring);
389
390 if (a->seq > b->seq) {
391 return a;
392 } else {
393 return b;
394 }
395}
771fe6b9 396
ee60e29f
CK		 397static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
398 struct radeon_fence *b)
399{
400 if (!a) {
401 return false;
402 }
403
404 if (!b) {
405 return true;
406 }
407
408 BUG_ON(a->ring != b->ring);
409
410 return a->seq < b->seq;
411}
412
e024e110
DA		 413/*
414 * Tiling registers
415 */
416struct radeon_surface_reg {
4c788679 417 struct radeon_bo *bo;
e024e110
DA		 418};
419
420#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 421
422/*
4c788679 423 * TTM.
771fe6b9 424 */
4c788679
JG		 425struct radeon_mman {
426 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 427 struct drm_global_reference mem_global_ref;
4c788679 428 struct ttm_bo_device bdev;
0a0c7596
JG		 429 bool mem_global_referenced;
430 bool initialized;
2014b569
CK		 431
432#if defined(CONFIG_DEBUG_FS)
433 struct dentry *vram;
dd66d20e 434 struct dentry *gtt;
2014b569 435#endif
4c788679
JG		 436};
437
721604a1
JG		 438/* bo virtual address in a specific vm */
439struct radeon_bo_va {
e971bd5e 440 /* protected by bo being reserved */
721604a1 441 struct list_head bo_list;
721604a1
JG		 442 uint64_t soffset;
443 uint64_t eoffset;
444 uint32_t flags;
445 bool valid;
e971bd5e
CK		 446 unsigned ref_count;
447
448 /* protected by vm mutex */
449 struct list_head vm_list;
450
451 /* constant after initialization */
452 struct radeon_vm *vm;
453 struct radeon_bo *bo;
721604a1
JG		 454};
455
4c788679
JG		 456struct radeon_bo {
457 /* Protected by gem.mutex */
458 struct list_head list;
459 /* Protected by tbo.reserved */
bda72d58 460 u32 initial_domain;
312ea8da
JG		 461 u32 placements[3];
462 struct ttm_placement placement;
4c788679
JG		 463 struct ttm_buffer_object tbo;
464 struct ttm_bo_kmap_obj kmap;
465 unsigned pin_count;
466 void *kptr;
467 u32 tiling_flags;
468 u32 pitch;
469 int surface_reg;
721604a1
JG		 470 /* list of all virtual address to which this bo
471 * is associated to
472 */
473 struct list_head va;
4c788679
JG		 474 /* Constant after initialization */
475 struct radeon_device *rdev;
441921d5 476 struct drm_gem_object gem_base;
63bc620b 477
409851f4
JG		 478 struct ttm_bo_kmap_obj dma_buf_vmap;
479 pid_t pid;
4c788679 480};
7e4d15d9 481#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 482
409851f4
JG		 483int radeon_gem_debugfs_init(struct radeon_device *rdev);
484
b15ba512
JG		 485/* sub-allocation manager, it has to be protected by another lock.
486 * By conception this is an helper for other part of the driver
487 * like the indirect buffer or semaphore, which both have their
488 * locking.
489 *
490 * Principe is simple, we keep a list of sub allocation in offset
491 * order (first entry has offset == 0, last entry has the highest
492 * offset).
493 *
494 * When allocating new object we first check if there is room at
495 * the end total_size - (last_object_offset + last_object_size) >=
496 * alloc_size. If so we allocate new object there.
497 *
498 * When there is not enough room at the end, we start waiting for
499 * each sub object until we reach object_offset+object_size >=
500 * alloc_size, this object then become the sub object we return.
501 *
502 * Alignment can't be bigger than page size.
503 *
504 * Hole are not considered for allocation to keep things simple.
505 * Assumption is that there won't be hole (all object on same
506 * alignment).
507 */
508struct radeon_sa_manager {
bfb38d35 509 wait_queue_head_t wq;
b15ba512 510 struct radeon_bo *bo;
c3b7fe8b
CK		 511 struct list_head *hole;
512 struct list_head flist[RADEON_NUM_RINGS];
513 struct list_head olist;
b15ba512
JG		 514 unsigned size;
515 uint64_t gpu_addr;
516 void *cpu_ptr;
517 uint32_t domain;
6c4f978b 518 uint32_t align;
b15ba512
JG		 519};
520
521struct radeon_sa_bo;
522
523/* sub-allocation buffer */
524struct radeon_sa_bo {
c3b7fe8b
CK		 525 struct list_head olist;
526 struct list_head flist;
b15ba512 527 struct radeon_sa_manager *manager;
e6661a96
CK		 528 unsigned soffset;
529 unsigned eoffset;
557017a0 530 struct radeon_fence *fence;
b15ba512
JG		 531};
532
771fe6b9
JG		 533/*
534 * GEM objects.
535 */
536struct radeon_gem {
4c788679 537 struct mutex mutex;
771fe6b9
JG		 538 struct list_head objects;
539};
540
541int radeon_gem_init(struct radeon_device *rdev);
542void radeon_gem_fini(struct radeon_device *rdev);
543int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 544 int alignment, int initial_domain,
545 bool discardable, bool kernel,
546 struct drm_gem_object **obj);
771fe6b9 547
ff72145b
DA		 548int radeon_mode_dumb_create(struct drm_file *file_priv,
549 struct drm_device *dev,
550 struct drm_mode_create_dumb *args);
551int radeon_mode_dumb_mmap(struct drm_file *filp,
552 struct drm_device *dev,
553 uint32_t handle, uint64_t *offset_p);
771fe6b9 554
c1341e52
JG		 555/*
556 * Semaphores.
557 */
c1341e52 558struct radeon_semaphore {
a8c05940
JG		 559 struct radeon_sa_bo *sa_bo;
560 signed waiters;
c1341e52 561 uint64_t gpu_addr;
1654b817 562 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
c1341e52
JG		 563};
564
c1341e52
JG		 565int radeon_semaphore_create(struct radeon_device *rdev,
566 struct radeon_semaphore **semaphore);
1654b817 567bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
c1341e52 568 struct radeon_semaphore *semaphore);
1654b817 569bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
c1341e52 570 struct radeon_semaphore *semaphore);
1654b817
CK		 571void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
572 struct radeon_fence *fence);
8f676c4c
CK		 573int radeon_semaphore_sync_rings(struct radeon_device *rdev,
574 struct radeon_semaphore *semaphore,
1654b817 575 int waiting_ring);
c1341e52 576void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 577 struct radeon_semaphore **semaphore,
a8c05940 578 struct radeon_fence *fence);
c1341e52 579
771fe6b9
JG		 580/*
581 * GART structures, functions & helpers
582 */
583struct radeon_mc;
584
a77f1718 585#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 586#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 587#define RADEON_GPU_PAGE_SHIFT 12
721604a1 588#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 589
771fe6b9
JG		 590struct radeon_gart {
591 dma_addr_t table_addr;
c9a1be96
JG		 592 struct radeon_bo *robj;
593 void *ptr;
771fe6b9
JG		 594 unsigned num_gpu_pages;
595 unsigned num_cpu_pages;
596 unsigned table_size;
771fe6b9
JG		 597 struct page **pages;
598 dma_addr_t *pages_addr;
599 bool ready;
600};
601
602int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
603void radeon_gart_table_ram_free(struct radeon_device *rdev);
604int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
605void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 606int radeon_gart_table_vram_pin(struct radeon_device *rdev);
607void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 608int radeon_gart_init(struct radeon_device *rdev);
609void radeon_gart_fini(struct radeon_device *rdev);
610void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
611 int pages);
612int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516
KRW		 613 int pages, struct page **pagelist,
614 dma_addr_t *dma_addr);
c9a1be96 615void radeon_gart_restore(struct radeon_device *rdev);
771fe6b9
JG		 616
617
618/*
619 * GPU MC structures, functions & helpers
620 */
621struct radeon_mc {
622 resource_size_t aper_size;
623 resource_size_t aper_base;
624 resource_size_t agp_base;
7a50f01a
DA		 625 /* for some chips with <= 32MB we need to lie
626 * about vram size near mc fb location */
3ce0a23d 627 u64 mc_vram_size;
d594e46a 628 u64 visible_vram_size;
3ce0a23d
JG		 629 u64 gtt_size;
630 u64 gtt_start;
631 u64 gtt_end;
3ce0a23d
JG		 632 u64 vram_start;
633 u64 vram_end;
771fe6b9 634 unsigned vram_width;
3ce0a23d 635 u64 real_vram_size;
771fe6b9
JG		 636 int vram_mtrr;
637 bool vram_is_ddr;
d594e46a 638 bool igp_sideport_enabled;
8d369bb1 639 u64 gtt_base_align;
9ed8b1f9 640 u64 mc_mask;
771fe6b9
JG		 641};
642
06b6476d
AD		 643bool radeon_combios_sideport_present(struct radeon_device *rdev);
644bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 645
646/*
647 * GPU scratch registers structures, functions & helpers
648 */
649struct radeon_scratch {
650 unsigned num_reg;
724c80e1 651 uint32_t reg_base;
771fe6b9
JG		 652 bool free[32];
653 uint32_t reg[32];
654};
655
656int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
657void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
658
75efdee1
AD		 659/*
660 * GPU doorbell structures, functions & helpers
661 */
d5754ab8
AL		 662#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
663
75efdee1 664struct radeon_doorbell {
75efdee1 665 /* doorbell mmio */
d5754ab8
AL		 666 resource_size_t base;
667 resource_size_t size;
668 u32 __iomem *ptr;
669 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
670 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
75efdee1
AD		 671};
672
673int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
674void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771fe6b9
JG		 675
676/*
677 * IRQS.
678 */
6f34be50 679
fa7f517c
CK		 680struct radeon_flip_work {
681 struct work_struct flip_work;
682 struct work_struct unpin_work;
683 struct radeon_device *rdev;
684 int crtc_id;
685 struct drm_framebuffer *fb;
6f34be50 686 struct drm_pending_vblank_event *event;
fa7f517c
CK		 687 struct radeon_bo *old_rbo;
688 struct radeon_bo *new_rbo;
689 struct radeon_fence *fence;
6f34be50
AD		 690};
691
692struct r500_irq_stat_regs {
693 u32 disp_int;
f122c610 694 u32 hdmi0_status;
6f34be50
AD		 695};
696
697struct r600_irq_stat_regs {
698 u32 disp_int;
699 u32 disp_int_cont;
700 u32 disp_int_cont2;
701 u32 d1grph_int;
702 u32 d2grph_int;
f122c610
AD		 703 u32 hdmi0_status;
704 u32 hdmi1_status;
6f34be50
AD		 705};
706
707struct evergreen_irq_stat_regs {
708 u32 disp_int;
709 u32 disp_int_cont;
710 u32 disp_int_cont2;
711 u32 disp_int_cont3;
712 u32 disp_int_cont4;
713 u32 disp_int_cont5;
714 u32 d1grph_int;
715 u32 d2grph_int;
716 u32 d3grph_int;
717 u32 d4grph_int;
718 u32 d5grph_int;
719 u32 d6grph_int;
f122c610
AD		 720 u32 afmt_status1;
721 u32 afmt_status2;
722 u32 afmt_status3;
723 u32 afmt_status4;
724 u32 afmt_status5;
725 u32 afmt_status6;
6f34be50
AD		 726};
727
a59781bb
AD		 728struct cik_irq_stat_regs {
729 u32 disp_int;
730 u32 disp_int_cont;
731 u32 disp_int_cont2;
732 u32 disp_int_cont3;
733 u32 disp_int_cont4;
734 u32 disp_int_cont5;
735 u32 disp_int_cont6;
f5d636d2
CK		 736 u32 d1grph_int;
737 u32 d2grph_int;
738 u32 d3grph_int;
739 u32 d4grph_int;
740 u32 d5grph_int;
741 u32 d6grph_int;
a59781bb
AD		 742};
743
6f34be50
AD		 744union radeon_irq_stat_regs {
745 struct r500_irq_stat_regs r500;
746 struct r600_irq_stat_regs r600;
747 struct evergreen_irq_stat_regs evergreen;
a59781bb 748 struct cik_irq_stat_regs cik;
6f34be50
AD		 749};
750
be0949f5 751#define RADEON_MAX_HPD_PINS 7
54bd5206 752#define RADEON_MAX_CRTCS 6
b530602f 753#define RADEON_MAX_AFMT_BLOCKS 7
54bd5206 754
771fe6b9 755struct radeon_irq {
fb98257a
CK		 756 bool installed;
757 spinlock_t lock;
736fc37f 758 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 759 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 760 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 761 wait_queue_head_t vblank_queue;
762 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 763 bool afmt[RADEON_MAX_AFMT_BLOCKS];
764 union radeon_irq_stat_regs stat_regs;
4a6369e9 765 bool dpm_thermal;
771fe6b9
JG		 766};
767
768int radeon_irq_kms_init(struct radeon_device *rdev);
769void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b
AD		 770void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
771void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 772void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
773void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 774void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
775void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
776void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
777void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 778
779/*
e32eb50d 780 * CP & rings.
771fe6b9 781 */
7465280c 782
771fe6b9 783struct radeon_ib {
68470ae7
JG		 784 struct radeon_sa_bo *sa_bo;
785 uint32_t length_dw;
786 uint64_t gpu_addr;
787 uint32_t *ptr;
876dc9f3 788 int ring;
68470ae7 789 struct radeon_fence *fence;
4bf3dd92 790 struct radeon_vm *vm;
68470ae7
JG		 791 bool is_const_ib;
792 struct radeon_semaphore *semaphore;
771fe6b9
JG		 793};
794
e32eb50d 795struct radeon_ring {
4c788679 796 struct radeon_bo *ring_obj;
771fe6b9 797 volatile uint32_t *ring;
5596a9db 798 unsigned rptr_offs;
45df6803 799 unsigned rptr_save_reg;
89d35807
AD		 800 u64 next_rptr_gpu_addr;
801 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 802 unsigned wptr;
803 unsigned wptr_old;
804 unsigned ring_size;
805 unsigned ring_free_dw;
806 int count_dw;
aee4aa73
CK		 807 atomic_t last_rptr;
808 atomic64_t last_activity;
771fe6b9
JG		 809 uint64_t gpu_addr;
810 uint32_t align_mask;
811 uint32_t ptr_mask;
771fe6b9 812 bool ready;
78c5560a 813 u32 nop;
8b25ed34 814 u32 idx;
5f0839c1
JG		 815 u64 last_semaphore_signal_addr;
816 u64 last_semaphore_wait_addr;
963e81f9
AD		 817 /* for CIK queues */
818 u32 me;
819 u32 pipe;
820 u32 queue;
821 struct radeon_bo *mqd_obj;
d5754ab8 822 u32 doorbell_index;
963e81f9
AD		 823 unsigned wptr_offs;
824};
825
826struct radeon_mec {
827 struct radeon_bo *hpd_eop_obj;
828 u64 hpd_eop_gpu_addr;
829 u32 num_pipe;
830 u32 num_mec;
831 u32 num_queue;
771fe6b9
JG		 832};
833
721604a1
JG		 834/*
835 * VM
836 */
ee60e29f 837
fa87e62d 838/* maximum number of VMIDs */
ee60e29f
CK		 839#define RADEON_NUM_VM 16
840
fa87e62d
DC		 841/* defines number of bits in page table versus page directory,
842 * a page is 4KB so we have 12 bits offset, 9 bits in the page
843 * table and the remaining 19 bits are in the page directory */
844#define RADEON_VM_BLOCK_SIZE 9
845
846/* number of entries in page table */
847#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
848
1c01103c
AD		 849/* PTBs (Page Table Blocks) need to be aligned to 32K */
850#define RADEON_VM_PTB_ALIGN_SIZE 32768
851#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
852#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
853
24c16439
CK		 854#define R600_PTE_VALID (1 << 0)
855#define R600_PTE_SYSTEM (1 << 1)
856#define R600_PTE_SNOOPED (1 << 2)
857#define R600_PTE_READABLE (1 << 5)
858#define R600_PTE_WRITEABLE (1 << 6)
859
ec3dbbcb
CK		 860/* PTE (Page Table Entry) fragment field for different page sizes */
861#define R600_PTE_FRAG_4KB (0 << 7)
862#define R600_PTE_FRAG_64KB (4 << 7)
863#define R600_PTE_FRAG_256KB (6 << 7)
864
0e97703c
CK		 865/* flags used for GART page table entries on R600+ */
866#define R600_PTE_GART ( R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED \
867 | R600_PTE_READABLE | R600_PTE_WRITEABLE)
868
6d2f2944
CK		 869struct radeon_vm_pt {
870 struct radeon_bo *bo;
871 uint64_t addr;
872};
873
721604a1 874struct radeon_vm {
721604a1 875 struct list_head va;
ee60e29f 876 unsigned id;
90a51a32
CK		 877
878 /* contains the page directory */
6d2f2944 879 struct radeon_bo *page_directory;
90a51a32 880 uint64_t pd_gpu_addr;
6d2f2944 881 unsigned max_pde_used;
90a51a32
CK		 882
883 /* array of page tables, one for each page directory entry */
6d2f2944 884 struct radeon_vm_pt *page_tables;
90a51a32 885
721604a1
JG		 886 struct mutex mutex;
887 /* last fence for cs using this vm */
888 struct radeon_fence *fence;
9b40e5d8
CK		 889 /* last flush or NULL if we still need to flush */
890 struct radeon_fence *last_flush;
593b2635
CK		 891 /* last use of vmid */
892 struct radeon_fence *last_id_use;
721604a1
JG		 893};
894
721604a1 895struct radeon_vm_manager {
ee60e29f 896 struct radeon_fence *active[RADEON_NUM_VM];
721604a1 897 uint32_t max_pfn;
721604a1
JG		 898 /* number of VMIDs */
899 unsigned nvm;
900 /* vram base address for page table entry */
901 u64 vram_base_offset;
67e915e4
AD		 902 /* is vm enabled? */
903 bool enabled;
721604a1
JG		 904};
905
906/*
907 * file private structure
908 */
909struct radeon_fpriv {
910 struct radeon_vm vm;
911};
912
d8f60cfc
AD		 913/*
914 * R6xx+ IH ring
915 */
916struct r600_ih {
4c788679 917 struct radeon_bo *ring_obj;
d8f60cfc
AD		 918 volatile uint32_t *ring;
919 unsigned rptr;
d8f60cfc
AD		 920 unsigned ring_size;
921 uint64_t gpu_addr;
d8f60cfc 922 uint32_t ptr_mask;
c20dc369 923 atomic_t lock;
d8f60cfc
AD		 924 bool enabled;
925};
926
347e7592 927/*
2948f5e6 928 * RLC stuff
347e7592 929 */
2948f5e6
AD		 930#include "clearstate_defs.h"
931
932struct radeon_rlc {
347e7592
AD		 933 /* for power gating */
934 struct radeon_bo *save_restore_obj;
935 uint64_t save_restore_gpu_addr;
2948f5e6 936 volatile uint32_t *sr_ptr;
1fd11777 937 const u32 *reg_list;
2948f5e6 938 u32 reg_list_size;
347e7592
AD		 939 /* for clear state */
940 struct radeon_bo *clear_state_obj;
941 uint64_t clear_state_gpu_addr;
2948f5e6 942 volatile uint32_t *cs_ptr;
1fd11777 943 const struct cs_section_def *cs_data;
22c775ce
AD		 944 u32 clear_state_size;
945 /* for cp tables */
946 struct radeon_bo *cp_table_obj;
947 uint64_t cp_table_gpu_addr;
948 volatile uint32_t *cp_table_ptr;
949 u32 cp_table_size;
347e7592
AD		 950};
951
69e130a6 952int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 953 struct radeon_ib *ib, struct radeon_vm *vm,
954 unsigned size);
f2e39221 955void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
4ef72566
CK		 956int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
957 struct radeon_ib *const_ib);
771fe6b9
JG		 958int radeon_ib_pool_init(struct radeon_device *rdev);
959void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 960int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 961/* Ring access between begin & end cannot sleep */
89d35807
AD		 962bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
963 struct radeon_ring *ring);
e32eb50d
CK		 964void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
965int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
966int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
967void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
968void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
d6999bc7 969void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 970void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
971int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
ff212f25
CK		 972void radeon_ring_lockup_update(struct radeon_device *rdev,
973 struct radeon_ring *ring);
069211e5 974bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 975unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
976 uint32_t **data);
977int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
978 unsigned size, uint32_t *data);
e32eb50d 979int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
ea31bf69 980 unsigned rptr_offs, u32 nop);
e32eb50d 981void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 982
983
4d75658b
AD		 984/* r600 async dma */
985void r600_dma_stop(struct radeon_device *rdev);
986int r600_dma_resume(struct radeon_device *rdev);
987void r600_dma_fini(struct radeon_device *rdev);
988
8c5fd7ef
AD		 989void cayman_dma_stop(struct radeon_device *rdev);
990int cayman_dma_resume(struct radeon_device *rdev);
991void cayman_dma_fini(struct radeon_device *rdev);
992
771fe6b9
JG		 993/*
994 * CS.
995 */
996struct radeon_cs_reloc {
997 struct drm_gem_object *gobj;
4c788679 998 struct radeon_bo *robj;
df0af440
CK		 999 struct ttm_validate_buffer tv;
1000 uint64_t gpu_offset;
ce6758c8
CK		 1001 unsigned prefered_domains;
1002 unsigned allowed_domains;
df0af440 1003 uint32_t tiling_flags;
771fe6b9 1004 uint32_t handle;
771fe6b9
JG		 1005};
1006
1007struct radeon_cs_chunk {
1008 uint32_t chunk_id;
1009 uint32_t length_dw;
1010 uint32_t *kdata;
721604a1 1011 void __user *user_ptr;
771fe6b9
JG		 1012};
1013
1014struct radeon_cs_parser {
c8c15ff1 1015 struct device *dev;
771fe6b9
JG		 1016 struct radeon_device *rdev;
1017 struct drm_file *filp;
1018 /* chunks */
1019 unsigned nchunks;
1020 struct radeon_cs_chunk *chunks;
1021 uint64_t *chunks_array;
1022 /* IB */
1023 unsigned idx;
1024 /* relocations */
1025 unsigned nrelocs;
1026 struct radeon_cs_reloc *relocs;
1027 struct radeon_cs_reloc **relocs_ptr;
df0af440 1028 struct radeon_cs_reloc *vm_bos;
771fe6b9 1029 struct list_head validated;
cf4ccd01 1030 unsigned dma_reloc_idx;
771fe6b9
JG		 1031 /* indices of various chunks */
1032 int chunk_ib_idx;
1033 int chunk_relocs_idx;
721604a1 1034 int chunk_flags_idx;
dfcf5f36 1035 int chunk_const_ib_idx;
f2e39221
JG		 1036 struct radeon_ib ib;
1037 struct radeon_ib const_ib;
771fe6b9 1038 void *track;
3ce0a23d 1039 unsigned family;
e70f224c 1040 int parser_error;
721604a1
JG		 1041 u32 cs_flags;
1042 u32 ring;
1043 s32 priority;
ecff665f 1044 struct ww_acquire_ctx ticket;
771fe6b9
JG		 1045};
1046
28a326c5
ML		 1047static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1048{
1049 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1050
1051 if (ibc->kdata)
1052 return ibc->kdata[idx];
1053 return p->ib.ptr[idx];
1054}
1055
513bcb46 1056
771fe6b9
JG		 1057struct radeon_cs_packet {
1058 unsigned idx;
1059 unsigned type;
1060 unsigned reg;
1061 unsigned opcode;
1062 int count;
1063 unsigned one_reg_wr;
1064};
1065
1066typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1067 struct radeon_cs_packet *pkt,
1068 unsigned idx, unsigned reg);
1069typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1070 struct radeon_cs_packet *pkt);
1071
1072
1073/*
1074 * AGP
1075 */
1076int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1077void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1078void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1079void radeon_agp_fini(struct radeon_device *rdev);
1080
1081
1082/*
1083 * Writeback
1084 */
1085struct radeon_wb {
4c788679 1086 struct radeon_bo *wb_obj;
771fe6b9
JG		 1087 volatile uint32_t *wb;
1088 uint64_t gpu_addr;
724c80e1 1089 bool enabled;
d0f8a854 1090 bool use_event;
771fe6b9
JG		 1091};
1092
724c80e1 1093#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1094#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1095#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1096#define RADEON_WB_CP1_RPTR_OFFSET 1280
1097#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1098#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1099#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1100#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1101#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1102#define CIK_WB_CP1_WPTR_OFFSET 3328
1103#define CIK_WB_CP2_WPTR_OFFSET 3584
724c80e1 1104
c93bb85b
JG		 1105/**
1106 * struct radeon_pm - power management datas
1107 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1108 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1109 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1110 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1111 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1112 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1113 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1114 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1115 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1116 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1117 * @needed_bandwidth: current bandwidth needs
1118 *
1119 * It keeps track of various data needed to take powermanagement decision.
25985edc 1120 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1121 * Equation between gpu/memory clock and available bandwidth is hw dependent
1122 * (type of memory, bus size, efficiency, ...)
1123 */
ce8f5370
AD		 1124
1125enum radeon_pm_method {
1126 PM_METHOD_PROFILE,
1127 PM_METHOD_DYNPM,
da321c8a 1128 PM_METHOD_DPM,
ce8f5370
AD		 1129};
1130
1131enum radeon_dynpm_state {
1132 DYNPM_STATE_DISABLED,
1133 DYNPM_STATE_MINIMUM,
1134 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1135 DYNPM_STATE_ACTIVE,
1136 DYNPM_STATE_SUSPENDED,
c913e23a 1137};
ce8f5370
AD		 1138enum radeon_dynpm_action {
1139 DYNPM_ACTION_NONE,
1140 DYNPM_ACTION_MINIMUM,
1141 DYNPM_ACTION_DOWNCLOCK,
1142 DYNPM_ACTION_UPCLOCK,
1143 DYNPM_ACTION_DEFAULT
c913e23a 1144};
56278a8e
AD		 1145
1146enum radeon_voltage_type {
1147 VOLTAGE_NONE = 0,
1148 VOLTAGE_GPIO,
1149 VOLTAGE_VDDC,
1150 VOLTAGE_SW
1151};
1152
0ec0e74f 1153enum radeon_pm_state_type {
da321c8a 1154 /* not used for dpm */
0ec0e74f
AD		 1155 POWER_STATE_TYPE_DEFAULT,
1156 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1157 /* user selectable states */
0ec0e74f
AD		 1158 POWER_STATE_TYPE_BATTERY,
1159 POWER_STATE_TYPE_BALANCED,
1160 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1161 /* internal states */
1162 POWER_STATE_TYPE_INTERNAL_UVD,
1163 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1164 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1165 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1166 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1167 POWER_STATE_TYPE_INTERNAL_BOOT,
1168 POWER_STATE_TYPE_INTERNAL_THERMAL,
1169 POWER_STATE_TYPE_INTERNAL_ACPI,
1170 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1171 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1172};
1173
ce8f5370
AD		 1174enum radeon_pm_profile_type {
1175 PM_PROFILE_DEFAULT,
1176 PM_PROFILE_AUTO,
1177 PM_PROFILE_LOW,
c9e75b21 1178 PM_PROFILE_MID,
ce8f5370
AD		 1179 PM_PROFILE_HIGH,
1180};
1181
1182#define PM_PROFILE_DEFAULT_IDX 0
1183#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1184#define PM_PROFILE_MID_SH_IDX 2
1185#define PM_PROFILE_HIGH_SH_IDX 3
1186#define PM_PROFILE_LOW_MH_IDX 4
1187#define PM_PROFILE_MID_MH_IDX 5
1188#define PM_PROFILE_HIGH_MH_IDX 6
1189#define PM_PROFILE_MAX 7
ce8f5370
AD		 1190
1191struct radeon_pm_profile {
1192 int dpms_off_ps_idx;
1193 int dpms_on_ps_idx;
1194 int dpms_off_cm_idx;
1195 int dpms_on_cm_idx;
516d0e46
AD		 1196};
1197
21a8122a
AD		 1198enum radeon_int_thermal_type {
1199 THERMAL_TYPE_NONE,
da321c8a
AD		 1200 THERMAL_TYPE_EXTERNAL,
1201 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1202 THERMAL_TYPE_RV6XX,
1203 THERMAL_TYPE_RV770,
da321c8a 1204 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1205 THERMAL_TYPE_EVERGREEN,
e33df25f 1206 THERMAL_TYPE_SUMO,
4fddba1f 1207 THERMAL_TYPE_NI,
14607d08 1208 THERMAL_TYPE_SI,
da321c8a 1209 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1210 THERMAL_TYPE_CI,
16fbe00d 1211 THERMAL_TYPE_KV,
21a8122a
AD		 1212};
1213
56278a8e
AD		 1214struct radeon_voltage {
1215 enum radeon_voltage_type type;
1216 /* gpio voltage */
1217 struct radeon_gpio_rec gpio;
1218 u32 delay; /* delay in usec from voltage drop to sclk change */
1219 bool active_high; /* voltage drop is active when bit is high */
1220 /* VDDC voltage */
1221 u8 vddc_id; /* index into vddc voltage table */
1222 u8 vddci_id; /* index into vddci voltage table */
1223 bool vddci_enabled;
1224 /* r6xx+ sw */
2feea49a
AD		 1225 u16 voltage;
1226 /* evergreen+ vddci */
1227 u16 vddci;
56278a8e
AD		 1228};
1229
d7311171
AD		 1230/* clock mode flags */
1231#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1232
56278a8e
AD		 1233struct radeon_pm_clock_info {
1234 /* memory clock */
1235 u32 mclk;
1236 /* engine clock */
1237 u32 sclk;
1238 /* voltage info */
1239 struct radeon_voltage voltage;
d7311171 1240 /* standardized clock flags */
56278a8e
AD		 1241 u32 flags;
1242};
1243
a48b9b4e 1244/* state flags */
d7311171 1245#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1246
56278a8e 1247struct radeon_power_state {
0ec0e74f 1248 enum radeon_pm_state_type type;
8f3f1c9a 1249 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1250 /* number of valid clock modes in this power state */
1251 int num_clock_modes;
56278a8e 1252 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1253 /* standardized state flags */
1254 u32 flags;
79daedc9
AD		 1255 u32 misc; /* vbios specific flags */
1256 u32 misc2; /* vbios specific flags */
1257 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1258};
1259
27459324
RM		 1260/*
1261 * Some modes are overclocked by very low value, accept them
1262 */
1263#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1264
2e9d4c05
AD		 1265enum radeon_dpm_auto_throttle_src {
1266 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1267 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1268};
1269
1270enum radeon_dpm_event_src {
1271 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1272 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1273 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1274 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1275 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1276};
1277
58bd2a88
AD		 1278#define RADEON_MAX_VCE_LEVELS 6
1279
b62d628b
AD		 1280enum radeon_vce_level {
1281 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1282 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1283 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1284 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1285 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1286 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1287};
1288
da321c8a
AD		 1289struct radeon_ps {
1290 u32 caps; /* vbios flags */
1291 u32 class; /* vbios flags */
1292 u32 class2; /* vbios flags */
1293 /* UVD clocks */
1294 u32 vclk;
1295 u32 dclk;
c4453e66
AD		 1296 /* VCE clocks */
1297 u32 evclk;
1298 u32 ecclk;
b62d628b
AD		 1299 bool vce_active;
1300 enum radeon_vce_level vce_level;
da321c8a
AD		 1301 /* asic priv */
1302 void *ps_priv;
1303};
1304
1305struct radeon_dpm_thermal {
1306 /* thermal interrupt work */
1307 struct work_struct work;
1308 /* low temperature threshold */
1309 int min_temp;
1310 /* high temperature threshold */
1311 int max_temp;
1312 /* was interrupt low to high or high to low */
1313 bool high_to_low;
1314};
1315
d22b7e40
AD		 1316enum radeon_clk_action
1317{
1318 RADEON_SCLK_UP = 1,
1319 RADEON_SCLK_DOWN
1320};
1321
1322struct radeon_blacklist_clocks
1323{
1324 u32 sclk;
1325 u32 mclk;
1326 enum radeon_clk_action action;
1327};
1328
61b7d601
AD		 1329struct radeon_clock_and_voltage_limits {
1330 u32 sclk;
1331 u32 mclk;
cdf6e805
AD		 1332 u16 vddc;
1333 u16 vddci;
61b7d601
AD		 1334};
1335
1336struct radeon_clock_array {
1337 u32 count;
1338 u32 *values;
1339};
1340
1341struct radeon_clock_voltage_dependency_entry {
1342 u32 clk;
1343 u16 v;
1344};
1345
1346struct radeon_clock_voltage_dependency_table {
1347 u32 count;
1348 struct radeon_clock_voltage_dependency_entry *entries;
1349};
1350
ef976ec4
AD		 1351union radeon_cac_leakage_entry {
1352 struct {
1353 u16 vddc;
1354 u32 leakage;
1355 };
1356 struct {
1357 u16 vddc1;
1358 u16 vddc2;
1359 u16 vddc3;
1360 };
61b7d601
AD		 1361};
1362
1363struct radeon_cac_leakage_table {
1364 u32 count;
ef976ec4 1365 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1366};
1367
929ee7a8
AD		 1368struct radeon_phase_shedding_limits_entry {
1369 u16 voltage;
1370 u32 sclk;
1371 u32 mclk;
1372};
1373
1374struct radeon_phase_shedding_limits_table {
1375 u32 count;
1376 struct radeon_phase_shedding_limits_entry *entries;
1377};
1378
84a9d9ee
AD		 1379struct radeon_uvd_clock_voltage_dependency_entry {
1380 u32 vclk;
1381 u32 dclk;
1382 u16 v;
1383};
1384
1385struct radeon_uvd_clock_voltage_dependency_table {
1386 u8 count;
1387 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1388};
1389
d29f013b
AD		 1390struct radeon_vce_clock_voltage_dependency_entry {
1391 u32 ecclk;
1392 u32 evclk;
1393 u16 v;
1394};
1395
1396struct radeon_vce_clock_voltage_dependency_table {
1397 u8 count;
1398 struct radeon_vce_clock_voltage_dependency_entry *entries;
1399};
1400
a5cb318e
AD		 1401struct radeon_ppm_table {
1402 u8 ppm_design;
1403 u16 cpu_core_number;
1404 u32 platform_tdp;
1405 u32 small_ac_platform_tdp;
1406 u32 platform_tdc;
1407 u32 small_ac_platform_tdc;
1408 u32 apu_tdp;
1409 u32 dgpu_tdp;
1410 u32 dgpu_ulv_power;
1411 u32 tj_max;
1412};
1413
58cb7632
AD		 1414struct radeon_cac_tdp_table {
1415 u16 tdp;
1416 u16 configurable_tdp;
1417 u16 tdc;
1418 u16 battery_power_limit;
1419 u16 small_power_limit;
1420 u16 low_cac_leakage;
1421 u16 high_cac_leakage;
1422 u16 maximum_power_delivery_limit;
1423};
1424
61b7d601
AD		 1425struct radeon_dpm_dynamic_state {
1426 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1427 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1428 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1429 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1430 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1431 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1432 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1433 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1434 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1435 struct radeon_clock_array valid_sclk_values;
1436 struct radeon_clock_array valid_mclk_values;
1437 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1438 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1439 u32 mclk_sclk_ratio;
1440 u32 sclk_mclk_delta;
1441 u16 vddc_vddci_delta;
1442 u16 min_vddc_for_pcie_gen2;
1443 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1444 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1445 struct radeon_ppm_table *ppm_table;
58cb7632 1446 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1447};
1448
1449struct radeon_dpm_fan {
1450 u16 t_min;
1451 u16 t_med;
1452 u16 t_high;
1453 u16 pwm_min;
1454 u16 pwm_med;
1455 u16 pwm_high;
1456 u8 t_hyst;
1457 u32 cycle_delay;
1458 u16 t_max;
1459 bool ucode_fan_control;
1460};
1461
32ce4652
AD		 1462enum radeon_pcie_gen {
1463 RADEON_PCIE_GEN1 = 0,
1464 RADEON_PCIE_GEN2 = 1,
1465 RADEON_PCIE_GEN3 = 2,
1466 RADEON_PCIE_GEN_INVALID = 0xffff
1467};
1468
70d01a5e
AD		 1469enum radeon_dpm_forced_level {
1470 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1471 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1472 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1473};
1474
58bd2a88
AD		 1475struct radeon_vce_state {
1476 /* vce clocks */
1477 u32 evclk;
1478 u32 ecclk;
1479 /* gpu clocks */
1480 u32 sclk;
1481 u32 mclk;
1482 u8 clk_idx;
1483 u8 pstate;
1484};
1485
da321c8a
AD		 1486struct radeon_dpm {
1487 struct radeon_ps *ps;
1488 /* number of valid power states */
1489 int num_ps;
1490 /* current power state that is active */
1491 struct radeon_ps *current_ps;
1492 /* requested power state */
1493 struct radeon_ps *requested_ps;
1494 /* boot up power state */
1495 struct radeon_ps *boot_ps;
1496 /* default uvd power state */
1497 struct radeon_ps *uvd_ps;
58bd2a88
AD		 1498 /* vce requirements */
1499 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1500 enum radeon_vce_level vce_level;
da321c8a
AD		 1501 enum radeon_pm_state_type state;
1502 enum radeon_pm_state_type user_state;
1503 u32 platform_caps;
1504 u32 voltage_response_time;
1505 u32 backbias_response_time;
1506 void *priv;
1507 u32 new_active_crtcs;
1508 int new_active_crtc_count;
1509 u32 current_active_crtcs;
1510 int current_active_crtc_count;
61b7d601
AD		 1511 struct radeon_dpm_dynamic_state dyn_state;
1512 struct radeon_dpm_fan fan;
1513 u32 tdp_limit;
1514 u32 near_tdp_limit;
a9e61410 1515 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1516 u32 sq_ramping_threshold;
1517 u32 cac_leakage;
1518 u16 tdp_od_limit;
1519 u32 tdp_adjustment;
1520 u16 load_line_slope;
1521 bool power_control;
5ca302f7 1522 bool ac_power;
da321c8a
AD		 1523 /* special states active */
1524 bool thermal_active;
8a227555 1525 bool uvd_active;
b62d628b 1526 bool vce_active;
da321c8a
AD		 1527 /* thermal handling */
1528 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1529 /* forced levels */
1530 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1531 /* track UVD streams */
1532 unsigned sd;
1533 unsigned hd;
da321c8a
AD		 1534};
1535
ce3537d5 1536void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
03afe6f6 1537void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
da321c8a 1538
c93bb85b 1539struct radeon_pm {
c913e23a 1540 struct mutex mutex;
db7fce39
CK		 1541 /* write locked while reprogramming mclk */
1542 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1543 u32 active_crtcs;
1544 int active_crtc_count;
c913e23a 1545 int req_vblank;
839461d3 1546 bool vblank_sync;
c93bb85b
JG		 1547 fixed20_12 max_bandwidth;
1548 fixed20_12 igp_sideport_mclk;
1549 fixed20_12 igp_system_mclk;
1550 fixed20_12 igp_ht_link_clk;
1551 fixed20_12 igp_ht_link_width;
1552 fixed20_12 k8_bandwidth;
1553 fixed20_12 sideport_bandwidth;
1554 fixed20_12 ht_bandwidth;
1555 fixed20_12 core_bandwidth;
1556 fixed20_12 sclk;
f47299c5 1557 fixed20_12 mclk;
c93bb85b 1558 fixed20_12 needed_bandwidth;
0975b162 1559 struct radeon_power_state *power_state;
56278a8e
AD		 1560 /* number of valid power states */
1561 int num_power_states;
a48b9b4e
AD		 1562 int current_power_state_index;
1563 int current_clock_mode_index;
1564 int requested_power_state_index;
1565 int requested_clock_mode_index;
1566 int default_power_state_index;
1567 u32 current_sclk;
1568 u32 current_mclk;
2feea49a
AD		 1569 u16 current_vddc;
1570 u16 current_vddci;
9ace9f7b
AD		 1571 u32 default_sclk;
1572 u32 default_mclk;
2feea49a
AD		 1573 u16 default_vddc;
1574 u16 default_vddci;
29fb52ca 1575 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1576 /* selected pm method */
1577 enum radeon_pm_method pm_method;
1578 /* dynpm power management */
1579 struct delayed_work dynpm_idle_work;
1580 enum radeon_dynpm_state dynpm_state;
1581 enum radeon_dynpm_action dynpm_planned_action;
1582 unsigned long dynpm_action_timeout;
1583 bool dynpm_can_upclock;
1584 bool dynpm_can_downclock;
1585 /* profile-based power management */
1586 enum radeon_pm_profile_type profile;
1587 int profile_index;
1588 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1589 /* internal thermal controller on rv6xx+ */
1590 enum radeon_int_thermal_type int_thermal_type;
1591 struct device *int_hwmon_dev;
da321c8a
AD		 1592 /* dpm */
1593 bool dpm_enabled;
1594 struct radeon_dpm dpm;
c93bb85b
JG		 1595};
1596
a4c9e2ee
AD		 1597int radeon_pm_get_type_index(struct radeon_device *rdev,
1598 enum radeon_pm_state_type ps_type,
1599 int instance);
f2ba57b5
CK		 1600/*
1601 * UVD
1602 */
1603#define RADEON_MAX_UVD_HANDLES 10
1604#define RADEON_UVD_STACK_SIZE (1024*1024)
1605#define RADEON_UVD_HEAP_SIZE (1024*1024)
1606
1607struct radeon_uvd {
1608 struct radeon_bo *vcpu_bo;
1609 void *cpu_addr;
1610 uint64_t gpu_addr;
9cc2e0e9 1611 void *saved_bo;
f2ba57b5
CK		 1612 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1613 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1614 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1615 struct delayed_work idle_work;
f2ba57b5
CK		 1616};
1617
1618int radeon_uvd_init(struct radeon_device *rdev);
1619void radeon_uvd_fini(struct radeon_device *rdev);
1620int radeon_uvd_suspend(struct radeon_device *rdev);
1621int radeon_uvd_resume(struct radeon_device *rdev);
1622int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1623 uint32_t handle, struct radeon_fence **fence);
1624int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1625 uint32_t handle, struct radeon_fence **fence);
1626void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1627void radeon_uvd_free_handles(struct radeon_device *rdev,
1628 struct drm_file *filp);
1629int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1630void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1631int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1632 unsigned vclk, unsigned dclk,
1633 unsigned vco_min, unsigned vco_max,
1634 unsigned fb_factor, unsigned fb_mask,
1635 unsigned pd_min, unsigned pd_max,
1636 unsigned pd_even,
1637 unsigned *optimal_fb_div,
1638 unsigned *optimal_vclk_div,
1639 unsigned *optimal_dclk_div);
1640int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1641 unsigned cg_upll_func_cntl);
771fe6b9 1642
d93f7937
CK		 1643/*
1644 * VCE
1645 */
1646#define RADEON_MAX_VCE_HANDLES 16
1647#define RADEON_VCE_STACK_SIZE (1024*1024)
1648#define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1649
1650struct radeon_vce {
1651 struct radeon_bo *vcpu_bo;
d93f7937 1652 uint64_t gpu_addr;
98ccc291
CK		 1653 unsigned fw_version;
1654 unsigned fb_version;
d93f7937
CK		 1655 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1656 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
2fc5703a 1657 unsigned img_size[RADEON_MAX_VCE_HANDLES];
03afe6f6 1658 struct delayed_work idle_work;
d93f7937
CK		 1659};
1660
1661int radeon_vce_init(struct radeon_device *rdev);
1662void radeon_vce_fini(struct radeon_device *rdev);
1663int radeon_vce_suspend(struct radeon_device *rdev);
1664int radeon_vce_resume(struct radeon_device *rdev);
1665int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1666 uint32_t handle, struct radeon_fence **fence);
1667int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1668 uint32_t handle, struct radeon_fence **fence);
1669void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
03afe6f6 1670void radeon_vce_note_usage(struct radeon_device *rdev);
2fc5703a 1671int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
d93f7937
CK		 1672int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1673bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1674 struct radeon_ring *ring,
1675 struct radeon_semaphore *semaphore,
1676 bool emit_wait);
1677void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1678void radeon_vce_fence_emit(struct radeon_device *rdev,
1679 struct radeon_fence *fence);
1680int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1681int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1682
b530602f 1683struct r600_audio_pin {
a92553ab
RM		 1684 int channels;
1685 int rate;
1686 int bits_per_sample;
1687 u8 status_bits;
1688 u8 category_code;
b530602f
AD		 1689 u32 offset;
1690 bool connected;
1691 u32 id;
1692};
1693
1694struct r600_audio {
1695 bool enabled;
1696 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1697 int num_pins;
a92553ab
RM		 1698};
1699
771fe6b9
JG		 1700/*
1701 * Benchmarking
1702 */
638dd7db 1703void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1704
1705
ecc0b326
MD		 1706/*
1707 * Testing
1708 */
1709void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1710void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1711 struct radeon_ring *cpA,
1712 struct radeon_ring *cpB);
60a7e396 1713void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326
MD		 1714
1715
771fe6b9
JG		 1716/*
1717 * Debugfs
1718 */
4d8bf9ae
CK		 1719struct radeon_debugfs {
1720 struct drm_info_list *files;
1721 unsigned num_files;
1722};
1723
771fe6b9
JG		 1724int radeon_debugfs_add_files(struct radeon_device *rdev,
1725 struct drm_info_list *files,
1726 unsigned nfiles);
1727int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1728
76a0df85
CK		 1729/*
1730 * ASIC ring specific functions.
1731 */
1732struct radeon_asic_ring {
1733 /* ring read/write ptr handling */
1734 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1735 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1736 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1737
1738 /* validating and patching of IBs */
1739 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1740 int (*cs_parse)(struct radeon_cs_parser *p);
1741
1742 /* command emmit functions */
1743 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1744 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1654b817 1745 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
76a0df85
CK		 1746 struct radeon_semaphore *semaphore, bool emit_wait);
1747 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1748
1749 /* testing functions */
1750 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1751 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1752 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1753
1754 /* deprecated */
1755 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1756};
771fe6b9
JG		 1757
1758/*
1759 * ASIC specific functions.
1760 */
1761struct radeon_asic {
068a117c 1762 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1763 void (*fini)(struct radeon_device *rdev);
1764 int (*resume)(struct radeon_device *rdev);
1765 int (*suspend)(struct radeon_device *rdev);
28d52043 1766 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1767 int (*asic_reset)(struct radeon_device *rdev);
54e88e06
AD		 1768 /* ioctl hw specific callback. Some hw might want to perform special
1769 * operation on specific ioctl. For instance on wait idle some hw
1770 * might want to perform and HDP flush through MMIO as it seems that
1771 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1772 * through ring.
1773 */
1774 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1775 /* check if 3D engine is idle */
1776 bool (*gui_idle)(struct radeon_device *rdev);
1777 /* wait for mc_idle */
1778 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1779 /* get the reference clock */
1780 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1781 /* get the gpu clock counter */
1782 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1783 /* gart */
c5b3b850
AD		 1784 struct {
1785 void (*tlb_flush)(struct radeon_device *rdev);
7f90fc96
CK		 1786 void (*set_page)(struct radeon_device *rdev, unsigned i,
1787 uint64_t addr);
c5b3b850 1788 } gart;
05b07147
CK		 1789 struct {
1790 int (*init)(struct radeon_device *rdev);
1791 void (*fini)(struct radeon_device *rdev);
43f1214a
AD		 1792 void (*set_page)(struct radeon_device *rdev,
1793 struct radeon_ib *ib,
1794 uint64_t pe,
dce34bfd
CK		 1795 uint64_t addr, unsigned count,
1796 uint32_t incr, uint32_t flags);
05b07147 1797 } vm;
54e88e06 1798 /* ring specific callbacks */
76a0df85 1799 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1800 /* irqs */
b35ea4ab
AD		 1801 struct {
1802 int (*set)(struct radeon_device *rdev);
1803 int (*process)(struct radeon_device *rdev);
1804 } irq;
54e88e06 1805 /* displays */
c79a49ca
AD		 1806 struct {
1807 /* display watermarks */
1808 void (*bandwidth_update)(struct radeon_device *rdev);
1809 /* get frame count */
1810 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1811 /* wait for vblank */
1812 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1813 /* set backlight level */
1814 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1815 /* get backlight level */
1816 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1817 /* audio callbacks */
1818 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1819 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1820 } display;
54e88e06 1821 /* copy functions for bo handling */
27cd7769
AD		 1822 struct {
1823 int (*blit)(struct radeon_device *rdev,
1824 uint64_t src_offset,
1825 uint64_t dst_offset,
1826 unsigned num_gpu_pages,
876dc9f3 1827 struct radeon_fence **fence);
27cd7769
AD		 1828 u32 blit_ring_index;
1829 int (*dma)(struct radeon_device *rdev,
1830 uint64_t src_offset,
1831 uint64_t dst_offset,
1832 unsigned num_gpu_pages,
876dc9f3 1833 struct radeon_fence **fence);
27cd7769
AD		 1834 u32 dma_ring_index;
1835 /* method used for bo copy */
1836 int (*copy)(struct radeon_device *rdev,
1837 uint64_t src_offset,
1838 uint64_t dst_offset,
1839 unsigned num_gpu_pages,
876dc9f3 1840 struct radeon_fence **fence);
27cd7769
AD		 1841 /* ring used for bo copies */
1842 u32 copy_ring_index;
1843 } copy;
54e88e06 1844 /* surfaces */
9e6f3d02
AD		 1845 struct {
1846 int (*set_reg)(struct radeon_device *rdev, int reg,
1847 uint32_t tiling_flags, uint32_t pitch,
1848 uint32_t offset, uint32_t obj_size);
1849 void (*clear_reg)(struct radeon_device *rdev, int reg);
1850 } surface;
54e88e06 1851 /* hotplug detect */
901ea57d
AD		 1852 struct {
1853 void (*init)(struct radeon_device *rdev);
1854 void (*fini)(struct radeon_device *rdev);
1855 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1856 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1857 } hpd;
da321c8a 1858 /* static power management */
a02fa397
AD		 1859 struct {
1860 void (*misc)(struct radeon_device *rdev);
1861 void (*prepare)(struct radeon_device *rdev);
1862 void (*finish)(struct radeon_device *rdev);
1863 void (*init_profile)(struct radeon_device *rdev);
1864 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1865 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1866 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1867 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1868 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1869 int (*get_pcie_lanes)(struct radeon_device *rdev);
1870 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1871 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1872 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
b59b7333 1873 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
6bd1c385 1874 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1875 } pm;
da321c8a
AD		 1876 /* dynamic power management */
1877 struct {
1878 int (*init)(struct radeon_device *rdev);
1879 void (*setup_asic)(struct radeon_device *rdev);
1880 int (*enable)(struct radeon_device *rdev);
914a8987 1881 int (*late_enable)(struct radeon_device *rdev);
da321c8a 1882 void (*disable)(struct radeon_device *rdev);
84dd1928 1883 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1884 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1885 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1886 void (*display_configuration_changed)(struct radeon_device *rdev);
1887 void (*fini)(struct radeon_device *rdev);
1888 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1889 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1890 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1891 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1892 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1893 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1894 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1c71bda0 1895 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
da321c8a 1896 } dpm;
6f34be50 1897 /* pageflipping */
0f9e006c 1898 struct {
157fa14d
CK		 1899 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1900 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
0f9e006c 1901 } pflip;
771fe6b9
JG		 1902};
1903
21f9a437
JG		 1904/*
1905 * Asic structures
1906 */
551ebd83 1907struct r100_asic {
225758d8
JG		 1908 const unsigned *reg_safe_bm;
1909 unsigned reg_safe_bm_size;
1910 u32 hdp_cntl;
551ebd83
DA		 1911};
1912
21f9a437 1913struct r300_asic {
225758d8
JG		 1914 const unsigned *reg_safe_bm;
1915 unsigned reg_safe_bm_size;
1916 u32 resync_scratch;
1917 u32 hdp_cntl;
21f9a437
JG		 1918};
1919
1920struct r600_asic {
225758d8
JG		 1921 unsigned max_pipes;
1922 unsigned max_tile_pipes;
1923 unsigned max_simds;
1924 unsigned max_backends;
1925 unsigned max_gprs;
1926 unsigned max_threads;
1927 unsigned max_stack_entries;
1928 unsigned max_hw_contexts;
1929 unsigned max_gs_threads;
1930 unsigned sx_max_export_size;
1931 unsigned sx_max_export_pos_size;
1932 unsigned sx_max_export_smx_size;
1933 unsigned sq_num_cf_insts;
1934 unsigned tiling_nbanks;
1935 unsigned tiling_npipes;
1936 unsigned tiling_group_size;
e7aeeba6 1937 unsigned tile_config;
e55b9422 1938 unsigned backend_map;
21f9a437
JG		 1939};
1940
1941struct rv770_asic {
225758d8
JG		 1942 unsigned max_pipes;
1943 unsigned max_tile_pipes;
1944 unsigned max_simds;
1945 unsigned max_backends;
1946 unsigned max_gprs;
1947 unsigned max_threads;
1948 unsigned max_stack_entries;
1949 unsigned max_hw_contexts;
1950 unsigned max_gs_threads;
1951 unsigned sx_max_export_size;
1952 unsigned sx_max_export_pos_size;
1953 unsigned sx_max_export_smx_size;
1954 unsigned sq_num_cf_insts;
1955 unsigned sx_num_of_sets;
1956 unsigned sc_prim_fifo_size;
1957 unsigned sc_hiz_tile_fifo_size;
1958 unsigned sc_earlyz_tile_fifo_fize;
1959 unsigned tiling_nbanks;
1960 unsigned tiling_npipes;
1961 unsigned tiling_group_size;
e7aeeba6 1962 unsigned tile_config;
e55b9422 1963 unsigned backend_map;
21f9a437
JG		 1964};
1965
32fcdbf4
AD		 1966struct evergreen_asic {
1967 unsigned num_ses;
1968 unsigned max_pipes;
1969 unsigned max_tile_pipes;
1970 unsigned max_simds;
1971 unsigned max_backends;
1972 unsigned max_gprs;
1973 unsigned max_threads;
1974 unsigned max_stack_entries;
1975 unsigned max_hw_contexts;
1976 unsigned max_gs_threads;
1977 unsigned sx_max_export_size;
1978 unsigned sx_max_export_pos_size;
1979 unsigned sx_max_export_smx_size;
1980 unsigned sq_num_cf_insts;
1981 unsigned sx_num_of_sets;
1982 unsigned sc_prim_fifo_size;
1983 unsigned sc_hiz_tile_fifo_size;
1984 unsigned sc_earlyz_tile_fifo_size;
1985 unsigned tiling_nbanks;
1986 unsigned tiling_npipes;
1987 unsigned tiling_group_size;
e7aeeba6 1988 unsigned tile_config;
e55b9422 1989 unsigned backend_map;
32fcdbf4
AD		 1990};
1991
fecf1d07
AD		 1992struct cayman_asic {
1993 unsigned max_shader_engines;
1994 unsigned max_pipes_per_simd;
1995 unsigned max_tile_pipes;
1996 unsigned max_simds_per_se;
1997 unsigned max_backends_per_se;
1998 unsigned max_texture_channel_caches;
1999 unsigned max_gprs;
2000 unsigned max_threads;
2001 unsigned max_gs_threads;
2002 unsigned max_stack_entries;
2003 unsigned sx_num_of_sets;
2004 unsigned sx_max_export_size;
2005 unsigned sx_max_export_pos_size;
2006 unsigned sx_max_export_smx_size;
2007 unsigned max_hw_contexts;
2008 unsigned sq_num_cf_insts;
2009 unsigned sc_prim_fifo_size;
2010 unsigned sc_hiz_tile_fifo_size;
2011 unsigned sc_earlyz_tile_fifo_size;
2012
2013 unsigned num_shader_engines;
2014 unsigned num_shader_pipes_per_simd;
2015 unsigned num_tile_pipes;
2016 unsigned num_simds_per_se;
2017 unsigned num_backends_per_se;
2018 unsigned backend_disable_mask_per_asic;
2019 unsigned backend_map;
2020 unsigned num_texture_channel_caches;
2021 unsigned mem_max_burst_length_bytes;
2022 unsigned mem_row_size_in_kb;
2023 unsigned shader_engine_tile_size;
2024 unsigned num_gpus;
2025 unsigned multi_gpu_tile_size;
2026
2027 unsigned tile_config;
fecf1d07
AD		 2028};
2029
0a96d72b
AD		 2030struct si_asic {
2031 unsigned max_shader_engines;
0a96d72b 2032 unsigned max_tile_pipes;
1a8ca750
AD		 2033 unsigned max_cu_per_sh;
2034 unsigned max_sh_per_se;
0a96d72b
AD		 2035 unsigned max_backends_per_se;
2036 unsigned max_texture_channel_caches;
2037 unsigned max_gprs;
2038 unsigned max_gs_threads;
2039 unsigned max_hw_contexts;
2040 unsigned sc_prim_fifo_size_frontend;
2041 unsigned sc_prim_fifo_size_backend;
2042 unsigned sc_hiz_tile_fifo_size;
2043 unsigned sc_earlyz_tile_fifo_size;
2044
0a96d72b 2045 unsigned num_tile_pipes;
439a1cff 2046 unsigned backend_enable_mask;
0a96d72b
AD		 2047 unsigned backend_disable_mask_per_asic;
2048 unsigned backend_map;
2049 unsigned num_texture_channel_caches;
2050 unsigned mem_max_burst_length_bytes;
2051 unsigned mem_row_size_in_kb;
2052 unsigned shader_engine_tile_size;
2053 unsigned num_gpus;
2054 unsigned multi_gpu_tile_size;
2055
2056 unsigned tile_config;
64d7b8be 2057 uint32_t tile_mode_array[32];
0a96d72b
AD		 2058};
2059
8cc1a532
AD		 2060struct cik_asic {
2061 unsigned max_shader_engines;
2062 unsigned max_tile_pipes;
2063 unsigned max_cu_per_sh;
2064 unsigned max_sh_per_se;
2065 unsigned max_backends_per_se;
2066 unsigned max_texture_channel_caches;
2067 unsigned max_gprs;
2068 unsigned max_gs_threads;
2069 unsigned max_hw_contexts;
2070 unsigned sc_prim_fifo_size_frontend;
2071 unsigned sc_prim_fifo_size_backend;
2072 unsigned sc_hiz_tile_fifo_size;
2073 unsigned sc_earlyz_tile_fifo_size;
2074
2075 unsigned num_tile_pipes;
439a1cff 2076 unsigned backend_enable_mask;
8cc1a532
AD		 2077 unsigned backend_disable_mask_per_asic;
2078 unsigned backend_map;
2079 unsigned num_texture_channel_caches;
2080 unsigned mem_max_burst_length_bytes;
2081 unsigned mem_row_size_in_kb;
2082 unsigned shader_engine_tile_size;
2083 unsigned num_gpus;
2084 unsigned multi_gpu_tile_size;
2085
2086 unsigned tile_config;
39aee490 2087 uint32_t tile_mode_array[32];
32f79a8a 2088 uint32_t macrotile_mode_array[16];
8cc1a532
AD		 2089};
2090
068a117c
JG		 2091union radeon_asic_config {
2092 struct r300_asic r300;
551ebd83 2093 struct r100_asic r100;
3ce0a23d
JG		 2094 struct r600_asic r600;
2095 struct rv770_asic rv770;
32fcdbf4 2096 struct evergreen_asic evergreen;
fecf1d07 2097 struct cayman_asic cayman;
0a96d72b 2098 struct si_asic si;
8cc1a532 2099 struct cik_asic cik;
068a117c
JG		 2100};
2101
0a10c851
DV		 2102/*
2103 * asic initizalization from radeon_asic.c
2104 */
2105void radeon_agp_disable(struct radeon_device *rdev);
2106int radeon_asic_init(struct radeon_device *rdev);
2107
771fe6b9
JG		 2108
2109/*
2110 * IOCTL.
2111 */
2112int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2113 struct drm_file *filp);
2114int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2115 struct drm_file *filp);
2116int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2117 struct drm_file *file_priv);
2118int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2119 struct drm_file *file_priv);
2120int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2121 struct drm_file *file_priv);
2122int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2123 struct drm_file *file_priv);
2124int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2125 struct drm_file *filp);
2126int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2127 struct drm_file *filp);
2128int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2129 struct drm_file *filp);
2130int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2131 struct drm_file *filp);
721604a1
JG		 2132int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2133 struct drm_file *filp);
bda72d58
MO		 2134int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2135 struct drm_file *filp);
771fe6b9 2136int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 2137int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2138 struct drm_file *filp);
2139int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2140 struct drm_file *filp);
771fe6b9 2141
16cdf04d
AD		 2142/* VRAM scratch page for HDP bug, default vram page */
2143struct r600_vram_scratch {
87cbf8f2
AD		 2144 struct radeon_bo *robj;
2145 volatile uint32_t *ptr;
16cdf04d 2146 u64 gpu_addr;
87cbf8f2 2147};
771fe6b9 2148
fd64ca8a
LT		 2149/*
2150 * ACPI
2151 */
2152struct radeon_atif_notification_cfg {
2153 bool enabled;
2154 int command_code;
2155};
2156
2157struct radeon_atif_notifications {
2158 bool display_switch;
2159 bool expansion_mode_change;
2160 bool thermal_state;
2161 bool forced_power_state;
2162 bool system_power_state;
2163 bool display_conf_change;
2164 bool px_gfx_switch;
2165 bool brightness_change;
2166 bool dgpu_display_event;
2167};
2168
2169struct radeon_atif_functions {
2170 bool system_params;
2171 bool sbios_requests;
2172 bool select_active_disp;
2173 bool lid_state;
2174 bool get_tv_standard;
2175 bool set_tv_standard;
2176 bool get_panel_expansion_mode;
2177 bool set_panel_expansion_mode;
2178 bool temperature_change;
2179 bool graphics_device_types;
2180};
2181
2182struct radeon_atif {
2183 struct radeon_atif_notifications notifications;
2184 struct radeon_atif_functions functions;
2185 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2186 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2187};
7a1619b9 2188
e3a15920
AD		 2189struct radeon_atcs_functions {
2190 bool get_ext_state;
2191 bool pcie_perf_req;
2192 bool pcie_dev_rdy;
2193 bool pcie_bus_width;
2194};
2195
2196struct radeon_atcs {
2197 struct radeon_atcs_functions functions;
2198};
2199
771fe6b9
JG		 2200/*
2201 * Core structure, functions and helpers.
2202 */
2203typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2204typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2205
2206struct radeon_device {
9f022ddf 2207 struct device *dev;
771fe6b9
JG		 2208 struct drm_device *ddev;
2209 struct pci_dev *pdev;
dee53e7f 2210 struct rw_semaphore exclusive_lock;
771fe6b9 2211 /* ASIC */
068a117c 2212 union radeon_asic_config config;
771fe6b9
JG		 2213 enum radeon_family family;
2214 unsigned long flags;
2215 int usec_timeout;
2216 enum radeon_pll_errata pll_errata;
2217 int num_gb_pipes;
f779b3e5 2218 int num_z_pipes;
771fe6b9
JG		 2219 int disp_priority;
2220 /* BIOS */
2221 uint8_t *bios;
2222 bool is_atom_bios;
2223 uint16_t bios_header_start;
4c788679 2224 struct radeon_bo *stollen_vga_memory;
771fe6b9 2225 /* Register mmio */
4c9bc75c
DA		 2226 resource_size_t rmmio_base;
2227 resource_size_t rmmio_size;
2c385151
DV		 2228 /* protects concurrent MM_INDEX/DATA based register access */
2229 spinlock_t mmio_idx_lock;
fe78118c
AD		 2230 /* protects concurrent SMC based register access */
2231 spinlock_t smc_idx_lock;
0a5b7b0b
AD		 2232 /* protects concurrent PLL register access */
2233 spinlock_t pll_idx_lock;
2234 /* protects concurrent MC register access */
2235 spinlock_t mc_idx_lock;
2236 /* protects concurrent PCIE register access */
2237 spinlock_t pcie_idx_lock;
2238 /* protects concurrent PCIE_PORT register access */
2239 spinlock_t pciep_idx_lock;
2240 /* protects concurrent PIF register access */
2241 spinlock_t pif_idx_lock;
2242 /* protects concurrent CG register access */
2243 spinlock_t cg_idx_lock;
2244 /* protects concurrent UVD register access */
2245 spinlock_t uvd_idx_lock;
2246 /* protects concurrent RCU register access */
2247 spinlock_t rcu_idx_lock;
2248 /* protects concurrent DIDT register access */
2249 spinlock_t didt_idx_lock;
2250 /* protects concurrent ENDPOINT (audio) register access */
2251 spinlock_t end_idx_lock;
a0533fbf 2252 void __iomem *rmmio;
771fe6b9
JG		 2253 radeon_rreg_t mc_rreg;
2254 radeon_wreg_t mc_wreg;
2255 radeon_rreg_t pll_rreg;
2256 radeon_wreg_t pll_wreg;
de1b2898 2257 uint32_t pcie_reg_mask;
771fe6b9
JG		 2258 radeon_rreg_t pciep_rreg;
2259 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2260 /* io port */
2261 void __iomem *rio_mem;
2262 resource_size_t rio_mem_size;
771fe6b9
JG		 2263 struct radeon_clock clock;
2264 struct radeon_mc mc;
2265 struct radeon_gart gart;
2266 struct radeon_mode_info mode_info;
2267 struct radeon_scratch scratch;
75efdee1 2268 struct radeon_doorbell doorbell;
771fe6b9 2269 struct radeon_mman mman;
7465280c 2270 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2271 wait_queue_head_t fence_queue;
d6999bc7 2272 struct mutex ring_lock;
e32eb50d 2273 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2274 bool ib_pool_ready;
2275 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2276 struct radeon_irq irq;
2277 struct radeon_asic *asic;
2278 struct radeon_gem gem;
c93bb85b 2279 struct radeon_pm pm;
f2ba57b5 2280 struct radeon_uvd uvd;
d93f7937 2281 struct radeon_vce vce;
f657c2a7 2282 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2283 struct radeon_wb wb;
3ce0a23d 2284 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2285 bool shutdown;
2286 bool suspend;
ad49f501 2287 bool need_dma32;
733289c2 2288 bool accel_working;
a0a53aa8 2289 bool fastfb_working; /* IGP feature*/
f9eaf9ae 2290 bool needs_reset;
e024e110 2291 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2292 const struct firmware *me_fw; /* all family ME firmware */
2293 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2294 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2295 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2296 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2297 const struct firmware *mec_fw; /* CIK MEC firmware */
21a93e13 2298 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2299 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2300 const struct firmware *uvd_fw; /* UVD firmware */
d93f7937 2301 const struct firmware *vce_fw; /* VCE firmware */
16cdf04d 2302 struct r600_vram_scratch vram_scratch;
3e5cb98d 2303 int msi_enabled; /* msi enabled */
d8f60cfc 2304 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2305 struct radeon_rlc rlc;
963e81f9 2306 struct radeon_mec mec;
d4877cf2 2307 struct work_struct hotplug_work;
f122c610 2308 struct work_struct audio_work;
8f61b34c 2309 struct work_struct reset_work;
18917b60 2310 int num_crtc; /* number of crtcs */
40bacf16 2311 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
948bee3f 2312 bool has_uvd;
b530602f 2313 struct r600_audio audio; /* audio stuff */
ce8f5370 2314 struct notifier_block acpi_nb;
9eba4a93 2315 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2316 struct drm_file *hyperz_filp;
9eba4a93 2317 struct drm_file *cmask_filp;
f376b94f
AD		 2318 /* i2c buses */
2319 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2320 /* debugfs */
2321 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2322 unsigned debugfs_count;
721604a1
JG		 2323 /* virtual memory */
2324 struct radeon_vm_manager vm_manager;
6759a0a7 2325 struct mutex gpu_clock_mutex;
67e8e3f9
MO		 2326 /* memory stats */
2327 atomic64_t vram_usage;
2328 atomic64_t gtt_usage;
2329 atomic64_t num_bytes_moved;
fd64ca8a
LT		 2330 /* ACPI interface */
2331 struct radeon_atif atif;
e3a15920 2332 struct radeon_atcs atcs;
f61d5b46
AD		 2333 /* srbm instance registers */
2334 struct mutex srbm_mutex;
64d8a728
AD		 2335 /* clock, powergating flags */
2336 u32 cg_flags;
2337 u32 pg_flags;
10ebc0bc
DA		 2338
2339 struct dev_pm_domain vga_pm_domain;
2340 bool have_disp_power_ref;
771fe6b9
JG		 2341};
2342
90c4cde9 2343bool radeon_is_px(struct drm_device *dev);
771fe6b9
JG		 2344int radeon_device_init(struct radeon_device *rdev,
2345 struct drm_device *ddev,
2346 struct pci_dev *pdev,
2347 uint32_t flags);
2348void radeon_device_fini(struct radeon_device *rdev);
2349int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2350
2ef9bdfe
DV		 2351uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2352 bool always_indirect);
2353void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2354 bool always_indirect);
6fcbef7a
AK		 2355u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2356void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2357
d5754ab8
AL		 2358u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2359void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
75efdee1 2360
4c788679
JG		 2361/*
2362 * Cast helper
2363 */
2364#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 2365
2366/*
2367 * Registers read & write functions.
2368 */
a0533fbf
BH		 2369#define RREG8(reg) readb((rdev->rmmio) + (reg))
2370#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2371#define RREG16(reg) readw((rdev->rmmio) + (reg))
2372#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2373#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2374#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2375#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2376#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2377#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2378#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2379#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2380#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2381#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2382#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2383#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2384#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2385#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2386#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2387#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2388#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2389#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2390#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2391#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2392#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2393#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2394#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2395#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2396#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2397#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2398#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2399#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2400#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2401#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2402#define WREG32_P(reg, val, mask) \
2403 do { \
2404 uint32_t tmp_ = RREG32(reg); \
2405 tmp_ &= (mask); \
2406 tmp_ |= ((val) & ~(mask)); \
2407 WREG32(reg, tmp_); \
2408 } while (0)
d5169fc4 2409#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2410#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2411#define WREG32_PLL_P(reg, val, mask) \
2412 do { \
2413 uint32_t tmp_ = RREG32_PLL(reg); \
2414 tmp_ &= (mask); \
2415 tmp_ |= ((val) & ~(mask)); \
2416 WREG32_PLL(reg, tmp_); \
2417 } while (0)
2ef9bdfe 2418#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2419#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2420#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2421
d5754ab8
AL		 2422#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2423#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
75efdee1 2424
de1b2898
DA		 2425/*
2426 * Indirect registers accessor
2427 */
2428static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2429{
0a5b7b0b 2430 unsigned long flags;
de1b2898
DA		 2431 uint32_t r;
2432
0a5b7b0b 2433 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2434 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2435 r = RREG32(RADEON_PCIE_DATA);
0a5b7b0b 2436 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2437 return r;
2438}
2439
2440static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2441{
0a5b7b0b
AD		 2442 unsigned long flags;
2443
2444 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2445 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2446 WREG32(RADEON_PCIE_DATA, (v));
0a5b7b0b 2447 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2448}
2449
1d5d0c34
AD		 2450static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2451{
fe78118c 2452 unsigned long flags;
1d5d0c34
AD		 2453 u32 r;
2454
fe78118c 2455 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2456 WREG32(TN_SMC_IND_INDEX_0, (reg));
2457 r = RREG32(TN_SMC_IND_DATA_0);
fe78118c 2458 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2459 return r;
2460}
2461
2462static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2463{
fe78118c
AD		 2464 unsigned long flags;
2465
2466 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2467 WREG32(TN_SMC_IND_INDEX_0, (reg));
2468 WREG32(TN_SMC_IND_DATA_0, (v));
fe78118c 2469 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2470}
2471
ff82bbc4
AD		 2472static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2473{
0a5b7b0b 2474 unsigned long flags;
ff82bbc4
AD		 2475 u32 r;
2476
0a5b7b0b 2477 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2478 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2479 r = RREG32(R600_RCU_DATA);
0a5b7b0b 2480 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2481 return r;
2482}
2483
2484static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2485{
0a5b7b0b
AD		 2486 unsigned long flags;
2487
2488 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2489 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2490 WREG32(R600_RCU_DATA, (v));
0a5b7b0b 2491 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2492}
2493
46f9564a
AD		 2494static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2495{
0a5b7b0b 2496 unsigned long flags;
46f9564a
AD		 2497 u32 r;
2498
0a5b7b0b 2499 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2500 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2501 r = RREG32(EVERGREEN_CG_IND_DATA);
0a5b7b0b 2502 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2503 return r;
2504}
2505
2506static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2507{
0a5b7b0b
AD		 2508 unsigned long flags;
2509
2510 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2511 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2512 WREG32(EVERGREEN_CG_IND_DATA, (v));
0a5b7b0b 2513 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2514}
2515
792edd69
AD		 2516static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2517{
0a5b7b0b 2518 unsigned long flags;
792edd69
AD		 2519 u32 r;
2520
0a5b7b0b 2521 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2522 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2523 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
0a5b7b0b 2524 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2525 return r;
2526}
2527
2528static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2529{
0a5b7b0b
AD		 2530 unsigned long flags;
2531
2532 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2533 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2534 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
0a5b7b0b 2535 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2536}
2537
2538static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2539{
0a5b7b0b 2540 unsigned long flags;
792edd69
AD		 2541 u32 r;
2542
0a5b7b0b 2543 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2544 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2545 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
0a5b7b0b 2546 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2547 return r;
2548}
2549
2550static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2551{
0a5b7b0b
AD		 2552 unsigned long flags;
2553
2554 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2555 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2556 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
0a5b7b0b 2557 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2558}
2559
93656cdd
AD		 2560static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2561{
0a5b7b0b 2562 unsigned long flags;
93656cdd
AD		 2563 u32 r;
2564
0a5b7b0b 2565 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2566 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2567 r = RREG32(R600_UVD_CTX_DATA);
0a5b7b0b 2568 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2569 return r;
2570}
2571
2572static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2573{
0a5b7b0b
AD		 2574 unsigned long flags;
2575
2576 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2577 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2578 WREG32(R600_UVD_CTX_DATA, (v));
0a5b7b0b 2579 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2580}
2581
1d58234d
AD		 2582
2583static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2584{
0a5b7b0b 2585 unsigned long flags;
1d58234d
AD		 2586 u32 r;
2587
0a5b7b0b 2588 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2589 WREG32(CIK_DIDT_IND_INDEX, (reg));
2590 r = RREG32(CIK_DIDT_IND_DATA);
0a5b7b0b 2591 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2592 return r;
2593}
2594
2595static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2596{
0a5b7b0b
AD		 2597 unsigned long flags;
2598
2599 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2600 WREG32(CIK_DIDT_IND_INDEX, (reg));
2601 WREG32(CIK_DIDT_IND_DATA, (v));
0a5b7b0b 2602 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2603}
2604
771fe6b9
JG		 2605void r100_pll_errata_after_index(struct radeon_device *rdev);
2606
2607
2608/*
2609 * ASICs helpers.
2610 */
b995e433
DA		 2611#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2612 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2613#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2614 (rdev->family == CHIP_RV200) || \
2615 (rdev->family == CHIP_RS100) || \
2616 (rdev->family == CHIP_RS200) || \
2617 (rdev->family == CHIP_RV250) || \
2618 (rdev->family == CHIP_RV280) || \
2619 (rdev->family == CHIP_RS300))
2620#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2621 (rdev->family == CHIP_RV350) || \
2622 (rdev->family == CHIP_R350) || \
2623 (rdev->family == CHIP_RV380) || \
2624 (rdev->family == CHIP_R420) || \
2625 (rdev->family == CHIP_R423) || \
2626 (rdev->family == CHIP_RV410) || \
2627 (rdev->family == CHIP_RS400) || \
2628 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2629#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2630 (rdev->ddev->pdev->device == 0x9443) || \
2631 (rdev->ddev->pdev->device == 0x944B) || \
2632 (rdev->ddev->pdev->device == 0x9506) || \
2633 (rdev->ddev->pdev->device == 0x9509) || \
2634 (rdev->ddev->pdev->device == 0x950F) || \
2635 (rdev->ddev->pdev->device == 0x689C) || \
2636 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2637#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2638#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2639 (rdev->family == CHIP_RS690) || \
2640 (rdev->family == CHIP_RS740) || \
2641 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2642#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2643#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2644#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2645#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2646 (rdev->flags & RADEON_IS_IGP))
1fe18305 2647#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2648#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2649#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2650 (rdev->flags & RADEON_IS_IGP))
624d3524 2651#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2652#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2653#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
be0949f5
AD		 2654#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2655#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
89d2618d
AD		 2656#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2657 (rdev->family == CHIP_MULLINS))
771fe6b9 2658
dc50ba7f
AD		 2659#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2660 (rdev->ddev->pdev->device == 0x6850) || \
2661 (rdev->ddev->pdev->device == 0x6858) || \
2662 (rdev->ddev->pdev->device == 0x6859) || \
2663 (rdev->ddev->pdev->device == 0x6840) || \
2664 (rdev->ddev->pdev->device == 0x6841) || \
2665 (rdev->ddev->pdev->device == 0x6842) || \
2666 (rdev->ddev->pdev->device == 0x6843))
2667
771fe6b9
JG		 2668/*
2669 * BIOS helpers.
2670 */
2671#define RBIOS8(i) (rdev->bios[i])
2672#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2673#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2674
2675int radeon_combios_init(struct radeon_device *rdev);
2676void radeon_combios_fini(struct radeon_device *rdev);
2677int radeon_atombios_init(struct radeon_device *rdev);
2678void radeon_atombios_fini(struct radeon_device *rdev);
2679
2680
2681/*
2682 * RING helpers.
2683 */
ce580fab 2684#if DRM_DEBUG_CODE == 0
e32eb50d 2685static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2686{
e32eb50d
CK		 2687 ring->ring[ring->wptr++] = v;
2688 ring->wptr &= ring->ptr_mask;
2689 ring->count_dw--;
2690 ring->ring_free_dw--;
771fe6b9 2691}
ce580fab
AK		 2692#else
2693/* With debugging this is just too big to inline */
e32eb50d 2694void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
ce580fab 2695#endif
771fe6b9
JG		 2696
2697/*
2698 * ASICs macro.
2699 */
068a117c 2700#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2701#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2702#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2703#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2704#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2705#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2706#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850
AD		 2707#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2708#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
05b07147
CK		 2709#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2710#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
43f1214a 2711#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
76a0df85
CK		 2712#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2713#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2714#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2715#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2716#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2717#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2718#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2719#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2720#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2721#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2722#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2723#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2724#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2725#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2726#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2727#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2728#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2729#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2730#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
27cd7769
AD		 2731#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2732#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2733#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2734#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2735#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2736#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2737#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2738#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2739#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2740#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2741#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2742#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2743#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2744#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
b59b7333 2745#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
6bd1c385 2746#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2747#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2748#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2749#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2750#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2751#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2752#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2753#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2754#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2755#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2756#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2757#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2758#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2759#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8 2760#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
157fa14d 2761#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
69b62ad8
AD		 2762#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2763#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2764#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2765#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2766#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2767#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2768#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
914a8987 2769#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
da321c8a 2770#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2771#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2772#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2773#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2774#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2775#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2776#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2777#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2778#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2779#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2780#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2781#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2782#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
1c71bda0 2783#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
771fe6b9 2784
6cf8a3f5 2785/* Common functions */
700a0cc0 2786/* AGP */
90aca4d2 2787extern int radeon_gpu_reset(struct radeon_device *rdev);
1a0041b8 2788extern void radeon_pci_config_reset(struct radeon_device *rdev);
410a3418 2789extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2790extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2791extern int radeon_modeset_init(struct radeon_device *rdev);
2792extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2793extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2794extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2795extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2796extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2797extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2798extern void radeon_wb_fini(struct radeon_device *rdev);
2799extern int radeon_wb_init(struct radeon_device *rdev);
2800extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2801extern void radeon_surface_init(struct radeon_device *rdev);
2802extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2803extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2804extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2805extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2806extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 2807extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2808extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
10ebc0bc
DA		 2809extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2810extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
53595338 2811extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2812extern void radeon_program_register_sequence(struct radeon_device *rdev,
2813 const u32 *registers,
2814 const u32 array_size);
6cf8a3f5 2815
721604a1
JG		 2816/*
2817 * vm
2818 */
2819int radeon_vm_manager_init(struct radeon_device *rdev);
2820void radeon_vm_manager_fini(struct radeon_device *rdev);
6d2f2944 2821int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2822void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
df0af440
CK		 2823struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2824 struct radeon_vm *vm,
2825 struct list_head *head);
ee60e29f
CK		 2826struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2827 struct radeon_vm *vm, int ring);
fa688343
CK		 2828void radeon_vm_flush(struct radeon_device *rdev,
2829 struct radeon_vm *vm,
2830 int ring);
ee60e29f
CK		 2831void radeon_vm_fence(struct radeon_device *rdev,
2832 struct radeon_vm *vm,
2833 struct radeon_fence *fence);
dce34bfd 2834uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
6d2f2944
CK		 2835int radeon_vm_update_page_directory(struct radeon_device *rdev,
2836 struct radeon_vm *vm);
9c57a6bd
CK		 2837int radeon_vm_bo_update(struct radeon_device *rdev,
2838 struct radeon_vm *vm,
2839 struct radeon_bo *bo,
2840 struct ttm_mem_reg *mem);
721604a1
JG		 2841void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2842 struct radeon_bo *bo);
421ca7ab
CK		 2843struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2844 struct radeon_bo *bo);
e971bd5e
CK		 2845struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2846 struct radeon_vm *vm,
2847 struct radeon_bo *bo);
2848int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2849 struct radeon_bo_va *bo_va,
2850 uint64_t offset,
2851 uint32_t flags);
721604a1 2852int radeon_vm_bo_rmv(struct radeon_device *rdev,
e971bd5e 2853 struct radeon_bo_va *bo_va);
721604a1 2854
f122c610
AD		 2855/* audio */
2856void r600_audio_update_hdmi(struct work_struct *work);
b530602f
AD		 2857struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2858struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
832eafaf
AD		 2859void r600_audio_enable(struct radeon_device *rdev,
2860 struct r600_audio_pin *pin,
2861 bool enable);
2862void dce6_audio_enable(struct radeon_device *rdev,
2863 struct r600_audio_pin *pin,
2864 bool enable);
721604a1 2865
16cdf04d
AD		 2866/*
2867 * R600 vram scratch functions
2868 */
2869int r600_vram_scratch_init(struct radeon_device *rdev);
2870void r600_vram_scratch_fini(struct radeon_device *rdev);
2871
285484e2
JG		 2872/*
2873 * r600 cs checking helper
2874 */
2875unsigned r600_mip_minify(unsigned size, unsigned level);
2876bool r600_fmt_is_valid_color(u32 format);
2877bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2878int r600_fmt_get_blocksize(u32 format);
2879int r600_fmt_get_nblocksx(u32 format, u32 w);
2880int r600_fmt_get_nblocksy(u32 format, u32 h);
2881
3574dda4
DV		 2882/*
2883 * r600 functions used by radeon_encoder.c
2884 */
1b688d08
RM		 2885struct radeon_hdmi_acr {
2886 u32 clock;
2887
2888 int n_32khz;
2889 int cts_32khz;
2890
2891 int n_44_1khz;
2892 int cts_44_1khz;
2893
2894 int n_48khz;
2895 int cts_48khz;
2896
2897};
2898
e55d3e6c
RM		 2899extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2900
416a2bd2
AD		 2901extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2902 u32 tiling_pipe_num,
2903 u32 max_rb_num,
2904 u32 total_max_rb_num,
2905 u32 enabled_rb_mask);
fe251e2f 2906
e55d3e6c
RM		 2907/*
2908 * evergreen functions used by radeon_encoder.c
2909 */
2910
0af62b01 2911extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2912extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2913
c4917074
AD		 2914/* radeon_acpi.c */
2915#if defined(CONFIG_ACPI)
2916extern int radeon_acpi_init(struct radeon_device *rdev);
2917extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2918extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2919extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2920 u8 perf_req, bool advertise);
dc50ba7f 2921extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2922#else
2923static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2924static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2925#endif
d7a2952f 2926
c38f34b5
IH		 2927int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2928 struct radeon_cs_packet *pkt,
2929 unsigned idx);
9ffb7a6d 2930bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2931void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2932 struct radeon_cs_packet *pkt);
e9716993
IH		 2933int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2934 struct radeon_cs_reloc **cs_reloc,
2935 int nomm);
40592a17
IH		 2936int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2937 uint32_t *vline_start_end,
2938 uint32_t *vline_status);
c38f34b5 2939
4c788679
JG		 2940#include "radeon_object.h"
2941
771fe6b9 2942#endif
Linux kernel - Deliverables
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