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Merge tag 'staging-4.5-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh...
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
0aea5e4a 67#include <linux/interval_tree.h>
341cb9e4 68#include <linux/hashtable.h>
954605ca 69#include <linux/fence.h>
771fe6b9 70
4c788679
JG		 71#include <ttm/ttm_bo_api.h>
72#include <ttm/ttm_bo_driver.h>
73#include <ttm/ttm_placement.h>
74#include <ttm/ttm_module.h>
147666fb 75#include <ttm/ttm_execbuf_util.h>
4c788679 76
d9fc9413
DV		 77#include <drm/drm_gem.h>
78
c2142715 79#include "radeon_family.h"
771fe6b9
JG		 80#include "radeon_mode.h"
81#include "radeon_reg.h"
771fe6b9
JG		 82
83/*
84 * Modules parameters.
85 */
86extern int radeon_no_wb;
87extern int radeon_modeset;
88extern int radeon_dynclks;
89extern int radeon_r4xx_atom;
90extern int radeon_agpmode;
91extern int radeon_vram_limit;
92extern int radeon_gart_size;
93extern int radeon_benchmarking;
ecc0b326 94extern int radeon_testing;
771fe6b9 95extern int radeon_connector_table;
4ce001ab 96extern int radeon_tv;
dafc3bd5 97extern int radeon_audio;
f46c0120 98extern int radeon_disp_priority;
e2b0a8e1 99extern int radeon_hw_i2c;
d42dd579 100extern int radeon_pcie_gen2;
a18cee15 101extern int radeon_msi;
3368ff0c 102extern int radeon_lockup_timeout;
a0a53aa8 103extern int radeon_fastfb;
da321c8a 104extern int radeon_dpm;
1294d4a3 105extern int radeon_aspm;
10ebc0bc 106extern int radeon_runtime_pm;
363eb0b4 107extern int radeon_hard_reset;
c1c44132 108extern int radeon_vm_size;
4510fb98 109extern int radeon_vm_block_size;
a624f429 110extern int radeon_deep_color;
39dc5454 111extern int radeon_use_pflipirq;
6e909f74 112extern int radeon_bapm;
bc13018b 113extern int radeon_backlight;
875711f0 114extern int radeon_auxch;
9843ead0 115extern int radeon_mst;
771fe6b9
JG		 116
117/*
118 * Copy from radeon_drv.h so we don't have to include both and have conflicting
119 * symbol;
120 */
bb635567
JG		 121#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
122#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 123/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 124#define RADEON_IB_POOL_SIZE 16
125#define RADEON_DEBUGFS_MAX_COMPONENTS 32
126#define RADEONFB_CONN_LIMIT 4
127#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 128
1b37078b
AD		 129/* internal ring indices */
130/* r1xx+ has gfx CP ring */
d93f7937 131#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 132
133/* cayman has 2 compute CP rings */
d93f7937
CK		 134#define CAYMAN_RING_TYPE_CP1_INDEX 1
135#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 136
4d75658b
AD		 137/* R600+ has an async dma ring */
138#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 139/* cayman add a second async dma ring */
140#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 141
f2ba57b5 142/* R600+ */
d93f7937
CK		 143#define R600_RING_TYPE_UVD_INDEX 5
144
145/* TN+ */
146#define TN_RING_TYPE_VCE1_INDEX 6
147#define TN_RING_TYPE_VCE2_INDEX 7
148
149/* max number of rings */
150#define RADEON_NUM_RINGS 8
f2ba57b5 151
1c61eae4
CK		 152/* number of hw syncs before falling back on blocking */
153#define RADEON_NUM_SYNCS 4
f2ba57b5 154
721604a1 155/* hardcode those limit for now */
ca19f21e 156#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 157#define RADEON_VA_RESERVED_SIZE (8 << 20)
158#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 159
1a0041b8
AD		 160/* hard reset data */
161#define RADEON_ASIC_RESET_DATA 0x39d5e86b
162
ec46c76d
AD		 163/* reset flags */
164#define RADEON_RESET_GFX (1 << 0)
165#define RADEON_RESET_COMPUTE (1 << 1)
166#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 167#define RADEON_RESET_CP (1 << 3)
168#define RADEON_RESET_GRBM (1 << 4)
169#define RADEON_RESET_DMA1 (1 << 5)
170#define RADEON_RESET_RLC (1 << 6)
171#define RADEON_RESET_SEM (1 << 7)
172#define RADEON_RESET_IH (1 << 8)
173#define RADEON_RESET_VMC (1 << 9)
174#define RADEON_RESET_MC (1 << 10)
175#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 176
22c775ce
AD		 177/* CG block flags */
178#define RADEON_CG_BLOCK_GFX (1 << 0)
179#define RADEON_CG_BLOCK_MC (1 << 1)
180#define RADEON_CG_BLOCK_SDMA (1 << 2)
181#define RADEON_CG_BLOCK_UVD (1 << 3)
182#define RADEON_CG_BLOCK_VCE (1 << 4)
183#define RADEON_CG_BLOCK_HDP (1 << 5)
e16866ec 184#define RADEON_CG_BLOCK_BIF (1 << 6)
22c775ce 185
64d8a728
AD		 186/* CG flags */
187#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
188#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
189#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
190#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
191#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
192#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
193#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
194#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
195#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
196#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
197#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
198#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
199#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
200#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
201#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
202#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
203#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
204
205/* PG flags */
2b19d17f 206#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
64d8a728
AD		 207#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
208#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
209#define RADEON_PG_SUPPORT_UVD (1 << 3)
210#define RADEON_PG_SUPPORT_VCE (1 << 4)
211#define RADEON_PG_SUPPORT_CP (1 << 5)
212#define RADEON_PG_SUPPORT_GDS (1 << 6)
213#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
214#define RADEON_PG_SUPPORT_SDMA (1 << 8)
215#define RADEON_PG_SUPPORT_ACP (1 << 9)
216#define RADEON_PG_SUPPORT_SAMU (1 << 10)
217
9e05fa1d
AD		 218/* max cursor sizes (in pixels) */
219#define CURSOR_WIDTH 64
220#define CURSOR_HEIGHT 64
221
222#define CIK_CURSOR_WIDTH 128
223#define CIK_CURSOR_HEIGHT 128
224
771fe6b9
JG		 225/*
226 * Errata workarounds.
227 */
228enum radeon_pll_errata {
229 CHIP_ERRATA_R300_CG = 0x00000001,
230 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
231 CHIP_ERRATA_PLL_DELAY = 0x00000004
232};
233
234
235struct radeon_device;
236
237
238/*
239 * BIOS.
240 */
241bool radeon_get_bios(struct radeon_device *rdev);
242
243/*
3ce0a23d 244 * Dummy page
771fe6b9 245 */
3ce0a23d 246struct radeon_dummy_page {
cb658906 247 uint64_t entry;
3ce0a23d
JG		 248 struct page *page;
249 dma_addr_t addr;
250};
251int radeon_dummy_page_init(struct radeon_device *rdev);
252void radeon_dummy_page_fini(struct radeon_device *rdev);
253
771fe6b9 254
3ce0a23d
JG		 255/*
256 * Clocks
257 */
771fe6b9
JG		 258struct radeon_clock {
259 struct radeon_pll p1pll;
260 struct radeon_pll p2pll;
bcc1c2a1 261 struct radeon_pll dcpll;
771fe6b9
JG		 262 struct radeon_pll spll;
263 struct radeon_pll mpll;
264 /* 10 Khz units */
265 uint32_t default_mclk;
266 uint32_t default_sclk;
bcc1c2a1 267 uint32_t default_dispclk;
4489cd62 268 uint32_t current_dispclk;
bcc1c2a1 269 uint32_t dp_extclk;
b20f9bef 270 uint32_t max_pixel_clock;
c9a392ea 271 uint32_t vco_freq;
771fe6b9
JG		 272};
273
7433874e
RM		 274/*
275 * Power management
276 */
277int radeon_pm_init(struct radeon_device *rdev);
914a8987 278int radeon_pm_late_init(struct radeon_device *rdev);
29fb52ca 279void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 280void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 281void radeon_pm_suspend(struct radeon_device *rdev);
282void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 283void radeon_combios_get_power_modes(struct radeon_device *rdev);
284void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 285int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
286 u8 clock_type,
287 u32 clock,
288 bool strobe_mode,
289 struct atom_clock_dividers *dividers);
eaa778af
AD		 290int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
291 u32 clock,
292 bool strobe_mode,
293 struct atom_mpll_param *mpll_param);
8a83ec5e 294void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 295int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
296 u16 voltage_level, u8 voltage_type,
297 u32 *gpio_value, u32 *gpio_mask);
298void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
299 u32 eng_clock, u32 mem_clock);
300int radeon_atom_get_voltage_step(struct radeon_device *rdev,
301 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 302int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
303 u16 voltage_id, u16 *voltage);
beb79f40
AD		 304int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
305 u16 *voltage,
306 u16 leakage_idx);
cc8dbbb4
AD		 307int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
308 u16 *leakage_id);
309int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
310 u16 *vddc, u16 *vddci,
311 u16 virtual_voltage_id,
312 u16 vbios_voltage_id);
e9f274b2
AD		 313int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
314 u16 virtual_voltage_id,
315 u16 *voltage);
ae5b0abb
AD		 316int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
317 u8 voltage_type,
318 u16 nominal_voltage,
319 u16 *true_voltage);
320int radeon_atom_get_min_voltage(struct radeon_device *rdev,
321 u8 voltage_type, u16 *min_voltage);
322int radeon_atom_get_max_voltage(struct radeon_device *rdev,
323 u8 voltage_type, u16 *max_voltage);
324int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 325 u8 voltage_type, u8 voltage_mode,
ae5b0abb 326 struct atom_voltage_table *voltage_table);
58653abd
AD		 327bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
328 u8 voltage_type, u8 voltage_mode);
636e2582
AD		 329int radeon_atom_get_svi2_info(struct radeon_device *rdev,
330 u8 voltage_type,
331 u8 *svd_gpio_id, u8 *svc_gpio_id);
ae5b0abb
AD		 332void radeon_atom_update_memory_dll(struct radeon_device *rdev,
333 u32 mem_clock);
334void radeon_atom_set_ac_timing(struct radeon_device *rdev,
335 u32 mem_clock);
336int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
337 u8 module_index,
338 struct atom_mc_reg_table *reg_table);
339int radeon_atom_get_memory_info(struct radeon_device *rdev,
340 u8 module_index, struct atom_memory_info *mem_info);
341int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
342 bool gddr5, u8 module_index,
343 struct atom_memory_clock_range_table *mclk_range_table);
344int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
345 u16 voltage_id, u16 *voltage);
f892034a 346void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 347extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
348 unsigned *bankh, unsigned *mtaspect,
349 unsigned *tile_split);
3ce0a23d 350
771fe6b9
JG		 351/*
352 * Fences.
353 */
354struct radeon_fence_driver {
0bfa4b41 355 struct radeon_device *rdev;
771fe6b9 356 uint32_t scratch_reg;
30eb77f4
JG		 357 uint64_t gpu_addr;
358 volatile uint32_t *cpu_addr;
68e250b7
CK		 359 /* sync_seq is protected by ring emission lock */
360 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 361 atomic64_t last_seq;
954605ca 362 bool initialized, delayed_irq;
0bfa4b41 363 struct delayed_work lockup_work;
771fe6b9
JG		 364};
365
366struct radeon_fence {
ad1a58a4 367 struct fence base;
954605ca 368
ad1a58a4
CK		 369 struct radeon_device *rdev;
370 uint64_t seq;
7465280c 371 /* RB, DMA, etc. */
ad1a58a4
CK		 372 unsigned ring;
373 bool is_vm_update;
954605ca 374
ad1a58a4 375 wait_queue_t fence_wake;
771fe6b9
JG		 376};
377
30eb77f4
JG		 378int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
379int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 380void radeon_fence_driver_fini(struct radeon_device *rdev);
eb98c709 381void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
876dc9f3 382int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 383void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 384bool radeon_fence_signaled(struct radeon_fence *fence);
385int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
37615527
CK		 386int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
387int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
0085c950
JG		 388int radeon_fence_wait_any(struct radeon_device *rdev,
389 struct radeon_fence **fences,
390 bool intr);
771fe6b9
JG		 391struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
392void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 393unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 394bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
395void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
396static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
397 struct radeon_fence *b)
398{
399 if (!a) {
400 return b;
401 }
402
403 if (!b) {
404 return a;
405 }
406
407 BUG_ON(a->ring != b->ring);
408
409 if (a->seq > b->seq) {
410 return a;
411 } else {
412 return b;
413 }
414}
771fe6b9 415
ee60e29f
CK		 416static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
417 struct radeon_fence *b)
418{
419 if (!a) {
420 return false;
421 }
422
423 if (!b) {
424 return true;
425 }
426
427 BUG_ON(a->ring != b->ring);
428
429 return a->seq < b->seq;
430}
431
e024e110
DA		 432/*
433 * Tiling registers
434 */
435struct radeon_surface_reg {
4c788679 436 struct radeon_bo *bo;
e024e110
DA		 437};
438
439#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 440
441/*
4c788679 442 * TTM.
771fe6b9 443 */
4c788679
JG		 444struct radeon_mman {
445 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 446 struct drm_global_reference mem_global_ref;
4c788679 447 struct ttm_bo_device bdev;
0a0c7596
JG		 448 bool mem_global_referenced;
449 bool initialized;
2014b569
CK		 450
451#if defined(CONFIG_DEBUG_FS)
452 struct dentry *vram;
dd66d20e 453 struct dentry *gtt;
2014b569 454#endif
4c788679
JG		 455};
456
1d0c0942
CK		 457struct radeon_bo_list {
458 struct radeon_bo *robj;
459 struct ttm_validate_buffer tv;
460 uint64_t gpu_offset;
461 unsigned prefered_domains;
462 unsigned allowed_domains;
463 uint32_t tiling_flags;
464};
465
721604a1
JG		 466/* bo virtual address in a specific vm */
467struct radeon_bo_va {
e971bd5e 468 /* protected by bo being reserved */
721604a1 469 struct list_head bo_list;
721604a1 470 uint32_t flags;
94214635 471 struct radeon_fence *last_pt_update;
e971bd5e
CK		 472 unsigned ref_count;
473
474 /* protected by vm mutex */
0aea5e4a 475 struct interval_tree_node it;
036bf46a 476 struct list_head vm_status;
e971bd5e
CK		 477
478 /* constant after initialization */
479 struct radeon_vm *vm;
480 struct radeon_bo *bo;
721604a1
JG		 481};
482
4c788679
JG		 483struct radeon_bo {
484 /* Protected by gem.mutex */
485 struct list_head list;
486 /* Protected by tbo.reserved */
bda72d58 487 u32 initial_domain;
c9da4a4b 488 struct ttm_place placements[4];
312ea8da 489 struct ttm_placement placement;
4c788679
JG		 490 struct ttm_buffer_object tbo;
491 struct ttm_bo_kmap_obj kmap;
02376d82 492 u32 flags;
4c788679
JG		 493 unsigned pin_count;
494 void *kptr;
495 u32 tiling_flags;
496 u32 pitch;
497 int surface_reg;
721604a1
JG		 498 /* list of all virtual address to which this bo
499 * is associated to
500 */
501 struct list_head va;
4c788679
JG		 502 /* Constant after initialization */
503 struct radeon_device *rdev;
441921d5 504 struct drm_gem_object gem_base;
63bc620b 505
409851f4
JG		 506 struct ttm_bo_kmap_obj dma_buf_vmap;
507 pid_t pid;
341cb9e4
CK		 508
509 struct radeon_mn *mn;
49ecb10e 510 struct list_head mn_list;
4c788679 511};
7e4d15d9 512#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 513
409851f4
JG		 514int radeon_gem_debugfs_init(struct radeon_device *rdev);
515
b15ba512
JG		 516/* sub-allocation manager, it has to be protected by another lock.
517 * By conception this is an helper for other part of the driver
518 * like the indirect buffer or semaphore, which both have their
519 * locking.
520 *
521 * Principe is simple, we keep a list of sub allocation in offset
522 * order (first entry has offset == 0, last entry has the highest
523 * offset).
524 *
525 * When allocating new object we first check if there is room at
526 * the end total_size - (last_object_offset + last_object_size) >=
527 * alloc_size. If so we allocate new object there.
528 *
529 * When there is not enough room at the end, we start waiting for
530 * each sub object until we reach object_offset+object_size >=
531 * alloc_size, this object then become the sub object we return.
532 *
533 * Alignment can't be bigger than page size.
534 *
535 * Hole are not considered for allocation to keep things simple.
536 * Assumption is that there won't be hole (all object on same
537 * alignment).
538 */
539struct radeon_sa_manager {
bfb38d35 540 wait_queue_head_t wq;
b15ba512 541 struct radeon_bo *bo;
c3b7fe8b
CK		 542 struct list_head *hole;
543 struct list_head flist[RADEON_NUM_RINGS];
544 struct list_head olist;
b15ba512
JG		 545 unsigned size;
546 uint64_t gpu_addr;
547 void *cpu_ptr;
548 uint32_t domain;
6c4f978b 549 uint32_t align;
b15ba512
JG		 550};
551
552struct radeon_sa_bo;
553
554/* sub-allocation buffer */
555struct radeon_sa_bo {
c3b7fe8b
CK		 556 struct list_head olist;
557 struct list_head flist;
b15ba512 558 struct radeon_sa_manager *manager;
e6661a96
CK		 559 unsigned soffset;
560 unsigned eoffset;
557017a0 561 struct radeon_fence *fence;
b15ba512
JG		 562};
563
771fe6b9
JG		 564/*
565 * GEM objects.
566 */
567struct radeon_gem {
4c788679 568 struct mutex mutex;
771fe6b9
JG		 569 struct list_head objects;
570};
571
572int radeon_gem_init(struct radeon_device *rdev);
573void radeon_gem_fini(struct radeon_device *rdev);
391bfec3 574int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
4c788679 575 int alignment, int initial_domain,
ed5cb43f 576 u32 flags, bool kernel,
4c788679 577 struct drm_gem_object **obj);
771fe6b9 578
ff72145b
DA		 579int radeon_mode_dumb_create(struct drm_file *file_priv,
580 struct drm_device *dev,
581 struct drm_mode_create_dumb *args);
582int radeon_mode_dumb_mmap(struct drm_file *filp,
583 struct drm_device *dev,
584 uint32_t handle, uint64_t *offset_p);
771fe6b9 585
c1341e52
JG		 586/*
587 * Semaphores.
588 */
c1341e52 589struct radeon_semaphore {
975700d2
CK		 590 struct radeon_sa_bo *sa_bo;
591 signed waiters;
592 uint64_t gpu_addr;
c1341e52
JG		 593};
594
c1341e52
JG		 595int radeon_semaphore_create(struct radeon_device *rdev,
596 struct radeon_semaphore **semaphore);
1654b817 597bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
c1341e52 598 struct radeon_semaphore *semaphore);
1654b817 599bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
c1341e52
JG		 600 struct radeon_semaphore *semaphore);
601void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 602 struct radeon_semaphore **semaphore,
a8c05940 603 struct radeon_fence *fence);
c1341e52 604
975700d2
CK		 605/*
606 * Synchronization
607 */
608struct radeon_sync {
609 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
610 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
ad1a58a4 611 struct radeon_fence *last_vm_update;
975700d2
CK		 612};
613
614void radeon_sync_create(struct radeon_sync *sync);
615void radeon_sync_fence(struct radeon_sync *sync,
616 struct radeon_fence *fence);
617int radeon_sync_resv(struct radeon_device *rdev,
618 struct radeon_sync *sync,
619 struct reservation_object *resv,
620 bool shared);
621int radeon_sync_rings(struct radeon_device *rdev,
622 struct radeon_sync *sync,
623 int waiting_ring);
624void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
625 struct radeon_fence *fence);
626
771fe6b9
JG		 627/*
628 * GART structures, functions & helpers
629 */
630struct radeon_mc;
631
a77f1718 632#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 633#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 634#define RADEON_GPU_PAGE_SHIFT 12
721604a1 635#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 636
77497f27
MD		 637#define RADEON_GART_PAGE_DUMMY 0
638#define RADEON_GART_PAGE_VALID (1 << 0)
639#define RADEON_GART_PAGE_READ (1 << 1)
640#define RADEON_GART_PAGE_WRITE (1 << 2)
641#define RADEON_GART_PAGE_SNOOP (1 << 3)
642
771fe6b9
JG		 643struct radeon_gart {
644 dma_addr_t table_addr;
c9a1be96
JG		 645 struct radeon_bo *robj;
646 void *ptr;
771fe6b9
JG		 647 unsigned num_gpu_pages;
648 unsigned num_cpu_pages;
649 unsigned table_size;
771fe6b9 650 struct page **pages;
cb658906 651 uint64_t *pages_entry;
771fe6b9
JG		 652 bool ready;
653};
654
655int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
656void radeon_gart_table_ram_free(struct radeon_device *rdev);
657int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
658void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 659int radeon_gart_table_vram_pin(struct radeon_device *rdev);
660void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 661int radeon_gart_init(struct radeon_device *rdev);
662void radeon_gart_fini(struct radeon_device *rdev);
663void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
664 int pages);
665int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516 666 int pages, struct page **pagelist,
77497f27 667 dma_addr_t *dma_addr, uint32_t flags);
771fe6b9
JG		 668
669
670/*
671 * GPU MC structures, functions & helpers
672 */
673struct radeon_mc {
674 resource_size_t aper_size;
675 resource_size_t aper_base;
676 resource_size_t agp_base;
7a50f01a
DA		 677 /* for some chips with <= 32MB we need to lie
678 * about vram size near mc fb location */
3ce0a23d 679 u64 mc_vram_size;
d594e46a 680 u64 visible_vram_size;
3ce0a23d
JG		 681 u64 gtt_size;
682 u64 gtt_start;
683 u64 gtt_end;
3ce0a23d
JG		 684 u64 vram_start;
685 u64 vram_end;
771fe6b9 686 unsigned vram_width;
3ce0a23d 687 u64 real_vram_size;
771fe6b9
JG		 688 int vram_mtrr;
689 bool vram_is_ddr;
d594e46a 690 bool igp_sideport_enabled;
8d369bb1 691 u64 gtt_base_align;
9ed8b1f9 692 u64 mc_mask;
771fe6b9
JG		 693};
694
06b6476d
AD		 695bool radeon_combios_sideport_present(struct radeon_device *rdev);
696bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 697
698/*
699 * GPU scratch registers structures, functions & helpers
700 */
701struct radeon_scratch {
702 unsigned num_reg;
724c80e1 703 uint32_t reg_base;
771fe6b9
JG		 704 bool free[32];
705 uint32_t reg[32];
706};
707
708int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
709void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
710
75efdee1
AD		 711/*
712 * GPU doorbell structures, functions & helpers
713 */
d5754ab8
AL		 714#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
715
75efdee1 716struct radeon_doorbell {
75efdee1 717 /* doorbell mmio */
d5754ab8
AL		 718 resource_size_t base;
719 resource_size_t size;
720 u32 __iomem *ptr;
721 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
a10e04f4 722 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
75efdee1
AD		 723};
724
725int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
726void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
ebff8453
OG		 727void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
728 phys_addr_t *aperture_base,
729 size_t *aperture_size,
730 size_t *start_offset);
771fe6b9
JG		 731
732/*
733 * IRQS.
734 */
6f34be50 735
fa7f517c
CK		 736struct radeon_flip_work {
737 struct work_struct flip_work;
738 struct work_struct unpin_work;
739 struct radeon_device *rdev;
740 int crtc_id;
c60381bd 741 uint64_t base;
6f34be50 742 struct drm_pending_vblank_event *event;
fa7f517c 743 struct radeon_bo *old_rbo;
a0e84764 744 struct fence *fence;
6f34be50
AD		 745};
746
747struct r500_irq_stat_regs {
748 u32 disp_int;
f122c610 749 u32 hdmi0_status;
6f34be50
AD		 750};
751
752struct r600_irq_stat_regs {
753 u32 disp_int;
754 u32 disp_int_cont;
755 u32 disp_int_cont2;
756 u32 d1grph_int;
757 u32 d2grph_int;
f122c610
AD		 758 u32 hdmi0_status;
759 u32 hdmi1_status;
6f34be50
AD		 760};
761
762struct evergreen_irq_stat_regs {
763 u32 disp_int;
764 u32 disp_int_cont;
765 u32 disp_int_cont2;
766 u32 disp_int_cont3;
767 u32 disp_int_cont4;
768 u32 disp_int_cont5;
769 u32 d1grph_int;
770 u32 d2grph_int;
771 u32 d3grph_int;
772 u32 d4grph_int;
773 u32 d5grph_int;
774 u32 d6grph_int;
f122c610
AD		 775 u32 afmt_status1;
776 u32 afmt_status2;
777 u32 afmt_status3;
778 u32 afmt_status4;
779 u32 afmt_status5;
780 u32 afmt_status6;
6f34be50
AD		 781};
782
a59781bb
AD		 783struct cik_irq_stat_regs {
784 u32 disp_int;
785 u32 disp_int_cont;
786 u32 disp_int_cont2;
787 u32 disp_int_cont3;
788 u32 disp_int_cont4;
789 u32 disp_int_cont5;
790 u32 disp_int_cont6;
f5d636d2
CK		 791 u32 d1grph_int;
792 u32 d2grph_int;
793 u32 d3grph_int;
794 u32 d4grph_int;
795 u32 d5grph_int;
796 u32 d6grph_int;
a59781bb
AD		 797};
798
6f34be50
AD		 799union radeon_irq_stat_regs {
800 struct r500_irq_stat_regs r500;
801 struct r600_irq_stat_regs r600;
802 struct evergreen_irq_stat_regs evergreen;
a59781bb 803 struct cik_irq_stat_regs cik;
6f34be50
AD		 804};
805
771fe6b9 806struct radeon_irq {
fb98257a
CK		 807 bool installed;
808 spinlock_t lock;
736fc37f 809 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 810 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 811 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 812 wait_queue_head_t vblank_queue;
813 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 814 bool afmt[RADEON_MAX_AFMT_BLOCKS];
815 union radeon_irq_stat_regs stat_regs;
4a6369e9 816 bool dpm_thermal;
771fe6b9
JG		 817};
818
819int radeon_irq_kms_init(struct radeon_device *rdev);
820void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b 821void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
954605ca 822bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
1b37078b 823void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 824void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
825void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 826void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
827void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
828void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
829void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 830
831/*
e32eb50d 832 * CP & rings.
771fe6b9 833 */
7465280c 834
771fe6b9 835struct radeon_ib {
68470ae7
JG		 836 struct radeon_sa_bo *sa_bo;
837 uint32_t length_dw;
838 uint64_t gpu_addr;
839 uint32_t *ptr;
876dc9f3 840 int ring;
68470ae7 841 struct radeon_fence *fence;
4bf3dd92 842 struct radeon_vm *vm;
68470ae7 843 bool is_const_ib;
975700d2 844 struct radeon_sync sync;
771fe6b9
JG		 845};
846
e32eb50d 847struct radeon_ring {
4c788679 848 struct radeon_bo *ring_obj;
771fe6b9 849 volatile uint32_t *ring;
5596a9db 850 unsigned rptr_offs;
45df6803 851 unsigned rptr_save_reg;
89d35807
AD		 852 u64 next_rptr_gpu_addr;
853 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 854 unsigned wptr;
855 unsigned wptr_old;
856 unsigned ring_size;
857 unsigned ring_free_dw;
858 int count_dw;
aee4aa73
CK		 859 atomic_t last_rptr;
860 atomic64_t last_activity;
771fe6b9
JG		 861 uint64_t gpu_addr;
862 uint32_t align_mask;
863 uint32_t ptr_mask;
771fe6b9 864 bool ready;
78c5560a 865 u32 nop;
8b25ed34 866 u32 idx;
5f0839c1
JG		 867 u64 last_semaphore_signal_addr;
868 u64 last_semaphore_wait_addr;
963e81f9
AD		 869 /* for CIK queues */
870 u32 me;
871 u32 pipe;
872 u32 queue;
873 struct radeon_bo *mqd_obj;
d5754ab8 874 u32 doorbell_index;
963e81f9
AD		 875 unsigned wptr_offs;
876};
877
878struct radeon_mec {
879 struct radeon_bo *hpd_eop_obj;
880 u64 hpd_eop_gpu_addr;
881 u32 num_pipe;
882 u32 num_mec;
883 u32 num_queue;
771fe6b9
JG		 884};
885
721604a1
JG		 886/*
887 * VM
888 */
ee60e29f 889
fa87e62d 890/* maximum number of VMIDs */
ee60e29f
CK		 891#define RADEON_NUM_VM 16
892
fa87e62d 893/* number of entries in page table */
4510fb98 894#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
fa87e62d 895
1c01103c
AD		 896/* PTBs (Page Table Blocks) need to be aligned to 32K */
897#define RADEON_VM_PTB_ALIGN_SIZE 32768
898#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
899#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
900
24c16439
CK		 901#define R600_PTE_VALID (1 << 0)
902#define R600_PTE_SYSTEM (1 << 1)
903#define R600_PTE_SNOOPED (1 << 2)
904#define R600_PTE_READABLE (1 << 5)
905#define R600_PTE_WRITEABLE (1 << 6)
906
ec3dbbcb
CK		 907/* PTE (Page Table Entry) fragment field for different page sizes */
908#define R600_PTE_FRAG_4KB (0 << 7)
909#define R600_PTE_FRAG_64KB (4 << 7)
910#define R600_PTE_FRAG_256KB (6 << 7)
911
33fa9fe3
CK		 912/* flags needed to be set so we can copy directly from the GART table */
913#define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
914 R600_PTE_SYSTEM | R600_PTE_VALID )
0e97703c 915
6d2f2944
CK		 916struct radeon_vm_pt {
917 struct radeon_bo *bo;
918 uint64_t addr;
919};
920
7c42bc1a
CK		 921struct radeon_vm_id {
922 unsigned id;
923 uint64_t pd_gpu_addr;
924 /* last flushed PD/PT update */
925 struct radeon_fence *flushed_updates;
926 /* last use of vmid */
927 struct radeon_fence *last_id_use;
928};
929
721604a1 930struct radeon_vm {
94214635
CK		 931 struct mutex mutex;
932
7c42bc1a 933 struct rb_root va;
90a51a32 934
f7a3db75
CK		 935 /* protecting invalidated and freed */
936 spinlock_t status_lock;
937
e31ad969 938 /* BOs moved, but not yet updated in the PT */
7c42bc1a 939 struct list_head invalidated;
e31ad969 940
036bf46a 941 /* BOs freed, but not yet updated in the PT */
7c42bc1a 942 struct list_head freed;
036bf46a 943
161ab658
CK		 944 /* BOs cleared in the PT */
945 struct list_head cleared;
946
90a51a32 947 /* contains the page directory */
7c42bc1a
CK		 948 struct radeon_bo *page_directory;
949 unsigned max_pde_used;
90a51a32
CK		 950
951 /* array of page tables, one for each page directory entry */
7c42bc1a 952 struct radeon_vm_pt *page_tables;
90a51a32 953
7c42bc1a 954 struct radeon_bo_va *ib_bo_va;
cc9e67e3 955
7c42bc1a
CK		 956 /* for id and flush management per ring */
957 struct radeon_vm_id ids[RADEON_NUM_RINGS];
721604a1
JG		 958};
959
721604a1 960struct radeon_vm_manager {
ee60e29f 961 struct radeon_fence *active[RADEON_NUM_VM];
721604a1 962 uint32_t max_pfn;
721604a1
JG		 963 /* number of VMIDs */
964 unsigned nvm;
965 /* vram base address for page table entry */
966 u64 vram_base_offset;
67e915e4
AD		 967 /* is vm enabled? */
968 bool enabled;
054e01d6
CK		 969 /* for hw to save the PD addr on suspend/resume */
970 uint32_t saved_table_addr[RADEON_NUM_VM];
721604a1
JG		 971};
972
973/*
974 * file private structure
975 */
976struct radeon_fpriv {
977 struct radeon_vm vm;
978};
979
d8f60cfc
AD		 980/*
981 * R6xx+ IH ring
982 */
983struct r600_ih {
4c788679 984 struct radeon_bo *ring_obj;
d8f60cfc
AD		 985 volatile uint32_t *ring;
986 unsigned rptr;
d8f60cfc
AD		 987 unsigned ring_size;
988 uint64_t gpu_addr;
d8f60cfc 989 uint32_t ptr_mask;
c20dc369 990 atomic_t lock;
d8f60cfc
AD		 991 bool enabled;
992};
993
347e7592 994/*
2948f5e6 995 * RLC stuff
347e7592 996 */
2948f5e6
AD		 997#include "clearstate_defs.h"
998
999struct radeon_rlc {
347e7592
AD		 1000 /* for power gating */
1001 struct radeon_bo *save_restore_obj;
1002 uint64_t save_restore_gpu_addr;
2948f5e6 1003 volatile uint32_t *sr_ptr;
1fd11777 1004 const u32 *reg_list;
2948f5e6 1005 u32 reg_list_size;
347e7592
AD		 1006 /* for clear state */
1007 struct radeon_bo *clear_state_obj;
1008 uint64_t clear_state_gpu_addr;
2948f5e6 1009 volatile uint32_t *cs_ptr;
1fd11777 1010 const struct cs_section_def *cs_data;
22c775ce
AD		 1011 u32 clear_state_size;
1012 /* for cp tables */
1013 struct radeon_bo *cp_table_obj;
1014 uint64_t cp_table_gpu_addr;
1015 volatile uint32_t *cp_table_ptr;
1016 u32 cp_table_size;
347e7592
AD		 1017};
1018
69e130a6 1019int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 1020 struct radeon_ib *ib, struct radeon_vm *vm,
1021 unsigned size);
f2e39221 1022void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
4ef72566 1023int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1538a9e0 1024 struct radeon_ib *const_ib, bool hdp_flush);
771fe6b9
JG		 1025int radeon_ib_pool_init(struct radeon_device *rdev);
1026void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 1027int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 1028/* Ring access between begin & end cannot sleep */
89d35807
AD		 1029bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1030 struct radeon_ring *ring);
e32eb50d
CK		 1031void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1032int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1033int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1538a9e0
MD		 1034void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1035 bool hdp_flush);
1036void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1037 bool hdp_flush);
d6999bc7 1038void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 1039void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1040int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
ff212f25
CK		 1041void radeon_ring_lockup_update(struct radeon_device *rdev,
1042 struct radeon_ring *ring);
069211e5 1043bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 1044unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1045 uint32_t **data);
1046int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1047 unsigned size, uint32_t *data);
e32eb50d 1048int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
ea31bf69 1049 unsigned rptr_offs, u32 nop);
e32eb50d 1050void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 1051
1052
4d75658b
AD		 1053/* r600 async dma */
1054void r600_dma_stop(struct radeon_device *rdev);
1055int r600_dma_resume(struct radeon_device *rdev);
1056void r600_dma_fini(struct radeon_device *rdev);
1057
8c5fd7ef
AD		 1058void cayman_dma_stop(struct radeon_device *rdev);
1059int cayman_dma_resume(struct radeon_device *rdev);
1060void cayman_dma_fini(struct radeon_device *rdev);
1061
771fe6b9
JG		 1062/*
1063 * CS.
1064 */
771fe6b9 1065struct radeon_cs_chunk {
771fe6b9
JG		 1066 uint32_t length_dw;
1067 uint32_t *kdata;
721604a1 1068 void __user *user_ptr;
771fe6b9
JG		 1069};
1070
1071struct radeon_cs_parser {
c8c15ff1 1072 struct device *dev;
771fe6b9
JG		 1073 struct radeon_device *rdev;
1074 struct drm_file *filp;
1075 /* chunks */
1076 unsigned nchunks;
1077 struct radeon_cs_chunk *chunks;
1078 uint64_t *chunks_array;
1079 /* IB */
1080 unsigned idx;
1081 /* relocations */
1082 unsigned nrelocs;
1d0c0942 1083 struct radeon_bo_list *relocs;
1d0c0942 1084 struct radeon_bo_list *vm_bos;
771fe6b9 1085 struct list_head validated;
cf4ccd01 1086 unsigned dma_reloc_idx;
771fe6b9 1087 /* indices of various chunks */
6d2d13dd
CK		 1088 struct radeon_cs_chunk *chunk_ib;
1089 struct radeon_cs_chunk *chunk_relocs;
1090 struct radeon_cs_chunk *chunk_flags;
1091 struct radeon_cs_chunk *chunk_const_ib;
f2e39221
JG		 1092 struct radeon_ib ib;
1093 struct radeon_ib const_ib;
771fe6b9 1094 void *track;
3ce0a23d 1095 unsigned family;
e70f224c 1096 int parser_error;
721604a1
JG		 1097 u32 cs_flags;
1098 u32 ring;
1099 s32 priority;
ecff665f 1100 struct ww_acquire_ctx ticket;
771fe6b9
JG		 1101};
1102
28a326c5
ML		 1103static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1104{
6d2d13dd 1105 struct radeon_cs_chunk *ibc = p->chunk_ib;
28a326c5
ML		 1106
1107 if (ibc->kdata)
1108 return ibc->kdata[idx];
1109 return p->ib.ptr[idx];
1110}
1111
513bcb46 1112
771fe6b9
JG		 1113struct radeon_cs_packet {
1114 unsigned idx;
1115 unsigned type;
1116 unsigned reg;
1117 unsigned opcode;
1118 int count;
1119 unsigned one_reg_wr;
1120};
1121
1122typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1123 struct radeon_cs_packet *pkt,
1124 unsigned idx, unsigned reg);
1125typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1126 struct radeon_cs_packet *pkt);
1127
1128
1129/*
1130 * AGP
1131 */
1132int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1133void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1134void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1135void radeon_agp_fini(struct radeon_device *rdev);
1136
1137
1138/*
1139 * Writeback
1140 */
1141struct radeon_wb {
4c788679 1142 struct radeon_bo *wb_obj;
771fe6b9
JG		 1143 volatile uint32_t *wb;
1144 uint64_t gpu_addr;
724c80e1 1145 bool enabled;
d0f8a854 1146 bool use_event;
771fe6b9
JG		 1147};
1148
724c80e1 1149#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1150#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1151#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1152#define RADEON_WB_CP1_RPTR_OFFSET 1280
1153#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1154#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1155#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1156#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1157#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1158#define CIK_WB_CP1_WPTR_OFFSET 3328
1159#define CIK_WB_CP2_WPTR_OFFSET 3584
adfed2b0
AD		 1160#define R600_WB_DMA_RING_TEST_OFFSET 3588
1161#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
724c80e1 1162
c93bb85b
JG		 1163/**
1164 * struct radeon_pm - power management datas
1165 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1166 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1167 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1168 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1169 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1170 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1171 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1172 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1173 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1174 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1175 * @needed_bandwidth: current bandwidth needs
1176 *
1177 * It keeps track of various data needed to take powermanagement decision.
25985edc 1178 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1179 * Equation between gpu/memory clock and available bandwidth is hw dependent
1180 * (type of memory, bus size, efficiency, ...)
1181 */
ce8f5370
AD		 1182
1183enum radeon_pm_method {
1184 PM_METHOD_PROFILE,
1185 PM_METHOD_DYNPM,
da321c8a 1186 PM_METHOD_DPM,
ce8f5370
AD		 1187};
1188
1189enum radeon_dynpm_state {
1190 DYNPM_STATE_DISABLED,
1191 DYNPM_STATE_MINIMUM,
1192 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1193 DYNPM_STATE_ACTIVE,
1194 DYNPM_STATE_SUSPENDED,
c913e23a 1195};
ce8f5370
AD		 1196enum radeon_dynpm_action {
1197 DYNPM_ACTION_NONE,
1198 DYNPM_ACTION_MINIMUM,
1199 DYNPM_ACTION_DOWNCLOCK,
1200 DYNPM_ACTION_UPCLOCK,
1201 DYNPM_ACTION_DEFAULT
c913e23a 1202};
56278a8e
AD		 1203
1204enum radeon_voltage_type {
1205 VOLTAGE_NONE = 0,
1206 VOLTAGE_GPIO,
1207 VOLTAGE_VDDC,
1208 VOLTAGE_SW
1209};
1210
0ec0e74f 1211enum radeon_pm_state_type {
da321c8a 1212 /* not used for dpm */
0ec0e74f
AD		 1213 POWER_STATE_TYPE_DEFAULT,
1214 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1215 /* user selectable states */
0ec0e74f
AD		 1216 POWER_STATE_TYPE_BATTERY,
1217 POWER_STATE_TYPE_BALANCED,
1218 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1219 /* internal states */
1220 POWER_STATE_TYPE_INTERNAL_UVD,
1221 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1222 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1223 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1224 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1225 POWER_STATE_TYPE_INTERNAL_BOOT,
1226 POWER_STATE_TYPE_INTERNAL_THERMAL,
1227 POWER_STATE_TYPE_INTERNAL_ACPI,
1228 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1229 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1230};
1231
ce8f5370
AD		 1232enum radeon_pm_profile_type {
1233 PM_PROFILE_DEFAULT,
1234 PM_PROFILE_AUTO,
1235 PM_PROFILE_LOW,
c9e75b21 1236 PM_PROFILE_MID,
ce8f5370
AD		 1237 PM_PROFILE_HIGH,
1238};
1239
1240#define PM_PROFILE_DEFAULT_IDX 0
1241#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1242#define PM_PROFILE_MID_SH_IDX 2
1243#define PM_PROFILE_HIGH_SH_IDX 3
1244#define PM_PROFILE_LOW_MH_IDX 4
1245#define PM_PROFILE_MID_MH_IDX 5
1246#define PM_PROFILE_HIGH_MH_IDX 6
1247#define PM_PROFILE_MAX 7
ce8f5370
AD		 1248
1249struct radeon_pm_profile {
1250 int dpms_off_ps_idx;
1251 int dpms_on_ps_idx;
1252 int dpms_off_cm_idx;
1253 int dpms_on_cm_idx;
516d0e46
AD		 1254};
1255
21a8122a
AD		 1256enum radeon_int_thermal_type {
1257 THERMAL_TYPE_NONE,
da321c8a
AD		 1258 THERMAL_TYPE_EXTERNAL,
1259 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1260 THERMAL_TYPE_RV6XX,
1261 THERMAL_TYPE_RV770,
da321c8a 1262 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1263 THERMAL_TYPE_EVERGREEN,
e33df25f 1264 THERMAL_TYPE_SUMO,
4fddba1f 1265 THERMAL_TYPE_NI,
14607d08 1266 THERMAL_TYPE_SI,
da321c8a 1267 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1268 THERMAL_TYPE_CI,
16fbe00d 1269 THERMAL_TYPE_KV,
21a8122a
AD		 1270};
1271
56278a8e
AD		 1272struct radeon_voltage {
1273 enum radeon_voltage_type type;
1274 /* gpio voltage */
1275 struct radeon_gpio_rec gpio;
1276 u32 delay; /* delay in usec from voltage drop to sclk change */
1277 bool active_high; /* voltage drop is active when bit is high */
1278 /* VDDC voltage */
1279 u8 vddc_id; /* index into vddc voltage table */
1280 u8 vddci_id; /* index into vddci voltage table */
1281 bool vddci_enabled;
1282 /* r6xx+ sw */
2feea49a
AD		 1283 u16 voltage;
1284 /* evergreen+ vddci */
1285 u16 vddci;
56278a8e
AD		 1286};
1287
d7311171
AD		 1288/* clock mode flags */
1289#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1290
56278a8e
AD		 1291struct radeon_pm_clock_info {
1292 /* memory clock */
1293 u32 mclk;
1294 /* engine clock */
1295 u32 sclk;
1296 /* voltage info */
1297 struct radeon_voltage voltage;
d7311171 1298 /* standardized clock flags */
56278a8e
AD		 1299 u32 flags;
1300};
1301
a48b9b4e 1302/* state flags */
d7311171 1303#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1304
56278a8e 1305struct radeon_power_state {
0ec0e74f 1306 enum radeon_pm_state_type type;
8f3f1c9a 1307 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1308 /* number of valid clock modes in this power state */
1309 int num_clock_modes;
56278a8e 1310 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1311 /* standardized state flags */
1312 u32 flags;
79daedc9
AD		 1313 u32 misc; /* vbios specific flags */
1314 u32 misc2; /* vbios specific flags */
1315 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1316};
1317
27459324
RM		 1318/*
1319 * Some modes are overclocked by very low value, accept them
1320 */
1321#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1322
2e9d4c05
AD		 1323enum radeon_dpm_auto_throttle_src {
1324 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1325 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1326};
1327
1328enum radeon_dpm_event_src {
1329 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1330 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1331 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1332 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1333 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1334};
1335
58bd2a88
AD		 1336#define RADEON_MAX_VCE_LEVELS 6
1337
b62d628b
AD		 1338enum radeon_vce_level {
1339 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1340 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1341 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1342 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1343 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1344 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1345};
1346
da321c8a
AD		 1347struct radeon_ps {
1348 u32 caps; /* vbios flags */
1349 u32 class; /* vbios flags */
1350 u32 class2; /* vbios flags */
1351 /* UVD clocks */
1352 u32 vclk;
1353 u32 dclk;
c4453e66
AD		 1354 /* VCE clocks */
1355 u32 evclk;
1356 u32 ecclk;
b62d628b
AD		 1357 bool vce_active;
1358 enum radeon_vce_level vce_level;
da321c8a
AD		 1359 /* asic priv */
1360 void *ps_priv;
1361};
1362
1363struct radeon_dpm_thermal {
1364 /* thermal interrupt work */
1365 struct work_struct work;
1366 /* low temperature threshold */
1367 int min_temp;
1368 /* high temperature threshold */
1369 int max_temp;
1370 /* was interrupt low to high or high to low */
1371 bool high_to_low;
1372};
1373
d22b7e40
AD		 1374enum radeon_clk_action
1375{
1376 RADEON_SCLK_UP = 1,
1377 RADEON_SCLK_DOWN
1378};
1379
1380struct radeon_blacklist_clocks
1381{
1382 u32 sclk;
1383 u32 mclk;
1384 enum radeon_clk_action action;
1385};
1386
61b7d601
AD		 1387struct radeon_clock_and_voltage_limits {
1388 u32 sclk;
1389 u32 mclk;
cdf6e805
AD		 1390 u16 vddc;
1391 u16 vddci;
61b7d601
AD		 1392};
1393
1394struct radeon_clock_array {
1395 u32 count;
1396 u32 *values;
1397};
1398
1399struct radeon_clock_voltage_dependency_entry {
1400 u32 clk;
1401 u16 v;
1402};
1403
1404struct radeon_clock_voltage_dependency_table {
1405 u32 count;
1406 struct radeon_clock_voltage_dependency_entry *entries;
1407};
1408
ef976ec4
AD		 1409union radeon_cac_leakage_entry {
1410 struct {
1411 u16 vddc;
1412 u32 leakage;
1413 };
1414 struct {
1415 u16 vddc1;
1416 u16 vddc2;
1417 u16 vddc3;
1418 };
61b7d601
AD		 1419};
1420
1421struct radeon_cac_leakage_table {
1422 u32 count;
ef976ec4 1423 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1424};
1425
929ee7a8
AD		 1426struct radeon_phase_shedding_limits_entry {
1427 u16 voltage;
1428 u32 sclk;
1429 u32 mclk;
1430};
1431
1432struct radeon_phase_shedding_limits_table {
1433 u32 count;
1434 struct radeon_phase_shedding_limits_entry *entries;
1435};
1436
84a9d9ee
AD		 1437struct radeon_uvd_clock_voltage_dependency_entry {
1438 u32 vclk;
1439 u32 dclk;
1440 u16 v;
1441};
1442
1443struct radeon_uvd_clock_voltage_dependency_table {
1444 u8 count;
1445 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1446};
1447
d29f013b
AD		 1448struct radeon_vce_clock_voltage_dependency_entry {
1449 u32 ecclk;
1450 u32 evclk;
1451 u16 v;
1452};
1453
1454struct radeon_vce_clock_voltage_dependency_table {
1455 u8 count;
1456 struct radeon_vce_clock_voltage_dependency_entry *entries;
1457};
1458
a5cb318e
AD		 1459struct radeon_ppm_table {
1460 u8 ppm_design;
1461 u16 cpu_core_number;
1462 u32 platform_tdp;
1463 u32 small_ac_platform_tdp;
1464 u32 platform_tdc;
1465 u32 small_ac_platform_tdc;
1466 u32 apu_tdp;
1467 u32 dgpu_tdp;
1468 u32 dgpu_ulv_power;
1469 u32 tj_max;
1470};
1471
58cb7632
AD		 1472struct radeon_cac_tdp_table {
1473 u16 tdp;
1474 u16 configurable_tdp;
1475 u16 tdc;
1476 u16 battery_power_limit;
1477 u16 small_power_limit;
1478 u16 low_cac_leakage;
1479 u16 high_cac_leakage;
1480 u16 maximum_power_delivery_limit;
1481};
1482
61b7d601
AD		 1483struct radeon_dpm_dynamic_state {
1484 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1485 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1486 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1487 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1488 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1489 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1490 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1491 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1492 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1493 struct radeon_clock_array valid_sclk_values;
1494 struct radeon_clock_array valid_mclk_values;
1495 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1496 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1497 u32 mclk_sclk_ratio;
1498 u32 sclk_mclk_delta;
1499 u16 vddc_vddci_delta;
1500 u16 min_vddc_for_pcie_gen2;
1501 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1502 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1503 struct radeon_ppm_table *ppm_table;
58cb7632 1504 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1505};
1506
1507struct radeon_dpm_fan {
1508 u16 t_min;
1509 u16 t_med;
1510 u16 t_high;
1511 u16 pwm_min;
1512 u16 pwm_med;
1513 u16 pwm_high;
1514 u8 t_hyst;
1515 u32 cycle_delay;
1516 u16 t_max;
e03cea36
AD		 1517 u8 control_mode;
1518 u16 default_max_fan_pwm;
1519 u16 default_fan_output_sensitivity;
1520 u16 fan_output_sensitivity;
61b7d601
AD		 1521 bool ucode_fan_control;
1522};
1523
32ce4652
AD		 1524enum radeon_pcie_gen {
1525 RADEON_PCIE_GEN1 = 0,
1526 RADEON_PCIE_GEN2 = 1,
1527 RADEON_PCIE_GEN3 = 2,
1528 RADEON_PCIE_GEN_INVALID = 0xffff
1529};
1530
70d01a5e
AD		 1531enum radeon_dpm_forced_level {
1532 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1533 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1534 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1535};
1536
58bd2a88
AD		 1537struct radeon_vce_state {
1538 /* vce clocks */
1539 u32 evclk;
1540 u32 ecclk;
1541 /* gpu clocks */
1542 u32 sclk;
1543 u32 mclk;
1544 u8 clk_idx;
1545 u8 pstate;
1546};
1547
da321c8a
AD		 1548struct radeon_dpm {
1549 struct radeon_ps *ps;
1550 /* number of valid power states */
1551 int num_ps;
1552 /* current power state that is active */
1553 struct radeon_ps *current_ps;
1554 /* requested power state */
1555 struct radeon_ps *requested_ps;
1556 /* boot up power state */
1557 struct radeon_ps *boot_ps;
1558 /* default uvd power state */
1559 struct radeon_ps *uvd_ps;
58bd2a88
AD		 1560 /* vce requirements */
1561 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1562 enum radeon_vce_level vce_level;
da321c8a
AD		 1563 enum radeon_pm_state_type state;
1564 enum radeon_pm_state_type user_state;
1565 u32 platform_caps;
1566 u32 voltage_response_time;
1567 u32 backbias_response_time;
1568 void *priv;
1569 u32 new_active_crtcs;
1570 int new_active_crtc_count;
1571 u32 current_active_crtcs;
1572 int current_active_crtc_count;
3899ca84 1573 bool single_display;
61b7d601
AD		 1574 struct radeon_dpm_dynamic_state dyn_state;
1575 struct radeon_dpm_fan fan;
1576 u32 tdp_limit;
1577 u32 near_tdp_limit;
a9e61410 1578 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1579 u32 sq_ramping_threshold;
1580 u32 cac_leakage;
1581 u16 tdp_od_limit;
1582 u32 tdp_adjustment;
1583 u16 load_line_slope;
1584 bool power_control;
5ca302f7 1585 bool ac_power;
da321c8a
AD		 1586 /* special states active */
1587 bool thermal_active;
8a227555 1588 bool uvd_active;
b62d628b 1589 bool vce_active;
da321c8a
AD		 1590 /* thermal handling */
1591 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1592 /* forced levels */
1593 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1594 /* track UVD streams */
1595 unsigned sd;
1596 unsigned hd;
da321c8a
AD		 1597};
1598
ce3537d5 1599void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
03afe6f6 1600void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
da321c8a 1601
c93bb85b 1602struct radeon_pm {
c913e23a 1603 struct mutex mutex;
db7fce39
CK		 1604 /* write locked while reprogramming mclk */
1605 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1606 u32 active_crtcs;
1607 int active_crtc_count;
c913e23a 1608 int req_vblank;
839461d3 1609 bool vblank_sync;
c93bb85b
JG		 1610 fixed20_12 max_bandwidth;
1611 fixed20_12 igp_sideport_mclk;
1612 fixed20_12 igp_system_mclk;
1613 fixed20_12 igp_ht_link_clk;
1614 fixed20_12 igp_ht_link_width;
1615 fixed20_12 k8_bandwidth;
1616 fixed20_12 sideport_bandwidth;
1617 fixed20_12 ht_bandwidth;
1618 fixed20_12 core_bandwidth;
1619 fixed20_12 sclk;
f47299c5 1620 fixed20_12 mclk;
c93bb85b 1621 fixed20_12 needed_bandwidth;
0975b162 1622 struct radeon_power_state *power_state;
56278a8e
AD		 1623 /* number of valid power states */
1624 int num_power_states;
a48b9b4e
AD		 1625 int current_power_state_index;
1626 int current_clock_mode_index;
1627 int requested_power_state_index;
1628 int requested_clock_mode_index;
1629 int default_power_state_index;
1630 u32 current_sclk;
1631 u32 current_mclk;
2feea49a
AD		 1632 u16 current_vddc;
1633 u16 current_vddci;
9ace9f7b
AD		 1634 u32 default_sclk;
1635 u32 default_mclk;
2feea49a
AD		 1636 u16 default_vddc;
1637 u16 default_vddci;
29fb52ca 1638 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1639 /* selected pm method */
1640 enum radeon_pm_method pm_method;
1641 /* dynpm power management */
1642 struct delayed_work dynpm_idle_work;
1643 enum radeon_dynpm_state dynpm_state;
1644 enum radeon_dynpm_action dynpm_planned_action;
1645 unsigned long dynpm_action_timeout;
1646 bool dynpm_can_upclock;
1647 bool dynpm_can_downclock;
1648 /* profile-based power management */
1649 enum radeon_pm_profile_type profile;
1650 int profile_index;
1651 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1652 /* internal thermal controller on rv6xx+ */
1653 enum radeon_int_thermal_type int_thermal_type;
1654 struct device *int_hwmon_dev;
9b92d1ec
AD		 1655 /* fan control parameters */
1656 bool no_fan;
1657 u8 fan_pulses_per_revolution;
1658 u8 fan_min_rpm;
1659 u8 fan_max_rpm;
da321c8a
AD		 1660 /* dpm */
1661 bool dpm_enabled;
49abb266 1662 bool sysfs_initialized;
da321c8a 1663 struct radeon_dpm dpm;
c93bb85b
JG		 1664};
1665
a4c9e2ee
AD		 1666int radeon_pm_get_type_index(struct radeon_device *rdev,
1667 enum radeon_pm_state_type ps_type,
1668 int instance);
f2ba57b5
CK		 1669/*
1670 * UVD
1671 */
1672#define RADEON_MAX_UVD_HANDLES 10
1673#define RADEON_UVD_STACK_SIZE (1024*1024)
1674#define RADEON_UVD_HEAP_SIZE (1024*1024)
1675
1676struct radeon_uvd {
1677 struct radeon_bo *vcpu_bo;
1678 void *cpu_addr;
1679 uint64_t gpu_addr;
1680 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1681 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1682 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1683 struct delayed_work idle_work;
f2ba57b5
CK		 1684};
1685
1686int radeon_uvd_init(struct radeon_device *rdev);
1687void radeon_uvd_fini(struct radeon_device *rdev);
1688int radeon_uvd_suspend(struct radeon_device *rdev);
1689int radeon_uvd_resume(struct radeon_device *rdev);
1690int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1691 uint32_t handle, struct radeon_fence **fence);
1692int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1693 uint32_t handle, struct radeon_fence **fence);
3852752c
CK		 1694void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1695 uint32_t allowed_domains);
f2ba57b5
CK		 1696void radeon_uvd_free_handles(struct radeon_device *rdev,
1697 struct drm_file *filp);
1698int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1699void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1700int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1701 unsigned vclk, unsigned dclk,
1702 unsigned vco_min, unsigned vco_max,
1703 unsigned fb_factor, unsigned fb_mask,
1704 unsigned pd_min, unsigned pd_max,
1705 unsigned pd_even,
1706 unsigned *optimal_fb_div,
1707 unsigned *optimal_vclk_div,
1708 unsigned *optimal_dclk_div);
1709int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1710 unsigned cg_upll_func_cntl);
771fe6b9 1711
d93f7937
CK		 1712/*
1713 * VCE
1714 */
1715#define RADEON_MAX_VCE_HANDLES 16
d93f7937
CK		 1716
1717struct radeon_vce {
1718 struct radeon_bo *vcpu_bo;
d93f7937 1719 uint64_t gpu_addr;
98ccc291
CK		 1720 unsigned fw_version;
1721 unsigned fb_version;
d93f7937
CK		 1722 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1723 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
2fc5703a 1724 unsigned img_size[RADEON_MAX_VCE_HANDLES];
03afe6f6 1725 struct delayed_work idle_work;
a918efab 1726 uint32_t keyselect;
d93f7937
CK		 1727};
1728
1729int radeon_vce_init(struct radeon_device *rdev);
1730void radeon_vce_fini(struct radeon_device *rdev);
1731int radeon_vce_suspend(struct radeon_device *rdev);
1732int radeon_vce_resume(struct radeon_device *rdev);
1733int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1734 uint32_t handle, struct radeon_fence **fence);
1735int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1736 uint32_t handle, struct radeon_fence **fence);
1737void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
03afe6f6 1738void radeon_vce_note_usage(struct radeon_device *rdev);
2fc5703a 1739int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
d93f7937
CK		 1740int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1741bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1742 struct radeon_ring *ring,
1743 struct radeon_semaphore *semaphore,
1744 bool emit_wait);
1745void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1746void radeon_vce_fence_emit(struct radeon_device *rdev,
1747 struct radeon_fence *fence);
1748int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1749int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1750
b530602f 1751struct r600_audio_pin {
a92553ab
RM		 1752 int channels;
1753 int rate;
1754 int bits_per_sample;
1755 u8 status_bits;
1756 u8 category_code;
b530602f
AD		 1757 u32 offset;
1758 bool connected;
1759 u32 id;
1760};
1761
1762struct r600_audio {
1763 bool enabled;
1764 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1765 int num_pins;
1a626b68
SG		 1766 struct radeon_audio_funcs *hdmi_funcs;
1767 struct radeon_audio_funcs *dp_funcs;
1768 struct radeon_audio_basic_funcs *funcs;
a92553ab
RM		 1769};
1770
771fe6b9
JG		 1771/*
1772 * Benchmarking
1773 */
638dd7db 1774void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1775
1776
ecc0b326
MD		 1777/*
1778 * Testing
1779 */
1780void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1781void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1782 struct radeon_ring *cpA,
1783 struct radeon_ring *cpB);
60a7e396 1784void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326 1785
341cb9e4
CK		 1786/*
1787 * MMU Notifier
1788 */
5a1aa4b4 1789#if defined(CONFIG_MMU_NOTIFIER)
341cb9e4
CK		 1790int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1791void radeon_mn_unregister(struct radeon_bo *bo);
5a1aa4b4
RC		 1792#else
1793static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1794{
1795 return -ENODEV;
1796}
1797static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1798#endif
ecc0b326 1799
771fe6b9
JG		 1800/*
1801 * Debugfs
1802 */
4d8bf9ae
CK		 1803struct radeon_debugfs {
1804 struct drm_info_list *files;
1805 unsigned num_files;
1806};
1807
771fe6b9
JG		 1808int radeon_debugfs_add_files(struct radeon_device *rdev,
1809 struct drm_info_list *files,
1810 unsigned nfiles);
1811int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1812
76a0df85
CK		 1813/*
1814 * ASIC ring specific functions.
1815 */
1816struct radeon_asic_ring {
1817 /* ring read/write ptr handling */
1818 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1819 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1820 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1821
1822 /* validating and patching of IBs */
1823 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1824 int (*cs_parse)(struct radeon_cs_parser *p);
1825
1826 /* command emmit functions */
1827 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1828 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
72a9987e 1829 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1654b817 1830 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
76a0df85 1831 struct radeon_semaphore *semaphore, bool emit_wait);
faffaf62
CK		 1832 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1833 unsigned vm_id, uint64_t pd_addr);
76a0df85
CK		 1834
1835 /* testing functions */
1836 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1837 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1838 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1839
1840 /* deprecated */
1841 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1842};
771fe6b9
JG		 1843
1844/*
1845 * ASIC specific functions.
1846 */
1847struct radeon_asic {
068a117c 1848 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1849 void (*fini)(struct radeon_device *rdev);
1850 int (*resume)(struct radeon_device *rdev);
1851 int (*suspend)(struct radeon_device *rdev);
28d52043 1852 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1853 int (*asic_reset)(struct radeon_device *rdev);
124764f1
MD		 1854 /* Flush the HDP cache via MMIO */
1855 void (*mmio_hdp_flush)(struct radeon_device *rdev);
54e88e06
AD		 1856 /* check if 3D engine is idle */
1857 bool (*gui_idle)(struct radeon_device *rdev);
1858 /* wait for mc_idle */
1859 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1860 /* get the reference clock */
1861 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1862 /* get the gpu clock counter */
1863 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
4ce4728b
AD		 1864 /* get register for info ioctl */
1865 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
54e88e06 1866 /* gart */
c5b3b850
AD		 1867 struct {
1868 void (*tlb_flush)(struct radeon_device *rdev);
cb658906 1869 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
7f90fc96 1870 void (*set_page)(struct radeon_device *rdev, unsigned i,
cb658906 1871 uint64_t entry);
c5b3b850 1872 } gart;
05b07147
CK		 1873 struct {
1874 int (*init)(struct radeon_device *rdev);
1875 void (*fini)(struct radeon_device *rdev);
03f62abd
CK		 1876 void (*copy_pages)(struct radeon_device *rdev,
1877 struct radeon_ib *ib,
1878 uint64_t pe, uint64_t src,
1879 unsigned count);
1880 void (*write_pages)(struct radeon_device *rdev,
1881 struct radeon_ib *ib,
1882 uint64_t pe,
1883 uint64_t addr, unsigned count,
1884 uint32_t incr, uint32_t flags);
1885 void (*set_pages)(struct radeon_device *rdev,
1886 struct radeon_ib *ib,
1887 uint64_t pe,
1888 uint64_t addr, unsigned count,
1889 uint32_t incr, uint32_t flags);
1890 void (*pad_ib)(struct radeon_ib *ib);
05b07147 1891 } vm;
54e88e06 1892 /* ring specific callbacks */
d26678da 1893 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1894 /* irqs */
b35ea4ab
AD		 1895 struct {
1896 int (*set)(struct radeon_device *rdev);
1897 int (*process)(struct radeon_device *rdev);
1898 } irq;
54e88e06 1899 /* displays */
c79a49ca
AD		 1900 struct {
1901 /* display watermarks */
1902 void (*bandwidth_update)(struct radeon_device *rdev);
1903 /* get frame count */
1904 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1905 /* wait for vblank */
1906 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1907 /* set backlight level */
1908 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1909 /* get backlight level */
1910 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1911 /* audio callbacks */
1912 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1913 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1914 } display;
54e88e06 1915 /* copy functions for bo handling */
27cd7769 1916 struct {
57d20a43
CK		 1917 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1918 uint64_t src_offset,
1919 uint64_t dst_offset,
1920 unsigned num_gpu_pages,
1921 struct reservation_object *resv);
27cd7769 1922 u32 blit_ring_index;
57d20a43
CK		 1923 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1924 uint64_t src_offset,
1925 uint64_t dst_offset,
1926 unsigned num_gpu_pages,
1927 struct reservation_object *resv);
27cd7769
AD		 1928 u32 dma_ring_index;
1929 /* method used for bo copy */
57d20a43
CK		 1930 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1931 uint64_t src_offset,
1932 uint64_t dst_offset,
1933 unsigned num_gpu_pages,
1934 struct reservation_object *resv);
27cd7769
AD		 1935 /* ring used for bo copies */
1936 u32 copy_ring_index;
1937 } copy;
54e88e06 1938 /* surfaces */
9e6f3d02
AD		 1939 struct {
1940 int (*set_reg)(struct radeon_device *rdev, int reg,
1941 uint32_t tiling_flags, uint32_t pitch,
1942 uint32_t offset, uint32_t obj_size);
1943 void (*clear_reg)(struct radeon_device *rdev, int reg);
1944 } surface;
54e88e06 1945 /* hotplug detect */
901ea57d
AD		 1946 struct {
1947 void (*init)(struct radeon_device *rdev);
1948 void (*fini)(struct radeon_device *rdev);
1949 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1950 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1951 } hpd;
da321c8a 1952 /* static power management */
a02fa397
AD		 1953 struct {
1954 void (*misc)(struct radeon_device *rdev);
1955 void (*prepare)(struct radeon_device *rdev);
1956 void (*finish)(struct radeon_device *rdev);
1957 void (*init_profile)(struct radeon_device *rdev);
1958 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1959 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1960 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1961 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1962 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1963 int (*get_pcie_lanes)(struct radeon_device *rdev);
1964 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1965 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1966 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
b59b7333 1967 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
6bd1c385 1968 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1969 } pm;
da321c8a
AD		 1970 /* dynamic power management */
1971 struct {
1972 int (*init)(struct radeon_device *rdev);
1973 void (*setup_asic)(struct radeon_device *rdev);
1974 int (*enable)(struct radeon_device *rdev);
914a8987 1975 int (*late_enable)(struct radeon_device *rdev);
da321c8a 1976 void (*disable)(struct radeon_device *rdev);
84dd1928 1977 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1978 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1979 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1980 void (*display_configuration_changed)(struct radeon_device *rdev);
1981 void (*fini)(struct radeon_device *rdev);
1982 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1983 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1984 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1985 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1986 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1987 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1988 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1c71bda0 1989 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
a35a4b2b
OC		 1990 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
1991 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
1992 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
1993 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
d7dbce09
AD		 1994 u32 (*get_current_sclk)(struct radeon_device *rdev);
1995 u32 (*get_current_mclk)(struct radeon_device *rdev);
da321c8a 1996 } dpm;
6f34be50 1997 /* pageflipping */
0f9e006c 1998 struct {
157fa14d
CK		 1999 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
2000 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
0f9e006c 2001 } pflip;
771fe6b9
JG		 2002};
2003
21f9a437
JG		 2004/*
2005 * Asic structures
2006 */
551ebd83 2007struct r100_asic {
225758d8
JG		 2008 const unsigned *reg_safe_bm;
2009 unsigned reg_safe_bm_size;
2010 u32 hdp_cntl;
551ebd83
DA		 2011};
2012
21f9a437 2013struct r300_asic {
225758d8
JG		 2014 const unsigned *reg_safe_bm;
2015 unsigned reg_safe_bm_size;
2016 u32 resync_scratch;
2017 u32 hdp_cntl;
21f9a437
JG		 2018};
2019
2020struct r600_asic {
225758d8
JG		 2021 unsigned max_pipes;
2022 unsigned max_tile_pipes;
2023 unsigned max_simds;
2024 unsigned max_backends;
2025 unsigned max_gprs;
2026 unsigned max_threads;
2027 unsigned max_stack_entries;
2028 unsigned max_hw_contexts;
2029 unsigned max_gs_threads;
2030 unsigned sx_max_export_size;
2031 unsigned sx_max_export_pos_size;
2032 unsigned sx_max_export_smx_size;
2033 unsigned sq_num_cf_insts;
2034 unsigned tiling_nbanks;
2035 unsigned tiling_npipes;
2036 unsigned tiling_group_size;
e7aeeba6 2037 unsigned tile_config;
e55b9422 2038 unsigned backend_map;
65fcf668 2039 unsigned active_simds;
21f9a437
JG		 2040};
2041
2042struct rv770_asic {
225758d8
JG		 2043 unsigned max_pipes;
2044 unsigned max_tile_pipes;
2045 unsigned max_simds;
2046 unsigned max_backends;
2047 unsigned max_gprs;
2048 unsigned max_threads;
2049 unsigned max_stack_entries;
2050 unsigned max_hw_contexts;
2051 unsigned max_gs_threads;
2052 unsigned sx_max_export_size;
2053 unsigned sx_max_export_pos_size;
2054 unsigned sx_max_export_smx_size;
2055 unsigned sq_num_cf_insts;
2056 unsigned sx_num_of_sets;
2057 unsigned sc_prim_fifo_size;
2058 unsigned sc_hiz_tile_fifo_size;
2059 unsigned sc_earlyz_tile_fifo_fize;
2060 unsigned tiling_nbanks;
2061 unsigned tiling_npipes;
2062 unsigned tiling_group_size;
e7aeeba6 2063 unsigned tile_config;
e55b9422 2064 unsigned backend_map;
65fcf668 2065 unsigned active_simds;
21f9a437
JG		 2066};
2067
32fcdbf4
AD		 2068struct evergreen_asic {
2069 unsigned num_ses;
2070 unsigned max_pipes;
2071 unsigned max_tile_pipes;
2072 unsigned max_simds;
2073 unsigned max_backends;
2074 unsigned max_gprs;
2075 unsigned max_threads;
2076 unsigned max_stack_entries;
2077 unsigned max_hw_contexts;
2078 unsigned max_gs_threads;
2079 unsigned sx_max_export_size;
2080 unsigned sx_max_export_pos_size;
2081 unsigned sx_max_export_smx_size;
2082 unsigned sq_num_cf_insts;
2083 unsigned sx_num_of_sets;
2084 unsigned sc_prim_fifo_size;
2085 unsigned sc_hiz_tile_fifo_size;
2086 unsigned sc_earlyz_tile_fifo_size;
2087 unsigned tiling_nbanks;
2088 unsigned tiling_npipes;
2089 unsigned tiling_group_size;
e7aeeba6 2090 unsigned tile_config;
e55b9422 2091 unsigned backend_map;
65fcf668 2092 unsigned active_simds;
32fcdbf4
AD		 2093};
2094
fecf1d07
AD		 2095struct cayman_asic {
2096 unsigned max_shader_engines;
2097 unsigned max_pipes_per_simd;
2098 unsigned max_tile_pipes;
2099 unsigned max_simds_per_se;
2100 unsigned max_backends_per_se;
2101 unsigned max_texture_channel_caches;
2102 unsigned max_gprs;
2103 unsigned max_threads;
2104 unsigned max_gs_threads;
2105 unsigned max_stack_entries;
2106 unsigned sx_num_of_sets;
2107 unsigned sx_max_export_size;
2108 unsigned sx_max_export_pos_size;
2109 unsigned sx_max_export_smx_size;
2110 unsigned max_hw_contexts;
2111 unsigned sq_num_cf_insts;
2112 unsigned sc_prim_fifo_size;
2113 unsigned sc_hiz_tile_fifo_size;
2114 unsigned sc_earlyz_tile_fifo_size;
2115
2116 unsigned num_shader_engines;
2117 unsigned num_shader_pipes_per_simd;
2118 unsigned num_tile_pipes;
2119 unsigned num_simds_per_se;
2120 unsigned num_backends_per_se;
2121 unsigned backend_disable_mask_per_asic;
2122 unsigned backend_map;
2123 unsigned num_texture_channel_caches;
2124 unsigned mem_max_burst_length_bytes;
2125 unsigned mem_row_size_in_kb;
2126 unsigned shader_engine_tile_size;
2127 unsigned num_gpus;
2128 unsigned multi_gpu_tile_size;
2129
2130 unsigned tile_config;
65fcf668 2131 unsigned active_simds;
fecf1d07
AD		 2132};
2133
0a96d72b
AD		 2134struct si_asic {
2135 unsigned max_shader_engines;
0a96d72b 2136 unsigned max_tile_pipes;
1a8ca750
AD		 2137 unsigned max_cu_per_sh;
2138 unsigned max_sh_per_se;
0a96d72b
AD		 2139 unsigned max_backends_per_se;
2140 unsigned max_texture_channel_caches;
2141 unsigned max_gprs;
2142 unsigned max_gs_threads;
2143 unsigned max_hw_contexts;
2144 unsigned sc_prim_fifo_size_frontend;
2145 unsigned sc_prim_fifo_size_backend;
2146 unsigned sc_hiz_tile_fifo_size;
2147 unsigned sc_earlyz_tile_fifo_size;
2148
0a96d72b 2149 unsigned num_tile_pipes;
439a1cff 2150 unsigned backend_enable_mask;
0a96d72b
AD		 2151 unsigned backend_disable_mask_per_asic;
2152 unsigned backend_map;
2153 unsigned num_texture_channel_caches;
2154 unsigned mem_max_burst_length_bytes;
2155 unsigned mem_row_size_in_kb;
2156 unsigned shader_engine_tile_size;
2157 unsigned num_gpus;
2158 unsigned multi_gpu_tile_size;
2159
2160 unsigned tile_config;
64d7b8be 2161 uint32_t tile_mode_array[32];
65fcf668 2162 uint32_t active_cus;
0a96d72b
AD		 2163};
2164
8cc1a532
AD		 2165struct cik_asic {
2166 unsigned max_shader_engines;
2167 unsigned max_tile_pipes;
2168 unsigned max_cu_per_sh;
2169 unsigned max_sh_per_se;
2170 unsigned max_backends_per_se;
2171 unsigned max_texture_channel_caches;
2172 unsigned max_gprs;
2173 unsigned max_gs_threads;
2174 unsigned max_hw_contexts;
2175 unsigned sc_prim_fifo_size_frontend;
2176 unsigned sc_prim_fifo_size_backend;
2177 unsigned sc_hiz_tile_fifo_size;
2178 unsigned sc_earlyz_tile_fifo_size;
2179
2180 unsigned num_tile_pipes;
439a1cff 2181 unsigned backend_enable_mask;
8cc1a532
AD		 2182 unsigned backend_disable_mask_per_asic;
2183 unsigned backend_map;
2184 unsigned num_texture_channel_caches;
2185 unsigned mem_max_burst_length_bytes;
2186 unsigned mem_row_size_in_kb;
2187 unsigned shader_engine_tile_size;
2188 unsigned num_gpus;
2189 unsigned multi_gpu_tile_size;
2190
2191 unsigned tile_config;
39aee490 2192 uint32_t tile_mode_array[32];
32f79a8a 2193 uint32_t macrotile_mode_array[16];
65fcf668 2194 uint32_t active_cus;
8cc1a532
AD		 2195};
2196
068a117c
JG		 2197union radeon_asic_config {
2198 struct r300_asic r300;
551ebd83 2199 struct r100_asic r100;
3ce0a23d
JG		 2200 struct r600_asic r600;
2201 struct rv770_asic rv770;
32fcdbf4 2202 struct evergreen_asic evergreen;
fecf1d07 2203 struct cayman_asic cayman;
0a96d72b 2204 struct si_asic si;
8cc1a532 2205 struct cik_asic cik;
068a117c
JG		 2206};
2207
0a10c851
DV		 2208/*
2209 * asic initizalization from radeon_asic.c
2210 */
2211void radeon_agp_disable(struct radeon_device *rdev);
2212int radeon_asic_init(struct radeon_device *rdev);
2213
771fe6b9
JG		 2214
2215/*
2216 * IOCTL.
2217 */
2218int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2219 struct drm_file *filp);
2220int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2221 struct drm_file *filp);
f72a113a
CK		 2222int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2223 struct drm_file *filp);
771fe6b9
JG		 2224int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2225 struct drm_file *file_priv);
2226int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2227 struct drm_file *file_priv);
2228int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2229 struct drm_file *file_priv);
2230int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2231 struct drm_file *file_priv);
2232int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2233 struct drm_file *filp);
2234int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2235 struct drm_file *filp);
2236int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2237 struct drm_file *filp);
2238int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2239 struct drm_file *filp);
721604a1
JG		 2240int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2241 struct drm_file *filp);
bda72d58
MO		 2242int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2243 struct drm_file *filp);
771fe6b9 2244int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 2245int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2246 struct drm_file *filp);
2247int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2248 struct drm_file *filp);
771fe6b9 2249
16cdf04d
AD		 2250/* VRAM scratch page for HDP bug, default vram page */
2251struct r600_vram_scratch {
87cbf8f2
AD		 2252 struct radeon_bo *robj;
2253 volatile uint32_t *ptr;
16cdf04d 2254 u64 gpu_addr;
87cbf8f2 2255};
771fe6b9 2256
fd64ca8a
LT		 2257/*
2258 * ACPI
2259 */
2260struct radeon_atif_notification_cfg {
2261 bool enabled;
2262 int command_code;
2263};
2264
2265struct radeon_atif_notifications {
2266 bool display_switch;
2267 bool expansion_mode_change;
2268 bool thermal_state;
2269 bool forced_power_state;
2270 bool system_power_state;
2271 bool display_conf_change;
2272 bool px_gfx_switch;
2273 bool brightness_change;
2274 bool dgpu_display_event;
2275};
2276
2277struct radeon_atif_functions {
2278 bool system_params;
2279 bool sbios_requests;
2280 bool select_active_disp;
2281 bool lid_state;
2282 bool get_tv_standard;
2283 bool set_tv_standard;
2284 bool get_panel_expansion_mode;
2285 bool set_panel_expansion_mode;
2286 bool temperature_change;
2287 bool graphics_device_types;
2288};
2289
2290struct radeon_atif {
2291 struct radeon_atif_notifications notifications;
2292 struct radeon_atif_functions functions;
2293 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2294 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2295};
7a1619b9 2296
e3a15920
AD		 2297struct radeon_atcs_functions {
2298 bool get_ext_state;
2299 bool pcie_perf_req;
2300 bool pcie_dev_rdy;
2301 bool pcie_bus_width;
2302};
2303
2304struct radeon_atcs {
2305 struct radeon_atcs_functions functions;
2306};
2307
771fe6b9
JG		 2308/*
2309 * Core structure, functions and helpers.
2310 */
2311typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2312typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2313
2314struct radeon_device {
9f022ddf 2315 struct device *dev;
771fe6b9
JG		 2316 struct drm_device *ddev;
2317 struct pci_dev *pdev;
dee53e7f 2318 struct rw_semaphore exclusive_lock;
771fe6b9 2319 /* ASIC */
068a117c 2320 union radeon_asic_config config;
771fe6b9
JG		 2321 enum radeon_family family;
2322 unsigned long flags;
2323 int usec_timeout;
2324 enum radeon_pll_errata pll_errata;
2325 int num_gb_pipes;
f779b3e5 2326 int num_z_pipes;
771fe6b9
JG		 2327 int disp_priority;
2328 /* BIOS */
2329 uint8_t *bios;
2330 bool is_atom_bios;
2331 uint16_t bios_header_start;
4c788679 2332 struct radeon_bo *stollen_vga_memory;
771fe6b9 2333 /* Register mmio */
4c9bc75c
DA		 2334 resource_size_t rmmio_base;
2335 resource_size_t rmmio_size;
2c385151
DV		 2336 /* protects concurrent MM_INDEX/DATA based register access */
2337 spinlock_t mmio_idx_lock;
fe78118c
AD		 2338 /* protects concurrent SMC based register access */
2339 spinlock_t smc_idx_lock;
0a5b7b0b
AD		 2340 /* protects concurrent PLL register access */
2341 spinlock_t pll_idx_lock;
2342 /* protects concurrent MC register access */
2343 spinlock_t mc_idx_lock;
2344 /* protects concurrent PCIE register access */
2345 spinlock_t pcie_idx_lock;
2346 /* protects concurrent PCIE_PORT register access */
2347 spinlock_t pciep_idx_lock;
2348 /* protects concurrent PIF register access */
2349 spinlock_t pif_idx_lock;
2350 /* protects concurrent CG register access */
2351 spinlock_t cg_idx_lock;
2352 /* protects concurrent UVD register access */
2353 spinlock_t uvd_idx_lock;
2354 /* protects concurrent RCU register access */
2355 spinlock_t rcu_idx_lock;
2356 /* protects concurrent DIDT register access */
2357 spinlock_t didt_idx_lock;
2358 /* protects concurrent ENDPOINT (audio) register access */
2359 spinlock_t end_idx_lock;
a0533fbf 2360 void __iomem *rmmio;
771fe6b9
JG		 2361 radeon_rreg_t mc_rreg;
2362 radeon_wreg_t mc_wreg;
2363 radeon_rreg_t pll_rreg;
2364 radeon_wreg_t pll_wreg;
de1b2898 2365 uint32_t pcie_reg_mask;
771fe6b9
JG		 2366 radeon_rreg_t pciep_rreg;
2367 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2368 /* io port */
2369 void __iomem *rio_mem;
2370 resource_size_t rio_mem_size;
771fe6b9
JG		 2371 struct radeon_clock clock;
2372 struct radeon_mc mc;
2373 struct radeon_gart gart;
2374 struct radeon_mode_info mode_info;
2375 struct radeon_scratch scratch;
75efdee1 2376 struct radeon_doorbell doorbell;
771fe6b9 2377 struct radeon_mman mman;
7465280c 2378 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2379 wait_queue_head_t fence_queue;
954605ca 2380 unsigned fence_context;
d6999bc7 2381 struct mutex ring_lock;
e32eb50d 2382 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2383 bool ib_pool_ready;
2384 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2385 struct radeon_irq irq;
2386 struct radeon_asic *asic;
2387 struct radeon_gem gem;
c93bb85b 2388 struct radeon_pm pm;
f2ba57b5 2389 struct radeon_uvd uvd;
d93f7937 2390 struct radeon_vce vce;
f657c2a7 2391 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2392 struct radeon_wb wb;
3ce0a23d 2393 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2394 bool shutdown;
2395 bool suspend;
ad49f501 2396 bool need_dma32;
733289c2 2397 bool accel_working;
a0a53aa8 2398 bool fastfb_working; /* IGP feature*/
9bb39ff4 2399 bool needs_reset, in_reset;
e024e110 2400 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2401 const struct firmware *me_fw; /* all family ME firmware */
2402 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2403 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2404 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2405 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2406 const struct firmware *mec_fw; /* CIK MEC firmware */
f2c6b0f4 2407 const struct firmware *mec2_fw; /* KV MEC2 firmware */
21a93e13 2408 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2409 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2410 const struct firmware *uvd_fw; /* UVD firmware */
d93f7937 2411 const struct firmware *vce_fw; /* VCE firmware */
629bd33c 2412 bool new_fw;
16cdf04d 2413 struct r600_vram_scratch vram_scratch;
3e5cb98d 2414 int msi_enabled; /* msi enabled */
d8f60cfc 2415 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2416 struct radeon_rlc rlc;
963e81f9 2417 struct radeon_mec mec;
cb5d4166 2418 struct delayed_work hotplug_work;
de6284aa 2419 struct work_struct dp_work;
f122c610 2420 struct work_struct audio_work;
18917b60 2421 int num_crtc; /* number of crtcs */
40bacf16 2422 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
948bee3f 2423 bool has_uvd;
b530602f 2424 struct r600_audio audio; /* audio stuff */
ce8f5370 2425 struct notifier_block acpi_nb;
9eba4a93 2426 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2427 struct drm_file *hyperz_filp;
9eba4a93 2428 struct drm_file *cmask_filp;
f376b94f
AD		 2429 /* i2c buses */
2430 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2431 /* debugfs */
2432 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2433 unsigned debugfs_count;
721604a1
JG		 2434 /* virtual memory */
2435 struct radeon_vm_manager vm_manager;
6759a0a7 2436 struct mutex gpu_clock_mutex;
67e8e3f9
MO		 2437 /* memory stats */
2438 atomic64_t vram_usage;
2439 atomic64_t gtt_usage;
2440 atomic64_t num_bytes_moved;
72b9076b 2441 atomic_t gpu_reset_counter;
fd64ca8a
LT		 2442 /* ACPI interface */
2443 struct radeon_atif atif;
e3a15920 2444 struct radeon_atcs atcs;
f61d5b46
AD		 2445 /* srbm instance registers */
2446 struct mutex srbm_mutex;
1c0a4625
OG		 2447 /* GRBM index mutex. Protects concurrents access to GRBM index */
2448 struct mutex grbm_idx_mutex;
64d8a728
AD		 2449 /* clock, powergating flags */
2450 u32 cg_flags;
2451 u32 pg_flags;
10ebc0bc
DA		 2452
2453 struct dev_pm_domain vga_pm_domain;
2454 bool have_disp_power_ref;
4807c5a8 2455 u32 px_quirk_flags;
71ecc97e
AD		 2456
2457 /* tracking pinned memory */
2458 u64 vram_pin_size;
2459 u64 gart_pin_size;
341cb9e4 2460
e28740ec
OG		 2461 /* amdkfd interface */
2462 struct kfd_dev *kfd;
e28740ec 2463
341cb9e4
CK		 2464 struct mutex mn_lock;
2465 DECLARE_HASHTABLE(mn_hash, 7);
771fe6b9
JG		 2466};
2467
90c4cde9 2468bool radeon_is_px(struct drm_device *dev);
771fe6b9
JG		 2469int radeon_device_init(struct radeon_device *rdev,
2470 struct drm_device *ddev,
2471 struct pci_dev *pdev,
2472 uint32_t flags);
2473void radeon_device_fini(struct radeon_device *rdev);
2474int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2475
59bc1d89
LK		 2476#define RADEON_MIN_MMIO_SIZE 0x10000
2477
9e5acbc2
DV		 2478uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2479void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
59bc1d89
LK		 2480static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2481 bool always_indirect)
2482{
2483 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2484 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2485 return readl(((void __iomem *)rdev->rmmio) + reg);
9e5acbc2
DV		 2486 else
2487 return r100_mm_rreg_slow(rdev, reg);
59bc1d89 2488}
59bc1d89
LK		 2489static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2490 bool always_indirect)
2491{
2492 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2493 writel(v, ((void __iomem *)rdev->rmmio) + reg);
9e5acbc2
DV		 2494 else
2495 r100_mm_wreg_slow(rdev, reg, v);
59bc1d89
LK		 2496}
2497
6fcbef7a
AK		 2498u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2499void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2500
d5754ab8
AL		 2501u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2502void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
75efdee1 2503
4c788679
JG		 2504/*
2505 * Cast helper
2506 */
954605ca
ML		 2507extern const struct fence_ops radeon_fence_ops;
2508
2509static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2510{
2511 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2512
2513 if (__f->base.ops == &radeon_fence_ops)
2514 return __f;
2515
2516 return NULL;
2517}
771fe6b9
JG		 2518
2519/*
2520 * Registers read & write functions.
2521 */
a0533fbf
BH		 2522#define RREG8(reg) readb((rdev->rmmio) + (reg))
2523#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2524#define RREG16(reg) readw((rdev->rmmio) + (reg))
2525#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2526#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2527#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2528#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2529#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2530#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2531#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2532#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2533#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2534#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2535#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2536#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2537#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2538#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2539#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2540#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2541#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2542#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2543#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2544#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2545#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2546#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2547#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2548#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2549#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2550#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2551#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2552#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2553#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2554#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2555#define WREG32_P(reg, val, mask) \
2556 do { \
2557 uint32_t tmp_ = RREG32(reg); \
2558 tmp_ &= (mask); \
2559 tmp_ |= ((val) & ~(mask)); \
2560 WREG32(reg, tmp_); \
2561 } while (0)
d5169fc4 2562#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2563#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2564#define WREG32_PLL_P(reg, val, mask) \
2565 do { \
2566 uint32_t tmp_ = RREG32_PLL(reg); \
2567 tmp_ &= (mask); \
2568 tmp_ |= ((val) & ~(mask)); \
2569 WREG32_PLL(reg, tmp_); \
2570 } while (0)
b7af630c
CK		 2571#define WREG32_SMC_P(reg, val, mask) \
2572 do { \
2573 uint32_t tmp_ = RREG32_SMC(reg); \
2574 tmp_ &= (mask); \
2575 tmp_ |= ((val) & ~(mask)); \
2576 WREG32_SMC(reg, tmp_); \
2577 } while (0)
2ef9bdfe 2578#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2579#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2580#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2581
d5754ab8
AL		 2582#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2583#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
75efdee1 2584
de1b2898 2585/*
9e5acbc2
DV		 2586 * Indirect registers accessors.
2587 * They used to be inlined, but this increases code size by ~65 kbytes.
2588 * Since each performs a pair of MMIO ops
2589 * within a spin_lock_irqsave/spin_unlock_irqrestore region,
2590 * the cost of call+ret is almost negligible. MMIO and locking
2591 * costs several dozens of cycles each at best, call+ret is ~5 cycles.
de1b2898 2592 */
9e5acbc2
DV		 2593uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2594void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2595u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2596void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2597u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2598void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2599u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2600void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2601u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2602void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2603u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2604void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2605u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2606void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2607u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2608void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1d58234d 2609
771fe6b9
JG		 2610void r100_pll_errata_after_index(struct radeon_device *rdev);
2611
2612
2613/*
2614 * ASICs helpers.
2615 */
b995e433
DA		 2616#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2617 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2618#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2619 (rdev->family == CHIP_RV200) || \
2620 (rdev->family == CHIP_RS100) || \
2621 (rdev->family == CHIP_RS200) || \
2622 (rdev->family == CHIP_RV250) || \
2623 (rdev->family == CHIP_RV280) || \
2624 (rdev->family == CHIP_RS300))
2625#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2626 (rdev->family == CHIP_RV350) || \
2627 (rdev->family == CHIP_R350) || \
2628 (rdev->family == CHIP_RV380) || \
2629 (rdev->family == CHIP_R420) || \
2630 (rdev->family == CHIP_R423) || \
2631 (rdev->family == CHIP_RV410) || \
2632 (rdev->family == CHIP_RS400) || \
2633 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2634#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2635 (rdev->ddev->pdev->device == 0x9443) || \
2636 (rdev->ddev->pdev->device == 0x944B) || \
2637 (rdev->ddev->pdev->device == 0x9506) || \
2638 (rdev->ddev->pdev->device == 0x9509) || \
2639 (rdev->ddev->pdev->device == 0x950F) || \
2640 (rdev->ddev->pdev->device == 0x689C) || \
2641 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2642#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2643#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2644 (rdev->family == CHIP_RS690) || \
2645 (rdev->family == CHIP_RS740) || \
2646 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2647#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2648#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2649#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2650#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2651 (rdev->flags & RADEON_IS_IGP))
1fe18305 2652#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2653#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2654#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2655 (rdev->flags & RADEON_IS_IGP))
624d3524 2656#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2657#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2658#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
be0949f5
AD		 2659#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2660#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
89d2618d
AD		 2661#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2662 (rdev->family == CHIP_MULLINS))
771fe6b9 2663
dc50ba7f
AD		 2664#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2665 (rdev->ddev->pdev->device == 0x6850) || \
2666 (rdev->ddev->pdev->device == 0x6858) || \
2667 (rdev->ddev->pdev->device == 0x6859) || \
2668 (rdev->ddev->pdev->device == 0x6840) || \
2669 (rdev->ddev->pdev->device == 0x6841) || \
2670 (rdev->ddev->pdev->device == 0x6842) || \
2671 (rdev->ddev->pdev->device == 0x6843))
2672
771fe6b9
JG		 2673/*
2674 * BIOS helpers.
2675 */
2676#define RBIOS8(i) (rdev->bios[i])
2677#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2678#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2679
2680int radeon_combios_init(struct radeon_device *rdev);
2681void radeon_combios_fini(struct radeon_device *rdev);
2682int radeon_atombios_init(struct radeon_device *rdev);
2683void radeon_atombios_fini(struct radeon_device *rdev);
2684
2685
2686/*
2687 * RING helpers.
2688 */
edf0ac7c
DH		 2689
2690/**
2691 * radeon_ring_write - write a value to the ring
2692 *
2693 * @ring: radeon_ring structure holding ring information
2694 * @v: dword (dw) value to write
2695 *
2696 * Write a value to the requested ring buffer (all asics).
2697 */
e32eb50d 2698static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2699{
edf0ac7c
DH		 2700 if (ring->count_dw <= 0)
2701 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2702
e32eb50d
CK		 2703 ring->ring[ring->wptr++] = v;
2704 ring->wptr &= ring->ptr_mask;
2705 ring->count_dw--;
2706 ring->ring_free_dw--;
771fe6b9 2707}
771fe6b9
JG		 2708
2709/*
2710 * ASICs macro.
2711 */
068a117c 2712#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2713#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2714#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2715#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2716#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2717#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2718#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850 2719#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
cb658906
MD		 2720#define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2721#define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
05b07147
CK		 2722#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2723#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
03f62abd
CK		 2724#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2725#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2726#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2727#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
76a0df85
CK		 2728#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2729#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2730#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2731#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2732#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2733#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
faffaf62 2734#define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
76a0df85
CK		 2735#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2736#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2737#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2738#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2739#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2740#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2741#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2742#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2743#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2744#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2745#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2746#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
57d20a43
CK		 2747#define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2748#define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2749#define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
27cd7769
AD		 2750#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2751#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2752#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2753#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2754#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2755#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2756#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2757#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2758#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2759#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2760#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
b59b7333 2761#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
6bd1c385 2762#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2763#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2764#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2765#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2766#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2767#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2768#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2769#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2770#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2771#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2772#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2773#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2774#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2775#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8 2776#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
157fa14d 2777#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
69b62ad8
AD		 2778#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2779#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2780#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2781#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
4ce4728b 2782#define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
da321c8a
AD		 2783#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2784#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2785#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
914a8987 2786#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
da321c8a 2787#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2788#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2789#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2790#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2791#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2792#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2793#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2794#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2795#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2796#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2797#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2798#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2799#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
1c71bda0 2800#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
d7dbce09
AD		 2801#define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2802#define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
771fe6b9 2803
6cf8a3f5 2804/* Common functions */
700a0cc0 2805/* AGP */
90aca4d2 2806extern int radeon_gpu_reset(struct radeon_device *rdev);
1a0041b8 2807extern void radeon_pci_config_reset(struct radeon_device *rdev);
410a3418 2808extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2809extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2810extern int radeon_modeset_init(struct radeon_device *rdev);
2811extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2812extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2813extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2814extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2815extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2816extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2817extern void radeon_wb_fini(struct radeon_device *rdev);
2818extern int radeon_wb_init(struct radeon_device *rdev);
2819extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2820extern void radeon_surface_init(struct radeon_device *rdev);
2821extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2822extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2823extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2824extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2825extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
f72a113a
CK		 2826extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2827 uint32_t flags);
2828extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2829extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
d594e46a
JG		 2830extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2831extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
10ebc0bc
DA		 2832extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2833extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
53595338 2834extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2835extern void radeon_program_register_sequence(struct radeon_device *rdev,
2836 const u32 *registers,
2837 const u32 array_size);
6cf8a3f5 2838
721604a1
JG		 2839/*
2840 * vm
2841 */
2842int radeon_vm_manager_init(struct radeon_device *rdev);
2843void radeon_vm_manager_fini(struct radeon_device *rdev);
6d2f2944 2844int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2845void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1d0c0942 2846struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
df0af440
CK		 2847 struct radeon_vm *vm,
2848 struct list_head *head);
ee60e29f
CK		 2849struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2850 struct radeon_vm *vm, int ring);
fa688343
CK		 2851void radeon_vm_flush(struct radeon_device *rdev,
2852 struct radeon_vm *vm,
ad1a58a4 2853 int ring, struct radeon_fence *fence);
ee60e29f
CK		 2854void radeon_vm_fence(struct radeon_device *rdev,
2855 struct radeon_vm *vm,
2856 struct radeon_fence *fence);
dce34bfd 2857uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
6d2f2944
CK		 2858int radeon_vm_update_page_directory(struct radeon_device *rdev,
2859 struct radeon_vm *vm);
036bf46a
CK		 2860int radeon_vm_clear_freed(struct radeon_device *rdev,
2861 struct radeon_vm *vm);
e31ad969
CK		 2862int radeon_vm_clear_invalids(struct radeon_device *rdev,
2863 struct radeon_vm *vm);
9c57a6bd 2864int radeon_vm_bo_update(struct radeon_device *rdev,
036bf46a 2865 struct radeon_bo_va *bo_va,
9c57a6bd 2866 struct ttm_mem_reg *mem);
721604a1
JG		 2867void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2868 struct radeon_bo *bo);
421ca7ab
CK		 2869struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2870 struct radeon_bo *bo);
e971bd5e
CK		 2871struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2872 struct radeon_vm *vm,
2873 struct radeon_bo *bo);
2874int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2875 struct radeon_bo_va *bo_va,
2876 uint64_t offset,
2877 uint32_t flags);
036bf46a
CK		 2878void radeon_vm_bo_rmv(struct radeon_device *rdev,
2879 struct radeon_bo_va *bo_va);
721604a1 2880
f122c610
AD		 2881/* audio */
2882void r600_audio_update_hdmi(struct work_struct *work);
b530602f
AD		 2883struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2884struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
832eafaf
AD		 2885void r600_audio_enable(struct radeon_device *rdev,
2886 struct r600_audio_pin *pin,
d3d8c141 2887 u8 enable_mask);
832eafaf
AD		 2888void dce6_audio_enable(struct radeon_device *rdev,
2889 struct r600_audio_pin *pin,
d3d8c141 2890 u8 enable_mask);
721604a1 2891
16cdf04d
AD		 2892/*
2893 * R600 vram scratch functions
2894 */
2895int r600_vram_scratch_init(struct radeon_device *rdev);
2896void r600_vram_scratch_fini(struct radeon_device *rdev);
2897
285484e2
JG		 2898/*
2899 * r600 cs checking helper
2900 */
2901unsigned r600_mip_minify(unsigned size, unsigned level);
2902bool r600_fmt_is_valid_color(u32 format);
2903bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2904int r600_fmt_get_blocksize(u32 format);
2905int r600_fmt_get_nblocksx(u32 format, u32 w);
2906int r600_fmt_get_nblocksy(u32 format, u32 h);
2907
3574dda4
DV		 2908/*
2909 * r600 functions used by radeon_encoder.c
2910 */
1b688d08
RM		 2911struct radeon_hdmi_acr {
2912 u32 clock;
2913
2914 int n_32khz;
2915 int cts_32khz;
2916
2917 int n_44_1khz;
2918 int cts_44_1khz;
2919
2920 int n_48khz;
2921 int cts_48khz;
2922
2923};
2924
e55d3e6c
RM		 2925extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2926
416a2bd2
AD		 2927extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2928 u32 tiling_pipe_num,
2929 u32 max_rb_num,
2930 u32 total_max_rb_num,
2931 u32 enabled_rb_mask);
fe251e2f 2932
e55d3e6c
RM		 2933/*
2934 * evergreen functions used by radeon_encoder.c
2935 */
2936
0af62b01 2937extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2938extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2939
c4917074
AD		 2940/* radeon_acpi.c */
2941#if defined(CONFIG_ACPI)
2942extern int radeon_acpi_init(struct radeon_device *rdev);
2943extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2944extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2945extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2946 u8 perf_req, bool advertise);
dc50ba7f 2947extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2948#else
2949static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2950static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2951#endif
d7a2952f 2952
c38f34b5
IH		 2953int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2954 struct radeon_cs_packet *pkt,
2955 unsigned idx);
9ffb7a6d 2956bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2957void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2958 struct radeon_cs_packet *pkt);
e9716993 2959int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
1d0c0942 2960 struct radeon_bo_list **cs_reloc,
e9716993 2961 int nomm);
40592a17
IH		 2962int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2963 uint32_t *vline_start_end,
2964 uint32_t *vline_status);
c38f34b5 2965
4c788679
JG		 2966#include "radeon_object.h"
2967
771fe6b9 2968#endif
Linux kernel - Deliverables
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