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drm/radeon/kms: add support for CP setup on cayman asics
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
771fe6b9
JG		 63#include <asm/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
771fe6b9
JG		 96
97/*
98 * Copy from radeon_drv.h so we don't have to include both and have conflicting
99 * symbol;
100 */
101#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
225758d8 102#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 103/* RADEON_IB_POOL_SIZE must be a power of 2 */
771fe6b9
JG		 104#define RADEON_IB_POOL_SIZE 16
105#define RADEON_DEBUGFS_MAX_NUM_FILES 32
106#define RADEONFB_CONN_LIMIT 4
f657c2a7 107#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 108
771fe6b9
JG		 109/*
110 * Errata workarounds.
111 */
112enum radeon_pll_errata {
113 CHIP_ERRATA_R300_CG = 0x00000001,
114 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
115 CHIP_ERRATA_PLL_DELAY = 0x00000004
116};
117
118
119struct radeon_device;
120
121
122/*
123 * BIOS.
124 */
6a9ee8af
DA		 125#define ATRM_BIOS_PAGE 4096
126
8edb381d 127#if defined(CONFIG_VGA_SWITCHEROO)
6a9ee8af
DA		 128bool radeon_atrm_supported(struct pci_dev *pdev);
129int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
8edb381d
DA		 130#else
131static inline bool radeon_atrm_supported(struct pci_dev *pdev)
132{
133 return false;
134}
135
136static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
137 return -EINVAL;
138}
139#endif
771fe6b9
JG		 140bool radeon_get_bios(struct radeon_device *rdev);
141
3ce0a23d 142
771fe6b9 143/*
3ce0a23d 144 * Dummy page
771fe6b9 145 */
3ce0a23d
JG		 146struct radeon_dummy_page {
147 struct page *page;
148 dma_addr_t addr;
149};
150int radeon_dummy_page_init(struct radeon_device *rdev);
151void radeon_dummy_page_fini(struct radeon_device *rdev);
152
771fe6b9 153
3ce0a23d
JG		 154/*
155 * Clocks
156 */
771fe6b9
JG		 157struct radeon_clock {
158 struct radeon_pll p1pll;
159 struct radeon_pll p2pll;
bcc1c2a1 160 struct radeon_pll dcpll;
771fe6b9
JG		 161 struct radeon_pll spll;
162 struct radeon_pll mpll;
163 /* 10 Khz units */
164 uint32_t default_mclk;
165 uint32_t default_sclk;
bcc1c2a1
AD		 166 uint32_t default_dispclk;
167 uint32_t dp_extclk;
771fe6b9
JG		 168};
169
7433874e
RM		 170/*
171 * Power management
172 */
173int radeon_pm_init(struct radeon_device *rdev);
29fb52ca 174void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 175void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 176void radeon_pm_suspend(struct radeon_device *rdev);
177void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 178void radeon_combios_get_power_modes(struct radeon_device *rdev);
179void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7ac9aa5a 180void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level);
f892034a 181void rs690_pm_info(struct radeon_device *rdev);
20d391d7
AD		 182extern int rv6xx_get_temp(struct radeon_device *rdev);
183extern int rv770_get_temp(struct radeon_device *rdev);
184extern int evergreen_get_temp(struct radeon_device *rdev);
185extern int sumo_get_temp(struct radeon_device *rdev);
3ce0a23d 186
771fe6b9
JG		 187/*
188 * Fences.
189 */
190struct radeon_fence_driver {
191 uint32_t scratch_reg;
192 atomic_t seq;
193 uint32_t last_seq;
225758d8
JG		 194 unsigned long last_jiffies;
195 unsigned long last_timeout;
771fe6b9
JG		 196 wait_queue_head_t queue;
197 rwlock_t lock;
198 struct list_head created;
199 struct list_head emited;
200 struct list_head signaled;
0a0c7596 201 bool initialized;
771fe6b9
JG		 202};
203
204struct radeon_fence {
205 struct radeon_device *rdev;
206 struct kref kref;
207 struct list_head list;
208 /* protected by radeon_fence.lock */
209 uint32_t seq;
771fe6b9
JG		 210 bool emited;
211 bool signaled;
212};
213
214int radeon_fence_driver_init(struct radeon_device *rdev);
215void radeon_fence_driver_fini(struct radeon_device *rdev);
216int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
217int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
218void radeon_fence_process(struct radeon_device *rdev);
219bool radeon_fence_signaled(struct radeon_fence *fence);
220int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
221int radeon_fence_wait_next(struct radeon_device *rdev);
222int radeon_fence_wait_last(struct radeon_device *rdev);
223struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
224void radeon_fence_unref(struct radeon_fence **fence);
225
e024e110
DA		 226/*
227 * Tiling registers
228 */
229struct radeon_surface_reg {
4c788679 230 struct radeon_bo *bo;
e024e110
DA		 231};
232
233#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 234
235/*
4c788679 236 * TTM.
771fe6b9 237 */
4c788679
JG		 238struct radeon_mman {
239 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 240 struct drm_global_reference mem_global_ref;
4c788679 241 struct ttm_bo_device bdev;
0a0c7596
JG		 242 bool mem_global_referenced;
243 bool initialized;
4c788679
JG		 244};
245
246struct radeon_bo {
247 /* Protected by gem.mutex */
248 struct list_head list;
249 /* Protected by tbo.reserved */
312ea8da
JG		 250 u32 placements[3];
251 struct ttm_placement placement;
4c788679
JG		 252 struct ttm_buffer_object tbo;
253 struct ttm_bo_kmap_obj kmap;
254 unsigned pin_count;
255 void *kptr;
256 u32 tiling_flags;
257 u32 pitch;
258 int surface_reg;
259 /* Constant after initialization */
260 struct radeon_device *rdev;
441921d5 261 struct drm_gem_object gem_base;
4c788679 262};
7e4d15d9 263#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 264
4c788679 265struct radeon_bo_list {
147666fb 266 struct ttm_validate_buffer tv;
4c788679 267 struct radeon_bo *bo;
771fe6b9
JG		 268 uint64_t gpu_offset;
269 unsigned rdomain;
270 unsigned wdomain;
4c788679 271 u32 tiling_flags;
771fe6b9
JG		 272};
273
771fe6b9
JG		 274/*
275 * GEM objects.
276 */
277struct radeon_gem {
4c788679 278 struct mutex mutex;
771fe6b9
JG		 279 struct list_head objects;
280};
281
282int radeon_gem_init(struct radeon_device *rdev);
283void radeon_gem_fini(struct radeon_device *rdev);
284int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 285 int alignment, int initial_domain,
286 bool discardable, bool kernel,
287 struct drm_gem_object **obj);
771fe6b9
JG		 288int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
289 uint64_t *gpu_addr);
290void radeon_gem_object_unpin(struct drm_gem_object *obj);
291
ff72145b
DA		 292int radeon_mode_dumb_create(struct drm_file *file_priv,
293 struct drm_device *dev,
294 struct drm_mode_create_dumb *args);
295int radeon_mode_dumb_mmap(struct drm_file *filp,
296 struct drm_device *dev,
297 uint32_t handle, uint64_t *offset_p);
298int radeon_mode_dumb_destroy(struct drm_file *file_priv,
299 struct drm_device *dev,
300 uint32_t handle);
771fe6b9
JG		 301
302/*
303 * GART structures, functions & helpers
304 */
305struct radeon_mc;
306
307struct radeon_gart_table_ram {
308 volatile uint32_t *ptr;
309};
310
311struct radeon_gart_table_vram {
4c788679 312 struct radeon_bo *robj;
771fe6b9
JG		 313 volatile uint32_t *ptr;
314};
315
316union radeon_gart_table {
317 struct radeon_gart_table_ram ram;
318 struct radeon_gart_table_vram vram;
319};
320
a77f1718 321#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 322#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
a77f1718 323
771fe6b9
JG		 324struct radeon_gart {
325 dma_addr_t table_addr;
326 unsigned num_gpu_pages;
327 unsigned num_cpu_pages;
328 unsigned table_size;
329 union radeon_gart_table table;
330 struct page **pages;
331 dma_addr_t *pages_addr;
c39d3516 332 bool *ttm_alloced;
771fe6b9
JG		 333 bool ready;
334};
335
336int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
337void radeon_gart_table_ram_free(struct radeon_device *rdev);
338int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
339void radeon_gart_table_vram_free(struct radeon_device *rdev);
340int radeon_gart_init(struct radeon_device *rdev);
341void radeon_gart_fini(struct radeon_device *rdev);
342void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
343 int pages);
344int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516
KRW		 345 int pages, struct page **pagelist,
346 dma_addr_t *dma_addr);
771fe6b9
JG		 347
348
349/*
350 * GPU MC structures, functions & helpers
351 */
352struct radeon_mc {
353 resource_size_t aper_size;
354 resource_size_t aper_base;
355 resource_size_t agp_base;
7a50f01a
DA		 356 /* for some chips with <= 32MB we need to lie
357 * about vram size near mc fb location */
3ce0a23d 358 u64 mc_vram_size;
d594e46a 359 u64 visible_vram_size;
c919b371 360 u64 active_vram_size;
3ce0a23d
JG		 361 u64 gtt_size;
362 u64 gtt_start;
363 u64 gtt_end;
3ce0a23d
JG		 364 u64 vram_start;
365 u64 vram_end;
771fe6b9 366 unsigned vram_width;
3ce0a23d 367 u64 real_vram_size;
771fe6b9
JG		 368 int vram_mtrr;
369 bool vram_is_ddr;
d594e46a 370 bool igp_sideport_enabled;
8d369bb1 371 u64 gtt_base_align;
771fe6b9
JG		 372};
373
06b6476d
AD		 374bool radeon_combios_sideport_present(struct radeon_device *rdev);
375bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 376
377/*
378 * GPU scratch registers structures, functions & helpers
379 */
380struct radeon_scratch {
381 unsigned num_reg;
724c80e1 382 uint32_t reg_base;
771fe6b9
JG		 383 bool free[32];
384 uint32_t reg[32];
385};
386
387int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
388void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
389
390
391/*
392 * IRQS.
393 */
6f34be50
AD		 394
395struct radeon_unpin_work {
396 struct work_struct work;
397 struct radeon_device *rdev;
398 int crtc_id;
399 struct radeon_fence *fence;
400 struct drm_pending_vblank_event *event;
401 struct radeon_bo *old_rbo;
402 u64 new_crtc_base;
403};
404
405struct r500_irq_stat_regs {
406 u32 disp_int;
407};
408
409struct r600_irq_stat_regs {
410 u32 disp_int;
411 u32 disp_int_cont;
412 u32 disp_int_cont2;
413 u32 d1grph_int;
414 u32 d2grph_int;
415};
416
417struct evergreen_irq_stat_regs {
418 u32 disp_int;
419 u32 disp_int_cont;
420 u32 disp_int_cont2;
421 u32 disp_int_cont3;
422 u32 disp_int_cont4;
423 u32 disp_int_cont5;
424 u32 d1grph_int;
425 u32 d2grph_int;
426 u32 d3grph_int;
427 u32 d4grph_int;
428 u32 d5grph_int;
429 u32 d6grph_int;
430};
431
432union radeon_irq_stat_regs {
433 struct r500_irq_stat_regs r500;
434 struct r600_irq_stat_regs r600;
435 struct evergreen_irq_stat_regs evergreen;
436};
437
771fe6b9
JG		 438struct radeon_irq {
439 bool installed;
440 bool sw_int;
441 /* FIXME: use a define max crtc rather than hardcode it */
45f9a39b 442 bool crtc_vblank_int[6];
6f34be50 443 bool pflip[6];
73a6d3fc 444 wait_queue_head_t vblank_queue;
b500f680
AD		 445 /* FIXME: use defines for max hpd/dacs */
446 bool hpd[6];
2031f77c
AD		 447 bool gui_idle;
448 bool gui_idle_acked;
449 wait_queue_head_t idle_queue;
f2594933
CK		 450 /* FIXME: use defines for max HDMI blocks */
451 bool hdmi[2];
1614f8b1
DA		 452 spinlock_t sw_lock;
453 int sw_refcount;
6f34be50
AD		 454 union radeon_irq_stat_regs stat_regs;
455 spinlock_t pflip_lock[6];
456 int pflip_refcount[6];
771fe6b9
JG		 457};
458
459int radeon_irq_kms_init(struct radeon_device *rdev);
460void radeon_irq_kms_fini(struct radeon_device *rdev);
1614f8b1
DA		 461void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
462void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
6f34be50
AD		 463void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
464void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 465
466/*
467 * CP & ring.
468 */
469struct radeon_ib {
470 struct list_head list;
e821767b 471 unsigned idx;
771fe6b9
JG		 472 uint64_t gpu_addr;
473 struct radeon_fence *fence;
e821767b 474 uint32_t *ptr;
771fe6b9 475 uint32_t length_dw;
e821767b 476 bool free;
771fe6b9
JG		 477};
478
ecb114a1
DA		 479/*
480 * locking -
481 * mutex protects scheduled_ibs, ready, alloc_bm
482 */
771fe6b9
JG		 483struct radeon_ib_pool {
484 struct mutex mutex;
4c788679 485 struct radeon_bo *robj;
9f93ed39 486 struct list_head bogus_ib;
771fe6b9
JG		 487 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
488 bool ready;
e821767b 489 unsigned head_id;
771fe6b9
JG		 490};
491
492struct radeon_cp {
4c788679 493 struct radeon_bo *ring_obj;
771fe6b9
JG		 494 volatile uint32_t *ring;
495 unsigned rptr;
496 unsigned wptr;
497 unsigned wptr_old;
498 unsigned ring_size;
499 unsigned ring_free_dw;
500 int count_dw;
501 uint64_t gpu_addr;
502 uint32_t align_mask;
503 uint32_t ptr_mask;
504 struct mutex mutex;
505 bool ready;
506};
507
d8f60cfc
AD		 508/*
509 * R6xx+ IH ring
510 */
511struct r600_ih {
4c788679 512 struct radeon_bo *ring_obj;
d8f60cfc
AD		 513 volatile uint32_t *ring;
514 unsigned rptr;
515 unsigned wptr;
516 unsigned wptr_old;
517 unsigned ring_size;
518 uint64_t gpu_addr;
d8f60cfc
AD		 519 uint32_t ptr_mask;
520 spinlock_t lock;
521 bool enabled;
522};
523
3ce0a23d 524struct r600_blit {
ff82f052 525 struct mutex mutex;
4c788679 526 struct radeon_bo *shader_obj;
3ce0a23d
JG		 527 u64 shader_gpu_addr;
528 u32 vs_offset, ps_offset;
529 u32 state_offset;
530 u32 state_len;
531 u32 vb_used, vb_total;
532 struct radeon_ib *vb_ib;
533};
534
771fe6b9
JG		 535int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
536void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
537int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
538int radeon_ib_pool_init(struct radeon_device *rdev);
539void radeon_ib_pool_fini(struct radeon_device *rdev);
540int radeon_ib_test(struct radeon_device *rdev);
9f93ed39 541extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
771fe6b9
JG		 542/* Ring access between begin & end cannot sleep */
543void radeon_ring_free_size(struct radeon_device *rdev);
91700f3c 544int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
771fe6b9 545int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
91700f3c 546void radeon_ring_commit(struct radeon_device *rdev);
771fe6b9
JG		 547void radeon_ring_unlock_commit(struct radeon_device *rdev);
548void radeon_ring_unlock_undo(struct radeon_device *rdev);
549int radeon_ring_test(struct radeon_device *rdev);
550int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
551void radeon_ring_fini(struct radeon_device *rdev);
552
553
554/*
555 * CS.
556 */
557struct radeon_cs_reloc {
558 struct drm_gem_object *gobj;
4c788679
JG		 559 struct radeon_bo *robj;
560 struct radeon_bo_list lobj;
771fe6b9
JG		 561 uint32_t handle;
562 uint32_t flags;
563};
564
565struct radeon_cs_chunk {
566 uint32_t chunk_id;
567 uint32_t length_dw;
513bcb46
DA		 568 int kpage_idx[2];
569 uint32_t *kpage[2];
771fe6b9 570 uint32_t *kdata;
513bcb46
DA		 571 void __user *user_ptr;
572 int last_copied_page;
573 int last_page_index;
771fe6b9
JG		 574};
575
576struct radeon_cs_parser {
c8c15ff1 577 struct device *dev;
771fe6b9
JG		 578 struct radeon_device *rdev;
579 struct drm_file *filp;
580 /* chunks */
581 unsigned nchunks;
582 struct radeon_cs_chunk *chunks;
583 uint64_t *chunks_array;
584 /* IB */
585 unsigned idx;
586 /* relocations */
587 unsigned nrelocs;
588 struct radeon_cs_reloc *relocs;
589 struct radeon_cs_reloc **relocs_ptr;
590 struct list_head validated;
591 /* indices of various chunks */
592 int chunk_ib_idx;
593 int chunk_relocs_idx;
594 struct radeon_ib *ib;
595 void *track;
3ce0a23d 596 unsigned family;
513bcb46 597 int parser_error;
771fe6b9
JG		 598};
599
513bcb46
DA		 600extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
601extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
602
603
604static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
605{
606 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
607 u32 pg_idx, pg_offset;
608 u32 idx_value = 0;
609 int new_page;
610
611 pg_idx = (idx * 4) / PAGE_SIZE;
612 pg_offset = (idx * 4) % PAGE_SIZE;
613
614 if (ibc->kpage_idx[0] == pg_idx)
615 return ibc->kpage[0][pg_offset/4];
616 if (ibc->kpage_idx[1] == pg_idx)
617 return ibc->kpage[1][pg_offset/4];
618
619 new_page = radeon_cs_update_pages(p, pg_idx);
620 if (new_page < 0) {
621 p->parser_error = new_page;
622 return 0;
623 }
624
625 idx_value = ibc->kpage[new_page][pg_offset/4];
626 return idx_value;
627}
628
771fe6b9
JG		 629struct radeon_cs_packet {
630 unsigned idx;
631 unsigned type;
632 unsigned reg;
633 unsigned opcode;
634 int count;
635 unsigned one_reg_wr;
636};
637
638typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
639 struct radeon_cs_packet *pkt,
640 unsigned idx, unsigned reg);
641typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
642 struct radeon_cs_packet *pkt);
643
644
645/*
646 * AGP
647 */
648int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 649void radeon_agp_resume(struct radeon_device *rdev);
10b06122 650void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 651void radeon_agp_fini(struct radeon_device *rdev);
652
653
654/*
655 * Writeback
656 */
657struct radeon_wb {
4c788679 658 struct radeon_bo *wb_obj;
771fe6b9
JG		 659 volatile uint32_t *wb;
660 uint64_t gpu_addr;
724c80e1 661 bool enabled;
d0f8a854 662 bool use_event;
771fe6b9
JG		 663};
664
724c80e1
AD		 665#define RADEON_WB_SCRATCH_OFFSET 0
666#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 667#define RADEON_WB_CP1_RPTR_OFFSET 1280
668#define RADEON_WB_CP2_RPTR_OFFSET 1536
724c80e1 669#define R600_WB_IH_WPTR_OFFSET 2048
d0f8a854 670#define R600_WB_EVENT_OFFSET 3072
724c80e1 671
c93bb85b
JG		 672/**
673 * struct radeon_pm - power management datas
674 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
675 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
676 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
677 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
678 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
679 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
680 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
681 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
682 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
683 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
684 * @needed_bandwidth: current bandwidth needs
685 *
686 * It keeps track of various data needed to take powermanagement decision.
687 * Bandwith need is used to determine minimun clock of the GPU and memory.
688 * Equation between gpu/memory clock and available bandwidth is hw dependent
689 * (type of memory, bus size, efficiency, ...)
690 */
ce8f5370
AD		 691
692enum radeon_pm_method {
693 PM_METHOD_PROFILE,
694 PM_METHOD_DYNPM,
695};
696
697enum radeon_dynpm_state {
698 DYNPM_STATE_DISABLED,
699 DYNPM_STATE_MINIMUM,
700 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 701 DYNPM_STATE_ACTIVE,
702 DYNPM_STATE_SUSPENDED,
c913e23a 703};
ce8f5370
AD		 704enum radeon_dynpm_action {
705 DYNPM_ACTION_NONE,
706 DYNPM_ACTION_MINIMUM,
707 DYNPM_ACTION_DOWNCLOCK,
708 DYNPM_ACTION_UPCLOCK,
709 DYNPM_ACTION_DEFAULT
c913e23a 710};
56278a8e
AD		 711
712enum radeon_voltage_type {
713 VOLTAGE_NONE = 0,
714 VOLTAGE_GPIO,
715 VOLTAGE_VDDC,
716 VOLTAGE_SW
717};
718
0ec0e74f
AD		 719enum radeon_pm_state_type {
720 POWER_STATE_TYPE_DEFAULT,
721 POWER_STATE_TYPE_POWERSAVE,
722 POWER_STATE_TYPE_BATTERY,
723 POWER_STATE_TYPE_BALANCED,
724 POWER_STATE_TYPE_PERFORMANCE,
725};
726
ce8f5370
AD		 727enum radeon_pm_profile_type {
728 PM_PROFILE_DEFAULT,
729 PM_PROFILE_AUTO,
730 PM_PROFILE_LOW,
c9e75b21 731 PM_PROFILE_MID,
ce8f5370
AD		 732 PM_PROFILE_HIGH,
733};
734
735#define PM_PROFILE_DEFAULT_IDX 0
736#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 737#define PM_PROFILE_MID_SH_IDX 2
738#define PM_PROFILE_HIGH_SH_IDX 3
739#define PM_PROFILE_LOW_MH_IDX 4
740#define PM_PROFILE_MID_MH_IDX 5
741#define PM_PROFILE_HIGH_MH_IDX 6
742#define PM_PROFILE_MAX 7
ce8f5370
AD		 743
744struct radeon_pm_profile {
745 int dpms_off_ps_idx;
746 int dpms_on_ps_idx;
747 int dpms_off_cm_idx;
748 int dpms_on_cm_idx;
516d0e46
AD		 749};
750
21a8122a
AD		 751enum radeon_int_thermal_type {
752 THERMAL_TYPE_NONE,
753 THERMAL_TYPE_RV6XX,
754 THERMAL_TYPE_RV770,
755 THERMAL_TYPE_EVERGREEN,
e33df25f 756 THERMAL_TYPE_SUMO,
4fddba1f 757 THERMAL_TYPE_NI,
21a8122a
AD		 758};
759
56278a8e
AD		 760struct radeon_voltage {
761 enum radeon_voltage_type type;
762 /* gpio voltage */
763 struct radeon_gpio_rec gpio;
764 u32 delay; /* delay in usec from voltage drop to sclk change */
765 bool active_high; /* voltage drop is active when bit is high */
766 /* VDDC voltage */
767 u8 vddc_id; /* index into vddc voltage table */
768 u8 vddci_id; /* index into vddci voltage table */
769 bool vddci_enabled;
770 /* r6xx+ sw */
771 u32 voltage;
772};
773
d7311171
AD		 774/* clock mode flags */
775#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
776
56278a8e
AD		 777struct radeon_pm_clock_info {
778 /* memory clock */
779 u32 mclk;
780 /* engine clock */
781 u32 sclk;
782 /* voltage info */
783 struct radeon_voltage voltage;
d7311171 784 /* standardized clock flags */
56278a8e
AD		 785 u32 flags;
786};
787
a48b9b4e 788/* state flags */
d7311171 789#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 790
56278a8e 791struct radeon_power_state {
0ec0e74f 792 enum radeon_pm_state_type type;
56278a8e
AD		 793 /* XXX: use a define for num clock modes */
794 struct radeon_pm_clock_info clock_info[8];
795 /* number of valid clock modes in this power state */
796 int num_clock_modes;
56278a8e 797 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 798 /* standardized state flags */
799 u32 flags;
79daedc9
AD		 800 u32 misc; /* vbios specific flags */
801 u32 misc2; /* vbios specific flags */
802 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 803};
804
27459324
RM		 805/*
806 * Some modes are overclocked by very low value, accept them
807 */
808#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
809
c93bb85b 810struct radeon_pm {
c913e23a 811 struct mutex mutex;
a48b9b4e
AD		 812 u32 active_crtcs;
813 int active_crtc_count;
c913e23a 814 int req_vblank;
839461d3 815 bool vblank_sync;
2031f77c 816 bool gui_idle;
c93bb85b
JG		 817 fixed20_12 max_bandwidth;
818 fixed20_12 igp_sideport_mclk;
819 fixed20_12 igp_system_mclk;
820 fixed20_12 igp_ht_link_clk;
821 fixed20_12 igp_ht_link_width;
822 fixed20_12 k8_bandwidth;
823 fixed20_12 sideport_bandwidth;
824 fixed20_12 ht_bandwidth;
825 fixed20_12 core_bandwidth;
826 fixed20_12 sclk;
f47299c5 827 fixed20_12 mclk;
c93bb85b 828 fixed20_12 needed_bandwidth;
0975b162 829 struct radeon_power_state *power_state;
56278a8e
AD		 830 /* number of valid power states */
831 int num_power_states;
a48b9b4e
AD		 832 int current_power_state_index;
833 int current_clock_mode_index;
834 int requested_power_state_index;
835 int requested_clock_mode_index;
836 int default_power_state_index;
837 u32 current_sclk;
838 u32 current_mclk;
4d60173f 839 u32 current_vddc;
9ace9f7b
AD		 840 u32 default_sclk;
841 u32 default_mclk;
842 u32 default_vddc;
29fb52ca 843 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 844 /* selected pm method */
845 enum radeon_pm_method pm_method;
846 /* dynpm power management */
847 struct delayed_work dynpm_idle_work;
848 enum radeon_dynpm_state dynpm_state;
849 enum radeon_dynpm_action dynpm_planned_action;
850 unsigned long dynpm_action_timeout;
851 bool dynpm_can_upclock;
852 bool dynpm_can_downclock;
853 /* profile-based power management */
854 enum radeon_pm_profile_type profile;
855 int profile_index;
856 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 857 /* internal thermal controller on rv6xx+ */
858 enum radeon_int_thermal_type int_thermal_type;
859 struct device *int_hwmon_dev;
c93bb85b
JG		 860};
861
771fe6b9
JG		 862
863/*
864 * Benchmarking
865 */
866void radeon_benchmark(struct radeon_device *rdev);
867
868
ecc0b326
MD		 869/*
870 * Testing
871 */
872void radeon_test_moves(struct radeon_device *rdev);
873
874
771fe6b9
JG		 875/*
876 * Debugfs
877 */
878int radeon_debugfs_add_files(struct radeon_device *rdev,
879 struct drm_info_list *files,
880 unsigned nfiles);
881int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9
JG		 882
883
884/*
885 * ASIC specific functions.
886 */
887struct radeon_asic {
068a117c 888 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 889 void (*fini)(struct radeon_device *rdev);
890 int (*resume)(struct radeon_device *rdev);
891 int (*suspend)(struct radeon_device *rdev);
28d52043 892 void (*vga_set_state)(struct radeon_device *rdev, bool state);
225758d8 893 bool (*gpu_is_lockup)(struct radeon_device *rdev);
a2d07b74 894 int (*asic_reset)(struct radeon_device *rdev);
771fe6b9
JG		 895 void (*gart_tlb_flush)(struct radeon_device *rdev);
896 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
897 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
898 void (*cp_fini)(struct radeon_device *rdev);
899 void (*cp_disable)(struct radeon_device *rdev);
3ce0a23d 900 void (*cp_commit)(struct radeon_device *rdev);
771fe6b9 901 void (*ring_start)(struct radeon_device *rdev);
3ce0a23d
JG		 902 int (*ring_test)(struct radeon_device *rdev);
903 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
771fe6b9
JG		 904 int (*irq_set)(struct radeon_device *rdev);
905 int (*irq_process)(struct radeon_device *rdev);
7ed220d7 906 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 907 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
908 int (*cs_parse)(struct radeon_cs_parser *p);
909 int (*copy_blit)(struct radeon_device *rdev,
910 uint64_t src_offset,
911 uint64_t dst_offset,
912 unsigned num_pages,
913 struct radeon_fence *fence);
914 int (*copy_dma)(struct radeon_device *rdev,
915 uint64_t src_offset,
916 uint64_t dst_offset,
917 unsigned num_pages,
918 struct radeon_fence *fence);
919 int (*copy)(struct radeon_device *rdev,
920 uint64_t src_offset,
921 uint64_t dst_offset,
922 unsigned num_pages,
923 struct radeon_fence *fence);
7433874e 924 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
771fe6b9 925 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
7433874e 926 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
771fe6b9 927 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
c836a412 928 int (*get_pcie_lanes)(struct radeon_device *rdev);
771fe6b9
JG		 929 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
930 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
e024e110
DA		 931 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
932 uint32_t tiling_flags, uint32_t pitch,
933 uint32_t offset, uint32_t obj_size);
9479c54f 934 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
c93bb85b 935 void (*bandwidth_update)(struct radeon_device *rdev);
429770b3
AD		 936 void (*hpd_init)(struct radeon_device *rdev);
937 void (*hpd_fini)(struct radeon_device *rdev);
938 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
939 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
062b389c
JG		 940 /* ioctl hw specific callback. Some hw might want to perform special
941 * operation on specific ioctl. For instance on wait idle some hw
942 * might want to perform and HDP flush through MMIO as it seems that
943 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
944 * through ring.
945 */
946 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
def9ba9c 947 bool (*gui_idle)(struct radeon_device *rdev);
ce8f5370 948 /* power management */
49e02b73
AD		 949 void (*pm_misc)(struct radeon_device *rdev);
950 void (*pm_prepare)(struct radeon_device *rdev);
951 void (*pm_finish)(struct radeon_device *rdev);
ce8f5370
AD		 952 void (*pm_init_profile)(struct radeon_device *rdev);
953 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
6f34be50
AD		 954 /* pageflipping */
955 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
956 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
957 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 958};
959
21f9a437
JG		 960/*
961 * Asic structures
962 */
225758d8
JG		 963struct r100_gpu_lockup {
964 unsigned long last_jiffies;
965 u32 last_cp_rptr;
966};
967
551ebd83 968struct r100_asic {
225758d8
JG		 969 const unsigned *reg_safe_bm;
970 unsigned reg_safe_bm_size;
971 u32 hdp_cntl;
972 struct r100_gpu_lockup lockup;
551ebd83
DA		 973};
974
21f9a437 975struct r300_asic {
225758d8
JG		 976 const unsigned *reg_safe_bm;
977 unsigned reg_safe_bm_size;
978 u32 resync_scratch;
979 u32 hdp_cntl;
980 struct r100_gpu_lockup lockup;
21f9a437
JG		 981};
982
983struct r600_asic {
225758d8
JG		 984 unsigned max_pipes;
985 unsigned max_tile_pipes;
986 unsigned max_simds;
987 unsigned max_backends;
988 unsigned max_gprs;
989 unsigned max_threads;
990 unsigned max_stack_entries;
991 unsigned max_hw_contexts;
992 unsigned max_gs_threads;
993 unsigned sx_max_export_size;
994 unsigned sx_max_export_pos_size;
995 unsigned sx_max_export_smx_size;
996 unsigned sq_num_cf_insts;
997 unsigned tiling_nbanks;
998 unsigned tiling_npipes;
999 unsigned tiling_group_size;
e7aeeba6 1000 unsigned tile_config;
225758d8 1001 struct r100_gpu_lockup lockup;
21f9a437
JG		 1002};
1003
1004struct rv770_asic {
225758d8
JG		 1005 unsigned max_pipes;
1006 unsigned max_tile_pipes;
1007 unsigned max_simds;
1008 unsigned max_backends;
1009 unsigned max_gprs;
1010 unsigned max_threads;
1011 unsigned max_stack_entries;
1012 unsigned max_hw_contexts;
1013 unsigned max_gs_threads;
1014 unsigned sx_max_export_size;
1015 unsigned sx_max_export_pos_size;
1016 unsigned sx_max_export_smx_size;
1017 unsigned sq_num_cf_insts;
1018 unsigned sx_num_of_sets;
1019 unsigned sc_prim_fifo_size;
1020 unsigned sc_hiz_tile_fifo_size;
1021 unsigned sc_earlyz_tile_fifo_fize;
1022 unsigned tiling_nbanks;
1023 unsigned tiling_npipes;
1024 unsigned tiling_group_size;
e7aeeba6 1025 unsigned tile_config;
225758d8 1026 struct r100_gpu_lockup lockup;
21f9a437
JG		 1027};
1028
32fcdbf4
AD		 1029struct evergreen_asic {
1030 unsigned num_ses;
1031 unsigned max_pipes;
1032 unsigned max_tile_pipes;
1033 unsigned max_simds;
1034 unsigned max_backends;
1035 unsigned max_gprs;
1036 unsigned max_threads;
1037 unsigned max_stack_entries;
1038 unsigned max_hw_contexts;
1039 unsigned max_gs_threads;
1040 unsigned sx_max_export_size;
1041 unsigned sx_max_export_pos_size;
1042 unsigned sx_max_export_smx_size;
1043 unsigned sq_num_cf_insts;
1044 unsigned sx_num_of_sets;
1045 unsigned sc_prim_fifo_size;
1046 unsigned sc_hiz_tile_fifo_size;
1047 unsigned sc_earlyz_tile_fifo_size;
1048 unsigned tiling_nbanks;
1049 unsigned tiling_npipes;
1050 unsigned tiling_group_size;
e7aeeba6 1051 unsigned tile_config;
17db7042 1052 struct r100_gpu_lockup lockup;
32fcdbf4
AD		 1053};
1054
fecf1d07
AD		 1055struct cayman_asic {
1056 unsigned max_shader_engines;
1057 unsigned max_pipes_per_simd;
1058 unsigned max_tile_pipes;
1059 unsigned max_simds_per_se;
1060 unsigned max_backends_per_se;
1061 unsigned max_texture_channel_caches;
1062 unsigned max_gprs;
1063 unsigned max_threads;
1064 unsigned max_gs_threads;
1065 unsigned max_stack_entries;
1066 unsigned sx_num_of_sets;
1067 unsigned sx_max_export_size;
1068 unsigned sx_max_export_pos_size;
1069 unsigned sx_max_export_smx_size;
1070 unsigned max_hw_contexts;
1071 unsigned sq_num_cf_insts;
1072 unsigned sc_prim_fifo_size;
1073 unsigned sc_hiz_tile_fifo_size;
1074 unsigned sc_earlyz_tile_fifo_size;
1075
1076 unsigned num_shader_engines;
1077 unsigned num_shader_pipes_per_simd;
1078 unsigned num_tile_pipes;
1079 unsigned num_simds_per_se;
1080 unsigned num_backends_per_se;
1081 unsigned backend_disable_mask_per_asic;
1082 unsigned backend_map;
1083 unsigned num_texture_channel_caches;
1084 unsigned mem_max_burst_length_bytes;
1085 unsigned mem_row_size_in_kb;
1086 unsigned shader_engine_tile_size;
1087 unsigned num_gpus;
1088 unsigned multi_gpu_tile_size;
1089
1090 unsigned tile_config;
1091 struct r100_gpu_lockup lockup;
1092};
1093
068a117c
JG		 1094union radeon_asic_config {
1095 struct r300_asic r300;
551ebd83 1096 struct r100_asic r100;
3ce0a23d
JG		 1097 struct r600_asic r600;
1098 struct rv770_asic rv770;
32fcdbf4 1099 struct evergreen_asic evergreen;
fecf1d07 1100 struct cayman_asic cayman;
068a117c
JG		 1101};
1102
0a10c851
DV		 1103/*
1104 * asic initizalization from radeon_asic.c
1105 */
1106void radeon_agp_disable(struct radeon_device *rdev);
1107int radeon_asic_init(struct radeon_device *rdev);
1108
771fe6b9
JG		 1109
1110/*
1111 * IOCTL.
1112 */
1113int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1114 struct drm_file *filp);
1115int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1116 struct drm_file *filp);
1117int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1118 struct drm_file *file_priv);
1119int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1120 struct drm_file *file_priv);
1121int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1122 struct drm_file *file_priv);
1123int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1124 struct drm_file *file_priv);
1125int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1126 struct drm_file *filp);
1127int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1128 struct drm_file *filp);
1129int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1130 struct drm_file *filp);
1131int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1132 struct drm_file *filp);
1133int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 1134int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1135 struct drm_file *filp);
1136int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1137 struct drm_file *filp);
771fe6b9 1138
87cbf8f2
AD		 1139/* VRAM scratch page for HDP bug */
1140struct r700_vram_scratch {
1141 struct radeon_bo *robj;
1142 volatile uint32_t *ptr;
1143};
771fe6b9
JG		 1144
1145/*
1146 * Core structure, functions and helpers.
1147 */
1148typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1149typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1150
1151struct radeon_device {
9f022ddf 1152 struct device *dev;
771fe6b9
JG		 1153 struct drm_device *ddev;
1154 struct pci_dev *pdev;
1155 /* ASIC */
068a117c 1156 union radeon_asic_config config;
771fe6b9
JG		 1157 enum radeon_family family;
1158 unsigned long flags;
1159 int usec_timeout;
1160 enum radeon_pll_errata pll_errata;
1161 int num_gb_pipes;
f779b3e5 1162 int num_z_pipes;
771fe6b9
JG		 1163 int disp_priority;
1164 /* BIOS */
1165 uint8_t *bios;
1166 bool is_atom_bios;
1167 uint16_t bios_header_start;
4c788679 1168 struct radeon_bo *stollen_vga_memory;
771fe6b9 1169 /* Register mmio */
4c9bc75c
DA		 1170 resource_size_t rmmio_base;
1171 resource_size_t rmmio_size;
771fe6b9 1172 void *rmmio;
771fe6b9
JG		 1173 radeon_rreg_t mc_rreg;
1174 radeon_wreg_t mc_wreg;
1175 radeon_rreg_t pll_rreg;
1176 radeon_wreg_t pll_wreg;
de1b2898 1177 uint32_t pcie_reg_mask;
771fe6b9
JG		 1178 radeon_rreg_t pciep_rreg;
1179 radeon_wreg_t pciep_wreg;
351a52a2
AD		 1180 /* io port */
1181 void __iomem *rio_mem;
1182 resource_size_t rio_mem_size;
771fe6b9
JG		 1183 struct radeon_clock clock;
1184 struct radeon_mc mc;
1185 struct radeon_gart gart;
1186 struct radeon_mode_info mode_info;
1187 struct radeon_scratch scratch;
1188 struct radeon_mman mman;
1189 struct radeon_fence_driver fence_drv;
1190 struct radeon_cp cp;
0c88a02e
AD		 1191 /* cayman compute rings */
1192 struct radeon_cp cp1;
1193 struct radeon_cp cp2;
771fe6b9
JG		 1194 struct radeon_ib_pool ib_pool;
1195 struct radeon_irq irq;
1196 struct radeon_asic *asic;
1197 struct radeon_gem gem;
c93bb85b 1198 struct radeon_pm pm;
f657c2a7 1199 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9
JG		 1200 struct mutex cs_mutex;
1201 struct radeon_wb wb;
3ce0a23d 1202 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 1203 bool gpu_lockup;
1204 bool shutdown;
1205 bool suspend;
ad49f501 1206 bool need_dma32;
733289c2 1207 bool accel_working;
e024e110 1208 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 1209 const struct firmware *me_fw; /* all family ME firmware */
1210 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 1211 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 1212 const struct firmware *mc_fw; /* NI MC firmware */
3ce0a23d 1213 struct r600_blit r600_blit;
87cbf8f2 1214 struct r700_vram_scratch vram_scratch;
3e5cb98d 1215 int msi_enabled; /* msi enabled */
d8f60cfc 1216 struct r600_ih ih; /* r6/700 interrupt ring */
d4877cf2 1217 struct work_struct hotplug_work;
18917b60 1218 int num_crtc; /* number of crtcs */
40bacf16 1219 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
5876dd24 1220 struct mutex vram_mutex;
dafc3bd5
CK		 1221
1222 /* audio stuff */
7eea7e9e 1223 bool audio_enabled;
dafc3bd5
CK		 1224 struct timer_list audio_timer;
1225 int audio_channels;
1226 int audio_rate;
1227 int audio_bits_per_sample;
1228 uint8_t audio_status_bits;
1229 uint8_t audio_category_code;
6a9ee8af 1230
ce8f5370 1231 struct notifier_block acpi_nb;
9eba4a93 1232 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 1233 struct drm_file *hyperz_filp;
9eba4a93 1234 struct drm_file *cmask_filp;
f376b94f
AD		 1235 /* i2c buses */
1236 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
771fe6b9
JG		 1237};
1238
1239int radeon_device_init(struct radeon_device *rdev,
1240 struct drm_device *ddev,
1241 struct pci_dev *pdev,
1242 uint32_t flags);
1243void radeon_device_fini(struct radeon_device *rdev);
1244int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1245
de1b2898
DA		 1246static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1247{
07bec2df 1248 if (reg < rdev->rmmio_size)
de1b2898
DA		 1249 return readl(((void __iomem *)rdev->rmmio) + reg);
1250 else {
1251 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1252 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1253 }
1254}
1255
1256static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1257{
07bec2df 1258 if (reg < rdev->rmmio_size)
de1b2898
DA		 1259 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1260 else {
1261 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1262 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1263 }
1264}
1265
351a52a2
AD		 1266static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
1267{
1268 if (reg < rdev->rio_mem_size)
1269 return ioread32(rdev->rio_mem + reg);
1270 else {
1271 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1272 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
1273 }
1274}
1275
1276static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1277{
1278 if (reg < rdev->rio_mem_size)
1279 iowrite32(v, rdev->rio_mem + reg);
1280 else {
1281 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1282 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
1283 }
1284}
1285
4c788679
JG		 1286/*
1287 * Cast helper
1288 */
1289#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 1290
1291/*
1292 * Registers read & write functions.
1293 */
1294#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
1295#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
9e46a48d
AD		 1296#define RREG16(reg) readw(((void __iomem *)rdev->rmmio) + (reg))
1297#define WREG16(reg, v) writew(v, ((void __iomem *)rdev->rmmio) + (reg))
de1b2898 1298#define RREG32(reg) r100_mm_rreg(rdev, (reg))
3ce0a23d 1299#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
de1b2898 1300#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
771fe6b9
JG		 1301#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1302#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1303#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1304#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1305#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1306#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 1307#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1308#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
aa5120d2
RM		 1309#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1310#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
771fe6b9
JG		 1311#define WREG32_P(reg, val, mask) \
1312 do { \
1313 uint32_t tmp_ = RREG32(reg); \
1314 tmp_ &= (mask); \
1315 tmp_ |= ((val) & ~(mask)); \
1316 WREG32(reg, tmp_); \
1317 } while (0)
1318#define WREG32_PLL_P(reg, val, mask) \
1319 do { \
1320 uint32_t tmp_ = RREG32_PLL(reg); \
1321 tmp_ &= (mask); \
1322 tmp_ |= ((val) & ~(mask)); \
1323 WREG32_PLL(reg, tmp_); \
1324 } while (0)
3ce0a23d 1325#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
351a52a2
AD		 1326#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1327#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 1328
de1b2898
DA		 1329/*
1330 * Indirect registers accessor
1331 */
1332static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1333{
1334 uint32_t r;
1335
1336 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1337 r = RREG32(RADEON_PCIE_DATA);
1338 return r;
1339}
1340
1341static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1342{
1343 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1344 WREG32(RADEON_PCIE_DATA, (v));
1345}
1346
771fe6b9
JG		 1347void r100_pll_errata_after_index(struct radeon_device *rdev);
1348
1349
1350/*
1351 * ASICs helpers.
1352 */
b995e433
DA		 1353#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1354 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 1355#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1356 (rdev->family == CHIP_RV200) || \
1357 (rdev->family == CHIP_RS100) || \
1358 (rdev->family == CHIP_RS200) || \
1359 (rdev->family == CHIP_RV250) || \
1360 (rdev->family == CHIP_RV280) || \
1361 (rdev->family == CHIP_RS300))
1362#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1363 (rdev->family == CHIP_RV350) || \
1364 (rdev->family == CHIP_R350) || \
1365 (rdev->family == CHIP_RV380) || \
1366 (rdev->family == CHIP_R420) || \
1367 (rdev->family == CHIP_R423) || \
1368 (rdev->family == CHIP_RV410) || \
1369 (rdev->family == CHIP_RS400) || \
1370 (rdev->family == CHIP_RS480))
3313e3d4
AD		 1371#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1372 (rdev->ddev->pdev->device == 0x9443) || \
1373 (rdev->ddev->pdev->device == 0x944B) || \
1374 (rdev->ddev->pdev->device == 0x9506) || \
1375 (rdev->ddev->pdev->device == 0x9509) || \
1376 (rdev->ddev->pdev->device == 0x950F) || \
1377 (rdev->ddev->pdev->device == 0x689C) || \
1378 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 1379#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 1380#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1381 (rdev->family == CHIP_RS690) || \
1382 (rdev->family == CHIP_RS740) || \
1383 (rdev->family >= CHIP_R600))
771fe6b9
JG		 1384#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1385#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 1386#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 1387#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1388 (rdev->flags & RADEON_IS_IGP))
1fe18305 1389#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
771fe6b9
JG		 1390
1391/*
1392 * BIOS helpers.
1393 */
1394#define RBIOS8(i) (rdev->bios[i])
1395#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1396#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1397
1398int radeon_combios_init(struct radeon_device *rdev);
1399void radeon_combios_fini(struct radeon_device *rdev);
1400int radeon_atombios_init(struct radeon_device *rdev);
1401void radeon_atombios_fini(struct radeon_device *rdev);
1402
1403
1404/*
1405 * RING helpers.
1406 */
771fe6b9
JG		 1407static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1408{
1409#if DRM_DEBUG_CODE
1410 if (rdev->cp.count_dw <= 0) {
1411 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1412 }
1413#endif
1414 rdev->cp.ring[rdev->cp.wptr++] = v;
1415 rdev->cp.wptr &= rdev->cp.ptr_mask;
1416 rdev->cp.count_dw--;
1417 rdev->cp.ring_free_dw--;
1418}
1419
1420
1421/*
1422 * ASICs macro.
1423 */
068a117c 1424#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 1425#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1426#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1427#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
771fe6b9 1428#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
28d52043 1429#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
225758d8 1430#define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
a2d07b74 1431#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
771fe6b9
JG		 1432#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1433#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
3ce0a23d 1434#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
771fe6b9 1435#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
3ce0a23d
JG		 1436#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1437#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
771fe6b9
JG		 1438#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1439#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
7ed220d7 1440#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
771fe6b9
JG		 1441#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1442#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1443#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1444#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
7433874e 1445#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
771fe6b9 1446#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
7433874e 1447#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
93e7de7b 1448#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
c836a412 1449#define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
771fe6b9
JG		 1450#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1451#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
e024e110
DA		 1452#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1453#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
c93bb85b 1454#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
429770b3
AD		 1455#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1456#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1457#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1458#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
def9ba9c 1459#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a424816f
AD		 1460#define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1461#define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1462#define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
ce8f5370
AD		 1463#define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1464#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
6f34be50
AD		 1465#define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc))
1466#define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base))
1467#define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc))
771fe6b9 1468
6cf8a3f5 1469/* Common functions */
700a0cc0 1470/* AGP */
90aca4d2 1471extern int radeon_gpu_reset(struct radeon_device *rdev);
700a0cc0 1472extern void radeon_agp_disable(struct radeon_device *rdev);
4aac0473 1473extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
82568565 1474extern void radeon_gart_restore(struct radeon_device *rdev);
21f9a437
JG		 1475extern int radeon_modeset_init(struct radeon_device *rdev);
1476extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 1477extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 1478extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 1479extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 1480extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 1481extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 1482extern void radeon_wb_fini(struct radeon_device *rdev);
1483extern int radeon_wb_init(struct radeon_device *rdev);
1484extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 1485extern void radeon_surface_init(struct radeon_device *rdev);
1486extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 1487extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 1488extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 1489extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 1490extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 1491extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1492extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
6a9ee8af
DA		 1493extern int radeon_resume_kms(struct drm_device *dev);
1494extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
6cf8a3f5 1495
3574dda4
DV		 1496/*
1497 * r600 functions used by radeon_encoder.c
1498 */
2cd6218c
RM		 1499extern void r600_hdmi_enable(struct drm_encoder *encoder);
1500extern void r600_hdmi_disable(struct drm_encoder *encoder);
dafc3bd5 1501extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
fe251e2f 1502
0af62b01
AD		 1503extern int ni_init_microcode(struct radeon_device *rdev);
1504extern int btc_mc_load_microcode(struct radeon_device *rdev);
1505
d7a2952f
AM		 1506/* radeon_acpi.c */
1507#if defined(CONFIG_ACPI)
1508extern int radeon_acpi_init(struct radeon_device *rdev);
1509#else
1510static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1511#endif
1512
4c788679
JG		 1513#include "radeon_object.h"
1514
771fe6b9 1515#endif
Linux kernel - Deliverables
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