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drm/radeon/kms: add irq mitigation code for sw interrupt.
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31#include "radeon_object.h"
32
33/* TODO: Here are things that needs to be done :
34 * - surface allocator & initializer : (bit like scratch reg) should
35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
36 * related to surface
37 * - WB : write back stuff (do it bit like scratch reg things)
38 * - Vblank : look at Jesse's rework and what we should do
39 * - r600/r700: gart & cp
40 * - cs : clean cs ioctl use bitmap & things like that.
41 * - power management stuff
42 * - Barrier in gart code
43 * - Unmappabled vram ?
44 * - TESTING, TESTING, TESTING
45 */
46
d39c3b89
JG		 47/* Initialization path:
48 * We expect that acceleration initialization might fail for various
49 * reasons even thought we work hard to make it works on most
50 * configurations. In order to still have a working userspace in such
51 * situation the init path must succeed up to the memory controller
52 * initialization point. Failure before this point are considered as
53 * fatal error. Here is the init callchain :
54 * radeon_device_init perform common structure, mutex initialization
55 * asic_init setup the GPU memory layout and perform all
56 * one time initialization (failure in this
57 * function are considered fatal)
58 * asic_startup setup the GPU acceleration, in order to
59 * follow guideline the first thing this
60 * function should do is setting the GPU
61 * memory controller (only MC setup failure
62 * are considered as fatal)
63 */
64
771fe6b9
JG		 65#include <asm/atomic.h>
66#include <linux/wait.h>
67#include <linux/list.h>
68#include <linux/kref.h>
69
c2142715 70#include "radeon_family.h"
771fe6b9
JG		 71#include "radeon_mode.h"
72#include "radeon_reg.h"
771fe6b9
JG		 73
74/*
75 * Modules parameters.
76 */
77extern int radeon_no_wb;
78extern int radeon_modeset;
79extern int radeon_dynclks;
80extern int radeon_r4xx_atom;
81extern int radeon_agpmode;
82extern int radeon_vram_limit;
83extern int radeon_gart_size;
84extern int radeon_benchmarking;
ecc0b326 85extern int radeon_testing;
771fe6b9 86extern int radeon_connector_table;
4ce001ab 87extern int radeon_tv;
771fe6b9
JG		 88
89/*
90 * Copy from radeon_drv.h so we don't have to include both and have conflicting
91 * symbol;
92 */
93#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
94#define RADEON_IB_POOL_SIZE 16
95#define RADEON_DEBUGFS_MAX_NUM_FILES 32
96#define RADEONFB_CONN_LIMIT 4
f657c2a7 97#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 98
771fe6b9
JG		 99/*
100 * Errata workarounds.
101 */
102enum radeon_pll_errata {
103 CHIP_ERRATA_R300_CG = 0x00000001,
104 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
105 CHIP_ERRATA_PLL_DELAY = 0x00000004
106};
107
108
109struct radeon_device;
110
111
112/*
113 * BIOS.
114 */
115bool radeon_get_bios(struct radeon_device *rdev);
116
3ce0a23d 117
771fe6b9 118/*
3ce0a23d 119 * Dummy page
771fe6b9 120 */
3ce0a23d
JG		 121struct radeon_dummy_page {
122 struct page *page;
123 dma_addr_t addr;
124};
125int radeon_dummy_page_init(struct radeon_device *rdev);
126void radeon_dummy_page_fini(struct radeon_device *rdev);
127
771fe6b9 128
3ce0a23d
JG		 129/*
130 * Clocks
131 */
771fe6b9
JG		 132struct radeon_clock {
133 struct radeon_pll p1pll;
134 struct radeon_pll p2pll;
135 struct radeon_pll spll;
136 struct radeon_pll mpll;
137 /* 10 Khz units */
138 uint32_t default_mclk;
139 uint32_t default_sclk;
140};
141
7433874e
RM		 142/*
143 * Power management
144 */
145int radeon_pm_init(struct radeon_device *rdev);
3ce0a23d 146
771fe6b9
JG		 147/*
148 * Fences.
149 */
150struct radeon_fence_driver {
151 uint32_t scratch_reg;
152 atomic_t seq;
153 uint32_t last_seq;
154 unsigned long count_timeout;
155 wait_queue_head_t queue;
156 rwlock_t lock;
157 struct list_head created;
158 struct list_head emited;
159 struct list_head signaled;
160};
161
162struct radeon_fence {
163 struct radeon_device *rdev;
164 struct kref kref;
165 struct list_head list;
166 /* protected by radeon_fence.lock */
167 uint32_t seq;
168 unsigned long timeout;
169 bool emited;
170 bool signaled;
171};
172
173int radeon_fence_driver_init(struct radeon_device *rdev);
174void radeon_fence_driver_fini(struct radeon_device *rdev);
175int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
176int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
177void radeon_fence_process(struct radeon_device *rdev);
178bool radeon_fence_signaled(struct radeon_fence *fence);
179int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
180int radeon_fence_wait_next(struct radeon_device *rdev);
181int radeon_fence_wait_last(struct radeon_device *rdev);
182struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
183void radeon_fence_unref(struct radeon_fence **fence);
184
e024e110
DA		 185/*
186 * Tiling registers
187 */
188struct radeon_surface_reg {
189 struct radeon_object *robj;
190};
191
192#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 193
194/*
195 * Radeon buffer.
196 */
197struct radeon_object;
198
199struct radeon_object_list {
200 struct list_head list;
201 struct radeon_object *robj;
202 uint64_t gpu_offset;
203 unsigned rdomain;
204 unsigned wdomain;
e024e110 205 uint32_t tiling_flags;
771fe6b9
JG		 206};
207
208int radeon_object_init(struct radeon_device *rdev);
209void radeon_object_fini(struct radeon_device *rdev);
210int radeon_object_create(struct radeon_device *rdev,
211 struct drm_gem_object *gobj,
212 unsigned long size,
213 bool kernel,
214 uint32_t domain,
215 bool interruptible,
216 struct radeon_object **robj_ptr);
217int radeon_object_kmap(struct radeon_object *robj, void **ptr);
218void radeon_object_kunmap(struct radeon_object *robj);
219void radeon_object_unref(struct radeon_object **robj);
220int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
221 uint64_t *gpu_addr);
222void radeon_object_unpin(struct radeon_object *robj);
223int radeon_object_wait(struct radeon_object *robj);
cefb87ef 224int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement);
771fe6b9
JG		 225int radeon_object_evict_vram(struct radeon_device *rdev);
226int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
227void radeon_object_force_delete(struct radeon_device *rdev);
228void radeon_object_list_add_object(struct radeon_object_list *lobj,
229 struct list_head *head);
230int radeon_object_list_validate(struct list_head *head, void *fence);
231void radeon_object_list_unvalidate(struct list_head *head);
232void radeon_object_list_clean(struct list_head *head);
233int radeon_object_fbdev_mmap(struct radeon_object *robj,
234 struct vm_area_struct *vma);
235unsigned long radeon_object_size(struct radeon_object *robj);
e024e110
DA		 236void radeon_object_clear_surface_reg(struct radeon_object *robj);
237int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
238 bool force_drop);
239void radeon_object_set_tiling_flags(struct radeon_object *robj,
240 uint32_t tiling_flags, uint32_t pitch);
241void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
242void radeon_bo_move_notify(struct ttm_buffer_object *bo,
243 struct ttm_mem_reg *mem);
244void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
771fe6b9
JG		 245/*
246 * GEM objects.
247 */
248struct radeon_gem {
249 struct list_head objects;
250};
251
252int radeon_gem_init(struct radeon_device *rdev);
253void radeon_gem_fini(struct radeon_device *rdev);
254int radeon_gem_object_create(struct radeon_device *rdev, int size,
255 int alignment, int initial_domain,
256 bool discardable, bool kernel,
257 bool interruptible,
258 struct drm_gem_object **obj);
259int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
260 uint64_t *gpu_addr);
261void radeon_gem_object_unpin(struct drm_gem_object *obj);
262
263
264/*
265 * GART structures, functions & helpers
266 */
267struct radeon_mc;
268
269struct radeon_gart_table_ram {
270 volatile uint32_t *ptr;
271};
272
273struct radeon_gart_table_vram {
274 struct radeon_object *robj;
275 volatile uint32_t *ptr;
276};
277
278union radeon_gart_table {
279 struct radeon_gart_table_ram ram;
280 struct radeon_gart_table_vram vram;
281};
282
a77f1718
MT		 283#define RADEON_GPU_PAGE_SIZE 4096
284
771fe6b9
JG		 285struct radeon_gart {
286 dma_addr_t table_addr;
287 unsigned num_gpu_pages;
288 unsigned num_cpu_pages;
289 unsigned table_size;
290 union radeon_gart_table table;
291 struct page **pages;
292 dma_addr_t *pages_addr;
293 bool ready;
294};
295
296int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
297void radeon_gart_table_ram_free(struct radeon_device *rdev);
298int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
299void radeon_gart_table_vram_free(struct radeon_device *rdev);
300int radeon_gart_init(struct radeon_device *rdev);
301void radeon_gart_fini(struct radeon_device *rdev);
302void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
303 int pages);
304int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
305 int pages, struct page **pagelist);
306
307
308/*
309 * GPU MC structures, functions & helpers
310 */
311struct radeon_mc {
312 resource_size_t aper_size;
313 resource_size_t aper_base;
314 resource_size_t agp_base;
7a50f01a
DA		 315 /* for some chips with <= 32MB we need to lie
316 * about vram size near mc fb location */
3ce0a23d
JG		 317 u64 mc_vram_size;
318 u64 gtt_location;
319 u64 gtt_size;
320 u64 gtt_start;
321 u64 gtt_end;
322 u64 vram_location;
323 u64 vram_start;
324 u64 vram_end;
771fe6b9 325 unsigned vram_width;
3ce0a23d 326 u64 real_vram_size;
771fe6b9
JG		 327 int vram_mtrr;
328 bool vram_is_ddr;
329};
330
331int radeon_mc_setup(struct radeon_device *rdev);
332
333
334/*
335 * GPU scratch registers structures, functions & helpers
336 */
337struct radeon_scratch {
338 unsigned num_reg;
339 bool free[32];
340 uint32_t reg[32];
341};
342
343int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
344void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
345
346
347/*
348 * IRQS.
349 */
350struct radeon_irq {
351 bool installed;
352 bool sw_int;
353 /* FIXME: use a define max crtc rather than hardcode it */
354 bool crtc_vblank_int[2];
1614f8b1
DA		 355 spinlock_t sw_lock;
356 int sw_refcount;
771fe6b9
JG		 357};
358
359int radeon_irq_kms_init(struct radeon_device *rdev);
360void radeon_irq_kms_fini(struct radeon_device *rdev);
1614f8b1
DA		 361void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
362void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
771fe6b9
JG		 363
364/*
365 * CP & ring.
366 */
367struct radeon_ib {
368 struct list_head list;
369 unsigned long idx;
370 uint64_t gpu_addr;
371 struct radeon_fence *fence;
513bcb46 372 uint32_t *ptr;
771fe6b9
JG		 373 uint32_t length_dw;
374};
375
ecb114a1
DA		 376/*
377 * locking -
378 * mutex protects scheduled_ibs, ready, alloc_bm
379 */
771fe6b9
JG		 380struct radeon_ib_pool {
381 struct mutex mutex;
382 struct radeon_object *robj;
383 struct list_head scheduled_ibs;
384 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
385 bool ready;
386 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
387};
388
389struct radeon_cp {
390 struct radeon_object *ring_obj;
391 volatile uint32_t *ring;
392 unsigned rptr;
393 unsigned wptr;
394 unsigned wptr_old;
395 unsigned ring_size;
396 unsigned ring_free_dw;
397 int count_dw;
398 uint64_t gpu_addr;
399 uint32_t align_mask;
400 uint32_t ptr_mask;
401 struct mutex mutex;
402 bool ready;
403};
404
d8f60cfc
AD		 405/*
406 * R6xx+ IH ring
407 */
408struct r600_ih {
409 struct radeon_object *ring_obj;
410 volatile uint32_t *ring;
411 unsigned rptr;
412 unsigned wptr;
413 unsigned wptr_old;
414 unsigned ring_size;
415 uint64_t gpu_addr;
416 uint32_t align_mask;
417 uint32_t ptr_mask;
418 spinlock_t lock;
419 bool enabled;
420};
421
3ce0a23d
JG		 422struct r600_blit {
423 struct radeon_object *shader_obj;
424 u64 shader_gpu_addr;
425 u32 vs_offset, ps_offset;
426 u32 state_offset;
427 u32 state_len;
428 u32 vb_used, vb_total;
429 struct radeon_ib *vb_ib;
430};
431
771fe6b9
JG		 432int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
433void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
434int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
435int radeon_ib_pool_init(struct radeon_device *rdev);
436void radeon_ib_pool_fini(struct radeon_device *rdev);
437int radeon_ib_test(struct radeon_device *rdev);
438/* Ring access between begin & end cannot sleep */
439void radeon_ring_free_size(struct radeon_device *rdev);
440int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
441void radeon_ring_unlock_commit(struct radeon_device *rdev);
442void radeon_ring_unlock_undo(struct radeon_device *rdev);
443int radeon_ring_test(struct radeon_device *rdev);
444int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
445void radeon_ring_fini(struct radeon_device *rdev);
446
447
448/*
449 * CS.
450 */
451struct radeon_cs_reloc {
452 struct drm_gem_object *gobj;
453 struct radeon_object *robj;
454 struct radeon_object_list lobj;
455 uint32_t handle;
456 uint32_t flags;
457};
458
459struct radeon_cs_chunk {
460 uint32_t chunk_id;
461 uint32_t length_dw;
513bcb46
DA		 462 int kpage_idx[2];
463 uint32_t *kpage[2];
771fe6b9 464 uint32_t *kdata;
513bcb46
DA		 465 void __user *user_ptr;
466 int last_copied_page;
467 int last_page_index;
771fe6b9
JG		 468};
469
470struct radeon_cs_parser {
471 struct radeon_device *rdev;
472 struct drm_file *filp;
473 /* chunks */
474 unsigned nchunks;
475 struct radeon_cs_chunk *chunks;
476 uint64_t *chunks_array;
477 /* IB */
478 unsigned idx;
479 /* relocations */
480 unsigned nrelocs;
481 struct radeon_cs_reloc *relocs;
482 struct radeon_cs_reloc **relocs_ptr;
483 struct list_head validated;
484 /* indices of various chunks */
485 int chunk_ib_idx;
486 int chunk_relocs_idx;
487 struct radeon_ib *ib;
488 void *track;
3ce0a23d 489 unsigned family;
513bcb46 490 int parser_error;
771fe6b9
JG		 491};
492
513bcb46
DA		 493extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
494extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
495
496
497static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
498{
499 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
500 u32 pg_idx, pg_offset;
501 u32 idx_value = 0;
502 int new_page;
503
504 pg_idx = (idx * 4) / PAGE_SIZE;
505 pg_offset = (idx * 4) % PAGE_SIZE;
506
507 if (ibc->kpage_idx[0] == pg_idx)
508 return ibc->kpage[0][pg_offset/4];
509 if (ibc->kpage_idx[1] == pg_idx)
510 return ibc->kpage[1][pg_offset/4];
511
512 new_page = radeon_cs_update_pages(p, pg_idx);
513 if (new_page < 0) {
514 p->parser_error = new_page;
515 return 0;
516 }
517
518 idx_value = ibc->kpage[new_page][pg_offset/4];
519 return idx_value;
520}
521
771fe6b9
JG		 522struct radeon_cs_packet {
523 unsigned idx;
524 unsigned type;
525 unsigned reg;
526 unsigned opcode;
527 int count;
528 unsigned one_reg_wr;
529};
530
531typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
532 struct radeon_cs_packet *pkt,
533 unsigned idx, unsigned reg);
534typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
535 struct radeon_cs_packet *pkt);
536
537
538/*
539 * AGP
540 */
541int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 542void radeon_agp_resume(struct radeon_device *rdev);
771fe6b9
JG		 543void radeon_agp_fini(struct radeon_device *rdev);
544
545
546/*
547 * Writeback
548 */
549struct radeon_wb {
550 struct radeon_object *wb_obj;
551 volatile uint32_t *wb;
552 uint64_t gpu_addr;
553};
554
c93bb85b
JG		 555/**
556 * struct radeon_pm - power management datas
557 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
558 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
559 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
560 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
561 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
562 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
563 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
564 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
565 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
566 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
567 * @needed_bandwidth: current bandwidth needs
568 *
569 * It keeps track of various data needed to take powermanagement decision.
570 * Bandwith need is used to determine minimun clock of the GPU and memory.
571 * Equation between gpu/memory clock and available bandwidth is hw dependent
572 * (type of memory, bus size, efficiency, ...)
573 */
574struct radeon_pm {
575 fixed20_12 max_bandwidth;
576 fixed20_12 igp_sideport_mclk;
577 fixed20_12 igp_system_mclk;
578 fixed20_12 igp_ht_link_clk;
579 fixed20_12 igp_ht_link_width;
580 fixed20_12 k8_bandwidth;
581 fixed20_12 sideport_bandwidth;
582 fixed20_12 ht_bandwidth;
583 fixed20_12 core_bandwidth;
584 fixed20_12 sclk;
585 fixed20_12 needed_bandwidth;
586};
587
771fe6b9
JG		 588
589/*
590 * Benchmarking
591 */
592void radeon_benchmark(struct radeon_device *rdev);
593
594
ecc0b326
MD		 595/*
596 * Testing
597 */
598void radeon_test_moves(struct radeon_device *rdev);
599
600
771fe6b9
JG		 601/*
602 * Debugfs
603 */
604int radeon_debugfs_add_files(struct radeon_device *rdev,
605 struct drm_info_list *files,
606 unsigned nfiles);
607int radeon_debugfs_fence_init(struct radeon_device *rdev);
608int r100_debugfs_rbbm_init(struct radeon_device *rdev);
609int r100_debugfs_cp_init(struct radeon_device *rdev);
610
611
612/*
613 * ASIC specific functions.
614 */
615struct radeon_asic {
068a117c 616 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 617 void (*fini)(struct radeon_device *rdev);
618 int (*resume)(struct radeon_device *rdev);
619 int (*suspend)(struct radeon_device *rdev);
28d52043 620 void (*vga_set_state)(struct radeon_device *rdev, bool state);
771fe6b9 621 int (*gpu_reset)(struct radeon_device *rdev);
771fe6b9
JG		 622 void (*gart_tlb_flush)(struct radeon_device *rdev);
623 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
624 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
625 void (*cp_fini)(struct radeon_device *rdev);
626 void (*cp_disable)(struct radeon_device *rdev);
3ce0a23d 627 void (*cp_commit)(struct radeon_device *rdev);
771fe6b9 628 void (*ring_start)(struct radeon_device *rdev);
3ce0a23d
JG		 629 int (*ring_test)(struct radeon_device *rdev);
630 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
771fe6b9
JG		 631 int (*irq_set)(struct radeon_device *rdev);
632 int (*irq_process)(struct radeon_device *rdev);
7ed220d7 633 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 634 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
635 int (*cs_parse)(struct radeon_cs_parser *p);
636 int (*copy_blit)(struct radeon_device *rdev,
637 uint64_t src_offset,
638 uint64_t dst_offset,
639 unsigned num_pages,
640 struct radeon_fence *fence);
641 int (*copy_dma)(struct radeon_device *rdev,
642 uint64_t src_offset,
643 uint64_t dst_offset,
644 unsigned num_pages,
645 struct radeon_fence *fence);
646 int (*copy)(struct radeon_device *rdev,
647 uint64_t src_offset,
648 uint64_t dst_offset,
649 unsigned num_pages,
650 struct radeon_fence *fence);
7433874e 651 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
771fe6b9 652 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
7433874e 653 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
771fe6b9
JG		 654 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
655 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
656 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
e024e110
DA		 657 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
658 uint32_t tiling_flags, uint32_t pitch,
659 uint32_t offset, uint32_t obj_size);
660 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
c93bb85b 661 void (*bandwidth_update)(struct radeon_device *rdev);
23956dfa 662 void (*hdp_flush)(struct radeon_device *rdev);
771fe6b9
JG		 663};
664
21f9a437
JG		 665/*
666 * Asic structures
667 */
551ebd83
DA		 668struct r100_asic {
669 const unsigned *reg_safe_bm;
670 unsigned reg_safe_bm_size;
671};
672
21f9a437
JG		 673struct r300_asic {
674 const unsigned *reg_safe_bm;
675 unsigned reg_safe_bm_size;
676};
677
678struct r600_asic {
679 unsigned max_pipes;
680 unsigned max_tile_pipes;
681 unsigned max_simds;
682 unsigned max_backends;
683 unsigned max_gprs;
684 unsigned max_threads;
685 unsigned max_stack_entries;
686 unsigned max_hw_contexts;
687 unsigned max_gs_threads;
688 unsigned sx_max_export_size;
689 unsigned sx_max_export_pos_size;
690 unsigned sx_max_export_smx_size;
691 unsigned sq_num_cf_insts;
692};
693
694struct rv770_asic {
695 unsigned max_pipes;
696 unsigned max_tile_pipes;
697 unsigned max_simds;
698 unsigned max_backends;
699 unsigned max_gprs;
700 unsigned max_threads;
701 unsigned max_stack_entries;
702 unsigned max_hw_contexts;
703 unsigned max_gs_threads;
704 unsigned sx_max_export_size;
705 unsigned sx_max_export_pos_size;
706 unsigned sx_max_export_smx_size;
707 unsigned sq_num_cf_insts;
708 unsigned sx_num_of_sets;
709 unsigned sc_prim_fifo_size;
710 unsigned sc_hiz_tile_fifo_size;
711 unsigned sc_earlyz_tile_fifo_fize;
712};
713
068a117c
JG		 714union radeon_asic_config {
715 struct r300_asic r300;
551ebd83 716 struct r100_asic r100;
3ce0a23d
JG		 717 struct r600_asic r600;
718 struct rv770_asic rv770;
068a117c
JG		 719};
720
771fe6b9
JG		 721
722/*
723 * IOCTL.
724 */
725int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
726 struct drm_file *filp);
727int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
728 struct drm_file *filp);
729int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
730 struct drm_file *file_priv);
731int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
732 struct drm_file *file_priv);
733int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
734 struct drm_file *file_priv);
735int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
736 struct drm_file *file_priv);
737int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
738 struct drm_file *filp);
739int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
740 struct drm_file *filp);
741int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
742 struct drm_file *filp);
743int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
744 struct drm_file *filp);
745int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 746int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
747 struct drm_file *filp);
748int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
749 struct drm_file *filp);
771fe6b9
JG		 750
751
752/*
753 * Core structure, functions and helpers.
754 */
755typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
756typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
757
758struct radeon_device {
9f022ddf 759 struct device *dev;
771fe6b9
JG		 760 struct drm_device *ddev;
761 struct pci_dev *pdev;
762 /* ASIC */
068a117c 763 union radeon_asic_config config;
771fe6b9
JG		 764 enum radeon_family family;
765 unsigned long flags;
766 int usec_timeout;
767 enum radeon_pll_errata pll_errata;
768 int num_gb_pipes;
f779b3e5 769 int num_z_pipes;
771fe6b9
JG		 770 int disp_priority;
771 /* BIOS */
772 uint8_t *bios;
773 bool is_atom_bios;
774 uint16_t bios_header_start;
775 struct radeon_object *stollen_vga_memory;
776 struct fb_info *fbdev_info;
777 struct radeon_object *fbdev_robj;
778 struct radeon_framebuffer *fbdev_rfb;
779 /* Register mmio */
4c9bc75c
DA		 780 resource_size_t rmmio_base;
781 resource_size_t rmmio_size;
771fe6b9 782 void *rmmio;
771fe6b9
JG		 783 radeon_rreg_t mc_rreg;
784 radeon_wreg_t mc_wreg;
785 radeon_rreg_t pll_rreg;
786 radeon_wreg_t pll_wreg;
de1b2898 787 uint32_t pcie_reg_mask;
771fe6b9
JG		 788 radeon_rreg_t pciep_rreg;
789 radeon_wreg_t pciep_wreg;
790 struct radeon_clock clock;
791 struct radeon_mc mc;
792 struct radeon_gart gart;
793 struct radeon_mode_info mode_info;
794 struct radeon_scratch scratch;
795 struct radeon_mman mman;
796 struct radeon_fence_driver fence_drv;
797 struct radeon_cp cp;
798 struct radeon_ib_pool ib_pool;
799 struct radeon_irq irq;
800 struct radeon_asic *asic;
801 struct radeon_gem gem;
c93bb85b 802 struct radeon_pm pm;
f657c2a7 803 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9
JG		 804 struct mutex cs_mutex;
805 struct radeon_wb wb;
3ce0a23d 806 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 807 bool gpu_lockup;
808 bool shutdown;
809 bool suspend;
ad49f501 810 bool need_dma32;
733289c2 811 bool accel_working;
e024e110 812 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 813 const struct firmware *me_fw; /* all family ME firmware */
814 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 815 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
3ce0a23d 816 struct r600_blit r600_blit;
3e5cb98d 817 int msi_enabled; /* msi enabled */
d8f60cfc 818 struct r600_ih ih; /* r6/700 interrupt ring */
771fe6b9
JG		 819};
820
821int radeon_device_init(struct radeon_device *rdev,
822 struct drm_device *ddev,
823 struct pci_dev *pdev,
824 uint32_t flags);
825void radeon_device_fini(struct radeon_device *rdev);
826int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
827
3ce0a23d
JG		 828/* r600 blit */
829int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
830void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
831void r600_kms_blit_copy(struct radeon_device *rdev,
832 u64 src_gpu_addr, u64 dst_gpu_addr,
833 int size_bytes);
834
de1b2898
DA		 835static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
836{
837 if (reg < 0x10000)
838 return readl(((void __iomem *)rdev->rmmio) + reg);
839 else {
840 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
841 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
842 }
843}
844
845static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
846{
847 if (reg < 0x10000)
848 writel(v, ((void __iomem *)rdev->rmmio) + reg);
849 else {
850 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
851 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
852 }
853}
854
771fe6b9
JG		 855
856/*
857 * Registers read & write functions.
858 */
859#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
860#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
de1b2898 861#define RREG32(reg) r100_mm_rreg(rdev, (reg))
3ce0a23d 862#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
de1b2898 863#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
771fe6b9
JG		 864#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
865#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
866#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
867#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
868#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
869#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 870#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
871#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
771fe6b9
JG		 872#define WREG32_P(reg, val, mask) \
873 do { \
874 uint32_t tmp_ = RREG32(reg); \
875 tmp_ &= (mask); \
876 tmp_ |= ((val) & ~(mask)); \
877 WREG32(reg, tmp_); \
878 } while (0)
879#define WREG32_PLL_P(reg, val, mask) \
880 do { \
881 uint32_t tmp_ = RREG32_PLL(reg); \
882 tmp_ &= (mask); \
883 tmp_ |= ((val) & ~(mask)); \
884 WREG32_PLL(reg, tmp_); \
885 } while (0)
3ce0a23d 886#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
771fe6b9 887
de1b2898
DA		 888/*
889 * Indirect registers accessor
890 */
891static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
892{
893 uint32_t r;
894
895 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
896 r = RREG32(RADEON_PCIE_DATA);
897 return r;
898}
899
900static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
901{
902 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
903 WREG32(RADEON_PCIE_DATA, (v));
904}
905
771fe6b9
JG		 906void r100_pll_errata_after_index(struct radeon_device *rdev);
907
908
909/*
910 * ASICs helpers.
911 */
b995e433
DA		 912#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
913 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 914#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
915 (rdev->family == CHIP_RV200) || \
916 (rdev->family == CHIP_RS100) || \
917 (rdev->family == CHIP_RS200) || \
918 (rdev->family == CHIP_RV250) || \
919 (rdev->family == CHIP_RV280) || \
920 (rdev->family == CHIP_RS300))
921#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
922 (rdev->family == CHIP_RV350) || \
923 (rdev->family == CHIP_R350) || \
924 (rdev->family == CHIP_RV380) || \
925 (rdev->family == CHIP_R420) || \
926 (rdev->family == CHIP_R423) || \
927 (rdev->family == CHIP_RV410) || \
928 (rdev->family == CHIP_RS400) || \
929 (rdev->family == CHIP_RS480))
930#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
931#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
932#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
933
934
935/*
936 * BIOS helpers.
937 */
938#define RBIOS8(i) (rdev->bios[i])
939#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
940#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
941
942int radeon_combios_init(struct radeon_device *rdev);
943void radeon_combios_fini(struct radeon_device *rdev);
944int radeon_atombios_init(struct radeon_device *rdev);
945void radeon_atombios_fini(struct radeon_device *rdev);
946
947
948/*
949 * RING helpers.
950 */
771fe6b9
JG		 951static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
952{
953#if DRM_DEBUG_CODE
954 if (rdev->cp.count_dw <= 0) {
955 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
956 }
957#endif
958 rdev->cp.ring[rdev->cp.wptr++] = v;
959 rdev->cp.wptr &= rdev->cp.ptr_mask;
960 rdev->cp.count_dw--;
961 rdev->cp.ring_free_dw--;
962}
963
964
965/*
966 * ASICs macro.
967 */
068a117c 968#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 969#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
970#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
971#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
771fe6b9 972#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
28d52043 973#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
771fe6b9 974#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
771fe6b9
JG		 975#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
976#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
3ce0a23d 977#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
771fe6b9 978#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
3ce0a23d
JG		 979#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
980#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
771fe6b9
JG		 981#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
982#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
7ed220d7 983#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
771fe6b9
JG		 984#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
985#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
986#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
987#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
7433874e 988#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
771fe6b9 989#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
7433874e 990#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
771fe6b9
JG		 991#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
992#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
993#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
e024e110
DA		 994#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
995#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
c93bb85b 996#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
23956dfa 997#define radeon_hdp_flush(rdev) (rdev)->asic->hdp_flush((rdev))
771fe6b9 998
6cf8a3f5 999/* Common functions */
4aac0473 1000extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
21f9a437
JG		 1001extern int radeon_modeset_init(struct radeon_device *rdev);
1002extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 1003extern bool radeon_card_posted(struct radeon_device *rdev);
72542d77 1004extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437
JG		 1005extern int radeon_clocks_init(struct radeon_device *rdev);
1006extern void radeon_clocks_fini(struct radeon_device *rdev);
1007extern void radeon_scratch_init(struct radeon_device *rdev);
1008extern void radeon_surface_init(struct radeon_device *rdev);
1009extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 1010extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 1011extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
6cf8a3f5 1012
a18d7ea1 1013/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
9f022ddf
JG		 1014struct r100_mc_save {
1015 u32 GENMO_WT;
1016 u32 CRTC_EXT_CNTL;
1017 u32 CRTC_GEN_CNTL;
1018 u32 CRTC2_GEN_CNTL;
1019 u32 CUR_OFFSET;
1020 u32 CUR2_OFFSET;
1021};
1022extern void r100_cp_disable(struct radeon_device *rdev);
1023extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
1024extern void r100_cp_fini(struct radeon_device *rdev);
21f9a437 1025extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
4aac0473
JG		 1026extern int r100_pci_gart_init(struct radeon_device *rdev);
1027extern void r100_pci_gart_fini(struct radeon_device *rdev);
21f9a437
JG		 1028extern int r100_pci_gart_enable(struct radeon_device *rdev);
1029extern void r100_pci_gart_disable(struct radeon_device *rdev);
1030extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
9f022ddf
JG		 1031extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
1032extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
1033extern void r100_ib_fini(struct radeon_device *rdev);
1034extern int r100_ib_init(struct radeon_device *rdev);
1035extern void r100_irq_disable(struct radeon_device *rdev);
1036extern int r100_irq_set(struct radeon_device *rdev);
1037extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1038extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
21f9a437 1039extern void r100_vram_init_sizes(struct radeon_device *rdev);
9f022ddf
JG		 1040extern void r100_wb_disable(struct radeon_device *rdev);
1041extern void r100_wb_fini(struct radeon_device *rdev);
1042extern int r100_wb_init(struct radeon_device *rdev);
d39c3b89
JG		 1043extern void r100_hdp_reset(struct radeon_device *rdev);
1044extern int r100_rb2d_reset(struct radeon_device *rdev);
1045extern int r100_cp_reset(struct radeon_device *rdev);
ca6ffc64 1046extern void r100_vga_render_disable(struct radeon_device *rdev);
207bf9e9
JG		 1047extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1048 struct radeon_cs_packet *pkt,
1049 struct radeon_object *robj);
1050extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1051 struct radeon_cs_packet *pkt,
1052 const unsigned *auth, unsigned n,
1053 radeon_packet0_check_t check);
1054extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
1055 struct radeon_cs_packet *pkt,
1056 unsigned idx);
17e15b0c 1057extern void r100_enable_bm(struct radeon_device *rdev);
9f022ddf 1058
d4550907
JG		 1059/* rv200,rv250,rv280 */
1060extern void r200_set_safe_registers(struct radeon_device *rdev);
9f022ddf
JG		 1061
1062/* r300,r350,rv350,rv370,rv380 */
1063extern void r300_set_reg_safe(struct radeon_device *rdev);
1064extern void r300_mc_program(struct radeon_device *rdev);
1065extern void r300_vram_info(struct radeon_device *rdev);
ca6ffc64
JG		 1066extern void r300_clock_startup(struct radeon_device *rdev);
1067extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
4aac0473
JG		 1068extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1069extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1070extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
9f022ddf 1071extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
a18d7ea1 1072
905b6822 1073/* r420,r423,rv410 */
d39c3b89 1074extern int r420_mc_init(struct radeon_device *rdev);
21f9a437
JG		 1075extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1076extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
9f022ddf 1077extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
d39c3b89 1078extern void r420_pipes_init(struct radeon_device *rdev);
905b6822 1079
21f9a437 1080/* rv515 */
d39c3b89
JG		 1081struct rv515_mc_save {
1082 u32 d1vga_control;
1083 u32 d2vga_control;
1084 u32 vga_render_control;
1085 u32 vga_hdp_control;
1086 u32 d1crtc_control;
1087 u32 d2crtc_control;
1088};
21f9a437 1089extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
d39c3b89
JG		 1090extern void rv515_vga_render_disable(struct radeon_device *rdev);
1091extern void rv515_set_safe_registers(struct radeon_device *rdev);
f0ed1f65
JG		 1092extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1093extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1094extern void rv515_clock_startup(struct radeon_device *rdev);
1095extern void rv515_debugfs(struct radeon_device *rdev);
1096extern int rv515_suspend(struct radeon_device *rdev);
21f9a437 1097
3bc68535
JG		 1098/* rs400 */
1099extern int rs400_gart_init(struct radeon_device *rdev);
1100extern int rs400_gart_enable(struct radeon_device *rdev);
1101extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1102extern void rs400_gart_disable(struct radeon_device *rdev);
1103extern void rs400_gart_fini(struct radeon_device *rdev);
1104
1105/* rs600 */
1106extern void rs600_set_safe_registers(struct radeon_device *rdev);
ac447df4
JG		 1107extern int rs600_irq_set(struct radeon_device *rdev);
1108extern void rs600_irq_disable(struct radeon_device *rdev);
3bc68535 1109
21f9a437
JG		 1110/* rs690, rs740 */
1111extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1112 struct drm_display_mode *mode1,
1113 struct drm_display_mode *mode2);
1114
1115/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1116extern bool r600_card_posted(struct radeon_device *rdev);
1117extern void r600_cp_stop(struct radeon_device *rdev);
1118extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1119extern int r600_cp_resume(struct radeon_device *rdev);
1120extern int r600_count_pipe_bits(uint32_t val);
1121extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1122extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
4aac0473 1123extern int r600_pcie_gart_init(struct radeon_device *rdev);
21f9a437
JG		 1124extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1125extern int r600_ib_test(struct radeon_device *rdev);
1126extern int r600_ring_test(struct radeon_device *rdev);
21f9a437 1127extern void r600_wb_fini(struct radeon_device *rdev);
81cc35bf
JG		 1128extern int r600_wb_enable(struct radeon_device *rdev);
1129extern void r600_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 1130extern void r600_scratch_init(struct radeon_device *rdev);
1131extern int r600_blit_init(struct radeon_device *rdev);
1132extern void r600_blit_fini(struct radeon_device *rdev);
d8f60cfc 1133extern int r600_init_microcode(struct radeon_device *rdev);
fe62e1a4 1134extern int r600_gpu_reset(struct radeon_device *rdev);
d8f60cfc
AD		 1135/* r600 irq */
1136extern int r600_irq_init(struct radeon_device *rdev);
1137extern void r600_irq_fini(struct radeon_device *rdev);
1138extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1139extern int r600_irq_set(struct radeon_device *rdev);
21f9a437 1140
771fe6b9 1141#endif
Linux kernel - Deliverables
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