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Merge branch 'clk' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux...
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
771fe6b9
JG		 96
97/*
98 * Copy from radeon_drv.h so we don't have to include both and have conflicting
99 * symbol;
100 */
101#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
225758d8 102#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 103/* RADEON_IB_POOL_SIZE must be a power of 2 */
771fe6b9
JG		 104#define RADEON_IB_POOL_SIZE 16
105#define RADEON_DEBUGFS_MAX_NUM_FILES 32
106#define RADEONFB_CONN_LIMIT 4
f657c2a7 107#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 108
771fe6b9
JG		 109/*
110 * Errata workarounds.
111 */
112enum radeon_pll_errata {
113 CHIP_ERRATA_R300_CG = 0x00000001,
114 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
115 CHIP_ERRATA_PLL_DELAY = 0x00000004
116};
117
118
119struct radeon_device;
120
121
122/*
123 * BIOS.
124 */
6a9ee8af
DA		 125#define ATRM_BIOS_PAGE 4096
126
8edb381d 127#if defined(CONFIG_VGA_SWITCHEROO)
6a9ee8af
DA		 128bool radeon_atrm_supported(struct pci_dev *pdev);
129int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
8edb381d
DA		 130#else
131static inline bool radeon_atrm_supported(struct pci_dev *pdev)
132{
133 return false;
134}
135
136static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
137 return -EINVAL;
138}
139#endif
771fe6b9
JG		 140bool radeon_get_bios(struct radeon_device *rdev);
141
3ce0a23d 142
771fe6b9 143/*
3ce0a23d 144 * Dummy page
771fe6b9 145 */
3ce0a23d
JG		 146struct radeon_dummy_page {
147 struct page *page;
148 dma_addr_t addr;
149};
150int radeon_dummy_page_init(struct radeon_device *rdev);
151void radeon_dummy_page_fini(struct radeon_device *rdev);
152
771fe6b9 153
3ce0a23d
JG		 154/*
155 * Clocks
156 */
771fe6b9
JG		 157struct radeon_clock {
158 struct radeon_pll p1pll;
159 struct radeon_pll p2pll;
bcc1c2a1 160 struct radeon_pll dcpll;
771fe6b9
JG		 161 struct radeon_pll spll;
162 struct radeon_pll mpll;
163 /* 10 Khz units */
164 uint32_t default_mclk;
165 uint32_t default_sclk;
bcc1c2a1
AD		 166 uint32_t default_dispclk;
167 uint32_t dp_extclk;
b20f9bef 168 uint32_t max_pixel_clock;
771fe6b9
JG		 169};
170
7433874e
RM		 171/*
172 * Power management
173 */
174int radeon_pm_init(struct radeon_device *rdev);
29fb52ca 175void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 176void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 177void radeon_pm_suspend(struct radeon_device *rdev);
178void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 179void radeon_combios_get_power_modes(struct radeon_device *rdev);
180void radeon_atombios_get_power_modes(struct radeon_device *rdev);
8a83ec5e 181void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ee4017f4 182int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage);
f892034a 183void rs690_pm_info(struct radeon_device *rdev);
20d391d7
AD		 184extern int rv6xx_get_temp(struct radeon_device *rdev);
185extern int rv770_get_temp(struct radeon_device *rdev);
186extern int evergreen_get_temp(struct radeon_device *rdev);
187extern int sumo_get_temp(struct radeon_device *rdev);
3ce0a23d 188
771fe6b9
JG		 189/*
190 * Fences.
191 */
192struct radeon_fence_driver {
193 uint32_t scratch_reg;
194 atomic_t seq;
195 uint32_t last_seq;
225758d8
JG		 196 unsigned long last_jiffies;
197 unsigned long last_timeout;
771fe6b9
JG		 198 wait_queue_head_t queue;
199 rwlock_t lock;
200 struct list_head created;
201 struct list_head emited;
202 struct list_head signaled;
0a0c7596 203 bool initialized;
771fe6b9
JG		 204};
205
206struct radeon_fence {
207 struct radeon_device *rdev;
208 struct kref kref;
209 struct list_head list;
210 /* protected by radeon_fence.lock */
211 uint32_t seq;
771fe6b9
JG		 212 bool emited;
213 bool signaled;
214};
215
216int radeon_fence_driver_init(struct radeon_device *rdev);
217void radeon_fence_driver_fini(struct radeon_device *rdev);
218int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
219int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
220void radeon_fence_process(struct radeon_device *rdev);
221bool radeon_fence_signaled(struct radeon_fence *fence);
222int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
223int radeon_fence_wait_next(struct radeon_device *rdev);
224int radeon_fence_wait_last(struct radeon_device *rdev);
225struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
226void radeon_fence_unref(struct radeon_fence **fence);
227
e024e110
DA		 228/*
229 * Tiling registers
230 */
231struct radeon_surface_reg {
4c788679 232 struct radeon_bo *bo;
e024e110
DA		 233};
234
235#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 236
237/*
4c788679 238 * TTM.
771fe6b9 239 */
4c788679
JG		 240struct radeon_mman {
241 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 242 struct drm_global_reference mem_global_ref;
4c788679 243 struct ttm_bo_device bdev;
0a0c7596
JG		 244 bool mem_global_referenced;
245 bool initialized;
4c788679
JG		 246};
247
248struct radeon_bo {
249 /* Protected by gem.mutex */
250 struct list_head list;
251 /* Protected by tbo.reserved */
312ea8da
JG		 252 u32 placements[3];
253 struct ttm_placement placement;
4c788679
JG		 254 struct ttm_buffer_object tbo;
255 struct ttm_bo_kmap_obj kmap;
256 unsigned pin_count;
257 void *kptr;
258 u32 tiling_flags;
259 u32 pitch;
260 int surface_reg;
261 /* Constant after initialization */
262 struct radeon_device *rdev;
441921d5 263 struct drm_gem_object gem_base;
4c788679 264};
7e4d15d9 265#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 266
4c788679 267struct radeon_bo_list {
147666fb 268 struct ttm_validate_buffer tv;
4c788679 269 struct radeon_bo *bo;
771fe6b9
JG		 270 uint64_t gpu_offset;
271 unsigned rdomain;
272 unsigned wdomain;
4c788679 273 u32 tiling_flags;
771fe6b9
JG		 274};
275
771fe6b9
JG		 276/*
277 * GEM objects.
278 */
279struct radeon_gem {
4c788679 280 struct mutex mutex;
771fe6b9
JG		 281 struct list_head objects;
282};
283
284int radeon_gem_init(struct radeon_device *rdev);
285void radeon_gem_fini(struct radeon_device *rdev);
286int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 287 int alignment, int initial_domain,
288 bool discardable, bool kernel,
289 struct drm_gem_object **obj);
771fe6b9
JG		 290int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
291 uint64_t *gpu_addr);
292void radeon_gem_object_unpin(struct drm_gem_object *obj);
293
ff72145b
DA		 294int radeon_mode_dumb_create(struct drm_file *file_priv,
295 struct drm_device *dev,
296 struct drm_mode_create_dumb *args);
297int radeon_mode_dumb_mmap(struct drm_file *filp,
298 struct drm_device *dev,
299 uint32_t handle, uint64_t *offset_p);
300int radeon_mode_dumb_destroy(struct drm_file *file_priv,
301 struct drm_device *dev,
302 uint32_t handle);
771fe6b9
JG		 303
304/*
305 * GART structures, functions & helpers
306 */
307struct radeon_mc;
308
309struct radeon_gart_table_ram {
310 volatile uint32_t *ptr;
311};
312
313struct radeon_gart_table_vram {
4c788679 314 struct radeon_bo *robj;
771fe6b9
JG		 315 volatile uint32_t *ptr;
316};
317
318union radeon_gart_table {
319 struct radeon_gart_table_ram ram;
320 struct radeon_gart_table_vram vram;
321};
322
a77f1718 323#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 324#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 325#define RADEON_GPU_PAGE_SHIFT 12
a77f1718 326
771fe6b9
JG		 327struct radeon_gart {
328 dma_addr_t table_addr;
329 unsigned num_gpu_pages;
330 unsigned num_cpu_pages;
331 unsigned table_size;
332 union radeon_gart_table table;
333 struct page **pages;
334 dma_addr_t *pages_addr;
c39d3516 335 bool *ttm_alloced;
771fe6b9
JG		 336 bool ready;
337};
338
339int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
340void radeon_gart_table_ram_free(struct radeon_device *rdev);
341int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
342void radeon_gart_table_vram_free(struct radeon_device *rdev);
343int radeon_gart_init(struct radeon_device *rdev);
344void radeon_gart_fini(struct radeon_device *rdev);
345void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
346 int pages);
347int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516
KRW		 348 int pages, struct page **pagelist,
349 dma_addr_t *dma_addr);
771fe6b9
JG		 350
351
352/*
353 * GPU MC structures, functions & helpers
354 */
355struct radeon_mc {
356 resource_size_t aper_size;
357 resource_size_t aper_base;
358 resource_size_t agp_base;
7a50f01a
DA		 359 /* for some chips with <= 32MB we need to lie
360 * about vram size near mc fb location */
3ce0a23d 361 u64 mc_vram_size;
d594e46a 362 u64 visible_vram_size;
3ce0a23d
JG		 363 u64 gtt_size;
364 u64 gtt_start;
365 u64 gtt_end;
3ce0a23d
JG		 366 u64 vram_start;
367 u64 vram_end;
771fe6b9 368 unsigned vram_width;
3ce0a23d 369 u64 real_vram_size;
771fe6b9
JG		 370 int vram_mtrr;
371 bool vram_is_ddr;
d594e46a 372 bool igp_sideport_enabled;
8d369bb1 373 u64 gtt_base_align;
771fe6b9
JG		 374};
375
06b6476d
AD		 376bool radeon_combios_sideport_present(struct radeon_device *rdev);
377bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 378
379/*
380 * GPU scratch registers structures, functions & helpers
381 */
382struct radeon_scratch {
383 unsigned num_reg;
724c80e1 384 uint32_t reg_base;
771fe6b9
JG		 385 bool free[32];
386 uint32_t reg[32];
387};
388
389int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
390void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
391
392
393/*
394 * IRQS.
395 */
6f34be50
AD		 396
397struct radeon_unpin_work {
398 struct work_struct work;
399 struct radeon_device *rdev;
400 int crtc_id;
401 struct radeon_fence *fence;
402 struct drm_pending_vblank_event *event;
403 struct radeon_bo *old_rbo;
404 u64 new_crtc_base;
405};
406
407struct r500_irq_stat_regs {
408 u32 disp_int;
409};
410
411struct r600_irq_stat_regs {
412 u32 disp_int;
413 u32 disp_int_cont;
414 u32 disp_int_cont2;
415 u32 d1grph_int;
416 u32 d2grph_int;
417};
418
419struct evergreen_irq_stat_regs {
420 u32 disp_int;
421 u32 disp_int_cont;
422 u32 disp_int_cont2;
423 u32 disp_int_cont3;
424 u32 disp_int_cont4;
425 u32 disp_int_cont5;
426 u32 d1grph_int;
427 u32 d2grph_int;
428 u32 d3grph_int;
429 u32 d4grph_int;
430 u32 d5grph_int;
431 u32 d6grph_int;
432};
433
434union radeon_irq_stat_regs {
435 struct r500_irq_stat_regs r500;
436 struct r600_irq_stat_regs r600;
437 struct evergreen_irq_stat_regs evergreen;
438};
439
771fe6b9
JG		 440struct radeon_irq {
441 bool installed;
442 bool sw_int;
443 /* FIXME: use a define max crtc rather than hardcode it */
45f9a39b 444 bool crtc_vblank_int[6];
6f34be50 445 bool pflip[6];
73a6d3fc 446 wait_queue_head_t vblank_queue;
b500f680
AD		 447 /* FIXME: use defines for max hpd/dacs */
448 bool hpd[6];
2031f77c
AD		 449 bool gui_idle;
450 bool gui_idle_acked;
451 wait_queue_head_t idle_queue;
f2594933
CK		 452 /* FIXME: use defines for max HDMI blocks */
453 bool hdmi[2];
1614f8b1
DA		 454 spinlock_t sw_lock;
455 int sw_refcount;
6f34be50
AD		 456 union radeon_irq_stat_regs stat_regs;
457 spinlock_t pflip_lock[6];
458 int pflip_refcount[6];
771fe6b9
JG		 459};
460
461int radeon_irq_kms_init(struct radeon_device *rdev);
462void radeon_irq_kms_fini(struct radeon_device *rdev);
1614f8b1
DA		 463void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
464void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
6f34be50
AD		 465void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
466void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 467
468/*
469 * CP & ring.
470 */
471struct radeon_ib {
472 struct list_head list;
e821767b 473 unsigned idx;
771fe6b9
JG		 474 uint64_t gpu_addr;
475 struct radeon_fence *fence;
e821767b 476 uint32_t *ptr;
771fe6b9 477 uint32_t length_dw;
e821767b 478 bool free;
771fe6b9
JG		 479};
480
ecb114a1
DA		 481/*
482 * locking -
483 * mutex protects scheduled_ibs, ready, alloc_bm
484 */
771fe6b9
JG		 485struct radeon_ib_pool {
486 struct mutex mutex;
4c788679 487 struct radeon_bo *robj;
9f93ed39 488 struct list_head bogus_ib;
771fe6b9
JG		 489 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
490 bool ready;
e821767b 491 unsigned head_id;
771fe6b9
JG		 492};
493
494struct radeon_cp {
4c788679 495 struct radeon_bo *ring_obj;
771fe6b9
JG		 496 volatile uint32_t *ring;
497 unsigned rptr;
498 unsigned wptr;
499 unsigned wptr_old;
500 unsigned ring_size;
501 unsigned ring_free_dw;
502 int count_dw;
503 uint64_t gpu_addr;
504 uint32_t align_mask;
505 uint32_t ptr_mask;
506 struct mutex mutex;
507 bool ready;
508};
509
d8f60cfc
AD		 510/*
511 * R6xx+ IH ring
512 */
513struct r600_ih {
4c788679 514 struct radeon_bo *ring_obj;
d8f60cfc
AD		 515 volatile uint32_t *ring;
516 unsigned rptr;
517 unsigned wptr;
518 unsigned wptr_old;
519 unsigned ring_size;
520 uint64_t gpu_addr;
d8f60cfc
AD		 521 uint32_t ptr_mask;
522 spinlock_t lock;
523 bool enabled;
524};
525
3ce0a23d 526struct r600_blit {
ff82f052 527 struct mutex mutex;
4c788679 528 struct radeon_bo *shader_obj;
3ce0a23d
JG		 529 u64 shader_gpu_addr;
530 u32 vs_offset, ps_offset;
531 u32 state_offset;
532 u32 state_len;
533 u32 vb_used, vb_total;
534 struct radeon_ib *vb_ib;
535};
536
771fe6b9
JG		 537int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
538void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
539int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
540int radeon_ib_pool_init(struct radeon_device *rdev);
541void radeon_ib_pool_fini(struct radeon_device *rdev);
542int radeon_ib_test(struct radeon_device *rdev);
9f93ed39 543extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
771fe6b9
JG		 544/* Ring access between begin & end cannot sleep */
545void radeon_ring_free_size(struct radeon_device *rdev);
91700f3c 546int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
771fe6b9 547int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
91700f3c 548void radeon_ring_commit(struct radeon_device *rdev);
771fe6b9
JG		 549void radeon_ring_unlock_commit(struct radeon_device *rdev);
550void radeon_ring_unlock_undo(struct radeon_device *rdev);
551int radeon_ring_test(struct radeon_device *rdev);
552int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
553void radeon_ring_fini(struct radeon_device *rdev);
554
555
556/*
557 * CS.
558 */
559struct radeon_cs_reloc {
560 struct drm_gem_object *gobj;
4c788679
JG		 561 struct radeon_bo *robj;
562 struct radeon_bo_list lobj;
771fe6b9
JG		 563 uint32_t handle;
564 uint32_t flags;
565};
566
567struct radeon_cs_chunk {
568 uint32_t chunk_id;
569 uint32_t length_dw;
513bcb46
DA		 570 int kpage_idx[2];
571 uint32_t *kpage[2];
771fe6b9 572 uint32_t *kdata;
513bcb46
DA		 573 void __user *user_ptr;
574 int last_copied_page;
575 int last_page_index;
771fe6b9
JG		 576};
577
578struct radeon_cs_parser {
c8c15ff1 579 struct device *dev;
771fe6b9
JG		 580 struct radeon_device *rdev;
581 struct drm_file *filp;
582 /* chunks */
583 unsigned nchunks;
584 struct radeon_cs_chunk *chunks;
585 uint64_t *chunks_array;
586 /* IB */
587 unsigned idx;
588 /* relocations */
589 unsigned nrelocs;
590 struct radeon_cs_reloc *relocs;
591 struct radeon_cs_reloc **relocs_ptr;
592 struct list_head validated;
593 /* indices of various chunks */
594 int chunk_ib_idx;
595 int chunk_relocs_idx;
596 struct radeon_ib *ib;
597 void *track;
3ce0a23d 598 unsigned family;
513bcb46 599 int parser_error;
771fe6b9
JG		 600};
601
513bcb46
DA		 602extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
603extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
604
605
606static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
607{
608 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
609 u32 pg_idx, pg_offset;
610 u32 idx_value = 0;
611 int new_page;
612
613 pg_idx = (idx * 4) / PAGE_SIZE;
614 pg_offset = (idx * 4) % PAGE_SIZE;
615
616 if (ibc->kpage_idx[0] == pg_idx)
617 return ibc->kpage[0][pg_offset/4];
618 if (ibc->kpage_idx[1] == pg_idx)
619 return ibc->kpage[1][pg_offset/4];
620
621 new_page = radeon_cs_update_pages(p, pg_idx);
622 if (new_page < 0) {
623 p->parser_error = new_page;
624 return 0;
625 }
626
627 idx_value = ibc->kpage[new_page][pg_offset/4];
628 return idx_value;
629}
630
771fe6b9
JG		 631struct radeon_cs_packet {
632 unsigned idx;
633 unsigned type;
634 unsigned reg;
635 unsigned opcode;
636 int count;
637 unsigned one_reg_wr;
638};
639
640typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
641 struct radeon_cs_packet *pkt,
642 unsigned idx, unsigned reg);
643typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
644 struct radeon_cs_packet *pkt);
645
646
647/*
648 * AGP
649 */
650int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 651void radeon_agp_resume(struct radeon_device *rdev);
10b06122 652void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 653void radeon_agp_fini(struct radeon_device *rdev);
654
655
656/*
657 * Writeback
658 */
659struct radeon_wb {
4c788679 660 struct radeon_bo *wb_obj;
771fe6b9
JG		 661 volatile uint32_t *wb;
662 uint64_t gpu_addr;
724c80e1 663 bool enabled;
d0f8a854 664 bool use_event;
771fe6b9
JG		 665};
666
724c80e1
AD		 667#define RADEON_WB_SCRATCH_OFFSET 0
668#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 669#define RADEON_WB_CP1_RPTR_OFFSET 1280
670#define RADEON_WB_CP2_RPTR_OFFSET 1536
724c80e1 671#define R600_WB_IH_WPTR_OFFSET 2048
d0f8a854 672#define R600_WB_EVENT_OFFSET 3072
724c80e1 673
c93bb85b
JG		 674/**
675 * struct radeon_pm - power management datas
676 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
677 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
678 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
679 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
680 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
681 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
682 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
683 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
684 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 685 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 686 * @needed_bandwidth: current bandwidth needs
687 *
688 * It keeps track of various data needed to take powermanagement decision.
25985edc 689 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 690 * Equation between gpu/memory clock and available bandwidth is hw dependent
691 * (type of memory, bus size, efficiency, ...)
692 */
ce8f5370
AD		 693
694enum radeon_pm_method {
695 PM_METHOD_PROFILE,
696 PM_METHOD_DYNPM,
697};
698
699enum radeon_dynpm_state {
700 DYNPM_STATE_DISABLED,
701 DYNPM_STATE_MINIMUM,
702 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 703 DYNPM_STATE_ACTIVE,
704 DYNPM_STATE_SUSPENDED,
c913e23a 705};
ce8f5370
AD		 706enum radeon_dynpm_action {
707 DYNPM_ACTION_NONE,
708 DYNPM_ACTION_MINIMUM,
709 DYNPM_ACTION_DOWNCLOCK,
710 DYNPM_ACTION_UPCLOCK,
711 DYNPM_ACTION_DEFAULT
c913e23a 712};
56278a8e
AD		 713
714enum radeon_voltage_type {
715 VOLTAGE_NONE = 0,
716 VOLTAGE_GPIO,
717 VOLTAGE_VDDC,
718 VOLTAGE_SW
719};
720
0ec0e74f
AD		 721enum radeon_pm_state_type {
722 POWER_STATE_TYPE_DEFAULT,
723 POWER_STATE_TYPE_POWERSAVE,
724 POWER_STATE_TYPE_BATTERY,
725 POWER_STATE_TYPE_BALANCED,
726 POWER_STATE_TYPE_PERFORMANCE,
727};
728
ce8f5370
AD		 729enum radeon_pm_profile_type {
730 PM_PROFILE_DEFAULT,
731 PM_PROFILE_AUTO,
732 PM_PROFILE_LOW,
c9e75b21 733 PM_PROFILE_MID,
ce8f5370
AD		 734 PM_PROFILE_HIGH,
735};
736
737#define PM_PROFILE_DEFAULT_IDX 0
738#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 739#define PM_PROFILE_MID_SH_IDX 2
740#define PM_PROFILE_HIGH_SH_IDX 3
741#define PM_PROFILE_LOW_MH_IDX 4
742#define PM_PROFILE_MID_MH_IDX 5
743#define PM_PROFILE_HIGH_MH_IDX 6
744#define PM_PROFILE_MAX 7
ce8f5370
AD		 745
746struct radeon_pm_profile {
747 int dpms_off_ps_idx;
748 int dpms_on_ps_idx;
749 int dpms_off_cm_idx;
750 int dpms_on_cm_idx;
516d0e46
AD		 751};
752
21a8122a
AD		 753enum radeon_int_thermal_type {
754 THERMAL_TYPE_NONE,
755 THERMAL_TYPE_RV6XX,
756 THERMAL_TYPE_RV770,
757 THERMAL_TYPE_EVERGREEN,
e33df25f 758 THERMAL_TYPE_SUMO,
4fddba1f 759 THERMAL_TYPE_NI,
21a8122a
AD		 760};
761
56278a8e
AD		 762struct radeon_voltage {
763 enum radeon_voltage_type type;
764 /* gpio voltage */
765 struct radeon_gpio_rec gpio;
766 u32 delay; /* delay in usec from voltage drop to sclk change */
767 bool active_high; /* voltage drop is active when bit is high */
768 /* VDDC voltage */
769 u8 vddc_id; /* index into vddc voltage table */
770 u8 vddci_id; /* index into vddci voltage table */
771 bool vddci_enabled;
772 /* r6xx+ sw */
2feea49a
AD		 773 u16 voltage;
774 /* evergreen+ vddci */
775 u16 vddci;
56278a8e
AD		 776};
777
d7311171
AD		 778/* clock mode flags */
779#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
780
56278a8e
AD		 781struct radeon_pm_clock_info {
782 /* memory clock */
783 u32 mclk;
784 /* engine clock */
785 u32 sclk;
786 /* voltage info */
787 struct radeon_voltage voltage;
d7311171 788 /* standardized clock flags */
56278a8e
AD		 789 u32 flags;
790};
791
a48b9b4e 792/* state flags */
d7311171 793#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 794
56278a8e 795struct radeon_power_state {
0ec0e74f 796 enum radeon_pm_state_type type;
56278a8e
AD		 797 /* XXX: use a define for num clock modes */
798 struct radeon_pm_clock_info clock_info[8];
799 /* number of valid clock modes in this power state */
800 int num_clock_modes;
56278a8e 801 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 802 /* standardized state flags */
803 u32 flags;
79daedc9
AD		 804 u32 misc; /* vbios specific flags */
805 u32 misc2; /* vbios specific flags */
806 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 807};
808
27459324
RM		 809/*
810 * Some modes are overclocked by very low value, accept them
811 */
812#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
813
c93bb85b 814struct radeon_pm {
c913e23a 815 struct mutex mutex;
a48b9b4e
AD		 816 u32 active_crtcs;
817 int active_crtc_count;
c913e23a 818 int req_vblank;
839461d3 819 bool vblank_sync;
2031f77c 820 bool gui_idle;
c93bb85b
JG		 821 fixed20_12 max_bandwidth;
822 fixed20_12 igp_sideport_mclk;
823 fixed20_12 igp_system_mclk;
824 fixed20_12 igp_ht_link_clk;
825 fixed20_12 igp_ht_link_width;
826 fixed20_12 k8_bandwidth;
827 fixed20_12 sideport_bandwidth;
828 fixed20_12 ht_bandwidth;
829 fixed20_12 core_bandwidth;
830 fixed20_12 sclk;
f47299c5 831 fixed20_12 mclk;
c93bb85b 832 fixed20_12 needed_bandwidth;
0975b162 833 struct radeon_power_state *power_state;
56278a8e
AD		 834 /* number of valid power states */
835 int num_power_states;
a48b9b4e
AD		 836 int current_power_state_index;
837 int current_clock_mode_index;
838 int requested_power_state_index;
839 int requested_clock_mode_index;
840 int default_power_state_index;
841 u32 current_sclk;
842 u32 current_mclk;
2feea49a
AD		 843 u16 current_vddc;
844 u16 current_vddci;
9ace9f7b
AD		 845 u32 default_sclk;
846 u32 default_mclk;
2feea49a
AD		 847 u16 default_vddc;
848 u16 default_vddci;
29fb52ca 849 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 850 /* selected pm method */
851 enum radeon_pm_method pm_method;
852 /* dynpm power management */
853 struct delayed_work dynpm_idle_work;
854 enum radeon_dynpm_state dynpm_state;
855 enum radeon_dynpm_action dynpm_planned_action;
856 unsigned long dynpm_action_timeout;
857 bool dynpm_can_upclock;
858 bool dynpm_can_downclock;
859 /* profile-based power management */
860 enum radeon_pm_profile_type profile;
861 int profile_index;
862 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 863 /* internal thermal controller on rv6xx+ */
864 enum radeon_int_thermal_type int_thermal_type;
865 struct device *int_hwmon_dev;
c93bb85b
JG		 866};
867
771fe6b9
JG		 868
869/*
870 * Benchmarking
871 */
872void radeon_benchmark(struct radeon_device *rdev);
873
874
ecc0b326
MD		 875/*
876 * Testing
877 */
878void radeon_test_moves(struct radeon_device *rdev);
879
880
771fe6b9
JG		 881/*
882 * Debugfs
883 */
884int radeon_debugfs_add_files(struct radeon_device *rdev,
885 struct drm_info_list *files,
886 unsigned nfiles);
887int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9
JG		 888
889
890/*
891 * ASIC specific functions.
892 */
893struct radeon_asic {
068a117c 894 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 895 void (*fini)(struct radeon_device *rdev);
896 int (*resume)(struct radeon_device *rdev);
897 int (*suspend)(struct radeon_device *rdev);
28d52043 898 void (*vga_set_state)(struct radeon_device *rdev, bool state);
225758d8 899 bool (*gpu_is_lockup)(struct radeon_device *rdev);
a2d07b74 900 int (*asic_reset)(struct radeon_device *rdev);
771fe6b9
JG		 901 void (*gart_tlb_flush)(struct radeon_device *rdev);
902 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
903 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
904 void (*cp_fini)(struct radeon_device *rdev);
905 void (*cp_disable)(struct radeon_device *rdev);
3ce0a23d 906 void (*cp_commit)(struct radeon_device *rdev);
771fe6b9 907 void (*ring_start)(struct radeon_device *rdev);
3ce0a23d
JG		 908 int (*ring_test)(struct radeon_device *rdev);
909 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
771fe6b9
JG		 910 int (*irq_set)(struct radeon_device *rdev);
911 int (*irq_process)(struct radeon_device *rdev);
7ed220d7 912 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 913 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
914 int (*cs_parse)(struct radeon_cs_parser *p);
915 int (*copy_blit)(struct radeon_device *rdev,
916 uint64_t src_offset,
917 uint64_t dst_offset,
003cefe0 918 unsigned num_gpu_pages,
771fe6b9
JG		 919 struct radeon_fence *fence);
920 int (*copy_dma)(struct radeon_device *rdev,
921 uint64_t src_offset,
922 uint64_t dst_offset,
003cefe0 923 unsigned num_gpu_pages,
771fe6b9
JG		 924 struct radeon_fence *fence);
925 int (*copy)(struct radeon_device *rdev,
926 uint64_t src_offset,
927 uint64_t dst_offset,
003cefe0 928 unsigned num_gpu_pages,
771fe6b9 929 struct radeon_fence *fence);
7433874e 930 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
771fe6b9 931 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
7433874e 932 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
771fe6b9 933 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
c836a412 934 int (*get_pcie_lanes)(struct radeon_device *rdev);
771fe6b9
JG		 935 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
936 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
e024e110
DA		 937 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
938 uint32_t tiling_flags, uint32_t pitch,
939 uint32_t offset, uint32_t obj_size);
9479c54f 940 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
c93bb85b 941 void (*bandwidth_update)(struct radeon_device *rdev);
429770b3
AD		 942 void (*hpd_init)(struct radeon_device *rdev);
943 void (*hpd_fini)(struct radeon_device *rdev);
944 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
945 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
062b389c
JG		 946 /* ioctl hw specific callback. Some hw might want to perform special
947 * operation on specific ioctl. For instance on wait idle some hw
948 * might want to perform and HDP flush through MMIO as it seems that
949 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
950 * through ring.
951 */
952 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
def9ba9c 953 bool (*gui_idle)(struct radeon_device *rdev);
ce8f5370 954 /* power management */
49e02b73
AD		 955 void (*pm_misc)(struct radeon_device *rdev);
956 void (*pm_prepare)(struct radeon_device *rdev);
957 void (*pm_finish)(struct radeon_device *rdev);
ce8f5370
AD		 958 void (*pm_init_profile)(struct radeon_device *rdev);
959 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
6f34be50
AD		 960 /* pageflipping */
961 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
962 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
963 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 964};
965
21f9a437
JG		 966/*
967 * Asic structures
968 */
225758d8
JG		 969struct r100_gpu_lockup {
970 unsigned long last_jiffies;
971 u32 last_cp_rptr;
972};
973
551ebd83 974struct r100_asic {
225758d8
JG		 975 const unsigned *reg_safe_bm;
976 unsigned reg_safe_bm_size;
977 u32 hdp_cntl;
978 struct r100_gpu_lockup lockup;
551ebd83
DA		 979};
980
21f9a437 981struct r300_asic {
225758d8
JG		 982 const unsigned *reg_safe_bm;
983 unsigned reg_safe_bm_size;
984 u32 resync_scratch;
985 u32 hdp_cntl;
986 struct r100_gpu_lockup lockup;
21f9a437
JG		 987};
988
989struct r600_asic {
225758d8
JG		 990 unsigned max_pipes;
991 unsigned max_tile_pipes;
992 unsigned max_simds;
993 unsigned max_backends;
994 unsigned max_gprs;
995 unsigned max_threads;
996 unsigned max_stack_entries;
997 unsigned max_hw_contexts;
998 unsigned max_gs_threads;
999 unsigned sx_max_export_size;
1000 unsigned sx_max_export_pos_size;
1001 unsigned sx_max_export_smx_size;
1002 unsigned sq_num_cf_insts;
1003 unsigned tiling_nbanks;
1004 unsigned tiling_npipes;
1005 unsigned tiling_group_size;
e7aeeba6 1006 unsigned tile_config;
e55b9422 1007 unsigned backend_map;
225758d8 1008 struct r100_gpu_lockup lockup;
21f9a437
JG		 1009};
1010
1011struct rv770_asic {
225758d8
JG		 1012 unsigned max_pipes;
1013 unsigned max_tile_pipes;
1014 unsigned max_simds;
1015 unsigned max_backends;
1016 unsigned max_gprs;
1017 unsigned max_threads;
1018 unsigned max_stack_entries;
1019 unsigned max_hw_contexts;
1020 unsigned max_gs_threads;
1021 unsigned sx_max_export_size;
1022 unsigned sx_max_export_pos_size;
1023 unsigned sx_max_export_smx_size;
1024 unsigned sq_num_cf_insts;
1025 unsigned sx_num_of_sets;
1026 unsigned sc_prim_fifo_size;
1027 unsigned sc_hiz_tile_fifo_size;
1028 unsigned sc_earlyz_tile_fifo_fize;
1029 unsigned tiling_nbanks;
1030 unsigned tiling_npipes;
1031 unsigned tiling_group_size;
e7aeeba6 1032 unsigned tile_config;
e55b9422 1033 unsigned backend_map;
225758d8 1034 struct r100_gpu_lockup lockup;
21f9a437
JG		 1035};
1036
32fcdbf4
AD		 1037struct evergreen_asic {
1038 unsigned num_ses;
1039 unsigned max_pipes;
1040 unsigned max_tile_pipes;
1041 unsigned max_simds;
1042 unsigned max_backends;
1043 unsigned max_gprs;
1044 unsigned max_threads;
1045 unsigned max_stack_entries;
1046 unsigned max_hw_contexts;
1047 unsigned max_gs_threads;
1048 unsigned sx_max_export_size;
1049 unsigned sx_max_export_pos_size;
1050 unsigned sx_max_export_smx_size;
1051 unsigned sq_num_cf_insts;
1052 unsigned sx_num_of_sets;
1053 unsigned sc_prim_fifo_size;
1054 unsigned sc_hiz_tile_fifo_size;
1055 unsigned sc_earlyz_tile_fifo_size;
1056 unsigned tiling_nbanks;
1057 unsigned tiling_npipes;
1058 unsigned tiling_group_size;
e7aeeba6 1059 unsigned tile_config;
e55b9422 1060 unsigned backend_map;
17db7042 1061 struct r100_gpu_lockup lockup;
32fcdbf4
AD		 1062};
1063
fecf1d07
AD		 1064struct cayman_asic {
1065 unsigned max_shader_engines;
1066 unsigned max_pipes_per_simd;
1067 unsigned max_tile_pipes;
1068 unsigned max_simds_per_se;
1069 unsigned max_backends_per_se;
1070 unsigned max_texture_channel_caches;
1071 unsigned max_gprs;
1072 unsigned max_threads;
1073 unsigned max_gs_threads;
1074 unsigned max_stack_entries;
1075 unsigned sx_num_of_sets;
1076 unsigned sx_max_export_size;
1077 unsigned sx_max_export_pos_size;
1078 unsigned sx_max_export_smx_size;
1079 unsigned max_hw_contexts;
1080 unsigned sq_num_cf_insts;
1081 unsigned sc_prim_fifo_size;
1082 unsigned sc_hiz_tile_fifo_size;
1083 unsigned sc_earlyz_tile_fifo_size;
1084
1085 unsigned num_shader_engines;
1086 unsigned num_shader_pipes_per_simd;
1087 unsigned num_tile_pipes;
1088 unsigned num_simds_per_se;
1089 unsigned num_backends_per_se;
1090 unsigned backend_disable_mask_per_asic;
1091 unsigned backend_map;
1092 unsigned num_texture_channel_caches;
1093 unsigned mem_max_burst_length_bytes;
1094 unsigned mem_row_size_in_kb;
1095 unsigned shader_engine_tile_size;
1096 unsigned num_gpus;
1097 unsigned multi_gpu_tile_size;
1098
1099 unsigned tile_config;
1100 struct r100_gpu_lockup lockup;
1101};
1102
068a117c
JG		 1103union radeon_asic_config {
1104 struct r300_asic r300;
551ebd83 1105 struct r100_asic r100;
3ce0a23d
JG		 1106 struct r600_asic r600;
1107 struct rv770_asic rv770;
32fcdbf4 1108 struct evergreen_asic evergreen;
fecf1d07 1109 struct cayman_asic cayman;
068a117c
JG		 1110};
1111
0a10c851
DV		 1112/*
1113 * asic initizalization from radeon_asic.c
1114 */
1115void radeon_agp_disable(struct radeon_device *rdev);
1116int radeon_asic_init(struct radeon_device *rdev);
1117
771fe6b9
JG		 1118
1119/*
1120 * IOCTL.
1121 */
1122int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1123 struct drm_file *filp);
1124int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1125 struct drm_file *filp);
1126int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1127 struct drm_file *file_priv);
1128int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1129 struct drm_file *file_priv);
1130int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1131 struct drm_file *file_priv);
1132int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1133 struct drm_file *file_priv);
1134int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1135 struct drm_file *filp);
1136int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1137 struct drm_file *filp);
1138int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1139 struct drm_file *filp);
1140int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1141 struct drm_file *filp);
1142int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 1143int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1144 struct drm_file *filp);
1145int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1146 struct drm_file *filp);
771fe6b9 1147
87cbf8f2
AD		 1148/* VRAM scratch page for HDP bug */
1149struct r700_vram_scratch {
1150 struct radeon_bo *robj;
1151 volatile uint32_t *ptr;
1152};
771fe6b9
JG		 1153
1154/*
1155 * Core structure, functions and helpers.
1156 */
1157typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1158typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1159
1160struct radeon_device {
9f022ddf 1161 struct device *dev;
771fe6b9
JG		 1162 struct drm_device *ddev;
1163 struct pci_dev *pdev;
1164 /* ASIC */
068a117c 1165 union radeon_asic_config config;
771fe6b9
JG		 1166 enum radeon_family family;
1167 unsigned long flags;
1168 int usec_timeout;
1169 enum radeon_pll_errata pll_errata;
1170 int num_gb_pipes;
f779b3e5 1171 int num_z_pipes;
771fe6b9
JG		 1172 int disp_priority;
1173 /* BIOS */
1174 uint8_t *bios;
1175 bool is_atom_bios;
1176 uint16_t bios_header_start;
4c788679 1177 struct radeon_bo *stollen_vga_memory;
771fe6b9 1178 /* Register mmio */
4c9bc75c
DA		 1179 resource_size_t rmmio_base;
1180 resource_size_t rmmio_size;
a0533fbf 1181 void __iomem *rmmio;
771fe6b9
JG		 1182 radeon_rreg_t mc_rreg;
1183 radeon_wreg_t mc_wreg;
1184 radeon_rreg_t pll_rreg;
1185 radeon_wreg_t pll_wreg;
de1b2898 1186 uint32_t pcie_reg_mask;
771fe6b9
JG		 1187 radeon_rreg_t pciep_rreg;
1188 radeon_wreg_t pciep_wreg;
351a52a2
AD		 1189 /* io port */
1190 void __iomem *rio_mem;
1191 resource_size_t rio_mem_size;
771fe6b9
JG		 1192 struct radeon_clock clock;
1193 struct radeon_mc mc;
1194 struct radeon_gart gart;
1195 struct radeon_mode_info mode_info;
1196 struct radeon_scratch scratch;
1197 struct radeon_mman mman;
1198 struct radeon_fence_driver fence_drv;
1199 struct radeon_cp cp;
0c88a02e
AD		 1200 /* cayman compute rings */
1201 struct radeon_cp cp1;
1202 struct radeon_cp cp2;
771fe6b9
JG		 1203 struct radeon_ib_pool ib_pool;
1204 struct radeon_irq irq;
1205 struct radeon_asic *asic;
1206 struct radeon_gem gem;
c93bb85b 1207 struct radeon_pm pm;
f657c2a7 1208 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9
JG		 1209 struct mutex cs_mutex;
1210 struct radeon_wb wb;
3ce0a23d 1211 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 1212 bool gpu_lockup;
1213 bool shutdown;
1214 bool suspend;
ad49f501 1215 bool need_dma32;
733289c2 1216 bool accel_working;
e024e110 1217 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 1218 const struct firmware *me_fw; /* all family ME firmware */
1219 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 1220 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 1221 const struct firmware *mc_fw; /* NI MC firmware */
3ce0a23d 1222 struct r600_blit r600_blit;
87cbf8f2 1223 struct r700_vram_scratch vram_scratch;
3e5cb98d 1224 int msi_enabled; /* msi enabled */
d8f60cfc 1225 struct r600_ih ih; /* r6/700 interrupt ring */
d4877cf2 1226 struct work_struct hotplug_work;
18917b60 1227 int num_crtc; /* number of crtcs */
40bacf16 1228 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
5876dd24 1229 struct mutex vram_mutex;
dafc3bd5
CK		 1230
1231 /* audio stuff */
7eea7e9e 1232 bool audio_enabled;
dafc3bd5
CK		 1233 struct timer_list audio_timer;
1234 int audio_channels;
1235 int audio_rate;
1236 int audio_bits_per_sample;
1237 uint8_t audio_status_bits;
1238 uint8_t audio_category_code;
6a9ee8af 1239
ce8f5370 1240 struct notifier_block acpi_nb;
9eba4a93 1241 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 1242 struct drm_file *hyperz_filp;
9eba4a93 1243 struct drm_file *cmask_filp;
f376b94f
AD		 1244 /* i2c buses */
1245 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
771fe6b9
JG		 1246};
1247
1248int radeon_device_init(struct radeon_device *rdev,
1249 struct drm_device *ddev,
1250 struct pci_dev *pdev,
1251 uint32_t flags);
1252void radeon_device_fini(struct radeon_device *rdev);
1253int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1254
de1b2898
DA		 1255static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1256{
07bec2df 1257 if (reg < rdev->rmmio_size)
a0533fbf 1258 return readl((rdev->rmmio) + reg);
de1b2898 1259 else {
a0533fbf
BH		 1260 writel(reg, (rdev->rmmio) + RADEON_MM_INDEX);
1261 return readl((rdev->rmmio) + RADEON_MM_DATA);
de1b2898
DA		 1262 }
1263}
1264
1265static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1266{
07bec2df 1267 if (reg < rdev->rmmio_size)
a0533fbf 1268 writel(v, (rdev->rmmio) + reg);
de1b2898 1269 else {
a0533fbf
BH		 1270 writel(reg, (rdev->rmmio) + RADEON_MM_INDEX);
1271 writel(v, (rdev->rmmio) + RADEON_MM_DATA);
de1b2898
DA		 1272 }
1273}
1274
351a52a2
AD		 1275static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
1276{
1277 if (reg < rdev->rio_mem_size)
1278 return ioread32(rdev->rio_mem + reg);
1279 else {
1280 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1281 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
1282 }
1283}
1284
1285static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1286{
1287 if (reg < rdev->rio_mem_size)
1288 iowrite32(v, rdev->rio_mem + reg);
1289 else {
1290 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1291 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
1292 }
1293}
1294
4c788679
JG		 1295/*
1296 * Cast helper
1297 */
1298#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 1299
1300/*
1301 * Registers read & write functions.
1302 */
a0533fbf
BH		 1303#define RREG8(reg) readb((rdev->rmmio) + (reg))
1304#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1305#define RREG16(reg) readw((rdev->rmmio) + (reg))
1306#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
de1b2898 1307#define RREG32(reg) r100_mm_rreg(rdev, (reg))
3ce0a23d 1308#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
de1b2898 1309#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
771fe6b9
JG		 1310#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1311#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1312#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1313#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1314#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1315#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 1316#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1317#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
aa5120d2
RM		 1318#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1319#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
771fe6b9
JG		 1320#define WREG32_P(reg, val, mask) \
1321 do { \
1322 uint32_t tmp_ = RREG32(reg); \
1323 tmp_ &= (mask); \
1324 tmp_ |= ((val) & ~(mask)); \
1325 WREG32(reg, tmp_); \
1326 } while (0)
1327#define WREG32_PLL_P(reg, val, mask) \
1328 do { \
1329 uint32_t tmp_ = RREG32_PLL(reg); \
1330 tmp_ &= (mask); \
1331 tmp_ |= ((val) & ~(mask)); \
1332 WREG32_PLL(reg, tmp_); \
1333 } while (0)
3ce0a23d 1334#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
351a52a2
AD		 1335#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1336#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 1337
de1b2898
DA		 1338/*
1339 * Indirect registers accessor
1340 */
1341static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1342{
1343 uint32_t r;
1344
1345 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1346 r = RREG32(RADEON_PCIE_DATA);
1347 return r;
1348}
1349
1350static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1351{
1352 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1353 WREG32(RADEON_PCIE_DATA, (v));
1354}
1355
771fe6b9
JG		 1356void r100_pll_errata_after_index(struct radeon_device *rdev);
1357
1358
1359/*
1360 * ASICs helpers.
1361 */
b995e433
DA		 1362#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1363 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 1364#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1365 (rdev->family == CHIP_RV200) || \
1366 (rdev->family == CHIP_RS100) || \
1367 (rdev->family == CHIP_RS200) || \
1368 (rdev->family == CHIP_RV250) || \
1369 (rdev->family == CHIP_RV280) || \
1370 (rdev->family == CHIP_RS300))
1371#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1372 (rdev->family == CHIP_RV350) || \
1373 (rdev->family == CHIP_R350) || \
1374 (rdev->family == CHIP_RV380) || \
1375 (rdev->family == CHIP_R420) || \
1376 (rdev->family == CHIP_R423) || \
1377 (rdev->family == CHIP_RV410) || \
1378 (rdev->family == CHIP_RS400) || \
1379 (rdev->family == CHIP_RS480))
3313e3d4
AD		 1380#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1381 (rdev->ddev->pdev->device == 0x9443) || \
1382 (rdev->ddev->pdev->device == 0x944B) || \
1383 (rdev->ddev->pdev->device == 0x9506) || \
1384 (rdev->ddev->pdev->device == 0x9509) || \
1385 (rdev->ddev->pdev->device == 0x950F) || \
1386 (rdev->ddev->pdev->device == 0x689C) || \
1387 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 1388#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 1389#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1390 (rdev->family == CHIP_RS690) || \
1391 (rdev->family == CHIP_RS740) || \
1392 (rdev->family >= CHIP_R600))
771fe6b9
JG		 1393#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1394#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 1395#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 1396#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1397 (rdev->flags & RADEON_IS_IGP))
1fe18305 1398#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
771fe6b9
JG		 1399
1400/*
1401 * BIOS helpers.
1402 */
1403#define RBIOS8(i) (rdev->bios[i])
1404#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1405#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1406
1407int radeon_combios_init(struct radeon_device *rdev);
1408void radeon_combios_fini(struct radeon_device *rdev);
1409int radeon_atombios_init(struct radeon_device *rdev);
1410void radeon_atombios_fini(struct radeon_device *rdev);
1411
1412
1413/*
1414 * RING helpers.
1415 */
771fe6b9
JG		 1416static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1417{
1418#if DRM_DEBUG_CODE
1419 if (rdev->cp.count_dw <= 0) {
1420 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1421 }
1422#endif
1423 rdev->cp.ring[rdev->cp.wptr++] = v;
1424 rdev->cp.wptr &= rdev->cp.ptr_mask;
1425 rdev->cp.count_dw--;
1426 rdev->cp.ring_free_dw--;
1427}
1428
1429
1430/*
1431 * ASICs macro.
1432 */
068a117c 1433#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 1434#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1435#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1436#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
771fe6b9 1437#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
28d52043 1438#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
225758d8 1439#define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
a2d07b74 1440#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
771fe6b9
JG		 1441#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1442#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
3ce0a23d 1443#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
771fe6b9 1444#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
3ce0a23d
JG		 1445#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1446#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
771fe6b9
JG		 1447#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1448#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
7ed220d7 1449#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
771fe6b9
JG		 1450#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1451#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1452#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1453#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
7433874e 1454#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
771fe6b9 1455#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
7433874e 1456#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
93e7de7b 1457#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
c836a412 1458#define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
771fe6b9
JG		 1459#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1460#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
e024e110
DA		 1461#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1462#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
c93bb85b 1463#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
429770b3
AD		 1464#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1465#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1466#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1467#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
def9ba9c 1468#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a424816f
AD		 1469#define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1470#define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1471#define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
ce8f5370
AD		 1472#define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1473#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
6f34be50
AD		 1474#define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc))
1475#define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base))
1476#define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc))
771fe6b9 1477
6cf8a3f5 1478/* Common functions */
700a0cc0 1479/* AGP */
90aca4d2 1480extern int radeon_gpu_reset(struct radeon_device *rdev);
700a0cc0 1481extern void radeon_agp_disable(struct radeon_device *rdev);
4aac0473 1482extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
82568565 1483extern void radeon_gart_restore(struct radeon_device *rdev);
21f9a437
JG		 1484extern int radeon_modeset_init(struct radeon_device *rdev);
1485extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 1486extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 1487extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 1488extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 1489extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 1490extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 1491extern void radeon_wb_fini(struct radeon_device *rdev);
1492extern int radeon_wb_init(struct radeon_device *rdev);
1493extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 1494extern void radeon_surface_init(struct radeon_device *rdev);
1495extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 1496extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 1497extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 1498extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 1499extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 1500extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1501extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
6a9ee8af
DA		 1502extern int radeon_resume_kms(struct drm_device *dev);
1503extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
53595338 1504extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
6cf8a3f5 1505
3574dda4
DV		 1506/*
1507 * r600 functions used by radeon_encoder.c
1508 */
2cd6218c
RM		 1509extern void r600_hdmi_enable(struct drm_encoder *encoder);
1510extern void r600_hdmi_disable(struct drm_encoder *encoder);
dafc3bd5 1511extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
fe251e2f 1512
0af62b01 1513extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 1514extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 1515
d7a2952f
AM		 1516/* radeon_acpi.c */
1517#if defined(CONFIG_ACPI)
1518extern int radeon_acpi_init(struct radeon_device *rdev);
1519#else
1520static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1521#endif
1522
4c788679
JG		 1523#include "radeon_object.h"
1524
771fe6b9 1525#endif
Linux kernel - Deliverables
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