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radeon/audio: defined initial audio interface that gets initialized via detect()...
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
0aea5e4a 67#include <linux/interval_tree.h>
341cb9e4 68#include <linux/hashtable.h>
954605ca 69#include <linux/fence.h>
771fe6b9 70
4c788679
JG		 71#include <ttm/ttm_bo_api.h>
72#include <ttm/ttm_bo_driver.h>
73#include <ttm/ttm_placement.h>
74#include <ttm/ttm_module.h>
147666fb 75#include <ttm/ttm_execbuf_util.h>
4c788679 76
d9fc9413
DV		 77#include <drm/drm_gem.h>
78
c2142715 79#include "radeon_family.h"
771fe6b9
JG		 80#include "radeon_mode.h"
81#include "radeon_reg.h"
771fe6b9
JG		 82
83/*
84 * Modules parameters.
85 */
86extern int radeon_no_wb;
87extern int radeon_modeset;
88extern int radeon_dynclks;
89extern int radeon_r4xx_atom;
90extern int radeon_agpmode;
91extern int radeon_vram_limit;
92extern int radeon_gart_size;
93extern int radeon_benchmarking;
ecc0b326 94extern int radeon_testing;
771fe6b9 95extern int radeon_connector_table;
4ce001ab 96extern int radeon_tv;
dafc3bd5 97extern int radeon_audio;
f46c0120 98extern int radeon_disp_priority;
e2b0a8e1 99extern int radeon_hw_i2c;
d42dd579 100extern int radeon_pcie_gen2;
a18cee15 101extern int radeon_msi;
3368ff0c 102extern int radeon_lockup_timeout;
a0a53aa8 103extern int radeon_fastfb;
da321c8a 104extern int radeon_dpm;
1294d4a3 105extern int radeon_aspm;
10ebc0bc 106extern int radeon_runtime_pm;
363eb0b4 107extern int radeon_hard_reset;
c1c44132 108extern int radeon_vm_size;
4510fb98 109extern int radeon_vm_block_size;
a624f429 110extern int radeon_deep_color;
39dc5454 111extern int radeon_use_pflipirq;
6e909f74 112extern int radeon_bapm;
bc13018b 113extern int radeon_backlight;
771fe6b9
JG		 114
115/*
116 * Copy from radeon_drv.h so we don't have to include both and have conflicting
117 * symbol;
118 */
bb635567
JG		 119#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
120#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 121/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 122#define RADEON_IB_POOL_SIZE 16
123#define RADEON_DEBUGFS_MAX_COMPONENTS 32
124#define RADEONFB_CONN_LIMIT 4
125#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 126
1b37078b
AD		 127/* internal ring indices */
128/* r1xx+ has gfx CP ring */
d93f7937 129#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 130
131/* cayman has 2 compute CP rings */
d93f7937
CK		 132#define CAYMAN_RING_TYPE_CP1_INDEX 1
133#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 134
4d75658b
AD		 135/* R600+ has an async dma ring */
136#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 137/* cayman add a second async dma ring */
138#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 139
f2ba57b5 140/* R600+ */
d93f7937
CK		 141#define R600_RING_TYPE_UVD_INDEX 5
142
143/* TN+ */
144#define TN_RING_TYPE_VCE1_INDEX 6
145#define TN_RING_TYPE_VCE2_INDEX 7
146
147/* max number of rings */
148#define RADEON_NUM_RINGS 8
f2ba57b5 149
1c61eae4
CK		 150/* number of hw syncs before falling back on blocking */
151#define RADEON_NUM_SYNCS 4
f2ba57b5 152
721604a1 153/* hardcode those limit for now */
ca19f21e 154#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 155#define RADEON_VA_RESERVED_SIZE (8 << 20)
156#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 157
1a0041b8
AD		 158/* hard reset data */
159#define RADEON_ASIC_RESET_DATA 0x39d5e86b
160
ec46c76d
AD		 161/* reset flags */
162#define RADEON_RESET_GFX (1 << 0)
163#define RADEON_RESET_COMPUTE (1 << 1)
164#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 165#define RADEON_RESET_CP (1 << 3)
166#define RADEON_RESET_GRBM (1 << 4)
167#define RADEON_RESET_DMA1 (1 << 5)
168#define RADEON_RESET_RLC (1 << 6)
169#define RADEON_RESET_SEM (1 << 7)
170#define RADEON_RESET_IH (1 << 8)
171#define RADEON_RESET_VMC (1 << 9)
172#define RADEON_RESET_MC (1 << 10)
173#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 174
22c775ce
AD		 175/* CG block flags */
176#define RADEON_CG_BLOCK_GFX (1 << 0)
177#define RADEON_CG_BLOCK_MC (1 << 1)
178#define RADEON_CG_BLOCK_SDMA (1 << 2)
179#define RADEON_CG_BLOCK_UVD (1 << 3)
180#define RADEON_CG_BLOCK_VCE (1 << 4)
181#define RADEON_CG_BLOCK_HDP (1 << 5)
e16866ec 182#define RADEON_CG_BLOCK_BIF (1 << 6)
22c775ce 183
64d8a728
AD		 184/* CG flags */
185#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
186#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
187#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
188#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
189#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
190#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
191#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
192#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
193#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
194#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
195#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
196#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
197#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
198#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
199#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
200#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
201#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
202
203/* PG flags */
2b19d17f 204#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
64d8a728
AD		 205#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
206#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
207#define RADEON_PG_SUPPORT_UVD (1 << 3)
208#define RADEON_PG_SUPPORT_VCE (1 << 4)
209#define RADEON_PG_SUPPORT_CP (1 << 5)
210#define RADEON_PG_SUPPORT_GDS (1 << 6)
211#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
212#define RADEON_PG_SUPPORT_SDMA (1 << 8)
213#define RADEON_PG_SUPPORT_ACP (1 << 9)
214#define RADEON_PG_SUPPORT_SAMU (1 << 10)
215
9e05fa1d
AD		 216/* max cursor sizes (in pixels) */
217#define CURSOR_WIDTH 64
218#define CURSOR_HEIGHT 64
219
220#define CIK_CURSOR_WIDTH 128
221#define CIK_CURSOR_HEIGHT 128
222
771fe6b9
JG		 223/*
224 * Errata workarounds.
225 */
226enum radeon_pll_errata {
227 CHIP_ERRATA_R300_CG = 0x00000001,
228 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
229 CHIP_ERRATA_PLL_DELAY = 0x00000004
230};
231
232
233struct radeon_device;
234
235
236/*
237 * BIOS.
238 */
239bool radeon_get_bios(struct radeon_device *rdev);
240
241/*
3ce0a23d 242 * Dummy page
771fe6b9 243 */
3ce0a23d
JG		 244struct radeon_dummy_page {
245 struct page *page;
246 dma_addr_t addr;
247};
248int radeon_dummy_page_init(struct radeon_device *rdev);
249void radeon_dummy_page_fini(struct radeon_device *rdev);
250
771fe6b9 251
3ce0a23d
JG		 252/*
253 * Clocks
254 */
771fe6b9
JG		 255struct radeon_clock {
256 struct radeon_pll p1pll;
257 struct radeon_pll p2pll;
bcc1c2a1 258 struct radeon_pll dcpll;
771fe6b9
JG		 259 struct radeon_pll spll;
260 struct radeon_pll mpll;
261 /* 10 Khz units */
262 uint32_t default_mclk;
263 uint32_t default_sclk;
bcc1c2a1 264 uint32_t default_dispclk;
4489cd62 265 uint32_t current_dispclk;
bcc1c2a1 266 uint32_t dp_extclk;
b20f9bef 267 uint32_t max_pixel_clock;
771fe6b9
JG		 268};
269
7433874e
RM		 270/*
271 * Power management
272 */
273int radeon_pm_init(struct radeon_device *rdev);
914a8987 274int radeon_pm_late_init(struct radeon_device *rdev);
29fb52ca 275void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 276void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 277void radeon_pm_suspend(struct radeon_device *rdev);
278void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 279void radeon_combios_get_power_modes(struct radeon_device *rdev);
280void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 281int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
282 u8 clock_type,
283 u32 clock,
284 bool strobe_mode,
285 struct atom_clock_dividers *dividers);
eaa778af
AD		 286int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
287 u32 clock,
288 bool strobe_mode,
289 struct atom_mpll_param *mpll_param);
8a83ec5e 290void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 291int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
292 u16 voltage_level, u8 voltage_type,
293 u32 *gpio_value, u32 *gpio_mask);
294void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
295 u32 eng_clock, u32 mem_clock);
296int radeon_atom_get_voltage_step(struct radeon_device *rdev,
297 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 298int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
299 u16 voltage_id, u16 *voltage);
beb79f40
AD		 300int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
301 u16 *voltage,
302 u16 leakage_idx);
cc8dbbb4
AD		 303int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
304 u16 *leakage_id);
305int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
306 u16 *vddc, u16 *vddci,
307 u16 virtual_voltage_id,
308 u16 vbios_voltage_id);
e9f274b2
AD		 309int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
310 u16 virtual_voltage_id,
311 u16 *voltage);
ae5b0abb
AD		 312int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
313 u8 voltage_type,
314 u16 nominal_voltage,
315 u16 *true_voltage);
316int radeon_atom_get_min_voltage(struct radeon_device *rdev,
317 u8 voltage_type, u16 *min_voltage);
318int radeon_atom_get_max_voltage(struct radeon_device *rdev,
319 u8 voltage_type, u16 *max_voltage);
320int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 321 u8 voltage_type, u8 voltage_mode,
ae5b0abb 322 struct atom_voltage_table *voltage_table);
58653abd
AD		 323bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
324 u8 voltage_type, u8 voltage_mode);
636e2582
AD		 325int radeon_atom_get_svi2_info(struct radeon_device *rdev,
326 u8 voltage_type,
327 u8 *svd_gpio_id, u8 *svc_gpio_id);
ae5b0abb
AD		 328void radeon_atom_update_memory_dll(struct radeon_device *rdev,
329 u32 mem_clock);
330void radeon_atom_set_ac_timing(struct radeon_device *rdev,
331 u32 mem_clock);
332int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
333 u8 module_index,
334 struct atom_mc_reg_table *reg_table);
335int radeon_atom_get_memory_info(struct radeon_device *rdev,
336 u8 module_index, struct atom_memory_info *mem_info);
337int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
338 bool gddr5, u8 module_index,
339 struct atom_memory_clock_range_table *mclk_range_table);
340int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
341 u16 voltage_id, u16 *voltage);
f892034a 342void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 343extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
344 unsigned *bankh, unsigned *mtaspect,
345 unsigned *tile_split);
3ce0a23d 346
771fe6b9
JG		 347/*
348 * Fences.
349 */
350struct radeon_fence_driver {
0bfa4b41 351 struct radeon_device *rdev;
771fe6b9 352 uint32_t scratch_reg;
30eb77f4
JG		 353 uint64_t gpu_addr;
354 volatile uint32_t *cpu_addr;
68e250b7
CK		 355 /* sync_seq is protected by ring emission lock */
356 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 357 atomic64_t last_seq;
954605ca 358 bool initialized, delayed_irq;
0bfa4b41 359 struct delayed_work lockup_work;
771fe6b9
JG		 360};
361
362struct radeon_fence {
ad1a58a4 363 struct fence base;
954605ca 364
ad1a58a4
CK		 365 struct radeon_device *rdev;
366 uint64_t seq;
7465280c 367 /* RB, DMA, etc. */
ad1a58a4
CK		 368 unsigned ring;
369 bool is_vm_update;
954605ca 370
ad1a58a4 371 wait_queue_t fence_wake;
771fe6b9
JG		 372};
373
30eb77f4
JG		 374int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
375int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 376void radeon_fence_driver_fini(struct radeon_device *rdev);
eb98c709 377void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
876dc9f3 378int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 379void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 380bool radeon_fence_signaled(struct radeon_fence *fence);
381int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
37615527
CK		 382int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
383int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
0085c950
JG		 384int radeon_fence_wait_any(struct radeon_device *rdev,
385 struct radeon_fence **fences,
386 bool intr);
771fe6b9
JG		 387struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
388void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 389unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 390bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
391void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
392static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
393 struct radeon_fence *b)
394{
395 if (!a) {
396 return b;
397 }
398
399 if (!b) {
400 return a;
401 }
402
403 BUG_ON(a->ring != b->ring);
404
405 if (a->seq > b->seq) {
406 return a;
407 } else {
408 return b;
409 }
410}
771fe6b9 411
ee60e29f
CK		 412static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
413 struct radeon_fence *b)
414{
415 if (!a) {
416 return false;
417 }
418
419 if (!b) {
420 return true;
421 }
422
423 BUG_ON(a->ring != b->ring);
424
425 return a->seq < b->seq;
426}
427
e024e110
DA		 428/*
429 * Tiling registers
430 */
431struct radeon_surface_reg {
4c788679 432 struct radeon_bo *bo;
e024e110
DA		 433};
434
435#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 436
437/*
4c788679 438 * TTM.
771fe6b9 439 */
4c788679
JG		 440struct radeon_mman {
441 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 442 struct drm_global_reference mem_global_ref;
4c788679 443 struct ttm_bo_device bdev;
0a0c7596
JG		 444 bool mem_global_referenced;
445 bool initialized;
2014b569
CK		 446
447#if defined(CONFIG_DEBUG_FS)
448 struct dentry *vram;
dd66d20e 449 struct dentry *gtt;
2014b569 450#endif
4c788679
JG		 451};
452
1d0c0942
CK		 453struct radeon_bo_list {
454 struct radeon_bo *robj;
455 struct ttm_validate_buffer tv;
456 uint64_t gpu_offset;
457 unsigned prefered_domains;
458 unsigned allowed_domains;
459 uint32_t tiling_flags;
460};
461
721604a1
JG		 462/* bo virtual address in a specific vm */
463struct radeon_bo_va {
e971bd5e 464 /* protected by bo being reserved */
721604a1 465 struct list_head bo_list;
721604a1 466 uint32_t flags;
e31ad969 467 uint64_t addr;
94214635 468 struct radeon_fence *last_pt_update;
e971bd5e
CK		 469 unsigned ref_count;
470
471 /* protected by vm mutex */
0aea5e4a 472 struct interval_tree_node it;
036bf46a 473 struct list_head vm_status;
e971bd5e
CK		 474
475 /* constant after initialization */
476 struct radeon_vm *vm;
477 struct radeon_bo *bo;
721604a1
JG		 478};
479
4c788679
JG		 480struct radeon_bo {
481 /* Protected by gem.mutex */
482 struct list_head list;
483 /* Protected by tbo.reserved */
bda72d58 484 u32 initial_domain;
c9da4a4b 485 struct ttm_place placements[4];
312ea8da 486 struct ttm_placement placement;
4c788679
JG		 487 struct ttm_buffer_object tbo;
488 struct ttm_bo_kmap_obj kmap;
02376d82 489 u32 flags;
4c788679
JG		 490 unsigned pin_count;
491 void *kptr;
492 u32 tiling_flags;
493 u32 pitch;
494 int surface_reg;
721604a1
JG		 495 /* list of all virtual address to which this bo
496 * is associated to
497 */
498 struct list_head va;
4c788679
JG		 499 /* Constant after initialization */
500 struct radeon_device *rdev;
441921d5 501 struct drm_gem_object gem_base;
63bc620b 502
409851f4
JG		 503 struct ttm_bo_kmap_obj dma_buf_vmap;
504 pid_t pid;
341cb9e4
CK		 505
506 struct radeon_mn *mn;
507 struct interval_tree_node mn_it;
4c788679 508};
7e4d15d9 509#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 510
409851f4
JG		 511int radeon_gem_debugfs_init(struct radeon_device *rdev);
512
b15ba512
JG		 513/* sub-allocation manager, it has to be protected by another lock.
514 * By conception this is an helper for other part of the driver
515 * like the indirect buffer or semaphore, which both have their
516 * locking.
517 *
518 * Principe is simple, we keep a list of sub allocation in offset
519 * order (first entry has offset == 0, last entry has the highest
520 * offset).
521 *
522 * When allocating new object we first check if there is room at
523 * the end total_size - (last_object_offset + last_object_size) >=
524 * alloc_size. If so we allocate new object there.
525 *
526 * When there is not enough room at the end, we start waiting for
527 * each sub object until we reach object_offset+object_size >=
528 * alloc_size, this object then become the sub object we return.
529 *
530 * Alignment can't be bigger than page size.
531 *
532 * Hole are not considered for allocation to keep things simple.
533 * Assumption is that there won't be hole (all object on same
534 * alignment).
535 */
536struct radeon_sa_manager {
bfb38d35 537 wait_queue_head_t wq;
b15ba512 538 struct radeon_bo *bo;
c3b7fe8b
CK		 539 struct list_head *hole;
540 struct list_head flist[RADEON_NUM_RINGS];
541 struct list_head olist;
b15ba512
JG		 542 unsigned size;
543 uint64_t gpu_addr;
544 void *cpu_ptr;
545 uint32_t domain;
6c4f978b 546 uint32_t align;
b15ba512
JG		 547};
548
549struct radeon_sa_bo;
550
551/* sub-allocation buffer */
552struct radeon_sa_bo {
c3b7fe8b
CK		 553 struct list_head olist;
554 struct list_head flist;
b15ba512 555 struct radeon_sa_manager *manager;
e6661a96
CK		 556 unsigned soffset;
557 unsigned eoffset;
557017a0 558 struct radeon_fence *fence;
b15ba512
JG		 559};
560
771fe6b9
JG		 561/*
562 * GEM objects.
563 */
564struct radeon_gem {
4c788679 565 struct mutex mutex;
771fe6b9
JG		 566 struct list_head objects;
567};
568
569int radeon_gem_init(struct radeon_device *rdev);
570void radeon_gem_fini(struct radeon_device *rdev);
391bfec3 571int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
4c788679 572 int alignment, int initial_domain,
ed5cb43f 573 u32 flags, bool kernel,
4c788679 574 struct drm_gem_object **obj);
771fe6b9 575
ff72145b
DA		 576int radeon_mode_dumb_create(struct drm_file *file_priv,
577 struct drm_device *dev,
578 struct drm_mode_create_dumb *args);
579int radeon_mode_dumb_mmap(struct drm_file *filp,
580 struct drm_device *dev,
581 uint32_t handle, uint64_t *offset_p);
771fe6b9 582
c1341e52
JG		 583/*
584 * Semaphores.
585 */
c1341e52 586struct radeon_semaphore {
975700d2
CK		 587 struct radeon_sa_bo *sa_bo;
588 signed waiters;
589 uint64_t gpu_addr;
c1341e52
JG		 590};
591
c1341e52
JG		 592int radeon_semaphore_create(struct radeon_device *rdev,
593 struct radeon_semaphore **semaphore);
1654b817 594bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
c1341e52 595 struct radeon_semaphore *semaphore);
1654b817 596bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
c1341e52
JG		 597 struct radeon_semaphore *semaphore);
598void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 599 struct radeon_semaphore **semaphore,
a8c05940 600 struct radeon_fence *fence);
c1341e52 601
975700d2
CK		 602/*
603 * Synchronization
604 */
605struct radeon_sync {
606 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
607 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
ad1a58a4 608 struct radeon_fence *last_vm_update;
975700d2
CK		 609};
610
611void radeon_sync_create(struct radeon_sync *sync);
612void radeon_sync_fence(struct radeon_sync *sync,
613 struct radeon_fence *fence);
614int radeon_sync_resv(struct radeon_device *rdev,
615 struct radeon_sync *sync,
616 struct reservation_object *resv,
617 bool shared);
618int radeon_sync_rings(struct radeon_device *rdev,
619 struct radeon_sync *sync,
620 int waiting_ring);
621void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
622 struct radeon_fence *fence);
623
771fe6b9
JG		 624/*
625 * GART structures, functions & helpers
626 */
627struct radeon_mc;
628
a77f1718 629#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 630#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 631#define RADEON_GPU_PAGE_SHIFT 12
721604a1 632#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 633
77497f27
MD		 634#define RADEON_GART_PAGE_DUMMY 0
635#define RADEON_GART_PAGE_VALID (1 << 0)
636#define RADEON_GART_PAGE_READ (1 << 1)
637#define RADEON_GART_PAGE_WRITE (1 << 2)
638#define RADEON_GART_PAGE_SNOOP (1 << 3)
639
771fe6b9
JG		 640struct radeon_gart {
641 dma_addr_t table_addr;
c9a1be96
JG		 642 struct radeon_bo *robj;
643 void *ptr;
771fe6b9
JG		 644 unsigned num_gpu_pages;
645 unsigned num_cpu_pages;
646 unsigned table_size;
771fe6b9
JG		 647 struct page **pages;
648 dma_addr_t *pages_addr;
649 bool ready;
650};
651
652int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
653void radeon_gart_table_ram_free(struct radeon_device *rdev);
654int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
655void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 656int radeon_gart_table_vram_pin(struct radeon_device *rdev);
657void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 658int radeon_gart_init(struct radeon_device *rdev);
659void radeon_gart_fini(struct radeon_device *rdev);
660void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
661 int pages);
662int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516 663 int pages, struct page **pagelist,
77497f27 664 dma_addr_t *dma_addr, uint32_t flags);
771fe6b9
JG		 665
666
667/*
668 * GPU MC structures, functions & helpers
669 */
670struct radeon_mc {
671 resource_size_t aper_size;
672 resource_size_t aper_base;
673 resource_size_t agp_base;
7a50f01a
DA		 674 /* for some chips with <= 32MB we need to lie
675 * about vram size near mc fb location */
3ce0a23d 676 u64 mc_vram_size;
d594e46a 677 u64 visible_vram_size;
3ce0a23d
JG		 678 u64 gtt_size;
679 u64 gtt_start;
680 u64 gtt_end;
3ce0a23d
JG		 681 u64 vram_start;
682 u64 vram_end;
771fe6b9 683 unsigned vram_width;
3ce0a23d 684 u64 real_vram_size;
771fe6b9
JG		 685 int vram_mtrr;
686 bool vram_is_ddr;
d594e46a 687 bool igp_sideport_enabled;
8d369bb1 688 u64 gtt_base_align;
9ed8b1f9 689 u64 mc_mask;
771fe6b9
JG		 690};
691
06b6476d
AD		 692bool radeon_combios_sideport_present(struct radeon_device *rdev);
693bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 694
695/*
696 * GPU scratch registers structures, functions & helpers
697 */
698struct radeon_scratch {
699 unsigned num_reg;
724c80e1 700 uint32_t reg_base;
771fe6b9
JG		 701 bool free[32];
702 uint32_t reg[32];
703};
704
705int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
706void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
707
75efdee1
AD		 708/*
709 * GPU doorbell structures, functions & helpers
710 */
d5754ab8
AL		 711#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
712
75efdee1 713struct radeon_doorbell {
75efdee1 714 /* doorbell mmio */
d5754ab8
AL		 715 resource_size_t base;
716 resource_size_t size;
717 u32 __iomem *ptr;
718 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
719 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
75efdee1
AD		 720};
721
722int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
723void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
ebff8453
OG		 724void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
725 phys_addr_t *aperture_base,
726 size_t *aperture_size,
727 size_t *start_offset);
771fe6b9
JG		 728
729/*
730 * IRQS.
731 */
6f34be50 732
fa7f517c
CK		 733struct radeon_flip_work {
734 struct work_struct flip_work;
735 struct work_struct unpin_work;
736 struct radeon_device *rdev;
737 int crtc_id;
c60381bd 738 uint64_t base;
6f34be50 739 struct drm_pending_vblank_event *event;
fa7f517c 740 struct radeon_bo *old_rbo;
a0e84764 741 struct fence *fence;
6f34be50
AD		 742};
743
744struct r500_irq_stat_regs {
745 u32 disp_int;
f122c610 746 u32 hdmi0_status;
6f34be50
AD		 747};
748
749struct r600_irq_stat_regs {
750 u32 disp_int;
751 u32 disp_int_cont;
752 u32 disp_int_cont2;
753 u32 d1grph_int;
754 u32 d2grph_int;
f122c610
AD		 755 u32 hdmi0_status;
756 u32 hdmi1_status;
6f34be50
AD		 757};
758
759struct evergreen_irq_stat_regs {
760 u32 disp_int;
761 u32 disp_int_cont;
762 u32 disp_int_cont2;
763 u32 disp_int_cont3;
764 u32 disp_int_cont4;
765 u32 disp_int_cont5;
766 u32 d1grph_int;
767 u32 d2grph_int;
768 u32 d3grph_int;
769 u32 d4grph_int;
770 u32 d5grph_int;
771 u32 d6grph_int;
f122c610
AD		 772 u32 afmt_status1;
773 u32 afmt_status2;
774 u32 afmt_status3;
775 u32 afmt_status4;
776 u32 afmt_status5;
777 u32 afmt_status6;
6f34be50
AD		 778};
779
a59781bb
AD		 780struct cik_irq_stat_regs {
781 u32 disp_int;
782 u32 disp_int_cont;
783 u32 disp_int_cont2;
784 u32 disp_int_cont3;
785 u32 disp_int_cont4;
786 u32 disp_int_cont5;
787 u32 disp_int_cont6;
f5d636d2
CK		 788 u32 d1grph_int;
789 u32 d2grph_int;
790 u32 d3grph_int;
791 u32 d4grph_int;
792 u32 d5grph_int;
793 u32 d6grph_int;
a59781bb
AD		 794};
795
6f34be50
AD		 796union radeon_irq_stat_regs {
797 struct r500_irq_stat_regs r500;
798 struct r600_irq_stat_regs r600;
799 struct evergreen_irq_stat_regs evergreen;
a59781bb 800 struct cik_irq_stat_regs cik;
6f34be50
AD		 801};
802
771fe6b9 803struct radeon_irq {
fb98257a
CK		 804 bool installed;
805 spinlock_t lock;
736fc37f 806 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 807 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 808 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 809 wait_queue_head_t vblank_queue;
810 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 811 bool afmt[RADEON_MAX_AFMT_BLOCKS];
812 union radeon_irq_stat_regs stat_regs;
4a6369e9 813 bool dpm_thermal;
771fe6b9
JG		 814};
815
816int radeon_irq_kms_init(struct radeon_device *rdev);
817void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b 818void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
954605ca 819bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
1b37078b 820void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 821void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
822void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 823void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
824void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
825void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
826void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 827
828/*
e32eb50d 829 * CP & rings.
771fe6b9 830 */
7465280c 831
771fe6b9 832struct radeon_ib {
68470ae7
JG		 833 struct radeon_sa_bo *sa_bo;
834 uint32_t length_dw;
835 uint64_t gpu_addr;
836 uint32_t *ptr;
876dc9f3 837 int ring;
68470ae7 838 struct radeon_fence *fence;
4bf3dd92 839 struct radeon_vm *vm;
68470ae7 840 bool is_const_ib;
975700d2 841 struct radeon_sync sync;
771fe6b9
JG		 842};
843
e32eb50d 844struct radeon_ring {
4c788679 845 struct radeon_bo *ring_obj;
771fe6b9 846 volatile uint32_t *ring;
5596a9db 847 unsigned rptr_offs;
45df6803 848 unsigned rptr_save_reg;
89d35807
AD		 849 u64 next_rptr_gpu_addr;
850 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 851 unsigned wptr;
852 unsigned wptr_old;
853 unsigned ring_size;
854 unsigned ring_free_dw;
855 int count_dw;
aee4aa73
CK		 856 atomic_t last_rptr;
857 atomic64_t last_activity;
771fe6b9
JG		 858 uint64_t gpu_addr;
859 uint32_t align_mask;
860 uint32_t ptr_mask;
771fe6b9 861 bool ready;
78c5560a 862 u32 nop;
8b25ed34 863 u32 idx;
5f0839c1
JG		 864 u64 last_semaphore_signal_addr;
865 u64 last_semaphore_wait_addr;
963e81f9
AD		 866 /* for CIK queues */
867 u32 me;
868 u32 pipe;
869 u32 queue;
870 struct radeon_bo *mqd_obj;
d5754ab8 871 u32 doorbell_index;
963e81f9
AD		 872 unsigned wptr_offs;
873};
874
875struct radeon_mec {
876 struct radeon_bo *hpd_eop_obj;
877 u64 hpd_eop_gpu_addr;
878 u32 num_pipe;
879 u32 num_mec;
880 u32 num_queue;
771fe6b9
JG		 881};
882
721604a1
JG		 883/*
884 * VM
885 */
ee60e29f 886
fa87e62d 887/* maximum number of VMIDs */
ee60e29f
CK		 888#define RADEON_NUM_VM 16
889
fa87e62d 890/* number of entries in page table */
4510fb98 891#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
fa87e62d 892
1c01103c
AD		 893/* PTBs (Page Table Blocks) need to be aligned to 32K */
894#define RADEON_VM_PTB_ALIGN_SIZE 32768
895#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
896#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
897
24c16439
CK		 898#define R600_PTE_VALID (1 << 0)
899#define R600_PTE_SYSTEM (1 << 1)
900#define R600_PTE_SNOOPED (1 << 2)
901#define R600_PTE_READABLE (1 << 5)
902#define R600_PTE_WRITEABLE (1 << 6)
903
ec3dbbcb
CK		 904/* PTE (Page Table Entry) fragment field for different page sizes */
905#define R600_PTE_FRAG_4KB (0 << 7)
906#define R600_PTE_FRAG_64KB (4 << 7)
907#define R600_PTE_FRAG_256KB (6 << 7)
908
33fa9fe3
CK		 909/* flags needed to be set so we can copy directly from the GART table */
910#define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
911 R600_PTE_SYSTEM | R600_PTE_VALID )
0e97703c 912
6d2f2944
CK		 913struct radeon_vm_pt {
914 struct radeon_bo *bo;
915 uint64_t addr;
916};
917
7c42bc1a
CK		 918struct radeon_vm_id {
919 unsigned id;
920 uint64_t pd_gpu_addr;
921 /* last flushed PD/PT update */
922 struct radeon_fence *flushed_updates;
923 /* last use of vmid */
924 struct radeon_fence *last_id_use;
925};
926
721604a1 927struct radeon_vm {
94214635
CK		 928 struct mutex mutex;
929
7c42bc1a 930 struct rb_root va;
90a51a32 931
f7a3db75
CK		 932 /* protecting invalidated and freed */
933 spinlock_t status_lock;
934
e31ad969 935 /* BOs moved, but not yet updated in the PT */
7c42bc1a 936 struct list_head invalidated;
e31ad969 937
036bf46a 938 /* BOs freed, but not yet updated in the PT */
7c42bc1a 939 struct list_head freed;
036bf46a 940
90a51a32 941 /* contains the page directory */
7c42bc1a
CK		 942 struct radeon_bo *page_directory;
943 unsigned max_pde_used;
90a51a32
CK		 944
945 /* array of page tables, one for each page directory entry */
7c42bc1a 946 struct radeon_vm_pt *page_tables;
90a51a32 947
7c42bc1a 948 struct radeon_bo_va *ib_bo_va;
cc9e67e3 949
7c42bc1a
CK		 950 /* for id and flush management per ring */
951 struct radeon_vm_id ids[RADEON_NUM_RINGS];
721604a1
JG		 952};
953
721604a1 954struct radeon_vm_manager {
ee60e29f 955 struct radeon_fence *active[RADEON_NUM_VM];
721604a1 956 uint32_t max_pfn;
721604a1
JG		 957 /* number of VMIDs */
958 unsigned nvm;
959 /* vram base address for page table entry */
960 u64 vram_base_offset;
67e915e4
AD		 961 /* is vm enabled? */
962 bool enabled;
054e01d6
CK		 963 /* for hw to save the PD addr on suspend/resume */
964 uint32_t saved_table_addr[RADEON_NUM_VM];
721604a1
JG		 965};
966
967/*
968 * file private structure
969 */
970struct radeon_fpriv {
971 struct radeon_vm vm;
972};
973
d8f60cfc
AD		 974/*
975 * R6xx+ IH ring
976 */
977struct r600_ih {
4c788679 978 struct radeon_bo *ring_obj;
d8f60cfc
AD		 979 volatile uint32_t *ring;
980 unsigned rptr;
d8f60cfc
AD		 981 unsigned ring_size;
982 uint64_t gpu_addr;
d8f60cfc 983 uint32_t ptr_mask;
c20dc369 984 atomic_t lock;
d8f60cfc
AD		 985 bool enabled;
986};
987
347e7592 988/*
2948f5e6 989 * RLC stuff
347e7592 990 */
2948f5e6
AD		 991#include "clearstate_defs.h"
992
993struct radeon_rlc {
347e7592
AD		 994 /* for power gating */
995 struct radeon_bo *save_restore_obj;
996 uint64_t save_restore_gpu_addr;
2948f5e6 997 volatile uint32_t *sr_ptr;
1fd11777 998 const u32 *reg_list;
2948f5e6 999 u32 reg_list_size;
347e7592
AD		 1000 /* for clear state */
1001 struct radeon_bo *clear_state_obj;
1002 uint64_t clear_state_gpu_addr;
2948f5e6 1003 volatile uint32_t *cs_ptr;
1fd11777 1004 const struct cs_section_def *cs_data;
22c775ce
AD		 1005 u32 clear_state_size;
1006 /* for cp tables */
1007 struct radeon_bo *cp_table_obj;
1008 uint64_t cp_table_gpu_addr;
1009 volatile uint32_t *cp_table_ptr;
1010 u32 cp_table_size;
347e7592
AD		 1011};
1012
69e130a6 1013int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 1014 struct radeon_ib *ib, struct radeon_vm *vm,
1015 unsigned size);
f2e39221 1016void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
4ef72566 1017int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1538a9e0 1018 struct radeon_ib *const_ib, bool hdp_flush);
771fe6b9
JG		 1019int radeon_ib_pool_init(struct radeon_device *rdev);
1020void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 1021int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 1022/* Ring access between begin & end cannot sleep */
89d35807
AD		 1023bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1024 struct radeon_ring *ring);
e32eb50d
CK		 1025void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1026int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1027int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1538a9e0
MD		 1028void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1029 bool hdp_flush);
1030void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1031 bool hdp_flush);
d6999bc7 1032void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 1033void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1034int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
ff212f25
CK		 1035void radeon_ring_lockup_update(struct radeon_device *rdev,
1036 struct radeon_ring *ring);
069211e5 1037bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 1038unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1039 uint32_t **data);
1040int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1041 unsigned size, uint32_t *data);
e32eb50d 1042int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
ea31bf69 1043 unsigned rptr_offs, u32 nop);
e32eb50d 1044void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 1045
1046
4d75658b
AD		 1047/* r600 async dma */
1048void r600_dma_stop(struct radeon_device *rdev);
1049int r600_dma_resume(struct radeon_device *rdev);
1050void r600_dma_fini(struct radeon_device *rdev);
1051
8c5fd7ef
AD		 1052void cayman_dma_stop(struct radeon_device *rdev);
1053int cayman_dma_resume(struct radeon_device *rdev);
1054void cayman_dma_fini(struct radeon_device *rdev);
1055
771fe6b9
JG		 1056/*
1057 * CS.
1058 */
771fe6b9 1059struct radeon_cs_chunk {
771fe6b9
JG		 1060 uint32_t length_dw;
1061 uint32_t *kdata;
721604a1 1062 void __user *user_ptr;
771fe6b9
JG		 1063};
1064
1065struct radeon_cs_parser {
c8c15ff1 1066 struct device *dev;
771fe6b9
JG		 1067 struct radeon_device *rdev;
1068 struct drm_file *filp;
1069 /* chunks */
1070 unsigned nchunks;
1071 struct radeon_cs_chunk *chunks;
1072 uint64_t *chunks_array;
1073 /* IB */
1074 unsigned idx;
1075 /* relocations */
1076 unsigned nrelocs;
1d0c0942 1077 struct radeon_bo_list *relocs;
1d0c0942 1078 struct radeon_bo_list *vm_bos;
771fe6b9 1079 struct list_head validated;
cf4ccd01 1080 unsigned dma_reloc_idx;
771fe6b9 1081 /* indices of various chunks */
6d2d13dd
CK		 1082 struct radeon_cs_chunk *chunk_ib;
1083 struct radeon_cs_chunk *chunk_relocs;
1084 struct radeon_cs_chunk *chunk_flags;
1085 struct radeon_cs_chunk *chunk_const_ib;
f2e39221
JG		 1086 struct radeon_ib ib;
1087 struct radeon_ib const_ib;
771fe6b9 1088 void *track;
3ce0a23d 1089 unsigned family;
e70f224c 1090 int parser_error;
721604a1
JG		 1091 u32 cs_flags;
1092 u32 ring;
1093 s32 priority;
ecff665f 1094 struct ww_acquire_ctx ticket;
771fe6b9
JG		 1095};
1096
28a326c5
ML		 1097static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1098{
6d2d13dd 1099 struct radeon_cs_chunk *ibc = p->chunk_ib;
28a326c5
ML		 1100
1101 if (ibc->kdata)
1102 return ibc->kdata[idx];
1103 return p->ib.ptr[idx];
1104}
1105
513bcb46 1106
771fe6b9
JG		 1107struct radeon_cs_packet {
1108 unsigned idx;
1109 unsigned type;
1110 unsigned reg;
1111 unsigned opcode;
1112 int count;
1113 unsigned one_reg_wr;
1114};
1115
1116typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1117 struct radeon_cs_packet *pkt,
1118 unsigned idx, unsigned reg);
1119typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1120 struct radeon_cs_packet *pkt);
1121
1122
1123/*
1124 * AGP
1125 */
1126int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1127void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1128void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1129void radeon_agp_fini(struct radeon_device *rdev);
1130
1131
1132/*
1133 * Writeback
1134 */
1135struct radeon_wb {
4c788679 1136 struct radeon_bo *wb_obj;
771fe6b9
JG		 1137 volatile uint32_t *wb;
1138 uint64_t gpu_addr;
724c80e1 1139 bool enabled;
d0f8a854 1140 bool use_event;
771fe6b9
JG		 1141};
1142
724c80e1 1143#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1144#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1145#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1146#define RADEON_WB_CP1_RPTR_OFFSET 1280
1147#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1148#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1149#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1150#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1151#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1152#define CIK_WB_CP1_WPTR_OFFSET 3328
1153#define CIK_WB_CP2_WPTR_OFFSET 3584
adfed2b0
AD		 1154#define R600_WB_DMA_RING_TEST_OFFSET 3588
1155#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
724c80e1 1156
c93bb85b
JG		 1157/**
1158 * struct radeon_pm - power management datas
1159 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1160 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1161 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1162 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1163 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1164 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1165 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1166 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1167 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1168 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1169 * @needed_bandwidth: current bandwidth needs
1170 *
1171 * It keeps track of various data needed to take powermanagement decision.
25985edc 1172 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1173 * Equation between gpu/memory clock and available bandwidth is hw dependent
1174 * (type of memory, bus size, efficiency, ...)
1175 */
ce8f5370
AD		 1176
1177enum radeon_pm_method {
1178 PM_METHOD_PROFILE,
1179 PM_METHOD_DYNPM,
da321c8a 1180 PM_METHOD_DPM,
ce8f5370
AD		 1181};
1182
1183enum radeon_dynpm_state {
1184 DYNPM_STATE_DISABLED,
1185 DYNPM_STATE_MINIMUM,
1186 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1187 DYNPM_STATE_ACTIVE,
1188 DYNPM_STATE_SUSPENDED,
c913e23a 1189};
ce8f5370
AD		 1190enum radeon_dynpm_action {
1191 DYNPM_ACTION_NONE,
1192 DYNPM_ACTION_MINIMUM,
1193 DYNPM_ACTION_DOWNCLOCK,
1194 DYNPM_ACTION_UPCLOCK,
1195 DYNPM_ACTION_DEFAULT
c913e23a 1196};
56278a8e
AD		 1197
1198enum radeon_voltage_type {
1199 VOLTAGE_NONE = 0,
1200 VOLTAGE_GPIO,
1201 VOLTAGE_VDDC,
1202 VOLTAGE_SW
1203};
1204
0ec0e74f 1205enum radeon_pm_state_type {
da321c8a 1206 /* not used for dpm */
0ec0e74f
AD		 1207 POWER_STATE_TYPE_DEFAULT,
1208 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1209 /* user selectable states */
0ec0e74f
AD		 1210 POWER_STATE_TYPE_BATTERY,
1211 POWER_STATE_TYPE_BALANCED,
1212 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1213 /* internal states */
1214 POWER_STATE_TYPE_INTERNAL_UVD,
1215 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1216 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1217 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1218 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1219 POWER_STATE_TYPE_INTERNAL_BOOT,
1220 POWER_STATE_TYPE_INTERNAL_THERMAL,
1221 POWER_STATE_TYPE_INTERNAL_ACPI,
1222 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1223 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1224};
1225
ce8f5370
AD		 1226enum radeon_pm_profile_type {
1227 PM_PROFILE_DEFAULT,
1228 PM_PROFILE_AUTO,
1229 PM_PROFILE_LOW,
c9e75b21 1230 PM_PROFILE_MID,
ce8f5370
AD		 1231 PM_PROFILE_HIGH,
1232};
1233
1234#define PM_PROFILE_DEFAULT_IDX 0
1235#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1236#define PM_PROFILE_MID_SH_IDX 2
1237#define PM_PROFILE_HIGH_SH_IDX 3
1238#define PM_PROFILE_LOW_MH_IDX 4
1239#define PM_PROFILE_MID_MH_IDX 5
1240#define PM_PROFILE_HIGH_MH_IDX 6
1241#define PM_PROFILE_MAX 7
ce8f5370
AD		 1242
1243struct radeon_pm_profile {
1244 int dpms_off_ps_idx;
1245 int dpms_on_ps_idx;
1246 int dpms_off_cm_idx;
1247 int dpms_on_cm_idx;
516d0e46
AD		 1248};
1249
21a8122a
AD		 1250enum radeon_int_thermal_type {
1251 THERMAL_TYPE_NONE,
da321c8a
AD		 1252 THERMAL_TYPE_EXTERNAL,
1253 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1254 THERMAL_TYPE_RV6XX,
1255 THERMAL_TYPE_RV770,
da321c8a 1256 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1257 THERMAL_TYPE_EVERGREEN,
e33df25f 1258 THERMAL_TYPE_SUMO,
4fddba1f 1259 THERMAL_TYPE_NI,
14607d08 1260 THERMAL_TYPE_SI,
da321c8a 1261 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1262 THERMAL_TYPE_CI,
16fbe00d 1263 THERMAL_TYPE_KV,
21a8122a
AD		 1264};
1265
56278a8e
AD		 1266struct radeon_voltage {
1267 enum radeon_voltage_type type;
1268 /* gpio voltage */
1269 struct radeon_gpio_rec gpio;
1270 u32 delay; /* delay in usec from voltage drop to sclk change */
1271 bool active_high; /* voltage drop is active when bit is high */
1272 /* VDDC voltage */
1273 u8 vddc_id; /* index into vddc voltage table */
1274 u8 vddci_id; /* index into vddci voltage table */
1275 bool vddci_enabled;
1276 /* r6xx+ sw */
2feea49a
AD		 1277 u16 voltage;
1278 /* evergreen+ vddci */
1279 u16 vddci;
56278a8e
AD		 1280};
1281
d7311171
AD		 1282/* clock mode flags */
1283#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1284
56278a8e
AD		 1285struct radeon_pm_clock_info {
1286 /* memory clock */
1287 u32 mclk;
1288 /* engine clock */
1289 u32 sclk;
1290 /* voltage info */
1291 struct radeon_voltage voltage;
d7311171 1292 /* standardized clock flags */
56278a8e
AD		 1293 u32 flags;
1294};
1295
a48b9b4e 1296/* state flags */
d7311171 1297#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1298
56278a8e 1299struct radeon_power_state {
0ec0e74f 1300 enum radeon_pm_state_type type;
8f3f1c9a 1301 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1302 /* number of valid clock modes in this power state */
1303 int num_clock_modes;
56278a8e 1304 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1305 /* standardized state flags */
1306 u32 flags;
79daedc9
AD		 1307 u32 misc; /* vbios specific flags */
1308 u32 misc2; /* vbios specific flags */
1309 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1310};
1311
27459324
RM		 1312/*
1313 * Some modes are overclocked by very low value, accept them
1314 */
1315#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1316
2e9d4c05
AD		 1317enum radeon_dpm_auto_throttle_src {
1318 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1319 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1320};
1321
1322enum radeon_dpm_event_src {
1323 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1324 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1325 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1326 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1327 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1328};
1329
58bd2a88
AD		 1330#define RADEON_MAX_VCE_LEVELS 6
1331
b62d628b
AD		 1332enum radeon_vce_level {
1333 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1334 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1335 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1336 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1337 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1338 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1339};
1340
da321c8a
AD		 1341struct radeon_ps {
1342 u32 caps; /* vbios flags */
1343 u32 class; /* vbios flags */
1344 u32 class2; /* vbios flags */
1345 /* UVD clocks */
1346 u32 vclk;
1347 u32 dclk;
c4453e66
AD		 1348 /* VCE clocks */
1349 u32 evclk;
1350 u32 ecclk;
b62d628b
AD		 1351 bool vce_active;
1352 enum radeon_vce_level vce_level;
da321c8a
AD		 1353 /* asic priv */
1354 void *ps_priv;
1355};
1356
1357struct radeon_dpm_thermal {
1358 /* thermal interrupt work */
1359 struct work_struct work;
1360 /* low temperature threshold */
1361 int min_temp;
1362 /* high temperature threshold */
1363 int max_temp;
1364 /* was interrupt low to high or high to low */
1365 bool high_to_low;
1366};
1367
d22b7e40
AD		 1368enum radeon_clk_action
1369{
1370 RADEON_SCLK_UP = 1,
1371 RADEON_SCLK_DOWN
1372};
1373
1374struct radeon_blacklist_clocks
1375{
1376 u32 sclk;
1377 u32 mclk;
1378 enum radeon_clk_action action;
1379};
1380
61b7d601
AD		 1381struct radeon_clock_and_voltage_limits {
1382 u32 sclk;
1383 u32 mclk;
cdf6e805
AD		 1384 u16 vddc;
1385 u16 vddci;
61b7d601
AD		 1386};
1387
1388struct radeon_clock_array {
1389 u32 count;
1390 u32 *values;
1391};
1392
1393struct radeon_clock_voltage_dependency_entry {
1394 u32 clk;
1395 u16 v;
1396};
1397
1398struct radeon_clock_voltage_dependency_table {
1399 u32 count;
1400 struct radeon_clock_voltage_dependency_entry *entries;
1401};
1402
ef976ec4
AD		 1403union radeon_cac_leakage_entry {
1404 struct {
1405 u16 vddc;
1406 u32 leakage;
1407 };
1408 struct {
1409 u16 vddc1;
1410 u16 vddc2;
1411 u16 vddc3;
1412 };
61b7d601
AD		 1413};
1414
1415struct radeon_cac_leakage_table {
1416 u32 count;
ef976ec4 1417 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1418};
1419
929ee7a8
AD		 1420struct radeon_phase_shedding_limits_entry {
1421 u16 voltage;
1422 u32 sclk;
1423 u32 mclk;
1424};
1425
1426struct radeon_phase_shedding_limits_table {
1427 u32 count;
1428 struct radeon_phase_shedding_limits_entry *entries;
1429};
1430
84a9d9ee
AD		 1431struct radeon_uvd_clock_voltage_dependency_entry {
1432 u32 vclk;
1433 u32 dclk;
1434 u16 v;
1435};
1436
1437struct radeon_uvd_clock_voltage_dependency_table {
1438 u8 count;
1439 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1440};
1441
d29f013b
AD		 1442struct radeon_vce_clock_voltage_dependency_entry {
1443 u32 ecclk;
1444 u32 evclk;
1445 u16 v;
1446};
1447
1448struct radeon_vce_clock_voltage_dependency_table {
1449 u8 count;
1450 struct radeon_vce_clock_voltage_dependency_entry *entries;
1451};
1452
a5cb318e
AD		 1453struct radeon_ppm_table {
1454 u8 ppm_design;
1455 u16 cpu_core_number;
1456 u32 platform_tdp;
1457 u32 small_ac_platform_tdp;
1458 u32 platform_tdc;
1459 u32 small_ac_platform_tdc;
1460 u32 apu_tdp;
1461 u32 dgpu_tdp;
1462 u32 dgpu_ulv_power;
1463 u32 tj_max;
1464};
1465
58cb7632
AD		 1466struct radeon_cac_tdp_table {
1467 u16 tdp;
1468 u16 configurable_tdp;
1469 u16 tdc;
1470 u16 battery_power_limit;
1471 u16 small_power_limit;
1472 u16 low_cac_leakage;
1473 u16 high_cac_leakage;
1474 u16 maximum_power_delivery_limit;
1475};
1476
61b7d601
AD		 1477struct radeon_dpm_dynamic_state {
1478 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1479 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1480 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1481 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1482 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1483 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1484 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1485 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1486 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1487 struct radeon_clock_array valid_sclk_values;
1488 struct radeon_clock_array valid_mclk_values;
1489 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1490 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1491 u32 mclk_sclk_ratio;
1492 u32 sclk_mclk_delta;
1493 u16 vddc_vddci_delta;
1494 u16 min_vddc_for_pcie_gen2;
1495 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1496 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1497 struct radeon_ppm_table *ppm_table;
58cb7632 1498 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1499};
1500
1501struct radeon_dpm_fan {
1502 u16 t_min;
1503 u16 t_med;
1504 u16 t_high;
1505 u16 pwm_min;
1506 u16 pwm_med;
1507 u16 pwm_high;
1508 u8 t_hyst;
1509 u32 cycle_delay;
1510 u16 t_max;
e03cea36
AD		 1511 u8 control_mode;
1512 u16 default_max_fan_pwm;
1513 u16 default_fan_output_sensitivity;
1514 u16 fan_output_sensitivity;
61b7d601
AD		 1515 bool ucode_fan_control;
1516};
1517
32ce4652
AD		 1518enum radeon_pcie_gen {
1519 RADEON_PCIE_GEN1 = 0,
1520 RADEON_PCIE_GEN2 = 1,
1521 RADEON_PCIE_GEN3 = 2,
1522 RADEON_PCIE_GEN_INVALID = 0xffff
1523};
1524
70d01a5e
AD		 1525enum radeon_dpm_forced_level {
1526 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1527 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1528 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1529};
1530
58bd2a88
AD		 1531struct radeon_vce_state {
1532 /* vce clocks */
1533 u32 evclk;
1534 u32 ecclk;
1535 /* gpu clocks */
1536 u32 sclk;
1537 u32 mclk;
1538 u8 clk_idx;
1539 u8 pstate;
1540};
1541
da321c8a
AD		 1542struct radeon_dpm {
1543 struct radeon_ps *ps;
1544 /* number of valid power states */
1545 int num_ps;
1546 /* current power state that is active */
1547 struct radeon_ps *current_ps;
1548 /* requested power state */
1549 struct radeon_ps *requested_ps;
1550 /* boot up power state */
1551 struct radeon_ps *boot_ps;
1552 /* default uvd power state */
1553 struct radeon_ps *uvd_ps;
58bd2a88
AD		 1554 /* vce requirements */
1555 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1556 enum radeon_vce_level vce_level;
da321c8a
AD		 1557 enum radeon_pm_state_type state;
1558 enum radeon_pm_state_type user_state;
1559 u32 platform_caps;
1560 u32 voltage_response_time;
1561 u32 backbias_response_time;
1562 void *priv;
1563 u32 new_active_crtcs;
1564 int new_active_crtc_count;
1565 u32 current_active_crtcs;
1566 int current_active_crtc_count;
61b7d601
AD		 1567 struct radeon_dpm_dynamic_state dyn_state;
1568 struct radeon_dpm_fan fan;
1569 u32 tdp_limit;
1570 u32 near_tdp_limit;
a9e61410 1571 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1572 u32 sq_ramping_threshold;
1573 u32 cac_leakage;
1574 u16 tdp_od_limit;
1575 u32 tdp_adjustment;
1576 u16 load_line_slope;
1577 bool power_control;
5ca302f7 1578 bool ac_power;
da321c8a
AD		 1579 /* special states active */
1580 bool thermal_active;
8a227555 1581 bool uvd_active;
b62d628b 1582 bool vce_active;
da321c8a
AD		 1583 /* thermal handling */
1584 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1585 /* forced levels */
1586 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1587 /* track UVD streams */
1588 unsigned sd;
1589 unsigned hd;
da321c8a
AD		 1590};
1591
ce3537d5 1592void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
03afe6f6 1593void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
da321c8a 1594
c93bb85b 1595struct radeon_pm {
c913e23a 1596 struct mutex mutex;
db7fce39
CK		 1597 /* write locked while reprogramming mclk */
1598 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1599 u32 active_crtcs;
1600 int active_crtc_count;
c913e23a 1601 int req_vblank;
839461d3 1602 bool vblank_sync;
c93bb85b
JG		 1603 fixed20_12 max_bandwidth;
1604 fixed20_12 igp_sideport_mclk;
1605 fixed20_12 igp_system_mclk;
1606 fixed20_12 igp_ht_link_clk;
1607 fixed20_12 igp_ht_link_width;
1608 fixed20_12 k8_bandwidth;
1609 fixed20_12 sideport_bandwidth;
1610 fixed20_12 ht_bandwidth;
1611 fixed20_12 core_bandwidth;
1612 fixed20_12 sclk;
f47299c5 1613 fixed20_12 mclk;
c93bb85b 1614 fixed20_12 needed_bandwidth;
0975b162 1615 struct radeon_power_state *power_state;
56278a8e
AD		 1616 /* number of valid power states */
1617 int num_power_states;
a48b9b4e
AD		 1618 int current_power_state_index;
1619 int current_clock_mode_index;
1620 int requested_power_state_index;
1621 int requested_clock_mode_index;
1622 int default_power_state_index;
1623 u32 current_sclk;
1624 u32 current_mclk;
2feea49a
AD		 1625 u16 current_vddc;
1626 u16 current_vddci;
9ace9f7b
AD		 1627 u32 default_sclk;
1628 u32 default_mclk;
2feea49a
AD		 1629 u16 default_vddc;
1630 u16 default_vddci;
29fb52ca 1631 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1632 /* selected pm method */
1633 enum radeon_pm_method pm_method;
1634 /* dynpm power management */
1635 struct delayed_work dynpm_idle_work;
1636 enum radeon_dynpm_state dynpm_state;
1637 enum radeon_dynpm_action dynpm_planned_action;
1638 unsigned long dynpm_action_timeout;
1639 bool dynpm_can_upclock;
1640 bool dynpm_can_downclock;
1641 /* profile-based power management */
1642 enum radeon_pm_profile_type profile;
1643 int profile_index;
1644 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1645 /* internal thermal controller on rv6xx+ */
1646 enum radeon_int_thermal_type int_thermal_type;
1647 struct device *int_hwmon_dev;
9b92d1ec
AD		 1648 /* fan control parameters */
1649 bool no_fan;
1650 u8 fan_pulses_per_revolution;
1651 u8 fan_min_rpm;
1652 u8 fan_max_rpm;
da321c8a
AD		 1653 /* dpm */
1654 bool dpm_enabled;
1655 struct radeon_dpm dpm;
c93bb85b
JG		 1656};
1657
a4c9e2ee
AD		 1658int radeon_pm_get_type_index(struct radeon_device *rdev,
1659 enum radeon_pm_state_type ps_type,
1660 int instance);
f2ba57b5
CK		 1661/*
1662 * UVD
1663 */
1664#define RADEON_MAX_UVD_HANDLES 10
1665#define RADEON_UVD_STACK_SIZE (1024*1024)
1666#define RADEON_UVD_HEAP_SIZE (1024*1024)
1667
1668struct radeon_uvd {
1669 struct radeon_bo *vcpu_bo;
1670 void *cpu_addr;
1671 uint64_t gpu_addr;
9cc2e0e9 1672 void *saved_bo;
f2ba57b5
CK		 1673 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1674 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1675 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1676 struct delayed_work idle_work;
f2ba57b5
CK		 1677};
1678
1679int radeon_uvd_init(struct radeon_device *rdev);
1680void radeon_uvd_fini(struct radeon_device *rdev);
1681int radeon_uvd_suspend(struct radeon_device *rdev);
1682int radeon_uvd_resume(struct radeon_device *rdev);
1683int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1684 uint32_t handle, struct radeon_fence **fence);
1685int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1686 uint32_t handle, struct radeon_fence **fence);
3852752c
CK		 1687void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1688 uint32_t allowed_domains);
f2ba57b5
CK		 1689void radeon_uvd_free_handles(struct radeon_device *rdev,
1690 struct drm_file *filp);
1691int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1692void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1693int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1694 unsigned vclk, unsigned dclk,
1695 unsigned vco_min, unsigned vco_max,
1696 unsigned fb_factor, unsigned fb_mask,
1697 unsigned pd_min, unsigned pd_max,
1698 unsigned pd_even,
1699 unsigned *optimal_fb_div,
1700 unsigned *optimal_vclk_div,
1701 unsigned *optimal_dclk_div);
1702int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1703 unsigned cg_upll_func_cntl);
771fe6b9 1704
d93f7937
CK		 1705/*
1706 * VCE
1707 */
1708#define RADEON_MAX_VCE_HANDLES 16
1709#define RADEON_VCE_STACK_SIZE (1024*1024)
1710#define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1711
1712struct radeon_vce {
1713 struct radeon_bo *vcpu_bo;
d93f7937 1714 uint64_t gpu_addr;
98ccc291
CK		 1715 unsigned fw_version;
1716 unsigned fb_version;
d93f7937
CK		 1717 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1718 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
2fc5703a 1719 unsigned img_size[RADEON_MAX_VCE_HANDLES];
03afe6f6 1720 struct delayed_work idle_work;
d93f7937
CK		 1721};
1722
1723int radeon_vce_init(struct radeon_device *rdev);
1724void radeon_vce_fini(struct radeon_device *rdev);
1725int radeon_vce_suspend(struct radeon_device *rdev);
1726int radeon_vce_resume(struct radeon_device *rdev);
1727int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1728 uint32_t handle, struct radeon_fence **fence);
1729int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1730 uint32_t handle, struct radeon_fence **fence);
1731void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
03afe6f6 1732void radeon_vce_note_usage(struct radeon_device *rdev);
2fc5703a 1733int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
d93f7937
CK		 1734int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1735bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1736 struct radeon_ring *ring,
1737 struct radeon_semaphore *semaphore,
1738 bool emit_wait);
1739void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1740void radeon_vce_fence_emit(struct radeon_device *rdev,
1741 struct radeon_fence *fence);
1742int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1743int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1744
b530602f 1745struct r600_audio_pin {
a92553ab
RM		 1746 int channels;
1747 int rate;
1748 int bits_per_sample;
1749 u8 status_bits;
1750 u8 category_code;
b530602f
AD		 1751 u32 offset;
1752 bool connected;
1753 u32 id;
1754};
1755
1756struct r600_audio {
1757 bool enabled;
1758 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1759 int num_pins;
1a626b68
SG		 1760 struct radeon_audio_funcs *hdmi_funcs;
1761 struct radeon_audio_funcs *dp_funcs;
1762 struct radeon_audio_basic_funcs *funcs;
a92553ab
RM		 1763};
1764
771fe6b9
JG		 1765/*
1766 * Benchmarking
1767 */
638dd7db 1768void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1769
1770
ecc0b326
MD		 1771/*
1772 * Testing
1773 */
1774void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1775void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1776 struct radeon_ring *cpA,
1777 struct radeon_ring *cpB);
60a7e396 1778void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326 1779
341cb9e4
CK		 1780/*
1781 * MMU Notifier
1782 */
1783int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1784void radeon_mn_unregister(struct radeon_bo *bo);
ecc0b326 1785
771fe6b9
JG		 1786/*
1787 * Debugfs
1788 */
4d8bf9ae
CK		 1789struct radeon_debugfs {
1790 struct drm_info_list *files;
1791 unsigned num_files;
1792};
1793
771fe6b9
JG		 1794int radeon_debugfs_add_files(struct radeon_device *rdev,
1795 struct drm_info_list *files,
1796 unsigned nfiles);
1797int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1798
76a0df85
CK		 1799/*
1800 * ASIC ring specific functions.
1801 */
1802struct radeon_asic_ring {
1803 /* ring read/write ptr handling */
1804 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1805 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1806 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1807
1808 /* validating and patching of IBs */
1809 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1810 int (*cs_parse)(struct radeon_cs_parser *p);
1811
1812 /* command emmit functions */
1813 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1814 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
72a9987e 1815 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1654b817 1816 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
76a0df85 1817 struct radeon_semaphore *semaphore, bool emit_wait);
faffaf62
CK		 1818 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1819 unsigned vm_id, uint64_t pd_addr);
76a0df85
CK		 1820
1821 /* testing functions */
1822 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1823 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1824 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1825
1826 /* deprecated */
1827 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1828};
771fe6b9
JG		 1829
1830/*
1831 * ASIC specific functions.
1832 */
1833struct radeon_asic {
068a117c 1834 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1835 void (*fini)(struct radeon_device *rdev);
1836 int (*resume)(struct radeon_device *rdev);
1837 int (*suspend)(struct radeon_device *rdev);
28d52043 1838 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1839 int (*asic_reset)(struct radeon_device *rdev);
124764f1
MD		 1840 /* Flush the HDP cache via MMIO */
1841 void (*mmio_hdp_flush)(struct radeon_device *rdev);
54e88e06
AD		 1842 /* check if 3D engine is idle */
1843 bool (*gui_idle)(struct radeon_device *rdev);
1844 /* wait for mc_idle */
1845 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1846 /* get the reference clock */
1847 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1848 /* get the gpu clock counter */
1849 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1850 /* gart */
c5b3b850
AD		 1851 struct {
1852 void (*tlb_flush)(struct radeon_device *rdev);
7f90fc96 1853 void (*set_page)(struct radeon_device *rdev, unsigned i,
77497f27 1854 uint64_t addr, uint32_t flags);
c5b3b850 1855 } gart;
05b07147
CK		 1856 struct {
1857 int (*init)(struct radeon_device *rdev);
1858 void (*fini)(struct radeon_device *rdev);
03f62abd
CK		 1859 void (*copy_pages)(struct radeon_device *rdev,
1860 struct radeon_ib *ib,
1861 uint64_t pe, uint64_t src,
1862 unsigned count);
1863 void (*write_pages)(struct radeon_device *rdev,
1864 struct radeon_ib *ib,
1865 uint64_t pe,
1866 uint64_t addr, unsigned count,
1867 uint32_t incr, uint32_t flags);
1868 void (*set_pages)(struct radeon_device *rdev,
1869 struct radeon_ib *ib,
1870 uint64_t pe,
1871 uint64_t addr, unsigned count,
1872 uint32_t incr, uint32_t flags);
1873 void (*pad_ib)(struct radeon_ib *ib);
05b07147 1874 } vm;
54e88e06 1875 /* ring specific callbacks */
76a0df85 1876 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1877 /* irqs */
b35ea4ab
AD		 1878 struct {
1879 int (*set)(struct radeon_device *rdev);
1880 int (*process)(struct radeon_device *rdev);
1881 } irq;
54e88e06 1882 /* displays */
c79a49ca
AD		 1883 struct {
1884 /* display watermarks */
1885 void (*bandwidth_update)(struct radeon_device *rdev);
1886 /* get frame count */
1887 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1888 /* wait for vblank */
1889 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1890 /* set backlight level */
1891 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1892 /* get backlight level */
1893 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1894 /* audio callbacks */
1895 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1896 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1897 } display;
54e88e06 1898 /* copy functions for bo handling */
27cd7769 1899 struct {
57d20a43
CK		 1900 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1901 uint64_t src_offset,
1902 uint64_t dst_offset,
1903 unsigned num_gpu_pages,
1904 struct reservation_object *resv);
27cd7769 1905 u32 blit_ring_index;
57d20a43
CK		 1906 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1907 uint64_t src_offset,
1908 uint64_t dst_offset,
1909 unsigned num_gpu_pages,
1910 struct reservation_object *resv);
27cd7769
AD		 1911 u32 dma_ring_index;
1912 /* method used for bo copy */
57d20a43
CK		 1913 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1914 uint64_t src_offset,
1915 uint64_t dst_offset,
1916 unsigned num_gpu_pages,
1917 struct reservation_object *resv);
27cd7769
AD		 1918 /* ring used for bo copies */
1919 u32 copy_ring_index;
1920 } copy;
54e88e06 1921 /* surfaces */
9e6f3d02
AD		 1922 struct {
1923 int (*set_reg)(struct radeon_device *rdev, int reg,
1924 uint32_t tiling_flags, uint32_t pitch,
1925 uint32_t offset, uint32_t obj_size);
1926 void (*clear_reg)(struct radeon_device *rdev, int reg);
1927 } surface;
54e88e06 1928 /* hotplug detect */
901ea57d
AD		 1929 struct {
1930 void (*init)(struct radeon_device *rdev);
1931 void (*fini)(struct radeon_device *rdev);
1932 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1933 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1934 } hpd;
da321c8a 1935 /* static power management */
a02fa397
AD		 1936 struct {
1937 void (*misc)(struct radeon_device *rdev);
1938 void (*prepare)(struct radeon_device *rdev);
1939 void (*finish)(struct radeon_device *rdev);
1940 void (*init_profile)(struct radeon_device *rdev);
1941 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1942 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1943 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1944 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1945 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1946 int (*get_pcie_lanes)(struct radeon_device *rdev);
1947 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1948 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1949 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
b59b7333 1950 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
6bd1c385 1951 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1952 } pm;
da321c8a
AD		 1953 /* dynamic power management */
1954 struct {
1955 int (*init)(struct radeon_device *rdev);
1956 void (*setup_asic)(struct radeon_device *rdev);
1957 int (*enable)(struct radeon_device *rdev);
914a8987 1958 int (*late_enable)(struct radeon_device *rdev);
da321c8a 1959 void (*disable)(struct radeon_device *rdev);
84dd1928 1960 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1961 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1962 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1963 void (*display_configuration_changed)(struct radeon_device *rdev);
1964 void (*fini)(struct radeon_device *rdev);
1965 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1966 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1967 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1968 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1969 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1970 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1971 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1c71bda0 1972 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
a35a4b2b
OC		 1973 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
1974 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
1975 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
1976 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
da321c8a 1977 } dpm;
6f34be50 1978 /* pageflipping */
0f9e006c 1979 struct {
157fa14d
CK		 1980 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1981 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
0f9e006c 1982 } pflip;
771fe6b9
JG		 1983};
1984
21f9a437
JG		 1985/*
1986 * Asic structures
1987 */
551ebd83 1988struct r100_asic {
225758d8
JG		 1989 const unsigned *reg_safe_bm;
1990 unsigned reg_safe_bm_size;
1991 u32 hdp_cntl;
551ebd83
DA		 1992};
1993
21f9a437 1994struct r300_asic {
225758d8
JG		 1995 const unsigned *reg_safe_bm;
1996 unsigned reg_safe_bm_size;
1997 u32 resync_scratch;
1998 u32 hdp_cntl;
21f9a437
JG		 1999};
2000
2001struct r600_asic {
225758d8
JG		 2002 unsigned max_pipes;
2003 unsigned max_tile_pipes;
2004 unsigned max_simds;
2005 unsigned max_backends;
2006 unsigned max_gprs;
2007 unsigned max_threads;
2008 unsigned max_stack_entries;
2009 unsigned max_hw_contexts;
2010 unsigned max_gs_threads;
2011 unsigned sx_max_export_size;
2012 unsigned sx_max_export_pos_size;
2013 unsigned sx_max_export_smx_size;
2014 unsigned sq_num_cf_insts;
2015 unsigned tiling_nbanks;
2016 unsigned tiling_npipes;
2017 unsigned tiling_group_size;
e7aeeba6 2018 unsigned tile_config;
e55b9422 2019 unsigned backend_map;
65fcf668 2020 unsigned active_simds;
21f9a437
JG		 2021};
2022
2023struct rv770_asic {
225758d8
JG		 2024 unsigned max_pipes;
2025 unsigned max_tile_pipes;
2026 unsigned max_simds;
2027 unsigned max_backends;
2028 unsigned max_gprs;
2029 unsigned max_threads;
2030 unsigned max_stack_entries;
2031 unsigned max_hw_contexts;
2032 unsigned max_gs_threads;
2033 unsigned sx_max_export_size;
2034 unsigned sx_max_export_pos_size;
2035 unsigned sx_max_export_smx_size;
2036 unsigned sq_num_cf_insts;
2037 unsigned sx_num_of_sets;
2038 unsigned sc_prim_fifo_size;
2039 unsigned sc_hiz_tile_fifo_size;
2040 unsigned sc_earlyz_tile_fifo_fize;
2041 unsigned tiling_nbanks;
2042 unsigned tiling_npipes;
2043 unsigned tiling_group_size;
e7aeeba6 2044 unsigned tile_config;
e55b9422 2045 unsigned backend_map;
65fcf668 2046 unsigned active_simds;
21f9a437
JG		 2047};
2048
32fcdbf4
AD		 2049struct evergreen_asic {
2050 unsigned num_ses;
2051 unsigned max_pipes;
2052 unsigned max_tile_pipes;
2053 unsigned max_simds;
2054 unsigned max_backends;
2055 unsigned max_gprs;
2056 unsigned max_threads;
2057 unsigned max_stack_entries;
2058 unsigned max_hw_contexts;
2059 unsigned max_gs_threads;
2060 unsigned sx_max_export_size;
2061 unsigned sx_max_export_pos_size;
2062 unsigned sx_max_export_smx_size;
2063 unsigned sq_num_cf_insts;
2064 unsigned sx_num_of_sets;
2065 unsigned sc_prim_fifo_size;
2066 unsigned sc_hiz_tile_fifo_size;
2067 unsigned sc_earlyz_tile_fifo_size;
2068 unsigned tiling_nbanks;
2069 unsigned tiling_npipes;
2070 unsigned tiling_group_size;
e7aeeba6 2071 unsigned tile_config;
e55b9422 2072 unsigned backend_map;
65fcf668 2073 unsigned active_simds;
32fcdbf4
AD		 2074};
2075
fecf1d07
AD		 2076struct cayman_asic {
2077 unsigned max_shader_engines;
2078 unsigned max_pipes_per_simd;
2079 unsigned max_tile_pipes;
2080 unsigned max_simds_per_se;
2081 unsigned max_backends_per_se;
2082 unsigned max_texture_channel_caches;
2083 unsigned max_gprs;
2084 unsigned max_threads;
2085 unsigned max_gs_threads;
2086 unsigned max_stack_entries;
2087 unsigned sx_num_of_sets;
2088 unsigned sx_max_export_size;
2089 unsigned sx_max_export_pos_size;
2090 unsigned sx_max_export_smx_size;
2091 unsigned max_hw_contexts;
2092 unsigned sq_num_cf_insts;
2093 unsigned sc_prim_fifo_size;
2094 unsigned sc_hiz_tile_fifo_size;
2095 unsigned sc_earlyz_tile_fifo_size;
2096
2097 unsigned num_shader_engines;
2098 unsigned num_shader_pipes_per_simd;
2099 unsigned num_tile_pipes;
2100 unsigned num_simds_per_se;
2101 unsigned num_backends_per_se;
2102 unsigned backend_disable_mask_per_asic;
2103 unsigned backend_map;
2104 unsigned num_texture_channel_caches;
2105 unsigned mem_max_burst_length_bytes;
2106 unsigned mem_row_size_in_kb;
2107 unsigned shader_engine_tile_size;
2108 unsigned num_gpus;
2109 unsigned multi_gpu_tile_size;
2110
2111 unsigned tile_config;
65fcf668 2112 unsigned active_simds;
fecf1d07
AD		 2113};
2114
0a96d72b
AD		 2115struct si_asic {
2116 unsigned max_shader_engines;
0a96d72b 2117 unsigned max_tile_pipes;
1a8ca750
AD		 2118 unsigned max_cu_per_sh;
2119 unsigned max_sh_per_se;
0a96d72b
AD		 2120 unsigned max_backends_per_se;
2121 unsigned max_texture_channel_caches;
2122 unsigned max_gprs;
2123 unsigned max_gs_threads;
2124 unsigned max_hw_contexts;
2125 unsigned sc_prim_fifo_size_frontend;
2126 unsigned sc_prim_fifo_size_backend;
2127 unsigned sc_hiz_tile_fifo_size;
2128 unsigned sc_earlyz_tile_fifo_size;
2129
0a96d72b 2130 unsigned num_tile_pipes;
439a1cff 2131 unsigned backend_enable_mask;
0a96d72b
AD		 2132 unsigned backend_disable_mask_per_asic;
2133 unsigned backend_map;
2134 unsigned num_texture_channel_caches;
2135 unsigned mem_max_burst_length_bytes;
2136 unsigned mem_row_size_in_kb;
2137 unsigned shader_engine_tile_size;
2138 unsigned num_gpus;
2139 unsigned multi_gpu_tile_size;
2140
2141 unsigned tile_config;
64d7b8be 2142 uint32_t tile_mode_array[32];
65fcf668 2143 uint32_t active_cus;
0a96d72b
AD		 2144};
2145
8cc1a532
AD		 2146struct cik_asic {
2147 unsigned max_shader_engines;
2148 unsigned max_tile_pipes;
2149 unsigned max_cu_per_sh;
2150 unsigned max_sh_per_se;
2151 unsigned max_backends_per_se;
2152 unsigned max_texture_channel_caches;
2153 unsigned max_gprs;
2154 unsigned max_gs_threads;
2155 unsigned max_hw_contexts;
2156 unsigned sc_prim_fifo_size_frontend;
2157 unsigned sc_prim_fifo_size_backend;
2158 unsigned sc_hiz_tile_fifo_size;
2159 unsigned sc_earlyz_tile_fifo_size;
2160
2161 unsigned num_tile_pipes;
439a1cff 2162 unsigned backend_enable_mask;
8cc1a532
AD		 2163 unsigned backend_disable_mask_per_asic;
2164 unsigned backend_map;
2165 unsigned num_texture_channel_caches;
2166 unsigned mem_max_burst_length_bytes;
2167 unsigned mem_row_size_in_kb;
2168 unsigned shader_engine_tile_size;
2169 unsigned num_gpus;
2170 unsigned multi_gpu_tile_size;
2171
2172 unsigned tile_config;
39aee490 2173 uint32_t tile_mode_array[32];
32f79a8a 2174 uint32_t macrotile_mode_array[16];
65fcf668 2175 uint32_t active_cus;
8cc1a532
AD		 2176};
2177
068a117c
JG		 2178union radeon_asic_config {
2179 struct r300_asic r300;
551ebd83 2180 struct r100_asic r100;
3ce0a23d
JG		 2181 struct r600_asic r600;
2182 struct rv770_asic rv770;
32fcdbf4 2183 struct evergreen_asic evergreen;
fecf1d07 2184 struct cayman_asic cayman;
0a96d72b 2185 struct si_asic si;
8cc1a532 2186 struct cik_asic cik;
068a117c
JG		 2187};
2188
0a10c851
DV		 2189/*
2190 * asic initizalization from radeon_asic.c
2191 */
2192void radeon_agp_disable(struct radeon_device *rdev);
2193int radeon_asic_init(struct radeon_device *rdev);
2194
771fe6b9
JG		 2195
2196/*
2197 * IOCTL.
2198 */
2199int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2200 struct drm_file *filp);
2201int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2202 struct drm_file *filp);
f72a113a
CK		 2203int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2204 struct drm_file *filp);
771fe6b9
JG		 2205int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2206 struct drm_file *file_priv);
2207int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2208 struct drm_file *file_priv);
2209int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2210 struct drm_file *file_priv);
2211int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2212 struct drm_file *file_priv);
2213int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2214 struct drm_file *filp);
2215int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2216 struct drm_file *filp);
2217int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2218 struct drm_file *filp);
2219int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2220 struct drm_file *filp);
721604a1
JG		 2221int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2222 struct drm_file *filp);
bda72d58
MO		 2223int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2224 struct drm_file *filp);
771fe6b9 2225int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 2226int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2227 struct drm_file *filp);
2228int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2229 struct drm_file *filp);
771fe6b9 2230
16cdf04d
AD		 2231/* VRAM scratch page for HDP bug, default vram page */
2232struct r600_vram_scratch {
87cbf8f2
AD		 2233 struct radeon_bo *robj;
2234 volatile uint32_t *ptr;
16cdf04d 2235 u64 gpu_addr;
87cbf8f2 2236};
771fe6b9 2237
fd64ca8a
LT		 2238/*
2239 * ACPI
2240 */
2241struct radeon_atif_notification_cfg {
2242 bool enabled;
2243 int command_code;
2244};
2245
2246struct radeon_atif_notifications {
2247 bool display_switch;
2248 bool expansion_mode_change;
2249 bool thermal_state;
2250 bool forced_power_state;
2251 bool system_power_state;
2252 bool display_conf_change;
2253 bool px_gfx_switch;
2254 bool brightness_change;
2255 bool dgpu_display_event;
2256};
2257
2258struct radeon_atif_functions {
2259 bool system_params;
2260 bool sbios_requests;
2261 bool select_active_disp;
2262 bool lid_state;
2263 bool get_tv_standard;
2264 bool set_tv_standard;
2265 bool get_panel_expansion_mode;
2266 bool set_panel_expansion_mode;
2267 bool temperature_change;
2268 bool graphics_device_types;
2269};
2270
2271struct radeon_atif {
2272 struct radeon_atif_notifications notifications;
2273 struct radeon_atif_functions functions;
2274 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2275 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2276};
7a1619b9 2277
e3a15920
AD		 2278struct radeon_atcs_functions {
2279 bool get_ext_state;
2280 bool pcie_perf_req;
2281 bool pcie_dev_rdy;
2282 bool pcie_bus_width;
2283};
2284
2285struct radeon_atcs {
2286 struct radeon_atcs_functions functions;
2287};
2288
771fe6b9
JG		 2289/*
2290 * Core structure, functions and helpers.
2291 */
2292typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2293typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2294
2295struct radeon_device {
9f022ddf 2296 struct device *dev;
771fe6b9
JG		 2297 struct drm_device *ddev;
2298 struct pci_dev *pdev;
dee53e7f 2299 struct rw_semaphore exclusive_lock;
771fe6b9 2300 /* ASIC */
068a117c 2301 union radeon_asic_config config;
771fe6b9
JG		 2302 enum radeon_family family;
2303 unsigned long flags;
2304 int usec_timeout;
2305 enum radeon_pll_errata pll_errata;
2306 int num_gb_pipes;
f779b3e5 2307 int num_z_pipes;
771fe6b9
JG		 2308 int disp_priority;
2309 /* BIOS */
2310 uint8_t *bios;
2311 bool is_atom_bios;
2312 uint16_t bios_header_start;
4c788679 2313 struct radeon_bo *stollen_vga_memory;
771fe6b9 2314 /* Register mmio */
4c9bc75c
DA		 2315 resource_size_t rmmio_base;
2316 resource_size_t rmmio_size;
2c385151
DV		 2317 /* protects concurrent MM_INDEX/DATA based register access */
2318 spinlock_t mmio_idx_lock;
fe78118c
AD		 2319 /* protects concurrent SMC based register access */
2320 spinlock_t smc_idx_lock;
0a5b7b0b
AD		 2321 /* protects concurrent PLL register access */
2322 spinlock_t pll_idx_lock;
2323 /* protects concurrent MC register access */
2324 spinlock_t mc_idx_lock;
2325 /* protects concurrent PCIE register access */
2326 spinlock_t pcie_idx_lock;
2327 /* protects concurrent PCIE_PORT register access */
2328 spinlock_t pciep_idx_lock;
2329 /* protects concurrent PIF register access */
2330 spinlock_t pif_idx_lock;
2331 /* protects concurrent CG register access */
2332 spinlock_t cg_idx_lock;
2333 /* protects concurrent UVD register access */
2334 spinlock_t uvd_idx_lock;
2335 /* protects concurrent RCU register access */
2336 spinlock_t rcu_idx_lock;
2337 /* protects concurrent DIDT register access */
2338 spinlock_t didt_idx_lock;
2339 /* protects concurrent ENDPOINT (audio) register access */
2340 spinlock_t end_idx_lock;
a0533fbf 2341 void __iomem *rmmio;
771fe6b9
JG		 2342 radeon_rreg_t mc_rreg;
2343 radeon_wreg_t mc_wreg;
2344 radeon_rreg_t pll_rreg;
2345 radeon_wreg_t pll_wreg;
de1b2898 2346 uint32_t pcie_reg_mask;
771fe6b9
JG		 2347 radeon_rreg_t pciep_rreg;
2348 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2349 /* io port */
2350 void __iomem *rio_mem;
2351 resource_size_t rio_mem_size;
771fe6b9
JG		 2352 struct radeon_clock clock;
2353 struct radeon_mc mc;
2354 struct radeon_gart gart;
2355 struct radeon_mode_info mode_info;
2356 struct radeon_scratch scratch;
75efdee1 2357 struct radeon_doorbell doorbell;
771fe6b9 2358 struct radeon_mman mman;
7465280c 2359 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2360 wait_queue_head_t fence_queue;
954605ca 2361 unsigned fence_context;
d6999bc7 2362 struct mutex ring_lock;
e32eb50d 2363 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2364 bool ib_pool_ready;
2365 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2366 struct radeon_irq irq;
2367 struct radeon_asic *asic;
2368 struct radeon_gem gem;
c93bb85b 2369 struct radeon_pm pm;
f2ba57b5 2370 struct radeon_uvd uvd;
d93f7937 2371 struct radeon_vce vce;
f657c2a7 2372 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2373 struct radeon_wb wb;
3ce0a23d 2374 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2375 bool shutdown;
2376 bool suspend;
ad49f501 2377 bool need_dma32;
733289c2 2378 bool accel_working;
a0a53aa8 2379 bool fastfb_working; /* IGP feature*/
9bb39ff4 2380 bool needs_reset, in_reset;
e024e110 2381 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2382 const struct firmware *me_fw; /* all family ME firmware */
2383 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2384 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2385 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2386 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2387 const struct firmware *mec_fw; /* CIK MEC firmware */
f2c6b0f4 2388 const struct firmware *mec2_fw; /* KV MEC2 firmware */
21a93e13 2389 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2390 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2391 const struct firmware *uvd_fw; /* UVD firmware */
d93f7937 2392 const struct firmware *vce_fw; /* VCE firmware */
629bd33c 2393 bool new_fw;
16cdf04d 2394 struct r600_vram_scratch vram_scratch;
3e5cb98d 2395 int msi_enabled; /* msi enabled */
d8f60cfc 2396 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2397 struct radeon_rlc rlc;
963e81f9 2398 struct radeon_mec mec;
d4877cf2 2399 struct work_struct hotplug_work;
f122c610 2400 struct work_struct audio_work;
18917b60 2401 int num_crtc; /* number of crtcs */
40bacf16 2402 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
948bee3f 2403 bool has_uvd;
b530602f 2404 struct r600_audio audio; /* audio stuff */
ce8f5370 2405 struct notifier_block acpi_nb;
9eba4a93 2406 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2407 struct drm_file *hyperz_filp;
9eba4a93 2408 struct drm_file *cmask_filp;
f376b94f
AD		 2409 /* i2c buses */
2410 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2411 /* debugfs */
2412 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2413 unsigned debugfs_count;
721604a1
JG		 2414 /* virtual memory */
2415 struct radeon_vm_manager vm_manager;
6759a0a7 2416 struct mutex gpu_clock_mutex;
67e8e3f9
MO		 2417 /* memory stats */
2418 atomic64_t vram_usage;
2419 atomic64_t gtt_usage;
2420 atomic64_t num_bytes_moved;
fd64ca8a
LT		 2421 /* ACPI interface */
2422 struct radeon_atif atif;
e3a15920 2423 struct radeon_atcs atcs;
f61d5b46
AD		 2424 /* srbm instance registers */
2425 struct mutex srbm_mutex;
1c0a4625
OG		 2426 /* GRBM index mutex. Protects concurrents access to GRBM index */
2427 struct mutex grbm_idx_mutex;
64d8a728
AD		 2428 /* clock, powergating flags */
2429 u32 cg_flags;
2430 u32 pg_flags;
10ebc0bc
DA		 2431
2432 struct dev_pm_domain vga_pm_domain;
2433 bool have_disp_power_ref;
4807c5a8 2434 u32 px_quirk_flags;
71ecc97e
AD		 2435
2436 /* tracking pinned memory */
2437 u64 vram_pin_size;
2438 u64 gart_pin_size;
341cb9e4 2439
e28740ec
OG		 2440 /* amdkfd interface */
2441 struct kfd_dev *kfd;
2442 struct radeon_sa_manager kfd_bo;
2443
341cb9e4
CK		 2444 struct mutex mn_lock;
2445 DECLARE_HASHTABLE(mn_hash, 7);
771fe6b9
JG		 2446};
2447
90c4cde9 2448bool radeon_is_px(struct drm_device *dev);
771fe6b9
JG		 2449int radeon_device_init(struct radeon_device *rdev,
2450 struct drm_device *ddev,
2451 struct pci_dev *pdev,
2452 uint32_t flags);
2453void radeon_device_fini(struct radeon_device *rdev);
2454int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2455
59bc1d89
LK		 2456#define RADEON_MIN_MMIO_SIZE 0x10000
2457
2458static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2459 bool always_indirect)
2460{
2461 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2462 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2463 return readl(((void __iomem *)rdev->rmmio) + reg);
2464 else {
2465 unsigned long flags;
2466 uint32_t ret;
2467
2468 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2469 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2470 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2471 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2472
2473 return ret;
2474 }
2475}
2476
2477static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2478 bool always_indirect)
2479{
2480 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2481 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2482 else {
2483 unsigned long flags;
2484
2485 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2486 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2487 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2488 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2489 }
2490}
2491
6fcbef7a
AK		 2492u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2493void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2494
d5754ab8
AL		 2495u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2496void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
75efdee1 2497
4c788679
JG		 2498/*
2499 * Cast helper
2500 */
954605ca
ML		 2501extern const struct fence_ops radeon_fence_ops;
2502
2503static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2504{
2505 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2506
2507 if (__f->base.ops == &radeon_fence_ops)
2508 return __f;
2509
2510 return NULL;
2511}
771fe6b9
JG		 2512
2513/*
2514 * Registers read & write functions.
2515 */
a0533fbf
BH		 2516#define RREG8(reg) readb((rdev->rmmio) + (reg))
2517#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2518#define RREG16(reg) readw((rdev->rmmio) + (reg))
2519#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2520#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2521#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2522#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2523#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2524#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2525#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2526#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2527#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2528#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2529#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2530#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2531#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2532#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2533#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2534#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2535#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2536#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2537#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2538#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2539#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2540#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2541#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2542#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2543#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2544#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2545#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2546#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2547#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2548#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2549#define WREG32_P(reg, val, mask) \
2550 do { \
2551 uint32_t tmp_ = RREG32(reg); \
2552 tmp_ &= (mask); \
2553 tmp_ |= ((val) & ~(mask)); \
2554 WREG32(reg, tmp_); \
2555 } while (0)
d5169fc4 2556#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2557#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2558#define WREG32_PLL_P(reg, val, mask) \
2559 do { \
2560 uint32_t tmp_ = RREG32_PLL(reg); \
2561 tmp_ &= (mask); \
2562 tmp_ |= ((val) & ~(mask)); \
2563 WREG32_PLL(reg, tmp_); \
2564 } while (0)
2ef9bdfe 2565#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2566#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2567#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2568
d5754ab8
AL		 2569#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2570#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
75efdee1 2571
de1b2898
DA		 2572/*
2573 * Indirect registers accessor
2574 */
2575static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2576{
0a5b7b0b 2577 unsigned long flags;
de1b2898
DA		 2578 uint32_t r;
2579
0a5b7b0b 2580 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2581 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2582 r = RREG32(RADEON_PCIE_DATA);
0a5b7b0b 2583 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2584 return r;
2585}
2586
2587static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2588{
0a5b7b0b
AD		 2589 unsigned long flags;
2590
2591 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2592 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2593 WREG32(RADEON_PCIE_DATA, (v));
0a5b7b0b 2594 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2595}
2596
1d5d0c34
AD		 2597static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2598{
fe78118c 2599 unsigned long flags;
1d5d0c34
AD		 2600 u32 r;
2601
fe78118c 2602 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2603 WREG32(TN_SMC_IND_INDEX_0, (reg));
2604 r = RREG32(TN_SMC_IND_DATA_0);
fe78118c 2605 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2606 return r;
2607}
2608
2609static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2610{
fe78118c
AD		 2611 unsigned long flags;
2612
2613 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2614 WREG32(TN_SMC_IND_INDEX_0, (reg));
2615 WREG32(TN_SMC_IND_DATA_0, (v));
fe78118c 2616 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2617}
2618
ff82bbc4
AD		 2619static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2620{
0a5b7b0b 2621 unsigned long flags;
ff82bbc4
AD		 2622 u32 r;
2623
0a5b7b0b 2624 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2625 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2626 r = RREG32(R600_RCU_DATA);
0a5b7b0b 2627 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2628 return r;
2629}
2630
2631static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2632{
0a5b7b0b
AD		 2633 unsigned long flags;
2634
2635 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2636 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2637 WREG32(R600_RCU_DATA, (v));
0a5b7b0b 2638 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2639}
2640
46f9564a
AD		 2641static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2642{
0a5b7b0b 2643 unsigned long flags;
46f9564a
AD		 2644 u32 r;
2645
0a5b7b0b 2646 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2647 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2648 r = RREG32(EVERGREEN_CG_IND_DATA);
0a5b7b0b 2649 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2650 return r;
2651}
2652
2653static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2654{
0a5b7b0b
AD		 2655 unsigned long flags;
2656
2657 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2658 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2659 WREG32(EVERGREEN_CG_IND_DATA, (v));
0a5b7b0b 2660 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2661}
2662
792edd69
AD		 2663static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2664{
0a5b7b0b 2665 unsigned long flags;
792edd69
AD		 2666 u32 r;
2667
0a5b7b0b 2668 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2669 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2670 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
0a5b7b0b 2671 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2672 return r;
2673}
2674
2675static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2676{
0a5b7b0b
AD		 2677 unsigned long flags;
2678
2679 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2680 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2681 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
0a5b7b0b 2682 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2683}
2684
2685static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2686{
0a5b7b0b 2687 unsigned long flags;
792edd69
AD		 2688 u32 r;
2689
0a5b7b0b 2690 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2691 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2692 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
0a5b7b0b 2693 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2694 return r;
2695}
2696
2697static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2698{
0a5b7b0b
AD		 2699 unsigned long flags;
2700
2701 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2702 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2703 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
0a5b7b0b 2704 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2705}
2706
93656cdd
AD		 2707static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2708{
0a5b7b0b 2709 unsigned long flags;
93656cdd
AD		 2710 u32 r;
2711
0a5b7b0b 2712 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2713 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2714 r = RREG32(R600_UVD_CTX_DATA);
0a5b7b0b 2715 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2716 return r;
2717}
2718
2719static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2720{
0a5b7b0b
AD		 2721 unsigned long flags;
2722
2723 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2724 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2725 WREG32(R600_UVD_CTX_DATA, (v));
0a5b7b0b 2726 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2727}
2728
1d58234d
AD		 2729
2730static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2731{
0a5b7b0b 2732 unsigned long flags;
1d58234d
AD		 2733 u32 r;
2734
0a5b7b0b 2735 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2736 WREG32(CIK_DIDT_IND_INDEX, (reg));
2737 r = RREG32(CIK_DIDT_IND_DATA);
0a5b7b0b 2738 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2739 return r;
2740}
2741
2742static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2743{
0a5b7b0b
AD		 2744 unsigned long flags;
2745
2746 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2747 WREG32(CIK_DIDT_IND_INDEX, (reg));
2748 WREG32(CIK_DIDT_IND_DATA, (v));
0a5b7b0b 2749 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2750}
2751
771fe6b9
JG		 2752void r100_pll_errata_after_index(struct radeon_device *rdev);
2753
2754
2755/*
2756 * ASICs helpers.
2757 */
b995e433
DA		 2758#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2759 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2760#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2761 (rdev->family == CHIP_RV200) || \
2762 (rdev->family == CHIP_RS100) || \
2763 (rdev->family == CHIP_RS200) || \
2764 (rdev->family == CHIP_RV250) || \
2765 (rdev->family == CHIP_RV280) || \
2766 (rdev->family == CHIP_RS300))
2767#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2768 (rdev->family == CHIP_RV350) || \
2769 (rdev->family == CHIP_R350) || \
2770 (rdev->family == CHIP_RV380) || \
2771 (rdev->family == CHIP_R420) || \
2772 (rdev->family == CHIP_R423) || \
2773 (rdev->family == CHIP_RV410) || \
2774 (rdev->family == CHIP_RS400) || \
2775 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2776#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2777 (rdev->ddev->pdev->device == 0x9443) || \
2778 (rdev->ddev->pdev->device == 0x944B) || \
2779 (rdev->ddev->pdev->device == 0x9506) || \
2780 (rdev->ddev->pdev->device == 0x9509) || \
2781 (rdev->ddev->pdev->device == 0x950F) || \
2782 (rdev->ddev->pdev->device == 0x689C) || \
2783 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2784#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2785#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2786 (rdev->family == CHIP_RS690) || \
2787 (rdev->family == CHIP_RS740) || \
2788 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2789#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2790#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2791#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2792#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2793 (rdev->flags & RADEON_IS_IGP))
1fe18305 2794#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2795#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2796#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2797 (rdev->flags & RADEON_IS_IGP))
624d3524 2798#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2799#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2800#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
be0949f5
AD		 2801#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2802#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
89d2618d
AD		 2803#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2804 (rdev->family == CHIP_MULLINS))
771fe6b9 2805
dc50ba7f
AD		 2806#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2807 (rdev->ddev->pdev->device == 0x6850) || \
2808 (rdev->ddev->pdev->device == 0x6858) || \
2809 (rdev->ddev->pdev->device == 0x6859) || \
2810 (rdev->ddev->pdev->device == 0x6840) || \
2811 (rdev->ddev->pdev->device == 0x6841) || \
2812 (rdev->ddev->pdev->device == 0x6842) || \
2813 (rdev->ddev->pdev->device == 0x6843))
2814
771fe6b9
JG		 2815/*
2816 * BIOS helpers.
2817 */
2818#define RBIOS8(i) (rdev->bios[i])
2819#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2820#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2821
2822int radeon_combios_init(struct radeon_device *rdev);
2823void radeon_combios_fini(struct radeon_device *rdev);
2824int radeon_atombios_init(struct radeon_device *rdev);
2825void radeon_atombios_fini(struct radeon_device *rdev);
2826
2827
2828/*
2829 * RING helpers.
2830 */
edf0ac7c
DH		 2831
2832/**
2833 * radeon_ring_write - write a value to the ring
2834 *
2835 * @ring: radeon_ring structure holding ring information
2836 * @v: dword (dw) value to write
2837 *
2838 * Write a value to the requested ring buffer (all asics).
2839 */
e32eb50d 2840static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2841{
edf0ac7c
DH		 2842 if (ring->count_dw <= 0)
2843 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2844
e32eb50d
CK		 2845 ring->ring[ring->wptr++] = v;
2846 ring->wptr &= ring->ptr_mask;
2847 ring->count_dw--;
2848 ring->ring_free_dw--;
771fe6b9 2849}
771fe6b9
JG		 2850
2851/*
2852 * ASICs macro.
2853 */
068a117c 2854#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2855#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2856#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2857#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2858#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2859#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2860#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850 2861#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
77497f27 2862#define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f))
05b07147
CK		 2863#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2864#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
03f62abd
CK		 2865#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2866#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2867#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2868#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
76a0df85
CK		 2869#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2870#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2871#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2872#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2873#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2874#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
faffaf62 2875#define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
76a0df85
CK		 2876#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2877#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2878#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2879#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2880#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2881#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2882#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2883#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2884#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2885#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2886#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2887#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
57d20a43
CK		 2888#define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2889#define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2890#define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
27cd7769
AD		 2891#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2892#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2893#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2894#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2895#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2896#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2897#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2898#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2899#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2900#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2901#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
b59b7333 2902#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
6bd1c385 2903#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2904#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2905#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2906#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2907#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2908#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2909#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2910#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2911#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2912#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2913#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2914#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2915#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2916#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8 2917#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
157fa14d 2918#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
69b62ad8
AD		 2919#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2920#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2921#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2922#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2923#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2924#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2925#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
914a8987 2926#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
da321c8a 2927#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2928#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2929#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2930#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2931#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2932#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2933#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2934#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2935#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2936#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2937#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2938#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2939#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
1c71bda0 2940#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
771fe6b9 2941
6cf8a3f5 2942/* Common functions */
700a0cc0 2943/* AGP */
90aca4d2 2944extern int radeon_gpu_reset(struct radeon_device *rdev);
1a0041b8 2945extern void radeon_pci_config_reset(struct radeon_device *rdev);
410a3418 2946extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2947extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2948extern int radeon_modeset_init(struct radeon_device *rdev);
2949extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2950extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2951extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2952extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2953extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2954extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2955extern void radeon_wb_fini(struct radeon_device *rdev);
2956extern int radeon_wb_init(struct radeon_device *rdev);
2957extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2958extern void radeon_surface_init(struct radeon_device *rdev);
2959extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2960extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2961extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2962extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2963extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
f72a113a
CK		 2964extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2965 uint32_t flags);
2966extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2967extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
d594e46a
JG		 2968extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2969extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
10ebc0bc
DA		 2970extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2971extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
53595338 2972extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2973extern void radeon_program_register_sequence(struct radeon_device *rdev,
2974 const u32 *registers,
2975 const u32 array_size);
6cf8a3f5 2976
721604a1
JG		 2977/*
2978 * vm
2979 */
2980int radeon_vm_manager_init(struct radeon_device *rdev);
2981void radeon_vm_manager_fini(struct radeon_device *rdev);
6d2f2944 2982int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2983void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1d0c0942 2984struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
df0af440
CK		 2985 struct radeon_vm *vm,
2986 struct list_head *head);
ee60e29f
CK		 2987struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2988 struct radeon_vm *vm, int ring);
fa688343
CK		 2989void radeon_vm_flush(struct radeon_device *rdev,
2990 struct radeon_vm *vm,
ad1a58a4 2991 int ring, struct radeon_fence *fence);
ee60e29f
CK		 2992void radeon_vm_fence(struct radeon_device *rdev,
2993 struct radeon_vm *vm,
2994 struct radeon_fence *fence);
dce34bfd 2995uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
6d2f2944
CK		 2996int radeon_vm_update_page_directory(struct radeon_device *rdev,
2997 struct radeon_vm *vm);
036bf46a
CK		 2998int radeon_vm_clear_freed(struct radeon_device *rdev,
2999 struct radeon_vm *vm);
e31ad969
CK		 3000int radeon_vm_clear_invalids(struct radeon_device *rdev,
3001 struct radeon_vm *vm);
9c57a6bd 3002int radeon_vm_bo_update(struct radeon_device *rdev,
036bf46a 3003 struct radeon_bo_va *bo_va,
9c57a6bd 3004 struct ttm_mem_reg *mem);
721604a1
JG		 3005void radeon_vm_bo_invalidate(struct radeon_device *rdev,
3006 struct radeon_bo *bo);
421ca7ab
CK		 3007struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
3008 struct radeon_bo *bo);
e971bd5e
CK		 3009struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
3010 struct radeon_vm *vm,
3011 struct radeon_bo *bo);
3012int radeon_vm_bo_set_addr(struct radeon_device *rdev,
3013 struct radeon_bo_va *bo_va,
3014 uint64_t offset,
3015 uint32_t flags);
036bf46a
CK		 3016void radeon_vm_bo_rmv(struct radeon_device *rdev,
3017 struct radeon_bo_va *bo_va);
721604a1 3018
f122c610
AD		 3019/* audio */
3020void r600_audio_update_hdmi(struct work_struct *work);
b530602f
AD		 3021struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
3022struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
832eafaf
AD		 3023void r600_audio_enable(struct radeon_device *rdev,
3024 struct r600_audio_pin *pin,
d3d8c141 3025 u8 enable_mask);
832eafaf
AD		 3026void dce6_audio_enable(struct radeon_device *rdev,
3027 struct r600_audio_pin *pin,
d3d8c141 3028 u8 enable_mask);
721604a1 3029
16cdf04d
AD		 3030/*
3031 * R600 vram scratch functions
3032 */
3033int r600_vram_scratch_init(struct radeon_device *rdev);
3034void r600_vram_scratch_fini(struct radeon_device *rdev);
3035
285484e2
JG		 3036/*
3037 * r600 cs checking helper
3038 */
3039unsigned r600_mip_minify(unsigned size, unsigned level);
3040bool r600_fmt_is_valid_color(u32 format);
3041bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
3042int r600_fmt_get_blocksize(u32 format);
3043int r600_fmt_get_nblocksx(u32 format, u32 w);
3044int r600_fmt_get_nblocksy(u32 format, u32 h);
3045
3574dda4
DV		 3046/*
3047 * r600 functions used by radeon_encoder.c
3048 */
1b688d08
RM		 3049struct radeon_hdmi_acr {
3050 u32 clock;
3051
3052 int n_32khz;
3053 int cts_32khz;
3054
3055 int n_44_1khz;
3056 int cts_44_1khz;
3057
3058 int n_48khz;
3059 int cts_48khz;
3060
3061};
3062
e55d3e6c
RM		 3063extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
3064
416a2bd2
AD		 3065extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
3066 u32 tiling_pipe_num,
3067 u32 max_rb_num,
3068 u32 total_max_rb_num,
3069 u32 enabled_rb_mask);
fe251e2f 3070
e55d3e6c
RM		 3071/*
3072 * evergreen functions used by radeon_encoder.c
3073 */
3074
0af62b01 3075extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 3076extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 3077
c4917074
AD		 3078/* radeon_acpi.c */
3079#if defined(CONFIG_ACPI)
3080extern int radeon_acpi_init(struct radeon_device *rdev);
3081extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 3082extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
3083extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 3084 u8 perf_req, bool advertise);
dc50ba7f 3085extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 3086#else
3087static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
3088static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
3089#endif
d7a2952f 3090
c38f34b5
IH		 3091int radeon_cs_packet_parse(struct radeon_cs_parser *p,
3092 struct radeon_cs_packet *pkt,
3093 unsigned idx);
9ffb7a6d 3094bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 3095void radeon_cs_dump_packet(struct radeon_cs_parser *p,
3096 struct radeon_cs_packet *pkt);
e9716993 3097int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
1d0c0942 3098 struct radeon_bo_list **cs_reloc,
e9716993 3099 int nomm);
40592a17
IH		 3100int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
3101 uint32_t *vline_start_end,
3102 uint32_t *vline_status);
c38f34b5 3103
4c788679
JG		 3104#include "radeon_object.h"
3105
771fe6b9 3106#endif
Linux kernel - Deliverables
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