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drm/radeon: add VRAM debugfs access v3
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
a18cee15 96extern int radeon_msi;
3368ff0c 97extern int radeon_lockup_timeout;
a0a53aa8 98extern int radeon_fastfb;
da321c8a 99extern int radeon_dpm;
1294d4a3 100extern int radeon_aspm;
10ebc0bc 101extern int radeon_runtime_pm;
771fe6b9
JG		 102
103/*
104 * Copy from radeon_drv.h so we don't have to include both and have conflicting
105 * symbol;
106 */
bb635567
JG		 107#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
108#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 109/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 110#define RADEON_IB_POOL_SIZE 16
111#define RADEON_DEBUGFS_MAX_COMPONENTS 32
112#define RADEONFB_CONN_LIMIT 4
113#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 114
1b37078b 115/* max number of rings */
f2ba57b5 116#define RADEON_NUM_RINGS 6
bb635567
JG		 117
118/* fence seq are set to this number when signaled */
119#define RADEON_FENCE_SIGNALED_SEQ 0LL
1b37078b
AD		 120
121/* internal ring indices */
122/* r1xx+ has gfx CP ring */
f2ba57b5 123#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 124
125/* cayman has 2 compute CP rings */
f2ba57b5
CK		 126#define CAYMAN_RING_TYPE_CP1_INDEX 1
127#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 128
4d75658b
AD		 129/* R600+ has an async dma ring */
130#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 131/* cayman add a second async dma ring */
132#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 133
f2ba57b5
CK		 134/* R600+ */
135#define R600_RING_TYPE_UVD_INDEX 5
136
721604a1 137/* hardcode those limit for now */
ca19f21e 138#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 139#define RADEON_VA_RESERVED_SIZE (8 << 20)
140#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 141
ec46c76d
AD		 142/* reset flags */
143#define RADEON_RESET_GFX (1 << 0)
144#define RADEON_RESET_COMPUTE (1 << 1)
145#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 146#define RADEON_RESET_CP (1 << 3)
147#define RADEON_RESET_GRBM (1 << 4)
148#define RADEON_RESET_DMA1 (1 << 5)
149#define RADEON_RESET_RLC (1 << 6)
150#define RADEON_RESET_SEM (1 << 7)
151#define RADEON_RESET_IH (1 << 8)
152#define RADEON_RESET_VMC (1 << 9)
153#define RADEON_RESET_MC (1 << 10)
154#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 155
22c775ce
AD		 156/* CG block flags */
157#define RADEON_CG_BLOCK_GFX (1 << 0)
158#define RADEON_CG_BLOCK_MC (1 << 1)
159#define RADEON_CG_BLOCK_SDMA (1 << 2)
160#define RADEON_CG_BLOCK_UVD (1 << 3)
161#define RADEON_CG_BLOCK_VCE (1 << 4)
162#define RADEON_CG_BLOCK_HDP (1 << 5)
e16866ec 163#define RADEON_CG_BLOCK_BIF (1 << 6)
22c775ce 164
64d8a728
AD		 165/* CG flags */
166#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
167#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
168#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
169#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
170#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
171#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
172#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
173#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
174#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
175#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
176#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
177#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
178#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
179#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
180#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
181#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
182#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
183
184/* PG flags */
2b19d17f 185#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
64d8a728
AD		 186#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
187#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
188#define RADEON_PG_SUPPORT_UVD (1 << 3)
189#define RADEON_PG_SUPPORT_VCE (1 << 4)
190#define RADEON_PG_SUPPORT_CP (1 << 5)
191#define RADEON_PG_SUPPORT_GDS (1 << 6)
192#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
193#define RADEON_PG_SUPPORT_SDMA (1 << 8)
194#define RADEON_PG_SUPPORT_ACP (1 << 9)
195#define RADEON_PG_SUPPORT_SAMU (1 << 10)
196
9e05fa1d
AD		 197/* max cursor sizes (in pixels) */
198#define CURSOR_WIDTH 64
199#define CURSOR_HEIGHT 64
200
201#define CIK_CURSOR_WIDTH 128
202#define CIK_CURSOR_HEIGHT 128
203
771fe6b9
JG		 204/*
205 * Errata workarounds.
206 */
207enum radeon_pll_errata {
208 CHIP_ERRATA_R300_CG = 0x00000001,
209 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
210 CHIP_ERRATA_PLL_DELAY = 0x00000004
211};
212
213
214struct radeon_device;
215
216
217/*
218 * BIOS.
219 */
220bool radeon_get_bios(struct radeon_device *rdev);
221
222/*
3ce0a23d 223 * Dummy page
771fe6b9 224 */
3ce0a23d
JG		 225struct radeon_dummy_page {
226 struct page *page;
227 dma_addr_t addr;
228};
229int radeon_dummy_page_init(struct radeon_device *rdev);
230void radeon_dummy_page_fini(struct radeon_device *rdev);
231
771fe6b9 232
3ce0a23d
JG		 233/*
234 * Clocks
235 */
771fe6b9
JG		 236struct radeon_clock {
237 struct radeon_pll p1pll;
238 struct radeon_pll p2pll;
bcc1c2a1 239 struct radeon_pll dcpll;
771fe6b9
JG		 240 struct radeon_pll spll;
241 struct radeon_pll mpll;
242 /* 10 Khz units */
243 uint32_t default_mclk;
244 uint32_t default_sclk;
bcc1c2a1 245 uint32_t default_dispclk;
4489cd62 246 uint32_t current_dispclk;
bcc1c2a1 247 uint32_t dp_extclk;
b20f9bef 248 uint32_t max_pixel_clock;
771fe6b9
JG		 249};
250
7433874e
RM		 251/*
252 * Power management
253 */
254int radeon_pm_init(struct radeon_device *rdev);
29fb52ca 255void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 256void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 257void radeon_pm_suspend(struct radeon_device *rdev);
258void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 259void radeon_combios_get_power_modes(struct radeon_device *rdev);
260void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 261int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
262 u8 clock_type,
263 u32 clock,
264 bool strobe_mode,
265 struct atom_clock_dividers *dividers);
eaa778af
AD		 266int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
267 u32 clock,
268 bool strobe_mode,
269 struct atom_mpll_param *mpll_param);
8a83ec5e 270void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 271int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
272 u16 voltage_level, u8 voltage_type,
273 u32 *gpio_value, u32 *gpio_mask);
274void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
275 u32 eng_clock, u32 mem_clock);
276int radeon_atom_get_voltage_step(struct radeon_device *rdev,
277 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 278int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
279 u16 voltage_id, u16 *voltage);
beb79f40
AD		 280int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
281 u16 *voltage,
282 u16 leakage_idx);
cc8dbbb4
AD		 283int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
284 u16 *leakage_id);
285int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
286 u16 *vddc, u16 *vddci,
287 u16 virtual_voltage_id,
288 u16 vbios_voltage_id);
ae5b0abb
AD		 289int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
290 u8 voltage_type,
291 u16 nominal_voltage,
292 u16 *true_voltage);
293int radeon_atom_get_min_voltage(struct radeon_device *rdev,
294 u8 voltage_type, u16 *min_voltage);
295int radeon_atom_get_max_voltage(struct radeon_device *rdev,
296 u8 voltage_type, u16 *max_voltage);
297int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 298 u8 voltage_type, u8 voltage_mode,
ae5b0abb 299 struct atom_voltage_table *voltage_table);
58653abd
AD		 300bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
301 u8 voltage_type, u8 voltage_mode);
ae5b0abb
AD		 302void radeon_atom_update_memory_dll(struct radeon_device *rdev,
303 u32 mem_clock);
304void radeon_atom_set_ac_timing(struct radeon_device *rdev,
305 u32 mem_clock);
306int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
307 u8 module_index,
308 struct atom_mc_reg_table *reg_table);
309int radeon_atom_get_memory_info(struct radeon_device *rdev,
310 u8 module_index, struct atom_memory_info *mem_info);
311int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
312 bool gddr5, u8 module_index,
313 struct atom_memory_clock_range_table *mclk_range_table);
314int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
315 u16 voltage_id, u16 *voltage);
f892034a 316void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 317extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
318 unsigned *bankh, unsigned *mtaspect,
319 unsigned *tile_split);
3ce0a23d 320
771fe6b9
JG		 321/*
322 * Fences.
323 */
324struct radeon_fence_driver {
325 uint32_t scratch_reg;
30eb77f4
JG		 326 uint64_t gpu_addr;
327 volatile uint32_t *cpu_addr;
68e250b7
CK		 328 /* sync_seq is protected by ring emission lock */
329 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 330 atomic64_t last_seq;
0a0c7596 331 bool initialized;
771fe6b9
JG		 332};
333
334struct radeon_fence {
335 struct radeon_device *rdev;
336 struct kref kref;
771fe6b9 337 /* protected by radeon_fence.lock */
bb635567 338 uint64_t seq;
7465280c 339 /* RB, DMA, etc. */
bb635567 340 unsigned ring;
771fe6b9
JG		 341};
342
30eb77f4
JG		 343int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
344int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 345void radeon_fence_driver_fini(struct radeon_device *rdev);
76903b96 346void radeon_fence_driver_force_completion(struct radeon_device *rdev);
876dc9f3 347int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 348void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 349bool radeon_fence_signaled(struct radeon_fence *fence);
350int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
1654b817 351int radeon_fence_wait_locked(struct radeon_fence *fence);
8a47cc9e 352int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
5f8f635e 353int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
0085c950
JG		 354int radeon_fence_wait_any(struct radeon_device *rdev,
355 struct radeon_fence **fences,
356 bool intr);
771fe6b9
JG		 357struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
358void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 359unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 360bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
361void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
362static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
363 struct radeon_fence *b)
364{
365 if (!a) {
366 return b;
367 }
368
369 if (!b) {
370 return a;
371 }
372
373 BUG_ON(a->ring != b->ring);
374
375 if (a->seq > b->seq) {
376 return a;
377 } else {
378 return b;
379 }
380}
771fe6b9 381
ee60e29f
CK		 382static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
383 struct radeon_fence *b)
384{
385 if (!a) {
386 return false;
387 }
388
389 if (!b) {
390 return true;
391 }
392
393 BUG_ON(a->ring != b->ring);
394
395 return a->seq < b->seq;
396}
397
e024e110
DA		 398/*
399 * Tiling registers
400 */
401struct radeon_surface_reg {
4c788679 402 struct radeon_bo *bo;
e024e110
DA		 403};
404
405#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 406
407/*
4c788679 408 * TTM.
771fe6b9 409 */
4c788679
JG		 410struct radeon_mman {
411 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 412 struct drm_global_reference mem_global_ref;
4c788679 413 struct ttm_bo_device bdev;
0a0c7596
JG		 414 bool mem_global_referenced;
415 bool initialized;
2014b569
CK		 416
417#if defined(CONFIG_DEBUG_FS)
418 struct dentry *vram;
419#endif
4c788679
JG		 420};
421
721604a1
JG		 422/* bo virtual address in a specific vm */
423struct radeon_bo_va {
e971bd5e 424 /* protected by bo being reserved */
721604a1 425 struct list_head bo_list;
721604a1
JG		 426 uint64_t soffset;
427 uint64_t eoffset;
428 uint32_t flags;
429 bool valid;
e971bd5e
CK		 430 unsigned ref_count;
431
432 /* protected by vm mutex */
433 struct list_head vm_list;
434
435 /* constant after initialization */
436 struct radeon_vm *vm;
437 struct radeon_bo *bo;
721604a1
JG		 438};
439
4c788679
JG		 440struct radeon_bo {
441 /* Protected by gem.mutex */
442 struct list_head list;
443 /* Protected by tbo.reserved */
312ea8da
JG		 444 u32 placements[3];
445 struct ttm_placement placement;
4c788679
JG		 446 struct ttm_buffer_object tbo;
447 struct ttm_bo_kmap_obj kmap;
448 unsigned pin_count;
449 void *kptr;
450 u32 tiling_flags;
451 u32 pitch;
452 int surface_reg;
721604a1
JG		 453 /* list of all virtual address to which this bo
454 * is associated to
455 */
456 struct list_head va;
4c788679
JG		 457 /* Constant after initialization */
458 struct radeon_device *rdev;
441921d5 459 struct drm_gem_object gem_base;
63bc620b 460
409851f4
JG		 461 struct ttm_bo_kmap_obj dma_buf_vmap;
462 pid_t pid;
4c788679 463};
7e4d15d9 464#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 465
4c788679 466struct radeon_bo_list {
147666fb 467 struct ttm_validate_buffer tv;
4c788679 468 struct radeon_bo *bo;
771fe6b9 469 uint64_t gpu_offset;
4474f3a9
CK		 470 bool written;
471 unsigned domain;
472 unsigned alt_domain;
4c788679 473 u32 tiling_flags;
771fe6b9
JG		 474};
475
409851f4
JG		 476int radeon_gem_debugfs_init(struct radeon_device *rdev);
477
b15ba512
JG		 478/* sub-allocation manager, it has to be protected by another lock.
479 * By conception this is an helper for other part of the driver
480 * like the indirect buffer or semaphore, which both have their
481 * locking.
482 *
483 * Principe is simple, we keep a list of sub allocation in offset
484 * order (first entry has offset == 0, last entry has the highest
485 * offset).
486 *
487 * When allocating new object we first check if there is room at
488 * the end total_size - (last_object_offset + last_object_size) >=
489 * alloc_size. If so we allocate new object there.
490 *
491 * When there is not enough room at the end, we start waiting for
492 * each sub object until we reach object_offset+object_size >=
493 * alloc_size, this object then become the sub object we return.
494 *
495 * Alignment can't be bigger than page size.
496 *
497 * Hole are not considered for allocation to keep things simple.
498 * Assumption is that there won't be hole (all object on same
499 * alignment).
500 */
501struct radeon_sa_manager {
bfb38d35 502 wait_queue_head_t wq;
b15ba512 503 struct radeon_bo *bo;
c3b7fe8b
CK		 504 struct list_head *hole;
505 struct list_head flist[RADEON_NUM_RINGS];
506 struct list_head olist;
b15ba512
JG		 507 unsigned size;
508 uint64_t gpu_addr;
509 void *cpu_ptr;
510 uint32_t domain;
6c4f978b 511 uint32_t align;
b15ba512
JG		 512};
513
514struct radeon_sa_bo;
515
516/* sub-allocation buffer */
517struct radeon_sa_bo {
c3b7fe8b
CK		 518 struct list_head olist;
519 struct list_head flist;
b15ba512 520 struct radeon_sa_manager *manager;
e6661a96
CK		 521 unsigned soffset;
522 unsigned eoffset;
557017a0 523 struct radeon_fence *fence;
b15ba512
JG		 524};
525
771fe6b9
JG		 526/*
527 * GEM objects.
528 */
529struct radeon_gem {
4c788679 530 struct mutex mutex;
771fe6b9
JG		 531 struct list_head objects;
532};
533
534int radeon_gem_init(struct radeon_device *rdev);
535void radeon_gem_fini(struct radeon_device *rdev);
536int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 537 int alignment, int initial_domain,
538 bool discardable, bool kernel,
539 struct drm_gem_object **obj);
771fe6b9 540
ff72145b
DA		 541int radeon_mode_dumb_create(struct drm_file *file_priv,
542 struct drm_device *dev,
543 struct drm_mode_create_dumb *args);
544int radeon_mode_dumb_mmap(struct drm_file *filp,
545 struct drm_device *dev,
546 uint32_t handle, uint64_t *offset_p);
771fe6b9 547
c1341e52
JG		 548/*
549 * Semaphores.
550 */
c1341e52
JG		 551/* everything here is constant */
552struct radeon_semaphore {
a8c05940
JG		 553 struct radeon_sa_bo *sa_bo;
554 signed waiters;
c1341e52 555 uint64_t gpu_addr;
1654b817 556 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
c1341e52
JG		 557};
558
c1341e52
JG		 559int radeon_semaphore_create(struct radeon_device *rdev,
560 struct radeon_semaphore **semaphore);
1654b817 561bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
c1341e52 562 struct radeon_semaphore *semaphore);
1654b817 563bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
c1341e52 564 struct radeon_semaphore *semaphore);
1654b817
CK		 565void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
566 struct radeon_fence *fence);
8f676c4c
CK		 567int radeon_semaphore_sync_rings(struct radeon_device *rdev,
568 struct radeon_semaphore *semaphore,
1654b817 569 int waiting_ring);
c1341e52 570void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 571 struct radeon_semaphore **semaphore,
a8c05940 572 struct radeon_fence *fence);
c1341e52 573
771fe6b9
JG		 574/*
575 * GART structures, functions & helpers
576 */
577struct radeon_mc;
578
a77f1718 579#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 580#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 581#define RADEON_GPU_PAGE_SHIFT 12
721604a1 582#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 583
771fe6b9
JG		 584struct radeon_gart {
585 dma_addr_t table_addr;
c9a1be96
JG		 586 struct radeon_bo *robj;
587 void *ptr;
771fe6b9
JG		 588 unsigned num_gpu_pages;
589 unsigned num_cpu_pages;
590 unsigned table_size;
771fe6b9
JG		 591 struct page **pages;
592 dma_addr_t *pages_addr;
593 bool ready;
594};
595
596int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
597void radeon_gart_table_ram_free(struct radeon_device *rdev);
598int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
599void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 600int radeon_gart_table_vram_pin(struct radeon_device *rdev);
601void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 602int radeon_gart_init(struct radeon_device *rdev);
603void radeon_gart_fini(struct radeon_device *rdev);
604void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
605 int pages);
606int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516
KRW		 607 int pages, struct page **pagelist,
608 dma_addr_t *dma_addr);
c9a1be96 609void radeon_gart_restore(struct radeon_device *rdev);
771fe6b9
JG		 610
611
612/*
613 * GPU MC structures, functions & helpers
614 */
615struct radeon_mc {
616 resource_size_t aper_size;
617 resource_size_t aper_base;
618 resource_size_t agp_base;
7a50f01a
DA		 619 /* for some chips with <= 32MB we need to lie
620 * about vram size near mc fb location */
3ce0a23d 621 u64 mc_vram_size;
d594e46a 622 u64 visible_vram_size;
3ce0a23d
JG		 623 u64 gtt_size;
624 u64 gtt_start;
625 u64 gtt_end;
3ce0a23d
JG		 626 u64 vram_start;
627 u64 vram_end;
771fe6b9 628 unsigned vram_width;
3ce0a23d 629 u64 real_vram_size;
771fe6b9
JG		 630 int vram_mtrr;
631 bool vram_is_ddr;
d594e46a 632 bool igp_sideport_enabled;
8d369bb1 633 u64 gtt_base_align;
9ed8b1f9 634 u64 mc_mask;
771fe6b9
JG		 635};
636
06b6476d
AD		 637bool radeon_combios_sideport_present(struct radeon_device *rdev);
638bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 639
640/*
641 * GPU scratch registers structures, functions & helpers
642 */
643struct radeon_scratch {
644 unsigned num_reg;
724c80e1 645 uint32_t reg_base;
771fe6b9
JG		 646 bool free[32];
647 uint32_t reg[32];
648};
649
650int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
651void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
652
75efdee1
AD		 653/*
654 * GPU doorbell structures, functions & helpers
655 */
d5754ab8
AL		 656#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
657
75efdee1 658struct radeon_doorbell {
75efdee1 659 /* doorbell mmio */
d5754ab8
AL		 660 resource_size_t base;
661 resource_size_t size;
662 u32 __iomem *ptr;
663 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
664 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
75efdee1
AD		 665};
666
667int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
668void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771fe6b9
JG		 669
670/*
671 * IRQS.
672 */
6f34be50
AD		 673
674struct radeon_unpin_work {
675 struct work_struct work;
676 struct radeon_device *rdev;
677 int crtc_id;
678 struct radeon_fence *fence;
679 struct drm_pending_vblank_event *event;
680 struct radeon_bo *old_rbo;
681 u64 new_crtc_base;
682};
683
684struct r500_irq_stat_regs {
685 u32 disp_int;
f122c610 686 u32 hdmi0_status;
6f34be50
AD		 687};
688
689struct r600_irq_stat_regs {
690 u32 disp_int;
691 u32 disp_int_cont;
692 u32 disp_int_cont2;
693 u32 d1grph_int;
694 u32 d2grph_int;
f122c610
AD		 695 u32 hdmi0_status;
696 u32 hdmi1_status;
6f34be50
AD		 697};
698
699struct evergreen_irq_stat_regs {
700 u32 disp_int;
701 u32 disp_int_cont;
702 u32 disp_int_cont2;
703 u32 disp_int_cont3;
704 u32 disp_int_cont4;
705 u32 disp_int_cont5;
706 u32 d1grph_int;
707 u32 d2grph_int;
708 u32 d3grph_int;
709 u32 d4grph_int;
710 u32 d5grph_int;
711 u32 d6grph_int;
f122c610
AD		 712 u32 afmt_status1;
713 u32 afmt_status2;
714 u32 afmt_status3;
715 u32 afmt_status4;
716 u32 afmt_status5;
717 u32 afmt_status6;
6f34be50
AD		 718};
719
a59781bb
AD		 720struct cik_irq_stat_regs {
721 u32 disp_int;
722 u32 disp_int_cont;
723 u32 disp_int_cont2;
724 u32 disp_int_cont3;
725 u32 disp_int_cont4;
726 u32 disp_int_cont5;
727 u32 disp_int_cont6;
728};
729
6f34be50
AD		 730union radeon_irq_stat_regs {
731 struct r500_irq_stat_regs r500;
732 struct r600_irq_stat_regs r600;
733 struct evergreen_irq_stat_regs evergreen;
a59781bb 734 struct cik_irq_stat_regs cik;
6f34be50
AD		 735};
736
54bd5206
IH		 737#define RADEON_MAX_HPD_PINS 6
738#define RADEON_MAX_CRTCS 6
b530602f 739#define RADEON_MAX_AFMT_BLOCKS 7
54bd5206 740
771fe6b9 741struct radeon_irq {
fb98257a
CK		 742 bool installed;
743 spinlock_t lock;
736fc37f 744 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 745 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 746 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 747 wait_queue_head_t vblank_queue;
748 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 749 bool afmt[RADEON_MAX_AFMT_BLOCKS];
750 union radeon_irq_stat_regs stat_regs;
4a6369e9 751 bool dpm_thermal;
771fe6b9
JG		 752};
753
754int radeon_irq_kms_init(struct radeon_device *rdev);
755void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b
AD		 756void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
757void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 758void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
759void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 760void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
761void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
762void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
763void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 764
765/*
e32eb50d 766 * CP & rings.
771fe6b9 767 */
7465280c 768
771fe6b9 769struct radeon_ib {
68470ae7
JG		 770 struct radeon_sa_bo *sa_bo;
771 uint32_t length_dw;
772 uint64_t gpu_addr;
773 uint32_t *ptr;
876dc9f3 774 int ring;
68470ae7 775 struct radeon_fence *fence;
4bf3dd92 776 struct radeon_vm *vm;
68470ae7
JG		 777 bool is_const_ib;
778 struct radeon_semaphore *semaphore;
771fe6b9
JG		 779};
780
e32eb50d 781struct radeon_ring {
4c788679 782 struct radeon_bo *ring_obj;
771fe6b9
JG		 783 volatile uint32_t *ring;
784 unsigned rptr;
5596a9db
CK		 785 unsigned rptr_offs;
786 unsigned rptr_reg;
45df6803 787 unsigned rptr_save_reg;
89d35807
AD		 788 u64 next_rptr_gpu_addr;
789 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 790 unsigned wptr;
791 unsigned wptr_old;
5596a9db 792 unsigned wptr_reg;
771fe6b9
JG		 793 unsigned ring_size;
794 unsigned ring_free_dw;
795 int count_dw;
069211e5
CK		 796 unsigned long last_activity;
797 unsigned last_rptr;
771fe6b9
JG		 798 uint64_t gpu_addr;
799 uint32_t align_mask;
800 uint32_t ptr_mask;
771fe6b9 801 bool ready;
78c5560a 802 u32 nop;
8b25ed34 803 u32 idx;
5f0839c1
JG		 804 u64 last_semaphore_signal_addr;
805 u64 last_semaphore_wait_addr;
963e81f9
AD		 806 /* for CIK queues */
807 u32 me;
808 u32 pipe;
809 u32 queue;
810 struct radeon_bo *mqd_obj;
d5754ab8 811 u32 doorbell_index;
963e81f9
AD		 812 unsigned wptr_offs;
813};
814
815struct radeon_mec {
816 struct radeon_bo *hpd_eop_obj;
817 u64 hpd_eop_gpu_addr;
818 u32 num_pipe;
819 u32 num_mec;
820 u32 num_queue;
771fe6b9
JG		 821};
822
721604a1
JG		 823/*
824 * VM
825 */
ee60e29f 826
fa87e62d 827/* maximum number of VMIDs */
ee60e29f
CK		 828#define RADEON_NUM_VM 16
829
fa87e62d
DC		 830/* defines number of bits in page table versus page directory,
831 * a page is 4KB so we have 12 bits offset, 9 bits in the page
832 * table and the remaining 19 bits are in the page directory */
833#define RADEON_VM_BLOCK_SIZE 9
834
835/* number of entries in page table */
836#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
837
1c01103c
AD		 838/* PTBs (Page Table Blocks) need to be aligned to 32K */
839#define RADEON_VM_PTB_ALIGN_SIZE 32768
840#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
841#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
842
24c16439
CK		 843#define R600_PTE_VALID (1 << 0)
844#define R600_PTE_SYSTEM (1 << 1)
845#define R600_PTE_SNOOPED (1 << 2)
846#define R600_PTE_READABLE (1 << 5)
847#define R600_PTE_WRITEABLE (1 << 6)
848
721604a1
JG		 849struct radeon_vm {
850 struct list_head list;
851 struct list_head va;
ee60e29f 852 unsigned id;
90a51a32
CK		 853
854 /* contains the page directory */
855 struct radeon_sa_bo *page_directory;
856 uint64_t pd_gpu_addr;
857
858 /* array of page tables, one for each page directory entry */
859 struct radeon_sa_bo **page_tables;
860
721604a1
JG		 861 struct mutex mutex;
862 /* last fence for cs using this vm */
863 struct radeon_fence *fence;
9b40e5d8
CK		 864 /* last flush or NULL if we still need to flush */
865 struct radeon_fence *last_flush;
721604a1
JG		 866};
867
721604a1 868struct radeon_vm_manager {
36ff39c4 869 struct mutex lock;
721604a1 870 struct list_head lru_vm;
ee60e29f 871 struct radeon_fence *active[RADEON_NUM_VM];
721604a1
JG		 872 struct radeon_sa_manager sa_manager;
873 uint32_t max_pfn;
721604a1
JG		 874 /* number of VMIDs */
875 unsigned nvm;
876 /* vram base address for page table entry */
877 u64 vram_base_offset;
67e915e4
AD		 878 /* is vm enabled? */
879 bool enabled;
721604a1
JG		 880};
881
882/*
883 * file private structure
884 */
885struct radeon_fpriv {
886 struct radeon_vm vm;
887};
888
d8f60cfc
AD		 889/*
890 * R6xx+ IH ring
891 */
892struct r600_ih {
4c788679 893 struct radeon_bo *ring_obj;
d8f60cfc
AD		 894 volatile uint32_t *ring;
895 unsigned rptr;
d8f60cfc
AD		 896 unsigned ring_size;
897 uint64_t gpu_addr;
d8f60cfc 898 uint32_t ptr_mask;
c20dc369 899 atomic_t lock;
d8f60cfc
AD		 900 bool enabled;
901};
902
347e7592 903/*
2948f5e6 904 * RLC stuff
347e7592 905 */
2948f5e6
AD		 906#include "clearstate_defs.h"
907
908struct radeon_rlc {
347e7592
AD		 909 /* for power gating */
910 struct radeon_bo *save_restore_obj;
911 uint64_t save_restore_gpu_addr;
2948f5e6 912 volatile uint32_t *sr_ptr;
1fd11777 913 const u32 *reg_list;
2948f5e6 914 u32 reg_list_size;
347e7592
AD		 915 /* for clear state */
916 struct radeon_bo *clear_state_obj;
917 uint64_t clear_state_gpu_addr;
2948f5e6 918 volatile uint32_t *cs_ptr;
1fd11777 919 const struct cs_section_def *cs_data;
22c775ce
AD		 920 u32 clear_state_size;
921 /* for cp tables */
922 struct radeon_bo *cp_table_obj;
923 uint64_t cp_table_gpu_addr;
924 volatile uint32_t *cp_table_ptr;
925 u32 cp_table_size;
347e7592
AD		 926};
927
69e130a6 928int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 929 struct radeon_ib *ib, struct radeon_vm *vm,
930 unsigned size);
f2e39221 931void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
4ef72566
CK		 932int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
933 struct radeon_ib *const_ib);
771fe6b9
JG		 934int radeon_ib_pool_init(struct radeon_device *rdev);
935void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 936int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 937/* Ring access between begin & end cannot sleep */
89d35807
AD		 938bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
939 struct radeon_ring *ring);
e32eb50d
CK		 940void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
941int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
942int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
943void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
944void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
d6999bc7 945void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 946void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
947int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
7b9ef16b 948void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
069211e5
CK		 949void radeon_ring_lockup_update(struct radeon_ring *ring);
950bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 951unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
952 uint32_t **data);
953int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
954 unsigned size, uint32_t *data);
e32eb50d 955int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
2e1e6dad 956 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, u32 nop);
e32eb50d 957void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 958
959
4d75658b
AD		 960/* r600 async dma */
961void r600_dma_stop(struct radeon_device *rdev);
962int r600_dma_resume(struct radeon_device *rdev);
963void r600_dma_fini(struct radeon_device *rdev);
964
8c5fd7ef
AD		 965void cayman_dma_stop(struct radeon_device *rdev);
966int cayman_dma_resume(struct radeon_device *rdev);
967void cayman_dma_fini(struct radeon_device *rdev);
968
771fe6b9
JG		 969/*
970 * CS.
971 */
972struct radeon_cs_reloc {
973 struct drm_gem_object *gobj;
4c788679
JG		 974 struct radeon_bo *robj;
975 struct radeon_bo_list lobj;
771fe6b9
JG		 976 uint32_t handle;
977 uint32_t flags;
978};
979
980struct radeon_cs_chunk {
981 uint32_t chunk_id;
982 uint32_t length_dw;
983 uint32_t *kdata;
721604a1 984 void __user *user_ptr;
771fe6b9
JG		 985};
986
987struct radeon_cs_parser {
c8c15ff1 988 struct device *dev;
771fe6b9
JG		 989 struct radeon_device *rdev;
990 struct drm_file *filp;
991 /* chunks */
992 unsigned nchunks;
993 struct radeon_cs_chunk *chunks;
994 uint64_t *chunks_array;
995 /* IB */
996 unsigned idx;
997 /* relocations */
998 unsigned nrelocs;
999 struct radeon_cs_reloc *relocs;
1000 struct radeon_cs_reloc **relocs_ptr;
1001 struct list_head validated;
cf4ccd01 1002 unsigned dma_reloc_idx;
771fe6b9
JG		 1003 /* indices of various chunks */
1004 int chunk_ib_idx;
1005 int chunk_relocs_idx;
721604a1 1006 int chunk_flags_idx;
dfcf5f36 1007 int chunk_const_ib_idx;
f2e39221
JG		 1008 struct radeon_ib ib;
1009 struct radeon_ib const_ib;
771fe6b9 1010 void *track;
3ce0a23d 1011 unsigned family;
e70f224c 1012 int parser_error;
721604a1
JG		 1013 u32 cs_flags;
1014 u32 ring;
1015 s32 priority;
ecff665f 1016 struct ww_acquire_ctx ticket;
771fe6b9
JG		 1017};
1018
28a326c5
ML		 1019static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1020{
1021 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1022
1023 if (ibc->kdata)
1024 return ibc->kdata[idx];
1025 return p->ib.ptr[idx];
1026}
1027
513bcb46 1028
771fe6b9
JG		 1029struct radeon_cs_packet {
1030 unsigned idx;
1031 unsigned type;
1032 unsigned reg;
1033 unsigned opcode;
1034 int count;
1035 unsigned one_reg_wr;
1036};
1037
1038typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1039 struct radeon_cs_packet *pkt,
1040 unsigned idx, unsigned reg);
1041typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1042 struct radeon_cs_packet *pkt);
1043
1044
1045/*
1046 * AGP
1047 */
1048int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1049void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1050void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1051void radeon_agp_fini(struct radeon_device *rdev);
1052
1053
1054/*
1055 * Writeback
1056 */
1057struct radeon_wb {
4c788679 1058 struct radeon_bo *wb_obj;
771fe6b9
JG		 1059 volatile uint32_t *wb;
1060 uint64_t gpu_addr;
724c80e1 1061 bool enabled;
d0f8a854 1062 bool use_event;
771fe6b9
JG		 1063};
1064
724c80e1 1065#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1066#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1067#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1068#define RADEON_WB_CP1_RPTR_OFFSET 1280
1069#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1070#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1071#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1072#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1073#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1074#define CIK_WB_CP1_WPTR_OFFSET 3328
1075#define CIK_WB_CP2_WPTR_OFFSET 3584
724c80e1 1076
c93bb85b
JG		 1077/**
1078 * struct radeon_pm - power management datas
1079 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1080 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1081 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1082 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1083 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1084 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1085 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1086 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1087 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1088 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1089 * @needed_bandwidth: current bandwidth needs
1090 *
1091 * It keeps track of various data needed to take powermanagement decision.
25985edc 1092 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1093 * Equation between gpu/memory clock and available bandwidth is hw dependent
1094 * (type of memory, bus size, efficiency, ...)
1095 */
ce8f5370
AD		 1096
1097enum radeon_pm_method {
1098 PM_METHOD_PROFILE,
1099 PM_METHOD_DYNPM,
da321c8a 1100 PM_METHOD_DPM,
ce8f5370
AD		 1101};
1102
1103enum radeon_dynpm_state {
1104 DYNPM_STATE_DISABLED,
1105 DYNPM_STATE_MINIMUM,
1106 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1107 DYNPM_STATE_ACTIVE,
1108 DYNPM_STATE_SUSPENDED,
c913e23a 1109};
ce8f5370
AD		 1110enum radeon_dynpm_action {
1111 DYNPM_ACTION_NONE,
1112 DYNPM_ACTION_MINIMUM,
1113 DYNPM_ACTION_DOWNCLOCK,
1114 DYNPM_ACTION_UPCLOCK,
1115 DYNPM_ACTION_DEFAULT
c913e23a 1116};
56278a8e
AD		 1117
1118enum radeon_voltage_type {
1119 VOLTAGE_NONE = 0,
1120 VOLTAGE_GPIO,
1121 VOLTAGE_VDDC,
1122 VOLTAGE_SW
1123};
1124
0ec0e74f 1125enum radeon_pm_state_type {
da321c8a 1126 /* not used for dpm */
0ec0e74f
AD		 1127 POWER_STATE_TYPE_DEFAULT,
1128 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1129 /* user selectable states */
0ec0e74f
AD		 1130 POWER_STATE_TYPE_BATTERY,
1131 POWER_STATE_TYPE_BALANCED,
1132 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1133 /* internal states */
1134 POWER_STATE_TYPE_INTERNAL_UVD,
1135 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1136 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1137 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1138 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1139 POWER_STATE_TYPE_INTERNAL_BOOT,
1140 POWER_STATE_TYPE_INTERNAL_THERMAL,
1141 POWER_STATE_TYPE_INTERNAL_ACPI,
1142 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1143 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1144};
1145
ce8f5370
AD		 1146enum radeon_pm_profile_type {
1147 PM_PROFILE_DEFAULT,
1148 PM_PROFILE_AUTO,
1149 PM_PROFILE_LOW,
c9e75b21 1150 PM_PROFILE_MID,
ce8f5370
AD		 1151 PM_PROFILE_HIGH,
1152};
1153
1154#define PM_PROFILE_DEFAULT_IDX 0
1155#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1156#define PM_PROFILE_MID_SH_IDX 2
1157#define PM_PROFILE_HIGH_SH_IDX 3
1158#define PM_PROFILE_LOW_MH_IDX 4
1159#define PM_PROFILE_MID_MH_IDX 5
1160#define PM_PROFILE_HIGH_MH_IDX 6
1161#define PM_PROFILE_MAX 7
ce8f5370
AD		 1162
1163struct radeon_pm_profile {
1164 int dpms_off_ps_idx;
1165 int dpms_on_ps_idx;
1166 int dpms_off_cm_idx;
1167 int dpms_on_cm_idx;
516d0e46
AD		 1168};
1169
21a8122a
AD		 1170enum radeon_int_thermal_type {
1171 THERMAL_TYPE_NONE,
da321c8a
AD		 1172 THERMAL_TYPE_EXTERNAL,
1173 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1174 THERMAL_TYPE_RV6XX,
1175 THERMAL_TYPE_RV770,
da321c8a 1176 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1177 THERMAL_TYPE_EVERGREEN,
e33df25f 1178 THERMAL_TYPE_SUMO,
4fddba1f 1179 THERMAL_TYPE_NI,
14607d08 1180 THERMAL_TYPE_SI,
da321c8a 1181 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1182 THERMAL_TYPE_CI,
16fbe00d 1183 THERMAL_TYPE_KV,
21a8122a
AD		 1184};
1185
56278a8e
AD		 1186struct radeon_voltage {
1187 enum radeon_voltage_type type;
1188 /* gpio voltage */
1189 struct radeon_gpio_rec gpio;
1190 u32 delay; /* delay in usec from voltage drop to sclk change */
1191 bool active_high; /* voltage drop is active when bit is high */
1192 /* VDDC voltage */
1193 u8 vddc_id; /* index into vddc voltage table */
1194 u8 vddci_id; /* index into vddci voltage table */
1195 bool vddci_enabled;
1196 /* r6xx+ sw */
2feea49a
AD		 1197 u16 voltage;
1198 /* evergreen+ vddci */
1199 u16 vddci;
56278a8e
AD		 1200};
1201
d7311171
AD		 1202/* clock mode flags */
1203#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1204
56278a8e
AD		 1205struct radeon_pm_clock_info {
1206 /* memory clock */
1207 u32 mclk;
1208 /* engine clock */
1209 u32 sclk;
1210 /* voltage info */
1211 struct radeon_voltage voltage;
d7311171 1212 /* standardized clock flags */
56278a8e
AD		 1213 u32 flags;
1214};
1215
a48b9b4e 1216/* state flags */
d7311171 1217#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1218
56278a8e 1219struct radeon_power_state {
0ec0e74f 1220 enum radeon_pm_state_type type;
8f3f1c9a 1221 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1222 /* number of valid clock modes in this power state */
1223 int num_clock_modes;
56278a8e 1224 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1225 /* standardized state flags */
1226 u32 flags;
79daedc9
AD		 1227 u32 misc; /* vbios specific flags */
1228 u32 misc2; /* vbios specific flags */
1229 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1230};
1231
27459324
RM		 1232/*
1233 * Some modes are overclocked by very low value, accept them
1234 */
1235#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1236
2e9d4c05
AD		 1237enum radeon_dpm_auto_throttle_src {
1238 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1239 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1240};
1241
1242enum radeon_dpm_event_src {
1243 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1244 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1245 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1246 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1247 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1248};
1249
da321c8a
AD		 1250struct radeon_ps {
1251 u32 caps; /* vbios flags */
1252 u32 class; /* vbios flags */
1253 u32 class2; /* vbios flags */
1254 /* UVD clocks */
1255 u32 vclk;
1256 u32 dclk;
c4453e66
AD		 1257 /* VCE clocks */
1258 u32 evclk;
1259 u32 ecclk;
da321c8a
AD		 1260 /* asic priv */
1261 void *ps_priv;
1262};
1263
1264struct radeon_dpm_thermal {
1265 /* thermal interrupt work */
1266 struct work_struct work;
1267 /* low temperature threshold */
1268 int min_temp;
1269 /* high temperature threshold */
1270 int max_temp;
1271 /* was interrupt low to high or high to low */
1272 bool high_to_low;
1273};
1274
d22b7e40
AD		 1275enum radeon_clk_action
1276{
1277 RADEON_SCLK_UP = 1,
1278 RADEON_SCLK_DOWN
1279};
1280
1281struct radeon_blacklist_clocks
1282{
1283 u32 sclk;
1284 u32 mclk;
1285 enum radeon_clk_action action;
1286};
1287
61b7d601
AD		 1288struct radeon_clock_and_voltage_limits {
1289 u32 sclk;
1290 u32 mclk;
cdf6e805
AD		 1291 u16 vddc;
1292 u16 vddci;
61b7d601
AD		 1293};
1294
1295struct radeon_clock_array {
1296 u32 count;
1297 u32 *values;
1298};
1299
1300struct radeon_clock_voltage_dependency_entry {
1301 u32 clk;
1302 u16 v;
1303};
1304
1305struct radeon_clock_voltage_dependency_table {
1306 u32 count;
1307 struct radeon_clock_voltage_dependency_entry *entries;
1308};
1309
ef976ec4
AD		 1310union radeon_cac_leakage_entry {
1311 struct {
1312 u16 vddc;
1313 u32 leakage;
1314 };
1315 struct {
1316 u16 vddc1;
1317 u16 vddc2;
1318 u16 vddc3;
1319 };
61b7d601
AD		 1320};
1321
1322struct radeon_cac_leakage_table {
1323 u32 count;
ef976ec4 1324 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1325};
1326
929ee7a8
AD		 1327struct radeon_phase_shedding_limits_entry {
1328 u16 voltage;
1329 u32 sclk;
1330 u32 mclk;
1331};
1332
1333struct radeon_phase_shedding_limits_table {
1334 u32 count;
1335 struct radeon_phase_shedding_limits_entry *entries;
1336};
1337
84a9d9ee
AD		 1338struct radeon_uvd_clock_voltage_dependency_entry {
1339 u32 vclk;
1340 u32 dclk;
1341 u16 v;
1342};
1343
1344struct radeon_uvd_clock_voltage_dependency_table {
1345 u8 count;
1346 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1347};
1348
d29f013b
AD		 1349struct radeon_vce_clock_voltage_dependency_entry {
1350 u32 ecclk;
1351 u32 evclk;
1352 u16 v;
1353};
1354
1355struct radeon_vce_clock_voltage_dependency_table {
1356 u8 count;
1357 struct radeon_vce_clock_voltage_dependency_entry *entries;
1358};
1359
a5cb318e
AD		 1360struct radeon_ppm_table {
1361 u8 ppm_design;
1362 u16 cpu_core_number;
1363 u32 platform_tdp;
1364 u32 small_ac_platform_tdp;
1365 u32 platform_tdc;
1366 u32 small_ac_platform_tdc;
1367 u32 apu_tdp;
1368 u32 dgpu_tdp;
1369 u32 dgpu_ulv_power;
1370 u32 tj_max;
1371};
1372
58cb7632
AD		 1373struct radeon_cac_tdp_table {
1374 u16 tdp;
1375 u16 configurable_tdp;
1376 u16 tdc;
1377 u16 battery_power_limit;
1378 u16 small_power_limit;
1379 u16 low_cac_leakage;
1380 u16 high_cac_leakage;
1381 u16 maximum_power_delivery_limit;
1382};
1383
61b7d601
AD		 1384struct radeon_dpm_dynamic_state {
1385 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1386 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1387 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1388 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1389 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1390 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1391 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1392 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1393 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1394 struct radeon_clock_array valid_sclk_values;
1395 struct radeon_clock_array valid_mclk_values;
1396 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1397 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1398 u32 mclk_sclk_ratio;
1399 u32 sclk_mclk_delta;
1400 u16 vddc_vddci_delta;
1401 u16 min_vddc_for_pcie_gen2;
1402 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1403 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1404 struct radeon_ppm_table *ppm_table;
58cb7632 1405 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1406};
1407
1408struct radeon_dpm_fan {
1409 u16 t_min;
1410 u16 t_med;
1411 u16 t_high;
1412 u16 pwm_min;
1413 u16 pwm_med;
1414 u16 pwm_high;
1415 u8 t_hyst;
1416 u32 cycle_delay;
1417 u16 t_max;
1418 bool ucode_fan_control;
1419};
1420
32ce4652
AD		 1421enum radeon_pcie_gen {
1422 RADEON_PCIE_GEN1 = 0,
1423 RADEON_PCIE_GEN2 = 1,
1424 RADEON_PCIE_GEN3 = 2,
1425 RADEON_PCIE_GEN_INVALID = 0xffff
1426};
1427
70d01a5e
AD		 1428enum radeon_dpm_forced_level {
1429 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1430 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1431 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1432};
1433
da321c8a
AD		 1434struct radeon_dpm {
1435 struct radeon_ps *ps;
1436 /* number of valid power states */
1437 int num_ps;
1438 /* current power state that is active */
1439 struct radeon_ps *current_ps;
1440 /* requested power state */
1441 struct radeon_ps *requested_ps;
1442 /* boot up power state */
1443 struct radeon_ps *boot_ps;
1444 /* default uvd power state */
1445 struct radeon_ps *uvd_ps;
1446 enum radeon_pm_state_type state;
1447 enum radeon_pm_state_type user_state;
1448 u32 platform_caps;
1449 u32 voltage_response_time;
1450 u32 backbias_response_time;
1451 void *priv;
1452 u32 new_active_crtcs;
1453 int new_active_crtc_count;
1454 u32 current_active_crtcs;
1455 int current_active_crtc_count;
61b7d601
AD		 1456 struct radeon_dpm_dynamic_state dyn_state;
1457 struct radeon_dpm_fan fan;
1458 u32 tdp_limit;
1459 u32 near_tdp_limit;
a9e61410 1460 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1461 u32 sq_ramping_threshold;
1462 u32 cac_leakage;
1463 u16 tdp_od_limit;
1464 u32 tdp_adjustment;
1465 u16 load_line_slope;
1466 bool power_control;
5ca302f7 1467 bool ac_power;
da321c8a
AD		 1468 /* special states active */
1469 bool thermal_active;
8a227555 1470 bool uvd_active;
da321c8a
AD		 1471 /* thermal handling */
1472 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1473 /* forced levels */
1474 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1475 /* track UVD streams */
1476 unsigned sd;
1477 unsigned hd;
da321c8a
AD		 1478};
1479
ce3537d5 1480void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
da321c8a 1481
c93bb85b 1482struct radeon_pm {
c913e23a 1483 struct mutex mutex;
db7fce39
CK		 1484 /* write locked while reprogramming mclk */
1485 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1486 u32 active_crtcs;
1487 int active_crtc_count;
c913e23a 1488 int req_vblank;
839461d3 1489 bool vblank_sync;
c93bb85b
JG		 1490 fixed20_12 max_bandwidth;
1491 fixed20_12 igp_sideport_mclk;
1492 fixed20_12 igp_system_mclk;
1493 fixed20_12 igp_ht_link_clk;
1494 fixed20_12 igp_ht_link_width;
1495 fixed20_12 k8_bandwidth;
1496 fixed20_12 sideport_bandwidth;
1497 fixed20_12 ht_bandwidth;
1498 fixed20_12 core_bandwidth;
1499 fixed20_12 sclk;
f47299c5 1500 fixed20_12 mclk;
c93bb85b 1501 fixed20_12 needed_bandwidth;
0975b162 1502 struct radeon_power_state *power_state;
56278a8e
AD		 1503 /* number of valid power states */
1504 int num_power_states;
a48b9b4e
AD		 1505 int current_power_state_index;
1506 int current_clock_mode_index;
1507 int requested_power_state_index;
1508 int requested_clock_mode_index;
1509 int default_power_state_index;
1510 u32 current_sclk;
1511 u32 current_mclk;
2feea49a
AD		 1512 u16 current_vddc;
1513 u16 current_vddci;
9ace9f7b
AD		 1514 u32 default_sclk;
1515 u32 default_mclk;
2feea49a
AD		 1516 u16 default_vddc;
1517 u16 default_vddci;
29fb52ca 1518 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1519 /* selected pm method */
1520 enum radeon_pm_method pm_method;
1521 /* dynpm power management */
1522 struct delayed_work dynpm_idle_work;
1523 enum radeon_dynpm_state dynpm_state;
1524 enum radeon_dynpm_action dynpm_planned_action;
1525 unsigned long dynpm_action_timeout;
1526 bool dynpm_can_upclock;
1527 bool dynpm_can_downclock;
1528 /* profile-based power management */
1529 enum radeon_pm_profile_type profile;
1530 int profile_index;
1531 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1532 /* internal thermal controller on rv6xx+ */
1533 enum radeon_int_thermal_type int_thermal_type;
1534 struct device *int_hwmon_dev;
da321c8a
AD		 1535 /* dpm */
1536 bool dpm_enabled;
1537 struct radeon_dpm dpm;
c93bb85b
JG		 1538};
1539
a4c9e2ee
AD		 1540int radeon_pm_get_type_index(struct radeon_device *rdev,
1541 enum radeon_pm_state_type ps_type,
1542 int instance);
f2ba57b5
CK		 1543/*
1544 * UVD
1545 */
1546#define RADEON_MAX_UVD_HANDLES 10
1547#define RADEON_UVD_STACK_SIZE (1024*1024)
1548#define RADEON_UVD_HEAP_SIZE (1024*1024)
1549
1550struct radeon_uvd {
1551 struct radeon_bo *vcpu_bo;
1552 void *cpu_addr;
1553 uint64_t gpu_addr;
9cc2e0e9 1554 void *saved_bo;
f2ba57b5
CK		 1555 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1556 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1557 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1558 struct delayed_work idle_work;
f2ba57b5
CK		 1559};
1560
1561int radeon_uvd_init(struct radeon_device *rdev);
1562void radeon_uvd_fini(struct radeon_device *rdev);
1563int radeon_uvd_suspend(struct radeon_device *rdev);
1564int radeon_uvd_resume(struct radeon_device *rdev);
1565int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1566 uint32_t handle, struct radeon_fence **fence);
1567int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1568 uint32_t handle, struct radeon_fence **fence);
1569void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1570void radeon_uvd_free_handles(struct radeon_device *rdev,
1571 struct drm_file *filp);
1572int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1573void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1574int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1575 unsigned vclk, unsigned dclk,
1576 unsigned vco_min, unsigned vco_max,
1577 unsigned fb_factor, unsigned fb_mask,
1578 unsigned pd_min, unsigned pd_max,
1579 unsigned pd_even,
1580 unsigned *optimal_fb_div,
1581 unsigned *optimal_vclk_div,
1582 unsigned *optimal_dclk_div);
1583int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1584 unsigned cg_upll_func_cntl);
771fe6b9 1585
b530602f 1586struct r600_audio_pin {
a92553ab
RM		 1587 int channels;
1588 int rate;
1589 int bits_per_sample;
1590 u8 status_bits;
1591 u8 category_code;
b530602f
AD		 1592 u32 offset;
1593 bool connected;
1594 u32 id;
1595};
1596
1597struct r600_audio {
1598 bool enabled;
1599 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1600 int num_pins;
a92553ab
RM		 1601};
1602
771fe6b9
JG		 1603/*
1604 * Benchmarking
1605 */
638dd7db 1606void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1607
1608
ecc0b326
MD		 1609/*
1610 * Testing
1611 */
1612void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1613void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1614 struct radeon_ring *cpA,
1615 struct radeon_ring *cpB);
60a7e396 1616void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326
MD		 1617
1618
771fe6b9
JG		 1619/*
1620 * Debugfs
1621 */
4d8bf9ae
CK		 1622struct radeon_debugfs {
1623 struct drm_info_list *files;
1624 unsigned num_files;
1625};
1626
771fe6b9
JG		 1627int radeon_debugfs_add_files(struct radeon_device *rdev,
1628 struct drm_info_list *files,
1629 unsigned nfiles);
1630int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1631
76a0df85
CK		 1632/*
1633 * ASIC ring specific functions.
1634 */
1635struct radeon_asic_ring {
1636 /* ring read/write ptr handling */
1637 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1638 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1639 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1640
1641 /* validating and patching of IBs */
1642 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1643 int (*cs_parse)(struct radeon_cs_parser *p);
1644
1645 /* command emmit functions */
1646 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1647 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1654b817 1648 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
76a0df85
CK		 1649 struct radeon_semaphore *semaphore, bool emit_wait);
1650 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1651
1652 /* testing functions */
1653 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1654 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1655 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1656
1657 /* deprecated */
1658 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1659};
771fe6b9
JG		 1660
1661/*
1662 * ASIC specific functions.
1663 */
1664struct radeon_asic {
068a117c 1665 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1666 void (*fini)(struct radeon_device *rdev);
1667 int (*resume)(struct radeon_device *rdev);
1668 int (*suspend)(struct radeon_device *rdev);
28d52043 1669 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1670 int (*asic_reset)(struct radeon_device *rdev);
54e88e06
AD		 1671 /* ioctl hw specific callback. Some hw might want to perform special
1672 * operation on specific ioctl. For instance on wait idle some hw
1673 * might want to perform and HDP flush through MMIO as it seems that
1674 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1675 * through ring.
1676 */
1677 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1678 /* check if 3D engine is idle */
1679 bool (*gui_idle)(struct radeon_device *rdev);
1680 /* wait for mc_idle */
1681 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1682 /* get the reference clock */
1683 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1684 /* get the gpu clock counter */
1685 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1686 /* gart */
c5b3b850
AD		 1687 struct {
1688 void (*tlb_flush)(struct radeon_device *rdev);
1689 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1690 } gart;
05b07147
CK		 1691 struct {
1692 int (*init)(struct radeon_device *rdev);
1693 void (*fini)(struct radeon_device *rdev);
43f1214a
AD		 1694 void (*set_page)(struct radeon_device *rdev,
1695 struct radeon_ib *ib,
1696 uint64_t pe,
dce34bfd
CK		 1697 uint64_t addr, unsigned count,
1698 uint32_t incr, uint32_t flags);
05b07147 1699 } vm;
54e88e06 1700 /* ring specific callbacks */
76a0df85 1701 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1702 /* irqs */
b35ea4ab
AD		 1703 struct {
1704 int (*set)(struct radeon_device *rdev);
1705 int (*process)(struct radeon_device *rdev);
1706 } irq;
54e88e06 1707 /* displays */
c79a49ca
AD		 1708 struct {
1709 /* display watermarks */
1710 void (*bandwidth_update)(struct radeon_device *rdev);
1711 /* get frame count */
1712 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1713 /* wait for vblank */
1714 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1715 /* set backlight level */
1716 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1717 /* get backlight level */
1718 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1719 /* audio callbacks */
1720 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1721 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1722 } display;
54e88e06 1723 /* copy functions for bo handling */
27cd7769
AD		 1724 struct {
1725 int (*blit)(struct radeon_device *rdev,
1726 uint64_t src_offset,
1727 uint64_t dst_offset,
1728 unsigned num_gpu_pages,
876dc9f3 1729 struct radeon_fence **fence);
27cd7769
AD		 1730 u32 blit_ring_index;
1731 int (*dma)(struct radeon_device *rdev,
1732 uint64_t src_offset,
1733 uint64_t dst_offset,
1734 unsigned num_gpu_pages,
876dc9f3 1735 struct radeon_fence **fence);
27cd7769
AD		 1736 u32 dma_ring_index;
1737 /* method used for bo copy */
1738 int (*copy)(struct radeon_device *rdev,
1739 uint64_t src_offset,
1740 uint64_t dst_offset,
1741 unsigned num_gpu_pages,
876dc9f3 1742 struct radeon_fence **fence);
27cd7769
AD		 1743 /* ring used for bo copies */
1744 u32 copy_ring_index;
1745 } copy;
54e88e06 1746 /* surfaces */
9e6f3d02
AD		 1747 struct {
1748 int (*set_reg)(struct radeon_device *rdev, int reg,
1749 uint32_t tiling_flags, uint32_t pitch,
1750 uint32_t offset, uint32_t obj_size);
1751 void (*clear_reg)(struct radeon_device *rdev, int reg);
1752 } surface;
54e88e06 1753 /* hotplug detect */
901ea57d
AD		 1754 struct {
1755 void (*init)(struct radeon_device *rdev);
1756 void (*fini)(struct radeon_device *rdev);
1757 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1758 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1759 } hpd;
da321c8a 1760 /* static power management */
a02fa397
AD		 1761 struct {
1762 void (*misc)(struct radeon_device *rdev);
1763 void (*prepare)(struct radeon_device *rdev);
1764 void (*finish)(struct radeon_device *rdev);
1765 void (*init_profile)(struct radeon_device *rdev);
1766 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1767 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1768 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1769 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1770 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1771 int (*get_pcie_lanes)(struct radeon_device *rdev);
1772 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1773 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1774 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
6bd1c385 1775 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1776 } pm;
da321c8a
AD		 1777 /* dynamic power management */
1778 struct {
1779 int (*init)(struct radeon_device *rdev);
1780 void (*setup_asic)(struct radeon_device *rdev);
1781 int (*enable)(struct radeon_device *rdev);
1782 void (*disable)(struct radeon_device *rdev);
84dd1928 1783 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1784 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1785 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1786 void (*display_configuration_changed)(struct radeon_device *rdev);
1787 void (*fini)(struct radeon_device *rdev);
1788 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1789 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1790 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1791 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1792 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1793 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1794 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1c71bda0 1795 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
da321c8a 1796 } dpm;
6f34be50 1797 /* pageflipping */
0f9e006c
AD		 1798 struct {
1799 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1800 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1801 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1802 } pflip;
771fe6b9
JG		 1803};
1804
21f9a437
JG		 1805/*
1806 * Asic structures
1807 */
551ebd83 1808struct r100_asic {
225758d8
JG		 1809 const unsigned *reg_safe_bm;
1810 unsigned reg_safe_bm_size;
1811 u32 hdp_cntl;
551ebd83
DA		 1812};
1813
21f9a437 1814struct r300_asic {
225758d8
JG		 1815 const unsigned *reg_safe_bm;
1816 unsigned reg_safe_bm_size;
1817 u32 resync_scratch;
1818 u32 hdp_cntl;
21f9a437
JG		 1819};
1820
1821struct r600_asic {
225758d8
JG		 1822 unsigned max_pipes;
1823 unsigned max_tile_pipes;
1824 unsigned max_simds;
1825 unsigned max_backends;
1826 unsigned max_gprs;
1827 unsigned max_threads;
1828 unsigned max_stack_entries;
1829 unsigned max_hw_contexts;
1830 unsigned max_gs_threads;
1831 unsigned sx_max_export_size;
1832 unsigned sx_max_export_pos_size;
1833 unsigned sx_max_export_smx_size;
1834 unsigned sq_num_cf_insts;
1835 unsigned tiling_nbanks;
1836 unsigned tiling_npipes;
1837 unsigned tiling_group_size;
e7aeeba6 1838 unsigned tile_config;
e55b9422 1839 unsigned backend_map;
21f9a437
JG		 1840};
1841
1842struct rv770_asic {
225758d8
JG		 1843 unsigned max_pipes;
1844 unsigned max_tile_pipes;
1845 unsigned max_simds;
1846 unsigned max_backends;
1847 unsigned max_gprs;
1848 unsigned max_threads;
1849 unsigned max_stack_entries;
1850 unsigned max_hw_contexts;
1851 unsigned max_gs_threads;
1852 unsigned sx_max_export_size;
1853 unsigned sx_max_export_pos_size;
1854 unsigned sx_max_export_smx_size;
1855 unsigned sq_num_cf_insts;
1856 unsigned sx_num_of_sets;
1857 unsigned sc_prim_fifo_size;
1858 unsigned sc_hiz_tile_fifo_size;
1859 unsigned sc_earlyz_tile_fifo_fize;
1860 unsigned tiling_nbanks;
1861 unsigned tiling_npipes;
1862 unsigned tiling_group_size;
e7aeeba6 1863 unsigned tile_config;
e55b9422 1864 unsigned backend_map;
21f9a437
JG		 1865};
1866
32fcdbf4
AD		 1867struct evergreen_asic {
1868 unsigned num_ses;
1869 unsigned max_pipes;
1870 unsigned max_tile_pipes;
1871 unsigned max_simds;
1872 unsigned max_backends;
1873 unsigned max_gprs;
1874 unsigned max_threads;
1875 unsigned max_stack_entries;
1876 unsigned max_hw_contexts;
1877 unsigned max_gs_threads;
1878 unsigned sx_max_export_size;
1879 unsigned sx_max_export_pos_size;
1880 unsigned sx_max_export_smx_size;
1881 unsigned sq_num_cf_insts;
1882 unsigned sx_num_of_sets;
1883 unsigned sc_prim_fifo_size;
1884 unsigned sc_hiz_tile_fifo_size;
1885 unsigned sc_earlyz_tile_fifo_size;
1886 unsigned tiling_nbanks;
1887 unsigned tiling_npipes;
1888 unsigned tiling_group_size;
e7aeeba6 1889 unsigned tile_config;
e55b9422 1890 unsigned backend_map;
32fcdbf4
AD		 1891};
1892
fecf1d07
AD		 1893struct cayman_asic {
1894 unsigned max_shader_engines;
1895 unsigned max_pipes_per_simd;
1896 unsigned max_tile_pipes;
1897 unsigned max_simds_per_se;
1898 unsigned max_backends_per_se;
1899 unsigned max_texture_channel_caches;
1900 unsigned max_gprs;
1901 unsigned max_threads;
1902 unsigned max_gs_threads;
1903 unsigned max_stack_entries;
1904 unsigned sx_num_of_sets;
1905 unsigned sx_max_export_size;
1906 unsigned sx_max_export_pos_size;
1907 unsigned sx_max_export_smx_size;
1908 unsigned max_hw_contexts;
1909 unsigned sq_num_cf_insts;
1910 unsigned sc_prim_fifo_size;
1911 unsigned sc_hiz_tile_fifo_size;
1912 unsigned sc_earlyz_tile_fifo_size;
1913
1914 unsigned num_shader_engines;
1915 unsigned num_shader_pipes_per_simd;
1916 unsigned num_tile_pipes;
1917 unsigned num_simds_per_se;
1918 unsigned num_backends_per_se;
1919 unsigned backend_disable_mask_per_asic;
1920 unsigned backend_map;
1921 unsigned num_texture_channel_caches;
1922 unsigned mem_max_burst_length_bytes;
1923 unsigned mem_row_size_in_kb;
1924 unsigned shader_engine_tile_size;
1925 unsigned num_gpus;
1926 unsigned multi_gpu_tile_size;
1927
1928 unsigned tile_config;
fecf1d07
AD		 1929};
1930
0a96d72b
AD		 1931struct si_asic {
1932 unsigned max_shader_engines;
0a96d72b 1933 unsigned max_tile_pipes;
1a8ca750
AD		 1934 unsigned max_cu_per_sh;
1935 unsigned max_sh_per_se;
0a96d72b
AD		 1936 unsigned max_backends_per_se;
1937 unsigned max_texture_channel_caches;
1938 unsigned max_gprs;
1939 unsigned max_gs_threads;
1940 unsigned max_hw_contexts;
1941 unsigned sc_prim_fifo_size_frontend;
1942 unsigned sc_prim_fifo_size_backend;
1943 unsigned sc_hiz_tile_fifo_size;
1944 unsigned sc_earlyz_tile_fifo_size;
1945
0a96d72b
AD		 1946 unsigned num_tile_pipes;
1947 unsigned num_backends_per_se;
1948 unsigned backend_disable_mask_per_asic;
1949 unsigned backend_map;
1950 unsigned num_texture_channel_caches;
1951 unsigned mem_max_burst_length_bytes;
1952 unsigned mem_row_size_in_kb;
1953 unsigned shader_engine_tile_size;
1954 unsigned num_gpus;
1955 unsigned multi_gpu_tile_size;
1956
1957 unsigned tile_config;
64d7b8be 1958 uint32_t tile_mode_array[32];
0a96d72b
AD		 1959};
1960
8cc1a532
AD		 1961struct cik_asic {
1962 unsigned max_shader_engines;
1963 unsigned max_tile_pipes;
1964 unsigned max_cu_per_sh;
1965 unsigned max_sh_per_se;
1966 unsigned max_backends_per_se;
1967 unsigned max_texture_channel_caches;
1968 unsigned max_gprs;
1969 unsigned max_gs_threads;
1970 unsigned max_hw_contexts;
1971 unsigned sc_prim_fifo_size_frontend;
1972 unsigned sc_prim_fifo_size_backend;
1973 unsigned sc_hiz_tile_fifo_size;
1974 unsigned sc_earlyz_tile_fifo_size;
1975
1976 unsigned num_tile_pipes;
1977 unsigned num_backends_per_se;
1978 unsigned backend_disable_mask_per_asic;
1979 unsigned backend_map;
1980 unsigned num_texture_channel_caches;
1981 unsigned mem_max_burst_length_bytes;
1982 unsigned mem_row_size_in_kb;
1983 unsigned shader_engine_tile_size;
1984 unsigned num_gpus;
1985 unsigned multi_gpu_tile_size;
1986
1987 unsigned tile_config;
39aee490 1988 uint32_t tile_mode_array[32];
32f79a8a 1989 uint32_t macrotile_mode_array[16];
8cc1a532
AD		 1990};
1991
068a117c
JG		 1992union radeon_asic_config {
1993 struct r300_asic r300;
551ebd83 1994 struct r100_asic r100;
3ce0a23d
JG		 1995 struct r600_asic r600;
1996 struct rv770_asic rv770;
32fcdbf4 1997 struct evergreen_asic evergreen;
fecf1d07 1998 struct cayman_asic cayman;
0a96d72b 1999 struct si_asic si;
8cc1a532 2000 struct cik_asic cik;
068a117c
JG		 2001};
2002
0a10c851
DV		 2003/*
2004 * asic initizalization from radeon_asic.c
2005 */
2006void radeon_agp_disable(struct radeon_device *rdev);
2007int radeon_asic_init(struct radeon_device *rdev);
2008
771fe6b9
JG		 2009
2010/*
2011 * IOCTL.
2012 */
2013int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2014 struct drm_file *filp);
2015int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2016 struct drm_file *filp);
2017int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2018 struct drm_file *file_priv);
2019int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2020 struct drm_file *file_priv);
2021int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2022 struct drm_file *file_priv);
2023int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2024 struct drm_file *file_priv);
2025int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2026 struct drm_file *filp);
2027int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2028 struct drm_file *filp);
2029int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2030 struct drm_file *filp);
2031int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2032 struct drm_file *filp);
721604a1
JG		 2033int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2034 struct drm_file *filp);
771fe6b9 2035int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 2036int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2037 struct drm_file *filp);
2038int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2039 struct drm_file *filp);
771fe6b9 2040
16cdf04d
AD		 2041/* VRAM scratch page for HDP bug, default vram page */
2042struct r600_vram_scratch {
87cbf8f2
AD		 2043 struct radeon_bo *robj;
2044 volatile uint32_t *ptr;
16cdf04d 2045 u64 gpu_addr;
87cbf8f2 2046};
771fe6b9 2047
fd64ca8a
LT		 2048/*
2049 * ACPI
2050 */
2051struct radeon_atif_notification_cfg {
2052 bool enabled;
2053 int command_code;
2054};
2055
2056struct radeon_atif_notifications {
2057 bool display_switch;
2058 bool expansion_mode_change;
2059 bool thermal_state;
2060 bool forced_power_state;
2061 bool system_power_state;
2062 bool display_conf_change;
2063 bool px_gfx_switch;
2064 bool brightness_change;
2065 bool dgpu_display_event;
2066};
2067
2068struct radeon_atif_functions {
2069 bool system_params;
2070 bool sbios_requests;
2071 bool select_active_disp;
2072 bool lid_state;
2073 bool get_tv_standard;
2074 bool set_tv_standard;
2075 bool get_panel_expansion_mode;
2076 bool set_panel_expansion_mode;
2077 bool temperature_change;
2078 bool graphics_device_types;
2079};
2080
2081struct radeon_atif {
2082 struct radeon_atif_notifications notifications;
2083 struct radeon_atif_functions functions;
2084 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2085 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2086};
7a1619b9 2087
e3a15920
AD		 2088struct radeon_atcs_functions {
2089 bool get_ext_state;
2090 bool pcie_perf_req;
2091 bool pcie_dev_rdy;
2092 bool pcie_bus_width;
2093};
2094
2095struct radeon_atcs {
2096 struct radeon_atcs_functions functions;
2097};
2098
771fe6b9
JG		 2099/*
2100 * Core structure, functions and helpers.
2101 */
2102typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2103typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2104
2105struct radeon_device {
9f022ddf 2106 struct device *dev;
771fe6b9
JG		 2107 struct drm_device *ddev;
2108 struct pci_dev *pdev;
dee53e7f 2109 struct rw_semaphore exclusive_lock;
771fe6b9 2110 /* ASIC */
068a117c 2111 union radeon_asic_config config;
771fe6b9
JG		 2112 enum radeon_family family;
2113 unsigned long flags;
2114 int usec_timeout;
2115 enum radeon_pll_errata pll_errata;
2116 int num_gb_pipes;
f779b3e5 2117 int num_z_pipes;
771fe6b9
JG		 2118 int disp_priority;
2119 /* BIOS */
2120 uint8_t *bios;
2121 bool is_atom_bios;
2122 uint16_t bios_header_start;
4c788679 2123 struct radeon_bo *stollen_vga_memory;
771fe6b9 2124 /* Register mmio */
4c9bc75c
DA		 2125 resource_size_t rmmio_base;
2126 resource_size_t rmmio_size;
2c385151
DV		 2127 /* protects concurrent MM_INDEX/DATA based register access */
2128 spinlock_t mmio_idx_lock;
fe78118c
AD		 2129 /* protects concurrent SMC based register access */
2130 spinlock_t smc_idx_lock;
0a5b7b0b
AD		 2131 /* protects concurrent PLL register access */
2132 spinlock_t pll_idx_lock;
2133 /* protects concurrent MC register access */
2134 spinlock_t mc_idx_lock;
2135 /* protects concurrent PCIE register access */
2136 spinlock_t pcie_idx_lock;
2137 /* protects concurrent PCIE_PORT register access */
2138 spinlock_t pciep_idx_lock;
2139 /* protects concurrent PIF register access */
2140 spinlock_t pif_idx_lock;
2141 /* protects concurrent CG register access */
2142 spinlock_t cg_idx_lock;
2143 /* protects concurrent UVD register access */
2144 spinlock_t uvd_idx_lock;
2145 /* protects concurrent RCU register access */
2146 spinlock_t rcu_idx_lock;
2147 /* protects concurrent DIDT register access */
2148 spinlock_t didt_idx_lock;
2149 /* protects concurrent ENDPOINT (audio) register access */
2150 spinlock_t end_idx_lock;
a0533fbf 2151 void __iomem *rmmio;
771fe6b9
JG		 2152 radeon_rreg_t mc_rreg;
2153 radeon_wreg_t mc_wreg;
2154 radeon_rreg_t pll_rreg;
2155 radeon_wreg_t pll_wreg;
de1b2898 2156 uint32_t pcie_reg_mask;
771fe6b9
JG		 2157 radeon_rreg_t pciep_rreg;
2158 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2159 /* io port */
2160 void __iomem *rio_mem;
2161 resource_size_t rio_mem_size;
771fe6b9
JG		 2162 struct radeon_clock clock;
2163 struct radeon_mc mc;
2164 struct radeon_gart gart;
2165 struct radeon_mode_info mode_info;
2166 struct radeon_scratch scratch;
75efdee1 2167 struct radeon_doorbell doorbell;
771fe6b9 2168 struct radeon_mman mman;
7465280c 2169 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2170 wait_queue_head_t fence_queue;
d6999bc7 2171 struct mutex ring_lock;
e32eb50d 2172 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2173 bool ib_pool_ready;
2174 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2175 struct radeon_irq irq;
2176 struct radeon_asic *asic;
2177 struct radeon_gem gem;
c93bb85b 2178 struct radeon_pm pm;
f2ba57b5 2179 struct radeon_uvd uvd;
f657c2a7 2180 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2181 struct radeon_wb wb;
3ce0a23d 2182 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2183 bool shutdown;
2184 bool suspend;
ad49f501 2185 bool need_dma32;
733289c2 2186 bool accel_working;
a0a53aa8 2187 bool fastfb_working; /* IGP feature*/
f9eaf9ae 2188 bool needs_reset;
e024e110 2189 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2190 const struct firmware *me_fw; /* all family ME firmware */
2191 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2192 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2193 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2194 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2195 const struct firmware *mec_fw; /* CIK MEC firmware */
21a93e13 2196 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2197 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2198 const struct firmware *uvd_fw; /* UVD firmware */
16cdf04d 2199 struct r600_vram_scratch vram_scratch;
3e5cb98d 2200 int msi_enabled; /* msi enabled */
d8f60cfc 2201 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2202 struct radeon_rlc rlc;
963e81f9 2203 struct radeon_mec mec;
d4877cf2 2204 struct work_struct hotplug_work;
f122c610 2205 struct work_struct audio_work;
8f61b34c 2206 struct work_struct reset_work;
18917b60 2207 int num_crtc; /* number of crtcs */
40bacf16 2208 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
948bee3f 2209 bool has_uvd;
b530602f 2210 struct r600_audio audio; /* audio stuff */
ce8f5370 2211 struct notifier_block acpi_nb;
9eba4a93 2212 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2213 struct drm_file *hyperz_filp;
9eba4a93 2214 struct drm_file *cmask_filp;
f376b94f
AD		 2215 /* i2c buses */
2216 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2217 /* debugfs */
2218 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2219 unsigned debugfs_count;
721604a1
JG		 2220 /* virtual memory */
2221 struct radeon_vm_manager vm_manager;
6759a0a7 2222 struct mutex gpu_clock_mutex;
fd64ca8a
LT		 2223 /* ACPI interface */
2224 struct radeon_atif atif;
e3a15920 2225 struct radeon_atcs atcs;
f61d5b46
AD		 2226 /* srbm instance registers */
2227 struct mutex srbm_mutex;
64d8a728
AD		 2228 /* clock, powergating flags */
2229 u32 cg_flags;
2230 u32 pg_flags;
10ebc0bc
DA		 2231
2232 struct dev_pm_domain vga_pm_domain;
2233 bool have_disp_power_ref;
771fe6b9
JG		 2234};
2235
2236int radeon_device_init(struct radeon_device *rdev,
2237 struct drm_device *ddev,
2238 struct pci_dev *pdev,
2239 uint32_t flags);
2240void radeon_device_fini(struct radeon_device *rdev);
2241int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2242
2ef9bdfe
DV		 2243uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2244 bool always_indirect);
2245void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2246 bool always_indirect);
6fcbef7a
AK		 2247u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2248void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2249
d5754ab8
AL		 2250u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2251void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
75efdee1 2252
4c788679
JG		 2253/*
2254 * Cast helper
2255 */
2256#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 2257
2258/*
2259 * Registers read & write functions.
2260 */
a0533fbf
BH		 2261#define RREG8(reg) readb((rdev->rmmio) + (reg))
2262#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2263#define RREG16(reg) readw((rdev->rmmio) + (reg))
2264#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2265#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2266#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2267#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2268#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2269#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2270#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2271#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2272#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2273#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2274#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2275#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2276#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2277#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2278#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2279#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2280#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2281#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2282#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2283#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2284#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2285#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2286#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2287#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2288#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2289#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2290#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2291#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2292#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2293#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2294#define WREG32_P(reg, val, mask) \
2295 do { \
2296 uint32_t tmp_ = RREG32(reg); \
2297 tmp_ &= (mask); \
2298 tmp_ |= ((val) & ~(mask)); \
2299 WREG32(reg, tmp_); \
2300 } while (0)
d5169fc4 2301#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2302#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2303#define WREG32_PLL_P(reg, val, mask) \
2304 do { \
2305 uint32_t tmp_ = RREG32_PLL(reg); \
2306 tmp_ &= (mask); \
2307 tmp_ |= ((val) & ~(mask)); \
2308 WREG32_PLL(reg, tmp_); \
2309 } while (0)
2ef9bdfe 2310#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2311#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2312#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2313
d5754ab8
AL		 2314#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2315#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
75efdee1 2316
de1b2898
DA		 2317/*
2318 * Indirect registers accessor
2319 */
2320static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2321{
0a5b7b0b 2322 unsigned long flags;
de1b2898
DA		 2323 uint32_t r;
2324
0a5b7b0b 2325 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2326 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2327 r = RREG32(RADEON_PCIE_DATA);
0a5b7b0b 2328 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2329 return r;
2330}
2331
2332static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2333{
0a5b7b0b
AD		 2334 unsigned long flags;
2335
2336 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2337 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2338 WREG32(RADEON_PCIE_DATA, (v));
0a5b7b0b 2339 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2340}
2341
1d5d0c34
AD		 2342static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2343{
fe78118c 2344 unsigned long flags;
1d5d0c34
AD		 2345 u32 r;
2346
fe78118c 2347 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2348 WREG32(TN_SMC_IND_INDEX_0, (reg));
2349 r = RREG32(TN_SMC_IND_DATA_0);
fe78118c 2350 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2351 return r;
2352}
2353
2354static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2355{
fe78118c
AD		 2356 unsigned long flags;
2357
2358 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2359 WREG32(TN_SMC_IND_INDEX_0, (reg));
2360 WREG32(TN_SMC_IND_DATA_0, (v));
fe78118c 2361 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2362}
2363
ff82bbc4
AD		 2364static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2365{
0a5b7b0b 2366 unsigned long flags;
ff82bbc4
AD		 2367 u32 r;
2368
0a5b7b0b 2369 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2370 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2371 r = RREG32(R600_RCU_DATA);
0a5b7b0b 2372 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2373 return r;
2374}
2375
2376static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2377{
0a5b7b0b
AD		 2378 unsigned long flags;
2379
2380 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2381 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2382 WREG32(R600_RCU_DATA, (v));
0a5b7b0b 2383 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2384}
2385
46f9564a
AD		 2386static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2387{
0a5b7b0b 2388 unsigned long flags;
46f9564a
AD		 2389 u32 r;
2390
0a5b7b0b 2391 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2392 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2393 r = RREG32(EVERGREEN_CG_IND_DATA);
0a5b7b0b 2394 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2395 return r;
2396}
2397
2398static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2399{
0a5b7b0b
AD		 2400 unsigned long flags;
2401
2402 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2403 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2404 WREG32(EVERGREEN_CG_IND_DATA, (v));
0a5b7b0b 2405 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2406}
2407
792edd69
AD		 2408static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2409{
0a5b7b0b 2410 unsigned long flags;
792edd69
AD		 2411 u32 r;
2412
0a5b7b0b 2413 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2414 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2415 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
0a5b7b0b 2416 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2417 return r;
2418}
2419
2420static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2421{
0a5b7b0b
AD		 2422 unsigned long flags;
2423
2424 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2425 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2426 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
0a5b7b0b 2427 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2428}
2429
2430static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2431{
0a5b7b0b 2432 unsigned long flags;
792edd69
AD		 2433 u32 r;
2434
0a5b7b0b 2435 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2436 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2437 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
0a5b7b0b 2438 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2439 return r;
2440}
2441
2442static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2443{
0a5b7b0b
AD		 2444 unsigned long flags;
2445
2446 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2447 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2448 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
0a5b7b0b 2449 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2450}
2451
93656cdd
AD		 2452static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2453{
0a5b7b0b 2454 unsigned long flags;
93656cdd
AD		 2455 u32 r;
2456
0a5b7b0b 2457 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2458 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2459 r = RREG32(R600_UVD_CTX_DATA);
0a5b7b0b 2460 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2461 return r;
2462}
2463
2464static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2465{
0a5b7b0b
AD		 2466 unsigned long flags;
2467
2468 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2469 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2470 WREG32(R600_UVD_CTX_DATA, (v));
0a5b7b0b 2471 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2472}
2473
1d58234d
AD		 2474
2475static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2476{
0a5b7b0b 2477 unsigned long flags;
1d58234d
AD		 2478 u32 r;
2479
0a5b7b0b 2480 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2481 WREG32(CIK_DIDT_IND_INDEX, (reg));
2482 r = RREG32(CIK_DIDT_IND_DATA);
0a5b7b0b 2483 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2484 return r;
2485}
2486
2487static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2488{
0a5b7b0b
AD		 2489 unsigned long flags;
2490
2491 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2492 WREG32(CIK_DIDT_IND_INDEX, (reg));
2493 WREG32(CIK_DIDT_IND_DATA, (v));
0a5b7b0b 2494 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2495}
2496
771fe6b9
JG		 2497void r100_pll_errata_after_index(struct radeon_device *rdev);
2498
2499
2500/*
2501 * ASICs helpers.
2502 */
b995e433
DA		 2503#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2504 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2505#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2506 (rdev->family == CHIP_RV200) || \
2507 (rdev->family == CHIP_RS100) || \
2508 (rdev->family == CHIP_RS200) || \
2509 (rdev->family == CHIP_RV250) || \
2510 (rdev->family == CHIP_RV280) || \
2511 (rdev->family == CHIP_RS300))
2512#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2513 (rdev->family == CHIP_RV350) || \
2514 (rdev->family == CHIP_R350) || \
2515 (rdev->family == CHIP_RV380) || \
2516 (rdev->family == CHIP_R420) || \
2517 (rdev->family == CHIP_R423) || \
2518 (rdev->family == CHIP_RV410) || \
2519 (rdev->family == CHIP_RS400) || \
2520 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2521#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2522 (rdev->ddev->pdev->device == 0x9443) || \
2523 (rdev->ddev->pdev->device == 0x944B) || \
2524 (rdev->ddev->pdev->device == 0x9506) || \
2525 (rdev->ddev->pdev->device == 0x9509) || \
2526 (rdev->ddev->pdev->device == 0x950F) || \
2527 (rdev->ddev->pdev->device == 0x689C) || \
2528 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2529#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2530#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2531 (rdev->family == CHIP_RS690) || \
2532 (rdev->family == CHIP_RS740) || \
2533 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2534#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2535#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2536#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2537#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2538 (rdev->flags & RADEON_IS_IGP))
1fe18305 2539#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2540#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2541#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2542 (rdev->flags & RADEON_IS_IGP))
624d3524 2543#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2544#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2545#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
771fe6b9 2546
dc50ba7f
AD		 2547#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2548 (rdev->ddev->pdev->device == 0x6850) || \
2549 (rdev->ddev->pdev->device == 0x6858) || \
2550 (rdev->ddev->pdev->device == 0x6859) || \
2551 (rdev->ddev->pdev->device == 0x6840) || \
2552 (rdev->ddev->pdev->device == 0x6841) || \
2553 (rdev->ddev->pdev->device == 0x6842) || \
2554 (rdev->ddev->pdev->device == 0x6843))
2555
771fe6b9
JG		 2556/*
2557 * BIOS helpers.
2558 */
2559#define RBIOS8(i) (rdev->bios[i])
2560#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2561#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2562
2563int radeon_combios_init(struct radeon_device *rdev);
2564void radeon_combios_fini(struct radeon_device *rdev);
2565int radeon_atombios_init(struct radeon_device *rdev);
2566void radeon_atombios_fini(struct radeon_device *rdev);
2567
2568
2569/*
2570 * RING helpers.
2571 */
ce580fab 2572#if DRM_DEBUG_CODE == 0
e32eb50d 2573static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2574{
e32eb50d
CK		 2575 ring->ring[ring->wptr++] = v;
2576 ring->wptr &= ring->ptr_mask;
2577 ring->count_dw--;
2578 ring->ring_free_dw--;
771fe6b9 2579}
ce580fab
AK		 2580#else
2581/* With debugging this is just too big to inline */
e32eb50d 2582void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
ce580fab 2583#endif
771fe6b9
JG		 2584
2585/*
2586 * ASICs macro.
2587 */
068a117c 2588#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2589#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2590#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2591#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2592#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2593#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2594#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850
AD		 2595#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2596#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
05b07147
CK		 2597#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2598#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
43f1214a 2599#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
76a0df85
CK		 2600#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2601#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2602#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2603#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2604#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2605#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2606#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2607#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2608#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2609#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2610#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2611#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2612#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2613#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2614#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2615#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2616#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2617#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2618#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
27cd7769
AD		 2619#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2620#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2621#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2622#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2623#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2624#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2625#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2626#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2627#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2628#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2629#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2630#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2631#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2632#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
6bd1c385 2633#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2634#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2635#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2636#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2637#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2638#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2639#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2640#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2641#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2642#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2643#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2644#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2645#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2646#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8
AD		 2647#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2648#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2649#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2650#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2651#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2652#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2653#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2654#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2655#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2656#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2657#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2658#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2659#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2660#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2661#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2662#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2663#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2664#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2665#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2666#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2667#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2668#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2669#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
1c71bda0 2670#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
771fe6b9 2671
6cf8a3f5 2672/* Common functions */
700a0cc0 2673/* AGP */
90aca4d2 2674extern int radeon_gpu_reset(struct radeon_device *rdev);
410a3418 2675extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2676extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2677extern int radeon_modeset_init(struct radeon_device *rdev);
2678extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2679extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2680extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2681extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2682extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2683extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2684extern void radeon_wb_fini(struct radeon_device *rdev);
2685extern int radeon_wb_init(struct radeon_device *rdev);
2686extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2687extern void radeon_surface_init(struct radeon_device *rdev);
2688extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2689extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2690extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2691extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2692extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 2693extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2694extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
10ebc0bc
DA		 2695extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2696extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
53595338 2697extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2698extern void radeon_program_register_sequence(struct radeon_device *rdev,
2699 const u32 *registers,
2700 const u32 array_size);
6cf8a3f5 2701
721604a1
JG		 2702/*
2703 * vm
2704 */
2705int radeon_vm_manager_init(struct radeon_device *rdev);
2706void radeon_vm_manager_fini(struct radeon_device *rdev);
d72d43cf 2707void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2708void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
ddf03f5c 2709int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
13e55c38 2710void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
ee60e29f
CK		 2711struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2712 struct radeon_vm *vm, int ring);
2713void radeon_vm_fence(struct radeon_device *rdev,
2714 struct radeon_vm *vm,
2715 struct radeon_fence *fence);
dce34bfd 2716uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
9c57a6bd
CK		 2717int radeon_vm_bo_update(struct radeon_device *rdev,
2718 struct radeon_vm *vm,
2719 struct radeon_bo *bo,
2720 struct ttm_mem_reg *mem);
721604a1
JG		 2721void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2722 struct radeon_bo *bo);
421ca7ab
CK		 2723struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2724 struct radeon_bo *bo);
e971bd5e
CK		 2725struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2726 struct radeon_vm *vm,
2727 struct radeon_bo *bo);
2728int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2729 struct radeon_bo_va *bo_va,
2730 uint64_t offset,
2731 uint32_t flags);
721604a1 2732int radeon_vm_bo_rmv(struct radeon_device *rdev,
e971bd5e 2733 struct radeon_bo_va *bo_va);
721604a1 2734
f122c610
AD		 2735/* audio */
2736void r600_audio_update_hdmi(struct work_struct *work);
b530602f
AD		 2737struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2738struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
721604a1 2739
16cdf04d
AD		 2740/*
2741 * R600 vram scratch functions
2742 */
2743int r600_vram_scratch_init(struct radeon_device *rdev);
2744void r600_vram_scratch_fini(struct radeon_device *rdev);
2745
285484e2
JG		 2746/*
2747 * r600 cs checking helper
2748 */
2749unsigned r600_mip_minify(unsigned size, unsigned level);
2750bool r600_fmt_is_valid_color(u32 format);
2751bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2752int r600_fmt_get_blocksize(u32 format);
2753int r600_fmt_get_nblocksx(u32 format, u32 w);
2754int r600_fmt_get_nblocksy(u32 format, u32 h);
2755
3574dda4
DV		 2756/*
2757 * r600 functions used by radeon_encoder.c
2758 */
1b688d08
RM		 2759struct radeon_hdmi_acr {
2760 u32 clock;
2761
2762 int n_32khz;
2763 int cts_32khz;
2764
2765 int n_44_1khz;
2766 int cts_44_1khz;
2767
2768 int n_48khz;
2769 int cts_48khz;
2770
2771};
2772
e55d3e6c
RM		 2773extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2774
416a2bd2
AD		 2775extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2776 u32 tiling_pipe_num,
2777 u32 max_rb_num,
2778 u32 total_max_rb_num,
2779 u32 enabled_rb_mask);
fe251e2f 2780
e55d3e6c
RM		 2781/*
2782 * evergreen functions used by radeon_encoder.c
2783 */
2784
0af62b01 2785extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2786extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2787
c4917074
AD		 2788/* radeon_acpi.c */
2789#if defined(CONFIG_ACPI)
2790extern int radeon_acpi_init(struct radeon_device *rdev);
2791extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2792extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2793extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2794 u8 perf_req, bool advertise);
dc50ba7f 2795extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2796#else
2797static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2798static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2799#endif
d7a2952f 2800
c38f34b5
IH		 2801int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2802 struct radeon_cs_packet *pkt,
2803 unsigned idx);
9ffb7a6d 2804bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2805void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2806 struct radeon_cs_packet *pkt);
e9716993
IH		 2807int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2808 struct radeon_cs_reloc **cs_reloc,
2809 int nomm);
40592a17
IH		 2810int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2811 uint32_t *vline_start_end,
2812 uint32_t *vline_status);
c38f34b5 2813
4c788679
JG		 2814#include "radeon_object.h"
2815
771fe6b9 2816#endif
Linux kernel - Deliverables
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