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drm/radeon: drop CP page table updates & cleanup v2
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
a18cee15 96extern int radeon_msi;
3368ff0c 97extern int radeon_lockup_timeout;
a0a53aa8 98extern int radeon_fastfb;
da321c8a 99extern int radeon_dpm;
1294d4a3 100extern int radeon_aspm;
10ebc0bc 101extern int radeon_runtime_pm;
771fe6b9
JG		 102
103/*
104 * Copy from radeon_drv.h so we don't have to include both and have conflicting
105 * symbol;
106 */
bb635567
JG		 107#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
108#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 109/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 110#define RADEON_IB_POOL_SIZE 16
111#define RADEON_DEBUGFS_MAX_COMPONENTS 32
112#define RADEONFB_CONN_LIMIT 4
113#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 114
1b37078b 115/* max number of rings */
f2ba57b5 116#define RADEON_NUM_RINGS 6
bb635567
JG		 117
118/* fence seq are set to this number when signaled */
119#define RADEON_FENCE_SIGNALED_SEQ 0LL
1b37078b
AD		 120
121/* internal ring indices */
122/* r1xx+ has gfx CP ring */
f2ba57b5 123#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 124
125/* cayman has 2 compute CP rings */
f2ba57b5
CK		 126#define CAYMAN_RING_TYPE_CP1_INDEX 1
127#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 128
4d75658b
AD		 129/* R600+ has an async dma ring */
130#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 131/* cayman add a second async dma ring */
132#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 133
f2ba57b5
CK		 134/* R600+ */
135#define R600_RING_TYPE_UVD_INDEX 5
136
721604a1 137/* hardcode those limit for now */
ca19f21e 138#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 139#define RADEON_VA_RESERVED_SIZE (8 << 20)
140#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 141
ec46c76d
AD		 142/* reset flags */
143#define RADEON_RESET_GFX (1 << 0)
144#define RADEON_RESET_COMPUTE (1 << 1)
145#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 146#define RADEON_RESET_CP (1 << 3)
147#define RADEON_RESET_GRBM (1 << 4)
148#define RADEON_RESET_DMA1 (1 << 5)
149#define RADEON_RESET_RLC (1 << 6)
150#define RADEON_RESET_SEM (1 << 7)
151#define RADEON_RESET_IH (1 << 8)
152#define RADEON_RESET_VMC (1 << 9)
153#define RADEON_RESET_MC (1 << 10)
154#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 155
22c775ce
AD		 156/* CG block flags */
157#define RADEON_CG_BLOCK_GFX (1 << 0)
158#define RADEON_CG_BLOCK_MC (1 << 1)
159#define RADEON_CG_BLOCK_SDMA (1 << 2)
160#define RADEON_CG_BLOCK_UVD (1 << 3)
161#define RADEON_CG_BLOCK_VCE (1 << 4)
162#define RADEON_CG_BLOCK_HDP (1 << 5)
e16866ec 163#define RADEON_CG_BLOCK_BIF (1 << 6)
22c775ce 164
64d8a728
AD		 165/* CG flags */
166#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
167#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
168#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
169#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
170#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
171#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
172#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
173#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
174#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
175#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
176#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
177#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
178#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
179#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
180#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
181#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
182#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
183
184/* PG flags */
2b19d17f 185#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
64d8a728
AD		 186#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
187#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
188#define RADEON_PG_SUPPORT_UVD (1 << 3)
189#define RADEON_PG_SUPPORT_VCE (1 << 4)
190#define RADEON_PG_SUPPORT_CP (1 << 5)
191#define RADEON_PG_SUPPORT_GDS (1 << 6)
192#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
193#define RADEON_PG_SUPPORT_SDMA (1 << 8)
194#define RADEON_PG_SUPPORT_ACP (1 << 9)
195#define RADEON_PG_SUPPORT_SAMU (1 << 10)
196
9e05fa1d
AD		 197/* max cursor sizes (in pixels) */
198#define CURSOR_WIDTH 64
199#define CURSOR_HEIGHT 64
200
201#define CIK_CURSOR_WIDTH 128
202#define CIK_CURSOR_HEIGHT 128
203
771fe6b9
JG		 204/*
205 * Errata workarounds.
206 */
207enum radeon_pll_errata {
208 CHIP_ERRATA_R300_CG = 0x00000001,
209 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
210 CHIP_ERRATA_PLL_DELAY = 0x00000004
211};
212
213
214struct radeon_device;
215
216
217/*
218 * BIOS.
219 */
220bool radeon_get_bios(struct radeon_device *rdev);
221
222/*
3ce0a23d 223 * Dummy page
771fe6b9 224 */
3ce0a23d
JG		 225struct radeon_dummy_page {
226 struct page *page;
227 dma_addr_t addr;
228};
229int radeon_dummy_page_init(struct radeon_device *rdev);
230void radeon_dummy_page_fini(struct radeon_device *rdev);
231
771fe6b9 232
3ce0a23d
JG		 233/*
234 * Clocks
235 */
771fe6b9
JG		 236struct radeon_clock {
237 struct radeon_pll p1pll;
238 struct radeon_pll p2pll;
bcc1c2a1 239 struct radeon_pll dcpll;
771fe6b9
JG		 240 struct radeon_pll spll;
241 struct radeon_pll mpll;
242 /* 10 Khz units */
243 uint32_t default_mclk;
244 uint32_t default_sclk;
bcc1c2a1 245 uint32_t default_dispclk;
4489cd62 246 uint32_t current_dispclk;
bcc1c2a1 247 uint32_t dp_extclk;
b20f9bef 248 uint32_t max_pixel_clock;
771fe6b9
JG		 249};
250
7433874e
RM		 251/*
252 * Power management
253 */
254int radeon_pm_init(struct radeon_device *rdev);
29fb52ca 255void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 256void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 257void radeon_pm_suspend(struct radeon_device *rdev);
258void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 259void radeon_combios_get_power_modes(struct radeon_device *rdev);
260void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 261int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
262 u8 clock_type,
263 u32 clock,
264 bool strobe_mode,
265 struct atom_clock_dividers *dividers);
eaa778af
AD		 266int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
267 u32 clock,
268 bool strobe_mode,
269 struct atom_mpll_param *mpll_param);
8a83ec5e 270void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 271int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
272 u16 voltage_level, u8 voltage_type,
273 u32 *gpio_value, u32 *gpio_mask);
274void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
275 u32 eng_clock, u32 mem_clock);
276int radeon_atom_get_voltage_step(struct radeon_device *rdev,
277 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 278int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
279 u16 voltage_id, u16 *voltage);
beb79f40
AD		 280int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
281 u16 *voltage,
282 u16 leakage_idx);
cc8dbbb4
AD		 283int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
284 u16 *leakage_id);
285int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
286 u16 *vddc, u16 *vddci,
287 u16 virtual_voltage_id,
288 u16 vbios_voltage_id);
ae5b0abb
AD		 289int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
290 u8 voltage_type,
291 u16 nominal_voltage,
292 u16 *true_voltage);
293int radeon_atom_get_min_voltage(struct radeon_device *rdev,
294 u8 voltage_type, u16 *min_voltage);
295int radeon_atom_get_max_voltage(struct radeon_device *rdev,
296 u8 voltage_type, u16 *max_voltage);
297int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 298 u8 voltage_type, u8 voltage_mode,
ae5b0abb 299 struct atom_voltage_table *voltage_table);
58653abd
AD		 300bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
301 u8 voltage_type, u8 voltage_mode);
ae5b0abb
AD		 302void radeon_atom_update_memory_dll(struct radeon_device *rdev,
303 u32 mem_clock);
304void radeon_atom_set_ac_timing(struct radeon_device *rdev,
305 u32 mem_clock);
306int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
307 u8 module_index,
308 struct atom_mc_reg_table *reg_table);
309int radeon_atom_get_memory_info(struct radeon_device *rdev,
310 u8 module_index, struct atom_memory_info *mem_info);
311int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
312 bool gddr5, u8 module_index,
313 struct atom_memory_clock_range_table *mclk_range_table);
314int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
315 u16 voltage_id, u16 *voltage);
f892034a 316void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 317extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
318 unsigned *bankh, unsigned *mtaspect,
319 unsigned *tile_split);
3ce0a23d 320
771fe6b9
JG		 321/*
322 * Fences.
323 */
324struct radeon_fence_driver {
325 uint32_t scratch_reg;
30eb77f4
JG		 326 uint64_t gpu_addr;
327 volatile uint32_t *cpu_addr;
68e250b7
CK		 328 /* sync_seq is protected by ring emission lock */
329 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 330 atomic64_t last_seq;
0a0c7596 331 bool initialized;
771fe6b9
JG		 332};
333
334struct radeon_fence {
335 struct radeon_device *rdev;
336 struct kref kref;
771fe6b9 337 /* protected by radeon_fence.lock */
bb635567 338 uint64_t seq;
7465280c 339 /* RB, DMA, etc. */
bb635567 340 unsigned ring;
771fe6b9
JG		 341};
342
30eb77f4
JG		 343int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
344int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 345void radeon_fence_driver_fini(struct radeon_device *rdev);
76903b96 346void radeon_fence_driver_force_completion(struct radeon_device *rdev);
876dc9f3 347int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 348void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 349bool radeon_fence_signaled(struct radeon_fence *fence);
350int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
8a47cc9e 351int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
5f8f635e 352int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
0085c950
JG		 353int radeon_fence_wait_any(struct radeon_device *rdev,
354 struct radeon_fence **fences,
355 bool intr);
771fe6b9
JG		 356struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
357void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 358unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 359bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
360void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
361static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
362 struct radeon_fence *b)
363{
364 if (!a) {
365 return b;
366 }
367
368 if (!b) {
369 return a;
370 }
371
372 BUG_ON(a->ring != b->ring);
373
374 if (a->seq > b->seq) {
375 return a;
376 } else {
377 return b;
378 }
379}
771fe6b9 380
ee60e29f
CK		 381static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
382 struct radeon_fence *b)
383{
384 if (!a) {
385 return false;
386 }
387
388 if (!b) {
389 return true;
390 }
391
392 BUG_ON(a->ring != b->ring);
393
394 return a->seq < b->seq;
395}
396
e024e110
DA		 397/*
398 * Tiling registers
399 */
400struct radeon_surface_reg {
4c788679 401 struct radeon_bo *bo;
e024e110
DA		 402};
403
404#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 405
406/*
4c788679 407 * TTM.
771fe6b9 408 */
4c788679
JG		 409struct radeon_mman {
410 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 411 struct drm_global_reference mem_global_ref;
4c788679 412 struct ttm_bo_device bdev;
0a0c7596
JG		 413 bool mem_global_referenced;
414 bool initialized;
4c788679
JG		 415};
416
721604a1
JG		 417/* bo virtual address in a specific vm */
418struct radeon_bo_va {
e971bd5e 419 /* protected by bo being reserved */
721604a1 420 struct list_head bo_list;
721604a1
JG		 421 uint64_t soffset;
422 uint64_t eoffset;
423 uint32_t flags;
424 bool valid;
e971bd5e
CK		 425 unsigned ref_count;
426
427 /* protected by vm mutex */
428 struct list_head vm_list;
429
430 /* constant after initialization */
431 struct radeon_vm *vm;
432 struct radeon_bo *bo;
721604a1
JG		 433};
434
4c788679
JG		 435struct radeon_bo {
436 /* Protected by gem.mutex */
437 struct list_head list;
438 /* Protected by tbo.reserved */
312ea8da
JG		 439 u32 placements[3];
440 struct ttm_placement placement;
4c788679
JG		 441 struct ttm_buffer_object tbo;
442 struct ttm_bo_kmap_obj kmap;
443 unsigned pin_count;
444 void *kptr;
445 u32 tiling_flags;
446 u32 pitch;
447 int surface_reg;
721604a1
JG		 448 /* list of all virtual address to which this bo
449 * is associated to
450 */
451 struct list_head va;
4c788679
JG		 452 /* Constant after initialization */
453 struct radeon_device *rdev;
441921d5 454 struct drm_gem_object gem_base;
63bc620b 455
409851f4
JG		 456 struct ttm_bo_kmap_obj dma_buf_vmap;
457 pid_t pid;
4c788679 458};
7e4d15d9 459#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 460
4c788679 461struct radeon_bo_list {
147666fb 462 struct ttm_validate_buffer tv;
4c788679 463 struct radeon_bo *bo;
771fe6b9 464 uint64_t gpu_offset;
4474f3a9
CK		 465 bool written;
466 unsigned domain;
467 unsigned alt_domain;
4c788679 468 u32 tiling_flags;
771fe6b9
JG		 469};
470
409851f4
JG		 471int radeon_gem_debugfs_init(struct radeon_device *rdev);
472
b15ba512
JG		 473/* sub-allocation manager, it has to be protected by another lock.
474 * By conception this is an helper for other part of the driver
475 * like the indirect buffer or semaphore, which both have their
476 * locking.
477 *
478 * Principe is simple, we keep a list of sub allocation in offset
479 * order (first entry has offset == 0, last entry has the highest
480 * offset).
481 *
482 * When allocating new object we first check if there is room at
483 * the end total_size - (last_object_offset + last_object_size) >=
484 * alloc_size. If so we allocate new object there.
485 *
486 * When there is not enough room at the end, we start waiting for
487 * each sub object until we reach object_offset+object_size >=
488 * alloc_size, this object then become the sub object we return.
489 *
490 * Alignment can't be bigger than page size.
491 *
492 * Hole are not considered for allocation to keep things simple.
493 * Assumption is that there won't be hole (all object on same
494 * alignment).
495 */
496struct radeon_sa_manager {
bfb38d35 497 wait_queue_head_t wq;
b15ba512 498 struct radeon_bo *bo;
c3b7fe8b
CK		 499 struct list_head *hole;
500 struct list_head flist[RADEON_NUM_RINGS];
501 struct list_head olist;
b15ba512
JG		 502 unsigned size;
503 uint64_t gpu_addr;
504 void *cpu_ptr;
505 uint32_t domain;
6c4f978b 506 uint32_t align;
b15ba512
JG		 507};
508
509struct radeon_sa_bo;
510
511/* sub-allocation buffer */
512struct radeon_sa_bo {
c3b7fe8b
CK		 513 struct list_head olist;
514 struct list_head flist;
b15ba512 515 struct radeon_sa_manager *manager;
e6661a96
CK		 516 unsigned soffset;
517 unsigned eoffset;
557017a0 518 struct radeon_fence *fence;
b15ba512
JG		 519};
520
771fe6b9
JG		 521/*
522 * GEM objects.
523 */
524struct radeon_gem {
4c788679 525 struct mutex mutex;
771fe6b9
JG		 526 struct list_head objects;
527};
528
529int radeon_gem_init(struct radeon_device *rdev);
530void radeon_gem_fini(struct radeon_device *rdev);
531int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 532 int alignment, int initial_domain,
533 bool discardable, bool kernel,
534 struct drm_gem_object **obj);
771fe6b9 535
ff72145b
DA		 536int radeon_mode_dumb_create(struct drm_file *file_priv,
537 struct drm_device *dev,
538 struct drm_mode_create_dumb *args);
539int radeon_mode_dumb_mmap(struct drm_file *filp,
540 struct drm_device *dev,
541 uint32_t handle, uint64_t *offset_p);
771fe6b9 542
c1341e52
JG		 543/*
544 * Semaphores.
545 */
c1341e52
JG		 546/* everything here is constant */
547struct radeon_semaphore {
a8c05940
JG		 548 struct radeon_sa_bo *sa_bo;
549 signed waiters;
c1341e52 550 uint64_t gpu_addr;
c1341e52
JG		 551};
552
c1341e52
JG		 553int radeon_semaphore_create(struct radeon_device *rdev,
554 struct radeon_semaphore **semaphore);
555void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
556 struct radeon_semaphore *semaphore);
557void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
558 struct radeon_semaphore *semaphore);
8f676c4c
CK		 559int radeon_semaphore_sync_rings(struct radeon_device *rdev,
560 struct radeon_semaphore *semaphore,
220907d9 561 int signaler, int waiter);
c1341e52 562void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 563 struct radeon_semaphore **semaphore,
a8c05940 564 struct radeon_fence *fence);
c1341e52 565
771fe6b9
JG		 566/*
567 * GART structures, functions & helpers
568 */
569struct radeon_mc;
570
a77f1718 571#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 572#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 573#define RADEON_GPU_PAGE_SHIFT 12
721604a1 574#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 575
771fe6b9
JG		 576struct radeon_gart {
577 dma_addr_t table_addr;
c9a1be96
JG		 578 struct radeon_bo *robj;
579 void *ptr;
771fe6b9
JG		 580 unsigned num_gpu_pages;
581 unsigned num_cpu_pages;
582 unsigned table_size;
771fe6b9
JG		 583 struct page **pages;
584 dma_addr_t *pages_addr;
585 bool ready;
586};
587
588int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
589void radeon_gart_table_ram_free(struct radeon_device *rdev);
590int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
591void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 592int radeon_gart_table_vram_pin(struct radeon_device *rdev);
593void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 594int radeon_gart_init(struct radeon_device *rdev);
595void radeon_gart_fini(struct radeon_device *rdev);
596void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
597 int pages);
598int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516
KRW		 599 int pages, struct page **pagelist,
600 dma_addr_t *dma_addr);
c9a1be96 601void radeon_gart_restore(struct radeon_device *rdev);
771fe6b9
JG		 602
603
604/*
605 * GPU MC structures, functions & helpers
606 */
607struct radeon_mc {
608 resource_size_t aper_size;
609 resource_size_t aper_base;
610 resource_size_t agp_base;
7a50f01a
DA		 611 /* for some chips with <= 32MB we need to lie
612 * about vram size near mc fb location */
3ce0a23d 613 u64 mc_vram_size;
d594e46a 614 u64 visible_vram_size;
3ce0a23d
JG		 615 u64 gtt_size;
616 u64 gtt_start;
617 u64 gtt_end;
3ce0a23d
JG		 618 u64 vram_start;
619 u64 vram_end;
771fe6b9 620 unsigned vram_width;
3ce0a23d 621 u64 real_vram_size;
771fe6b9
JG		 622 int vram_mtrr;
623 bool vram_is_ddr;
d594e46a 624 bool igp_sideport_enabled;
8d369bb1 625 u64 gtt_base_align;
9ed8b1f9 626 u64 mc_mask;
771fe6b9
JG		 627};
628
06b6476d
AD		 629bool radeon_combios_sideport_present(struct radeon_device *rdev);
630bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 631
632/*
633 * GPU scratch registers structures, functions & helpers
634 */
635struct radeon_scratch {
636 unsigned num_reg;
724c80e1 637 uint32_t reg_base;
771fe6b9
JG		 638 bool free[32];
639 uint32_t reg[32];
640};
641
642int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
643void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
644
75efdee1
AD		 645/*
646 * GPU doorbell structures, functions & helpers
647 */
648struct radeon_doorbell {
649 u32 num_pages;
650 bool free[1024];
651 /* doorbell mmio */
652 resource_size_t base;
653 resource_size_t size;
654 void __iomem *ptr;
655};
656
657int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
658void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771fe6b9
JG		 659
660/*
661 * IRQS.
662 */
6f34be50
AD		 663
664struct radeon_unpin_work {
665 struct work_struct work;
666 struct radeon_device *rdev;
667 int crtc_id;
668 struct radeon_fence *fence;
669 struct drm_pending_vblank_event *event;
670 struct radeon_bo *old_rbo;
671 u64 new_crtc_base;
672};
673
674struct r500_irq_stat_regs {
675 u32 disp_int;
f122c610 676 u32 hdmi0_status;
6f34be50
AD		 677};
678
679struct r600_irq_stat_regs {
680 u32 disp_int;
681 u32 disp_int_cont;
682 u32 disp_int_cont2;
683 u32 d1grph_int;
684 u32 d2grph_int;
f122c610
AD		 685 u32 hdmi0_status;
686 u32 hdmi1_status;
6f34be50
AD		 687};
688
689struct evergreen_irq_stat_regs {
690 u32 disp_int;
691 u32 disp_int_cont;
692 u32 disp_int_cont2;
693 u32 disp_int_cont3;
694 u32 disp_int_cont4;
695 u32 disp_int_cont5;
696 u32 d1grph_int;
697 u32 d2grph_int;
698 u32 d3grph_int;
699 u32 d4grph_int;
700 u32 d5grph_int;
701 u32 d6grph_int;
f122c610
AD		 702 u32 afmt_status1;
703 u32 afmt_status2;
704 u32 afmt_status3;
705 u32 afmt_status4;
706 u32 afmt_status5;
707 u32 afmt_status6;
6f34be50
AD		 708};
709
a59781bb
AD		 710struct cik_irq_stat_regs {
711 u32 disp_int;
712 u32 disp_int_cont;
713 u32 disp_int_cont2;
714 u32 disp_int_cont3;
715 u32 disp_int_cont4;
716 u32 disp_int_cont5;
717 u32 disp_int_cont6;
718};
719
6f34be50
AD		 720union radeon_irq_stat_regs {
721 struct r500_irq_stat_regs r500;
722 struct r600_irq_stat_regs r600;
723 struct evergreen_irq_stat_regs evergreen;
a59781bb 724 struct cik_irq_stat_regs cik;
6f34be50
AD		 725};
726
54bd5206
IH		 727#define RADEON_MAX_HPD_PINS 6
728#define RADEON_MAX_CRTCS 6
b530602f 729#define RADEON_MAX_AFMT_BLOCKS 7
54bd5206 730
771fe6b9 731struct radeon_irq {
fb98257a
CK		 732 bool installed;
733 spinlock_t lock;
736fc37f 734 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 735 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 736 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 737 wait_queue_head_t vblank_queue;
738 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 739 bool afmt[RADEON_MAX_AFMT_BLOCKS];
740 union radeon_irq_stat_regs stat_regs;
4a6369e9 741 bool dpm_thermal;
771fe6b9
JG		 742};
743
744int radeon_irq_kms_init(struct radeon_device *rdev);
745void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b
AD		 746void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
747void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 748void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
749void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 750void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
751void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
752void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
753void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 754
755/*
e32eb50d 756 * CP & rings.
771fe6b9 757 */
7465280c 758
771fe6b9 759struct radeon_ib {
68470ae7
JG		 760 struct radeon_sa_bo *sa_bo;
761 uint32_t length_dw;
762 uint64_t gpu_addr;
763 uint32_t *ptr;
876dc9f3 764 int ring;
68470ae7 765 struct radeon_fence *fence;
4bf3dd92 766 struct radeon_vm *vm;
68470ae7 767 bool is_const_ib;
220907d9 768 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
68470ae7 769 struct radeon_semaphore *semaphore;
771fe6b9
JG		 770};
771
e32eb50d 772struct radeon_ring {
4c788679 773 struct radeon_bo *ring_obj;
771fe6b9
JG		 774 volatile uint32_t *ring;
775 unsigned rptr;
5596a9db
CK		 776 unsigned rptr_offs;
777 unsigned rptr_reg;
45df6803 778 unsigned rptr_save_reg;
89d35807
AD		 779 u64 next_rptr_gpu_addr;
780 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 781 unsigned wptr;
782 unsigned wptr_old;
5596a9db 783 unsigned wptr_reg;
771fe6b9
JG		 784 unsigned ring_size;
785 unsigned ring_free_dw;
786 int count_dw;
069211e5
CK		 787 unsigned long last_activity;
788 unsigned last_rptr;
771fe6b9
JG		 789 uint64_t gpu_addr;
790 uint32_t align_mask;
791 uint32_t ptr_mask;
771fe6b9 792 bool ready;
78c5560a 793 u32 nop;
8b25ed34 794 u32 idx;
5f0839c1
JG		 795 u64 last_semaphore_signal_addr;
796 u64 last_semaphore_wait_addr;
963e81f9
AD		 797 /* for CIK queues */
798 u32 me;
799 u32 pipe;
800 u32 queue;
801 struct radeon_bo *mqd_obj;
802 u32 doorbell_page_num;
803 u32 doorbell_offset;
804 unsigned wptr_offs;
805};
806
807struct radeon_mec {
808 struct radeon_bo *hpd_eop_obj;
809 u64 hpd_eop_gpu_addr;
810 u32 num_pipe;
811 u32 num_mec;
812 u32 num_queue;
771fe6b9
JG		 813};
814
721604a1
JG		 815/*
816 * VM
817 */
ee60e29f 818
fa87e62d 819/* maximum number of VMIDs */
ee60e29f
CK		 820#define RADEON_NUM_VM 16
821
fa87e62d
DC		 822/* defines number of bits in page table versus page directory,
823 * a page is 4KB so we have 12 bits offset, 9 bits in the page
824 * table and the remaining 19 bits are in the page directory */
825#define RADEON_VM_BLOCK_SIZE 9
826
827/* number of entries in page table */
828#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
829
1c01103c
AD		 830/* PTBs (Page Table Blocks) need to be aligned to 32K */
831#define RADEON_VM_PTB_ALIGN_SIZE 32768
832#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
833#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
834
24c16439
CK		 835#define R600_PTE_VALID (1 << 0)
836#define R600_PTE_SYSTEM (1 << 1)
837#define R600_PTE_SNOOPED (1 << 2)
838#define R600_PTE_READABLE (1 << 5)
839#define R600_PTE_WRITEABLE (1 << 6)
840
721604a1
JG		 841struct radeon_vm {
842 struct list_head list;
843 struct list_head va;
ee60e29f 844 unsigned id;
90a51a32
CK		 845
846 /* contains the page directory */
847 struct radeon_sa_bo *page_directory;
848 uint64_t pd_gpu_addr;
849
850 /* array of page tables, one for each page directory entry */
851 struct radeon_sa_bo **page_tables;
852
721604a1
JG		 853 struct mutex mutex;
854 /* last fence for cs using this vm */
855 struct radeon_fence *fence;
9b40e5d8
CK		 856 /* last flush or NULL if we still need to flush */
857 struct radeon_fence *last_flush;
721604a1
JG		 858};
859
721604a1 860struct radeon_vm_manager {
36ff39c4 861 struct mutex lock;
721604a1 862 struct list_head lru_vm;
ee60e29f 863 struct radeon_fence *active[RADEON_NUM_VM];
721604a1
JG		 864 struct radeon_sa_manager sa_manager;
865 uint32_t max_pfn;
721604a1
JG		 866 /* number of VMIDs */
867 unsigned nvm;
868 /* vram base address for page table entry */
869 u64 vram_base_offset;
67e915e4
AD		 870 /* is vm enabled? */
871 bool enabled;
721604a1
JG		 872};
873
874/*
875 * file private structure
876 */
877struct radeon_fpriv {
878 struct radeon_vm vm;
879};
880
d8f60cfc
AD		 881/*
882 * R6xx+ IH ring
883 */
884struct r600_ih {
4c788679 885 struct radeon_bo *ring_obj;
d8f60cfc
AD		 886 volatile uint32_t *ring;
887 unsigned rptr;
d8f60cfc
AD		 888 unsigned ring_size;
889 uint64_t gpu_addr;
d8f60cfc 890 uint32_t ptr_mask;
c20dc369 891 atomic_t lock;
d8f60cfc
AD		 892 bool enabled;
893};
894
347e7592 895/*
2948f5e6 896 * RLC stuff
347e7592 897 */
2948f5e6
AD		 898#include "clearstate_defs.h"
899
900struct radeon_rlc {
347e7592
AD		 901 /* for power gating */
902 struct radeon_bo *save_restore_obj;
903 uint64_t save_restore_gpu_addr;
2948f5e6 904 volatile uint32_t *sr_ptr;
1fd11777 905 const u32 *reg_list;
2948f5e6 906 u32 reg_list_size;
347e7592
AD		 907 /* for clear state */
908 struct radeon_bo *clear_state_obj;
909 uint64_t clear_state_gpu_addr;
2948f5e6 910 volatile uint32_t *cs_ptr;
1fd11777 911 const struct cs_section_def *cs_data;
22c775ce
AD		 912 u32 clear_state_size;
913 /* for cp tables */
914 struct radeon_bo *cp_table_obj;
915 uint64_t cp_table_gpu_addr;
916 volatile uint32_t *cp_table_ptr;
917 u32 cp_table_size;
347e7592
AD		 918};
919
69e130a6 920int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 921 struct radeon_ib *ib, struct radeon_vm *vm,
922 unsigned size);
f2e39221 923void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
43f1214a 924void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
4ef72566
CK		 925int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
926 struct radeon_ib *const_ib);
771fe6b9
JG		 927int radeon_ib_pool_init(struct radeon_device *rdev);
928void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 929int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 930/* Ring access between begin & end cannot sleep */
89d35807
AD		 931bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
932 struct radeon_ring *ring);
e32eb50d
CK		 933void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
934int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
935int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
936void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
937void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
d6999bc7 938void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 939void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
940int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
7b9ef16b 941void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
069211e5
CK		 942void radeon_ring_lockup_update(struct radeon_ring *ring);
943bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 944unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
945 uint32_t **data);
946int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
947 unsigned size, uint32_t *data);
e32eb50d 948int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
2e1e6dad 949 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, u32 nop);
e32eb50d 950void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 951
952
4d75658b
AD		 953/* r600 async dma */
954void r600_dma_stop(struct radeon_device *rdev);
955int r600_dma_resume(struct radeon_device *rdev);
956void r600_dma_fini(struct radeon_device *rdev);
957
8c5fd7ef
AD		 958void cayman_dma_stop(struct radeon_device *rdev);
959int cayman_dma_resume(struct radeon_device *rdev);
960void cayman_dma_fini(struct radeon_device *rdev);
961
771fe6b9
JG		 962/*
963 * CS.
964 */
965struct radeon_cs_reloc {
966 struct drm_gem_object *gobj;
4c788679
JG		 967 struct radeon_bo *robj;
968 struct radeon_bo_list lobj;
771fe6b9
JG		 969 uint32_t handle;
970 uint32_t flags;
971};
972
973struct radeon_cs_chunk {
974 uint32_t chunk_id;
975 uint32_t length_dw;
721604a1
JG		 976 int kpage_idx[2];
977 uint32_t *kpage[2];
771fe6b9 978 uint32_t *kdata;
721604a1
JG		 979 void __user *user_ptr;
980 int last_copied_page;
981 int last_page_index;
771fe6b9
JG		 982};
983
984struct radeon_cs_parser {
c8c15ff1 985 struct device *dev;
771fe6b9
JG		 986 struct radeon_device *rdev;
987 struct drm_file *filp;
988 /* chunks */
989 unsigned nchunks;
990 struct radeon_cs_chunk *chunks;
991 uint64_t *chunks_array;
992 /* IB */
993 unsigned idx;
994 /* relocations */
995 unsigned nrelocs;
996 struct radeon_cs_reloc *relocs;
997 struct radeon_cs_reloc **relocs_ptr;
998 struct list_head validated;
cf4ccd01 999 unsigned dma_reloc_idx;
771fe6b9
JG		 1000 /* indices of various chunks */
1001 int chunk_ib_idx;
1002 int chunk_relocs_idx;
721604a1 1003 int chunk_flags_idx;
dfcf5f36 1004 int chunk_const_ib_idx;
f2e39221
JG		 1005 struct radeon_ib ib;
1006 struct radeon_ib const_ib;
771fe6b9 1007 void *track;
3ce0a23d 1008 unsigned family;
e70f224c 1009 int parser_error;
721604a1
JG		 1010 u32 cs_flags;
1011 u32 ring;
1012 s32 priority;
ecff665f 1013 struct ww_acquire_ctx ticket;
771fe6b9
JG		 1014};
1015
513bcb46 1016extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
ce580fab 1017extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
513bcb46 1018
771fe6b9
JG		 1019struct radeon_cs_packet {
1020 unsigned idx;
1021 unsigned type;
1022 unsigned reg;
1023 unsigned opcode;
1024 int count;
1025 unsigned one_reg_wr;
1026};
1027
1028typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1029 struct radeon_cs_packet *pkt,
1030 unsigned idx, unsigned reg);
1031typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1032 struct radeon_cs_packet *pkt);
1033
1034
1035/*
1036 * AGP
1037 */
1038int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1039void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1040void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1041void radeon_agp_fini(struct radeon_device *rdev);
1042
1043
1044/*
1045 * Writeback
1046 */
1047struct radeon_wb {
4c788679 1048 struct radeon_bo *wb_obj;
771fe6b9
JG		 1049 volatile uint32_t *wb;
1050 uint64_t gpu_addr;
724c80e1 1051 bool enabled;
d0f8a854 1052 bool use_event;
771fe6b9
JG		 1053};
1054
724c80e1 1055#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1056#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1057#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1058#define RADEON_WB_CP1_RPTR_OFFSET 1280
1059#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1060#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1061#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1062#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1063#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1064#define CIK_WB_CP1_WPTR_OFFSET 3328
1065#define CIK_WB_CP2_WPTR_OFFSET 3584
724c80e1 1066
c93bb85b
JG		 1067/**
1068 * struct radeon_pm - power management datas
1069 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1070 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1071 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1072 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1073 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1074 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1075 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1076 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1077 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1078 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1079 * @needed_bandwidth: current bandwidth needs
1080 *
1081 * It keeps track of various data needed to take powermanagement decision.
25985edc 1082 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1083 * Equation between gpu/memory clock and available bandwidth is hw dependent
1084 * (type of memory, bus size, efficiency, ...)
1085 */
ce8f5370
AD		 1086
1087enum radeon_pm_method {
1088 PM_METHOD_PROFILE,
1089 PM_METHOD_DYNPM,
da321c8a 1090 PM_METHOD_DPM,
ce8f5370
AD		 1091};
1092
1093enum radeon_dynpm_state {
1094 DYNPM_STATE_DISABLED,
1095 DYNPM_STATE_MINIMUM,
1096 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1097 DYNPM_STATE_ACTIVE,
1098 DYNPM_STATE_SUSPENDED,
c913e23a 1099};
ce8f5370
AD		 1100enum radeon_dynpm_action {
1101 DYNPM_ACTION_NONE,
1102 DYNPM_ACTION_MINIMUM,
1103 DYNPM_ACTION_DOWNCLOCK,
1104 DYNPM_ACTION_UPCLOCK,
1105 DYNPM_ACTION_DEFAULT
c913e23a 1106};
56278a8e
AD		 1107
1108enum radeon_voltage_type {
1109 VOLTAGE_NONE = 0,
1110 VOLTAGE_GPIO,
1111 VOLTAGE_VDDC,
1112 VOLTAGE_SW
1113};
1114
0ec0e74f 1115enum radeon_pm_state_type {
da321c8a 1116 /* not used for dpm */
0ec0e74f
AD		 1117 POWER_STATE_TYPE_DEFAULT,
1118 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1119 /* user selectable states */
0ec0e74f
AD		 1120 POWER_STATE_TYPE_BATTERY,
1121 POWER_STATE_TYPE_BALANCED,
1122 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1123 /* internal states */
1124 POWER_STATE_TYPE_INTERNAL_UVD,
1125 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1126 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1127 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1128 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1129 POWER_STATE_TYPE_INTERNAL_BOOT,
1130 POWER_STATE_TYPE_INTERNAL_THERMAL,
1131 POWER_STATE_TYPE_INTERNAL_ACPI,
1132 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1133 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1134};
1135
ce8f5370
AD		 1136enum radeon_pm_profile_type {
1137 PM_PROFILE_DEFAULT,
1138 PM_PROFILE_AUTO,
1139 PM_PROFILE_LOW,
c9e75b21 1140 PM_PROFILE_MID,
ce8f5370
AD		 1141 PM_PROFILE_HIGH,
1142};
1143
1144#define PM_PROFILE_DEFAULT_IDX 0
1145#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1146#define PM_PROFILE_MID_SH_IDX 2
1147#define PM_PROFILE_HIGH_SH_IDX 3
1148#define PM_PROFILE_LOW_MH_IDX 4
1149#define PM_PROFILE_MID_MH_IDX 5
1150#define PM_PROFILE_HIGH_MH_IDX 6
1151#define PM_PROFILE_MAX 7
ce8f5370
AD		 1152
1153struct radeon_pm_profile {
1154 int dpms_off_ps_idx;
1155 int dpms_on_ps_idx;
1156 int dpms_off_cm_idx;
1157 int dpms_on_cm_idx;
516d0e46
AD		 1158};
1159
21a8122a
AD		 1160enum radeon_int_thermal_type {
1161 THERMAL_TYPE_NONE,
da321c8a
AD		 1162 THERMAL_TYPE_EXTERNAL,
1163 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1164 THERMAL_TYPE_RV6XX,
1165 THERMAL_TYPE_RV770,
da321c8a 1166 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1167 THERMAL_TYPE_EVERGREEN,
e33df25f 1168 THERMAL_TYPE_SUMO,
4fddba1f 1169 THERMAL_TYPE_NI,
14607d08 1170 THERMAL_TYPE_SI,
da321c8a 1171 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1172 THERMAL_TYPE_CI,
16fbe00d 1173 THERMAL_TYPE_KV,
21a8122a
AD		 1174};
1175
56278a8e
AD		 1176struct radeon_voltage {
1177 enum radeon_voltage_type type;
1178 /* gpio voltage */
1179 struct radeon_gpio_rec gpio;
1180 u32 delay; /* delay in usec from voltage drop to sclk change */
1181 bool active_high; /* voltage drop is active when bit is high */
1182 /* VDDC voltage */
1183 u8 vddc_id; /* index into vddc voltage table */
1184 u8 vddci_id; /* index into vddci voltage table */
1185 bool vddci_enabled;
1186 /* r6xx+ sw */
2feea49a
AD		 1187 u16 voltage;
1188 /* evergreen+ vddci */
1189 u16 vddci;
56278a8e
AD		 1190};
1191
d7311171
AD		 1192/* clock mode flags */
1193#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1194
56278a8e
AD		 1195struct radeon_pm_clock_info {
1196 /* memory clock */
1197 u32 mclk;
1198 /* engine clock */
1199 u32 sclk;
1200 /* voltage info */
1201 struct radeon_voltage voltage;
d7311171 1202 /* standardized clock flags */
56278a8e
AD		 1203 u32 flags;
1204};
1205
a48b9b4e 1206/* state flags */
d7311171 1207#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1208
56278a8e 1209struct radeon_power_state {
0ec0e74f 1210 enum radeon_pm_state_type type;
8f3f1c9a 1211 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1212 /* number of valid clock modes in this power state */
1213 int num_clock_modes;
56278a8e 1214 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1215 /* standardized state flags */
1216 u32 flags;
79daedc9
AD		 1217 u32 misc; /* vbios specific flags */
1218 u32 misc2; /* vbios specific flags */
1219 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1220};
1221
27459324
RM		 1222/*
1223 * Some modes are overclocked by very low value, accept them
1224 */
1225#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1226
2e9d4c05
AD		 1227enum radeon_dpm_auto_throttle_src {
1228 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1229 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1230};
1231
1232enum radeon_dpm_event_src {
1233 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1234 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1235 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1236 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1237 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1238};
1239
da321c8a
AD		 1240struct radeon_ps {
1241 u32 caps; /* vbios flags */
1242 u32 class; /* vbios flags */
1243 u32 class2; /* vbios flags */
1244 /* UVD clocks */
1245 u32 vclk;
1246 u32 dclk;
c4453e66
AD		 1247 /* VCE clocks */
1248 u32 evclk;
1249 u32 ecclk;
da321c8a
AD		 1250 /* asic priv */
1251 void *ps_priv;
1252};
1253
1254struct radeon_dpm_thermal {
1255 /* thermal interrupt work */
1256 struct work_struct work;
1257 /* low temperature threshold */
1258 int min_temp;
1259 /* high temperature threshold */
1260 int max_temp;
1261 /* was interrupt low to high or high to low */
1262 bool high_to_low;
1263};
1264
d22b7e40
AD		 1265enum radeon_clk_action
1266{
1267 RADEON_SCLK_UP = 1,
1268 RADEON_SCLK_DOWN
1269};
1270
1271struct radeon_blacklist_clocks
1272{
1273 u32 sclk;
1274 u32 mclk;
1275 enum radeon_clk_action action;
1276};
1277
61b7d601
AD		 1278struct radeon_clock_and_voltage_limits {
1279 u32 sclk;
1280 u32 mclk;
1281 u32 vddc;
1282 u32 vddci;
1283};
1284
1285struct radeon_clock_array {
1286 u32 count;
1287 u32 *values;
1288};
1289
1290struct radeon_clock_voltage_dependency_entry {
1291 u32 clk;
1292 u16 v;
1293};
1294
1295struct radeon_clock_voltage_dependency_table {
1296 u32 count;
1297 struct radeon_clock_voltage_dependency_entry *entries;
1298};
1299
ef976ec4
AD		 1300union radeon_cac_leakage_entry {
1301 struct {
1302 u16 vddc;
1303 u32 leakage;
1304 };
1305 struct {
1306 u16 vddc1;
1307 u16 vddc2;
1308 u16 vddc3;
1309 };
61b7d601
AD		 1310};
1311
1312struct radeon_cac_leakage_table {
1313 u32 count;
ef976ec4 1314 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1315};
1316
929ee7a8
AD		 1317struct radeon_phase_shedding_limits_entry {
1318 u16 voltage;
1319 u32 sclk;
1320 u32 mclk;
1321};
1322
1323struct radeon_phase_shedding_limits_table {
1324 u32 count;
1325 struct radeon_phase_shedding_limits_entry *entries;
1326};
1327
84a9d9ee
AD		 1328struct radeon_uvd_clock_voltage_dependency_entry {
1329 u32 vclk;
1330 u32 dclk;
1331 u16 v;
1332};
1333
1334struct radeon_uvd_clock_voltage_dependency_table {
1335 u8 count;
1336 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1337};
1338
d29f013b
AD		 1339struct radeon_vce_clock_voltage_dependency_entry {
1340 u32 ecclk;
1341 u32 evclk;
1342 u16 v;
1343};
1344
1345struct radeon_vce_clock_voltage_dependency_table {
1346 u8 count;
1347 struct radeon_vce_clock_voltage_dependency_entry *entries;
1348};
1349
a5cb318e
AD		 1350struct radeon_ppm_table {
1351 u8 ppm_design;
1352 u16 cpu_core_number;
1353 u32 platform_tdp;
1354 u32 small_ac_platform_tdp;
1355 u32 platform_tdc;
1356 u32 small_ac_platform_tdc;
1357 u32 apu_tdp;
1358 u32 dgpu_tdp;
1359 u32 dgpu_ulv_power;
1360 u32 tj_max;
1361};
1362
58cb7632
AD		 1363struct radeon_cac_tdp_table {
1364 u16 tdp;
1365 u16 configurable_tdp;
1366 u16 tdc;
1367 u16 battery_power_limit;
1368 u16 small_power_limit;
1369 u16 low_cac_leakage;
1370 u16 high_cac_leakage;
1371 u16 maximum_power_delivery_limit;
1372};
1373
61b7d601
AD		 1374struct radeon_dpm_dynamic_state {
1375 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1376 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1377 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1378 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1379 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1380 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1381 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1382 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1383 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1384 struct radeon_clock_array valid_sclk_values;
1385 struct radeon_clock_array valid_mclk_values;
1386 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1387 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1388 u32 mclk_sclk_ratio;
1389 u32 sclk_mclk_delta;
1390 u16 vddc_vddci_delta;
1391 u16 min_vddc_for_pcie_gen2;
1392 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1393 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1394 struct radeon_ppm_table *ppm_table;
58cb7632 1395 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1396};
1397
1398struct radeon_dpm_fan {
1399 u16 t_min;
1400 u16 t_med;
1401 u16 t_high;
1402 u16 pwm_min;
1403 u16 pwm_med;
1404 u16 pwm_high;
1405 u8 t_hyst;
1406 u32 cycle_delay;
1407 u16 t_max;
1408 bool ucode_fan_control;
1409};
1410
32ce4652
AD		 1411enum radeon_pcie_gen {
1412 RADEON_PCIE_GEN1 = 0,
1413 RADEON_PCIE_GEN2 = 1,
1414 RADEON_PCIE_GEN3 = 2,
1415 RADEON_PCIE_GEN_INVALID = 0xffff
1416};
1417
70d01a5e
AD		 1418enum radeon_dpm_forced_level {
1419 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1420 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1421 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1422};
1423
da321c8a
AD		 1424struct radeon_dpm {
1425 struct radeon_ps *ps;
1426 /* number of valid power states */
1427 int num_ps;
1428 /* current power state that is active */
1429 struct radeon_ps *current_ps;
1430 /* requested power state */
1431 struct radeon_ps *requested_ps;
1432 /* boot up power state */
1433 struct radeon_ps *boot_ps;
1434 /* default uvd power state */
1435 struct radeon_ps *uvd_ps;
1436 enum radeon_pm_state_type state;
1437 enum radeon_pm_state_type user_state;
1438 u32 platform_caps;
1439 u32 voltage_response_time;
1440 u32 backbias_response_time;
1441 void *priv;
1442 u32 new_active_crtcs;
1443 int new_active_crtc_count;
1444 u32 current_active_crtcs;
1445 int current_active_crtc_count;
61b7d601
AD		 1446 struct radeon_dpm_dynamic_state dyn_state;
1447 struct radeon_dpm_fan fan;
1448 u32 tdp_limit;
1449 u32 near_tdp_limit;
a9e61410 1450 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1451 u32 sq_ramping_threshold;
1452 u32 cac_leakage;
1453 u16 tdp_od_limit;
1454 u32 tdp_adjustment;
1455 u16 load_line_slope;
1456 bool power_control;
5ca302f7 1457 bool ac_power;
da321c8a
AD		 1458 /* special states active */
1459 bool thermal_active;
8a227555 1460 bool uvd_active;
da321c8a
AD		 1461 /* thermal handling */
1462 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1463 /* forced levels */
1464 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1465 /* track UVD streams */
1466 unsigned sd;
1467 unsigned hd;
da321c8a
AD		 1468};
1469
ce3537d5 1470void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
da321c8a 1471
c93bb85b 1472struct radeon_pm {
c913e23a 1473 struct mutex mutex;
db7fce39
CK		 1474 /* write locked while reprogramming mclk */
1475 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1476 u32 active_crtcs;
1477 int active_crtc_count;
c913e23a 1478 int req_vblank;
839461d3 1479 bool vblank_sync;
c93bb85b
JG		 1480 fixed20_12 max_bandwidth;
1481 fixed20_12 igp_sideport_mclk;
1482 fixed20_12 igp_system_mclk;
1483 fixed20_12 igp_ht_link_clk;
1484 fixed20_12 igp_ht_link_width;
1485 fixed20_12 k8_bandwidth;
1486 fixed20_12 sideport_bandwidth;
1487 fixed20_12 ht_bandwidth;
1488 fixed20_12 core_bandwidth;
1489 fixed20_12 sclk;
f47299c5 1490 fixed20_12 mclk;
c93bb85b 1491 fixed20_12 needed_bandwidth;
0975b162 1492 struct radeon_power_state *power_state;
56278a8e
AD		 1493 /* number of valid power states */
1494 int num_power_states;
a48b9b4e
AD		 1495 int current_power_state_index;
1496 int current_clock_mode_index;
1497 int requested_power_state_index;
1498 int requested_clock_mode_index;
1499 int default_power_state_index;
1500 u32 current_sclk;
1501 u32 current_mclk;
2feea49a
AD		 1502 u16 current_vddc;
1503 u16 current_vddci;
9ace9f7b
AD		 1504 u32 default_sclk;
1505 u32 default_mclk;
2feea49a
AD		 1506 u16 default_vddc;
1507 u16 default_vddci;
29fb52ca 1508 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1509 /* selected pm method */
1510 enum radeon_pm_method pm_method;
1511 /* dynpm power management */
1512 struct delayed_work dynpm_idle_work;
1513 enum radeon_dynpm_state dynpm_state;
1514 enum radeon_dynpm_action dynpm_planned_action;
1515 unsigned long dynpm_action_timeout;
1516 bool dynpm_can_upclock;
1517 bool dynpm_can_downclock;
1518 /* profile-based power management */
1519 enum radeon_pm_profile_type profile;
1520 int profile_index;
1521 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1522 /* internal thermal controller on rv6xx+ */
1523 enum radeon_int_thermal_type int_thermal_type;
1524 struct device *int_hwmon_dev;
da321c8a
AD		 1525 /* dpm */
1526 bool dpm_enabled;
1527 struct radeon_dpm dpm;
c93bb85b
JG		 1528};
1529
a4c9e2ee
AD		 1530int radeon_pm_get_type_index(struct radeon_device *rdev,
1531 enum radeon_pm_state_type ps_type,
1532 int instance);
f2ba57b5
CK		 1533/*
1534 * UVD
1535 */
1536#define RADEON_MAX_UVD_HANDLES 10
1537#define RADEON_UVD_STACK_SIZE (1024*1024)
1538#define RADEON_UVD_HEAP_SIZE (1024*1024)
1539
1540struct radeon_uvd {
1541 struct radeon_bo *vcpu_bo;
1542 void *cpu_addr;
1543 uint64_t gpu_addr;
9cc2e0e9 1544 void *saved_bo;
f2ba57b5
CK		 1545 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1546 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1547 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1548 struct delayed_work idle_work;
f2ba57b5
CK		 1549};
1550
1551int radeon_uvd_init(struct radeon_device *rdev);
1552void radeon_uvd_fini(struct radeon_device *rdev);
1553int radeon_uvd_suspend(struct radeon_device *rdev);
1554int radeon_uvd_resume(struct radeon_device *rdev);
1555int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1556 uint32_t handle, struct radeon_fence **fence);
1557int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1558 uint32_t handle, struct radeon_fence **fence);
1559void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1560void radeon_uvd_free_handles(struct radeon_device *rdev,
1561 struct drm_file *filp);
1562int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1563void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1564int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1565 unsigned vclk, unsigned dclk,
1566 unsigned vco_min, unsigned vco_max,
1567 unsigned fb_factor, unsigned fb_mask,
1568 unsigned pd_min, unsigned pd_max,
1569 unsigned pd_even,
1570 unsigned *optimal_fb_div,
1571 unsigned *optimal_vclk_div,
1572 unsigned *optimal_dclk_div);
1573int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1574 unsigned cg_upll_func_cntl);
771fe6b9 1575
b530602f 1576struct r600_audio_pin {
a92553ab
RM		 1577 int channels;
1578 int rate;
1579 int bits_per_sample;
1580 u8 status_bits;
1581 u8 category_code;
b530602f
AD		 1582 u32 offset;
1583 bool connected;
1584 u32 id;
1585};
1586
1587struct r600_audio {
1588 bool enabled;
1589 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1590 int num_pins;
a92553ab
RM		 1591};
1592
771fe6b9
JG		 1593/*
1594 * Benchmarking
1595 */
638dd7db 1596void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1597
1598
ecc0b326
MD		 1599/*
1600 * Testing
1601 */
1602void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1603void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1604 struct radeon_ring *cpA,
1605 struct radeon_ring *cpB);
60a7e396 1606void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326
MD		 1607
1608
771fe6b9
JG		 1609/*
1610 * Debugfs
1611 */
4d8bf9ae
CK		 1612struct radeon_debugfs {
1613 struct drm_info_list *files;
1614 unsigned num_files;
1615};
1616
771fe6b9
JG		 1617int radeon_debugfs_add_files(struct radeon_device *rdev,
1618 struct drm_info_list *files,
1619 unsigned nfiles);
1620int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1621
76a0df85
CK		 1622/*
1623 * ASIC ring specific functions.
1624 */
1625struct radeon_asic_ring {
1626 /* ring read/write ptr handling */
1627 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1628 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1629 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1630
1631 /* validating and patching of IBs */
1632 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1633 int (*cs_parse)(struct radeon_cs_parser *p);
1634
1635 /* command emmit functions */
1636 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1637 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1638 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1639 struct radeon_semaphore *semaphore, bool emit_wait);
1640 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1641
1642 /* testing functions */
1643 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1644 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1645 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1646
1647 /* deprecated */
1648 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1649};
771fe6b9
JG		 1650
1651/*
1652 * ASIC specific functions.
1653 */
1654struct radeon_asic {
068a117c 1655 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1656 void (*fini)(struct radeon_device *rdev);
1657 int (*resume)(struct radeon_device *rdev);
1658 int (*suspend)(struct radeon_device *rdev);
28d52043 1659 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1660 int (*asic_reset)(struct radeon_device *rdev);
54e88e06
AD		 1661 /* ioctl hw specific callback. Some hw might want to perform special
1662 * operation on specific ioctl. For instance on wait idle some hw
1663 * might want to perform and HDP flush through MMIO as it seems that
1664 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1665 * through ring.
1666 */
1667 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1668 /* check if 3D engine is idle */
1669 bool (*gui_idle)(struct radeon_device *rdev);
1670 /* wait for mc_idle */
1671 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1672 /* get the reference clock */
1673 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1674 /* get the gpu clock counter */
1675 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1676 /* gart */
c5b3b850
AD		 1677 struct {
1678 void (*tlb_flush)(struct radeon_device *rdev);
1679 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1680 } gart;
05b07147
CK		 1681 struct {
1682 int (*init)(struct radeon_device *rdev);
1683 void (*fini)(struct radeon_device *rdev);
43f1214a
AD		 1684 void (*set_page)(struct radeon_device *rdev,
1685 struct radeon_ib *ib,
1686 uint64_t pe,
dce34bfd
CK		 1687 uint64_t addr, unsigned count,
1688 uint32_t incr, uint32_t flags);
05b07147 1689 } vm;
54e88e06 1690 /* ring specific callbacks */
76a0df85 1691 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1692 /* irqs */
b35ea4ab
AD		 1693 struct {
1694 int (*set)(struct radeon_device *rdev);
1695 int (*process)(struct radeon_device *rdev);
1696 } irq;
54e88e06 1697 /* displays */
c79a49ca
AD		 1698 struct {
1699 /* display watermarks */
1700 void (*bandwidth_update)(struct radeon_device *rdev);
1701 /* get frame count */
1702 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1703 /* wait for vblank */
1704 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1705 /* set backlight level */
1706 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1707 /* get backlight level */
1708 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1709 /* audio callbacks */
1710 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1711 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1712 } display;
54e88e06 1713 /* copy functions for bo handling */
27cd7769
AD		 1714 struct {
1715 int (*blit)(struct radeon_device *rdev,
1716 uint64_t src_offset,
1717 uint64_t dst_offset,
1718 unsigned num_gpu_pages,
876dc9f3 1719 struct radeon_fence **fence);
27cd7769
AD		 1720 u32 blit_ring_index;
1721 int (*dma)(struct radeon_device *rdev,
1722 uint64_t src_offset,
1723 uint64_t dst_offset,
1724 unsigned num_gpu_pages,
876dc9f3 1725 struct radeon_fence **fence);
27cd7769
AD		 1726 u32 dma_ring_index;
1727 /* method used for bo copy */
1728 int (*copy)(struct radeon_device *rdev,
1729 uint64_t src_offset,
1730 uint64_t dst_offset,
1731 unsigned num_gpu_pages,
876dc9f3 1732 struct radeon_fence **fence);
27cd7769
AD		 1733 /* ring used for bo copies */
1734 u32 copy_ring_index;
1735 } copy;
54e88e06 1736 /* surfaces */
9e6f3d02
AD		 1737 struct {
1738 int (*set_reg)(struct radeon_device *rdev, int reg,
1739 uint32_t tiling_flags, uint32_t pitch,
1740 uint32_t offset, uint32_t obj_size);
1741 void (*clear_reg)(struct radeon_device *rdev, int reg);
1742 } surface;
54e88e06 1743 /* hotplug detect */
901ea57d
AD		 1744 struct {
1745 void (*init)(struct radeon_device *rdev);
1746 void (*fini)(struct radeon_device *rdev);
1747 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1748 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1749 } hpd;
da321c8a 1750 /* static power management */
a02fa397
AD		 1751 struct {
1752 void (*misc)(struct radeon_device *rdev);
1753 void (*prepare)(struct radeon_device *rdev);
1754 void (*finish)(struct radeon_device *rdev);
1755 void (*init_profile)(struct radeon_device *rdev);
1756 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1757 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1758 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1759 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1760 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1761 int (*get_pcie_lanes)(struct radeon_device *rdev);
1762 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1763 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1764 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
6bd1c385 1765 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1766 } pm;
da321c8a
AD		 1767 /* dynamic power management */
1768 struct {
1769 int (*init)(struct radeon_device *rdev);
1770 void (*setup_asic)(struct radeon_device *rdev);
1771 int (*enable)(struct radeon_device *rdev);
1772 void (*disable)(struct radeon_device *rdev);
84dd1928 1773 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1774 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1775 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1776 void (*display_configuration_changed)(struct radeon_device *rdev);
1777 void (*fini)(struct radeon_device *rdev);
1778 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1779 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1780 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1781 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1782 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1783 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1784 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1c71bda0 1785 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
da321c8a 1786 } dpm;
6f34be50 1787 /* pageflipping */
0f9e006c
AD		 1788 struct {
1789 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1790 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1791 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1792 } pflip;
771fe6b9
JG		 1793};
1794
21f9a437
JG		 1795/*
1796 * Asic structures
1797 */
551ebd83 1798struct r100_asic {
225758d8
JG		 1799 const unsigned *reg_safe_bm;
1800 unsigned reg_safe_bm_size;
1801 u32 hdp_cntl;
551ebd83
DA		 1802};
1803
21f9a437 1804struct r300_asic {
225758d8
JG		 1805 const unsigned *reg_safe_bm;
1806 unsigned reg_safe_bm_size;
1807 u32 resync_scratch;
1808 u32 hdp_cntl;
21f9a437
JG		 1809};
1810
1811struct r600_asic {
225758d8
JG		 1812 unsigned max_pipes;
1813 unsigned max_tile_pipes;
1814 unsigned max_simds;
1815 unsigned max_backends;
1816 unsigned max_gprs;
1817 unsigned max_threads;
1818 unsigned max_stack_entries;
1819 unsigned max_hw_contexts;
1820 unsigned max_gs_threads;
1821 unsigned sx_max_export_size;
1822 unsigned sx_max_export_pos_size;
1823 unsigned sx_max_export_smx_size;
1824 unsigned sq_num_cf_insts;
1825 unsigned tiling_nbanks;
1826 unsigned tiling_npipes;
1827 unsigned tiling_group_size;
e7aeeba6 1828 unsigned tile_config;
e55b9422 1829 unsigned backend_map;
21f9a437
JG		 1830};
1831
1832struct rv770_asic {
225758d8
JG		 1833 unsigned max_pipes;
1834 unsigned max_tile_pipes;
1835 unsigned max_simds;
1836 unsigned max_backends;
1837 unsigned max_gprs;
1838 unsigned max_threads;
1839 unsigned max_stack_entries;
1840 unsigned max_hw_contexts;
1841 unsigned max_gs_threads;
1842 unsigned sx_max_export_size;
1843 unsigned sx_max_export_pos_size;
1844 unsigned sx_max_export_smx_size;
1845 unsigned sq_num_cf_insts;
1846 unsigned sx_num_of_sets;
1847 unsigned sc_prim_fifo_size;
1848 unsigned sc_hiz_tile_fifo_size;
1849 unsigned sc_earlyz_tile_fifo_fize;
1850 unsigned tiling_nbanks;
1851 unsigned tiling_npipes;
1852 unsigned tiling_group_size;
e7aeeba6 1853 unsigned tile_config;
e55b9422 1854 unsigned backend_map;
21f9a437
JG		 1855};
1856
32fcdbf4
AD		 1857struct evergreen_asic {
1858 unsigned num_ses;
1859 unsigned max_pipes;
1860 unsigned max_tile_pipes;
1861 unsigned max_simds;
1862 unsigned max_backends;
1863 unsigned max_gprs;
1864 unsigned max_threads;
1865 unsigned max_stack_entries;
1866 unsigned max_hw_contexts;
1867 unsigned max_gs_threads;
1868 unsigned sx_max_export_size;
1869 unsigned sx_max_export_pos_size;
1870 unsigned sx_max_export_smx_size;
1871 unsigned sq_num_cf_insts;
1872 unsigned sx_num_of_sets;
1873 unsigned sc_prim_fifo_size;
1874 unsigned sc_hiz_tile_fifo_size;
1875 unsigned sc_earlyz_tile_fifo_size;
1876 unsigned tiling_nbanks;
1877 unsigned tiling_npipes;
1878 unsigned tiling_group_size;
e7aeeba6 1879 unsigned tile_config;
e55b9422 1880 unsigned backend_map;
32fcdbf4
AD		 1881};
1882
fecf1d07
AD		 1883struct cayman_asic {
1884 unsigned max_shader_engines;
1885 unsigned max_pipes_per_simd;
1886 unsigned max_tile_pipes;
1887 unsigned max_simds_per_se;
1888 unsigned max_backends_per_se;
1889 unsigned max_texture_channel_caches;
1890 unsigned max_gprs;
1891 unsigned max_threads;
1892 unsigned max_gs_threads;
1893 unsigned max_stack_entries;
1894 unsigned sx_num_of_sets;
1895 unsigned sx_max_export_size;
1896 unsigned sx_max_export_pos_size;
1897 unsigned sx_max_export_smx_size;
1898 unsigned max_hw_contexts;
1899 unsigned sq_num_cf_insts;
1900 unsigned sc_prim_fifo_size;
1901 unsigned sc_hiz_tile_fifo_size;
1902 unsigned sc_earlyz_tile_fifo_size;
1903
1904 unsigned num_shader_engines;
1905 unsigned num_shader_pipes_per_simd;
1906 unsigned num_tile_pipes;
1907 unsigned num_simds_per_se;
1908 unsigned num_backends_per_se;
1909 unsigned backend_disable_mask_per_asic;
1910 unsigned backend_map;
1911 unsigned num_texture_channel_caches;
1912 unsigned mem_max_burst_length_bytes;
1913 unsigned mem_row_size_in_kb;
1914 unsigned shader_engine_tile_size;
1915 unsigned num_gpus;
1916 unsigned multi_gpu_tile_size;
1917
1918 unsigned tile_config;
fecf1d07
AD		 1919};
1920
0a96d72b
AD		 1921struct si_asic {
1922 unsigned max_shader_engines;
0a96d72b 1923 unsigned max_tile_pipes;
1a8ca750
AD		 1924 unsigned max_cu_per_sh;
1925 unsigned max_sh_per_se;
0a96d72b
AD		 1926 unsigned max_backends_per_se;
1927 unsigned max_texture_channel_caches;
1928 unsigned max_gprs;
1929 unsigned max_gs_threads;
1930 unsigned max_hw_contexts;
1931 unsigned sc_prim_fifo_size_frontend;
1932 unsigned sc_prim_fifo_size_backend;
1933 unsigned sc_hiz_tile_fifo_size;
1934 unsigned sc_earlyz_tile_fifo_size;
1935
0a96d72b
AD		 1936 unsigned num_tile_pipes;
1937 unsigned num_backends_per_se;
1938 unsigned backend_disable_mask_per_asic;
1939 unsigned backend_map;
1940 unsigned num_texture_channel_caches;
1941 unsigned mem_max_burst_length_bytes;
1942 unsigned mem_row_size_in_kb;
1943 unsigned shader_engine_tile_size;
1944 unsigned num_gpus;
1945 unsigned multi_gpu_tile_size;
1946
1947 unsigned tile_config;
64d7b8be 1948 uint32_t tile_mode_array[32];
0a96d72b
AD		 1949};
1950
8cc1a532
AD		 1951struct cik_asic {
1952 unsigned max_shader_engines;
1953 unsigned max_tile_pipes;
1954 unsigned max_cu_per_sh;
1955 unsigned max_sh_per_se;
1956 unsigned max_backends_per_se;
1957 unsigned max_texture_channel_caches;
1958 unsigned max_gprs;
1959 unsigned max_gs_threads;
1960 unsigned max_hw_contexts;
1961 unsigned sc_prim_fifo_size_frontend;
1962 unsigned sc_prim_fifo_size_backend;
1963 unsigned sc_hiz_tile_fifo_size;
1964 unsigned sc_earlyz_tile_fifo_size;
1965
1966 unsigned num_tile_pipes;
1967 unsigned num_backends_per_se;
1968 unsigned backend_disable_mask_per_asic;
1969 unsigned backend_map;
1970 unsigned num_texture_channel_caches;
1971 unsigned mem_max_burst_length_bytes;
1972 unsigned mem_row_size_in_kb;
1973 unsigned shader_engine_tile_size;
1974 unsigned num_gpus;
1975 unsigned multi_gpu_tile_size;
1976
1977 unsigned tile_config;
39aee490 1978 uint32_t tile_mode_array[32];
8cc1a532
AD		 1979};
1980
068a117c
JG		 1981union radeon_asic_config {
1982 struct r300_asic r300;
551ebd83 1983 struct r100_asic r100;
3ce0a23d
JG		 1984 struct r600_asic r600;
1985 struct rv770_asic rv770;
32fcdbf4 1986 struct evergreen_asic evergreen;
fecf1d07 1987 struct cayman_asic cayman;
0a96d72b 1988 struct si_asic si;
8cc1a532 1989 struct cik_asic cik;
068a117c
JG		 1990};
1991
0a10c851
DV		 1992/*
1993 * asic initizalization from radeon_asic.c
1994 */
1995void radeon_agp_disable(struct radeon_device *rdev);
1996int radeon_asic_init(struct radeon_device *rdev);
1997
771fe6b9
JG		 1998
1999/*
2000 * IOCTL.
2001 */
2002int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2003 struct drm_file *filp);
2004int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2005 struct drm_file *filp);
2006int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2007 struct drm_file *file_priv);
2008int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2009 struct drm_file *file_priv);
2010int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2011 struct drm_file *file_priv);
2012int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2013 struct drm_file *file_priv);
2014int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2015 struct drm_file *filp);
2016int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2017 struct drm_file *filp);
2018int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2019 struct drm_file *filp);
2020int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2021 struct drm_file *filp);
721604a1
JG		 2022int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2023 struct drm_file *filp);
771fe6b9 2024int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 2025int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2026 struct drm_file *filp);
2027int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2028 struct drm_file *filp);
771fe6b9 2029
16cdf04d
AD		 2030/* VRAM scratch page for HDP bug, default vram page */
2031struct r600_vram_scratch {
87cbf8f2
AD		 2032 struct radeon_bo *robj;
2033 volatile uint32_t *ptr;
16cdf04d 2034 u64 gpu_addr;
87cbf8f2 2035};
771fe6b9 2036
fd64ca8a
LT		 2037/*
2038 * ACPI
2039 */
2040struct radeon_atif_notification_cfg {
2041 bool enabled;
2042 int command_code;
2043};
2044
2045struct radeon_atif_notifications {
2046 bool display_switch;
2047 bool expansion_mode_change;
2048 bool thermal_state;
2049 bool forced_power_state;
2050 bool system_power_state;
2051 bool display_conf_change;
2052 bool px_gfx_switch;
2053 bool brightness_change;
2054 bool dgpu_display_event;
2055};
2056
2057struct radeon_atif_functions {
2058 bool system_params;
2059 bool sbios_requests;
2060 bool select_active_disp;
2061 bool lid_state;
2062 bool get_tv_standard;
2063 bool set_tv_standard;
2064 bool get_panel_expansion_mode;
2065 bool set_panel_expansion_mode;
2066 bool temperature_change;
2067 bool graphics_device_types;
2068};
2069
2070struct radeon_atif {
2071 struct radeon_atif_notifications notifications;
2072 struct radeon_atif_functions functions;
2073 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2074 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2075};
7a1619b9 2076
e3a15920
AD		 2077struct radeon_atcs_functions {
2078 bool get_ext_state;
2079 bool pcie_perf_req;
2080 bool pcie_dev_rdy;
2081 bool pcie_bus_width;
2082};
2083
2084struct radeon_atcs {
2085 struct radeon_atcs_functions functions;
2086};
2087
771fe6b9
JG		 2088/*
2089 * Core structure, functions and helpers.
2090 */
2091typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2092typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2093
2094struct radeon_device {
9f022ddf 2095 struct device *dev;
771fe6b9
JG		 2096 struct drm_device *ddev;
2097 struct pci_dev *pdev;
dee53e7f 2098 struct rw_semaphore exclusive_lock;
771fe6b9 2099 /* ASIC */
068a117c 2100 union radeon_asic_config config;
771fe6b9
JG		 2101 enum radeon_family family;
2102 unsigned long flags;
2103 int usec_timeout;
2104 enum radeon_pll_errata pll_errata;
2105 int num_gb_pipes;
f779b3e5 2106 int num_z_pipes;
771fe6b9
JG		 2107 int disp_priority;
2108 /* BIOS */
2109 uint8_t *bios;
2110 bool is_atom_bios;
2111 uint16_t bios_header_start;
4c788679 2112 struct radeon_bo *stollen_vga_memory;
771fe6b9 2113 /* Register mmio */
4c9bc75c
DA		 2114 resource_size_t rmmio_base;
2115 resource_size_t rmmio_size;
2c385151
DV		 2116 /* protects concurrent MM_INDEX/DATA based register access */
2117 spinlock_t mmio_idx_lock;
fe78118c
AD		 2118 /* protects concurrent SMC based register access */
2119 spinlock_t smc_idx_lock;
0a5b7b0b
AD		 2120 /* protects concurrent PLL register access */
2121 spinlock_t pll_idx_lock;
2122 /* protects concurrent MC register access */
2123 spinlock_t mc_idx_lock;
2124 /* protects concurrent PCIE register access */
2125 spinlock_t pcie_idx_lock;
2126 /* protects concurrent PCIE_PORT register access */
2127 spinlock_t pciep_idx_lock;
2128 /* protects concurrent PIF register access */
2129 spinlock_t pif_idx_lock;
2130 /* protects concurrent CG register access */
2131 spinlock_t cg_idx_lock;
2132 /* protects concurrent UVD register access */
2133 spinlock_t uvd_idx_lock;
2134 /* protects concurrent RCU register access */
2135 spinlock_t rcu_idx_lock;
2136 /* protects concurrent DIDT register access */
2137 spinlock_t didt_idx_lock;
2138 /* protects concurrent ENDPOINT (audio) register access */
2139 spinlock_t end_idx_lock;
a0533fbf 2140 void __iomem *rmmio;
771fe6b9
JG		 2141 radeon_rreg_t mc_rreg;
2142 radeon_wreg_t mc_wreg;
2143 radeon_rreg_t pll_rreg;
2144 radeon_wreg_t pll_wreg;
de1b2898 2145 uint32_t pcie_reg_mask;
771fe6b9
JG		 2146 radeon_rreg_t pciep_rreg;
2147 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2148 /* io port */
2149 void __iomem *rio_mem;
2150 resource_size_t rio_mem_size;
771fe6b9
JG		 2151 struct radeon_clock clock;
2152 struct radeon_mc mc;
2153 struct radeon_gart gart;
2154 struct radeon_mode_info mode_info;
2155 struct radeon_scratch scratch;
75efdee1 2156 struct radeon_doorbell doorbell;
771fe6b9 2157 struct radeon_mman mman;
7465280c 2158 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2159 wait_queue_head_t fence_queue;
d6999bc7 2160 struct mutex ring_lock;
e32eb50d 2161 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2162 bool ib_pool_ready;
2163 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2164 struct radeon_irq irq;
2165 struct radeon_asic *asic;
2166 struct radeon_gem gem;
c93bb85b 2167 struct radeon_pm pm;
f2ba57b5 2168 struct radeon_uvd uvd;
f657c2a7 2169 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2170 struct radeon_wb wb;
3ce0a23d 2171 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2172 bool shutdown;
2173 bool suspend;
ad49f501 2174 bool need_dma32;
733289c2 2175 bool accel_working;
a0a53aa8 2176 bool fastfb_working; /* IGP feature*/
f9eaf9ae 2177 bool needs_reset;
e024e110 2178 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2179 const struct firmware *me_fw; /* all family ME firmware */
2180 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2181 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2182 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2183 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2184 const struct firmware *mec_fw; /* CIK MEC firmware */
21a93e13 2185 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2186 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2187 const struct firmware *uvd_fw; /* UVD firmware */
16cdf04d 2188 struct r600_vram_scratch vram_scratch;
3e5cb98d 2189 int msi_enabled; /* msi enabled */
d8f60cfc 2190 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2191 struct radeon_rlc rlc;
963e81f9 2192 struct radeon_mec mec;
d4877cf2 2193 struct work_struct hotplug_work;
f122c610 2194 struct work_struct audio_work;
8f61b34c 2195 struct work_struct reset_work;
18917b60 2196 int num_crtc; /* number of crtcs */
40bacf16 2197 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
948bee3f 2198 bool has_uvd;
b530602f 2199 struct r600_audio audio; /* audio stuff */
ce8f5370 2200 struct notifier_block acpi_nb;
9eba4a93 2201 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2202 struct drm_file *hyperz_filp;
9eba4a93 2203 struct drm_file *cmask_filp;
f376b94f
AD		 2204 /* i2c buses */
2205 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2206 /* debugfs */
2207 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2208 unsigned debugfs_count;
721604a1
JG		 2209 /* virtual memory */
2210 struct radeon_vm_manager vm_manager;
6759a0a7 2211 struct mutex gpu_clock_mutex;
fd64ca8a
LT		 2212 /* ACPI interface */
2213 struct radeon_atif atif;
e3a15920 2214 struct radeon_atcs atcs;
f61d5b46
AD		 2215 /* srbm instance registers */
2216 struct mutex srbm_mutex;
64d8a728
AD		 2217 /* clock, powergating flags */
2218 u32 cg_flags;
2219 u32 pg_flags;
10ebc0bc
DA		 2220
2221 struct dev_pm_domain vga_pm_domain;
2222 bool have_disp_power_ref;
771fe6b9
JG		 2223};
2224
2225int radeon_device_init(struct radeon_device *rdev,
2226 struct drm_device *ddev,
2227 struct pci_dev *pdev,
2228 uint32_t flags);
2229void radeon_device_fini(struct radeon_device *rdev);
2230int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2231
2ef9bdfe
DV		 2232uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2233 bool always_indirect);
2234void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2235 bool always_indirect);
6fcbef7a
AK		 2236u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2237void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2238
75efdee1
AD		 2239u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset);
2240void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
2241
4c788679
JG		 2242/*
2243 * Cast helper
2244 */
2245#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 2246
2247/*
2248 * Registers read & write functions.
2249 */
a0533fbf
BH		 2250#define RREG8(reg) readb((rdev->rmmio) + (reg))
2251#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2252#define RREG16(reg) readw((rdev->rmmio) + (reg))
2253#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2254#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2255#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2256#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2257#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2258#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2259#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2260#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2261#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2262#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2263#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2264#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2265#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2266#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2267#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2268#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2269#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2270#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2271#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2272#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2273#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2274#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2275#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2276#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2277#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2278#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2279#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2280#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2281#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2282#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2283#define WREG32_P(reg, val, mask) \
2284 do { \
2285 uint32_t tmp_ = RREG32(reg); \
2286 tmp_ &= (mask); \
2287 tmp_ |= ((val) & ~(mask)); \
2288 WREG32(reg, tmp_); \
2289 } while (0)
d5169fc4 2290#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2291#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2292#define WREG32_PLL_P(reg, val, mask) \
2293 do { \
2294 uint32_t tmp_ = RREG32_PLL(reg); \
2295 tmp_ &= (mask); \
2296 tmp_ |= ((val) & ~(mask)); \
2297 WREG32_PLL(reg, tmp_); \
2298 } while (0)
2ef9bdfe 2299#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2300#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2301#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2302
75efdee1
AD		 2303#define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset))
2304#define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v))
2305
de1b2898
DA		 2306/*
2307 * Indirect registers accessor
2308 */
2309static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2310{
0a5b7b0b 2311 unsigned long flags;
de1b2898
DA		 2312 uint32_t r;
2313
0a5b7b0b 2314 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2315 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2316 r = RREG32(RADEON_PCIE_DATA);
0a5b7b0b 2317 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2318 return r;
2319}
2320
2321static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2322{
0a5b7b0b
AD		 2323 unsigned long flags;
2324
2325 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2326 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2327 WREG32(RADEON_PCIE_DATA, (v));
0a5b7b0b 2328 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2329}
2330
1d5d0c34
AD		 2331static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2332{
fe78118c 2333 unsigned long flags;
1d5d0c34
AD		 2334 u32 r;
2335
fe78118c 2336 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2337 WREG32(TN_SMC_IND_INDEX_0, (reg));
2338 r = RREG32(TN_SMC_IND_DATA_0);
fe78118c 2339 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2340 return r;
2341}
2342
2343static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2344{
fe78118c
AD		 2345 unsigned long flags;
2346
2347 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2348 WREG32(TN_SMC_IND_INDEX_0, (reg));
2349 WREG32(TN_SMC_IND_DATA_0, (v));
fe78118c 2350 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2351}
2352
ff82bbc4
AD		 2353static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2354{
0a5b7b0b 2355 unsigned long flags;
ff82bbc4
AD		 2356 u32 r;
2357
0a5b7b0b 2358 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2359 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2360 r = RREG32(R600_RCU_DATA);
0a5b7b0b 2361 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2362 return r;
2363}
2364
2365static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2366{
0a5b7b0b
AD		 2367 unsigned long flags;
2368
2369 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2370 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2371 WREG32(R600_RCU_DATA, (v));
0a5b7b0b 2372 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2373}
2374
46f9564a
AD		 2375static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2376{
0a5b7b0b 2377 unsigned long flags;
46f9564a
AD		 2378 u32 r;
2379
0a5b7b0b 2380 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2381 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2382 r = RREG32(EVERGREEN_CG_IND_DATA);
0a5b7b0b 2383 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2384 return r;
2385}
2386
2387static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2388{
0a5b7b0b
AD		 2389 unsigned long flags;
2390
2391 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2392 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2393 WREG32(EVERGREEN_CG_IND_DATA, (v));
0a5b7b0b 2394 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2395}
2396
792edd69
AD		 2397static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2398{
0a5b7b0b 2399 unsigned long flags;
792edd69
AD		 2400 u32 r;
2401
0a5b7b0b 2402 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2403 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2404 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
0a5b7b0b 2405 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2406 return r;
2407}
2408
2409static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2410{
0a5b7b0b
AD		 2411 unsigned long flags;
2412
2413 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2414 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2415 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
0a5b7b0b 2416 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2417}
2418
2419static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2420{
0a5b7b0b 2421 unsigned long flags;
792edd69
AD		 2422 u32 r;
2423
0a5b7b0b 2424 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2425 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2426 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
0a5b7b0b 2427 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2428 return r;
2429}
2430
2431static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2432{
0a5b7b0b
AD		 2433 unsigned long flags;
2434
2435 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2436 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2437 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
0a5b7b0b 2438 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2439}
2440
93656cdd
AD		 2441static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2442{
0a5b7b0b 2443 unsigned long flags;
93656cdd
AD		 2444 u32 r;
2445
0a5b7b0b 2446 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2447 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2448 r = RREG32(R600_UVD_CTX_DATA);
0a5b7b0b 2449 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2450 return r;
2451}
2452
2453static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2454{
0a5b7b0b
AD		 2455 unsigned long flags;
2456
2457 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2458 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2459 WREG32(R600_UVD_CTX_DATA, (v));
0a5b7b0b 2460 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2461}
2462
1d58234d
AD		 2463
2464static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2465{
0a5b7b0b 2466 unsigned long flags;
1d58234d
AD		 2467 u32 r;
2468
0a5b7b0b 2469 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2470 WREG32(CIK_DIDT_IND_INDEX, (reg));
2471 r = RREG32(CIK_DIDT_IND_DATA);
0a5b7b0b 2472 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2473 return r;
2474}
2475
2476static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2477{
0a5b7b0b
AD		 2478 unsigned long flags;
2479
2480 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2481 WREG32(CIK_DIDT_IND_INDEX, (reg));
2482 WREG32(CIK_DIDT_IND_DATA, (v));
0a5b7b0b 2483 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2484}
2485
771fe6b9
JG		 2486void r100_pll_errata_after_index(struct radeon_device *rdev);
2487
2488
2489/*
2490 * ASICs helpers.
2491 */
b995e433
DA		 2492#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2493 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2494#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2495 (rdev->family == CHIP_RV200) || \
2496 (rdev->family == CHIP_RS100) || \
2497 (rdev->family == CHIP_RS200) || \
2498 (rdev->family == CHIP_RV250) || \
2499 (rdev->family == CHIP_RV280) || \
2500 (rdev->family == CHIP_RS300))
2501#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2502 (rdev->family == CHIP_RV350) || \
2503 (rdev->family == CHIP_R350) || \
2504 (rdev->family == CHIP_RV380) || \
2505 (rdev->family == CHIP_R420) || \
2506 (rdev->family == CHIP_R423) || \
2507 (rdev->family == CHIP_RV410) || \
2508 (rdev->family == CHIP_RS400) || \
2509 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2510#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2511 (rdev->ddev->pdev->device == 0x9443) || \
2512 (rdev->ddev->pdev->device == 0x944B) || \
2513 (rdev->ddev->pdev->device == 0x9506) || \
2514 (rdev->ddev->pdev->device == 0x9509) || \
2515 (rdev->ddev->pdev->device == 0x950F) || \
2516 (rdev->ddev->pdev->device == 0x689C) || \
2517 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2518#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2519#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2520 (rdev->family == CHIP_RS690) || \
2521 (rdev->family == CHIP_RS740) || \
2522 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2523#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2524#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2525#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2526#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2527 (rdev->flags & RADEON_IS_IGP))
1fe18305 2528#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2529#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2530#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2531 (rdev->flags & RADEON_IS_IGP))
624d3524 2532#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2533#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2534#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
771fe6b9 2535
dc50ba7f
AD		 2536#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2537 (rdev->ddev->pdev->device == 0x6850) || \
2538 (rdev->ddev->pdev->device == 0x6858) || \
2539 (rdev->ddev->pdev->device == 0x6859) || \
2540 (rdev->ddev->pdev->device == 0x6840) || \
2541 (rdev->ddev->pdev->device == 0x6841) || \
2542 (rdev->ddev->pdev->device == 0x6842) || \
2543 (rdev->ddev->pdev->device == 0x6843))
2544
771fe6b9
JG		 2545/*
2546 * BIOS helpers.
2547 */
2548#define RBIOS8(i) (rdev->bios[i])
2549#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2550#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2551
2552int radeon_combios_init(struct radeon_device *rdev);
2553void radeon_combios_fini(struct radeon_device *rdev);
2554int radeon_atombios_init(struct radeon_device *rdev);
2555void radeon_atombios_fini(struct radeon_device *rdev);
2556
2557
2558/*
2559 * RING helpers.
2560 */
ce580fab 2561#if DRM_DEBUG_CODE == 0
e32eb50d 2562static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2563{
e32eb50d
CK		 2564 ring->ring[ring->wptr++] = v;
2565 ring->wptr &= ring->ptr_mask;
2566 ring->count_dw--;
2567 ring->ring_free_dw--;
771fe6b9 2568}
ce580fab
AK		 2569#else
2570/* With debugging this is just too big to inline */
e32eb50d 2571void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
ce580fab 2572#endif
771fe6b9
JG		 2573
2574/*
2575 * ASICs macro.
2576 */
068a117c 2577#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2578#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2579#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2580#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2581#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2582#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2583#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850
AD		 2584#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2585#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
05b07147
CK		 2586#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2587#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
43f1214a 2588#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
76a0df85
CK		 2589#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2590#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2591#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2592#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2593#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2594#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2595#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2596#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2597#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2598#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2599#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2600#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2601#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2602#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2603#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2604#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2605#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2606#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2607#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
27cd7769
AD		 2608#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2609#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2610#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2611#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2612#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2613#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2614#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2615#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2616#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2617#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2618#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2619#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2620#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2621#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
6bd1c385 2622#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2623#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2624#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2625#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2626#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2627#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2628#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2629#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2630#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2631#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2632#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2633#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2634#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2635#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8
AD		 2636#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2637#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2638#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2639#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2640#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2641#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2642#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2643#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2644#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2645#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2646#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2647#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2648#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2649#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2650#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2651#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2652#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2653#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2654#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2655#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2656#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2657#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2658#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
1c71bda0 2659#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
771fe6b9 2660
6cf8a3f5 2661/* Common functions */
700a0cc0 2662/* AGP */
90aca4d2 2663extern int radeon_gpu_reset(struct radeon_device *rdev);
410a3418 2664extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2665extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2666extern int radeon_modeset_init(struct radeon_device *rdev);
2667extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2668extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2669extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2670extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2671extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2672extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2673extern void radeon_wb_fini(struct radeon_device *rdev);
2674extern int radeon_wb_init(struct radeon_device *rdev);
2675extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2676extern void radeon_surface_init(struct radeon_device *rdev);
2677extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2678extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2679extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2680extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2681extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 2682extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2683extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
10ebc0bc
DA		 2684extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2685extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
53595338 2686extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2687extern void radeon_program_register_sequence(struct radeon_device *rdev,
2688 const u32 *registers,
2689 const u32 array_size);
6cf8a3f5 2690
721604a1
JG		 2691/*
2692 * vm
2693 */
2694int radeon_vm_manager_init(struct radeon_device *rdev);
2695void radeon_vm_manager_fini(struct radeon_device *rdev);
d72d43cf 2696void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2697void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
ddf03f5c 2698int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
13e55c38 2699void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
ee60e29f
CK		 2700struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2701 struct radeon_vm *vm, int ring);
2702void radeon_vm_fence(struct radeon_device *rdev,
2703 struct radeon_vm *vm,
2704 struct radeon_fence *fence);
dce34bfd 2705uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
721604a1
JG		 2706int radeon_vm_bo_update_pte(struct radeon_device *rdev,
2707 struct radeon_vm *vm,
2708 struct radeon_bo *bo,
2709 struct ttm_mem_reg *mem);
2710void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2711 struct radeon_bo *bo);
421ca7ab
CK		 2712struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2713 struct radeon_bo *bo);
e971bd5e
CK		 2714struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2715 struct radeon_vm *vm,
2716 struct radeon_bo *bo);
2717int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2718 struct radeon_bo_va *bo_va,
2719 uint64_t offset,
2720 uint32_t flags);
721604a1 2721int radeon_vm_bo_rmv(struct radeon_device *rdev,
e971bd5e 2722 struct radeon_bo_va *bo_va);
721604a1 2723
f122c610
AD		 2724/* audio */
2725void r600_audio_update_hdmi(struct work_struct *work);
b530602f
AD		 2726struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2727struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
721604a1 2728
16cdf04d
AD		 2729/*
2730 * R600 vram scratch functions
2731 */
2732int r600_vram_scratch_init(struct radeon_device *rdev);
2733void r600_vram_scratch_fini(struct radeon_device *rdev);
2734
285484e2
JG		 2735/*
2736 * r600 cs checking helper
2737 */
2738unsigned r600_mip_minify(unsigned size, unsigned level);
2739bool r600_fmt_is_valid_color(u32 format);
2740bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2741int r600_fmt_get_blocksize(u32 format);
2742int r600_fmt_get_nblocksx(u32 format, u32 w);
2743int r600_fmt_get_nblocksy(u32 format, u32 h);
2744
3574dda4
DV		 2745/*
2746 * r600 functions used by radeon_encoder.c
2747 */
1b688d08
RM		 2748struct radeon_hdmi_acr {
2749 u32 clock;
2750
2751 int n_32khz;
2752 int cts_32khz;
2753
2754 int n_44_1khz;
2755 int cts_44_1khz;
2756
2757 int n_48khz;
2758 int cts_48khz;
2759
2760};
2761
e55d3e6c
RM		 2762extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2763
416a2bd2
AD		 2764extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2765 u32 tiling_pipe_num,
2766 u32 max_rb_num,
2767 u32 total_max_rb_num,
2768 u32 enabled_rb_mask);
fe251e2f 2769
e55d3e6c
RM		 2770/*
2771 * evergreen functions used by radeon_encoder.c
2772 */
2773
0af62b01 2774extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2775extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2776
c4917074
AD		 2777/* radeon_acpi.c */
2778#if defined(CONFIG_ACPI)
2779extern int radeon_acpi_init(struct radeon_device *rdev);
2780extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2781extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2782extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2783 u8 perf_req, bool advertise);
dc50ba7f 2784extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2785#else
2786static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2787static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2788#endif
d7a2952f 2789
c38f34b5
IH		 2790int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2791 struct radeon_cs_packet *pkt,
2792 unsigned idx);
9ffb7a6d 2793bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2794void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2795 struct radeon_cs_packet *pkt);
e9716993
IH		 2796int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2797 struct radeon_cs_reloc **cs_reloc,
2798 int nomm);
40592a17
IH		 2799int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2800 uint32_t *vline_start_end,
2801 uint32_t *vline_status);
c38f34b5 2802
4c788679
JG		 2803#include "radeon_object.h"
2804
771fe6b9 2805#endif
Linux kernel - Deliverables
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