Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __RADEON_H__ | |
29 | #define __RADEON_H__ | |
30 | ||
771fe6b9 JG |
31 | /* TODO: Here are things that needs to be done : |
32 | * - surface allocator & initializer : (bit like scratch reg) should | |
33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings | |
34 | * related to surface | |
35 | * - WB : write back stuff (do it bit like scratch reg things) | |
36 | * - Vblank : look at Jesse's rework and what we should do | |
37 | * - r600/r700: gart & cp | |
38 | * - cs : clean cs ioctl use bitmap & things like that. | |
39 | * - power management stuff | |
40 | * - Barrier in gart code | |
41 | * - Unmappabled vram ? | |
42 | * - TESTING, TESTING, TESTING | |
43 | */ | |
44 | ||
d39c3b89 JG |
45 | /* Initialization path: |
46 | * We expect that acceleration initialization might fail for various | |
47 | * reasons even thought we work hard to make it works on most | |
48 | * configurations. In order to still have a working userspace in such | |
49 | * situation the init path must succeed up to the memory controller | |
50 | * initialization point. Failure before this point are considered as | |
51 | * fatal error. Here is the init callchain : | |
52 | * radeon_device_init perform common structure, mutex initialization | |
53 | * asic_init setup the GPU memory layout and perform all | |
54 | * one time initialization (failure in this | |
55 | * function are considered fatal) | |
56 | * asic_startup setup the GPU acceleration, in order to | |
57 | * follow guideline the first thing this | |
58 | * function should do is setting the GPU | |
59 | * memory controller (only MC setup failure | |
60 | * are considered as fatal) | |
61 | */ | |
62 | ||
771fe6b9 JG |
63 | #include <asm/atomic.h> |
64 | #include <linux/wait.h> | |
65 | #include <linux/list.h> | |
66 | #include <linux/kref.h> | |
67 | ||
4c788679 JG |
68 | #include <ttm/ttm_bo_api.h> |
69 | #include <ttm/ttm_bo_driver.h> | |
70 | #include <ttm/ttm_placement.h> | |
71 | #include <ttm/ttm_module.h> | |
147666fb | 72 | #include <ttm/ttm_execbuf_util.h> |
4c788679 | 73 | |
c2142715 | 74 | #include "radeon_family.h" |
771fe6b9 JG |
75 | #include "radeon_mode.h" |
76 | #include "radeon_reg.h" | |
771fe6b9 JG |
77 | |
78 | /* | |
79 | * Modules parameters. | |
80 | */ | |
81 | extern int radeon_no_wb; | |
82 | extern int radeon_modeset; | |
83 | extern int radeon_dynclks; | |
84 | extern int radeon_r4xx_atom; | |
85 | extern int radeon_agpmode; | |
86 | extern int radeon_vram_limit; | |
87 | extern int radeon_gart_size; | |
88 | extern int radeon_benchmarking; | |
ecc0b326 | 89 | extern int radeon_testing; |
771fe6b9 | 90 | extern int radeon_connector_table; |
4ce001ab | 91 | extern int radeon_tv; |
dafc3bd5 | 92 | extern int radeon_audio; |
f46c0120 | 93 | extern int radeon_disp_priority; |
e2b0a8e1 | 94 | extern int radeon_hw_i2c; |
d42dd579 | 95 | extern int radeon_pcie_gen2; |
771fe6b9 JG |
96 | |
97 | /* | |
98 | * Copy from radeon_drv.h so we don't have to include both and have conflicting | |
99 | * symbol; | |
100 | */ | |
101 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ | |
225758d8 | 102 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
e821767b | 103 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
771fe6b9 JG |
104 | #define RADEON_IB_POOL_SIZE 16 |
105 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 | |
106 | #define RADEONFB_CONN_LIMIT 4 | |
f657c2a7 | 107 | #define RADEON_BIOS_NUM_SCRATCH 8 |
771fe6b9 | 108 | |
771fe6b9 JG |
109 | /* |
110 | * Errata workarounds. | |
111 | */ | |
112 | enum radeon_pll_errata { | |
113 | CHIP_ERRATA_R300_CG = 0x00000001, | |
114 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, | |
115 | CHIP_ERRATA_PLL_DELAY = 0x00000004 | |
116 | }; | |
117 | ||
118 | ||
119 | struct radeon_device; | |
120 | ||
121 | ||
122 | /* | |
123 | * BIOS. | |
124 | */ | |
6a9ee8af DA |
125 | #define ATRM_BIOS_PAGE 4096 |
126 | ||
8edb381d | 127 | #if defined(CONFIG_VGA_SWITCHEROO) |
6a9ee8af DA |
128 | bool radeon_atrm_supported(struct pci_dev *pdev); |
129 | int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len); | |
8edb381d DA |
130 | #else |
131 | static inline bool radeon_atrm_supported(struct pci_dev *pdev) | |
132 | { | |
133 | return false; | |
134 | } | |
135 | ||
136 | static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){ | |
137 | return -EINVAL; | |
138 | } | |
139 | #endif | |
771fe6b9 JG |
140 | bool radeon_get_bios(struct radeon_device *rdev); |
141 | ||
3ce0a23d | 142 | |
771fe6b9 | 143 | /* |
3ce0a23d | 144 | * Dummy page |
771fe6b9 | 145 | */ |
3ce0a23d JG |
146 | struct radeon_dummy_page { |
147 | struct page *page; | |
148 | dma_addr_t addr; | |
149 | }; | |
150 | int radeon_dummy_page_init(struct radeon_device *rdev); | |
151 | void radeon_dummy_page_fini(struct radeon_device *rdev); | |
152 | ||
771fe6b9 | 153 | |
3ce0a23d JG |
154 | /* |
155 | * Clocks | |
156 | */ | |
771fe6b9 JG |
157 | struct radeon_clock { |
158 | struct radeon_pll p1pll; | |
159 | struct radeon_pll p2pll; | |
bcc1c2a1 | 160 | struct radeon_pll dcpll; |
771fe6b9 JG |
161 | struct radeon_pll spll; |
162 | struct radeon_pll mpll; | |
163 | /* 10 Khz units */ | |
164 | uint32_t default_mclk; | |
165 | uint32_t default_sclk; | |
bcc1c2a1 AD |
166 | uint32_t default_dispclk; |
167 | uint32_t dp_extclk; | |
b20f9bef | 168 | uint32_t max_pixel_clock; |
771fe6b9 JG |
169 | }; |
170 | ||
7433874e RM |
171 | /* |
172 | * Power management | |
173 | */ | |
174 | int radeon_pm_init(struct radeon_device *rdev); | |
29fb52ca | 175 | void radeon_pm_fini(struct radeon_device *rdev); |
c913e23a | 176 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
ce8f5370 AD |
177 | void radeon_pm_suspend(struct radeon_device *rdev); |
178 | void radeon_pm_resume(struct radeon_device *rdev); | |
56278a8e AD |
179 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
180 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); | |
8a83ec5e | 181 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
ee4017f4 | 182 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage); |
f892034a | 183 | void rs690_pm_info(struct radeon_device *rdev); |
20d391d7 AD |
184 | extern int rv6xx_get_temp(struct radeon_device *rdev); |
185 | extern int rv770_get_temp(struct radeon_device *rdev); | |
186 | extern int evergreen_get_temp(struct radeon_device *rdev); | |
187 | extern int sumo_get_temp(struct radeon_device *rdev); | |
3ce0a23d | 188 | |
771fe6b9 JG |
189 | /* |
190 | * Fences. | |
191 | */ | |
192 | struct radeon_fence_driver { | |
193 | uint32_t scratch_reg; | |
194 | atomic_t seq; | |
195 | uint32_t last_seq; | |
225758d8 JG |
196 | unsigned long last_jiffies; |
197 | unsigned long last_timeout; | |
771fe6b9 JG |
198 | wait_queue_head_t queue; |
199 | rwlock_t lock; | |
200 | struct list_head created; | |
201 | struct list_head emited; | |
202 | struct list_head signaled; | |
0a0c7596 | 203 | bool initialized; |
771fe6b9 JG |
204 | }; |
205 | ||
206 | struct radeon_fence { | |
207 | struct radeon_device *rdev; | |
208 | struct kref kref; | |
209 | struct list_head list; | |
210 | /* protected by radeon_fence.lock */ | |
211 | uint32_t seq; | |
771fe6b9 JG |
212 | bool emited; |
213 | bool signaled; | |
214 | }; | |
215 | ||
216 | int radeon_fence_driver_init(struct radeon_device *rdev); | |
217 | void radeon_fence_driver_fini(struct radeon_device *rdev); | |
218 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); | |
219 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); | |
220 | void radeon_fence_process(struct radeon_device *rdev); | |
221 | bool radeon_fence_signaled(struct radeon_fence *fence); | |
222 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); | |
223 | int radeon_fence_wait_next(struct radeon_device *rdev); | |
224 | int radeon_fence_wait_last(struct radeon_device *rdev); | |
225 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); | |
226 | void radeon_fence_unref(struct radeon_fence **fence); | |
227 | ||
e024e110 DA |
228 | /* |
229 | * Tiling registers | |
230 | */ | |
231 | struct radeon_surface_reg { | |
4c788679 | 232 | struct radeon_bo *bo; |
e024e110 DA |
233 | }; |
234 | ||
235 | #define RADEON_GEM_MAX_SURFACES 8 | |
771fe6b9 JG |
236 | |
237 | /* | |
4c788679 | 238 | * TTM. |
771fe6b9 | 239 | */ |
4c788679 JG |
240 | struct radeon_mman { |
241 | struct ttm_bo_global_ref bo_global_ref; | |
ba4420c2 | 242 | struct drm_global_reference mem_global_ref; |
4c788679 | 243 | struct ttm_bo_device bdev; |
0a0c7596 JG |
244 | bool mem_global_referenced; |
245 | bool initialized; | |
4c788679 JG |
246 | }; |
247 | ||
248 | struct radeon_bo { | |
249 | /* Protected by gem.mutex */ | |
250 | struct list_head list; | |
251 | /* Protected by tbo.reserved */ | |
312ea8da JG |
252 | u32 placements[3]; |
253 | struct ttm_placement placement; | |
4c788679 JG |
254 | struct ttm_buffer_object tbo; |
255 | struct ttm_bo_kmap_obj kmap; | |
256 | unsigned pin_count; | |
257 | void *kptr; | |
258 | u32 tiling_flags; | |
259 | u32 pitch; | |
260 | int surface_reg; | |
261 | /* Constant after initialization */ | |
262 | struct radeon_device *rdev; | |
441921d5 | 263 | struct drm_gem_object gem_base; |
4c788679 | 264 | }; |
7e4d15d9 | 265 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
771fe6b9 | 266 | |
4c788679 | 267 | struct radeon_bo_list { |
147666fb | 268 | struct ttm_validate_buffer tv; |
4c788679 | 269 | struct radeon_bo *bo; |
771fe6b9 JG |
270 | uint64_t gpu_offset; |
271 | unsigned rdomain; | |
272 | unsigned wdomain; | |
4c788679 | 273 | u32 tiling_flags; |
771fe6b9 JG |
274 | }; |
275 | ||
771fe6b9 JG |
276 | /* |
277 | * GEM objects. | |
278 | */ | |
279 | struct radeon_gem { | |
4c788679 | 280 | struct mutex mutex; |
771fe6b9 JG |
281 | struct list_head objects; |
282 | }; | |
283 | ||
284 | int radeon_gem_init(struct radeon_device *rdev); | |
285 | void radeon_gem_fini(struct radeon_device *rdev); | |
286 | int radeon_gem_object_create(struct radeon_device *rdev, int size, | |
4c788679 JG |
287 | int alignment, int initial_domain, |
288 | bool discardable, bool kernel, | |
289 | struct drm_gem_object **obj); | |
771fe6b9 JG |
290 | int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, |
291 | uint64_t *gpu_addr); | |
292 | void radeon_gem_object_unpin(struct drm_gem_object *obj); | |
293 | ||
ff72145b DA |
294 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
295 | struct drm_device *dev, | |
296 | struct drm_mode_create_dumb *args); | |
297 | int radeon_mode_dumb_mmap(struct drm_file *filp, | |
298 | struct drm_device *dev, | |
299 | uint32_t handle, uint64_t *offset_p); | |
300 | int radeon_mode_dumb_destroy(struct drm_file *file_priv, | |
301 | struct drm_device *dev, | |
302 | uint32_t handle); | |
771fe6b9 JG |
303 | |
304 | /* | |
305 | * GART structures, functions & helpers | |
306 | */ | |
307 | struct radeon_mc; | |
308 | ||
309 | struct radeon_gart_table_ram { | |
310 | volatile uint32_t *ptr; | |
311 | }; | |
312 | ||
313 | struct radeon_gart_table_vram { | |
4c788679 | 314 | struct radeon_bo *robj; |
771fe6b9 JG |
315 | volatile uint32_t *ptr; |
316 | }; | |
317 | ||
318 | union radeon_gart_table { | |
319 | struct radeon_gart_table_ram ram; | |
320 | struct radeon_gart_table_vram vram; | |
321 | }; | |
322 | ||
a77f1718 | 323 | #define RADEON_GPU_PAGE_SIZE 4096 |
d594e46a | 324 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
a77f1718 | 325 | |
771fe6b9 JG |
326 | struct radeon_gart { |
327 | dma_addr_t table_addr; | |
328 | unsigned num_gpu_pages; | |
329 | unsigned num_cpu_pages; | |
330 | unsigned table_size; | |
331 | union radeon_gart_table table; | |
332 | struct page **pages; | |
333 | dma_addr_t *pages_addr; | |
c39d3516 | 334 | bool *ttm_alloced; |
771fe6b9 JG |
335 | bool ready; |
336 | }; | |
337 | ||
338 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); | |
339 | void radeon_gart_table_ram_free(struct radeon_device *rdev); | |
340 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); | |
341 | void radeon_gart_table_vram_free(struct radeon_device *rdev); | |
342 | int radeon_gart_init(struct radeon_device *rdev); | |
343 | void radeon_gart_fini(struct radeon_device *rdev); | |
344 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, | |
345 | int pages); | |
346 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, | |
c39d3516 KRW |
347 | int pages, struct page **pagelist, |
348 | dma_addr_t *dma_addr); | |
771fe6b9 JG |
349 | |
350 | ||
351 | /* | |
352 | * GPU MC structures, functions & helpers | |
353 | */ | |
354 | struct radeon_mc { | |
355 | resource_size_t aper_size; | |
356 | resource_size_t aper_base; | |
357 | resource_size_t agp_base; | |
7a50f01a DA |
358 | /* for some chips with <= 32MB we need to lie |
359 | * about vram size near mc fb location */ | |
3ce0a23d | 360 | u64 mc_vram_size; |
d594e46a | 361 | u64 visible_vram_size; |
3ce0a23d JG |
362 | u64 gtt_size; |
363 | u64 gtt_start; | |
364 | u64 gtt_end; | |
3ce0a23d JG |
365 | u64 vram_start; |
366 | u64 vram_end; | |
771fe6b9 | 367 | unsigned vram_width; |
3ce0a23d | 368 | u64 real_vram_size; |
771fe6b9 JG |
369 | int vram_mtrr; |
370 | bool vram_is_ddr; | |
d594e46a | 371 | bool igp_sideport_enabled; |
8d369bb1 | 372 | u64 gtt_base_align; |
771fe6b9 JG |
373 | }; |
374 | ||
06b6476d AD |
375 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
376 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); | |
771fe6b9 JG |
377 | |
378 | /* | |
379 | * GPU scratch registers structures, functions & helpers | |
380 | */ | |
381 | struct radeon_scratch { | |
382 | unsigned num_reg; | |
724c80e1 | 383 | uint32_t reg_base; |
771fe6b9 JG |
384 | bool free[32]; |
385 | uint32_t reg[32]; | |
386 | }; | |
387 | ||
388 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); | |
389 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); | |
390 | ||
391 | ||
392 | /* | |
393 | * IRQS. | |
394 | */ | |
6f34be50 AD |
395 | |
396 | struct radeon_unpin_work { | |
397 | struct work_struct work; | |
398 | struct radeon_device *rdev; | |
399 | int crtc_id; | |
400 | struct radeon_fence *fence; | |
401 | struct drm_pending_vblank_event *event; | |
402 | struct radeon_bo *old_rbo; | |
403 | u64 new_crtc_base; | |
404 | }; | |
405 | ||
406 | struct r500_irq_stat_regs { | |
407 | u32 disp_int; | |
408 | }; | |
409 | ||
410 | struct r600_irq_stat_regs { | |
411 | u32 disp_int; | |
412 | u32 disp_int_cont; | |
413 | u32 disp_int_cont2; | |
414 | u32 d1grph_int; | |
415 | u32 d2grph_int; | |
416 | }; | |
417 | ||
418 | struct evergreen_irq_stat_regs { | |
419 | u32 disp_int; | |
420 | u32 disp_int_cont; | |
421 | u32 disp_int_cont2; | |
422 | u32 disp_int_cont3; | |
423 | u32 disp_int_cont4; | |
424 | u32 disp_int_cont5; | |
425 | u32 d1grph_int; | |
426 | u32 d2grph_int; | |
427 | u32 d3grph_int; | |
428 | u32 d4grph_int; | |
429 | u32 d5grph_int; | |
430 | u32 d6grph_int; | |
431 | }; | |
432 | ||
433 | union radeon_irq_stat_regs { | |
434 | struct r500_irq_stat_regs r500; | |
435 | struct r600_irq_stat_regs r600; | |
436 | struct evergreen_irq_stat_regs evergreen; | |
437 | }; | |
438 | ||
771fe6b9 JG |
439 | struct radeon_irq { |
440 | bool installed; | |
441 | bool sw_int; | |
442 | /* FIXME: use a define max crtc rather than hardcode it */ | |
45f9a39b | 443 | bool crtc_vblank_int[6]; |
6f34be50 | 444 | bool pflip[6]; |
73a6d3fc | 445 | wait_queue_head_t vblank_queue; |
b500f680 AD |
446 | /* FIXME: use defines for max hpd/dacs */ |
447 | bool hpd[6]; | |
2031f77c AD |
448 | bool gui_idle; |
449 | bool gui_idle_acked; | |
450 | wait_queue_head_t idle_queue; | |
f2594933 CK |
451 | /* FIXME: use defines for max HDMI blocks */ |
452 | bool hdmi[2]; | |
1614f8b1 DA |
453 | spinlock_t sw_lock; |
454 | int sw_refcount; | |
6f34be50 AD |
455 | union radeon_irq_stat_regs stat_regs; |
456 | spinlock_t pflip_lock[6]; | |
457 | int pflip_refcount[6]; | |
771fe6b9 JG |
458 | }; |
459 | ||
460 | int radeon_irq_kms_init(struct radeon_device *rdev); | |
461 | void radeon_irq_kms_fini(struct radeon_device *rdev); | |
1614f8b1 DA |
462 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev); |
463 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev); | |
6f34be50 AD |
464 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
465 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); | |
771fe6b9 JG |
466 | |
467 | /* | |
468 | * CP & ring. | |
469 | */ | |
470 | struct radeon_ib { | |
471 | struct list_head list; | |
e821767b | 472 | unsigned idx; |
771fe6b9 JG |
473 | uint64_t gpu_addr; |
474 | struct radeon_fence *fence; | |
e821767b | 475 | uint32_t *ptr; |
771fe6b9 | 476 | uint32_t length_dw; |
e821767b | 477 | bool free; |
771fe6b9 JG |
478 | }; |
479 | ||
ecb114a1 DA |
480 | /* |
481 | * locking - | |
482 | * mutex protects scheduled_ibs, ready, alloc_bm | |
483 | */ | |
771fe6b9 JG |
484 | struct radeon_ib_pool { |
485 | struct mutex mutex; | |
4c788679 | 486 | struct radeon_bo *robj; |
9f93ed39 | 487 | struct list_head bogus_ib; |
771fe6b9 JG |
488 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; |
489 | bool ready; | |
e821767b | 490 | unsigned head_id; |
771fe6b9 JG |
491 | }; |
492 | ||
493 | struct radeon_cp { | |
4c788679 | 494 | struct radeon_bo *ring_obj; |
771fe6b9 JG |
495 | volatile uint32_t *ring; |
496 | unsigned rptr; | |
497 | unsigned wptr; | |
498 | unsigned wptr_old; | |
499 | unsigned ring_size; | |
500 | unsigned ring_free_dw; | |
501 | int count_dw; | |
502 | uint64_t gpu_addr; | |
503 | uint32_t align_mask; | |
504 | uint32_t ptr_mask; | |
505 | struct mutex mutex; | |
506 | bool ready; | |
507 | }; | |
508 | ||
d8f60cfc AD |
509 | /* |
510 | * R6xx+ IH ring | |
511 | */ | |
512 | struct r600_ih { | |
4c788679 | 513 | struct radeon_bo *ring_obj; |
d8f60cfc AD |
514 | volatile uint32_t *ring; |
515 | unsigned rptr; | |
516 | unsigned wptr; | |
517 | unsigned wptr_old; | |
518 | unsigned ring_size; | |
519 | uint64_t gpu_addr; | |
d8f60cfc AD |
520 | uint32_t ptr_mask; |
521 | spinlock_t lock; | |
522 | bool enabled; | |
523 | }; | |
524 | ||
3ce0a23d | 525 | struct r600_blit { |
ff82f052 | 526 | struct mutex mutex; |
4c788679 | 527 | struct radeon_bo *shader_obj; |
3ce0a23d JG |
528 | u64 shader_gpu_addr; |
529 | u32 vs_offset, ps_offset; | |
530 | u32 state_offset; | |
531 | u32 state_len; | |
532 | u32 vb_used, vb_total; | |
533 | struct radeon_ib *vb_ib; | |
534 | }; | |
535 | ||
771fe6b9 JG |
536 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); |
537 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); | |
538 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); | |
539 | int radeon_ib_pool_init(struct radeon_device *rdev); | |
540 | void radeon_ib_pool_fini(struct radeon_device *rdev); | |
541 | int radeon_ib_test(struct radeon_device *rdev); | |
9f93ed39 | 542 | extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib); |
771fe6b9 JG |
543 | /* Ring access between begin & end cannot sleep */ |
544 | void radeon_ring_free_size(struct radeon_device *rdev); | |
91700f3c | 545 | int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw); |
771fe6b9 | 546 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); |
91700f3c | 547 | void radeon_ring_commit(struct radeon_device *rdev); |
771fe6b9 JG |
548 | void radeon_ring_unlock_commit(struct radeon_device *rdev); |
549 | void radeon_ring_unlock_undo(struct radeon_device *rdev); | |
550 | int radeon_ring_test(struct radeon_device *rdev); | |
551 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
552 | void radeon_ring_fini(struct radeon_device *rdev); | |
553 | ||
554 | ||
555 | /* | |
556 | * CS. | |
557 | */ | |
558 | struct radeon_cs_reloc { | |
559 | struct drm_gem_object *gobj; | |
4c788679 JG |
560 | struct radeon_bo *robj; |
561 | struct radeon_bo_list lobj; | |
771fe6b9 JG |
562 | uint32_t handle; |
563 | uint32_t flags; | |
564 | }; | |
565 | ||
566 | struct radeon_cs_chunk { | |
567 | uint32_t chunk_id; | |
568 | uint32_t length_dw; | |
513bcb46 DA |
569 | int kpage_idx[2]; |
570 | uint32_t *kpage[2]; | |
771fe6b9 | 571 | uint32_t *kdata; |
513bcb46 DA |
572 | void __user *user_ptr; |
573 | int last_copied_page; | |
574 | int last_page_index; | |
771fe6b9 JG |
575 | }; |
576 | ||
577 | struct radeon_cs_parser { | |
c8c15ff1 | 578 | struct device *dev; |
771fe6b9 JG |
579 | struct radeon_device *rdev; |
580 | struct drm_file *filp; | |
581 | /* chunks */ | |
582 | unsigned nchunks; | |
583 | struct radeon_cs_chunk *chunks; | |
584 | uint64_t *chunks_array; | |
585 | /* IB */ | |
586 | unsigned idx; | |
587 | /* relocations */ | |
588 | unsigned nrelocs; | |
589 | struct radeon_cs_reloc *relocs; | |
590 | struct radeon_cs_reloc **relocs_ptr; | |
591 | struct list_head validated; | |
592 | /* indices of various chunks */ | |
593 | int chunk_ib_idx; | |
594 | int chunk_relocs_idx; | |
595 | struct radeon_ib *ib; | |
596 | void *track; | |
3ce0a23d | 597 | unsigned family; |
513bcb46 | 598 | int parser_error; |
771fe6b9 JG |
599 | }; |
600 | ||
513bcb46 DA |
601 | extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); |
602 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); | |
603 | ||
604 | ||
605 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) | |
606 | { | |
607 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; | |
608 | u32 pg_idx, pg_offset; | |
609 | u32 idx_value = 0; | |
610 | int new_page; | |
611 | ||
612 | pg_idx = (idx * 4) / PAGE_SIZE; | |
613 | pg_offset = (idx * 4) % PAGE_SIZE; | |
614 | ||
615 | if (ibc->kpage_idx[0] == pg_idx) | |
616 | return ibc->kpage[0][pg_offset/4]; | |
617 | if (ibc->kpage_idx[1] == pg_idx) | |
618 | return ibc->kpage[1][pg_offset/4]; | |
619 | ||
620 | new_page = radeon_cs_update_pages(p, pg_idx); | |
621 | if (new_page < 0) { | |
622 | p->parser_error = new_page; | |
623 | return 0; | |
624 | } | |
625 | ||
626 | idx_value = ibc->kpage[new_page][pg_offset/4]; | |
627 | return idx_value; | |
628 | } | |
629 | ||
771fe6b9 JG |
630 | struct radeon_cs_packet { |
631 | unsigned idx; | |
632 | unsigned type; | |
633 | unsigned reg; | |
634 | unsigned opcode; | |
635 | int count; | |
636 | unsigned one_reg_wr; | |
637 | }; | |
638 | ||
639 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, | |
640 | struct radeon_cs_packet *pkt, | |
641 | unsigned idx, unsigned reg); | |
642 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, | |
643 | struct radeon_cs_packet *pkt); | |
644 | ||
645 | ||
646 | /* | |
647 | * AGP | |
648 | */ | |
649 | int radeon_agp_init(struct radeon_device *rdev); | |
0ebf1717 | 650 | void radeon_agp_resume(struct radeon_device *rdev); |
10b06122 | 651 | void radeon_agp_suspend(struct radeon_device *rdev); |
771fe6b9 JG |
652 | void radeon_agp_fini(struct radeon_device *rdev); |
653 | ||
654 | ||
655 | /* | |
656 | * Writeback | |
657 | */ | |
658 | struct radeon_wb { | |
4c788679 | 659 | struct radeon_bo *wb_obj; |
771fe6b9 JG |
660 | volatile uint32_t *wb; |
661 | uint64_t gpu_addr; | |
724c80e1 | 662 | bool enabled; |
d0f8a854 | 663 | bool use_event; |
771fe6b9 JG |
664 | }; |
665 | ||
724c80e1 AD |
666 | #define RADEON_WB_SCRATCH_OFFSET 0 |
667 | #define RADEON_WB_CP_RPTR_OFFSET 1024 | |
0c88a02e AD |
668 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
669 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 | |
724c80e1 | 670 | #define R600_WB_IH_WPTR_OFFSET 2048 |
d0f8a854 | 671 | #define R600_WB_EVENT_OFFSET 3072 |
724c80e1 | 672 | |
c93bb85b JG |
673 | /** |
674 | * struct radeon_pm - power management datas | |
675 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) | |
676 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) | |
677 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) | |
678 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) | |
679 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) | |
680 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) | |
681 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) | |
682 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) | |
683 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) | |
25985edc | 684 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
c93bb85b JG |
685 | * @needed_bandwidth: current bandwidth needs |
686 | * | |
687 | * It keeps track of various data needed to take powermanagement decision. | |
25985edc | 688 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
c93bb85b JG |
689 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
690 | * (type of memory, bus size, efficiency, ...) | |
691 | */ | |
ce8f5370 AD |
692 | |
693 | enum radeon_pm_method { | |
694 | PM_METHOD_PROFILE, | |
695 | PM_METHOD_DYNPM, | |
696 | }; | |
697 | ||
698 | enum radeon_dynpm_state { | |
699 | DYNPM_STATE_DISABLED, | |
700 | DYNPM_STATE_MINIMUM, | |
701 | DYNPM_STATE_PAUSED, | |
3f53eb6f RW |
702 | DYNPM_STATE_ACTIVE, |
703 | DYNPM_STATE_SUSPENDED, | |
c913e23a | 704 | }; |
ce8f5370 AD |
705 | enum radeon_dynpm_action { |
706 | DYNPM_ACTION_NONE, | |
707 | DYNPM_ACTION_MINIMUM, | |
708 | DYNPM_ACTION_DOWNCLOCK, | |
709 | DYNPM_ACTION_UPCLOCK, | |
710 | DYNPM_ACTION_DEFAULT | |
c913e23a | 711 | }; |
56278a8e AD |
712 | |
713 | enum radeon_voltage_type { | |
714 | VOLTAGE_NONE = 0, | |
715 | VOLTAGE_GPIO, | |
716 | VOLTAGE_VDDC, | |
717 | VOLTAGE_SW | |
718 | }; | |
719 | ||
0ec0e74f AD |
720 | enum radeon_pm_state_type { |
721 | POWER_STATE_TYPE_DEFAULT, | |
722 | POWER_STATE_TYPE_POWERSAVE, | |
723 | POWER_STATE_TYPE_BATTERY, | |
724 | POWER_STATE_TYPE_BALANCED, | |
725 | POWER_STATE_TYPE_PERFORMANCE, | |
726 | }; | |
727 | ||
ce8f5370 AD |
728 | enum radeon_pm_profile_type { |
729 | PM_PROFILE_DEFAULT, | |
730 | PM_PROFILE_AUTO, | |
731 | PM_PROFILE_LOW, | |
c9e75b21 | 732 | PM_PROFILE_MID, |
ce8f5370 AD |
733 | PM_PROFILE_HIGH, |
734 | }; | |
735 | ||
736 | #define PM_PROFILE_DEFAULT_IDX 0 | |
737 | #define PM_PROFILE_LOW_SH_IDX 1 | |
c9e75b21 AD |
738 | #define PM_PROFILE_MID_SH_IDX 2 |
739 | #define PM_PROFILE_HIGH_SH_IDX 3 | |
740 | #define PM_PROFILE_LOW_MH_IDX 4 | |
741 | #define PM_PROFILE_MID_MH_IDX 5 | |
742 | #define PM_PROFILE_HIGH_MH_IDX 6 | |
743 | #define PM_PROFILE_MAX 7 | |
ce8f5370 AD |
744 | |
745 | struct radeon_pm_profile { | |
746 | int dpms_off_ps_idx; | |
747 | int dpms_on_ps_idx; | |
748 | int dpms_off_cm_idx; | |
749 | int dpms_on_cm_idx; | |
516d0e46 AD |
750 | }; |
751 | ||
21a8122a AD |
752 | enum radeon_int_thermal_type { |
753 | THERMAL_TYPE_NONE, | |
754 | THERMAL_TYPE_RV6XX, | |
755 | THERMAL_TYPE_RV770, | |
756 | THERMAL_TYPE_EVERGREEN, | |
e33df25f | 757 | THERMAL_TYPE_SUMO, |
4fddba1f | 758 | THERMAL_TYPE_NI, |
21a8122a AD |
759 | }; |
760 | ||
56278a8e AD |
761 | struct radeon_voltage { |
762 | enum radeon_voltage_type type; | |
763 | /* gpio voltage */ | |
764 | struct radeon_gpio_rec gpio; | |
765 | u32 delay; /* delay in usec from voltage drop to sclk change */ | |
766 | bool active_high; /* voltage drop is active when bit is high */ | |
767 | /* VDDC voltage */ | |
768 | u8 vddc_id; /* index into vddc voltage table */ | |
769 | u8 vddci_id; /* index into vddci voltage table */ | |
770 | bool vddci_enabled; | |
771 | /* r6xx+ sw */ | |
2feea49a AD |
772 | u16 voltage; |
773 | /* evergreen+ vddci */ | |
774 | u16 vddci; | |
56278a8e AD |
775 | }; |
776 | ||
d7311171 AD |
777 | /* clock mode flags */ |
778 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) | |
779 | ||
56278a8e AD |
780 | struct radeon_pm_clock_info { |
781 | /* memory clock */ | |
782 | u32 mclk; | |
783 | /* engine clock */ | |
784 | u32 sclk; | |
785 | /* voltage info */ | |
786 | struct radeon_voltage voltage; | |
d7311171 | 787 | /* standardized clock flags */ |
56278a8e AD |
788 | u32 flags; |
789 | }; | |
790 | ||
a48b9b4e | 791 | /* state flags */ |
d7311171 | 792 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
a48b9b4e | 793 | |
56278a8e | 794 | struct radeon_power_state { |
0ec0e74f | 795 | enum radeon_pm_state_type type; |
56278a8e AD |
796 | /* XXX: use a define for num clock modes */ |
797 | struct radeon_pm_clock_info clock_info[8]; | |
798 | /* number of valid clock modes in this power state */ | |
799 | int num_clock_modes; | |
56278a8e | 800 | struct radeon_pm_clock_info *default_clock_mode; |
a48b9b4e AD |
801 | /* standardized state flags */ |
802 | u32 flags; | |
79daedc9 AD |
803 | u32 misc; /* vbios specific flags */ |
804 | u32 misc2; /* vbios specific flags */ | |
805 | int pcie_lanes; /* pcie lanes */ | |
56278a8e AD |
806 | }; |
807 | ||
27459324 RM |
808 | /* |
809 | * Some modes are overclocked by very low value, accept them | |
810 | */ | |
811 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ | |
812 | ||
c93bb85b | 813 | struct radeon_pm { |
c913e23a | 814 | struct mutex mutex; |
a48b9b4e AD |
815 | u32 active_crtcs; |
816 | int active_crtc_count; | |
c913e23a | 817 | int req_vblank; |
839461d3 | 818 | bool vblank_sync; |
2031f77c | 819 | bool gui_idle; |
c93bb85b JG |
820 | fixed20_12 max_bandwidth; |
821 | fixed20_12 igp_sideport_mclk; | |
822 | fixed20_12 igp_system_mclk; | |
823 | fixed20_12 igp_ht_link_clk; | |
824 | fixed20_12 igp_ht_link_width; | |
825 | fixed20_12 k8_bandwidth; | |
826 | fixed20_12 sideport_bandwidth; | |
827 | fixed20_12 ht_bandwidth; | |
828 | fixed20_12 core_bandwidth; | |
829 | fixed20_12 sclk; | |
f47299c5 | 830 | fixed20_12 mclk; |
c93bb85b | 831 | fixed20_12 needed_bandwidth; |
0975b162 | 832 | struct radeon_power_state *power_state; |
56278a8e AD |
833 | /* number of valid power states */ |
834 | int num_power_states; | |
a48b9b4e AD |
835 | int current_power_state_index; |
836 | int current_clock_mode_index; | |
837 | int requested_power_state_index; | |
838 | int requested_clock_mode_index; | |
839 | int default_power_state_index; | |
840 | u32 current_sclk; | |
841 | u32 current_mclk; | |
2feea49a AD |
842 | u16 current_vddc; |
843 | u16 current_vddci; | |
9ace9f7b AD |
844 | u32 default_sclk; |
845 | u32 default_mclk; | |
2feea49a AD |
846 | u16 default_vddc; |
847 | u16 default_vddci; | |
29fb52ca | 848 | struct radeon_i2c_chan *i2c_bus; |
ce8f5370 AD |
849 | /* selected pm method */ |
850 | enum radeon_pm_method pm_method; | |
851 | /* dynpm power management */ | |
852 | struct delayed_work dynpm_idle_work; | |
853 | enum radeon_dynpm_state dynpm_state; | |
854 | enum radeon_dynpm_action dynpm_planned_action; | |
855 | unsigned long dynpm_action_timeout; | |
856 | bool dynpm_can_upclock; | |
857 | bool dynpm_can_downclock; | |
858 | /* profile-based power management */ | |
859 | enum radeon_pm_profile_type profile; | |
860 | int profile_index; | |
861 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; | |
21a8122a AD |
862 | /* internal thermal controller on rv6xx+ */ |
863 | enum radeon_int_thermal_type int_thermal_type; | |
864 | struct device *int_hwmon_dev; | |
c93bb85b JG |
865 | }; |
866 | ||
771fe6b9 JG |
867 | |
868 | /* | |
869 | * Benchmarking | |
870 | */ | |
871 | void radeon_benchmark(struct radeon_device *rdev); | |
872 | ||
873 | ||
ecc0b326 MD |
874 | /* |
875 | * Testing | |
876 | */ | |
877 | void radeon_test_moves(struct radeon_device *rdev); | |
878 | ||
879 | ||
771fe6b9 JG |
880 | /* |
881 | * Debugfs | |
882 | */ | |
883 | int radeon_debugfs_add_files(struct radeon_device *rdev, | |
884 | struct drm_info_list *files, | |
885 | unsigned nfiles); | |
886 | int radeon_debugfs_fence_init(struct radeon_device *rdev); | |
771fe6b9 JG |
887 | |
888 | ||
889 | /* | |
890 | * ASIC specific functions. | |
891 | */ | |
892 | struct radeon_asic { | |
068a117c | 893 | int (*init)(struct radeon_device *rdev); |
3ce0a23d JG |
894 | void (*fini)(struct radeon_device *rdev); |
895 | int (*resume)(struct radeon_device *rdev); | |
896 | int (*suspend)(struct radeon_device *rdev); | |
28d52043 | 897 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
225758d8 | 898 | bool (*gpu_is_lockup)(struct radeon_device *rdev); |
a2d07b74 | 899 | int (*asic_reset)(struct radeon_device *rdev); |
771fe6b9 JG |
900 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
901 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); | |
902 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); | |
903 | void (*cp_fini)(struct radeon_device *rdev); | |
904 | void (*cp_disable)(struct radeon_device *rdev); | |
3ce0a23d | 905 | void (*cp_commit)(struct radeon_device *rdev); |
771fe6b9 | 906 | void (*ring_start)(struct radeon_device *rdev); |
3ce0a23d JG |
907 | int (*ring_test)(struct radeon_device *rdev); |
908 | void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); | |
771fe6b9 JG |
909 | int (*irq_set)(struct radeon_device *rdev); |
910 | int (*irq_process)(struct radeon_device *rdev); | |
7ed220d7 | 911 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
771fe6b9 JG |
912 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
913 | int (*cs_parse)(struct radeon_cs_parser *p); | |
914 | int (*copy_blit)(struct radeon_device *rdev, | |
915 | uint64_t src_offset, | |
916 | uint64_t dst_offset, | |
917 | unsigned num_pages, | |
918 | struct radeon_fence *fence); | |
919 | int (*copy_dma)(struct radeon_device *rdev, | |
920 | uint64_t src_offset, | |
921 | uint64_t dst_offset, | |
922 | unsigned num_pages, | |
923 | struct radeon_fence *fence); | |
924 | int (*copy)(struct radeon_device *rdev, | |
925 | uint64_t src_offset, | |
926 | uint64_t dst_offset, | |
927 | unsigned num_pages, | |
928 | struct radeon_fence *fence); | |
7433874e | 929 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
771fe6b9 | 930 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
7433874e | 931 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
771fe6b9 | 932 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
c836a412 | 933 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
771fe6b9 JG |
934 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
935 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); | |
e024e110 DA |
936 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
937 | uint32_t tiling_flags, uint32_t pitch, | |
938 | uint32_t offset, uint32_t obj_size); | |
9479c54f | 939 | void (*clear_surface_reg)(struct radeon_device *rdev, int reg); |
c93bb85b | 940 | void (*bandwidth_update)(struct radeon_device *rdev); |
429770b3 AD |
941 | void (*hpd_init)(struct radeon_device *rdev); |
942 | void (*hpd_fini)(struct radeon_device *rdev); | |
943 | bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
944 | void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
062b389c JG |
945 | /* ioctl hw specific callback. Some hw might want to perform special |
946 | * operation on specific ioctl. For instance on wait idle some hw | |
947 | * might want to perform and HDP flush through MMIO as it seems that | |
948 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed | |
949 | * through ring. | |
950 | */ | |
951 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); | |
def9ba9c | 952 | bool (*gui_idle)(struct radeon_device *rdev); |
ce8f5370 | 953 | /* power management */ |
49e02b73 AD |
954 | void (*pm_misc)(struct radeon_device *rdev); |
955 | void (*pm_prepare)(struct radeon_device *rdev); | |
956 | void (*pm_finish)(struct radeon_device *rdev); | |
ce8f5370 AD |
957 | void (*pm_init_profile)(struct radeon_device *rdev); |
958 | void (*pm_get_dynpm_state)(struct radeon_device *rdev); | |
6f34be50 AD |
959 | /* pageflipping */ |
960 | void (*pre_page_flip)(struct radeon_device *rdev, int crtc); | |
961 | u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
962 | void (*post_page_flip)(struct radeon_device *rdev, int crtc); | |
771fe6b9 JG |
963 | }; |
964 | ||
21f9a437 JG |
965 | /* |
966 | * Asic structures | |
967 | */ | |
225758d8 JG |
968 | struct r100_gpu_lockup { |
969 | unsigned long last_jiffies; | |
970 | u32 last_cp_rptr; | |
971 | }; | |
972 | ||
551ebd83 | 973 | struct r100_asic { |
225758d8 JG |
974 | const unsigned *reg_safe_bm; |
975 | unsigned reg_safe_bm_size; | |
976 | u32 hdp_cntl; | |
977 | struct r100_gpu_lockup lockup; | |
551ebd83 DA |
978 | }; |
979 | ||
21f9a437 | 980 | struct r300_asic { |
225758d8 JG |
981 | const unsigned *reg_safe_bm; |
982 | unsigned reg_safe_bm_size; | |
983 | u32 resync_scratch; | |
984 | u32 hdp_cntl; | |
985 | struct r100_gpu_lockup lockup; | |
21f9a437 JG |
986 | }; |
987 | ||
988 | struct r600_asic { | |
225758d8 JG |
989 | unsigned max_pipes; |
990 | unsigned max_tile_pipes; | |
991 | unsigned max_simds; | |
992 | unsigned max_backends; | |
993 | unsigned max_gprs; | |
994 | unsigned max_threads; | |
995 | unsigned max_stack_entries; | |
996 | unsigned max_hw_contexts; | |
997 | unsigned max_gs_threads; | |
998 | unsigned sx_max_export_size; | |
999 | unsigned sx_max_export_pos_size; | |
1000 | unsigned sx_max_export_smx_size; | |
1001 | unsigned sq_num_cf_insts; | |
1002 | unsigned tiling_nbanks; | |
1003 | unsigned tiling_npipes; | |
1004 | unsigned tiling_group_size; | |
e7aeeba6 | 1005 | unsigned tile_config; |
225758d8 | 1006 | struct r100_gpu_lockup lockup; |
21f9a437 JG |
1007 | }; |
1008 | ||
1009 | struct rv770_asic { | |
225758d8 JG |
1010 | unsigned max_pipes; |
1011 | unsigned max_tile_pipes; | |
1012 | unsigned max_simds; | |
1013 | unsigned max_backends; | |
1014 | unsigned max_gprs; | |
1015 | unsigned max_threads; | |
1016 | unsigned max_stack_entries; | |
1017 | unsigned max_hw_contexts; | |
1018 | unsigned max_gs_threads; | |
1019 | unsigned sx_max_export_size; | |
1020 | unsigned sx_max_export_pos_size; | |
1021 | unsigned sx_max_export_smx_size; | |
1022 | unsigned sq_num_cf_insts; | |
1023 | unsigned sx_num_of_sets; | |
1024 | unsigned sc_prim_fifo_size; | |
1025 | unsigned sc_hiz_tile_fifo_size; | |
1026 | unsigned sc_earlyz_tile_fifo_fize; | |
1027 | unsigned tiling_nbanks; | |
1028 | unsigned tiling_npipes; | |
1029 | unsigned tiling_group_size; | |
e7aeeba6 | 1030 | unsigned tile_config; |
225758d8 | 1031 | struct r100_gpu_lockup lockup; |
21f9a437 JG |
1032 | }; |
1033 | ||
32fcdbf4 AD |
1034 | struct evergreen_asic { |
1035 | unsigned num_ses; | |
1036 | unsigned max_pipes; | |
1037 | unsigned max_tile_pipes; | |
1038 | unsigned max_simds; | |
1039 | unsigned max_backends; | |
1040 | unsigned max_gprs; | |
1041 | unsigned max_threads; | |
1042 | unsigned max_stack_entries; | |
1043 | unsigned max_hw_contexts; | |
1044 | unsigned max_gs_threads; | |
1045 | unsigned sx_max_export_size; | |
1046 | unsigned sx_max_export_pos_size; | |
1047 | unsigned sx_max_export_smx_size; | |
1048 | unsigned sq_num_cf_insts; | |
1049 | unsigned sx_num_of_sets; | |
1050 | unsigned sc_prim_fifo_size; | |
1051 | unsigned sc_hiz_tile_fifo_size; | |
1052 | unsigned sc_earlyz_tile_fifo_size; | |
1053 | unsigned tiling_nbanks; | |
1054 | unsigned tiling_npipes; | |
1055 | unsigned tiling_group_size; | |
e7aeeba6 | 1056 | unsigned tile_config; |
17db7042 | 1057 | struct r100_gpu_lockup lockup; |
32fcdbf4 AD |
1058 | }; |
1059 | ||
fecf1d07 AD |
1060 | struct cayman_asic { |
1061 | unsigned max_shader_engines; | |
1062 | unsigned max_pipes_per_simd; | |
1063 | unsigned max_tile_pipes; | |
1064 | unsigned max_simds_per_se; | |
1065 | unsigned max_backends_per_se; | |
1066 | unsigned max_texture_channel_caches; | |
1067 | unsigned max_gprs; | |
1068 | unsigned max_threads; | |
1069 | unsigned max_gs_threads; | |
1070 | unsigned max_stack_entries; | |
1071 | unsigned sx_num_of_sets; | |
1072 | unsigned sx_max_export_size; | |
1073 | unsigned sx_max_export_pos_size; | |
1074 | unsigned sx_max_export_smx_size; | |
1075 | unsigned max_hw_contexts; | |
1076 | unsigned sq_num_cf_insts; | |
1077 | unsigned sc_prim_fifo_size; | |
1078 | unsigned sc_hiz_tile_fifo_size; | |
1079 | unsigned sc_earlyz_tile_fifo_size; | |
1080 | ||
1081 | unsigned num_shader_engines; | |
1082 | unsigned num_shader_pipes_per_simd; | |
1083 | unsigned num_tile_pipes; | |
1084 | unsigned num_simds_per_se; | |
1085 | unsigned num_backends_per_se; | |
1086 | unsigned backend_disable_mask_per_asic; | |
1087 | unsigned backend_map; | |
1088 | unsigned num_texture_channel_caches; | |
1089 | unsigned mem_max_burst_length_bytes; | |
1090 | unsigned mem_row_size_in_kb; | |
1091 | unsigned shader_engine_tile_size; | |
1092 | unsigned num_gpus; | |
1093 | unsigned multi_gpu_tile_size; | |
1094 | ||
1095 | unsigned tile_config; | |
1096 | struct r100_gpu_lockup lockup; | |
1097 | }; | |
1098 | ||
068a117c JG |
1099 | union radeon_asic_config { |
1100 | struct r300_asic r300; | |
551ebd83 | 1101 | struct r100_asic r100; |
3ce0a23d JG |
1102 | struct r600_asic r600; |
1103 | struct rv770_asic rv770; | |
32fcdbf4 | 1104 | struct evergreen_asic evergreen; |
fecf1d07 | 1105 | struct cayman_asic cayman; |
068a117c JG |
1106 | }; |
1107 | ||
0a10c851 DV |
1108 | /* |
1109 | * asic initizalization from radeon_asic.c | |
1110 | */ | |
1111 | void radeon_agp_disable(struct radeon_device *rdev); | |
1112 | int radeon_asic_init(struct radeon_device *rdev); | |
1113 | ||
771fe6b9 JG |
1114 | |
1115 | /* | |
1116 | * IOCTL. | |
1117 | */ | |
1118 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, | |
1119 | struct drm_file *filp); | |
1120 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, | |
1121 | struct drm_file *filp); | |
1122 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, | |
1123 | struct drm_file *file_priv); | |
1124 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1125 | struct drm_file *file_priv); | |
1126 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1127 | struct drm_file *file_priv); | |
1128 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1129 | struct drm_file *file_priv); | |
1130 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
1131 | struct drm_file *filp); | |
1132 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1133 | struct drm_file *filp); | |
1134 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1135 | struct drm_file *filp); | |
1136 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
1137 | struct drm_file *filp); | |
1138 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); | |
e024e110 DA |
1139 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
1140 | struct drm_file *filp); | |
1141 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | |
1142 | struct drm_file *filp); | |
771fe6b9 | 1143 | |
87cbf8f2 AD |
1144 | /* VRAM scratch page for HDP bug */ |
1145 | struct r700_vram_scratch { | |
1146 | struct radeon_bo *robj; | |
1147 | volatile uint32_t *ptr; | |
1148 | }; | |
771fe6b9 JG |
1149 | |
1150 | /* | |
1151 | * Core structure, functions and helpers. | |
1152 | */ | |
1153 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); | |
1154 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); | |
1155 | ||
1156 | struct radeon_device { | |
9f022ddf | 1157 | struct device *dev; |
771fe6b9 JG |
1158 | struct drm_device *ddev; |
1159 | struct pci_dev *pdev; | |
1160 | /* ASIC */ | |
068a117c | 1161 | union radeon_asic_config config; |
771fe6b9 JG |
1162 | enum radeon_family family; |
1163 | unsigned long flags; | |
1164 | int usec_timeout; | |
1165 | enum radeon_pll_errata pll_errata; | |
1166 | int num_gb_pipes; | |
f779b3e5 | 1167 | int num_z_pipes; |
771fe6b9 JG |
1168 | int disp_priority; |
1169 | /* BIOS */ | |
1170 | uint8_t *bios; | |
1171 | bool is_atom_bios; | |
1172 | uint16_t bios_header_start; | |
4c788679 | 1173 | struct radeon_bo *stollen_vga_memory; |
771fe6b9 | 1174 | /* Register mmio */ |
4c9bc75c DA |
1175 | resource_size_t rmmio_base; |
1176 | resource_size_t rmmio_size; | |
771fe6b9 | 1177 | void *rmmio; |
771fe6b9 JG |
1178 | radeon_rreg_t mc_rreg; |
1179 | radeon_wreg_t mc_wreg; | |
1180 | radeon_rreg_t pll_rreg; | |
1181 | radeon_wreg_t pll_wreg; | |
de1b2898 | 1182 | uint32_t pcie_reg_mask; |
771fe6b9 JG |
1183 | radeon_rreg_t pciep_rreg; |
1184 | radeon_wreg_t pciep_wreg; | |
351a52a2 AD |
1185 | /* io port */ |
1186 | void __iomem *rio_mem; | |
1187 | resource_size_t rio_mem_size; | |
771fe6b9 JG |
1188 | struct radeon_clock clock; |
1189 | struct radeon_mc mc; | |
1190 | struct radeon_gart gart; | |
1191 | struct radeon_mode_info mode_info; | |
1192 | struct radeon_scratch scratch; | |
1193 | struct radeon_mman mman; | |
1194 | struct radeon_fence_driver fence_drv; | |
1195 | struct radeon_cp cp; | |
0c88a02e AD |
1196 | /* cayman compute rings */ |
1197 | struct radeon_cp cp1; | |
1198 | struct radeon_cp cp2; | |
771fe6b9 JG |
1199 | struct radeon_ib_pool ib_pool; |
1200 | struct radeon_irq irq; | |
1201 | struct radeon_asic *asic; | |
1202 | struct radeon_gem gem; | |
c93bb85b | 1203 | struct radeon_pm pm; |
f657c2a7 | 1204 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
771fe6b9 JG |
1205 | struct mutex cs_mutex; |
1206 | struct radeon_wb wb; | |
3ce0a23d | 1207 | struct radeon_dummy_page dummy_page; |
771fe6b9 JG |
1208 | bool gpu_lockup; |
1209 | bool shutdown; | |
1210 | bool suspend; | |
ad49f501 | 1211 | bool need_dma32; |
733289c2 | 1212 | bool accel_working; |
e024e110 | 1213 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
3ce0a23d JG |
1214 | const struct firmware *me_fw; /* all family ME firmware */ |
1215 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ | |
d8f60cfc | 1216 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
0af62b01 | 1217 | const struct firmware *mc_fw; /* NI MC firmware */ |
3ce0a23d | 1218 | struct r600_blit r600_blit; |
87cbf8f2 | 1219 | struct r700_vram_scratch vram_scratch; |
3e5cb98d | 1220 | int msi_enabled; /* msi enabled */ |
d8f60cfc | 1221 | struct r600_ih ih; /* r6/700 interrupt ring */ |
d4877cf2 | 1222 | struct work_struct hotplug_work; |
18917b60 | 1223 | int num_crtc; /* number of crtcs */ |
40bacf16 | 1224 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
5876dd24 | 1225 | struct mutex vram_mutex; |
dafc3bd5 CK |
1226 | |
1227 | /* audio stuff */ | |
7eea7e9e | 1228 | bool audio_enabled; |
dafc3bd5 CK |
1229 | struct timer_list audio_timer; |
1230 | int audio_channels; | |
1231 | int audio_rate; | |
1232 | int audio_bits_per_sample; | |
1233 | uint8_t audio_status_bits; | |
1234 | uint8_t audio_category_code; | |
6a9ee8af | 1235 | |
ce8f5370 | 1236 | struct notifier_block acpi_nb; |
9eba4a93 | 1237 | /* only one userspace can use Hyperz features or CMASK at a time */ |
ab9e1f59 | 1238 | struct drm_file *hyperz_filp; |
9eba4a93 | 1239 | struct drm_file *cmask_filp; |
f376b94f AD |
1240 | /* i2c buses */ |
1241 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; | |
771fe6b9 JG |
1242 | }; |
1243 | ||
1244 | int radeon_device_init(struct radeon_device *rdev, | |
1245 | struct drm_device *ddev, | |
1246 | struct pci_dev *pdev, | |
1247 | uint32_t flags); | |
1248 | void radeon_device_fini(struct radeon_device *rdev); | |
1249 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); | |
1250 | ||
de1b2898 DA |
1251 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
1252 | { | |
07bec2df | 1253 | if (reg < rdev->rmmio_size) |
de1b2898 DA |
1254 | return readl(((void __iomem *)rdev->rmmio) + reg); |
1255 | else { | |
1256 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); | |
1257 | return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); | |
1258 | } | |
1259 | } | |
1260 | ||
1261 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
1262 | { | |
07bec2df | 1263 | if (reg < rdev->rmmio_size) |
de1b2898 DA |
1264 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
1265 | else { | |
1266 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); | |
1267 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); | |
1268 | } | |
1269 | } | |
1270 | ||
351a52a2 AD |
1271 | static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) |
1272 | { | |
1273 | if (reg < rdev->rio_mem_size) | |
1274 | return ioread32(rdev->rio_mem + reg); | |
1275 | else { | |
1276 | iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); | |
1277 | return ioread32(rdev->rio_mem + RADEON_MM_DATA); | |
1278 | } | |
1279 | } | |
1280 | ||
1281 | static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
1282 | { | |
1283 | if (reg < rdev->rio_mem_size) | |
1284 | iowrite32(v, rdev->rio_mem + reg); | |
1285 | else { | |
1286 | iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); | |
1287 | iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); | |
1288 | } | |
1289 | } | |
1290 | ||
4c788679 JG |
1291 | /* |
1292 | * Cast helper | |
1293 | */ | |
1294 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) | |
771fe6b9 JG |
1295 | |
1296 | /* | |
1297 | * Registers read & write functions. | |
1298 | */ | |
1299 | #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) | |
1300 | #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) | |
9e46a48d AD |
1301 | #define RREG16(reg) readw(((void __iomem *)rdev->rmmio) + (reg)) |
1302 | #define WREG16(reg, v) writew(v, ((void __iomem *)rdev->rmmio) + (reg)) | |
de1b2898 | 1303 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
3ce0a23d | 1304 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) |
de1b2898 | 1305 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
771fe6b9 JG |
1306 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1307 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
1308 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) | |
1309 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) | |
1310 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) | |
1311 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) | |
de1b2898 DA |
1312 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
1313 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) | |
aa5120d2 RM |
1314 | #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) |
1315 | #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) | |
771fe6b9 JG |
1316 | #define WREG32_P(reg, val, mask) \ |
1317 | do { \ | |
1318 | uint32_t tmp_ = RREG32(reg); \ | |
1319 | tmp_ &= (mask); \ | |
1320 | tmp_ |= ((val) & ~(mask)); \ | |
1321 | WREG32(reg, tmp_); \ | |
1322 | } while (0) | |
1323 | #define WREG32_PLL_P(reg, val, mask) \ | |
1324 | do { \ | |
1325 | uint32_t tmp_ = RREG32_PLL(reg); \ | |
1326 | tmp_ &= (mask); \ | |
1327 | tmp_ |= ((val) & ~(mask)); \ | |
1328 | WREG32_PLL(reg, tmp_); \ | |
1329 | } while (0) | |
3ce0a23d | 1330 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) |
351a52a2 AD |
1331 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
1332 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) | |
771fe6b9 | 1333 | |
de1b2898 DA |
1334 | /* |
1335 | * Indirect registers accessor | |
1336 | */ | |
1337 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) | |
1338 | { | |
1339 | uint32_t r; | |
1340 | ||
1341 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
1342 | r = RREG32(RADEON_PCIE_DATA); | |
1343 | return r; | |
1344 | } | |
1345 | ||
1346 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
1347 | { | |
1348 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
1349 | WREG32(RADEON_PCIE_DATA, (v)); | |
1350 | } | |
1351 | ||
771fe6b9 JG |
1352 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
1353 | ||
1354 | ||
1355 | /* | |
1356 | * ASICs helpers. | |
1357 | */ | |
b995e433 DA |
1358 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
1359 | (rdev->pdev->device == 0x5969)) | |
771fe6b9 JG |
1360 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
1361 | (rdev->family == CHIP_RV200) || \ | |
1362 | (rdev->family == CHIP_RS100) || \ | |
1363 | (rdev->family == CHIP_RS200) || \ | |
1364 | (rdev->family == CHIP_RV250) || \ | |
1365 | (rdev->family == CHIP_RV280) || \ | |
1366 | (rdev->family == CHIP_RS300)) | |
1367 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ | |
1368 | (rdev->family == CHIP_RV350) || \ | |
1369 | (rdev->family == CHIP_R350) || \ | |
1370 | (rdev->family == CHIP_RV380) || \ | |
1371 | (rdev->family == CHIP_R420) || \ | |
1372 | (rdev->family == CHIP_R423) || \ | |
1373 | (rdev->family == CHIP_RV410) || \ | |
1374 | (rdev->family == CHIP_RS400) || \ | |
1375 | (rdev->family == CHIP_RS480)) | |
3313e3d4 AD |
1376 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
1377 | (rdev->ddev->pdev->device == 0x9443) || \ | |
1378 | (rdev->ddev->pdev->device == 0x944B) || \ | |
1379 | (rdev->ddev->pdev->device == 0x9506) || \ | |
1380 | (rdev->ddev->pdev->device == 0x9509) || \ | |
1381 | (rdev->ddev->pdev->device == 0x950F) || \ | |
1382 | (rdev->ddev->pdev->device == 0x689C) || \ | |
1383 | (rdev->ddev->pdev->device == 0x689D)) | |
771fe6b9 | 1384 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
99999aaa AD |
1385 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
1386 | (rdev->family == CHIP_RS690) || \ | |
1387 | (rdev->family == CHIP_RS740) || \ | |
1388 | (rdev->family >= CHIP_R600)) | |
771fe6b9 JG |
1389 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
1390 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) | |
bcc1c2a1 | 1391 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
633b9164 AD |
1392 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
1393 | (rdev->flags & RADEON_IS_IGP)) | |
1fe18305 | 1394 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
771fe6b9 JG |
1395 | |
1396 | /* | |
1397 | * BIOS helpers. | |
1398 | */ | |
1399 | #define RBIOS8(i) (rdev->bios[i]) | |
1400 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) | |
1401 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) | |
1402 | ||
1403 | int radeon_combios_init(struct radeon_device *rdev); | |
1404 | void radeon_combios_fini(struct radeon_device *rdev); | |
1405 | int radeon_atombios_init(struct radeon_device *rdev); | |
1406 | void radeon_atombios_fini(struct radeon_device *rdev); | |
1407 | ||
1408 | ||
1409 | /* | |
1410 | * RING helpers. | |
1411 | */ | |
771fe6b9 JG |
1412 | static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
1413 | { | |
1414 | #if DRM_DEBUG_CODE | |
1415 | if (rdev->cp.count_dw <= 0) { | |
1416 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); | |
1417 | } | |
1418 | #endif | |
1419 | rdev->cp.ring[rdev->cp.wptr++] = v; | |
1420 | rdev->cp.wptr &= rdev->cp.ptr_mask; | |
1421 | rdev->cp.count_dw--; | |
1422 | rdev->cp.ring_free_dw--; | |
1423 | } | |
1424 | ||
1425 | ||
1426 | /* | |
1427 | * ASICs macro. | |
1428 | */ | |
068a117c | 1429 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
3ce0a23d JG |
1430 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
1431 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) | |
1432 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) | |
771fe6b9 | 1433 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
28d52043 | 1434 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
225758d8 | 1435 | #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev)) |
a2d07b74 | 1436 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
771fe6b9 JG |
1437 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
1438 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) | |
3ce0a23d | 1439 | #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
771fe6b9 | 1440 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
3ce0a23d JG |
1441 | #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) |
1442 | #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) | |
771fe6b9 JG |
1443 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
1444 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) | |
7ed220d7 | 1445 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
771fe6b9 JG |
1446 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
1447 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) | |
1448 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) | |
1449 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) | |
7433874e | 1450 | #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) |
771fe6b9 | 1451 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
7433874e | 1452 | #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) |
93e7de7b | 1453 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) |
c836a412 | 1454 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev)) |
771fe6b9 JG |
1455 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
1456 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) | |
e024e110 DA |
1457 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) |
1458 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) | |
c93bb85b | 1459 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
429770b3 AD |
1460 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) |
1461 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) | |
1462 | #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) | |
1463 | #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) | |
def9ba9c | 1464 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
a424816f AD |
1465 | #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev)) |
1466 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev)) | |
1467 | #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev)) | |
ce8f5370 AD |
1468 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev)) |
1469 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev)) | |
6f34be50 AD |
1470 | #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc)) |
1471 | #define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base)) | |
1472 | #define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc)) | |
771fe6b9 | 1473 | |
6cf8a3f5 | 1474 | /* Common functions */ |
700a0cc0 | 1475 | /* AGP */ |
90aca4d2 | 1476 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
700a0cc0 | 1477 | extern void radeon_agp_disable(struct radeon_device *rdev); |
4aac0473 | 1478 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
82568565 | 1479 | extern void radeon_gart_restore(struct radeon_device *rdev); |
21f9a437 JG |
1480 | extern int radeon_modeset_init(struct radeon_device *rdev); |
1481 | extern void radeon_modeset_fini(struct radeon_device *rdev); | |
9f022ddf | 1482 | extern bool radeon_card_posted(struct radeon_device *rdev); |
f47299c5 | 1483 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
f46c0120 | 1484 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
72542d77 | 1485 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
21f9a437 | 1486 | extern void radeon_scratch_init(struct radeon_device *rdev); |
724c80e1 AD |
1487 | extern void radeon_wb_fini(struct radeon_device *rdev); |
1488 | extern int radeon_wb_init(struct radeon_device *rdev); | |
1489 | extern void radeon_wb_disable(struct radeon_device *rdev); | |
21f9a437 JG |
1490 | extern void radeon_surface_init(struct radeon_device *rdev); |
1491 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); | |
ca6ffc64 | 1492 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
d39c3b89 | 1493 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
312ea8da | 1494 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
d03d8589 | 1495 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
d594e46a JG |
1496 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
1497 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); | |
6a9ee8af DA |
1498 | extern int radeon_resume_kms(struct drm_device *dev); |
1499 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); | |
53595338 | 1500 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
6cf8a3f5 | 1501 | |
3574dda4 DV |
1502 | /* |
1503 | * r600 functions used by radeon_encoder.c | |
1504 | */ | |
2cd6218c RM |
1505 | extern void r600_hdmi_enable(struct drm_encoder *encoder); |
1506 | extern void r600_hdmi_disable(struct drm_encoder *encoder); | |
dafc3bd5 | 1507 | extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
fe251e2f | 1508 | |
0af62b01 | 1509 | extern int ni_init_microcode(struct radeon_device *rdev); |
755d819e | 1510 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
0af62b01 | 1511 | |
d7a2952f AM |
1512 | /* radeon_acpi.c */ |
1513 | #if defined(CONFIG_ACPI) | |
1514 | extern int radeon_acpi_init(struct radeon_device *rdev); | |
1515 | #else | |
1516 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } | |
1517 | #endif | |
1518 | ||
4c788679 JG |
1519 | #include "radeon_object.h" |
1520 | ||
771fe6b9 | 1521 | #endif |