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drm/radeon: fix speaker allocation setup
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
0aea5e4a 67#include <linux/interval_tree.h>
341cb9e4 68#include <linux/hashtable.h>
954605ca 69#include <linux/fence.h>
771fe6b9 70
4c788679
JG		 71#include <ttm/ttm_bo_api.h>
72#include <ttm/ttm_bo_driver.h>
73#include <ttm/ttm_placement.h>
74#include <ttm/ttm_module.h>
147666fb 75#include <ttm/ttm_execbuf_util.h>
4c788679 76
d9fc9413
DV		 77#include <drm/drm_gem.h>
78
c2142715 79#include "radeon_family.h"
771fe6b9
JG		 80#include "radeon_mode.h"
81#include "radeon_reg.h"
771fe6b9
JG		 82
83/*
84 * Modules parameters.
85 */
86extern int radeon_no_wb;
87extern int radeon_modeset;
88extern int radeon_dynclks;
89extern int radeon_r4xx_atom;
90extern int radeon_agpmode;
91extern int radeon_vram_limit;
92extern int radeon_gart_size;
93extern int radeon_benchmarking;
ecc0b326 94extern int radeon_testing;
771fe6b9 95extern int radeon_connector_table;
4ce001ab 96extern int radeon_tv;
dafc3bd5 97extern int radeon_audio;
f46c0120 98extern int radeon_disp_priority;
e2b0a8e1 99extern int radeon_hw_i2c;
d42dd579 100extern int radeon_pcie_gen2;
a18cee15 101extern int radeon_msi;
3368ff0c 102extern int radeon_lockup_timeout;
a0a53aa8 103extern int radeon_fastfb;
da321c8a 104extern int radeon_dpm;
1294d4a3 105extern int radeon_aspm;
10ebc0bc 106extern int radeon_runtime_pm;
363eb0b4 107extern int radeon_hard_reset;
c1c44132 108extern int radeon_vm_size;
4510fb98 109extern int radeon_vm_block_size;
a624f429 110extern int radeon_deep_color;
39dc5454 111extern int radeon_use_pflipirq;
6e909f74 112extern int radeon_bapm;
771fe6b9
JG		 113
114/*
115 * Copy from radeon_drv.h so we don't have to include both and have conflicting
116 * symbol;
117 */
bb635567
JG		 118#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
119#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 120/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 121#define RADEON_IB_POOL_SIZE 16
122#define RADEON_DEBUGFS_MAX_COMPONENTS 32
123#define RADEONFB_CONN_LIMIT 4
124#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 125
1b37078b
AD		 126/* internal ring indices */
127/* r1xx+ has gfx CP ring */
d93f7937 128#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 129
130/* cayman has 2 compute CP rings */
d93f7937
CK		 131#define CAYMAN_RING_TYPE_CP1_INDEX 1
132#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 133
4d75658b
AD		 134/* R600+ has an async dma ring */
135#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 136/* cayman add a second async dma ring */
137#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 138
f2ba57b5 139/* R600+ */
d93f7937
CK		 140#define R600_RING_TYPE_UVD_INDEX 5
141
142/* TN+ */
143#define TN_RING_TYPE_VCE1_INDEX 6
144#define TN_RING_TYPE_VCE2_INDEX 7
145
146/* max number of rings */
147#define RADEON_NUM_RINGS 8
f2ba57b5 148
1c61eae4
CK		 149/* number of hw syncs before falling back on blocking */
150#define RADEON_NUM_SYNCS 4
f2ba57b5 151
8f53492f
CK		 152/* number of hw syncs before falling back on blocking */
153#define RADEON_NUM_SYNCS 4
154
721604a1 155/* hardcode those limit for now */
ca19f21e 156#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 157#define RADEON_VA_RESERVED_SIZE (8 << 20)
158#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 159
1a0041b8
AD		 160/* hard reset data */
161#define RADEON_ASIC_RESET_DATA 0x39d5e86b
162
ec46c76d
AD		 163/* reset flags */
164#define RADEON_RESET_GFX (1 << 0)
165#define RADEON_RESET_COMPUTE (1 << 1)
166#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 167#define RADEON_RESET_CP (1 << 3)
168#define RADEON_RESET_GRBM (1 << 4)
169#define RADEON_RESET_DMA1 (1 << 5)
170#define RADEON_RESET_RLC (1 << 6)
171#define RADEON_RESET_SEM (1 << 7)
172#define RADEON_RESET_IH (1 << 8)
173#define RADEON_RESET_VMC (1 << 9)
174#define RADEON_RESET_MC (1 << 10)
175#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 176
22c775ce
AD		 177/* CG block flags */
178#define RADEON_CG_BLOCK_GFX (1 << 0)
179#define RADEON_CG_BLOCK_MC (1 << 1)
180#define RADEON_CG_BLOCK_SDMA (1 << 2)
181#define RADEON_CG_BLOCK_UVD (1 << 3)
182#define RADEON_CG_BLOCK_VCE (1 << 4)
183#define RADEON_CG_BLOCK_HDP (1 << 5)
e16866ec 184#define RADEON_CG_BLOCK_BIF (1 << 6)
22c775ce 185
64d8a728
AD		 186/* CG flags */
187#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
188#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
189#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
190#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
191#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
192#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
193#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
194#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
195#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
196#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
197#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
198#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
199#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
200#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
201#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
202#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
203#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
204
205/* PG flags */
2b19d17f 206#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
64d8a728
AD		 207#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
208#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
209#define RADEON_PG_SUPPORT_UVD (1 << 3)
210#define RADEON_PG_SUPPORT_VCE (1 << 4)
211#define RADEON_PG_SUPPORT_CP (1 << 5)
212#define RADEON_PG_SUPPORT_GDS (1 << 6)
213#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
214#define RADEON_PG_SUPPORT_SDMA (1 << 8)
215#define RADEON_PG_SUPPORT_ACP (1 << 9)
216#define RADEON_PG_SUPPORT_SAMU (1 << 10)
217
9e05fa1d
AD		 218/* max cursor sizes (in pixels) */
219#define CURSOR_WIDTH 64
220#define CURSOR_HEIGHT 64
221
222#define CIK_CURSOR_WIDTH 128
223#define CIK_CURSOR_HEIGHT 128
224
771fe6b9
JG		 225/*
226 * Errata workarounds.
227 */
228enum radeon_pll_errata {
229 CHIP_ERRATA_R300_CG = 0x00000001,
230 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
231 CHIP_ERRATA_PLL_DELAY = 0x00000004
232};
233
234
235struct radeon_device;
236
237
238/*
239 * BIOS.
240 */
241bool radeon_get_bios(struct radeon_device *rdev);
242
243/*
3ce0a23d 244 * Dummy page
771fe6b9 245 */
3ce0a23d
JG		 246struct radeon_dummy_page {
247 struct page *page;
248 dma_addr_t addr;
249};
250int radeon_dummy_page_init(struct radeon_device *rdev);
251void radeon_dummy_page_fini(struct radeon_device *rdev);
252
771fe6b9 253
3ce0a23d
JG		 254/*
255 * Clocks
256 */
771fe6b9
JG		 257struct radeon_clock {
258 struct radeon_pll p1pll;
259 struct radeon_pll p2pll;
bcc1c2a1 260 struct radeon_pll dcpll;
771fe6b9
JG		 261 struct radeon_pll spll;
262 struct radeon_pll mpll;
263 /* 10 Khz units */
264 uint32_t default_mclk;
265 uint32_t default_sclk;
bcc1c2a1 266 uint32_t default_dispclk;
4489cd62 267 uint32_t current_dispclk;
bcc1c2a1 268 uint32_t dp_extclk;
b20f9bef 269 uint32_t max_pixel_clock;
771fe6b9
JG		 270};
271
7433874e
RM		 272/*
273 * Power management
274 */
275int radeon_pm_init(struct radeon_device *rdev);
914a8987 276int radeon_pm_late_init(struct radeon_device *rdev);
29fb52ca 277void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 278void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 279void radeon_pm_suspend(struct radeon_device *rdev);
280void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 281void radeon_combios_get_power_modes(struct radeon_device *rdev);
282void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 283int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
284 u8 clock_type,
285 u32 clock,
286 bool strobe_mode,
287 struct atom_clock_dividers *dividers);
eaa778af
AD		 288int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
289 u32 clock,
290 bool strobe_mode,
291 struct atom_mpll_param *mpll_param);
8a83ec5e 292void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 293int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
294 u16 voltage_level, u8 voltage_type,
295 u32 *gpio_value, u32 *gpio_mask);
296void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
297 u32 eng_clock, u32 mem_clock);
298int radeon_atom_get_voltage_step(struct radeon_device *rdev,
299 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 300int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
301 u16 voltage_id, u16 *voltage);
beb79f40
AD		 302int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
303 u16 *voltage,
304 u16 leakage_idx);
cc8dbbb4
AD		 305int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
306 u16 *leakage_id);
307int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
308 u16 *vddc, u16 *vddci,
309 u16 virtual_voltage_id,
310 u16 vbios_voltage_id);
e9f274b2
AD		 311int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
312 u16 virtual_voltage_id,
313 u16 *voltage);
ae5b0abb
AD		 314int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
315 u8 voltage_type,
316 u16 nominal_voltage,
317 u16 *true_voltage);
318int radeon_atom_get_min_voltage(struct radeon_device *rdev,
319 u8 voltage_type, u16 *min_voltage);
320int radeon_atom_get_max_voltage(struct radeon_device *rdev,
321 u8 voltage_type, u16 *max_voltage);
322int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 323 u8 voltage_type, u8 voltage_mode,
ae5b0abb 324 struct atom_voltage_table *voltage_table);
58653abd
AD		 325bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
326 u8 voltage_type, u8 voltage_mode);
636e2582
AD		 327int radeon_atom_get_svi2_info(struct radeon_device *rdev,
328 u8 voltage_type,
329 u8 *svd_gpio_id, u8 *svc_gpio_id);
ae5b0abb
AD		 330void radeon_atom_update_memory_dll(struct radeon_device *rdev,
331 u32 mem_clock);
332void radeon_atom_set_ac_timing(struct radeon_device *rdev,
333 u32 mem_clock);
334int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
335 u8 module_index,
336 struct atom_mc_reg_table *reg_table);
337int radeon_atom_get_memory_info(struct radeon_device *rdev,
338 u8 module_index, struct atom_memory_info *mem_info);
339int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
340 bool gddr5, u8 module_index,
341 struct atom_memory_clock_range_table *mclk_range_table);
342int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
343 u16 voltage_id, u16 *voltage);
f892034a 344void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 345extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
346 unsigned *bankh, unsigned *mtaspect,
347 unsigned *tile_split);
3ce0a23d 348
771fe6b9
JG		 349/*
350 * Fences.
351 */
352struct radeon_fence_driver {
0bfa4b41 353 struct radeon_device *rdev;
771fe6b9 354 uint32_t scratch_reg;
30eb77f4
JG		 355 uint64_t gpu_addr;
356 volatile uint32_t *cpu_addr;
68e250b7
CK		 357 /* sync_seq is protected by ring emission lock */
358 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 359 atomic64_t last_seq;
954605ca 360 bool initialized, delayed_irq;
0bfa4b41 361 struct delayed_work lockup_work;
771fe6b9
JG		 362};
363
364struct radeon_fence {
954605ca
ML		 365 struct fence base;
366
771fe6b9 367 struct radeon_device *rdev;
bb635567 368 uint64_t seq;
7465280c 369 /* RB, DMA, etc. */
bb635567 370 unsigned ring;
954605ca
ML		 371
372 wait_queue_t fence_wake;
771fe6b9
JG		 373};
374
30eb77f4
JG		 375int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
376int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 377void radeon_fence_driver_fini(struct radeon_device *rdev);
eb98c709 378void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
876dc9f3 379int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 380void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 381bool radeon_fence_signaled(struct radeon_fence *fence);
382int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
37615527
CK		 383int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
384int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
0085c950
JG		 385int radeon_fence_wait_any(struct radeon_device *rdev,
386 struct radeon_fence **fences,
387 bool intr);
771fe6b9
JG		 388struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
389void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 390unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 391bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
392void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
393static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
394 struct radeon_fence *b)
395{
396 if (!a) {
397 return b;
398 }
399
400 if (!b) {
401 return a;
402 }
403
404 BUG_ON(a->ring != b->ring);
405
406 if (a->seq > b->seq) {
407 return a;
408 } else {
409 return b;
410 }
411}
771fe6b9 412
ee60e29f
CK		 413static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
414 struct radeon_fence *b)
415{
416 if (!a) {
417 return false;
418 }
419
420 if (!b) {
421 return true;
422 }
423
424 BUG_ON(a->ring != b->ring);
425
426 return a->seq < b->seq;
427}
428
e024e110
DA		 429/*
430 * Tiling registers
431 */
432struct radeon_surface_reg {
4c788679 433 struct radeon_bo *bo;
e024e110
DA		 434};
435
436#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 437
438/*
4c788679 439 * TTM.
771fe6b9 440 */
4c788679
JG		 441struct radeon_mman {
442 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 443 struct drm_global_reference mem_global_ref;
4c788679 444 struct ttm_bo_device bdev;
0a0c7596
JG		 445 bool mem_global_referenced;
446 bool initialized;
2014b569
CK		 447
448#if defined(CONFIG_DEBUG_FS)
449 struct dentry *vram;
dd66d20e 450 struct dentry *gtt;
2014b569 451#endif
4c788679
JG		 452};
453
721604a1
JG		 454/* bo virtual address in a specific vm */
455struct radeon_bo_va {
e971bd5e 456 /* protected by bo being reserved */
721604a1 457 struct list_head bo_list;
721604a1 458 uint32_t flags;
e31ad969 459 uint64_t addr;
e971bd5e
CK		 460 unsigned ref_count;
461
462 /* protected by vm mutex */
0aea5e4a 463 struct interval_tree_node it;
036bf46a 464 struct list_head vm_status;
e971bd5e
CK		 465
466 /* constant after initialization */
467 struct radeon_vm *vm;
468 struct radeon_bo *bo;
721604a1
JG		 469};
470
4c788679
JG		 471struct radeon_bo {
472 /* Protected by gem.mutex */
473 struct list_head list;
474 /* Protected by tbo.reserved */
bda72d58 475 u32 initial_domain;
f1217ed0 476 struct ttm_place placements[3];
312ea8da 477 struct ttm_placement placement;
4c788679
JG		 478 struct ttm_buffer_object tbo;
479 struct ttm_bo_kmap_obj kmap;
02376d82 480 u32 flags;
4c788679
JG		 481 unsigned pin_count;
482 void *kptr;
483 u32 tiling_flags;
484 u32 pitch;
485 int surface_reg;
721604a1
JG		 486 /* list of all virtual address to which this bo
487 * is associated to
488 */
489 struct list_head va;
4c788679
JG		 490 /* Constant after initialization */
491 struct radeon_device *rdev;
441921d5 492 struct drm_gem_object gem_base;
63bc620b 493
409851f4
JG		 494 struct ttm_bo_kmap_obj dma_buf_vmap;
495 pid_t pid;
341cb9e4
CK		 496
497 struct radeon_mn *mn;
498 struct interval_tree_node mn_it;
4c788679 499};
7e4d15d9 500#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 501
409851f4
JG		 502int radeon_gem_debugfs_init(struct radeon_device *rdev);
503
b15ba512
JG		 504/* sub-allocation manager, it has to be protected by another lock.
505 * By conception this is an helper for other part of the driver
506 * like the indirect buffer or semaphore, which both have their
507 * locking.
508 *
509 * Principe is simple, we keep a list of sub allocation in offset
510 * order (first entry has offset == 0, last entry has the highest
511 * offset).
512 *
513 * When allocating new object we first check if there is room at
514 * the end total_size - (last_object_offset + last_object_size) >=
515 * alloc_size. If so we allocate new object there.
516 *
517 * When there is not enough room at the end, we start waiting for
518 * each sub object until we reach object_offset+object_size >=
519 * alloc_size, this object then become the sub object we return.
520 *
521 * Alignment can't be bigger than page size.
522 *
523 * Hole are not considered for allocation to keep things simple.
524 * Assumption is that there won't be hole (all object on same
525 * alignment).
526 */
527struct radeon_sa_manager {
bfb38d35 528 wait_queue_head_t wq;
b15ba512 529 struct radeon_bo *bo;
c3b7fe8b
CK		 530 struct list_head *hole;
531 struct list_head flist[RADEON_NUM_RINGS];
532 struct list_head olist;
b15ba512
JG		 533 unsigned size;
534 uint64_t gpu_addr;
535 void *cpu_ptr;
536 uint32_t domain;
6c4f978b 537 uint32_t align;
b15ba512
JG		 538};
539
540struct radeon_sa_bo;
541
542/* sub-allocation buffer */
543struct radeon_sa_bo {
c3b7fe8b
CK		 544 struct list_head olist;
545 struct list_head flist;
b15ba512 546 struct radeon_sa_manager *manager;
e6661a96
CK		 547 unsigned soffset;
548 unsigned eoffset;
557017a0 549 struct radeon_fence *fence;
b15ba512
JG		 550};
551
771fe6b9
JG		 552/*
553 * GEM objects.
554 */
555struct radeon_gem {
4c788679 556 struct mutex mutex;
771fe6b9
JG		 557 struct list_head objects;
558};
559
560int radeon_gem_init(struct radeon_device *rdev);
561void radeon_gem_fini(struct radeon_device *rdev);
391bfec3 562int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
4c788679 563 int alignment, int initial_domain,
ed5cb43f 564 u32 flags, bool kernel,
4c788679 565 struct drm_gem_object **obj);
771fe6b9 566
ff72145b
DA		 567int radeon_mode_dumb_create(struct drm_file *file_priv,
568 struct drm_device *dev,
569 struct drm_mode_create_dumb *args);
570int radeon_mode_dumb_mmap(struct drm_file *filp,
571 struct drm_device *dev,
572 uint32_t handle, uint64_t *offset_p);
771fe6b9 573
c1341e52
JG		 574/*
575 * Semaphores.
576 */
c1341e52 577struct radeon_semaphore {
a8c05940
JG		 578 struct radeon_sa_bo *sa_bo;
579 signed waiters;
c1341e52 580 uint64_t gpu_addr;
1654b817 581 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
c1341e52
JG		 582};
583
c1341e52
JG		 584int radeon_semaphore_create(struct radeon_device *rdev,
585 struct radeon_semaphore **semaphore);
1654b817 586bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
c1341e52 587 struct radeon_semaphore *semaphore);
1654b817 588bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
c1341e52 589 struct radeon_semaphore *semaphore);
57d20a43
CK		 590void radeon_semaphore_sync_fence(struct radeon_semaphore *semaphore,
591 struct radeon_fence *fence);
392a250b
ML		 592int radeon_semaphore_sync_resv(struct radeon_device *rdev,
593 struct radeon_semaphore *semaphore,
594 struct reservation_object *resv,
595 bool shared);
8f676c4c
CK		 596int radeon_semaphore_sync_rings(struct radeon_device *rdev,
597 struct radeon_semaphore *semaphore,
1654b817 598 int waiting_ring);
c1341e52 599void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 600 struct radeon_semaphore **semaphore,
a8c05940 601 struct radeon_fence *fence);
c1341e52 602
771fe6b9
JG		 603/*
604 * GART structures, functions & helpers
605 */
606struct radeon_mc;
607
a77f1718 608#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 609#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 610#define RADEON_GPU_PAGE_SHIFT 12
721604a1 611#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 612
77497f27
MD		 613#define RADEON_GART_PAGE_DUMMY 0
614#define RADEON_GART_PAGE_VALID (1 << 0)
615#define RADEON_GART_PAGE_READ (1 << 1)
616#define RADEON_GART_PAGE_WRITE (1 << 2)
617#define RADEON_GART_PAGE_SNOOP (1 << 3)
618
771fe6b9
JG		 619struct radeon_gart {
620 dma_addr_t table_addr;
c9a1be96
JG		 621 struct radeon_bo *robj;
622 void *ptr;
771fe6b9
JG		 623 unsigned num_gpu_pages;
624 unsigned num_cpu_pages;
625 unsigned table_size;
771fe6b9
JG		 626 struct page **pages;
627 dma_addr_t *pages_addr;
628 bool ready;
629};
630
631int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
632void radeon_gart_table_ram_free(struct radeon_device *rdev);
633int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
634void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 635int radeon_gart_table_vram_pin(struct radeon_device *rdev);
636void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 637int radeon_gart_init(struct radeon_device *rdev);
638void radeon_gart_fini(struct radeon_device *rdev);
639void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
640 int pages);
641int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516 642 int pages, struct page **pagelist,
77497f27 643 dma_addr_t *dma_addr, uint32_t flags);
771fe6b9
JG		 644
645
646/*
647 * GPU MC structures, functions & helpers
648 */
649struct radeon_mc {
650 resource_size_t aper_size;
651 resource_size_t aper_base;
652 resource_size_t agp_base;
7a50f01a
DA		 653 /* for some chips with <= 32MB we need to lie
654 * about vram size near mc fb location */
3ce0a23d 655 u64 mc_vram_size;
d594e46a 656 u64 visible_vram_size;
3ce0a23d
JG		 657 u64 gtt_size;
658 u64 gtt_start;
659 u64 gtt_end;
3ce0a23d
JG		 660 u64 vram_start;
661 u64 vram_end;
771fe6b9 662 unsigned vram_width;
3ce0a23d 663 u64 real_vram_size;
771fe6b9
JG		 664 int vram_mtrr;
665 bool vram_is_ddr;
d594e46a 666 bool igp_sideport_enabled;
8d369bb1 667 u64 gtt_base_align;
9ed8b1f9 668 u64 mc_mask;
771fe6b9
JG		 669};
670
06b6476d
AD		 671bool radeon_combios_sideport_present(struct radeon_device *rdev);
672bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 673
674/*
675 * GPU scratch registers structures, functions & helpers
676 */
677struct radeon_scratch {
678 unsigned num_reg;
724c80e1 679 uint32_t reg_base;
771fe6b9
JG		 680 bool free[32];
681 uint32_t reg[32];
682};
683
684int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
685void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
686
75efdee1
AD		 687/*
688 * GPU doorbell structures, functions & helpers
689 */
d5754ab8
AL		 690#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
691
75efdee1 692struct radeon_doorbell {
75efdee1 693 /* doorbell mmio */
d5754ab8
AL		 694 resource_size_t base;
695 resource_size_t size;
696 u32 __iomem *ptr;
697 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
698 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
75efdee1
AD		 699};
700
701int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
702void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771fe6b9
JG		 703
704/*
705 * IRQS.
706 */
6f34be50 707
fa7f517c
CK		 708struct radeon_flip_work {
709 struct work_struct flip_work;
710 struct work_struct unpin_work;
711 struct radeon_device *rdev;
712 int crtc_id;
c60381bd 713 uint64_t base;
6f34be50 714 struct drm_pending_vblank_event *event;
fa7f517c 715 struct radeon_bo *old_rbo;
a0e84764 716 struct fence *fence;
6f34be50
AD		 717};
718
719struct r500_irq_stat_regs {
720 u32 disp_int;
f122c610 721 u32 hdmi0_status;
6f34be50
AD		 722};
723
724struct r600_irq_stat_regs {
725 u32 disp_int;
726 u32 disp_int_cont;
727 u32 disp_int_cont2;
728 u32 d1grph_int;
729 u32 d2grph_int;
f122c610
AD		 730 u32 hdmi0_status;
731 u32 hdmi1_status;
6f34be50
AD		 732};
733
734struct evergreen_irq_stat_regs {
735 u32 disp_int;
736 u32 disp_int_cont;
737 u32 disp_int_cont2;
738 u32 disp_int_cont3;
739 u32 disp_int_cont4;
740 u32 disp_int_cont5;
741 u32 d1grph_int;
742 u32 d2grph_int;
743 u32 d3grph_int;
744 u32 d4grph_int;
745 u32 d5grph_int;
746 u32 d6grph_int;
f122c610
AD		 747 u32 afmt_status1;
748 u32 afmt_status2;
749 u32 afmt_status3;
750 u32 afmt_status4;
751 u32 afmt_status5;
752 u32 afmt_status6;
6f34be50
AD		 753};
754
a59781bb
AD		 755struct cik_irq_stat_regs {
756 u32 disp_int;
757 u32 disp_int_cont;
758 u32 disp_int_cont2;
759 u32 disp_int_cont3;
760 u32 disp_int_cont4;
761 u32 disp_int_cont5;
762 u32 disp_int_cont6;
f5d636d2
CK		 763 u32 d1grph_int;
764 u32 d2grph_int;
765 u32 d3grph_int;
766 u32 d4grph_int;
767 u32 d5grph_int;
768 u32 d6grph_int;
a59781bb
AD		 769};
770
6f34be50
AD		 771union radeon_irq_stat_regs {
772 struct r500_irq_stat_regs r500;
773 struct r600_irq_stat_regs r600;
774 struct evergreen_irq_stat_regs evergreen;
a59781bb 775 struct cik_irq_stat_regs cik;
6f34be50
AD		 776};
777
771fe6b9 778struct radeon_irq {
fb98257a
CK		 779 bool installed;
780 spinlock_t lock;
736fc37f 781 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 782 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 783 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 784 wait_queue_head_t vblank_queue;
785 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 786 bool afmt[RADEON_MAX_AFMT_BLOCKS];
787 union radeon_irq_stat_regs stat_regs;
4a6369e9 788 bool dpm_thermal;
771fe6b9
JG		 789};
790
791int radeon_irq_kms_init(struct radeon_device *rdev);
792void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b 793void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
954605ca 794bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
1b37078b 795void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 796void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
797void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 798void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
799void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
800void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
801void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 802
803/*
e32eb50d 804 * CP & rings.
771fe6b9 805 */
7465280c 806
771fe6b9 807struct radeon_ib {
68470ae7
JG		 808 struct radeon_sa_bo *sa_bo;
809 uint32_t length_dw;
810 uint64_t gpu_addr;
811 uint32_t *ptr;
876dc9f3 812 int ring;
68470ae7 813 struct radeon_fence *fence;
4bf3dd92 814 struct radeon_vm *vm;
68470ae7
JG		 815 bool is_const_ib;
816 struct radeon_semaphore *semaphore;
771fe6b9
JG		 817};
818
e32eb50d 819struct radeon_ring {
4c788679 820 struct radeon_bo *ring_obj;
771fe6b9 821 volatile uint32_t *ring;
5596a9db 822 unsigned rptr_offs;
45df6803 823 unsigned rptr_save_reg;
89d35807
AD		 824 u64 next_rptr_gpu_addr;
825 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 826 unsigned wptr;
827 unsigned wptr_old;
828 unsigned ring_size;
829 unsigned ring_free_dw;
830 int count_dw;
aee4aa73
CK		 831 atomic_t last_rptr;
832 atomic64_t last_activity;
771fe6b9
JG		 833 uint64_t gpu_addr;
834 uint32_t align_mask;
835 uint32_t ptr_mask;
771fe6b9 836 bool ready;
78c5560a 837 u32 nop;
8b25ed34 838 u32 idx;
5f0839c1
JG		 839 u64 last_semaphore_signal_addr;
840 u64 last_semaphore_wait_addr;
963e81f9
AD		 841 /* for CIK queues */
842 u32 me;
843 u32 pipe;
844 u32 queue;
845 struct radeon_bo *mqd_obj;
d5754ab8 846 u32 doorbell_index;
963e81f9
AD		 847 unsigned wptr_offs;
848};
849
850struct radeon_mec {
851 struct radeon_bo *hpd_eop_obj;
852 u64 hpd_eop_gpu_addr;
853 u32 num_pipe;
854 u32 num_mec;
855 u32 num_queue;
771fe6b9
JG		 856};
857
721604a1
JG		 858/*
859 * VM
860 */
ee60e29f 861
fa87e62d 862/* maximum number of VMIDs */
ee60e29f
CK		 863#define RADEON_NUM_VM 16
864
fa87e62d 865/* number of entries in page table */
4510fb98 866#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
fa87e62d 867
1c01103c
AD		 868/* PTBs (Page Table Blocks) need to be aligned to 32K */
869#define RADEON_VM_PTB_ALIGN_SIZE 32768
870#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
871#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
872
24c16439
CK		 873#define R600_PTE_VALID (1 << 0)
874#define R600_PTE_SYSTEM (1 << 1)
875#define R600_PTE_SNOOPED (1 << 2)
876#define R600_PTE_READABLE (1 << 5)
877#define R600_PTE_WRITEABLE (1 << 6)
878
ec3dbbcb
CK		 879/* PTE (Page Table Entry) fragment field for different page sizes */
880#define R600_PTE_FRAG_4KB (0 << 7)
881#define R600_PTE_FRAG_64KB (4 << 7)
882#define R600_PTE_FRAG_256KB (6 << 7)
883
33fa9fe3
CK		 884/* flags needed to be set so we can copy directly from the GART table */
885#define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
886 R600_PTE_SYSTEM | R600_PTE_VALID )
0e97703c 887
6d2f2944
CK		 888struct radeon_vm_pt {
889 struct radeon_bo *bo;
890 uint64_t addr;
891};
892
721604a1 893struct radeon_vm {
0aea5e4a 894 struct rb_root va;
ee60e29f 895 unsigned id;
90a51a32 896
e31ad969
CK		 897 /* BOs moved, but not yet updated in the PT */
898 struct list_head invalidated;
899
036bf46a
CK		 900 /* BOs freed, but not yet updated in the PT */
901 struct list_head freed;
902
90a51a32 903 /* contains the page directory */
6d2f2944 904 struct radeon_bo *page_directory;
90a51a32 905 uint64_t pd_gpu_addr;
6d2f2944 906 unsigned max_pde_used;
90a51a32
CK		 907
908 /* array of page tables, one for each page directory entry */
6d2f2944 909 struct radeon_vm_pt *page_tables;
90a51a32 910
cc9e67e3
CK		 911 struct radeon_bo_va *ib_bo_va;
912
721604a1
JG		 913 struct mutex mutex;
914 /* last fence for cs using this vm */
915 struct radeon_fence *fence;
9b40e5d8
CK		 916 /* last flush or NULL if we still need to flush */
917 struct radeon_fence *last_flush;
593b2635
CK		 918 /* last use of vmid */
919 struct radeon_fence *last_id_use;
721604a1
JG		 920};
921
721604a1 922struct radeon_vm_manager {
ee60e29f 923 struct radeon_fence *active[RADEON_NUM_VM];
721604a1 924 uint32_t max_pfn;
721604a1
JG		 925 /* number of VMIDs */
926 unsigned nvm;
927 /* vram base address for page table entry */
928 u64 vram_base_offset;
67e915e4
AD		 929 /* is vm enabled? */
930 bool enabled;
054e01d6
CK		 931 /* for hw to save the PD addr on suspend/resume */
932 uint32_t saved_table_addr[RADEON_NUM_VM];
721604a1
JG		 933};
934
935/*
936 * file private structure
937 */
938struct radeon_fpriv {
939 struct radeon_vm vm;
940};
941
d8f60cfc
AD		 942/*
943 * R6xx+ IH ring
944 */
945struct r600_ih {
4c788679 946 struct radeon_bo *ring_obj;
d8f60cfc
AD		 947 volatile uint32_t *ring;
948 unsigned rptr;
d8f60cfc
AD		 949 unsigned ring_size;
950 uint64_t gpu_addr;
d8f60cfc 951 uint32_t ptr_mask;
c20dc369 952 atomic_t lock;
d8f60cfc
AD		 953 bool enabled;
954};
955
347e7592 956/*
2948f5e6 957 * RLC stuff
347e7592 958 */
2948f5e6
AD		 959#include "clearstate_defs.h"
960
961struct radeon_rlc {
347e7592
AD		 962 /* for power gating */
963 struct radeon_bo *save_restore_obj;
964 uint64_t save_restore_gpu_addr;
2948f5e6 965 volatile uint32_t *sr_ptr;
1fd11777 966 const u32 *reg_list;
2948f5e6 967 u32 reg_list_size;
347e7592
AD		 968 /* for clear state */
969 struct radeon_bo *clear_state_obj;
970 uint64_t clear_state_gpu_addr;
2948f5e6 971 volatile uint32_t *cs_ptr;
1fd11777 972 const struct cs_section_def *cs_data;
22c775ce
AD		 973 u32 clear_state_size;
974 /* for cp tables */
975 struct radeon_bo *cp_table_obj;
976 uint64_t cp_table_gpu_addr;
977 volatile uint32_t *cp_table_ptr;
978 u32 cp_table_size;
347e7592
AD		 979};
980
69e130a6 981int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 982 struct radeon_ib *ib, struct radeon_vm *vm,
983 unsigned size);
f2e39221 984void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
4ef72566 985int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1538a9e0 986 struct radeon_ib *const_ib, bool hdp_flush);
771fe6b9
JG		 987int radeon_ib_pool_init(struct radeon_device *rdev);
988void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 989int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 990/* Ring access between begin & end cannot sleep */
89d35807
AD		 991bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
992 struct radeon_ring *ring);
e32eb50d
CK		 993void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
994int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
995int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1538a9e0
MD		 996void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
997 bool hdp_flush);
998void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
999 bool hdp_flush);
d6999bc7 1000void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 1001void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1002int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
ff212f25
CK		 1003void radeon_ring_lockup_update(struct radeon_device *rdev,
1004 struct radeon_ring *ring);
069211e5 1005bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 1006unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1007 uint32_t **data);
1008int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1009 unsigned size, uint32_t *data);
e32eb50d 1010int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
ea31bf69 1011 unsigned rptr_offs, u32 nop);
e32eb50d 1012void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 1013
1014
4d75658b
AD		 1015/* r600 async dma */
1016void r600_dma_stop(struct radeon_device *rdev);
1017int r600_dma_resume(struct radeon_device *rdev);
1018void r600_dma_fini(struct radeon_device *rdev);
1019
8c5fd7ef
AD		 1020void cayman_dma_stop(struct radeon_device *rdev);
1021int cayman_dma_resume(struct radeon_device *rdev);
1022void cayman_dma_fini(struct radeon_device *rdev);
1023
771fe6b9
JG		 1024/*
1025 * CS.
1026 */
1027struct radeon_cs_reloc {
1028 struct drm_gem_object *gobj;
4c788679 1029 struct radeon_bo *robj;
df0af440
CK		 1030 struct ttm_validate_buffer tv;
1031 uint64_t gpu_offset;
ce6758c8
CK		 1032 unsigned prefered_domains;
1033 unsigned allowed_domains;
df0af440 1034 uint32_t tiling_flags;
771fe6b9 1035 uint32_t handle;
771fe6b9
JG		 1036};
1037
1038struct radeon_cs_chunk {
1039 uint32_t chunk_id;
1040 uint32_t length_dw;
1041 uint32_t *kdata;
721604a1 1042 void __user *user_ptr;
771fe6b9
JG		 1043};
1044
1045struct radeon_cs_parser {
c8c15ff1 1046 struct device *dev;
771fe6b9
JG		 1047 struct radeon_device *rdev;
1048 struct drm_file *filp;
1049 /* chunks */
1050 unsigned nchunks;
1051 struct radeon_cs_chunk *chunks;
1052 uint64_t *chunks_array;
1053 /* IB */
1054 unsigned idx;
1055 /* relocations */
1056 unsigned nrelocs;
1057 struct radeon_cs_reloc *relocs;
1058 struct radeon_cs_reloc **relocs_ptr;
df0af440 1059 struct radeon_cs_reloc *vm_bos;
771fe6b9 1060 struct list_head validated;
cf4ccd01 1061 unsigned dma_reloc_idx;
771fe6b9
JG		 1062 /* indices of various chunks */
1063 int chunk_ib_idx;
1064 int chunk_relocs_idx;
721604a1 1065 int chunk_flags_idx;
dfcf5f36 1066 int chunk_const_ib_idx;
f2e39221
JG		 1067 struct radeon_ib ib;
1068 struct radeon_ib const_ib;
771fe6b9 1069 void *track;
3ce0a23d 1070 unsigned family;
e70f224c 1071 int parser_error;
721604a1
JG		 1072 u32 cs_flags;
1073 u32 ring;
1074 s32 priority;
ecff665f 1075 struct ww_acquire_ctx ticket;
771fe6b9
JG		 1076};
1077
28a326c5
ML		 1078static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1079{
1080 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1081
1082 if (ibc->kdata)
1083 return ibc->kdata[idx];
1084 return p->ib.ptr[idx];
1085}
1086
513bcb46 1087
771fe6b9
JG		 1088struct radeon_cs_packet {
1089 unsigned idx;
1090 unsigned type;
1091 unsigned reg;
1092 unsigned opcode;
1093 int count;
1094 unsigned one_reg_wr;
1095};
1096
1097typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1098 struct radeon_cs_packet *pkt,
1099 unsigned idx, unsigned reg);
1100typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1101 struct radeon_cs_packet *pkt);
1102
1103
1104/*
1105 * AGP
1106 */
1107int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1108void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1109void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1110void radeon_agp_fini(struct radeon_device *rdev);
1111
1112
1113/*
1114 * Writeback
1115 */
1116struct radeon_wb {
4c788679 1117 struct radeon_bo *wb_obj;
771fe6b9
JG		 1118 volatile uint32_t *wb;
1119 uint64_t gpu_addr;
724c80e1 1120 bool enabled;
d0f8a854 1121 bool use_event;
771fe6b9
JG		 1122};
1123
724c80e1 1124#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1125#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1126#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1127#define RADEON_WB_CP1_RPTR_OFFSET 1280
1128#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1129#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1130#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1131#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1132#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1133#define CIK_WB_CP1_WPTR_OFFSET 3328
1134#define CIK_WB_CP2_WPTR_OFFSET 3584
724c80e1 1135
c93bb85b
JG		 1136/**
1137 * struct radeon_pm - power management datas
1138 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1139 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1140 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1141 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1142 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1143 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1144 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1145 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1146 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1147 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1148 * @needed_bandwidth: current bandwidth needs
1149 *
1150 * It keeps track of various data needed to take powermanagement decision.
25985edc 1151 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1152 * Equation between gpu/memory clock and available bandwidth is hw dependent
1153 * (type of memory, bus size, efficiency, ...)
1154 */
ce8f5370
AD		 1155
1156enum radeon_pm_method {
1157 PM_METHOD_PROFILE,
1158 PM_METHOD_DYNPM,
da321c8a 1159 PM_METHOD_DPM,
ce8f5370
AD		 1160};
1161
1162enum radeon_dynpm_state {
1163 DYNPM_STATE_DISABLED,
1164 DYNPM_STATE_MINIMUM,
1165 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1166 DYNPM_STATE_ACTIVE,
1167 DYNPM_STATE_SUSPENDED,
c913e23a 1168};
ce8f5370
AD		 1169enum radeon_dynpm_action {
1170 DYNPM_ACTION_NONE,
1171 DYNPM_ACTION_MINIMUM,
1172 DYNPM_ACTION_DOWNCLOCK,
1173 DYNPM_ACTION_UPCLOCK,
1174 DYNPM_ACTION_DEFAULT
c913e23a 1175};
56278a8e
AD		 1176
1177enum radeon_voltage_type {
1178 VOLTAGE_NONE = 0,
1179 VOLTAGE_GPIO,
1180 VOLTAGE_VDDC,
1181 VOLTAGE_SW
1182};
1183
0ec0e74f 1184enum radeon_pm_state_type {
da321c8a 1185 /* not used for dpm */
0ec0e74f
AD		 1186 POWER_STATE_TYPE_DEFAULT,
1187 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1188 /* user selectable states */
0ec0e74f
AD		 1189 POWER_STATE_TYPE_BATTERY,
1190 POWER_STATE_TYPE_BALANCED,
1191 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1192 /* internal states */
1193 POWER_STATE_TYPE_INTERNAL_UVD,
1194 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1195 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1196 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1197 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1198 POWER_STATE_TYPE_INTERNAL_BOOT,
1199 POWER_STATE_TYPE_INTERNAL_THERMAL,
1200 POWER_STATE_TYPE_INTERNAL_ACPI,
1201 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1202 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1203};
1204
ce8f5370
AD		 1205enum radeon_pm_profile_type {
1206 PM_PROFILE_DEFAULT,
1207 PM_PROFILE_AUTO,
1208 PM_PROFILE_LOW,
c9e75b21 1209 PM_PROFILE_MID,
ce8f5370
AD		 1210 PM_PROFILE_HIGH,
1211};
1212
1213#define PM_PROFILE_DEFAULT_IDX 0
1214#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1215#define PM_PROFILE_MID_SH_IDX 2
1216#define PM_PROFILE_HIGH_SH_IDX 3
1217#define PM_PROFILE_LOW_MH_IDX 4
1218#define PM_PROFILE_MID_MH_IDX 5
1219#define PM_PROFILE_HIGH_MH_IDX 6
1220#define PM_PROFILE_MAX 7
ce8f5370
AD		 1221
1222struct radeon_pm_profile {
1223 int dpms_off_ps_idx;
1224 int dpms_on_ps_idx;
1225 int dpms_off_cm_idx;
1226 int dpms_on_cm_idx;
516d0e46
AD		 1227};
1228
21a8122a
AD		 1229enum radeon_int_thermal_type {
1230 THERMAL_TYPE_NONE,
da321c8a
AD		 1231 THERMAL_TYPE_EXTERNAL,
1232 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1233 THERMAL_TYPE_RV6XX,
1234 THERMAL_TYPE_RV770,
da321c8a 1235 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1236 THERMAL_TYPE_EVERGREEN,
e33df25f 1237 THERMAL_TYPE_SUMO,
4fddba1f 1238 THERMAL_TYPE_NI,
14607d08 1239 THERMAL_TYPE_SI,
da321c8a 1240 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1241 THERMAL_TYPE_CI,
16fbe00d 1242 THERMAL_TYPE_KV,
21a8122a
AD		 1243};
1244
56278a8e
AD		 1245struct radeon_voltage {
1246 enum radeon_voltage_type type;
1247 /* gpio voltage */
1248 struct radeon_gpio_rec gpio;
1249 u32 delay; /* delay in usec from voltage drop to sclk change */
1250 bool active_high; /* voltage drop is active when bit is high */
1251 /* VDDC voltage */
1252 u8 vddc_id; /* index into vddc voltage table */
1253 u8 vddci_id; /* index into vddci voltage table */
1254 bool vddci_enabled;
1255 /* r6xx+ sw */
2feea49a
AD		 1256 u16 voltage;
1257 /* evergreen+ vddci */
1258 u16 vddci;
56278a8e
AD		 1259};
1260
d7311171
AD		 1261/* clock mode flags */
1262#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1263
56278a8e
AD		 1264struct radeon_pm_clock_info {
1265 /* memory clock */
1266 u32 mclk;
1267 /* engine clock */
1268 u32 sclk;
1269 /* voltage info */
1270 struct radeon_voltage voltage;
d7311171 1271 /* standardized clock flags */
56278a8e
AD		 1272 u32 flags;
1273};
1274
a48b9b4e 1275/* state flags */
d7311171 1276#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1277
56278a8e 1278struct radeon_power_state {
0ec0e74f 1279 enum radeon_pm_state_type type;
8f3f1c9a 1280 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1281 /* number of valid clock modes in this power state */
1282 int num_clock_modes;
56278a8e 1283 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1284 /* standardized state flags */
1285 u32 flags;
79daedc9
AD		 1286 u32 misc; /* vbios specific flags */
1287 u32 misc2; /* vbios specific flags */
1288 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1289};
1290
27459324
RM		 1291/*
1292 * Some modes are overclocked by very low value, accept them
1293 */
1294#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1295
2e9d4c05
AD		 1296enum radeon_dpm_auto_throttle_src {
1297 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1298 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1299};
1300
1301enum radeon_dpm_event_src {
1302 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1303 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1304 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1305 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1306 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1307};
1308
58bd2a88
AD		 1309#define RADEON_MAX_VCE_LEVELS 6
1310
b62d628b
AD		 1311enum radeon_vce_level {
1312 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1313 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1314 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1315 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1316 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1317 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1318};
1319
da321c8a
AD		 1320struct radeon_ps {
1321 u32 caps; /* vbios flags */
1322 u32 class; /* vbios flags */
1323 u32 class2; /* vbios flags */
1324 /* UVD clocks */
1325 u32 vclk;
1326 u32 dclk;
c4453e66
AD		 1327 /* VCE clocks */
1328 u32 evclk;
1329 u32 ecclk;
b62d628b
AD		 1330 bool vce_active;
1331 enum radeon_vce_level vce_level;
da321c8a
AD		 1332 /* asic priv */
1333 void *ps_priv;
1334};
1335
1336struct radeon_dpm_thermal {
1337 /* thermal interrupt work */
1338 struct work_struct work;
1339 /* low temperature threshold */
1340 int min_temp;
1341 /* high temperature threshold */
1342 int max_temp;
1343 /* was interrupt low to high or high to low */
1344 bool high_to_low;
1345};
1346
d22b7e40
AD		 1347enum radeon_clk_action
1348{
1349 RADEON_SCLK_UP = 1,
1350 RADEON_SCLK_DOWN
1351};
1352
1353struct radeon_blacklist_clocks
1354{
1355 u32 sclk;
1356 u32 mclk;
1357 enum radeon_clk_action action;
1358};
1359
61b7d601
AD		 1360struct radeon_clock_and_voltage_limits {
1361 u32 sclk;
1362 u32 mclk;
cdf6e805
AD		 1363 u16 vddc;
1364 u16 vddci;
61b7d601
AD		 1365};
1366
1367struct radeon_clock_array {
1368 u32 count;
1369 u32 *values;
1370};
1371
1372struct radeon_clock_voltage_dependency_entry {
1373 u32 clk;
1374 u16 v;
1375};
1376
1377struct radeon_clock_voltage_dependency_table {
1378 u32 count;
1379 struct radeon_clock_voltage_dependency_entry *entries;
1380};
1381
ef976ec4
AD		 1382union radeon_cac_leakage_entry {
1383 struct {
1384 u16 vddc;
1385 u32 leakage;
1386 };
1387 struct {
1388 u16 vddc1;
1389 u16 vddc2;
1390 u16 vddc3;
1391 };
61b7d601
AD		 1392};
1393
1394struct radeon_cac_leakage_table {
1395 u32 count;
ef976ec4 1396 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1397};
1398
929ee7a8
AD		 1399struct radeon_phase_shedding_limits_entry {
1400 u16 voltage;
1401 u32 sclk;
1402 u32 mclk;
1403};
1404
1405struct radeon_phase_shedding_limits_table {
1406 u32 count;
1407 struct radeon_phase_shedding_limits_entry *entries;
1408};
1409
84a9d9ee
AD		 1410struct radeon_uvd_clock_voltage_dependency_entry {
1411 u32 vclk;
1412 u32 dclk;
1413 u16 v;
1414};
1415
1416struct radeon_uvd_clock_voltage_dependency_table {
1417 u8 count;
1418 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1419};
1420
d29f013b
AD		 1421struct radeon_vce_clock_voltage_dependency_entry {
1422 u32 ecclk;
1423 u32 evclk;
1424 u16 v;
1425};
1426
1427struct radeon_vce_clock_voltage_dependency_table {
1428 u8 count;
1429 struct radeon_vce_clock_voltage_dependency_entry *entries;
1430};
1431
a5cb318e
AD		 1432struct radeon_ppm_table {
1433 u8 ppm_design;
1434 u16 cpu_core_number;
1435 u32 platform_tdp;
1436 u32 small_ac_platform_tdp;
1437 u32 platform_tdc;
1438 u32 small_ac_platform_tdc;
1439 u32 apu_tdp;
1440 u32 dgpu_tdp;
1441 u32 dgpu_ulv_power;
1442 u32 tj_max;
1443};
1444
58cb7632
AD		 1445struct radeon_cac_tdp_table {
1446 u16 tdp;
1447 u16 configurable_tdp;
1448 u16 tdc;
1449 u16 battery_power_limit;
1450 u16 small_power_limit;
1451 u16 low_cac_leakage;
1452 u16 high_cac_leakage;
1453 u16 maximum_power_delivery_limit;
1454};
1455
61b7d601
AD		 1456struct radeon_dpm_dynamic_state {
1457 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1458 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1459 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1460 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1461 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1462 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1463 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1464 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1465 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1466 struct radeon_clock_array valid_sclk_values;
1467 struct radeon_clock_array valid_mclk_values;
1468 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1469 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1470 u32 mclk_sclk_ratio;
1471 u32 sclk_mclk_delta;
1472 u16 vddc_vddci_delta;
1473 u16 min_vddc_for_pcie_gen2;
1474 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1475 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1476 struct radeon_ppm_table *ppm_table;
58cb7632 1477 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1478};
1479
1480struct radeon_dpm_fan {
1481 u16 t_min;
1482 u16 t_med;
1483 u16 t_high;
1484 u16 pwm_min;
1485 u16 pwm_med;
1486 u16 pwm_high;
1487 u8 t_hyst;
1488 u32 cycle_delay;
1489 u16 t_max;
1490 bool ucode_fan_control;
1491};
1492
32ce4652
AD		 1493enum radeon_pcie_gen {
1494 RADEON_PCIE_GEN1 = 0,
1495 RADEON_PCIE_GEN2 = 1,
1496 RADEON_PCIE_GEN3 = 2,
1497 RADEON_PCIE_GEN_INVALID = 0xffff
1498};
1499
70d01a5e
AD		 1500enum radeon_dpm_forced_level {
1501 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1502 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1503 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1504};
1505
58bd2a88
AD		 1506struct radeon_vce_state {
1507 /* vce clocks */
1508 u32 evclk;
1509 u32 ecclk;
1510 /* gpu clocks */
1511 u32 sclk;
1512 u32 mclk;
1513 u8 clk_idx;
1514 u8 pstate;
1515};
1516
da321c8a
AD		 1517struct radeon_dpm {
1518 struct radeon_ps *ps;
1519 /* number of valid power states */
1520 int num_ps;
1521 /* current power state that is active */
1522 struct radeon_ps *current_ps;
1523 /* requested power state */
1524 struct radeon_ps *requested_ps;
1525 /* boot up power state */
1526 struct radeon_ps *boot_ps;
1527 /* default uvd power state */
1528 struct radeon_ps *uvd_ps;
58bd2a88
AD		 1529 /* vce requirements */
1530 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1531 enum radeon_vce_level vce_level;
da321c8a
AD		 1532 enum radeon_pm_state_type state;
1533 enum radeon_pm_state_type user_state;
1534 u32 platform_caps;
1535 u32 voltage_response_time;
1536 u32 backbias_response_time;
1537 void *priv;
1538 u32 new_active_crtcs;
1539 int new_active_crtc_count;
1540 u32 current_active_crtcs;
1541 int current_active_crtc_count;
61b7d601
AD		 1542 struct radeon_dpm_dynamic_state dyn_state;
1543 struct radeon_dpm_fan fan;
1544 u32 tdp_limit;
1545 u32 near_tdp_limit;
a9e61410 1546 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1547 u32 sq_ramping_threshold;
1548 u32 cac_leakage;
1549 u16 tdp_od_limit;
1550 u32 tdp_adjustment;
1551 u16 load_line_slope;
1552 bool power_control;
5ca302f7 1553 bool ac_power;
da321c8a
AD		 1554 /* special states active */
1555 bool thermal_active;
8a227555 1556 bool uvd_active;
b62d628b 1557 bool vce_active;
da321c8a
AD		 1558 /* thermal handling */
1559 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1560 /* forced levels */
1561 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1562 /* track UVD streams */
1563 unsigned sd;
1564 unsigned hd;
da321c8a
AD		 1565};
1566
ce3537d5 1567void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
03afe6f6 1568void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
da321c8a 1569
c93bb85b 1570struct radeon_pm {
c913e23a 1571 struct mutex mutex;
db7fce39
CK		 1572 /* write locked while reprogramming mclk */
1573 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1574 u32 active_crtcs;
1575 int active_crtc_count;
c913e23a 1576 int req_vblank;
839461d3 1577 bool vblank_sync;
c93bb85b
JG		 1578 fixed20_12 max_bandwidth;
1579 fixed20_12 igp_sideport_mclk;
1580 fixed20_12 igp_system_mclk;
1581 fixed20_12 igp_ht_link_clk;
1582 fixed20_12 igp_ht_link_width;
1583 fixed20_12 k8_bandwidth;
1584 fixed20_12 sideport_bandwidth;
1585 fixed20_12 ht_bandwidth;
1586 fixed20_12 core_bandwidth;
1587 fixed20_12 sclk;
f47299c5 1588 fixed20_12 mclk;
c93bb85b 1589 fixed20_12 needed_bandwidth;
0975b162 1590 struct radeon_power_state *power_state;
56278a8e
AD		 1591 /* number of valid power states */
1592 int num_power_states;
a48b9b4e
AD		 1593 int current_power_state_index;
1594 int current_clock_mode_index;
1595 int requested_power_state_index;
1596 int requested_clock_mode_index;
1597 int default_power_state_index;
1598 u32 current_sclk;
1599 u32 current_mclk;
2feea49a
AD		 1600 u16 current_vddc;
1601 u16 current_vddci;
9ace9f7b
AD		 1602 u32 default_sclk;
1603 u32 default_mclk;
2feea49a
AD		 1604 u16 default_vddc;
1605 u16 default_vddci;
29fb52ca 1606 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1607 /* selected pm method */
1608 enum radeon_pm_method pm_method;
1609 /* dynpm power management */
1610 struct delayed_work dynpm_idle_work;
1611 enum radeon_dynpm_state dynpm_state;
1612 enum radeon_dynpm_action dynpm_planned_action;
1613 unsigned long dynpm_action_timeout;
1614 bool dynpm_can_upclock;
1615 bool dynpm_can_downclock;
1616 /* profile-based power management */
1617 enum radeon_pm_profile_type profile;
1618 int profile_index;
1619 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1620 /* internal thermal controller on rv6xx+ */
1621 enum radeon_int_thermal_type int_thermal_type;
1622 struct device *int_hwmon_dev;
da321c8a
AD		 1623 /* dpm */
1624 bool dpm_enabled;
1625 struct radeon_dpm dpm;
c93bb85b
JG		 1626};
1627
a4c9e2ee
AD		 1628int radeon_pm_get_type_index(struct radeon_device *rdev,
1629 enum radeon_pm_state_type ps_type,
1630 int instance);
f2ba57b5
CK		 1631/*
1632 * UVD
1633 */
1634#define RADEON_MAX_UVD_HANDLES 10
1635#define RADEON_UVD_STACK_SIZE (1024*1024)
1636#define RADEON_UVD_HEAP_SIZE (1024*1024)
1637
1638struct radeon_uvd {
1639 struct radeon_bo *vcpu_bo;
1640 void *cpu_addr;
1641 uint64_t gpu_addr;
9cc2e0e9 1642 void *saved_bo;
f2ba57b5
CK		 1643 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1644 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1645 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1646 struct delayed_work idle_work;
f2ba57b5
CK		 1647};
1648
1649int radeon_uvd_init(struct radeon_device *rdev);
1650void radeon_uvd_fini(struct radeon_device *rdev);
1651int radeon_uvd_suspend(struct radeon_device *rdev);
1652int radeon_uvd_resume(struct radeon_device *rdev);
1653int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1654 uint32_t handle, struct radeon_fence **fence);
1655int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1656 uint32_t handle, struct radeon_fence **fence);
3852752c
CK		 1657void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1658 uint32_t allowed_domains);
f2ba57b5
CK		 1659void radeon_uvd_free_handles(struct radeon_device *rdev,
1660 struct drm_file *filp);
1661int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1662void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1663int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1664 unsigned vclk, unsigned dclk,
1665 unsigned vco_min, unsigned vco_max,
1666 unsigned fb_factor, unsigned fb_mask,
1667 unsigned pd_min, unsigned pd_max,
1668 unsigned pd_even,
1669 unsigned *optimal_fb_div,
1670 unsigned *optimal_vclk_div,
1671 unsigned *optimal_dclk_div);
1672int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1673 unsigned cg_upll_func_cntl);
771fe6b9 1674
d93f7937
CK		 1675/*
1676 * VCE
1677 */
1678#define RADEON_MAX_VCE_HANDLES 16
1679#define RADEON_VCE_STACK_SIZE (1024*1024)
1680#define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1681
1682struct radeon_vce {
1683 struct radeon_bo *vcpu_bo;
d93f7937 1684 uint64_t gpu_addr;
98ccc291
CK		 1685 unsigned fw_version;
1686 unsigned fb_version;
d93f7937
CK		 1687 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1688 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
2fc5703a 1689 unsigned img_size[RADEON_MAX_VCE_HANDLES];
03afe6f6 1690 struct delayed_work idle_work;
d93f7937
CK		 1691};
1692
1693int radeon_vce_init(struct radeon_device *rdev);
1694void radeon_vce_fini(struct radeon_device *rdev);
1695int radeon_vce_suspend(struct radeon_device *rdev);
1696int radeon_vce_resume(struct radeon_device *rdev);
1697int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1698 uint32_t handle, struct radeon_fence **fence);
1699int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1700 uint32_t handle, struct radeon_fence **fence);
1701void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
03afe6f6 1702void radeon_vce_note_usage(struct radeon_device *rdev);
2fc5703a 1703int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
d93f7937
CK		 1704int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1705bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1706 struct radeon_ring *ring,
1707 struct radeon_semaphore *semaphore,
1708 bool emit_wait);
1709void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1710void radeon_vce_fence_emit(struct radeon_device *rdev,
1711 struct radeon_fence *fence);
1712int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1713int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1714
b530602f 1715struct r600_audio_pin {
a92553ab
RM		 1716 int channels;
1717 int rate;
1718 int bits_per_sample;
1719 u8 status_bits;
1720 u8 category_code;
b530602f
AD		 1721 u32 offset;
1722 bool connected;
1723 u32 id;
1724};
1725
1726struct r600_audio {
1727 bool enabled;
1728 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1729 int num_pins;
a92553ab
RM		 1730};
1731
771fe6b9
JG		 1732/*
1733 * Benchmarking
1734 */
638dd7db 1735void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1736
1737
ecc0b326
MD		 1738/*
1739 * Testing
1740 */
1741void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1742void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1743 struct radeon_ring *cpA,
1744 struct radeon_ring *cpB);
60a7e396 1745void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326 1746
341cb9e4
CK		 1747/*
1748 * MMU Notifier
1749 */
1750int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1751void radeon_mn_unregister(struct radeon_bo *bo);
ecc0b326 1752
771fe6b9
JG		 1753/*
1754 * Debugfs
1755 */
4d8bf9ae
CK		 1756struct radeon_debugfs {
1757 struct drm_info_list *files;
1758 unsigned num_files;
1759};
1760
771fe6b9
JG		 1761int radeon_debugfs_add_files(struct radeon_device *rdev,
1762 struct drm_info_list *files,
1763 unsigned nfiles);
1764int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1765
76a0df85
CK		 1766/*
1767 * ASIC ring specific functions.
1768 */
1769struct radeon_asic_ring {
1770 /* ring read/write ptr handling */
1771 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1772 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1773 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1774
1775 /* validating and patching of IBs */
1776 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1777 int (*cs_parse)(struct radeon_cs_parser *p);
1778
1779 /* command emmit functions */
1780 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1781 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
72a9987e 1782 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1654b817 1783 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
76a0df85
CK		 1784 struct radeon_semaphore *semaphore, bool emit_wait);
1785 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1786
1787 /* testing functions */
1788 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1789 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1790 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1791
1792 /* deprecated */
1793 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1794};
771fe6b9
JG		 1795
1796/*
1797 * ASIC specific functions.
1798 */
1799struct radeon_asic {
068a117c 1800 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1801 void (*fini)(struct radeon_device *rdev);
1802 int (*resume)(struct radeon_device *rdev);
1803 int (*suspend)(struct radeon_device *rdev);
28d52043 1804 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1805 int (*asic_reset)(struct radeon_device *rdev);
124764f1
MD		 1806 /* Flush the HDP cache via MMIO */
1807 void (*mmio_hdp_flush)(struct radeon_device *rdev);
54e88e06
AD		 1808 /* check if 3D engine is idle */
1809 bool (*gui_idle)(struct radeon_device *rdev);
1810 /* wait for mc_idle */
1811 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1812 /* get the reference clock */
1813 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1814 /* get the gpu clock counter */
1815 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1816 /* gart */
c5b3b850
AD		 1817 struct {
1818 void (*tlb_flush)(struct radeon_device *rdev);
7f90fc96 1819 void (*set_page)(struct radeon_device *rdev, unsigned i,
77497f27 1820 uint64_t addr, uint32_t flags);
c5b3b850 1821 } gart;
05b07147
CK		 1822 struct {
1823 int (*init)(struct radeon_device *rdev);
1824 void (*fini)(struct radeon_device *rdev);
03f62abd
CK		 1825 void (*copy_pages)(struct radeon_device *rdev,
1826 struct radeon_ib *ib,
1827 uint64_t pe, uint64_t src,
1828 unsigned count);
1829 void (*write_pages)(struct radeon_device *rdev,
1830 struct radeon_ib *ib,
1831 uint64_t pe,
1832 uint64_t addr, unsigned count,
1833 uint32_t incr, uint32_t flags);
1834 void (*set_pages)(struct radeon_device *rdev,
1835 struct radeon_ib *ib,
1836 uint64_t pe,
1837 uint64_t addr, unsigned count,
1838 uint32_t incr, uint32_t flags);
1839 void (*pad_ib)(struct radeon_ib *ib);
05b07147 1840 } vm;
54e88e06 1841 /* ring specific callbacks */
76a0df85 1842 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1843 /* irqs */
b35ea4ab
AD		 1844 struct {
1845 int (*set)(struct radeon_device *rdev);
1846 int (*process)(struct radeon_device *rdev);
1847 } irq;
54e88e06 1848 /* displays */
c79a49ca
AD		 1849 struct {
1850 /* display watermarks */
1851 void (*bandwidth_update)(struct radeon_device *rdev);
1852 /* get frame count */
1853 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1854 /* wait for vblank */
1855 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1856 /* set backlight level */
1857 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1858 /* get backlight level */
1859 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1860 /* audio callbacks */
1861 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1862 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1863 } display;
54e88e06 1864 /* copy functions for bo handling */
27cd7769 1865 struct {
57d20a43
CK		 1866 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1867 uint64_t src_offset,
1868 uint64_t dst_offset,
1869 unsigned num_gpu_pages,
1870 struct reservation_object *resv);
27cd7769 1871 u32 blit_ring_index;
57d20a43
CK		 1872 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1873 uint64_t src_offset,
1874 uint64_t dst_offset,
1875 unsigned num_gpu_pages,
1876 struct reservation_object *resv);
27cd7769
AD		 1877 u32 dma_ring_index;
1878 /* method used for bo copy */
57d20a43
CK		 1879 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1880 uint64_t src_offset,
1881 uint64_t dst_offset,
1882 unsigned num_gpu_pages,
1883 struct reservation_object *resv);
27cd7769
AD		 1884 /* ring used for bo copies */
1885 u32 copy_ring_index;
1886 } copy;
54e88e06 1887 /* surfaces */
9e6f3d02
AD		 1888 struct {
1889 int (*set_reg)(struct radeon_device *rdev, int reg,
1890 uint32_t tiling_flags, uint32_t pitch,
1891 uint32_t offset, uint32_t obj_size);
1892 void (*clear_reg)(struct radeon_device *rdev, int reg);
1893 } surface;
54e88e06 1894 /* hotplug detect */
901ea57d
AD		 1895 struct {
1896 void (*init)(struct radeon_device *rdev);
1897 void (*fini)(struct radeon_device *rdev);
1898 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1899 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1900 } hpd;
da321c8a 1901 /* static power management */
a02fa397
AD		 1902 struct {
1903 void (*misc)(struct radeon_device *rdev);
1904 void (*prepare)(struct radeon_device *rdev);
1905 void (*finish)(struct radeon_device *rdev);
1906 void (*init_profile)(struct radeon_device *rdev);
1907 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1908 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1909 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1910 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1911 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1912 int (*get_pcie_lanes)(struct radeon_device *rdev);
1913 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1914 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1915 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
b59b7333 1916 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
6bd1c385 1917 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1918 } pm;
da321c8a
AD		 1919 /* dynamic power management */
1920 struct {
1921 int (*init)(struct radeon_device *rdev);
1922 void (*setup_asic)(struct radeon_device *rdev);
1923 int (*enable)(struct radeon_device *rdev);
914a8987 1924 int (*late_enable)(struct radeon_device *rdev);
da321c8a 1925 void (*disable)(struct radeon_device *rdev);
84dd1928 1926 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1927 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1928 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1929 void (*display_configuration_changed)(struct radeon_device *rdev);
1930 void (*fini)(struct radeon_device *rdev);
1931 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1932 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1933 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1934 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1935 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1936 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1937 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1c71bda0 1938 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
da321c8a 1939 } dpm;
6f34be50 1940 /* pageflipping */
0f9e006c 1941 struct {
157fa14d
CK		 1942 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1943 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
0f9e006c 1944 } pflip;
771fe6b9
JG		 1945};
1946
21f9a437
JG		 1947/*
1948 * Asic structures
1949 */
551ebd83 1950struct r100_asic {
225758d8
JG		 1951 const unsigned *reg_safe_bm;
1952 unsigned reg_safe_bm_size;
1953 u32 hdp_cntl;
551ebd83
DA		 1954};
1955
21f9a437 1956struct r300_asic {
225758d8
JG		 1957 const unsigned *reg_safe_bm;
1958 unsigned reg_safe_bm_size;
1959 u32 resync_scratch;
1960 u32 hdp_cntl;
21f9a437
JG		 1961};
1962
1963struct r600_asic {
225758d8
JG		 1964 unsigned max_pipes;
1965 unsigned max_tile_pipes;
1966 unsigned max_simds;
1967 unsigned max_backends;
1968 unsigned max_gprs;
1969 unsigned max_threads;
1970 unsigned max_stack_entries;
1971 unsigned max_hw_contexts;
1972 unsigned max_gs_threads;
1973 unsigned sx_max_export_size;
1974 unsigned sx_max_export_pos_size;
1975 unsigned sx_max_export_smx_size;
1976 unsigned sq_num_cf_insts;
1977 unsigned tiling_nbanks;
1978 unsigned tiling_npipes;
1979 unsigned tiling_group_size;
e7aeeba6 1980 unsigned tile_config;
e55b9422 1981 unsigned backend_map;
65fcf668 1982 unsigned active_simds;
21f9a437
JG		 1983};
1984
1985struct rv770_asic {
225758d8
JG		 1986 unsigned max_pipes;
1987 unsigned max_tile_pipes;
1988 unsigned max_simds;
1989 unsigned max_backends;
1990 unsigned max_gprs;
1991 unsigned max_threads;
1992 unsigned max_stack_entries;
1993 unsigned max_hw_contexts;
1994 unsigned max_gs_threads;
1995 unsigned sx_max_export_size;
1996 unsigned sx_max_export_pos_size;
1997 unsigned sx_max_export_smx_size;
1998 unsigned sq_num_cf_insts;
1999 unsigned sx_num_of_sets;
2000 unsigned sc_prim_fifo_size;
2001 unsigned sc_hiz_tile_fifo_size;
2002 unsigned sc_earlyz_tile_fifo_fize;
2003 unsigned tiling_nbanks;
2004 unsigned tiling_npipes;
2005 unsigned tiling_group_size;
e7aeeba6 2006 unsigned tile_config;
e55b9422 2007 unsigned backend_map;
65fcf668 2008 unsigned active_simds;
21f9a437
JG		 2009};
2010
32fcdbf4
AD		 2011struct evergreen_asic {
2012 unsigned num_ses;
2013 unsigned max_pipes;
2014 unsigned max_tile_pipes;
2015 unsigned max_simds;
2016 unsigned max_backends;
2017 unsigned max_gprs;
2018 unsigned max_threads;
2019 unsigned max_stack_entries;
2020 unsigned max_hw_contexts;
2021 unsigned max_gs_threads;
2022 unsigned sx_max_export_size;
2023 unsigned sx_max_export_pos_size;
2024 unsigned sx_max_export_smx_size;
2025 unsigned sq_num_cf_insts;
2026 unsigned sx_num_of_sets;
2027 unsigned sc_prim_fifo_size;
2028 unsigned sc_hiz_tile_fifo_size;
2029 unsigned sc_earlyz_tile_fifo_size;
2030 unsigned tiling_nbanks;
2031 unsigned tiling_npipes;
2032 unsigned tiling_group_size;
e7aeeba6 2033 unsigned tile_config;
e55b9422 2034 unsigned backend_map;
65fcf668 2035 unsigned active_simds;
32fcdbf4
AD		 2036};
2037
fecf1d07
AD		 2038struct cayman_asic {
2039 unsigned max_shader_engines;
2040 unsigned max_pipes_per_simd;
2041 unsigned max_tile_pipes;
2042 unsigned max_simds_per_se;
2043 unsigned max_backends_per_se;
2044 unsigned max_texture_channel_caches;
2045 unsigned max_gprs;
2046 unsigned max_threads;
2047 unsigned max_gs_threads;
2048 unsigned max_stack_entries;
2049 unsigned sx_num_of_sets;
2050 unsigned sx_max_export_size;
2051 unsigned sx_max_export_pos_size;
2052 unsigned sx_max_export_smx_size;
2053 unsigned max_hw_contexts;
2054 unsigned sq_num_cf_insts;
2055 unsigned sc_prim_fifo_size;
2056 unsigned sc_hiz_tile_fifo_size;
2057 unsigned sc_earlyz_tile_fifo_size;
2058
2059 unsigned num_shader_engines;
2060 unsigned num_shader_pipes_per_simd;
2061 unsigned num_tile_pipes;
2062 unsigned num_simds_per_se;
2063 unsigned num_backends_per_se;
2064 unsigned backend_disable_mask_per_asic;
2065 unsigned backend_map;
2066 unsigned num_texture_channel_caches;
2067 unsigned mem_max_burst_length_bytes;
2068 unsigned mem_row_size_in_kb;
2069 unsigned shader_engine_tile_size;
2070 unsigned num_gpus;
2071 unsigned multi_gpu_tile_size;
2072
2073 unsigned tile_config;
65fcf668 2074 unsigned active_simds;
fecf1d07
AD		 2075};
2076
0a96d72b
AD		 2077struct si_asic {
2078 unsigned max_shader_engines;
0a96d72b 2079 unsigned max_tile_pipes;
1a8ca750
AD		 2080 unsigned max_cu_per_sh;
2081 unsigned max_sh_per_se;
0a96d72b
AD		 2082 unsigned max_backends_per_se;
2083 unsigned max_texture_channel_caches;
2084 unsigned max_gprs;
2085 unsigned max_gs_threads;
2086 unsigned max_hw_contexts;
2087 unsigned sc_prim_fifo_size_frontend;
2088 unsigned sc_prim_fifo_size_backend;
2089 unsigned sc_hiz_tile_fifo_size;
2090 unsigned sc_earlyz_tile_fifo_size;
2091
0a96d72b 2092 unsigned num_tile_pipes;
439a1cff 2093 unsigned backend_enable_mask;
0a96d72b
AD		 2094 unsigned backend_disable_mask_per_asic;
2095 unsigned backend_map;
2096 unsigned num_texture_channel_caches;
2097 unsigned mem_max_burst_length_bytes;
2098 unsigned mem_row_size_in_kb;
2099 unsigned shader_engine_tile_size;
2100 unsigned num_gpus;
2101 unsigned multi_gpu_tile_size;
2102
2103 unsigned tile_config;
64d7b8be 2104 uint32_t tile_mode_array[32];
65fcf668 2105 uint32_t active_cus;
0a96d72b
AD		 2106};
2107
8cc1a532
AD		 2108struct cik_asic {
2109 unsigned max_shader_engines;
2110 unsigned max_tile_pipes;
2111 unsigned max_cu_per_sh;
2112 unsigned max_sh_per_se;
2113 unsigned max_backends_per_se;
2114 unsigned max_texture_channel_caches;
2115 unsigned max_gprs;
2116 unsigned max_gs_threads;
2117 unsigned max_hw_contexts;
2118 unsigned sc_prim_fifo_size_frontend;
2119 unsigned sc_prim_fifo_size_backend;
2120 unsigned sc_hiz_tile_fifo_size;
2121 unsigned sc_earlyz_tile_fifo_size;
2122
2123 unsigned num_tile_pipes;
439a1cff 2124 unsigned backend_enable_mask;
8cc1a532
AD		 2125 unsigned backend_disable_mask_per_asic;
2126 unsigned backend_map;
2127 unsigned num_texture_channel_caches;
2128 unsigned mem_max_burst_length_bytes;
2129 unsigned mem_row_size_in_kb;
2130 unsigned shader_engine_tile_size;
2131 unsigned num_gpus;
2132 unsigned multi_gpu_tile_size;
2133
2134 unsigned tile_config;
39aee490 2135 uint32_t tile_mode_array[32];
32f79a8a 2136 uint32_t macrotile_mode_array[16];
65fcf668 2137 uint32_t active_cus;
8cc1a532
AD		 2138};
2139
068a117c
JG		 2140union radeon_asic_config {
2141 struct r300_asic r300;
551ebd83 2142 struct r100_asic r100;
3ce0a23d
JG		 2143 struct r600_asic r600;
2144 struct rv770_asic rv770;
32fcdbf4 2145 struct evergreen_asic evergreen;
fecf1d07 2146 struct cayman_asic cayman;
0a96d72b 2147 struct si_asic si;
8cc1a532 2148 struct cik_asic cik;
068a117c
JG		 2149};
2150
0a10c851
DV		 2151/*
2152 * asic initizalization from radeon_asic.c
2153 */
2154void radeon_agp_disable(struct radeon_device *rdev);
2155int radeon_asic_init(struct radeon_device *rdev);
2156
771fe6b9
JG		 2157
2158/*
2159 * IOCTL.
2160 */
2161int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2162 struct drm_file *filp);
2163int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2164 struct drm_file *filp);
f72a113a
CK		 2165int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2166 struct drm_file *filp);
771fe6b9
JG		 2167int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2168 struct drm_file *file_priv);
2169int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2170 struct drm_file *file_priv);
2171int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2172 struct drm_file *file_priv);
2173int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2174 struct drm_file *file_priv);
2175int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2176 struct drm_file *filp);
2177int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2178 struct drm_file *filp);
2179int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2180 struct drm_file *filp);
2181int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2182 struct drm_file *filp);
721604a1
JG		 2183int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2184 struct drm_file *filp);
bda72d58
MO		 2185int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2186 struct drm_file *filp);
771fe6b9 2187int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 2188int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2189 struct drm_file *filp);
2190int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2191 struct drm_file *filp);
771fe6b9 2192
16cdf04d
AD		 2193/* VRAM scratch page for HDP bug, default vram page */
2194struct r600_vram_scratch {
87cbf8f2
AD		 2195 struct radeon_bo *robj;
2196 volatile uint32_t *ptr;
16cdf04d 2197 u64 gpu_addr;
87cbf8f2 2198};
771fe6b9 2199
fd64ca8a
LT		 2200/*
2201 * ACPI
2202 */
2203struct radeon_atif_notification_cfg {
2204 bool enabled;
2205 int command_code;
2206};
2207
2208struct radeon_atif_notifications {
2209 bool display_switch;
2210 bool expansion_mode_change;
2211 bool thermal_state;
2212 bool forced_power_state;
2213 bool system_power_state;
2214 bool display_conf_change;
2215 bool px_gfx_switch;
2216 bool brightness_change;
2217 bool dgpu_display_event;
2218};
2219
2220struct radeon_atif_functions {
2221 bool system_params;
2222 bool sbios_requests;
2223 bool select_active_disp;
2224 bool lid_state;
2225 bool get_tv_standard;
2226 bool set_tv_standard;
2227 bool get_panel_expansion_mode;
2228 bool set_panel_expansion_mode;
2229 bool temperature_change;
2230 bool graphics_device_types;
2231};
2232
2233struct radeon_atif {
2234 struct radeon_atif_notifications notifications;
2235 struct radeon_atif_functions functions;
2236 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2237 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2238};
7a1619b9 2239
e3a15920
AD		 2240struct radeon_atcs_functions {
2241 bool get_ext_state;
2242 bool pcie_perf_req;
2243 bool pcie_dev_rdy;
2244 bool pcie_bus_width;
2245};
2246
2247struct radeon_atcs {
2248 struct radeon_atcs_functions functions;
2249};
2250
771fe6b9
JG		 2251/*
2252 * Core structure, functions and helpers.
2253 */
2254typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2255typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2256
2257struct radeon_device {
9f022ddf 2258 struct device *dev;
771fe6b9
JG		 2259 struct drm_device *ddev;
2260 struct pci_dev *pdev;
dee53e7f 2261 struct rw_semaphore exclusive_lock;
771fe6b9 2262 /* ASIC */
068a117c 2263 union radeon_asic_config config;
771fe6b9
JG		 2264 enum radeon_family family;
2265 unsigned long flags;
2266 int usec_timeout;
2267 enum radeon_pll_errata pll_errata;
2268 int num_gb_pipes;
f779b3e5 2269 int num_z_pipes;
771fe6b9
JG		 2270 int disp_priority;
2271 /* BIOS */
2272 uint8_t *bios;
2273 bool is_atom_bios;
2274 uint16_t bios_header_start;
4c788679 2275 struct radeon_bo *stollen_vga_memory;
771fe6b9 2276 /* Register mmio */
4c9bc75c
DA		 2277 resource_size_t rmmio_base;
2278 resource_size_t rmmio_size;
2c385151
DV		 2279 /* protects concurrent MM_INDEX/DATA based register access */
2280 spinlock_t mmio_idx_lock;
fe78118c
AD		 2281 /* protects concurrent SMC based register access */
2282 spinlock_t smc_idx_lock;
0a5b7b0b
AD		 2283 /* protects concurrent PLL register access */
2284 spinlock_t pll_idx_lock;
2285 /* protects concurrent MC register access */
2286 spinlock_t mc_idx_lock;
2287 /* protects concurrent PCIE register access */
2288 spinlock_t pcie_idx_lock;
2289 /* protects concurrent PCIE_PORT register access */
2290 spinlock_t pciep_idx_lock;
2291 /* protects concurrent PIF register access */
2292 spinlock_t pif_idx_lock;
2293 /* protects concurrent CG register access */
2294 spinlock_t cg_idx_lock;
2295 /* protects concurrent UVD register access */
2296 spinlock_t uvd_idx_lock;
2297 /* protects concurrent RCU register access */
2298 spinlock_t rcu_idx_lock;
2299 /* protects concurrent DIDT register access */
2300 spinlock_t didt_idx_lock;
2301 /* protects concurrent ENDPOINT (audio) register access */
2302 spinlock_t end_idx_lock;
a0533fbf 2303 void __iomem *rmmio;
771fe6b9
JG		 2304 radeon_rreg_t mc_rreg;
2305 radeon_wreg_t mc_wreg;
2306 radeon_rreg_t pll_rreg;
2307 radeon_wreg_t pll_wreg;
de1b2898 2308 uint32_t pcie_reg_mask;
771fe6b9
JG		 2309 radeon_rreg_t pciep_rreg;
2310 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2311 /* io port */
2312 void __iomem *rio_mem;
2313 resource_size_t rio_mem_size;
771fe6b9
JG		 2314 struct radeon_clock clock;
2315 struct radeon_mc mc;
2316 struct radeon_gart gart;
2317 struct radeon_mode_info mode_info;
2318 struct radeon_scratch scratch;
75efdee1 2319 struct radeon_doorbell doorbell;
771fe6b9 2320 struct radeon_mman mman;
7465280c 2321 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2322 wait_queue_head_t fence_queue;
954605ca 2323 unsigned fence_context;
d6999bc7 2324 struct mutex ring_lock;
e32eb50d 2325 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2326 bool ib_pool_ready;
2327 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2328 struct radeon_irq irq;
2329 struct radeon_asic *asic;
2330 struct radeon_gem gem;
c93bb85b 2331 struct radeon_pm pm;
f2ba57b5 2332 struct radeon_uvd uvd;
d93f7937 2333 struct radeon_vce vce;
f657c2a7 2334 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2335 struct radeon_wb wb;
3ce0a23d 2336 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2337 bool shutdown;
2338 bool suspend;
ad49f501 2339 bool need_dma32;
733289c2 2340 bool accel_working;
a0a53aa8 2341 bool fastfb_working; /* IGP feature*/
9bb39ff4 2342 bool needs_reset, in_reset;
e024e110 2343 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2344 const struct firmware *me_fw; /* all family ME firmware */
2345 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2346 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2347 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2348 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2349 const struct firmware *mec_fw; /* CIK MEC firmware */
f2c6b0f4 2350 const struct firmware *mec2_fw; /* KV MEC2 firmware */
21a93e13 2351 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2352 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2353 const struct firmware *uvd_fw; /* UVD firmware */
d93f7937 2354 const struct firmware *vce_fw; /* VCE firmware */
629bd33c 2355 bool new_fw;
16cdf04d 2356 struct r600_vram_scratch vram_scratch;
3e5cb98d 2357 int msi_enabled; /* msi enabled */
d8f60cfc 2358 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2359 struct radeon_rlc rlc;
963e81f9 2360 struct radeon_mec mec;
d4877cf2 2361 struct work_struct hotplug_work;
f122c610 2362 struct work_struct audio_work;
18917b60 2363 int num_crtc; /* number of crtcs */
40bacf16 2364 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
948bee3f 2365 bool has_uvd;
b530602f 2366 struct r600_audio audio; /* audio stuff */
ce8f5370 2367 struct notifier_block acpi_nb;
9eba4a93 2368 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2369 struct drm_file *hyperz_filp;
9eba4a93 2370 struct drm_file *cmask_filp;
f376b94f
AD		 2371 /* i2c buses */
2372 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2373 /* debugfs */
2374 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2375 unsigned debugfs_count;
721604a1
JG		 2376 /* virtual memory */
2377 struct radeon_vm_manager vm_manager;
6759a0a7 2378 struct mutex gpu_clock_mutex;
67e8e3f9
MO		 2379 /* memory stats */
2380 atomic64_t vram_usage;
2381 atomic64_t gtt_usage;
2382 atomic64_t num_bytes_moved;
fd64ca8a
LT		 2383 /* ACPI interface */
2384 struct radeon_atif atif;
e3a15920 2385 struct radeon_atcs atcs;
f61d5b46
AD		 2386 /* srbm instance registers */
2387 struct mutex srbm_mutex;
64d8a728
AD		 2388 /* clock, powergating flags */
2389 u32 cg_flags;
2390 u32 pg_flags;
10ebc0bc
DA		 2391
2392 struct dev_pm_domain vga_pm_domain;
2393 bool have_disp_power_ref;
4807c5a8 2394 u32 px_quirk_flags;
71ecc97e
AD		 2395
2396 /* tracking pinned memory */
2397 u64 vram_pin_size;
2398 u64 gart_pin_size;
341cb9e4
CK		 2399
2400 struct mutex mn_lock;
2401 DECLARE_HASHTABLE(mn_hash, 7);
771fe6b9
JG		 2402};
2403
90c4cde9 2404bool radeon_is_px(struct drm_device *dev);
771fe6b9
JG		 2405int radeon_device_init(struct radeon_device *rdev,
2406 struct drm_device *ddev,
2407 struct pci_dev *pdev,
2408 uint32_t flags);
2409void radeon_device_fini(struct radeon_device *rdev);
2410int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2411
59bc1d89
LK		 2412#define RADEON_MIN_MMIO_SIZE 0x10000
2413
2414static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2415 bool always_indirect)
2416{
2417 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2418 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2419 return readl(((void __iomem *)rdev->rmmio) + reg);
2420 else {
2421 unsigned long flags;
2422 uint32_t ret;
2423
2424 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2425 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2426 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2427 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2428
2429 return ret;
2430 }
2431}
2432
2433static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2434 bool always_indirect)
2435{
2436 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2437 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2438 else {
2439 unsigned long flags;
2440
2441 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2442 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2443 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2444 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2445 }
2446}
2447
6fcbef7a
AK		 2448u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2449void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2450
d5754ab8
AL		 2451u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2452void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
75efdee1 2453
4c788679
JG		 2454/*
2455 * Cast helper
2456 */
954605ca
ML		 2457extern const struct fence_ops radeon_fence_ops;
2458
2459static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2460{
2461 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2462
2463 if (__f->base.ops == &radeon_fence_ops)
2464 return __f;
2465
2466 return NULL;
2467}
771fe6b9
JG		 2468
2469/*
2470 * Registers read & write functions.
2471 */
a0533fbf
BH		 2472#define RREG8(reg) readb((rdev->rmmio) + (reg))
2473#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2474#define RREG16(reg) readw((rdev->rmmio) + (reg))
2475#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2476#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2477#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2478#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2479#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2480#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2481#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2482#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2483#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2484#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2485#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2486#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2487#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2488#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2489#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2490#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2491#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2492#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2493#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2494#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2495#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2496#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2497#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2498#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2499#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2500#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2501#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2502#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2503#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2504#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2505#define WREG32_P(reg, val, mask) \
2506 do { \
2507 uint32_t tmp_ = RREG32(reg); \
2508 tmp_ &= (mask); \
2509 tmp_ |= ((val) & ~(mask)); \
2510 WREG32(reg, tmp_); \
2511 } while (0)
d5169fc4 2512#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2513#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2514#define WREG32_PLL_P(reg, val, mask) \
2515 do { \
2516 uint32_t tmp_ = RREG32_PLL(reg); \
2517 tmp_ &= (mask); \
2518 tmp_ |= ((val) & ~(mask)); \
2519 WREG32_PLL(reg, tmp_); \
2520 } while (0)
2ef9bdfe 2521#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2522#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2523#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2524
d5754ab8
AL		 2525#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2526#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
75efdee1 2527
de1b2898
DA		 2528/*
2529 * Indirect registers accessor
2530 */
2531static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2532{
0a5b7b0b 2533 unsigned long flags;
de1b2898
DA		 2534 uint32_t r;
2535
0a5b7b0b 2536 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2537 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2538 r = RREG32(RADEON_PCIE_DATA);
0a5b7b0b 2539 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2540 return r;
2541}
2542
2543static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2544{
0a5b7b0b
AD		 2545 unsigned long flags;
2546
2547 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2548 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2549 WREG32(RADEON_PCIE_DATA, (v));
0a5b7b0b 2550 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2551}
2552
1d5d0c34
AD		 2553static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2554{
fe78118c 2555 unsigned long flags;
1d5d0c34
AD		 2556 u32 r;
2557
fe78118c 2558 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2559 WREG32(TN_SMC_IND_INDEX_0, (reg));
2560 r = RREG32(TN_SMC_IND_DATA_0);
fe78118c 2561 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2562 return r;
2563}
2564
2565static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2566{
fe78118c
AD		 2567 unsigned long flags;
2568
2569 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2570 WREG32(TN_SMC_IND_INDEX_0, (reg));
2571 WREG32(TN_SMC_IND_DATA_0, (v));
fe78118c 2572 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2573}
2574
ff82bbc4
AD		 2575static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2576{
0a5b7b0b 2577 unsigned long flags;
ff82bbc4
AD		 2578 u32 r;
2579
0a5b7b0b 2580 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2581 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2582 r = RREG32(R600_RCU_DATA);
0a5b7b0b 2583 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2584 return r;
2585}
2586
2587static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2588{
0a5b7b0b
AD		 2589 unsigned long flags;
2590
2591 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2592 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2593 WREG32(R600_RCU_DATA, (v));
0a5b7b0b 2594 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2595}
2596
46f9564a
AD		 2597static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2598{
0a5b7b0b 2599 unsigned long flags;
46f9564a
AD		 2600 u32 r;
2601
0a5b7b0b 2602 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2603 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2604 r = RREG32(EVERGREEN_CG_IND_DATA);
0a5b7b0b 2605 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2606 return r;
2607}
2608
2609static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2610{
0a5b7b0b
AD		 2611 unsigned long flags;
2612
2613 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2614 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2615 WREG32(EVERGREEN_CG_IND_DATA, (v));
0a5b7b0b 2616 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2617}
2618
792edd69
AD		 2619static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2620{
0a5b7b0b 2621 unsigned long flags;
792edd69
AD		 2622 u32 r;
2623
0a5b7b0b 2624 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2625 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2626 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
0a5b7b0b 2627 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2628 return r;
2629}
2630
2631static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2632{
0a5b7b0b
AD		 2633 unsigned long flags;
2634
2635 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2636 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2637 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
0a5b7b0b 2638 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2639}
2640
2641static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2642{
0a5b7b0b 2643 unsigned long flags;
792edd69
AD		 2644 u32 r;
2645
0a5b7b0b 2646 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2647 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2648 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
0a5b7b0b 2649 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2650 return r;
2651}
2652
2653static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2654{
0a5b7b0b
AD		 2655 unsigned long flags;
2656
2657 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2658 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2659 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
0a5b7b0b 2660 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2661}
2662
93656cdd
AD		 2663static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2664{
0a5b7b0b 2665 unsigned long flags;
93656cdd
AD		 2666 u32 r;
2667
0a5b7b0b 2668 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2669 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2670 r = RREG32(R600_UVD_CTX_DATA);
0a5b7b0b 2671 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2672 return r;
2673}
2674
2675static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2676{
0a5b7b0b
AD		 2677 unsigned long flags;
2678
2679 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2680 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2681 WREG32(R600_UVD_CTX_DATA, (v));
0a5b7b0b 2682 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2683}
2684
1d58234d
AD		 2685
2686static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2687{
0a5b7b0b 2688 unsigned long flags;
1d58234d
AD		 2689 u32 r;
2690
0a5b7b0b 2691 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2692 WREG32(CIK_DIDT_IND_INDEX, (reg));
2693 r = RREG32(CIK_DIDT_IND_DATA);
0a5b7b0b 2694 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2695 return r;
2696}
2697
2698static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2699{
0a5b7b0b
AD		 2700 unsigned long flags;
2701
2702 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2703 WREG32(CIK_DIDT_IND_INDEX, (reg));
2704 WREG32(CIK_DIDT_IND_DATA, (v));
0a5b7b0b 2705 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2706}
2707
771fe6b9
JG		 2708void r100_pll_errata_after_index(struct radeon_device *rdev);
2709
2710
2711/*
2712 * ASICs helpers.
2713 */
b995e433
DA		 2714#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2715 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2716#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2717 (rdev->family == CHIP_RV200) || \
2718 (rdev->family == CHIP_RS100) || \
2719 (rdev->family == CHIP_RS200) || \
2720 (rdev->family == CHIP_RV250) || \
2721 (rdev->family == CHIP_RV280) || \
2722 (rdev->family == CHIP_RS300))
2723#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2724 (rdev->family == CHIP_RV350) || \
2725 (rdev->family == CHIP_R350) || \
2726 (rdev->family == CHIP_RV380) || \
2727 (rdev->family == CHIP_R420) || \
2728 (rdev->family == CHIP_R423) || \
2729 (rdev->family == CHIP_RV410) || \
2730 (rdev->family == CHIP_RS400) || \
2731 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2732#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2733 (rdev->ddev->pdev->device == 0x9443) || \
2734 (rdev->ddev->pdev->device == 0x944B) || \
2735 (rdev->ddev->pdev->device == 0x9506) || \
2736 (rdev->ddev->pdev->device == 0x9509) || \
2737 (rdev->ddev->pdev->device == 0x950F) || \
2738 (rdev->ddev->pdev->device == 0x689C) || \
2739 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2740#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2741#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2742 (rdev->family == CHIP_RS690) || \
2743 (rdev->family == CHIP_RS740) || \
2744 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2745#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2746#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2747#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2748#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2749 (rdev->flags & RADEON_IS_IGP))
1fe18305 2750#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2751#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2752#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2753 (rdev->flags & RADEON_IS_IGP))
624d3524 2754#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2755#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2756#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
be0949f5
AD		 2757#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2758#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
89d2618d
AD		 2759#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2760 (rdev->family == CHIP_MULLINS))
771fe6b9 2761
dc50ba7f
AD		 2762#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2763 (rdev->ddev->pdev->device == 0x6850) || \
2764 (rdev->ddev->pdev->device == 0x6858) || \
2765 (rdev->ddev->pdev->device == 0x6859) || \
2766 (rdev->ddev->pdev->device == 0x6840) || \
2767 (rdev->ddev->pdev->device == 0x6841) || \
2768 (rdev->ddev->pdev->device == 0x6842) || \
2769 (rdev->ddev->pdev->device == 0x6843))
2770
771fe6b9
JG		 2771/*
2772 * BIOS helpers.
2773 */
2774#define RBIOS8(i) (rdev->bios[i])
2775#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2776#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2777
2778int radeon_combios_init(struct radeon_device *rdev);
2779void radeon_combios_fini(struct radeon_device *rdev);
2780int radeon_atombios_init(struct radeon_device *rdev);
2781void radeon_atombios_fini(struct radeon_device *rdev);
2782
2783
2784/*
2785 * RING helpers.
2786 */
edf0ac7c
DH		 2787
2788/**
2789 * radeon_ring_write - write a value to the ring
2790 *
2791 * @ring: radeon_ring structure holding ring information
2792 * @v: dword (dw) value to write
2793 *
2794 * Write a value to the requested ring buffer (all asics).
2795 */
e32eb50d 2796static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2797{
edf0ac7c
DH		 2798 if (ring->count_dw <= 0)
2799 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2800
e32eb50d
CK		 2801 ring->ring[ring->wptr++] = v;
2802 ring->wptr &= ring->ptr_mask;
2803 ring->count_dw--;
2804 ring->ring_free_dw--;
771fe6b9 2805}
771fe6b9
JG		 2806
2807/*
2808 * ASICs macro.
2809 */
068a117c 2810#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2811#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2812#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2813#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2814#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2815#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2816#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850 2817#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
77497f27 2818#define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f))
05b07147
CK		 2819#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2820#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
03f62abd
CK		 2821#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2822#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2823#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2824#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
76a0df85
CK		 2825#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2826#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2827#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2828#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2829#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2830#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2831#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2832#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2833#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2834#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2835#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2836#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2837#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2838#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2839#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2840#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2841#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2842#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2843#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
57d20a43
CK		 2844#define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2845#define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2846#define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
27cd7769
AD		 2847#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2848#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2849#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2850#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2851#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2852#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2853#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2854#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2855#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2856#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2857#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
b59b7333 2858#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
6bd1c385 2859#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2860#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2861#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2862#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2863#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2864#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2865#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2866#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2867#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2868#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2869#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2870#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2871#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2872#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8 2873#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
157fa14d 2874#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
69b62ad8
AD		 2875#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2876#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2877#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2878#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2879#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2880#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2881#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
914a8987 2882#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
da321c8a 2883#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2884#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2885#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2886#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2887#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2888#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2889#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2890#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2891#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2892#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2893#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2894#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2895#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
1c71bda0 2896#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
771fe6b9 2897
6cf8a3f5 2898/* Common functions */
700a0cc0 2899/* AGP */
90aca4d2 2900extern int radeon_gpu_reset(struct radeon_device *rdev);
1a0041b8 2901extern void radeon_pci_config_reset(struct radeon_device *rdev);
410a3418 2902extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2903extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2904extern int radeon_modeset_init(struct radeon_device *rdev);
2905extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2906extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2907extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2908extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2909extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2910extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2911extern void radeon_wb_fini(struct radeon_device *rdev);
2912extern int radeon_wb_init(struct radeon_device *rdev);
2913extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2914extern void radeon_surface_init(struct radeon_device *rdev);
2915extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2916extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2917extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2918extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2919extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
f72a113a
CK		 2920extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2921 uint32_t flags);
2922extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2923extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
d594e46a
JG		 2924extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2925extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
10ebc0bc
DA		 2926extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2927extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
53595338 2928extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2929extern void radeon_program_register_sequence(struct radeon_device *rdev,
2930 const u32 *registers,
2931 const u32 array_size);
6cf8a3f5 2932
721604a1
JG		 2933/*
2934 * vm
2935 */
2936int radeon_vm_manager_init(struct radeon_device *rdev);
2937void radeon_vm_manager_fini(struct radeon_device *rdev);
6d2f2944 2938int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2939void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
df0af440
CK		 2940struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2941 struct radeon_vm *vm,
2942 struct list_head *head);
ee60e29f
CK		 2943struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2944 struct radeon_vm *vm, int ring);
fa688343
CK		 2945void radeon_vm_flush(struct radeon_device *rdev,
2946 struct radeon_vm *vm,
2947 int ring);
ee60e29f
CK		 2948void radeon_vm_fence(struct radeon_device *rdev,
2949 struct radeon_vm *vm,
2950 struct radeon_fence *fence);
dce34bfd 2951uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
6d2f2944
CK		 2952int radeon_vm_update_page_directory(struct radeon_device *rdev,
2953 struct radeon_vm *vm);
036bf46a
CK		 2954int radeon_vm_clear_freed(struct radeon_device *rdev,
2955 struct radeon_vm *vm);
e31ad969
CK		 2956int radeon_vm_clear_invalids(struct radeon_device *rdev,
2957 struct radeon_vm *vm);
9c57a6bd 2958int radeon_vm_bo_update(struct radeon_device *rdev,
036bf46a 2959 struct radeon_bo_va *bo_va,
9c57a6bd 2960 struct ttm_mem_reg *mem);
721604a1
JG		 2961void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2962 struct radeon_bo *bo);
421ca7ab
CK		 2963struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2964 struct radeon_bo *bo);
e971bd5e
CK		 2965struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2966 struct radeon_vm *vm,
2967 struct radeon_bo *bo);
2968int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2969 struct radeon_bo_va *bo_va,
2970 uint64_t offset,
2971 uint32_t flags);
036bf46a
CK		 2972void radeon_vm_bo_rmv(struct radeon_device *rdev,
2973 struct radeon_bo_va *bo_va);
721604a1 2974
f122c610
AD		 2975/* audio */
2976void r600_audio_update_hdmi(struct work_struct *work);
b530602f
AD		 2977struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2978struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
832eafaf
AD		 2979void r600_audio_enable(struct radeon_device *rdev,
2980 struct r600_audio_pin *pin,
d3d8c141 2981 u8 enable_mask);
832eafaf
AD		 2982void dce6_audio_enable(struct radeon_device *rdev,
2983 struct r600_audio_pin *pin,
d3d8c141 2984 u8 enable_mask);
721604a1 2985
16cdf04d
AD		 2986/*
2987 * R600 vram scratch functions
2988 */
2989int r600_vram_scratch_init(struct radeon_device *rdev);
2990void r600_vram_scratch_fini(struct radeon_device *rdev);
2991
285484e2
JG		 2992/*
2993 * r600 cs checking helper
2994 */
2995unsigned r600_mip_minify(unsigned size, unsigned level);
2996bool r600_fmt_is_valid_color(u32 format);
2997bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2998int r600_fmt_get_blocksize(u32 format);
2999int r600_fmt_get_nblocksx(u32 format, u32 w);
3000int r600_fmt_get_nblocksy(u32 format, u32 h);
3001
3574dda4
DV		 3002/*
3003 * r600 functions used by radeon_encoder.c
3004 */
1b688d08
RM		 3005struct radeon_hdmi_acr {
3006 u32 clock;
3007
3008 int n_32khz;
3009 int cts_32khz;
3010
3011 int n_44_1khz;
3012 int cts_44_1khz;
3013
3014 int n_48khz;
3015 int cts_48khz;
3016
3017};
3018
e55d3e6c
RM		 3019extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
3020
416a2bd2
AD		 3021extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
3022 u32 tiling_pipe_num,
3023 u32 max_rb_num,
3024 u32 total_max_rb_num,
3025 u32 enabled_rb_mask);
fe251e2f 3026
e55d3e6c
RM		 3027/*
3028 * evergreen functions used by radeon_encoder.c
3029 */
3030
0af62b01 3031extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 3032extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 3033
c4917074
AD		 3034/* radeon_acpi.c */
3035#if defined(CONFIG_ACPI)
3036extern int radeon_acpi_init(struct radeon_device *rdev);
3037extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 3038extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
3039extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 3040 u8 perf_req, bool advertise);
dc50ba7f 3041extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 3042#else
3043static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
3044static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
3045#endif
d7a2952f 3046
c38f34b5
IH		 3047int radeon_cs_packet_parse(struct radeon_cs_parser *p,
3048 struct radeon_cs_packet *pkt,
3049 unsigned idx);
9ffb7a6d 3050bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 3051void radeon_cs_dump_packet(struct radeon_cs_parser *p,
3052 struct radeon_cs_packet *pkt);
e9716993
IH		 3053int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
3054 struct radeon_cs_reloc **cs_reloc,
3055 int nomm);
40592a17
IH		 3056int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
3057 uint32_t *vline_start_end,
3058 uint32_t *vline_status);
c38f34b5 3059
4c788679
JG		 3060#include "radeon_object.h"
3061
771fe6b9 3062#endif
Linux kernel - Deliverables
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