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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __RADEON_H__ | |
29 | #define __RADEON_H__ | |
30 | ||
771fe6b9 JG |
31 | /* TODO: Here are things that needs to be done : |
32 | * - surface allocator & initializer : (bit like scratch reg) should | |
33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings | |
34 | * related to surface | |
35 | * - WB : write back stuff (do it bit like scratch reg things) | |
36 | * - Vblank : look at Jesse's rework and what we should do | |
37 | * - r600/r700: gart & cp | |
38 | * - cs : clean cs ioctl use bitmap & things like that. | |
39 | * - power management stuff | |
40 | * - Barrier in gart code | |
41 | * - Unmappabled vram ? | |
42 | * - TESTING, TESTING, TESTING | |
43 | */ | |
44 | ||
d39c3b89 JG |
45 | /* Initialization path: |
46 | * We expect that acceleration initialization might fail for various | |
47 | * reasons even thought we work hard to make it works on most | |
48 | * configurations. In order to still have a working userspace in such | |
49 | * situation the init path must succeed up to the memory controller | |
50 | * initialization point. Failure before this point are considered as | |
51 | * fatal error. Here is the init callchain : | |
52 | * radeon_device_init perform common structure, mutex initialization | |
53 | * asic_init setup the GPU memory layout and perform all | |
54 | * one time initialization (failure in this | |
55 | * function are considered fatal) | |
56 | * asic_startup setup the GPU acceleration, in order to | |
57 | * follow guideline the first thing this | |
58 | * function should do is setting the GPU | |
59 | * memory controller (only MC setup failure | |
60 | * are considered as fatal) | |
61 | */ | |
62 | ||
771fe6b9 JG |
63 | #include <asm/atomic.h> |
64 | #include <linux/wait.h> | |
65 | #include <linux/list.h> | |
66 | #include <linux/kref.h> | |
67 | ||
4c788679 JG |
68 | #include <ttm/ttm_bo_api.h> |
69 | #include <ttm/ttm_bo_driver.h> | |
70 | #include <ttm/ttm_placement.h> | |
71 | #include <ttm/ttm_module.h> | |
72 | ||
c2142715 | 73 | #include "radeon_family.h" |
771fe6b9 JG |
74 | #include "radeon_mode.h" |
75 | #include "radeon_reg.h" | |
771fe6b9 JG |
76 | |
77 | /* | |
78 | * Modules parameters. | |
79 | */ | |
80 | extern int radeon_no_wb; | |
81 | extern int radeon_modeset; | |
82 | extern int radeon_dynclks; | |
83 | extern int radeon_r4xx_atom; | |
84 | extern int radeon_agpmode; | |
85 | extern int radeon_vram_limit; | |
86 | extern int radeon_gart_size; | |
87 | extern int radeon_benchmarking; | |
ecc0b326 | 88 | extern int radeon_testing; |
771fe6b9 | 89 | extern int radeon_connector_table; |
4ce001ab | 90 | extern int radeon_tv; |
771fe6b9 JG |
91 | |
92 | /* | |
93 | * Copy from radeon_drv.h so we don't have to include both and have conflicting | |
94 | * symbol; | |
95 | */ | |
96 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ | |
97 | #define RADEON_IB_POOL_SIZE 16 | |
98 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 | |
99 | #define RADEONFB_CONN_LIMIT 4 | |
f657c2a7 | 100 | #define RADEON_BIOS_NUM_SCRATCH 8 |
771fe6b9 | 101 | |
771fe6b9 JG |
102 | /* |
103 | * Errata workarounds. | |
104 | */ | |
105 | enum radeon_pll_errata { | |
106 | CHIP_ERRATA_R300_CG = 0x00000001, | |
107 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, | |
108 | CHIP_ERRATA_PLL_DELAY = 0x00000004 | |
109 | }; | |
110 | ||
111 | ||
112 | struct radeon_device; | |
113 | ||
114 | ||
115 | /* | |
116 | * BIOS. | |
117 | */ | |
118 | bool radeon_get_bios(struct radeon_device *rdev); | |
119 | ||
3ce0a23d | 120 | |
771fe6b9 | 121 | /* |
3ce0a23d | 122 | * Dummy page |
771fe6b9 | 123 | */ |
3ce0a23d JG |
124 | struct radeon_dummy_page { |
125 | struct page *page; | |
126 | dma_addr_t addr; | |
127 | }; | |
128 | int radeon_dummy_page_init(struct radeon_device *rdev); | |
129 | void radeon_dummy_page_fini(struct radeon_device *rdev); | |
130 | ||
771fe6b9 | 131 | |
3ce0a23d JG |
132 | /* |
133 | * Clocks | |
134 | */ | |
771fe6b9 JG |
135 | struct radeon_clock { |
136 | struct radeon_pll p1pll; | |
137 | struct radeon_pll p2pll; | |
138 | struct radeon_pll spll; | |
139 | struct radeon_pll mpll; | |
140 | /* 10 Khz units */ | |
141 | uint32_t default_mclk; | |
142 | uint32_t default_sclk; | |
143 | }; | |
144 | ||
7433874e RM |
145 | /* |
146 | * Power management | |
147 | */ | |
148 | int radeon_pm_init(struct radeon_device *rdev); | |
3ce0a23d | 149 | |
771fe6b9 JG |
150 | /* |
151 | * Fences. | |
152 | */ | |
153 | struct radeon_fence_driver { | |
154 | uint32_t scratch_reg; | |
155 | atomic_t seq; | |
156 | uint32_t last_seq; | |
157 | unsigned long count_timeout; | |
158 | wait_queue_head_t queue; | |
159 | rwlock_t lock; | |
160 | struct list_head created; | |
161 | struct list_head emited; | |
162 | struct list_head signaled; | |
163 | }; | |
164 | ||
165 | struct radeon_fence { | |
166 | struct radeon_device *rdev; | |
167 | struct kref kref; | |
168 | struct list_head list; | |
169 | /* protected by radeon_fence.lock */ | |
170 | uint32_t seq; | |
171 | unsigned long timeout; | |
172 | bool emited; | |
173 | bool signaled; | |
174 | }; | |
175 | ||
176 | int radeon_fence_driver_init(struct radeon_device *rdev); | |
177 | void radeon_fence_driver_fini(struct radeon_device *rdev); | |
178 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); | |
179 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); | |
180 | void radeon_fence_process(struct radeon_device *rdev); | |
181 | bool radeon_fence_signaled(struct radeon_fence *fence); | |
182 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); | |
183 | int radeon_fence_wait_next(struct radeon_device *rdev); | |
184 | int radeon_fence_wait_last(struct radeon_device *rdev); | |
185 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); | |
186 | void radeon_fence_unref(struct radeon_fence **fence); | |
187 | ||
e024e110 DA |
188 | /* |
189 | * Tiling registers | |
190 | */ | |
191 | struct radeon_surface_reg { | |
4c788679 | 192 | struct radeon_bo *bo; |
e024e110 DA |
193 | }; |
194 | ||
195 | #define RADEON_GEM_MAX_SURFACES 8 | |
771fe6b9 JG |
196 | |
197 | /* | |
4c788679 | 198 | * TTM. |
771fe6b9 | 199 | */ |
4c788679 JG |
200 | struct radeon_mman { |
201 | struct ttm_bo_global_ref bo_global_ref; | |
202 | struct ttm_global_reference mem_global_ref; | |
203 | bool mem_global_referenced; | |
204 | struct ttm_bo_device bdev; | |
205 | }; | |
206 | ||
207 | struct radeon_bo { | |
208 | /* Protected by gem.mutex */ | |
209 | struct list_head list; | |
210 | /* Protected by tbo.reserved */ | |
211 | struct ttm_buffer_object tbo; | |
212 | struct ttm_bo_kmap_obj kmap; | |
213 | unsigned pin_count; | |
214 | void *kptr; | |
215 | u32 tiling_flags; | |
216 | u32 pitch; | |
217 | int surface_reg; | |
218 | /* Constant after initialization */ | |
219 | struct radeon_device *rdev; | |
220 | struct drm_gem_object *gobj; | |
221 | }; | |
771fe6b9 | 222 | |
4c788679 | 223 | struct radeon_bo_list { |
771fe6b9 | 224 | struct list_head list; |
4c788679 | 225 | struct radeon_bo *bo; |
771fe6b9 JG |
226 | uint64_t gpu_offset; |
227 | unsigned rdomain; | |
228 | unsigned wdomain; | |
4c788679 | 229 | u32 tiling_flags; |
771fe6b9 JG |
230 | }; |
231 | ||
771fe6b9 JG |
232 | /* |
233 | * GEM objects. | |
234 | */ | |
235 | struct radeon_gem { | |
4c788679 | 236 | struct mutex mutex; |
771fe6b9 JG |
237 | struct list_head objects; |
238 | }; | |
239 | ||
240 | int radeon_gem_init(struct radeon_device *rdev); | |
241 | void radeon_gem_fini(struct radeon_device *rdev); | |
242 | int radeon_gem_object_create(struct radeon_device *rdev, int size, | |
4c788679 JG |
243 | int alignment, int initial_domain, |
244 | bool discardable, bool kernel, | |
245 | struct drm_gem_object **obj); | |
771fe6b9 JG |
246 | int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, |
247 | uint64_t *gpu_addr); | |
248 | void radeon_gem_object_unpin(struct drm_gem_object *obj); | |
249 | ||
250 | ||
251 | /* | |
252 | * GART structures, functions & helpers | |
253 | */ | |
254 | struct radeon_mc; | |
255 | ||
256 | struct radeon_gart_table_ram { | |
257 | volatile uint32_t *ptr; | |
258 | }; | |
259 | ||
260 | struct radeon_gart_table_vram { | |
4c788679 | 261 | struct radeon_bo *robj; |
771fe6b9 JG |
262 | volatile uint32_t *ptr; |
263 | }; | |
264 | ||
265 | union radeon_gart_table { | |
266 | struct radeon_gart_table_ram ram; | |
267 | struct radeon_gart_table_vram vram; | |
268 | }; | |
269 | ||
a77f1718 MT |
270 | #define RADEON_GPU_PAGE_SIZE 4096 |
271 | ||
771fe6b9 JG |
272 | struct radeon_gart { |
273 | dma_addr_t table_addr; | |
274 | unsigned num_gpu_pages; | |
275 | unsigned num_cpu_pages; | |
276 | unsigned table_size; | |
277 | union radeon_gart_table table; | |
278 | struct page **pages; | |
279 | dma_addr_t *pages_addr; | |
280 | bool ready; | |
281 | }; | |
282 | ||
283 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); | |
284 | void radeon_gart_table_ram_free(struct radeon_device *rdev); | |
285 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); | |
286 | void radeon_gart_table_vram_free(struct radeon_device *rdev); | |
287 | int radeon_gart_init(struct radeon_device *rdev); | |
288 | void radeon_gart_fini(struct radeon_device *rdev); | |
289 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, | |
290 | int pages); | |
291 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, | |
292 | int pages, struct page **pagelist); | |
293 | ||
294 | ||
295 | /* | |
296 | * GPU MC structures, functions & helpers | |
297 | */ | |
298 | struct radeon_mc { | |
299 | resource_size_t aper_size; | |
300 | resource_size_t aper_base; | |
301 | resource_size_t agp_base; | |
7a50f01a DA |
302 | /* for some chips with <= 32MB we need to lie |
303 | * about vram size near mc fb location */ | |
3ce0a23d JG |
304 | u64 mc_vram_size; |
305 | u64 gtt_location; | |
306 | u64 gtt_size; | |
307 | u64 gtt_start; | |
308 | u64 gtt_end; | |
309 | u64 vram_location; | |
310 | u64 vram_start; | |
311 | u64 vram_end; | |
771fe6b9 | 312 | unsigned vram_width; |
3ce0a23d | 313 | u64 real_vram_size; |
771fe6b9 JG |
314 | int vram_mtrr; |
315 | bool vram_is_ddr; | |
316 | }; | |
317 | ||
318 | int radeon_mc_setup(struct radeon_device *rdev); | |
319 | ||
320 | ||
321 | /* | |
322 | * GPU scratch registers structures, functions & helpers | |
323 | */ | |
324 | struct radeon_scratch { | |
325 | unsigned num_reg; | |
326 | bool free[32]; | |
327 | uint32_t reg[32]; | |
328 | }; | |
329 | ||
330 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); | |
331 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); | |
332 | ||
333 | ||
334 | /* | |
335 | * IRQS. | |
336 | */ | |
337 | struct radeon_irq { | |
338 | bool installed; | |
339 | bool sw_int; | |
340 | /* FIXME: use a define max crtc rather than hardcode it */ | |
341 | bool crtc_vblank_int[2]; | |
1614f8b1 DA |
342 | spinlock_t sw_lock; |
343 | int sw_refcount; | |
771fe6b9 JG |
344 | }; |
345 | ||
346 | int radeon_irq_kms_init(struct radeon_device *rdev); | |
347 | void radeon_irq_kms_fini(struct radeon_device *rdev); | |
1614f8b1 DA |
348 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev); |
349 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev); | |
771fe6b9 JG |
350 | |
351 | /* | |
352 | * CP & ring. | |
353 | */ | |
354 | struct radeon_ib { | |
355 | struct list_head list; | |
356 | unsigned long idx; | |
357 | uint64_t gpu_addr; | |
358 | struct radeon_fence *fence; | |
513bcb46 | 359 | uint32_t *ptr; |
771fe6b9 JG |
360 | uint32_t length_dw; |
361 | }; | |
362 | ||
ecb114a1 DA |
363 | /* |
364 | * locking - | |
365 | * mutex protects scheduled_ibs, ready, alloc_bm | |
366 | */ | |
771fe6b9 JG |
367 | struct radeon_ib_pool { |
368 | struct mutex mutex; | |
4c788679 | 369 | struct radeon_bo *robj; |
771fe6b9 JG |
370 | struct list_head scheduled_ibs; |
371 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; | |
372 | bool ready; | |
373 | DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE); | |
374 | }; | |
375 | ||
376 | struct radeon_cp { | |
4c788679 | 377 | struct radeon_bo *ring_obj; |
771fe6b9 JG |
378 | volatile uint32_t *ring; |
379 | unsigned rptr; | |
380 | unsigned wptr; | |
381 | unsigned wptr_old; | |
382 | unsigned ring_size; | |
383 | unsigned ring_free_dw; | |
384 | int count_dw; | |
385 | uint64_t gpu_addr; | |
386 | uint32_t align_mask; | |
387 | uint32_t ptr_mask; | |
388 | struct mutex mutex; | |
389 | bool ready; | |
390 | }; | |
391 | ||
d8f60cfc AD |
392 | /* |
393 | * R6xx+ IH ring | |
394 | */ | |
395 | struct r600_ih { | |
4c788679 | 396 | struct radeon_bo *ring_obj; |
d8f60cfc AD |
397 | volatile uint32_t *ring; |
398 | unsigned rptr; | |
399 | unsigned wptr; | |
400 | unsigned wptr_old; | |
401 | unsigned ring_size; | |
402 | uint64_t gpu_addr; | |
403 | uint32_t align_mask; | |
404 | uint32_t ptr_mask; | |
405 | spinlock_t lock; | |
406 | bool enabled; | |
407 | }; | |
408 | ||
3ce0a23d | 409 | struct r600_blit { |
4c788679 | 410 | struct radeon_bo *shader_obj; |
3ce0a23d JG |
411 | u64 shader_gpu_addr; |
412 | u32 vs_offset, ps_offset; | |
413 | u32 state_offset; | |
414 | u32 state_len; | |
415 | u32 vb_used, vb_total; | |
416 | struct radeon_ib *vb_ib; | |
417 | }; | |
418 | ||
771fe6b9 JG |
419 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); |
420 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); | |
421 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); | |
422 | int radeon_ib_pool_init(struct radeon_device *rdev); | |
423 | void radeon_ib_pool_fini(struct radeon_device *rdev); | |
424 | int radeon_ib_test(struct radeon_device *rdev); | |
425 | /* Ring access between begin & end cannot sleep */ | |
426 | void radeon_ring_free_size(struct radeon_device *rdev); | |
427 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); | |
428 | void radeon_ring_unlock_commit(struct radeon_device *rdev); | |
429 | void radeon_ring_unlock_undo(struct radeon_device *rdev); | |
430 | int radeon_ring_test(struct radeon_device *rdev); | |
431 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
432 | void radeon_ring_fini(struct radeon_device *rdev); | |
433 | ||
434 | ||
435 | /* | |
436 | * CS. | |
437 | */ | |
438 | struct radeon_cs_reloc { | |
439 | struct drm_gem_object *gobj; | |
4c788679 JG |
440 | struct radeon_bo *robj; |
441 | struct radeon_bo_list lobj; | |
771fe6b9 JG |
442 | uint32_t handle; |
443 | uint32_t flags; | |
444 | }; | |
445 | ||
446 | struct radeon_cs_chunk { | |
447 | uint32_t chunk_id; | |
448 | uint32_t length_dw; | |
513bcb46 DA |
449 | int kpage_idx[2]; |
450 | uint32_t *kpage[2]; | |
771fe6b9 | 451 | uint32_t *kdata; |
513bcb46 DA |
452 | void __user *user_ptr; |
453 | int last_copied_page; | |
454 | int last_page_index; | |
771fe6b9 JG |
455 | }; |
456 | ||
457 | struct radeon_cs_parser { | |
458 | struct radeon_device *rdev; | |
459 | struct drm_file *filp; | |
460 | /* chunks */ | |
461 | unsigned nchunks; | |
462 | struct radeon_cs_chunk *chunks; | |
463 | uint64_t *chunks_array; | |
464 | /* IB */ | |
465 | unsigned idx; | |
466 | /* relocations */ | |
467 | unsigned nrelocs; | |
468 | struct radeon_cs_reloc *relocs; | |
469 | struct radeon_cs_reloc **relocs_ptr; | |
470 | struct list_head validated; | |
471 | /* indices of various chunks */ | |
472 | int chunk_ib_idx; | |
473 | int chunk_relocs_idx; | |
474 | struct radeon_ib *ib; | |
475 | void *track; | |
3ce0a23d | 476 | unsigned family; |
513bcb46 | 477 | int parser_error; |
771fe6b9 JG |
478 | }; |
479 | ||
513bcb46 DA |
480 | extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); |
481 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); | |
482 | ||
483 | ||
484 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) | |
485 | { | |
486 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; | |
487 | u32 pg_idx, pg_offset; | |
488 | u32 idx_value = 0; | |
489 | int new_page; | |
490 | ||
491 | pg_idx = (idx * 4) / PAGE_SIZE; | |
492 | pg_offset = (idx * 4) % PAGE_SIZE; | |
493 | ||
494 | if (ibc->kpage_idx[0] == pg_idx) | |
495 | return ibc->kpage[0][pg_offset/4]; | |
496 | if (ibc->kpage_idx[1] == pg_idx) | |
497 | return ibc->kpage[1][pg_offset/4]; | |
498 | ||
499 | new_page = radeon_cs_update_pages(p, pg_idx); | |
500 | if (new_page < 0) { | |
501 | p->parser_error = new_page; | |
502 | return 0; | |
503 | } | |
504 | ||
505 | idx_value = ibc->kpage[new_page][pg_offset/4]; | |
506 | return idx_value; | |
507 | } | |
508 | ||
771fe6b9 JG |
509 | struct radeon_cs_packet { |
510 | unsigned idx; | |
511 | unsigned type; | |
512 | unsigned reg; | |
513 | unsigned opcode; | |
514 | int count; | |
515 | unsigned one_reg_wr; | |
516 | }; | |
517 | ||
518 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, | |
519 | struct radeon_cs_packet *pkt, | |
520 | unsigned idx, unsigned reg); | |
521 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, | |
522 | struct radeon_cs_packet *pkt); | |
523 | ||
524 | ||
525 | /* | |
526 | * AGP | |
527 | */ | |
528 | int radeon_agp_init(struct radeon_device *rdev); | |
0ebf1717 | 529 | void radeon_agp_resume(struct radeon_device *rdev); |
771fe6b9 JG |
530 | void radeon_agp_fini(struct radeon_device *rdev); |
531 | ||
532 | ||
533 | /* | |
534 | * Writeback | |
535 | */ | |
536 | struct radeon_wb { | |
4c788679 | 537 | struct radeon_bo *wb_obj; |
771fe6b9 JG |
538 | volatile uint32_t *wb; |
539 | uint64_t gpu_addr; | |
540 | }; | |
541 | ||
c93bb85b JG |
542 | /** |
543 | * struct radeon_pm - power management datas | |
544 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) | |
545 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) | |
546 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) | |
547 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) | |
548 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) | |
549 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) | |
550 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) | |
551 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) | |
552 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) | |
553 | * @sclk: GPU clock Mhz (core bandwith depends of this clock) | |
554 | * @needed_bandwidth: current bandwidth needs | |
555 | * | |
556 | * It keeps track of various data needed to take powermanagement decision. | |
557 | * Bandwith need is used to determine minimun clock of the GPU and memory. | |
558 | * Equation between gpu/memory clock and available bandwidth is hw dependent | |
559 | * (type of memory, bus size, efficiency, ...) | |
560 | */ | |
561 | struct radeon_pm { | |
562 | fixed20_12 max_bandwidth; | |
563 | fixed20_12 igp_sideport_mclk; | |
564 | fixed20_12 igp_system_mclk; | |
565 | fixed20_12 igp_ht_link_clk; | |
566 | fixed20_12 igp_ht_link_width; | |
567 | fixed20_12 k8_bandwidth; | |
568 | fixed20_12 sideport_bandwidth; | |
569 | fixed20_12 ht_bandwidth; | |
570 | fixed20_12 core_bandwidth; | |
571 | fixed20_12 sclk; | |
572 | fixed20_12 needed_bandwidth; | |
573 | }; | |
574 | ||
771fe6b9 JG |
575 | |
576 | /* | |
577 | * Benchmarking | |
578 | */ | |
579 | void radeon_benchmark(struct radeon_device *rdev); | |
580 | ||
581 | ||
ecc0b326 MD |
582 | /* |
583 | * Testing | |
584 | */ | |
585 | void radeon_test_moves(struct radeon_device *rdev); | |
586 | ||
587 | ||
771fe6b9 JG |
588 | /* |
589 | * Debugfs | |
590 | */ | |
591 | int radeon_debugfs_add_files(struct radeon_device *rdev, | |
592 | struct drm_info_list *files, | |
593 | unsigned nfiles); | |
594 | int radeon_debugfs_fence_init(struct radeon_device *rdev); | |
595 | int r100_debugfs_rbbm_init(struct radeon_device *rdev); | |
596 | int r100_debugfs_cp_init(struct radeon_device *rdev); | |
597 | ||
598 | ||
599 | /* | |
600 | * ASIC specific functions. | |
601 | */ | |
602 | struct radeon_asic { | |
068a117c | 603 | int (*init)(struct radeon_device *rdev); |
3ce0a23d JG |
604 | void (*fini)(struct radeon_device *rdev); |
605 | int (*resume)(struct radeon_device *rdev); | |
606 | int (*suspend)(struct radeon_device *rdev); | |
28d52043 | 607 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
771fe6b9 | 608 | int (*gpu_reset)(struct radeon_device *rdev); |
771fe6b9 JG |
609 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
610 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); | |
611 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); | |
612 | void (*cp_fini)(struct radeon_device *rdev); | |
613 | void (*cp_disable)(struct radeon_device *rdev); | |
3ce0a23d | 614 | void (*cp_commit)(struct radeon_device *rdev); |
771fe6b9 | 615 | void (*ring_start)(struct radeon_device *rdev); |
3ce0a23d JG |
616 | int (*ring_test)(struct radeon_device *rdev); |
617 | void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); | |
771fe6b9 JG |
618 | int (*irq_set)(struct radeon_device *rdev); |
619 | int (*irq_process)(struct radeon_device *rdev); | |
7ed220d7 | 620 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
771fe6b9 JG |
621 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
622 | int (*cs_parse)(struct radeon_cs_parser *p); | |
623 | int (*copy_blit)(struct radeon_device *rdev, | |
624 | uint64_t src_offset, | |
625 | uint64_t dst_offset, | |
626 | unsigned num_pages, | |
627 | struct radeon_fence *fence); | |
628 | int (*copy_dma)(struct radeon_device *rdev, | |
629 | uint64_t src_offset, | |
630 | uint64_t dst_offset, | |
631 | unsigned num_pages, | |
632 | struct radeon_fence *fence); | |
633 | int (*copy)(struct radeon_device *rdev, | |
634 | uint64_t src_offset, | |
635 | uint64_t dst_offset, | |
636 | unsigned num_pages, | |
637 | struct radeon_fence *fence); | |
7433874e | 638 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
771fe6b9 | 639 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
7433874e | 640 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
771fe6b9 JG |
641 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
642 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); | |
643 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); | |
e024e110 DA |
644 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
645 | uint32_t tiling_flags, uint32_t pitch, | |
646 | uint32_t offset, uint32_t obj_size); | |
647 | int (*clear_surface_reg)(struct radeon_device *rdev, int reg); | |
c93bb85b | 648 | void (*bandwidth_update)(struct radeon_device *rdev); |
23956dfa | 649 | void (*hdp_flush)(struct radeon_device *rdev); |
771fe6b9 JG |
650 | }; |
651 | ||
21f9a437 JG |
652 | /* |
653 | * Asic structures | |
654 | */ | |
551ebd83 DA |
655 | struct r100_asic { |
656 | const unsigned *reg_safe_bm; | |
657 | unsigned reg_safe_bm_size; | |
658 | }; | |
659 | ||
21f9a437 JG |
660 | struct r300_asic { |
661 | const unsigned *reg_safe_bm; | |
662 | unsigned reg_safe_bm_size; | |
663 | }; | |
664 | ||
665 | struct r600_asic { | |
666 | unsigned max_pipes; | |
667 | unsigned max_tile_pipes; | |
668 | unsigned max_simds; | |
669 | unsigned max_backends; | |
670 | unsigned max_gprs; | |
671 | unsigned max_threads; | |
672 | unsigned max_stack_entries; | |
673 | unsigned max_hw_contexts; | |
674 | unsigned max_gs_threads; | |
675 | unsigned sx_max_export_size; | |
676 | unsigned sx_max_export_pos_size; | |
677 | unsigned sx_max_export_smx_size; | |
678 | unsigned sq_num_cf_insts; | |
679 | }; | |
680 | ||
681 | struct rv770_asic { | |
682 | unsigned max_pipes; | |
683 | unsigned max_tile_pipes; | |
684 | unsigned max_simds; | |
685 | unsigned max_backends; | |
686 | unsigned max_gprs; | |
687 | unsigned max_threads; | |
688 | unsigned max_stack_entries; | |
689 | unsigned max_hw_contexts; | |
690 | unsigned max_gs_threads; | |
691 | unsigned sx_max_export_size; | |
692 | unsigned sx_max_export_pos_size; | |
693 | unsigned sx_max_export_smx_size; | |
694 | unsigned sq_num_cf_insts; | |
695 | unsigned sx_num_of_sets; | |
696 | unsigned sc_prim_fifo_size; | |
697 | unsigned sc_hiz_tile_fifo_size; | |
698 | unsigned sc_earlyz_tile_fifo_fize; | |
699 | }; | |
700 | ||
068a117c JG |
701 | union radeon_asic_config { |
702 | struct r300_asic r300; | |
551ebd83 | 703 | struct r100_asic r100; |
3ce0a23d JG |
704 | struct r600_asic r600; |
705 | struct rv770_asic rv770; | |
068a117c JG |
706 | }; |
707 | ||
771fe6b9 JG |
708 | |
709 | /* | |
710 | * IOCTL. | |
711 | */ | |
712 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, | |
713 | struct drm_file *filp); | |
714 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, | |
715 | struct drm_file *filp); | |
716 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, | |
717 | struct drm_file *file_priv); | |
718 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
719 | struct drm_file *file_priv); | |
720 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
721 | struct drm_file *file_priv); | |
722 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, | |
723 | struct drm_file *file_priv); | |
724 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
725 | struct drm_file *filp); | |
726 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
727 | struct drm_file *filp); | |
728 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, | |
729 | struct drm_file *filp); | |
730 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
731 | struct drm_file *filp); | |
732 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); | |
e024e110 DA |
733 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
734 | struct drm_file *filp); | |
735 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | |
736 | struct drm_file *filp); | |
771fe6b9 JG |
737 | |
738 | ||
739 | /* | |
740 | * Core structure, functions and helpers. | |
741 | */ | |
742 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); | |
743 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); | |
744 | ||
745 | struct radeon_device { | |
9f022ddf | 746 | struct device *dev; |
771fe6b9 JG |
747 | struct drm_device *ddev; |
748 | struct pci_dev *pdev; | |
749 | /* ASIC */ | |
068a117c | 750 | union radeon_asic_config config; |
771fe6b9 JG |
751 | enum radeon_family family; |
752 | unsigned long flags; | |
753 | int usec_timeout; | |
754 | enum radeon_pll_errata pll_errata; | |
755 | int num_gb_pipes; | |
f779b3e5 | 756 | int num_z_pipes; |
771fe6b9 JG |
757 | int disp_priority; |
758 | /* BIOS */ | |
759 | uint8_t *bios; | |
760 | bool is_atom_bios; | |
761 | uint16_t bios_header_start; | |
4c788679 | 762 | struct radeon_bo *stollen_vga_memory; |
771fe6b9 | 763 | struct fb_info *fbdev_info; |
4c788679 | 764 | struct radeon_bo *fbdev_rbo; |
771fe6b9 JG |
765 | struct radeon_framebuffer *fbdev_rfb; |
766 | /* Register mmio */ | |
4c9bc75c DA |
767 | resource_size_t rmmio_base; |
768 | resource_size_t rmmio_size; | |
771fe6b9 | 769 | void *rmmio; |
771fe6b9 JG |
770 | radeon_rreg_t mc_rreg; |
771 | radeon_wreg_t mc_wreg; | |
772 | radeon_rreg_t pll_rreg; | |
773 | radeon_wreg_t pll_wreg; | |
de1b2898 | 774 | uint32_t pcie_reg_mask; |
771fe6b9 JG |
775 | radeon_rreg_t pciep_rreg; |
776 | radeon_wreg_t pciep_wreg; | |
777 | struct radeon_clock clock; | |
778 | struct radeon_mc mc; | |
779 | struct radeon_gart gart; | |
780 | struct radeon_mode_info mode_info; | |
781 | struct radeon_scratch scratch; | |
782 | struct radeon_mman mman; | |
783 | struct radeon_fence_driver fence_drv; | |
784 | struct radeon_cp cp; | |
785 | struct radeon_ib_pool ib_pool; | |
786 | struct radeon_irq irq; | |
787 | struct radeon_asic *asic; | |
788 | struct radeon_gem gem; | |
c93bb85b | 789 | struct radeon_pm pm; |
f657c2a7 | 790 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
771fe6b9 JG |
791 | struct mutex cs_mutex; |
792 | struct radeon_wb wb; | |
3ce0a23d | 793 | struct radeon_dummy_page dummy_page; |
771fe6b9 JG |
794 | bool gpu_lockup; |
795 | bool shutdown; | |
796 | bool suspend; | |
ad49f501 | 797 | bool need_dma32; |
733289c2 | 798 | bool accel_working; |
e024e110 | 799 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
3ce0a23d JG |
800 | const struct firmware *me_fw; /* all family ME firmware */ |
801 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ | |
d8f60cfc | 802 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
3ce0a23d | 803 | struct r600_blit r600_blit; |
3e5cb98d | 804 | int msi_enabled; /* msi enabled */ |
d8f60cfc | 805 | struct r600_ih ih; /* r6/700 interrupt ring */ |
771fe6b9 JG |
806 | }; |
807 | ||
808 | int radeon_device_init(struct radeon_device *rdev, | |
809 | struct drm_device *ddev, | |
810 | struct pci_dev *pdev, | |
811 | uint32_t flags); | |
812 | void radeon_device_fini(struct radeon_device *rdev); | |
813 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); | |
814 | ||
3ce0a23d JG |
815 | /* r600 blit */ |
816 | int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes); | |
817 | void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence); | |
818 | void r600_kms_blit_copy(struct radeon_device *rdev, | |
819 | u64 src_gpu_addr, u64 dst_gpu_addr, | |
820 | int size_bytes); | |
821 | ||
de1b2898 DA |
822 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
823 | { | |
824 | if (reg < 0x10000) | |
825 | return readl(((void __iomem *)rdev->rmmio) + reg); | |
826 | else { | |
827 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); | |
828 | return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); | |
829 | } | |
830 | } | |
831 | ||
832 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
833 | { | |
834 | if (reg < 0x10000) | |
835 | writel(v, ((void __iomem *)rdev->rmmio) + reg); | |
836 | else { | |
837 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); | |
838 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); | |
839 | } | |
840 | } | |
841 | ||
4c788679 JG |
842 | /* |
843 | * Cast helper | |
844 | */ | |
845 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) | |
771fe6b9 JG |
846 | |
847 | /* | |
848 | * Registers read & write functions. | |
849 | */ | |
850 | #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) | |
851 | #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) | |
de1b2898 | 852 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
3ce0a23d | 853 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) |
de1b2898 | 854 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
771fe6b9 JG |
855 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
856 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
857 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) | |
858 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) | |
859 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) | |
860 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) | |
de1b2898 DA |
861 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
862 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) | |
771fe6b9 JG |
863 | #define WREG32_P(reg, val, mask) \ |
864 | do { \ | |
865 | uint32_t tmp_ = RREG32(reg); \ | |
866 | tmp_ &= (mask); \ | |
867 | tmp_ |= ((val) & ~(mask)); \ | |
868 | WREG32(reg, tmp_); \ | |
869 | } while (0) | |
870 | #define WREG32_PLL_P(reg, val, mask) \ | |
871 | do { \ | |
872 | uint32_t tmp_ = RREG32_PLL(reg); \ | |
873 | tmp_ &= (mask); \ | |
874 | tmp_ |= ((val) & ~(mask)); \ | |
875 | WREG32_PLL(reg, tmp_); \ | |
876 | } while (0) | |
3ce0a23d | 877 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) |
771fe6b9 | 878 | |
de1b2898 DA |
879 | /* |
880 | * Indirect registers accessor | |
881 | */ | |
882 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) | |
883 | { | |
884 | uint32_t r; | |
885 | ||
886 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
887 | r = RREG32(RADEON_PCIE_DATA); | |
888 | return r; | |
889 | } | |
890 | ||
891 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
892 | { | |
893 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
894 | WREG32(RADEON_PCIE_DATA, (v)); | |
895 | } | |
896 | ||
771fe6b9 JG |
897 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
898 | ||
899 | ||
900 | /* | |
901 | * ASICs helpers. | |
902 | */ | |
b995e433 DA |
903 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
904 | (rdev->pdev->device == 0x5969)) | |
771fe6b9 JG |
905 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
906 | (rdev->family == CHIP_RV200) || \ | |
907 | (rdev->family == CHIP_RS100) || \ | |
908 | (rdev->family == CHIP_RS200) || \ | |
909 | (rdev->family == CHIP_RV250) || \ | |
910 | (rdev->family == CHIP_RV280) || \ | |
911 | (rdev->family == CHIP_RS300)) | |
912 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ | |
913 | (rdev->family == CHIP_RV350) || \ | |
914 | (rdev->family == CHIP_R350) || \ | |
915 | (rdev->family == CHIP_RV380) || \ | |
916 | (rdev->family == CHIP_R420) || \ | |
917 | (rdev->family == CHIP_R423) || \ | |
918 | (rdev->family == CHIP_RV410) || \ | |
919 | (rdev->family == CHIP_RS400) || \ | |
920 | (rdev->family == CHIP_RS480)) | |
921 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) | |
922 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) | |
923 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) | |
924 | ||
925 | ||
926 | /* | |
927 | * BIOS helpers. | |
928 | */ | |
929 | #define RBIOS8(i) (rdev->bios[i]) | |
930 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) | |
931 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) | |
932 | ||
933 | int radeon_combios_init(struct radeon_device *rdev); | |
934 | void radeon_combios_fini(struct radeon_device *rdev); | |
935 | int radeon_atombios_init(struct radeon_device *rdev); | |
936 | void radeon_atombios_fini(struct radeon_device *rdev); | |
937 | ||
938 | ||
939 | /* | |
940 | * RING helpers. | |
941 | */ | |
771fe6b9 JG |
942 | static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
943 | { | |
944 | #if DRM_DEBUG_CODE | |
945 | if (rdev->cp.count_dw <= 0) { | |
946 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); | |
947 | } | |
948 | #endif | |
949 | rdev->cp.ring[rdev->cp.wptr++] = v; | |
950 | rdev->cp.wptr &= rdev->cp.ptr_mask; | |
951 | rdev->cp.count_dw--; | |
952 | rdev->cp.ring_free_dw--; | |
953 | } | |
954 | ||
955 | ||
956 | /* | |
957 | * ASICs macro. | |
958 | */ | |
068a117c | 959 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
3ce0a23d JG |
960 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
961 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) | |
962 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) | |
771fe6b9 | 963 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
28d52043 | 964 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
771fe6b9 | 965 | #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) |
771fe6b9 JG |
966 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
967 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) | |
3ce0a23d | 968 | #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
771fe6b9 | 969 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
3ce0a23d JG |
970 | #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) |
971 | #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) | |
771fe6b9 JG |
972 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
973 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) | |
7ed220d7 | 974 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
771fe6b9 JG |
975 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
976 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) | |
977 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) | |
978 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) | |
7433874e | 979 | #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) |
771fe6b9 | 980 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
7433874e | 981 | #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) |
771fe6b9 JG |
982 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
983 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) | |
984 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) | |
e024e110 DA |
985 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) |
986 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) | |
c93bb85b | 987 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
23956dfa | 988 | #define radeon_hdp_flush(rdev) (rdev)->asic->hdp_flush((rdev)) |
771fe6b9 | 989 | |
6cf8a3f5 | 990 | /* Common functions */ |
4aac0473 | 991 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
21f9a437 JG |
992 | extern int radeon_modeset_init(struct radeon_device *rdev); |
993 | extern void radeon_modeset_fini(struct radeon_device *rdev); | |
9f022ddf | 994 | extern bool radeon_card_posted(struct radeon_device *rdev); |
72542d77 | 995 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
21f9a437 JG |
996 | extern int radeon_clocks_init(struct radeon_device *rdev); |
997 | extern void radeon_clocks_fini(struct radeon_device *rdev); | |
998 | extern void radeon_scratch_init(struct radeon_device *rdev); | |
999 | extern void radeon_surface_init(struct radeon_device *rdev); | |
1000 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); | |
ca6ffc64 | 1001 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
d39c3b89 | 1002 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
6cf8a3f5 | 1003 | |
a18d7ea1 | 1004 | /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ |
9f022ddf JG |
1005 | struct r100_mc_save { |
1006 | u32 GENMO_WT; | |
1007 | u32 CRTC_EXT_CNTL; | |
1008 | u32 CRTC_GEN_CNTL; | |
1009 | u32 CRTC2_GEN_CNTL; | |
1010 | u32 CUR_OFFSET; | |
1011 | u32 CUR2_OFFSET; | |
1012 | }; | |
1013 | extern void r100_cp_disable(struct radeon_device *rdev); | |
1014 | extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); | |
1015 | extern void r100_cp_fini(struct radeon_device *rdev); | |
21f9a437 | 1016 | extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
4aac0473 JG |
1017 | extern int r100_pci_gart_init(struct radeon_device *rdev); |
1018 | extern void r100_pci_gart_fini(struct radeon_device *rdev); | |
21f9a437 JG |
1019 | extern int r100_pci_gart_enable(struct radeon_device *rdev); |
1020 | extern void r100_pci_gart_disable(struct radeon_device *rdev); | |
1021 | extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | |
9f022ddf JG |
1022 | extern int r100_debugfs_mc_info_init(struct radeon_device *rdev); |
1023 | extern int r100_gui_wait_for_idle(struct radeon_device *rdev); | |
1024 | extern void r100_ib_fini(struct radeon_device *rdev); | |
1025 | extern int r100_ib_init(struct radeon_device *rdev); | |
1026 | extern void r100_irq_disable(struct radeon_device *rdev); | |
1027 | extern int r100_irq_set(struct radeon_device *rdev); | |
1028 | extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); | |
1029 | extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); | |
21f9a437 | 1030 | extern void r100_vram_init_sizes(struct radeon_device *rdev); |
9f022ddf JG |
1031 | extern void r100_wb_disable(struct radeon_device *rdev); |
1032 | extern void r100_wb_fini(struct radeon_device *rdev); | |
1033 | extern int r100_wb_init(struct radeon_device *rdev); | |
d39c3b89 JG |
1034 | extern void r100_hdp_reset(struct radeon_device *rdev); |
1035 | extern int r100_rb2d_reset(struct radeon_device *rdev); | |
1036 | extern int r100_cp_reset(struct radeon_device *rdev); | |
ca6ffc64 | 1037 | extern void r100_vga_render_disable(struct radeon_device *rdev); |
207bf9e9 JG |
1038 | extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
1039 | struct radeon_cs_packet *pkt, | |
4c788679 | 1040 | struct radeon_bo *robj); |
207bf9e9 JG |
1041 | extern int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
1042 | struct radeon_cs_packet *pkt, | |
1043 | const unsigned *auth, unsigned n, | |
1044 | radeon_packet0_check_t check); | |
1045 | extern int r100_cs_packet_parse(struct radeon_cs_parser *p, | |
1046 | struct radeon_cs_packet *pkt, | |
1047 | unsigned idx); | |
17e15b0c | 1048 | extern void r100_enable_bm(struct radeon_device *rdev); |
9f022ddf | 1049 | |
d4550907 JG |
1050 | /* rv200,rv250,rv280 */ |
1051 | extern void r200_set_safe_registers(struct radeon_device *rdev); | |
9f022ddf JG |
1052 | |
1053 | /* r300,r350,rv350,rv370,rv380 */ | |
1054 | extern void r300_set_reg_safe(struct radeon_device *rdev); | |
1055 | extern void r300_mc_program(struct radeon_device *rdev); | |
1056 | extern void r300_vram_info(struct radeon_device *rdev); | |
ca6ffc64 JG |
1057 | extern void r300_clock_startup(struct radeon_device *rdev); |
1058 | extern int r300_mc_wait_for_idle(struct radeon_device *rdev); | |
4aac0473 JG |
1059 | extern int rv370_pcie_gart_init(struct radeon_device *rdev); |
1060 | extern void rv370_pcie_gart_fini(struct radeon_device *rdev); | |
1061 | extern int rv370_pcie_gart_enable(struct radeon_device *rdev); | |
9f022ddf | 1062 | extern void rv370_pcie_gart_disable(struct radeon_device *rdev); |
a18d7ea1 | 1063 | |
905b6822 | 1064 | /* r420,r423,rv410 */ |
d39c3b89 | 1065 | extern int r420_mc_init(struct radeon_device *rdev); |
21f9a437 JG |
1066 | extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); |
1067 | extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); | |
9f022ddf | 1068 | extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); |
d39c3b89 | 1069 | extern void r420_pipes_init(struct radeon_device *rdev); |
905b6822 | 1070 | |
21f9a437 | 1071 | /* rv515 */ |
d39c3b89 JG |
1072 | struct rv515_mc_save { |
1073 | u32 d1vga_control; | |
1074 | u32 d2vga_control; | |
1075 | u32 vga_render_control; | |
1076 | u32 vga_hdp_control; | |
1077 | u32 d1crtc_control; | |
1078 | u32 d2crtc_control; | |
1079 | }; | |
21f9a437 | 1080 | extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev); |
d39c3b89 JG |
1081 | extern void rv515_vga_render_disable(struct radeon_device *rdev); |
1082 | extern void rv515_set_safe_registers(struct radeon_device *rdev); | |
f0ed1f65 JG |
1083 | extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); |
1084 | extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); | |
1085 | extern void rv515_clock_startup(struct radeon_device *rdev); | |
1086 | extern void rv515_debugfs(struct radeon_device *rdev); | |
1087 | extern int rv515_suspend(struct radeon_device *rdev); | |
21f9a437 | 1088 | |
3bc68535 JG |
1089 | /* rs400 */ |
1090 | extern int rs400_gart_init(struct radeon_device *rdev); | |
1091 | extern int rs400_gart_enable(struct radeon_device *rdev); | |
1092 | extern void rs400_gart_adjust_size(struct radeon_device *rdev); | |
1093 | extern void rs400_gart_disable(struct radeon_device *rdev); | |
1094 | extern void rs400_gart_fini(struct radeon_device *rdev); | |
1095 | ||
1096 | /* rs600 */ | |
1097 | extern void rs600_set_safe_registers(struct radeon_device *rdev); | |
ac447df4 JG |
1098 | extern int rs600_irq_set(struct radeon_device *rdev); |
1099 | extern void rs600_irq_disable(struct radeon_device *rdev); | |
3bc68535 | 1100 | |
21f9a437 JG |
1101 | /* rs690, rs740 */ |
1102 | extern void rs690_line_buffer_adjust(struct radeon_device *rdev, | |
1103 | struct drm_display_mode *mode1, | |
1104 | struct drm_display_mode *mode2); | |
1105 | ||
1106 | /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ | |
1107 | extern bool r600_card_posted(struct radeon_device *rdev); | |
1108 | extern void r600_cp_stop(struct radeon_device *rdev); | |
1109 | extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
1110 | extern int r600_cp_resume(struct radeon_device *rdev); | |
1111 | extern int r600_count_pipe_bits(uint32_t val); | |
1112 | extern int r600_gart_clear_page(struct radeon_device *rdev, int i); | |
1113 | extern int r600_mc_wait_for_idle(struct radeon_device *rdev); | |
4aac0473 | 1114 | extern int r600_pcie_gart_init(struct radeon_device *rdev); |
21f9a437 JG |
1115 | extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
1116 | extern int r600_ib_test(struct radeon_device *rdev); | |
1117 | extern int r600_ring_test(struct radeon_device *rdev); | |
21f9a437 | 1118 | extern void r600_wb_fini(struct radeon_device *rdev); |
81cc35bf JG |
1119 | extern int r600_wb_enable(struct radeon_device *rdev); |
1120 | extern void r600_wb_disable(struct radeon_device *rdev); | |
21f9a437 JG |
1121 | extern void r600_scratch_init(struct radeon_device *rdev); |
1122 | extern int r600_blit_init(struct radeon_device *rdev); | |
1123 | extern void r600_blit_fini(struct radeon_device *rdev); | |
d8f60cfc | 1124 | extern int r600_init_microcode(struct radeon_device *rdev); |
fe62e1a4 | 1125 | extern int r600_gpu_reset(struct radeon_device *rdev); |
d8f60cfc AD |
1126 | /* r600 irq */ |
1127 | extern int r600_irq_init(struct radeon_device *rdev); | |
1128 | extern void r600_irq_fini(struct radeon_device *rdev); | |
1129 | extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); | |
1130 | extern int r600_irq_set(struct radeon_device *rdev); | |
21f9a437 | 1131 | |
4c788679 JG |
1132 | #include "radeon_object.h" |
1133 | ||
771fe6b9 | 1134 | #endif |