projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon: update radeon_atom_is_voltage_gpio() for SI
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
a18cee15 96extern int radeon_msi;
3368ff0c 97extern int radeon_lockup_timeout;
a0a53aa8 98extern int radeon_fastfb;
da321c8a 99extern int radeon_dpm;
771fe6b9
JG		 100
101/*
102 * Copy from radeon_drv.h so we don't have to include both and have conflicting
103 * symbol;
104 */
bb635567
JG		 105#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
106#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 107/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 108#define RADEON_IB_POOL_SIZE 16
109#define RADEON_DEBUGFS_MAX_COMPONENTS 32
110#define RADEONFB_CONN_LIMIT 4
111#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 112
1b37078b 113/* max number of rings */
f2ba57b5 114#define RADEON_NUM_RINGS 6
bb635567
JG		 115
116/* fence seq are set to this number when signaled */
117#define RADEON_FENCE_SIGNALED_SEQ 0LL
1b37078b
AD		 118
119/* internal ring indices */
120/* r1xx+ has gfx CP ring */
f2ba57b5 121#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 122
123/* cayman has 2 compute CP rings */
f2ba57b5
CK		 124#define CAYMAN_RING_TYPE_CP1_INDEX 1
125#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 126
4d75658b
AD		 127/* R600+ has an async dma ring */
128#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 129/* cayman add a second async dma ring */
130#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 131
f2ba57b5
CK		 132/* R600+ */
133#define R600_RING_TYPE_UVD_INDEX 5
134
721604a1 135/* hardcode those limit for now */
ca19f21e 136#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 137#define RADEON_VA_RESERVED_SIZE (8 << 20)
138#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 139
ec46c76d
AD		 140/* reset flags */
141#define RADEON_RESET_GFX (1 << 0)
142#define RADEON_RESET_COMPUTE (1 << 1)
143#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 144#define RADEON_RESET_CP (1 << 3)
145#define RADEON_RESET_GRBM (1 << 4)
146#define RADEON_RESET_DMA1 (1 << 5)
147#define RADEON_RESET_RLC (1 << 6)
148#define RADEON_RESET_SEM (1 << 7)
149#define RADEON_RESET_IH (1 << 8)
150#define RADEON_RESET_VMC (1 << 9)
151#define RADEON_RESET_MC (1 << 10)
152#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 153
9e05fa1d
AD		 154/* max cursor sizes (in pixels) */
155#define CURSOR_WIDTH 64
156#define CURSOR_HEIGHT 64
157
158#define CIK_CURSOR_WIDTH 128
159#define CIK_CURSOR_HEIGHT 128
160
771fe6b9
JG		 161/*
162 * Errata workarounds.
163 */
164enum radeon_pll_errata {
165 CHIP_ERRATA_R300_CG = 0x00000001,
166 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
167 CHIP_ERRATA_PLL_DELAY = 0x00000004
168};
169
170
171struct radeon_device;
172
173
174/*
175 * BIOS.
176 */
177bool radeon_get_bios(struct radeon_device *rdev);
178
179/*
3ce0a23d 180 * Dummy page
771fe6b9 181 */
3ce0a23d
JG		 182struct radeon_dummy_page {
183 struct page *page;
184 dma_addr_t addr;
185};
186int radeon_dummy_page_init(struct radeon_device *rdev);
187void radeon_dummy_page_fini(struct radeon_device *rdev);
188
771fe6b9 189
3ce0a23d
JG		 190/*
191 * Clocks
192 */
771fe6b9
JG		 193struct radeon_clock {
194 struct radeon_pll p1pll;
195 struct radeon_pll p2pll;
bcc1c2a1 196 struct radeon_pll dcpll;
771fe6b9
JG		 197 struct radeon_pll spll;
198 struct radeon_pll mpll;
199 /* 10 Khz units */
200 uint32_t default_mclk;
201 uint32_t default_sclk;
bcc1c2a1
AD		 202 uint32_t default_dispclk;
203 uint32_t dp_extclk;
b20f9bef 204 uint32_t max_pixel_clock;
771fe6b9
JG		 205};
206
7433874e
RM		 207/*
208 * Power management
209 */
210int radeon_pm_init(struct radeon_device *rdev);
29fb52ca 211void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 212void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 213void radeon_pm_suspend(struct radeon_device *rdev);
214void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 215void radeon_combios_get_power_modes(struct radeon_device *rdev);
216void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 217int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
218 u8 clock_type,
219 u32 clock,
220 bool strobe_mode,
221 struct atom_clock_dividers *dividers);
eaa778af
AD		 222int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
223 u32 clock,
224 bool strobe_mode,
225 struct atom_mpll_param *mpll_param);
8a83ec5e 226void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 227int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
228 u16 voltage_level, u8 voltage_type,
229 u32 *gpio_value, u32 *gpio_mask);
230void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
231 u32 eng_clock, u32 mem_clock);
232int radeon_atom_get_voltage_step(struct radeon_device *rdev,
233 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 234int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
235 u16 voltage_id, u16 *voltage);
ae5b0abb
AD		 236int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
237 u8 voltage_type,
238 u16 nominal_voltage,
239 u16 *true_voltage);
240int radeon_atom_get_min_voltage(struct radeon_device *rdev,
241 u8 voltage_type, u16 *min_voltage);
242int radeon_atom_get_max_voltage(struct radeon_device *rdev,
243 u8 voltage_type, u16 *max_voltage);
244int radeon_atom_get_voltage_table(struct radeon_device *rdev,
245 u8 voltage_type,
246 struct atom_voltage_table *voltage_table);
58653abd
AD		 247bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
248 u8 voltage_type, u8 voltage_mode);
ae5b0abb
AD		 249void radeon_atom_update_memory_dll(struct radeon_device *rdev,
250 u32 mem_clock);
251void radeon_atom_set_ac_timing(struct radeon_device *rdev,
252 u32 mem_clock);
253int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
254 u8 module_index,
255 struct atom_mc_reg_table *reg_table);
256int radeon_atom_get_memory_info(struct radeon_device *rdev,
257 u8 module_index, struct atom_memory_info *mem_info);
258int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
259 bool gddr5, u8 module_index,
260 struct atom_memory_clock_range_table *mclk_range_table);
261int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
262 u16 voltage_id, u16 *voltage);
f892034a 263void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 264extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
265 unsigned *bankh, unsigned *mtaspect,
266 unsigned *tile_split);
3ce0a23d 267
771fe6b9
JG		 268/*
269 * Fences.
270 */
271struct radeon_fence_driver {
272 uint32_t scratch_reg;
30eb77f4
JG		 273 uint64_t gpu_addr;
274 volatile uint32_t *cpu_addr;
68e250b7
CK		 275 /* sync_seq is protected by ring emission lock */
276 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 277 atomic64_t last_seq;
36abacae 278 unsigned long last_activity;
0a0c7596 279 bool initialized;
771fe6b9
JG		 280};
281
282struct radeon_fence {
283 struct radeon_device *rdev;
284 struct kref kref;
771fe6b9 285 /* protected by radeon_fence.lock */
bb635567 286 uint64_t seq;
7465280c 287 /* RB, DMA, etc. */
bb635567 288 unsigned ring;
771fe6b9
JG		 289};
290
30eb77f4
JG		 291int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
292int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 293void radeon_fence_driver_fini(struct radeon_device *rdev);
76903b96 294void radeon_fence_driver_force_completion(struct radeon_device *rdev);
876dc9f3 295int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 296void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 297bool radeon_fence_signaled(struct radeon_fence *fence);
298int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
8a47cc9e 299int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
5f8f635e 300int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
0085c950
JG		 301int radeon_fence_wait_any(struct radeon_device *rdev,
302 struct radeon_fence **fences,
303 bool intr);
771fe6b9
JG		 304struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
305void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 306unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 307bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
308void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
309static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
310 struct radeon_fence *b)
311{
312 if (!a) {
313 return b;
314 }
315
316 if (!b) {
317 return a;
318 }
319
320 BUG_ON(a->ring != b->ring);
321
322 if (a->seq > b->seq) {
323 return a;
324 } else {
325 return b;
326 }
327}
771fe6b9 328
ee60e29f
CK		 329static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
330 struct radeon_fence *b)
331{
332 if (!a) {
333 return false;
334 }
335
336 if (!b) {
337 return true;
338 }
339
340 BUG_ON(a->ring != b->ring);
341
342 return a->seq < b->seq;
343}
344
e024e110
DA		 345/*
346 * Tiling registers
347 */
348struct radeon_surface_reg {
4c788679 349 struct radeon_bo *bo;
e024e110
DA		 350};
351
352#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 353
354/*
4c788679 355 * TTM.
771fe6b9 356 */
4c788679
JG		 357struct radeon_mman {
358 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 359 struct drm_global_reference mem_global_ref;
4c788679 360 struct ttm_bo_device bdev;
0a0c7596
JG		 361 bool mem_global_referenced;
362 bool initialized;
4c788679
JG		 363};
364
721604a1
JG		 365/* bo virtual address in a specific vm */
366struct radeon_bo_va {
e971bd5e 367 /* protected by bo being reserved */
721604a1 368 struct list_head bo_list;
721604a1
JG		 369 uint64_t soffset;
370 uint64_t eoffset;
371 uint32_t flags;
372 bool valid;
e971bd5e
CK		 373 unsigned ref_count;
374
375 /* protected by vm mutex */
376 struct list_head vm_list;
377
378 /* constant after initialization */
379 struct radeon_vm *vm;
380 struct radeon_bo *bo;
721604a1
JG		 381};
382
4c788679
JG		 383struct radeon_bo {
384 /* Protected by gem.mutex */
385 struct list_head list;
386 /* Protected by tbo.reserved */
312ea8da
JG		 387 u32 placements[3];
388 struct ttm_placement placement;
4c788679
JG		 389 struct ttm_buffer_object tbo;
390 struct ttm_bo_kmap_obj kmap;
391 unsigned pin_count;
392 void *kptr;
393 u32 tiling_flags;
394 u32 pitch;
395 int surface_reg;
721604a1
JG		 396 /* list of all virtual address to which this bo
397 * is associated to
398 */
399 struct list_head va;
4c788679
JG		 400 /* Constant after initialization */
401 struct radeon_device *rdev;
441921d5 402 struct drm_gem_object gem_base;
63bc620b 403
409851f4
JG		 404 struct ttm_bo_kmap_obj dma_buf_vmap;
405 pid_t pid;
4c788679 406};
7e4d15d9 407#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 408
4c788679 409struct radeon_bo_list {
147666fb 410 struct ttm_validate_buffer tv;
4c788679 411 struct radeon_bo *bo;
771fe6b9 412 uint64_t gpu_offset;
4474f3a9
CK		 413 bool written;
414 unsigned domain;
415 unsigned alt_domain;
4c788679 416 u32 tiling_flags;
771fe6b9
JG		 417};
418
409851f4
JG		 419int radeon_gem_debugfs_init(struct radeon_device *rdev);
420
b15ba512
JG		 421/* sub-allocation manager, it has to be protected by another lock.
422 * By conception this is an helper for other part of the driver
423 * like the indirect buffer or semaphore, which both have their
424 * locking.
425 *
426 * Principe is simple, we keep a list of sub allocation in offset
427 * order (first entry has offset == 0, last entry has the highest
428 * offset).
429 *
430 * When allocating new object we first check if there is room at
431 * the end total_size - (last_object_offset + last_object_size) >=
432 * alloc_size. If so we allocate new object there.
433 *
434 * When there is not enough room at the end, we start waiting for
435 * each sub object until we reach object_offset+object_size >=
436 * alloc_size, this object then become the sub object we return.
437 *
438 * Alignment can't be bigger than page size.
439 *
440 * Hole are not considered for allocation to keep things simple.
441 * Assumption is that there won't be hole (all object on same
442 * alignment).
443 */
444struct radeon_sa_manager {
bfb38d35 445 wait_queue_head_t wq;
b15ba512 446 struct radeon_bo *bo;
c3b7fe8b
CK		 447 struct list_head *hole;
448 struct list_head flist[RADEON_NUM_RINGS];
449 struct list_head olist;
b15ba512
JG		 450 unsigned size;
451 uint64_t gpu_addr;
452 void *cpu_ptr;
453 uint32_t domain;
454};
455
456struct radeon_sa_bo;
457
458/* sub-allocation buffer */
459struct radeon_sa_bo {
c3b7fe8b
CK		 460 struct list_head olist;
461 struct list_head flist;
b15ba512 462 struct radeon_sa_manager *manager;
e6661a96
CK		 463 unsigned soffset;
464 unsigned eoffset;
557017a0 465 struct radeon_fence *fence;
b15ba512
JG		 466};
467
771fe6b9
JG		 468/*
469 * GEM objects.
470 */
471struct radeon_gem {
4c788679 472 struct mutex mutex;
771fe6b9
JG		 473 struct list_head objects;
474};
475
476int radeon_gem_init(struct radeon_device *rdev);
477void radeon_gem_fini(struct radeon_device *rdev);
478int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 479 int alignment, int initial_domain,
480 bool discardable, bool kernel,
481 struct drm_gem_object **obj);
771fe6b9 482
ff72145b
DA		 483int radeon_mode_dumb_create(struct drm_file *file_priv,
484 struct drm_device *dev,
485 struct drm_mode_create_dumb *args);
486int radeon_mode_dumb_mmap(struct drm_file *filp,
487 struct drm_device *dev,
488 uint32_t handle, uint64_t *offset_p);
489int radeon_mode_dumb_destroy(struct drm_file *file_priv,
490 struct drm_device *dev,
491 uint32_t handle);
771fe6b9 492
c1341e52
JG		 493/*
494 * Semaphores.
495 */
c1341e52
JG		 496/* everything here is constant */
497struct radeon_semaphore {
a8c05940
JG		 498 struct radeon_sa_bo *sa_bo;
499 signed waiters;
c1341e52 500 uint64_t gpu_addr;
c1341e52
JG		 501};
502
c1341e52
JG		 503int radeon_semaphore_create(struct radeon_device *rdev,
504 struct radeon_semaphore **semaphore);
505void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
506 struct radeon_semaphore *semaphore);
507void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
508 struct radeon_semaphore *semaphore);
8f676c4c
CK		 509int radeon_semaphore_sync_rings(struct radeon_device *rdev,
510 struct radeon_semaphore *semaphore,
220907d9 511 int signaler, int waiter);
c1341e52 512void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 513 struct radeon_semaphore **semaphore,
a8c05940 514 struct radeon_fence *fence);
c1341e52 515
771fe6b9
JG		 516/*
517 * GART structures, functions & helpers
518 */
519struct radeon_mc;
520
a77f1718 521#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 522#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 523#define RADEON_GPU_PAGE_SHIFT 12
721604a1 524#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 525
771fe6b9
JG		 526struct radeon_gart {
527 dma_addr_t table_addr;
c9a1be96
JG		 528 struct radeon_bo *robj;
529 void *ptr;
771fe6b9
JG		 530 unsigned num_gpu_pages;
531 unsigned num_cpu_pages;
532 unsigned table_size;
771fe6b9
JG		 533 struct page **pages;
534 dma_addr_t *pages_addr;
535 bool ready;
536};
537
538int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
539void radeon_gart_table_ram_free(struct radeon_device *rdev);
540int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
541void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 542int radeon_gart_table_vram_pin(struct radeon_device *rdev);
543void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 544int radeon_gart_init(struct radeon_device *rdev);
545void radeon_gart_fini(struct radeon_device *rdev);
546void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
547 int pages);
548int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516
KRW		 549 int pages, struct page **pagelist,
550 dma_addr_t *dma_addr);
c9a1be96 551void radeon_gart_restore(struct radeon_device *rdev);
771fe6b9
JG		 552
553
554/*
555 * GPU MC structures, functions & helpers
556 */
557struct radeon_mc {
558 resource_size_t aper_size;
559 resource_size_t aper_base;
560 resource_size_t agp_base;
7a50f01a
DA		 561 /* for some chips with <= 32MB we need to lie
562 * about vram size near mc fb location */
3ce0a23d 563 u64 mc_vram_size;
d594e46a 564 u64 visible_vram_size;
3ce0a23d
JG		 565 u64 gtt_size;
566 u64 gtt_start;
567 u64 gtt_end;
3ce0a23d
JG		 568 u64 vram_start;
569 u64 vram_end;
771fe6b9 570 unsigned vram_width;
3ce0a23d 571 u64 real_vram_size;
771fe6b9
JG		 572 int vram_mtrr;
573 bool vram_is_ddr;
d594e46a 574 bool igp_sideport_enabled;
8d369bb1 575 u64 gtt_base_align;
9ed8b1f9 576 u64 mc_mask;
771fe6b9
JG		 577};
578
06b6476d
AD		 579bool radeon_combios_sideport_present(struct radeon_device *rdev);
580bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 581
582/*
583 * GPU scratch registers structures, functions & helpers
584 */
585struct radeon_scratch {
586 unsigned num_reg;
724c80e1 587 uint32_t reg_base;
771fe6b9
JG		 588 bool free[32];
589 uint32_t reg[32];
590};
591
592int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
593void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
594
75efdee1
AD		 595/*
596 * GPU doorbell structures, functions & helpers
597 */
598struct radeon_doorbell {
599 u32 num_pages;
600 bool free[1024];
601 /* doorbell mmio */
602 resource_size_t base;
603 resource_size_t size;
604 void __iomem *ptr;
605};
606
607int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
608void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771fe6b9
JG		 609
610/*
611 * IRQS.
612 */
6f34be50
AD		 613
614struct radeon_unpin_work {
615 struct work_struct work;
616 struct radeon_device *rdev;
617 int crtc_id;
618 struct radeon_fence *fence;
619 struct drm_pending_vblank_event *event;
620 struct radeon_bo *old_rbo;
621 u64 new_crtc_base;
622};
623
624struct r500_irq_stat_regs {
625 u32 disp_int;
f122c610 626 u32 hdmi0_status;
6f34be50
AD		 627};
628
629struct r600_irq_stat_regs {
630 u32 disp_int;
631 u32 disp_int_cont;
632 u32 disp_int_cont2;
633 u32 d1grph_int;
634 u32 d2grph_int;
f122c610
AD		 635 u32 hdmi0_status;
636 u32 hdmi1_status;
6f34be50
AD		 637};
638
639struct evergreen_irq_stat_regs {
640 u32 disp_int;
641 u32 disp_int_cont;
642 u32 disp_int_cont2;
643 u32 disp_int_cont3;
644 u32 disp_int_cont4;
645 u32 disp_int_cont5;
646 u32 d1grph_int;
647 u32 d2grph_int;
648 u32 d3grph_int;
649 u32 d4grph_int;
650 u32 d5grph_int;
651 u32 d6grph_int;
f122c610
AD		 652 u32 afmt_status1;
653 u32 afmt_status2;
654 u32 afmt_status3;
655 u32 afmt_status4;
656 u32 afmt_status5;
657 u32 afmt_status6;
6f34be50
AD		 658};
659
a59781bb
AD		 660struct cik_irq_stat_regs {
661 u32 disp_int;
662 u32 disp_int_cont;
663 u32 disp_int_cont2;
664 u32 disp_int_cont3;
665 u32 disp_int_cont4;
666 u32 disp_int_cont5;
667 u32 disp_int_cont6;
668};
669
6f34be50
AD		 670union radeon_irq_stat_regs {
671 struct r500_irq_stat_regs r500;
672 struct r600_irq_stat_regs r600;
673 struct evergreen_irq_stat_regs evergreen;
a59781bb 674 struct cik_irq_stat_regs cik;
6f34be50
AD		 675};
676
54bd5206
IH		 677#define RADEON_MAX_HPD_PINS 6
678#define RADEON_MAX_CRTCS 6
f122c610 679#define RADEON_MAX_AFMT_BLOCKS 6
54bd5206 680
771fe6b9 681struct radeon_irq {
fb98257a
CK		 682 bool installed;
683 spinlock_t lock;
736fc37f 684 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 685 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 686 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 687 wait_queue_head_t vblank_queue;
688 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 689 bool afmt[RADEON_MAX_AFMT_BLOCKS];
690 union radeon_irq_stat_regs stat_regs;
4a6369e9 691 bool dpm_thermal;
771fe6b9
JG		 692};
693
694int radeon_irq_kms_init(struct radeon_device *rdev);
695void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b
AD		 696void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
697void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 698void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
699void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 700void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
701void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
702void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
703void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 704
705/*
e32eb50d 706 * CP & rings.
771fe6b9 707 */
7465280c 708
771fe6b9 709struct radeon_ib {
68470ae7
JG		 710 struct radeon_sa_bo *sa_bo;
711 uint32_t length_dw;
712 uint64_t gpu_addr;
713 uint32_t *ptr;
876dc9f3 714 int ring;
68470ae7 715 struct radeon_fence *fence;
4bf3dd92 716 struct radeon_vm *vm;
68470ae7 717 bool is_const_ib;
220907d9 718 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
68470ae7 719 struct radeon_semaphore *semaphore;
771fe6b9
JG		 720};
721
e32eb50d 722struct radeon_ring {
4c788679 723 struct radeon_bo *ring_obj;
771fe6b9
JG		 724 volatile uint32_t *ring;
725 unsigned rptr;
5596a9db
CK		 726 unsigned rptr_offs;
727 unsigned rptr_reg;
45df6803 728 unsigned rptr_save_reg;
89d35807
AD		 729 u64 next_rptr_gpu_addr;
730 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 731 unsigned wptr;
732 unsigned wptr_old;
5596a9db 733 unsigned wptr_reg;
771fe6b9
JG		 734 unsigned ring_size;
735 unsigned ring_free_dw;
736 int count_dw;
069211e5
CK		 737 unsigned long last_activity;
738 unsigned last_rptr;
771fe6b9
JG		 739 uint64_t gpu_addr;
740 uint32_t align_mask;
741 uint32_t ptr_mask;
771fe6b9 742 bool ready;
78c5560a
AD		 743 u32 ptr_reg_shift;
744 u32 ptr_reg_mask;
745 u32 nop;
8b25ed34 746 u32 idx;
5f0839c1
JG		 747 u64 last_semaphore_signal_addr;
748 u64 last_semaphore_wait_addr;
963e81f9
AD		 749 /* for CIK queues */
750 u32 me;
751 u32 pipe;
752 u32 queue;
753 struct radeon_bo *mqd_obj;
754 u32 doorbell_page_num;
755 u32 doorbell_offset;
756 unsigned wptr_offs;
757};
758
759struct radeon_mec {
760 struct radeon_bo *hpd_eop_obj;
761 u64 hpd_eop_gpu_addr;
762 u32 num_pipe;
763 u32 num_mec;
764 u32 num_queue;
771fe6b9
JG		 765};
766
721604a1
JG		 767/*
768 * VM
769 */
ee60e29f 770
fa87e62d 771/* maximum number of VMIDs */
ee60e29f
CK		 772#define RADEON_NUM_VM 16
773
fa87e62d
DC		 774/* defines number of bits in page table versus page directory,
775 * a page is 4KB so we have 12 bits offset, 9 bits in the page
776 * table and the remaining 19 bits are in the page directory */
777#define RADEON_VM_BLOCK_SIZE 9
778
779/* number of entries in page table */
780#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
781
721604a1
JG		 782struct radeon_vm {
783 struct list_head list;
784 struct list_head va;
ee60e29f 785 unsigned id;
90a51a32
CK		 786
787 /* contains the page directory */
788 struct radeon_sa_bo *page_directory;
789 uint64_t pd_gpu_addr;
790
791 /* array of page tables, one for each page directory entry */
792 struct radeon_sa_bo **page_tables;
793
721604a1
JG		 794 struct mutex mutex;
795 /* last fence for cs using this vm */
796 struct radeon_fence *fence;
9b40e5d8
CK		 797 /* last flush or NULL if we still need to flush */
798 struct radeon_fence *last_flush;
721604a1
JG		 799};
800
721604a1 801struct radeon_vm_manager {
36ff39c4 802 struct mutex lock;
721604a1 803 struct list_head lru_vm;
ee60e29f 804 struct radeon_fence *active[RADEON_NUM_VM];
721604a1
JG		 805 struct radeon_sa_manager sa_manager;
806 uint32_t max_pfn;
721604a1
JG		 807 /* number of VMIDs */
808 unsigned nvm;
809 /* vram base address for page table entry */
810 u64 vram_base_offset;
67e915e4
AD		 811 /* is vm enabled? */
812 bool enabled;
721604a1
JG		 813};
814
815/*
816 * file private structure
817 */
818struct radeon_fpriv {
819 struct radeon_vm vm;
820};
821
d8f60cfc
AD		 822/*
823 * R6xx+ IH ring
824 */
825struct r600_ih {
4c788679 826 struct radeon_bo *ring_obj;
d8f60cfc
AD		 827 volatile uint32_t *ring;
828 unsigned rptr;
d8f60cfc
AD		 829 unsigned ring_size;
830 uint64_t gpu_addr;
d8f60cfc 831 uint32_t ptr_mask;
c20dc369 832 atomic_t lock;
d8f60cfc
AD		 833 bool enabled;
834};
835
8eec9d6f
IH		 836struct r600_blit_cp_primitives {
837 void (*set_render_target)(struct radeon_device *rdev, int format,
838 int w, int h, u64 gpu_addr);
839 void (*cp_set_surface_sync)(struct radeon_device *rdev,
840 u32 sync_type, u32 size,
841 u64 mc_addr);
842 void (*set_shaders)(struct radeon_device *rdev);
843 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
844 void (*set_tex_resource)(struct radeon_device *rdev,
845 int format, int w, int h, int pitch,
9bb7703c 846 u64 gpu_addr, u32 size);
8eec9d6f
IH		 847 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
848 int x2, int y2);
849 void (*draw_auto)(struct radeon_device *rdev);
850 void (*set_default_state)(struct radeon_device *rdev);
851};
852
3ce0a23d 853struct r600_blit {
4c788679 854 struct radeon_bo *shader_obj;
8eec9d6f
IH		 855 struct r600_blit_cp_primitives primitives;
856 int max_dim;
857 int ring_size_common;
858 int ring_size_per_loop;
3ce0a23d
JG		 859 u64 shader_gpu_addr;
860 u32 vs_offset, ps_offset;
861 u32 state_offset;
862 u32 state_len;
3ce0a23d
JG		 863};
864
347e7592 865/*
2948f5e6 866 * RLC stuff
347e7592 867 */
2948f5e6
AD		 868#include "clearstate_defs.h"
869
870struct radeon_rlc {
347e7592
AD		 871 /* for power gating */
872 struct radeon_bo *save_restore_obj;
873 uint64_t save_restore_gpu_addr;
2948f5e6
AD		 874 volatile uint32_t *sr_ptr;
875 u32 *reg_list;
876 u32 reg_list_size;
347e7592
AD		 877 /* for clear state */
878 struct radeon_bo *clear_state_obj;
879 uint64_t clear_state_gpu_addr;
2948f5e6
AD		 880 volatile uint32_t *cs_ptr;
881 struct cs_section_def *cs_data;
347e7592
AD		 882};
883
69e130a6 884int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 885 struct radeon_ib *ib, struct radeon_vm *vm,
886 unsigned size);
f2e39221 887void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
43f1214a 888void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
4ef72566
CK		 889int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
890 struct radeon_ib *const_ib);
771fe6b9
JG		 891int radeon_ib_pool_init(struct radeon_device *rdev);
892void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 893int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 894/* Ring access between begin & end cannot sleep */
89d35807
AD		 895bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
896 struct radeon_ring *ring);
e32eb50d
CK		 897void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
898int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
899int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
900void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
901void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
d6999bc7 902void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 903void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
904int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
7b9ef16b 905void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
069211e5
CK		 906void radeon_ring_lockup_update(struct radeon_ring *ring);
907bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 908unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
909 uint32_t **data);
910int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
911 unsigned size, uint32_t *data);
e32eb50d 912int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
78c5560a
AD		 913 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
914 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
e32eb50d 915void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 916
917
4d75658b
AD		 918/* r600 async dma */
919void r600_dma_stop(struct radeon_device *rdev);
920int r600_dma_resume(struct radeon_device *rdev);
921void r600_dma_fini(struct radeon_device *rdev);
922
8c5fd7ef
AD		 923void cayman_dma_stop(struct radeon_device *rdev);
924int cayman_dma_resume(struct radeon_device *rdev);
925void cayman_dma_fini(struct radeon_device *rdev);
926
771fe6b9
JG		 927/*
928 * CS.
929 */
930struct radeon_cs_reloc {
931 struct drm_gem_object *gobj;
4c788679
JG		 932 struct radeon_bo *robj;
933 struct radeon_bo_list lobj;
771fe6b9
JG		 934 uint32_t handle;
935 uint32_t flags;
936};
937
938struct radeon_cs_chunk {
939 uint32_t chunk_id;
940 uint32_t length_dw;
721604a1
JG		 941 int kpage_idx[2];
942 uint32_t *kpage[2];
771fe6b9 943 uint32_t *kdata;
721604a1
JG		 944 void __user *user_ptr;
945 int last_copied_page;
946 int last_page_index;
771fe6b9
JG		 947};
948
949struct radeon_cs_parser {
c8c15ff1 950 struct device *dev;
771fe6b9
JG		 951 struct radeon_device *rdev;
952 struct drm_file *filp;
953 /* chunks */
954 unsigned nchunks;
955 struct radeon_cs_chunk *chunks;
956 uint64_t *chunks_array;
957 /* IB */
958 unsigned idx;
959 /* relocations */
960 unsigned nrelocs;
961 struct radeon_cs_reloc *relocs;
962 struct radeon_cs_reloc **relocs_ptr;
963 struct list_head validated;
cf4ccd01 964 unsigned dma_reloc_idx;
771fe6b9
JG		 965 /* indices of various chunks */
966 int chunk_ib_idx;
967 int chunk_relocs_idx;
721604a1 968 int chunk_flags_idx;
dfcf5f36 969 int chunk_const_ib_idx;
f2e39221
JG		 970 struct radeon_ib ib;
971 struct radeon_ib const_ib;
771fe6b9 972 void *track;
3ce0a23d 973 unsigned family;
e70f224c 974 int parser_error;
721604a1
JG		 975 u32 cs_flags;
976 u32 ring;
977 s32 priority;
771fe6b9
JG		 978};
979
513bcb46 980extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
ce580fab 981extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
513bcb46 982
771fe6b9
JG		 983struct radeon_cs_packet {
984 unsigned idx;
985 unsigned type;
986 unsigned reg;
987 unsigned opcode;
988 int count;
989 unsigned one_reg_wr;
990};
991
992typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
993 struct radeon_cs_packet *pkt,
994 unsigned idx, unsigned reg);
995typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
996 struct radeon_cs_packet *pkt);
997
998
999/*
1000 * AGP
1001 */
1002int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1003void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1004void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1005void radeon_agp_fini(struct radeon_device *rdev);
1006
1007
1008/*
1009 * Writeback
1010 */
1011struct radeon_wb {
4c788679 1012 struct radeon_bo *wb_obj;
771fe6b9
JG		 1013 volatile uint32_t *wb;
1014 uint64_t gpu_addr;
724c80e1 1015 bool enabled;
d0f8a854 1016 bool use_event;
771fe6b9
JG		 1017};
1018
724c80e1 1019#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1020#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1021#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1022#define RADEON_WB_CP1_RPTR_OFFSET 1280
1023#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1024#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1025#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1026#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
f2ba57b5 1027#define R600_WB_UVD_RPTR_OFFSET 2560
d0f8a854 1028#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1029#define CIK_WB_CP1_WPTR_OFFSET 3328
1030#define CIK_WB_CP2_WPTR_OFFSET 3584
724c80e1 1031
c93bb85b
JG		 1032/**
1033 * struct radeon_pm - power management datas
1034 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1035 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1036 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1037 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1038 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1039 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1040 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1041 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1042 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1043 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1044 * @needed_bandwidth: current bandwidth needs
1045 *
1046 * It keeps track of various data needed to take powermanagement decision.
25985edc 1047 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1048 * Equation between gpu/memory clock and available bandwidth is hw dependent
1049 * (type of memory, bus size, efficiency, ...)
1050 */
ce8f5370
AD		 1051
1052enum radeon_pm_method {
1053 PM_METHOD_PROFILE,
1054 PM_METHOD_DYNPM,
da321c8a 1055 PM_METHOD_DPM,
ce8f5370
AD		 1056};
1057
1058enum radeon_dynpm_state {
1059 DYNPM_STATE_DISABLED,
1060 DYNPM_STATE_MINIMUM,
1061 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1062 DYNPM_STATE_ACTIVE,
1063 DYNPM_STATE_SUSPENDED,
c913e23a 1064};
ce8f5370
AD		 1065enum radeon_dynpm_action {
1066 DYNPM_ACTION_NONE,
1067 DYNPM_ACTION_MINIMUM,
1068 DYNPM_ACTION_DOWNCLOCK,
1069 DYNPM_ACTION_UPCLOCK,
1070 DYNPM_ACTION_DEFAULT
c913e23a 1071};
56278a8e
AD		 1072
1073enum radeon_voltage_type {
1074 VOLTAGE_NONE = 0,
1075 VOLTAGE_GPIO,
1076 VOLTAGE_VDDC,
1077 VOLTAGE_SW
1078};
1079
0ec0e74f 1080enum radeon_pm_state_type {
da321c8a 1081 /* not used for dpm */
0ec0e74f
AD		 1082 POWER_STATE_TYPE_DEFAULT,
1083 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1084 /* user selectable states */
0ec0e74f
AD		 1085 POWER_STATE_TYPE_BATTERY,
1086 POWER_STATE_TYPE_BALANCED,
1087 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1088 /* internal states */
1089 POWER_STATE_TYPE_INTERNAL_UVD,
1090 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1091 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1092 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1093 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1094 POWER_STATE_TYPE_INTERNAL_BOOT,
1095 POWER_STATE_TYPE_INTERNAL_THERMAL,
1096 POWER_STATE_TYPE_INTERNAL_ACPI,
1097 POWER_STATE_TYPE_INTERNAL_ULV,
0ec0e74f
AD		 1098};
1099
ce8f5370
AD		 1100enum radeon_pm_profile_type {
1101 PM_PROFILE_DEFAULT,
1102 PM_PROFILE_AUTO,
1103 PM_PROFILE_LOW,
c9e75b21 1104 PM_PROFILE_MID,
ce8f5370
AD		 1105 PM_PROFILE_HIGH,
1106};
1107
1108#define PM_PROFILE_DEFAULT_IDX 0
1109#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1110#define PM_PROFILE_MID_SH_IDX 2
1111#define PM_PROFILE_HIGH_SH_IDX 3
1112#define PM_PROFILE_LOW_MH_IDX 4
1113#define PM_PROFILE_MID_MH_IDX 5
1114#define PM_PROFILE_HIGH_MH_IDX 6
1115#define PM_PROFILE_MAX 7
ce8f5370
AD		 1116
1117struct radeon_pm_profile {
1118 int dpms_off_ps_idx;
1119 int dpms_on_ps_idx;
1120 int dpms_off_cm_idx;
1121 int dpms_on_cm_idx;
516d0e46
AD		 1122};
1123
21a8122a
AD		 1124enum radeon_int_thermal_type {
1125 THERMAL_TYPE_NONE,
da321c8a
AD		 1126 THERMAL_TYPE_EXTERNAL,
1127 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1128 THERMAL_TYPE_RV6XX,
1129 THERMAL_TYPE_RV770,
da321c8a 1130 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1131 THERMAL_TYPE_EVERGREEN,
e33df25f 1132 THERMAL_TYPE_SUMO,
4fddba1f 1133 THERMAL_TYPE_NI,
14607d08 1134 THERMAL_TYPE_SI,
da321c8a 1135 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1136 THERMAL_TYPE_CI,
21a8122a
AD		 1137};
1138
56278a8e
AD		 1139struct radeon_voltage {
1140 enum radeon_voltage_type type;
1141 /* gpio voltage */
1142 struct radeon_gpio_rec gpio;
1143 u32 delay; /* delay in usec from voltage drop to sclk change */
1144 bool active_high; /* voltage drop is active when bit is high */
1145 /* VDDC voltage */
1146 u8 vddc_id; /* index into vddc voltage table */
1147 u8 vddci_id; /* index into vddci voltage table */
1148 bool vddci_enabled;
1149 /* r6xx+ sw */
2feea49a
AD		 1150 u16 voltage;
1151 /* evergreen+ vddci */
1152 u16 vddci;
56278a8e
AD		 1153};
1154
d7311171
AD		 1155/* clock mode flags */
1156#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1157
56278a8e
AD		 1158struct radeon_pm_clock_info {
1159 /* memory clock */
1160 u32 mclk;
1161 /* engine clock */
1162 u32 sclk;
1163 /* voltage info */
1164 struct radeon_voltage voltage;
d7311171 1165 /* standardized clock flags */
56278a8e
AD		 1166 u32 flags;
1167};
1168
a48b9b4e 1169/* state flags */
d7311171 1170#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1171
56278a8e 1172struct radeon_power_state {
0ec0e74f 1173 enum radeon_pm_state_type type;
8f3f1c9a 1174 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1175 /* number of valid clock modes in this power state */
1176 int num_clock_modes;
56278a8e 1177 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1178 /* standardized state flags */
1179 u32 flags;
79daedc9
AD		 1180 u32 misc; /* vbios specific flags */
1181 u32 misc2; /* vbios specific flags */
1182 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1183};
1184
27459324
RM		 1185/*
1186 * Some modes are overclocked by very low value, accept them
1187 */
1188#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1189
2e9d4c05
AD		 1190enum radeon_dpm_auto_throttle_src {
1191 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1192 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1193};
1194
1195enum radeon_dpm_event_src {
1196 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1197 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1198 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1199 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1200 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1201};
1202
da321c8a
AD		 1203struct radeon_ps {
1204 u32 caps; /* vbios flags */
1205 u32 class; /* vbios flags */
1206 u32 class2; /* vbios flags */
1207 /* UVD clocks */
1208 u32 vclk;
1209 u32 dclk;
1210 /* asic priv */
1211 void *ps_priv;
1212};
1213
1214struct radeon_dpm_thermal {
1215 /* thermal interrupt work */
1216 struct work_struct work;
1217 /* low temperature threshold */
1218 int min_temp;
1219 /* high temperature threshold */
1220 int max_temp;
1221 /* was interrupt low to high or high to low */
1222 bool high_to_low;
1223};
1224
d22b7e40
AD		 1225enum radeon_clk_action
1226{
1227 RADEON_SCLK_UP = 1,
1228 RADEON_SCLK_DOWN
1229};
1230
1231struct radeon_blacklist_clocks
1232{
1233 u32 sclk;
1234 u32 mclk;
1235 enum radeon_clk_action action;
1236};
1237
61b7d601
AD		 1238struct radeon_clock_and_voltage_limits {
1239 u32 sclk;
1240 u32 mclk;
1241 u32 vddc;
1242 u32 vddci;
1243};
1244
1245struct radeon_clock_array {
1246 u32 count;
1247 u32 *values;
1248};
1249
1250struct radeon_clock_voltage_dependency_entry {
1251 u32 clk;
1252 u16 v;
1253};
1254
1255struct radeon_clock_voltage_dependency_table {
1256 u32 count;
1257 struct radeon_clock_voltage_dependency_entry *entries;
1258};
1259
1260struct radeon_cac_leakage_entry {
1261 u16 vddc;
1262 u32 leakage;
1263};
1264
1265struct radeon_cac_leakage_table {
1266 u32 count;
1267 struct radeon_cac_leakage_entry *entries;
1268};
1269
1270struct radeon_dpm_dynamic_state {
1271 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1272 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1273 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1274 struct radeon_clock_array valid_sclk_values;
1275 struct radeon_clock_array valid_mclk_values;
1276 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1277 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1278 u32 mclk_sclk_ratio;
1279 u32 sclk_mclk_delta;
1280 u16 vddc_vddci_delta;
1281 u16 min_vddc_for_pcie_gen2;
1282 struct radeon_cac_leakage_table cac_leakage_table;
1283};
1284
1285struct radeon_dpm_fan {
1286 u16 t_min;
1287 u16 t_med;
1288 u16 t_high;
1289 u16 pwm_min;
1290 u16 pwm_med;
1291 u16 pwm_high;
1292 u8 t_hyst;
1293 u32 cycle_delay;
1294 u16 t_max;
1295 bool ucode_fan_control;
1296};
1297
da321c8a
AD		 1298struct radeon_dpm {
1299 struct radeon_ps *ps;
1300 /* number of valid power states */
1301 int num_ps;
1302 /* current power state that is active */
1303 struct radeon_ps *current_ps;
1304 /* requested power state */
1305 struct radeon_ps *requested_ps;
1306 /* boot up power state */
1307 struct radeon_ps *boot_ps;
1308 /* default uvd power state */
1309 struct radeon_ps *uvd_ps;
1310 enum radeon_pm_state_type state;
1311 enum radeon_pm_state_type user_state;
1312 u32 platform_caps;
1313 u32 voltage_response_time;
1314 u32 backbias_response_time;
1315 void *priv;
1316 u32 new_active_crtcs;
1317 int new_active_crtc_count;
1318 u32 current_active_crtcs;
1319 int current_active_crtc_count;
61b7d601
AD		 1320 struct radeon_dpm_dynamic_state dyn_state;
1321 struct radeon_dpm_fan fan;
1322 u32 tdp_limit;
1323 u32 near_tdp_limit;
1324 u32 sq_ramping_threshold;
1325 u32 cac_leakage;
1326 u16 tdp_od_limit;
1327 u32 tdp_adjustment;
1328 u16 load_line_slope;
1329 bool power_control;
5ca302f7 1330 bool ac_power;
da321c8a
AD		 1331 /* special states active */
1332 bool thermal_active;
8a227555 1333 bool uvd_active;
da321c8a
AD		 1334 /* thermal handling */
1335 struct radeon_dpm_thermal thermal;
1336};
1337
1338void radeon_dpm_enable_power_state(struct radeon_device *rdev,
1339 enum radeon_pm_state_type dpm_state);
1340
1341
c93bb85b 1342struct radeon_pm {
c913e23a 1343 struct mutex mutex;
db7fce39
CK		 1344 /* write locked while reprogramming mclk */
1345 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1346 u32 active_crtcs;
1347 int active_crtc_count;
c913e23a 1348 int req_vblank;
839461d3 1349 bool vblank_sync;
c93bb85b
JG		 1350 fixed20_12 max_bandwidth;
1351 fixed20_12 igp_sideport_mclk;
1352 fixed20_12 igp_system_mclk;
1353 fixed20_12 igp_ht_link_clk;
1354 fixed20_12 igp_ht_link_width;
1355 fixed20_12 k8_bandwidth;
1356 fixed20_12 sideport_bandwidth;
1357 fixed20_12 ht_bandwidth;
1358 fixed20_12 core_bandwidth;
1359 fixed20_12 sclk;
f47299c5 1360 fixed20_12 mclk;
c93bb85b 1361 fixed20_12 needed_bandwidth;
0975b162 1362 struct radeon_power_state *power_state;
56278a8e
AD		 1363 /* number of valid power states */
1364 int num_power_states;
a48b9b4e
AD		 1365 int current_power_state_index;
1366 int current_clock_mode_index;
1367 int requested_power_state_index;
1368 int requested_clock_mode_index;
1369 int default_power_state_index;
1370 u32 current_sclk;
1371 u32 current_mclk;
2feea49a
AD		 1372 u16 current_vddc;
1373 u16 current_vddci;
9ace9f7b
AD		 1374 u32 default_sclk;
1375 u32 default_mclk;
2feea49a
AD		 1376 u16 default_vddc;
1377 u16 default_vddci;
29fb52ca 1378 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1379 /* selected pm method */
1380 enum radeon_pm_method pm_method;
1381 /* dynpm power management */
1382 struct delayed_work dynpm_idle_work;
1383 enum radeon_dynpm_state dynpm_state;
1384 enum radeon_dynpm_action dynpm_planned_action;
1385 unsigned long dynpm_action_timeout;
1386 bool dynpm_can_upclock;
1387 bool dynpm_can_downclock;
1388 /* profile-based power management */
1389 enum radeon_pm_profile_type profile;
1390 int profile_index;
1391 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1392 /* internal thermal controller on rv6xx+ */
1393 enum radeon_int_thermal_type int_thermal_type;
1394 struct device *int_hwmon_dev;
da321c8a
AD		 1395 /* dpm */
1396 bool dpm_enabled;
1397 struct radeon_dpm dpm;
c93bb85b
JG		 1398};
1399
a4c9e2ee
AD		 1400int radeon_pm_get_type_index(struct radeon_device *rdev,
1401 enum radeon_pm_state_type ps_type,
1402 int instance);
f2ba57b5
CK		 1403/*
1404 * UVD
1405 */
1406#define RADEON_MAX_UVD_HANDLES 10
1407#define RADEON_UVD_STACK_SIZE (1024*1024)
1408#define RADEON_UVD_HEAP_SIZE (1024*1024)
1409
1410struct radeon_uvd {
1411 struct radeon_bo *vcpu_bo;
1412 void *cpu_addr;
1413 uint64_t gpu_addr;
1414 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1415 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
55b51c88 1416 struct delayed_work idle_work;
f2ba57b5
CK		 1417};
1418
1419int radeon_uvd_init(struct radeon_device *rdev);
1420void radeon_uvd_fini(struct radeon_device *rdev);
1421int radeon_uvd_suspend(struct radeon_device *rdev);
1422int radeon_uvd_resume(struct radeon_device *rdev);
1423int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1424 uint32_t handle, struct radeon_fence **fence);
1425int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1426 uint32_t handle, struct radeon_fence **fence);
1427void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1428void radeon_uvd_free_handles(struct radeon_device *rdev,
1429 struct drm_file *filp);
1430int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1431void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1432int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1433 unsigned vclk, unsigned dclk,
1434 unsigned vco_min, unsigned vco_max,
1435 unsigned fb_factor, unsigned fb_mask,
1436 unsigned pd_min, unsigned pd_max,
1437 unsigned pd_even,
1438 unsigned *optimal_fb_div,
1439 unsigned *optimal_vclk_div,
1440 unsigned *optimal_dclk_div);
1441int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1442 unsigned cg_upll_func_cntl);
771fe6b9 1443
a92553ab 1444struct r600_audio {
a92553ab
RM		 1445 int channels;
1446 int rate;
1447 int bits_per_sample;
1448 u8 status_bits;
1449 u8 category_code;
1450};
1451
771fe6b9
JG		 1452/*
1453 * Benchmarking
1454 */
638dd7db 1455void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1456
1457
ecc0b326
MD		 1458/*
1459 * Testing
1460 */
1461void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1462void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1463 struct radeon_ring *cpA,
1464 struct radeon_ring *cpB);
60a7e396 1465void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326
MD		 1466
1467
771fe6b9
JG		 1468/*
1469 * Debugfs
1470 */
4d8bf9ae
CK		 1471struct radeon_debugfs {
1472 struct drm_info_list *files;
1473 unsigned num_files;
1474};
1475
771fe6b9
JG		 1476int radeon_debugfs_add_files(struct radeon_device *rdev,
1477 struct drm_info_list *files,
1478 unsigned nfiles);
1479int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9
JG		 1480
1481
1482/*
1483 * ASIC specific functions.
1484 */
1485struct radeon_asic {
068a117c 1486 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1487 void (*fini)(struct radeon_device *rdev);
1488 int (*resume)(struct radeon_device *rdev);
1489 int (*suspend)(struct radeon_device *rdev);
28d52043 1490 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1491 int (*asic_reset)(struct radeon_device *rdev);
54e88e06
AD		 1492 /* ioctl hw specific callback. Some hw might want to perform special
1493 * operation on specific ioctl. For instance on wait idle some hw
1494 * might want to perform and HDP flush through MMIO as it seems that
1495 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1496 * through ring.
1497 */
1498 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1499 /* check if 3D engine is idle */
1500 bool (*gui_idle)(struct radeon_device *rdev);
1501 /* wait for mc_idle */
1502 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1503 /* get the reference clock */
1504 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1505 /* get the gpu clock counter */
1506 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1507 /* gart */
c5b3b850
AD		 1508 struct {
1509 void (*tlb_flush)(struct radeon_device *rdev);
1510 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1511 } gart;
05b07147
CK		 1512 struct {
1513 int (*init)(struct radeon_device *rdev);
1514 void (*fini)(struct radeon_device *rdev);
2a6f1abb
CK		 1515
1516 u32 pt_ring_index;
43f1214a
AD		 1517 void (*set_page)(struct radeon_device *rdev,
1518 struct radeon_ib *ib,
1519 uint64_t pe,
dce34bfd
CK		 1520 uint64_t addr, unsigned count,
1521 uint32_t incr, uint32_t flags);
05b07147 1522 } vm;
54e88e06 1523 /* ring specific callbacks */
4c87bc26
CK		 1524 struct {
1525 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
721604a1 1526 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
4c87bc26 1527 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
e32eb50d 1528 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
4c87bc26 1529 struct radeon_semaphore *semaphore, bool emit_wait);
eb0c19c5 1530 int (*cs_parse)(struct radeon_cs_parser *p);
f712812e
AD		 1531 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1532 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1533 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
312c4a8c 1534 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
498522b4 1535 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
f93bdefe
AD		 1536
1537 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1538 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1539 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
4c87bc26 1540 } ring[RADEON_NUM_RINGS];
54e88e06 1541 /* irqs */
b35ea4ab
AD		 1542 struct {
1543 int (*set)(struct radeon_device *rdev);
1544 int (*process)(struct radeon_device *rdev);
1545 } irq;
54e88e06 1546 /* displays */
c79a49ca
AD		 1547 struct {
1548 /* display watermarks */
1549 void (*bandwidth_update)(struct radeon_device *rdev);
1550 /* get frame count */
1551 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1552 /* wait for vblank */
1553 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1554 /* set backlight level */
1555 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1556 /* get backlight level */
1557 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1558 /* audio callbacks */
1559 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1560 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1561 } display;
54e88e06 1562 /* copy functions for bo handling */
27cd7769
AD		 1563 struct {
1564 int (*blit)(struct radeon_device *rdev,
1565 uint64_t src_offset,
1566 uint64_t dst_offset,
1567 unsigned num_gpu_pages,
876dc9f3 1568 struct radeon_fence **fence);
27cd7769
AD		 1569 u32 blit_ring_index;
1570 int (*dma)(struct radeon_device *rdev,
1571 uint64_t src_offset,
1572 uint64_t dst_offset,
1573 unsigned num_gpu_pages,
876dc9f3 1574 struct radeon_fence **fence);
27cd7769
AD		 1575 u32 dma_ring_index;
1576 /* method used for bo copy */
1577 int (*copy)(struct radeon_device *rdev,
1578 uint64_t src_offset,
1579 uint64_t dst_offset,
1580 unsigned num_gpu_pages,
876dc9f3 1581 struct radeon_fence **fence);
27cd7769
AD		 1582 /* ring used for bo copies */
1583 u32 copy_ring_index;
1584 } copy;
54e88e06 1585 /* surfaces */
9e6f3d02
AD		 1586 struct {
1587 int (*set_reg)(struct radeon_device *rdev, int reg,
1588 uint32_t tiling_flags, uint32_t pitch,
1589 uint32_t offset, uint32_t obj_size);
1590 void (*clear_reg)(struct radeon_device *rdev, int reg);
1591 } surface;
54e88e06 1592 /* hotplug detect */
901ea57d
AD		 1593 struct {
1594 void (*init)(struct radeon_device *rdev);
1595 void (*fini)(struct radeon_device *rdev);
1596 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1597 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1598 } hpd;
da321c8a 1599 /* static power management */
a02fa397
AD		 1600 struct {
1601 void (*misc)(struct radeon_device *rdev);
1602 void (*prepare)(struct radeon_device *rdev);
1603 void (*finish)(struct radeon_device *rdev);
1604 void (*init_profile)(struct radeon_device *rdev);
1605 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1606 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1607 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1608 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1609 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1610 int (*get_pcie_lanes)(struct radeon_device *rdev);
1611 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1612 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1613 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
6bd1c385 1614 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1615 } pm;
da321c8a
AD		 1616 /* dynamic power management */
1617 struct {
1618 int (*init)(struct radeon_device *rdev);
1619 void (*setup_asic)(struct radeon_device *rdev);
1620 int (*enable)(struct radeon_device *rdev);
1621 void (*disable)(struct radeon_device *rdev);
84dd1928 1622 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1623 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1624 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1625 void (*display_configuration_changed)(struct radeon_device *rdev);
1626 void (*fini)(struct radeon_device *rdev);
1627 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1628 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1629 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1630 } dpm;
6f34be50 1631 /* pageflipping */
0f9e006c
AD		 1632 struct {
1633 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1634 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1635 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1636 } pflip;
771fe6b9
JG		 1637};
1638
21f9a437
JG		 1639/*
1640 * Asic structures
1641 */
551ebd83 1642struct r100_asic {
225758d8
JG		 1643 const unsigned *reg_safe_bm;
1644 unsigned reg_safe_bm_size;
1645 u32 hdp_cntl;
551ebd83
DA		 1646};
1647
21f9a437 1648struct r300_asic {
225758d8
JG		 1649 const unsigned *reg_safe_bm;
1650 unsigned reg_safe_bm_size;
1651 u32 resync_scratch;
1652 u32 hdp_cntl;
21f9a437
JG		 1653};
1654
1655struct r600_asic {
225758d8
JG		 1656 unsigned max_pipes;
1657 unsigned max_tile_pipes;
1658 unsigned max_simds;
1659 unsigned max_backends;
1660 unsigned max_gprs;
1661 unsigned max_threads;
1662 unsigned max_stack_entries;
1663 unsigned max_hw_contexts;
1664 unsigned max_gs_threads;
1665 unsigned sx_max_export_size;
1666 unsigned sx_max_export_pos_size;
1667 unsigned sx_max_export_smx_size;
1668 unsigned sq_num_cf_insts;
1669 unsigned tiling_nbanks;
1670 unsigned tiling_npipes;
1671 unsigned tiling_group_size;
e7aeeba6 1672 unsigned tile_config;
e55b9422 1673 unsigned backend_map;
21f9a437
JG		 1674};
1675
1676struct rv770_asic {
225758d8
JG		 1677 unsigned max_pipes;
1678 unsigned max_tile_pipes;
1679 unsigned max_simds;
1680 unsigned max_backends;
1681 unsigned max_gprs;
1682 unsigned max_threads;
1683 unsigned max_stack_entries;
1684 unsigned max_hw_contexts;
1685 unsigned max_gs_threads;
1686 unsigned sx_max_export_size;
1687 unsigned sx_max_export_pos_size;
1688 unsigned sx_max_export_smx_size;
1689 unsigned sq_num_cf_insts;
1690 unsigned sx_num_of_sets;
1691 unsigned sc_prim_fifo_size;
1692 unsigned sc_hiz_tile_fifo_size;
1693 unsigned sc_earlyz_tile_fifo_fize;
1694 unsigned tiling_nbanks;
1695 unsigned tiling_npipes;
1696 unsigned tiling_group_size;
e7aeeba6 1697 unsigned tile_config;
e55b9422 1698 unsigned backend_map;
21f9a437
JG		 1699};
1700
32fcdbf4
AD		 1701struct evergreen_asic {
1702 unsigned num_ses;
1703 unsigned max_pipes;
1704 unsigned max_tile_pipes;
1705 unsigned max_simds;
1706 unsigned max_backends;
1707 unsigned max_gprs;
1708 unsigned max_threads;
1709 unsigned max_stack_entries;
1710 unsigned max_hw_contexts;
1711 unsigned max_gs_threads;
1712 unsigned sx_max_export_size;
1713 unsigned sx_max_export_pos_size;
1714 unsigned sx_max_export_smx_size;
1715 unsigned sq_num_cf_insts;
1716 unsigned sx_num_of_sets;
1717 unsigned sc_prim_fifo_size;
1718 unsigned sc_hiz_tile_fifo_size;
1719 unsigned sc_earlyz_tile_fifo_size;
1720 unsigned tiling_nbanks;
1721 unsigned tiling_npipes;
1722 unsigned tiling_group_size;
e7aeeba6 1723 unsigned tile_config;
e55b9422 1724 unsigned backend_map;
32fcdbf4
AD		 1725};
1726
fecf1d07
AD		 1727struct cayman_asic {
1728 unsigned max_shader_engines;
1729 unsigned max_pipes_per_simd;
1730 unsigned max_tile_pipes;
1731 unsigned max_simds_per_se;
1732 unsigned max_backends_per_se;
1733 unsigned max_texture_channel_caches;
1734 unsigned max_gprs;
1735 unsigned max_threads;
1736 unsigned max_gs_threads;
1737 unsigned max_stack_entries;
1738 unsigned sx_num_of_sets;
1739 unsigned sx_max_export_size;
1740 unsigned sx_max_export_pos_size;
1741 unsigned sx_max_export_smx_size;
1742 unsigned max_hw_contexts;
1743 unsigned sq_num_cf_insts;
1744 unsigned sc_prim_fifo_size;
1745 unsigned sc_hiz_tile_fifo_size;
1746 unsigned sc_earlyz_tile_fifo_size;
1747
1748 unsigned num_shader_engines;
1749 unsigned num_shader_pipes_per_simd;
1750 unsigned num_tile_pipes;
1751 unsigned num_simds_per_se;
1752 unsigned num_backends_per_se;
1753 unsigned backend_disable_mask_per_asic;
1754 unsigned backend_map;
1755 unsigned num_texture_channel_caches;
1756 unsigned mem_max_burst_length_bytes;
1757 unsigned mem_row_size_in_kb;
1758 unsigned shader_engine_tile_size;
1759 unsigned num_gpus;
1760 unsigned multi_gpu_tile_size;
1761
1762 unsigned tile_config;
fecf1d07
AD		 1763};
1764
0a96d72b
AD		 1765struct si_asic {
1766 unsigned max_shader_engines;
0a96d72b 1767 unsigned max_tile_pipes;
1a8ca750
AD		 1768 unsigned max_cu_per_sh;
1769 unsigned max_sh_per_se;
0a96d72b
AD		 1770 unsigned max_backends_per_se;
1771 unsigned max_texture_channel_caches;
1772 unsigned max_gprs;
1773 unsigned max_gs_threads;
1774 unsigned max_hw_contexts;
1775 unsigned sc_prim_fifo_size_frontend;
1776 unsigned sc_prim_fifo_size_backend;
1777 unsigned sc_hiz_tile_fifo_size;
1778 unsigned sc_earlyz_tile_fifo_size;
1779
0a96d72b
AD		 1780 unsigned num_tile_pipes;
1781 unsigned num_backends_per_se;
1782 unsigned backend_disable_mask_per_asic;
1783 unsigned backend_map;
1784 unsigned num_texture_channel_caches;
1785 unsigned mem_max_burst_length_bytes;
1786 unsigned mem_row_size_in_kb;
1787 unsigned shader_engine_tile_size;
1788 unsigned num_gpus;
1789 unsigned multi_gpu_tile_size;
1790
1791 unsigned tile_config;
64d7b8be 1792 uint32_t tile_mode_array[32];
0a96d72b
AD		 1793};
1794
8cc1a532
AD		 1795struct cik_asic {
1796 unsigned max_shader_engines;
1797 unsigned max_tile_pipes;
1798 unsigned max_cu_per_sh;
1799 unsigned max_sh_per_se;
1800 unsigned max_backends_per_se;
1801 unsigned max_texture_channel_caches;
1802 unsigned max_gprs;
1803 unsigned max_gs_threads;
1804 unsigned max_hw_contexts;
1805 unsigned sc_prim_fifo_size_frontend;
1806 unsigned sc_prim_fifo_size_backend;
1807 unsigned sc_hiz_tile_fifo_size;
1808 unsigned sc_earlyz_tile_fifo_size;
1809
1810 unsigned num_tile_pipes;
1811 unsigned num_backends_per_se;
1812 unsigned backend_disable_mask_per_asic;
1813 unsigned backend_map;
1814 unsigned num_texture_channel_caches;
1815 unsigned mem_max_burst_length_bytes;
1816 unsigned mem_row_size_in_kb;
1817 unsigned shader_engine_tile_size;
1818 unsigned num_gpus;
1819 unsigned multi_gpu_tile_size;
1820
1821 unsigned tile_config;
39aee490 1822 uint32_t tile_mode_array[32];
8cc1a532
AD		 1823};
1824
068a117c
JG		 1825union radeon_asic_config {
1826 struct r300_asic r300;
551ebd83 1827 struct r100_asic r100;
3ce0a23d
JG		 1828 struct r600_asic r600;
1829 struct rv770_asic rv770;
32fcdbf4 1830 struct evergreen_asic evergreen;
fecf1d07 1831 struct cayman_asic cayman;
0a96d72b 1832 struct si_asic si;
8cc1a532 1833 struct cik_asic cik;
068a117c
JG		 1834};
1835
0a10c851
DV		 1836/*
1837 * asic initizalization from radeon_asic.c
1838 */
1839void radeon_agp_disable(struct radeon_device *rdev);
1840int radeon_asic_init(struct radeon_device *rdev);
1841
771fe6b9
JG		 1842
1843/*
1844 * IOCTL.
1845 */
1846int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1847 struct drm_file *filp);
1848int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1849 struct drm_file *filp);
1850int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1851 struct drm_file *file_priv);
1852int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1853 struct drm_file *file_priv);
1854int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1855 struct drm_file *file_priv);
1856int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1857 struct drm_file *file_priv);
1858int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1859 struct drm_file *filp);
1860int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1861 struct drm_file *filp);
1862int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1863 struct drm_file *filp);
1864int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1865 struct drm_file *filp);
721604a1
JG		 1866int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1867 struct drm_file *filp);
771fe6b9 1868int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 1869int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1870 struct drm_file *filp);
1871int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1872 struct drm_file *filp);
771fe6b9 1873
16cdf04d
AD		 1874/* VRAM scratch page for HDP bug, default vram page */
1875struct r600_vram_scratch {
87cbf8f2
AD		 1876 struct radeon_bo *robj;
1877 volatile uint32_t *ptr;
16cdf04d 1878 u64 gpu_addr;
87cbf8f2 1879};
771fe6b9 1880
fd64ca8a
LT		 1881/*
1882 * ACPI
1883 */
1884struct radeon_atif_notification_cfg {
1885 bool enabled;
1886 int command_code;
1887};
1888
1889struct radeon_atif_notifications {
1890 bool display_switch;
1891 bool expansion_mode_change;
1892 bool thermal_state;
1893 bool forced_power_state;
1894 bool system_power_state;
1895 bool display_conf_change;
1896 bool px_gfx_switch;
1897 bool brightness_change;
1898 bool dgpu_display_event;
1899};
1900
1901struct radeon_atif_functions {
1902 bool system_params;
1903 bool sbios_requests;
1904 bool select_active_disp;
1905 bool lid_state;
1906 bool get_tv_standard;
1907 bool set_tv_standard;
1908 bool get_panel_expansion_mode;
1909 bool set_panel_expansion_mode;
1910 bool temperature_change;
1911 bool graphics_device_types;
1912};
1913
1914struct radeon_atif {
1915 struct radeon_atif_notifications notifications;
1916 struct radeon_atif_functions functions;
1917 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 1918 struct radeon_encoder *encoder_for_bl;
fd64ca8a 1919};
7a1619b9 1920
e3a15920
AD		 1921struct radeon_atcs_functions {
1922 bool get_ext_state;
1923 bool pcie_perf_req;
1924 bool pcie_dev_rdy;
1925 bool pcie_bus_width;
1926};
1927
1928struct radeon_atcs {
1929 struct radeon_atcs_functions functions;
1930};
1931
771fe6b9
JG		 1932/*
1933 * Core structure, functions and helpers.
1934 */
1935typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1936typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1937
1938struct radeon_device {
9f022ddf 1939 struct device *dev;
771fe6b9
JG		 1940 struct drm_device *ddev;
1941 struct pci_dev *pdev;
dee53e7f 1942 struct rw_semaphore exclusive_lock;
771fe6b9 1943 /* ASIC */
068a117c 1944 union radeon_asic_config config;
771fe6b9
JG		 1945 enum radeon_family family;
1946 unsigned long flags;
1947 int usec_timeout;
1948 enum radeon_pll_errata pll_errata;
1949 int num_gb_pipes;
f779b3e5 1950 int num_z_pipes;
771fe6b9
JG		 1951 int disp_priority;
1952 /* BIOS */
1953 uint8_t *bios;
1954 bool is_atom_bios;
1955 uint16_t bios_header_start;
4c788679 1956 struct radeon_bo *stollen_vga_memory;
771fe6b9 1957 /* Register mmio */
4c9bc75c
DA		 1958 resource_size_t rmmio_base;
1959 resource_size_t rmmio_size;
2c385151
DV		 1960 /* protects concurrent MM_INDEX/DATA based register access */
1961 spinlock_t mmio_idx_lock;
a0533fbf 1962 void __iomem *rmmio;
771fe6b9
JG		 1963 radeon_rreg_t mc_rreg;
1964 radeon_wreg_t mc_wreg;
1965 radeon_rreg_t pll_rreg;
1966 radeon_wreg_t pll_wreg;
de1b2898 1967 uint32_t pcie_reg_mask;
771fe6b9
JG		 1968 radeon_rreg_t pciep_rreg;
1969 radeon_wreg_t pciep_wreg;
351a52a2
AD		 1970 /* io port */
1971 void __iomem *rio_mem;
1972 resource_size_t rio_mem_size;
771fe6b9
JG		 1973 struct radeon_clock clock;
1974 struct radeon_mc mc;
1975 struct radeon_gart gart;
1976 struct radeon_mode_info mode_info;
1977 struct radeon_scratch scratch;
75efdee1 1978 struct radeon_doorbell doorbell;
771fe6b9 1979 struct radeon_mman mman;
7465280c 1980 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 1981 wait_queue_head_t fence_queue;
d6999bc7 1982 struct mutex ring_lock;
e32eb50d 1983 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 1984 bool ib_pool_ready;
1985 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 1986 struct radeon_irq irq;
1987 struct radeon_asic *asic;
1988 struct radeon_gem gem;
c93bb85b 1989 struct radeon_pm pm;
f2ba57b5 1990 struct radeon_uvd uvd;
f657c2a7 1991 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 1992 struct radeon_wb wb;
3ce0a23d 1993 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 1994 bool shutdown;
1995 bool suspend;
ad49f501 1996 bool need_dma32;
733289c2 1997 bool accel_working;
a0a53aa8 1998 bool fastfb_working; /* IGP feature*/
e024e110 1999 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2000 const struct firmware *me_fw; /* all family ME firmware */
2001 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2002 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2003 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2004 const struct firmware *ce_fw; /* SI CE firmware */
f2ba57b5 2005 const struct firmware *uvd_fw; /* UVD firmware */
02c81327 2006 const struct firmware *mec_fw; /* CIK MEC firmware */
21a93e13 2007 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2008 const struct firmware *smc_fw; /* SMC firmware */
3ce0a23d 2009 struct r600_blit r600_blit;
16cdf04d 2010 struct r600_vram_scratch vram_scratch;
3e5cb98d 2011 int msi_enabled; /* msi enabled */
d8f60cfc 2012 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2013 struct radeon_rlc rlc;
963e81f9 2014 struct radeon_mec mec;
d4877cf2 2015 struct work_struct hotplug_work;
f122c610 2016 struct work_struct audio_work;
8f61b34c 2017 struct work_struct reset_work;
18917b60 2018 int num_crtc; /* number of crtcs */
40bacf16 2019 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
3299de95 2020 bool audio_enabled;
948bee3f 2021 bool has_uvd;
3299de95 2022 struct r600_audio audio_status; /* audio stuff */
ce8f5370 2023 struct notifier_block acpi_nb;
9eba4a93 2024 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2025 struct drm_file *hyperz_filp;
9eba4a93 2026 struct drm_file *cmask_filp;
f376b94f
AD		 2027 /* i2c buses */
2028 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2029 /* debugfs */
2030 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2031 unsigned debugfs_count;
721604a1
JG		 2032 /* virtual memory */
2033 struct radeon_vm_manager vm_manager;
6759a0a7 2034 struct mutex gpu_clock_mutex;
fd64ca8a
LT		 2035 /* ACPI interface */
2036 struct radeon_atif atif;
e3a15920 2037 struct radeon_atcs atcs;
771fe6b9
JG		 2038};
2039
2040int radeon_device_init(struct radeon_device *rdev,
2041 struct drm_device *ddev,
2042 struct pci_dev *pdev,
2043 uint32_t flags);
2044void radeon_device_fini(struct radeon_device *rdev);
2045int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2046
2ef9bdfe
DV		 2047uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2048 bool always_indirect);
2049void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2050 bool always_indirect);
6fcbef7a
AK		 2051u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2052void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2053
75efdee1
AD		 2054u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset);
2055void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
2056
4c788679
JG		 2057/*
2058 * Cast helper
2059 */
2060#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 2061
2062/*
2063 * Registers read & write functions.
2064 */
a0533fbf
BH		 2065#define RREG8(reg) readb((rdev->rmmio) + (reg))
2066#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2067#define RREG16(reg) readw((rdev->rmmio) + (reg))
2068#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2069#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2070#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2071#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2072#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2073#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2074#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2075#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2076#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2077#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2078#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2079#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2080#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2081#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2082#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2083#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2084#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2085#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2086#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2087#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2088#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2089#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
771fe6b9
JG		 2090#define WREG32_P(reg, val, mask) \
2091 do { \
2092 uint32_t tmp_ = RREG32(reg); \
2093 tmp_ &= (mask); \
2094 tmp_ |= ((val) & ~(mask)); \
2095 WREG32(reg, tmp_); \
2096 } while (0)
d5169fc4
RM		 2097#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2098#define WREG32_OR(reg, or) WREG32_P(reg, or, ~or)
771fe6b9
JG		 2099#define WREG32_PLL_P(reg, val, mask) \
2100 do { \
2101 uint32_t tmp_ = RREG32_PLL(reg); \
2102 tmp_ &= (mask); \
2103 tmp_ |= ((val) & ~(mask)); \
2104 WREG32_PLL(reg, tmp_); \
2105 } while (0)
2ef9bdfe 2106#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2107#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2108#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2109
75efdee1
AD		 2110#define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset))
2111#define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v))
2112
de1b2898
DA		 2113/*
2114 * Indirect registers accessor
2115 */
2116static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2117{
2118 uint32_t r;
2119
2120 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2121 r = RREG32(RADEON_PCIE_DATA);
2122 return r;
2123}
2124
2125static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2126{
2127 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2128 WREG32(RADEON_PCIE_DATA, (v));
2129}
2130
1d5d0c34
AD		 2131static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2132{
2133 u32 r;
2134
2135 WREG32(TN_SMC_IND_INDEX_0, (reg));
2136 r = RREG32(TN_SMC_IND_DATA_0);
2137 return r;
2138}
2139
2140static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2141{
2142 WREG32(TN_SMC_IND_INDEX_0, (reg));
2143 WREG32(TN_SMC_IND_DATA_0, (v));
2144}
2145
ff82bbc4
AD		 2146static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2147{
2148 u32 r;
2149
2150 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2151 r = RREG32(R600_RCU_DATA);
2152 return r;
2153}
2154
2155static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2156{
2157 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2158 WREG32(R600_RCU_DATA, (v));
2159}
2160
46f9564a
AD		 2161static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2162{
2163 u32 r;
2164
2165 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2166 r = RREG32(EVERGREEN_CG_IND_DATA);
2167 return r;
2168}
2169
2170static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2171{
2172 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2173 WREG32(EVERGREEN_CG_IND_DATA, (v));
2174}
2175
771fe6b9
JG		 2176void r100_pll_errata_after_index(struct radeon_device *rdev);
2177
2178
2179/*
2180 * ASICs helpers.
2181 */
b995e433
DA		 2182#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2183 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2184#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2185 (rdev->family == CHIP_RV200) || \
2186 (rdev->family == CHIP_RS100) || \
2187 (rdev->family == CHIP_RS200) || \
2188 (rdev->family == CHIP_RV250) || \
2189 (rdev->family == CHIP_RV280) || \
2190 (rdev->family == CHIP_RS300))
2191#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2192 (rdev->family == CHIP_RV350) || \
2193 (rdev->family == CHIP_R350) || \
2194 (rdev->family == CHIP_RV380) || \
2195 (rdev->family == CHIP_R420) || \
2196 (rdev->family == CHIP_R423) || \
2197 (rdev->family == CHIP_RV410) || \
2198 (rdev->family == CHIP_RS400) || \
2199 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2200#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2201 (rdev->ddev->pdev->device == 0x9443) || \
2202 (rdev->ddev->pdev->device == 0x944B) || \
2203 (rdev->ddev->pdev->device == 0x9506) || \
2204 (rdev->ddev->pdev->device == 0x9509) || \
2205 (rdev->ddev->pdev->device == 0x950F) || \
2206 (rdev->ddev->pdev->device == 0x689C) || \
2207 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2208#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2209#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2210 (rdev->family == CHIP_RS690) || \
2211 (rdev->family == CHIP_RS740) || \
2212 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2213#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2214#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2215#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2216#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2217 (rdev->flags & RADEON_IS_IGP))
1fe18305 2218#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2219#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2220#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2221 (rdev->flags & RADEON_IS_IGP))
624d3524 2222#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2223#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2224#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
771fe6b9 2225
dc50ba7f
AD		 2226#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2227 (rdev->ddev->pdev->device == 0x6850) || \
2228 (rdev->ddev->pdev->device == 0x6858) || \
2229 (rdev->ddev->pdev->device == 0x6859) || \
2230 (rdev->ddev->pdev->device == 0x6840) || \
2231 (rdev->ddev->pdev->device == 0x6841) || \
2232 (rdev->ddev->pdev->device == 0x6842) || \
2233 (rdev->ddev->pdev->device == 0x6843))
2234
771fe6b9
JG		 2235/*
2236 * BIOS helpers.
2237 */
2238#define RBIOS8(i) (rdev->bios[i])
2239#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2240#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2241
2242int radeon_combios_init(struct radeon_device *rdev);
2243void radeon_combios_fini(struct radeon_device *rdev);
2244int radeon_atombios_init(struct radeon_device *rdev);
2245void radeon_atombios_fini(struct radeon_device *rdev);
2246
2247
2248/*
2249 * RING helpers.
2250 */
ce580fab 2251#if DRM_DEBUG_CODE == 0
e32eb50d 2252static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2253{
e32eb50d
CK		 2254 ring->ring[ring->wptr++] = v;
2255 ring->wptr &= ring->ptr_mask;
2256 ring->count_dw--;
2257 ring->ring_free_dw--;
771fe6b9 2258}
ce580fab
AK		 2259#else
2260/* With debugging this is just too big to inline */
e32eb50d 2261void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
ce580fab 2262#endif
771fe6b9
JG		 2263
2264/*
2265 * ASICs macro.
2266 */
068a117c 2267#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2268#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2269#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2270#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
eb0c19c5 2271#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
28d52043 2272#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2273#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850
AD		 2274#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2275#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
05b07147
CK		 2276#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2277#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
43f1214a 2278#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
f712812e
AD		 2279#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
2280#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
2281#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
4c87bc26 2282#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
721604a1 2283#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
312c4a8c 2284#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
498522b4 2285#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
f93bdefe
AD		 2286#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_rptr((rdev), (r))
2287#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_wptr((rdev), (r))
2288#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].set_wptr((rdev), (r))
b35ea4ab
AD		 2289#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2290#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2291#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2292#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2293#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2294#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2295#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
4c87bc26
CK		 2296#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
2297#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
27cd7769
AD		 2298#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2299#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2300#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2301#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2302#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2303#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2304#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2305#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2306#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2307#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2308#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2309#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2310#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2311#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
6bd1c385 2312#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2313#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2314#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2315#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2316#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2317#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2318#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2319#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2320#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2321#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2322#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2323#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2324#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2325#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8
AD		 2326#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2327#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2328#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2329#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2330#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2331#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2332#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2333#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2334#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2335#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2336#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2337#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2338#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2339#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2340#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2341#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2342#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2343#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2344#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
771fe6b9 2345
6cf8a3f5 2346/* Common functions */
700a0cc0 2347/* AGP */
90aca4d2 2348extern int radeon_gpu_reset(struct radeon_device *rdev);
410a3418 2349extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2350extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2351extern int radeon_modeset_init(struct radeon_device *rdev);
2352extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2353extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2354extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2355extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2356extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2357extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2358extern void radeon_wb_fini(struct radeon_device *rdev);
2359extern int radeon_wb_init(struct radeon_device *rdev);
2360extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2361extern void radeon_surface_init(struct radeon_device *rdev);
2362extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2363extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2364extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2365extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2366extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 2367extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2368extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
6a9ee8af
DA		 2369extern int radeon_resume_kms(struct drm_device *dev);
2370extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
53595338 2371extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2372extern void radeon_program_register_sequence(struct radeon_device *rdev,
2373 const u32 *registers,
2374 const u32 array_size);
6cf8a3f5 2375
721604a1
JG		 2376/*
2377 * vm
2378 */
2379int radeon_vm_manager_init(struct radeon_device *rdev);
2380void radeon_vm_manager_fini(struct radeon_device *rdev);
d72d43cf 2381void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2382void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
ddf03f5c 2383int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
13e55c38 2384void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
ee60e29f
CK		 2385struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2386 struct radeon_vm *vm, int ring);
2387void radeon_vm_fence(struct radeon_device *rdev,
2388 struct radeon_vm *vm,
2389 struct radeon_fence *fence);
dce34bfd 2390uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
721604a1
JG		 2391int radeon_vm_bo_update_pte(struct radeon_device *rdev,
2392 struct radeon_vm *vm,
2393 struct radeon_bo *bo,
2394 struct ttm_mem_reg *mem);
2395void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2396 struct radeon_bo *bo);
421ca7ab
CK		 2397struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2398 struct radeon_bo *bo);
e971bd5e
CK		 2399struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2400 struct radeon_vm *vm,
2401 struct radeon_bo *bo);
2402int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2403 struct radeon_bo_va *bo_va,
2404 uint64_t offset,
2405 uint32_t flags);
721604a1 2406int radeon_vm_bo_rmv(struct radeon_device *rdev,
e971bd5e 2407 struct radeon_bo_va *bo_va);
721604a1 2408
f122c610
AD		 2409/* audio */
2410void r600_audio_update_hdmi(struct work_struct *work);
721604a1 2411
16cdf04d
AD		 2412/*
2413 * R600 vram scratch functions
2414 */
2415int r600_vram_scratch_init(struct radeon_device *rdev);
2416void r600_vram_scratch_fini(struct radeon_device *rdev);
2417
285484e2
JG		 2418/*
2419 * r600 cs checking helper
2420 */
2421unsigned r600_mip_minify(unsigned size, unsigned level);
2422bool r600_fmt_is_valid_color(u32 format);
2423bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2424int r600_fmt_get_blocksize(u32 format);
2425int r600_fmt_get_nblocksx(u32 format, u32 w);
2426int r600_fmt_get_nblocksy(u32 format, u32 h);
2427
3574dda4
DV		 2428/*
2429 * r600 functions used by radeon_encoder.c
2430 */
1b688d08
RM		 2431struct radeon_hdmi_acr {
2432 u32 clock;
2433
2434 int n_32khz;
2435 int cts_32khz;
2436
2437 int n_44_1khz;
2438 int cts_44_1khz;
2439
2440 int n_48khz;
2441 int cts_48khz;
2442
2443};
2444
e55d3e6c
RM		 2445extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2446
416a2bd2
AD		 2447extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2448 u32 tiling_pipe_num,
2449 u32 max_rb_num,
2450 u32 total_max_rb_num,
2451 u32 enabled_rb_mask);
fe251e2f 2452
e55d3e6c
RM		 2453/*
2454 * evergreen functions used by radeon_encoder.c
2455 */
2456
0af62b01 2457extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2458extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2459
c4917074
AD		 2460/* radeon_acpi.c */
2461#if defined(CONFIG_ACPI)
2462extern int radeon_acpi_init(struct radeon_device *rdev);
2463extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2464extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2465extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2466 u8 perf_req, bool advertise);
dc50ba7f 2467extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2468#else
2469static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2470static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2471#endif
d7a2952f 2472
c38f34b5
IH		 2473int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2474 struct radeon_cs_packet *pkt,
2475 unsigned idx);
9ffb7a6d 2476bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2477void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2478 struct radeon_cs_packet *pkt);
e9716993
IH		 2479int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2480 struct radeon_cs_reloc **cs_reloc,
2481 int nomm);
40592a17
IH		 2482int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2483 uint32_t *vline_start_end,
2484 uint32_t *vline_status);
c38f34b5 2485
4c788679
JG		 2486#include "radeon_object.h"
2487
771fe6b9 2488#endif
Linux kernel - Deliverables
This page took 0.982713 seconds and 5 git commands to generate.