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drm/radeon: Add radeon_test_syncing function v2
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
a18cee15 96extern int radeon_msi;
771fe6b9
JG		 97
98/*
99 * Copy from radeon_drv.h so we don't have to include both and have conflicting
100 * symbol;
101 */
102#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
225758d8 103#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 104/* RADEON_IB_POOL_SIZE must be a power of 2 */
771fe6b9 105#define RADEON_IB_POOL_SIZE 16
c245cb9e 106#define RADEON_DEBUGFS_MAX_COMPONENTS 32
771fe6b9 107#define RADEONFB_CONN_LIMIT 4
f657c2a7 108#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 109
771fe6b9
JG		 110/*
111 * Errata workarounds.
112 */
113enum radeon_pll_errata {
114 CHIP_ERRATA_R300_CG = 0x00000001,
115 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
116 CHIP_ERRATA_PLL_DELAY = 0x00000004
117};
118
119
120struct radeon_device;
121
122
123/*
124 * BIOS.
125 */
6a9ee8af
DA		 126#define ATRM_BIOS_PAGE 4096
127
8edb381d 128#if defined(CONFIG_VGA_SWITCHEROO)
6a9ee8af
DA		 129bool radeon_atrm_supported(struct pci_dev *pdev);
130int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
8edb381d
DA		 131#else
132static inline bool radeon_atrm_supported(struct pci_dev *pdev)
133{
134 return false;
135}
136
137static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
138 return -EINVAL;
139}
140#endif
771fe6b9
JG		 141bool radeon_get_bios(struct radeon_device *rdev);
142
3ce0a23d 143
771fe6b9 144/*
3ce0a23d 145 * Dummy page
771fe6b9 146 */
3ce0a23d
JG		 147struct radeon_dummy_page {
148 struct page *page;
149 dma_addr_t addr;
150};
151int radeon_dummy_page_init(struct radeon_device *rdev);
152void radeon_dummy_page_fini(struct radeon_device *rdev);
153
771fe6b9 154
3ce0a23d
JG		 155/*
156 * Clocks
157 */
771fe6b9
JG		 158struct radeon_clock {
159 struct radeon_pll p1pll;
160 struct radeon_pll p2pll;
bcc1c2a1 161 struct radeon_pll dcpll;
771fe6b9
JG		 162 struct radeon_pll spll;
163 struct radeon_pll mpll;
164 /* 10 Khz units */
165 uint32_t default_mclk;
166 uint32_t default_sclk;
bcc1c2a1
AD		 167 uint32_t default_dispclk;
168 uint32_t dp_extclk;
b20f9bef 169 uint32_t max_pixel_clock;
771fe6b9
JG		 170};
171
7433874e
RM		 172/*
173 * Power management
174 */
175int radeon_pm_init(struct radeon_device *rdev);
29fb52ca 176void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 177void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 178void radeon_pm_suspend(struct radeon_device *rdev);
179void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 180void radeon_combios_get_power_modes(struct radeon_device *rdev);
181void radeon_atombios_get_power_modes(struct radeon_device *rdev);
8a83ec5e 182void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ee4017f4 183int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage);
f892034a 184void rs690_pm_info(struct radeon_device *rdev);
20d391d7
AD		 185extern int rv6xx_get_temp(struct radeon_device *rdev);
186extern int rv770_get_temp(struct radeon_device *rdev);
187extern int evergreen_get_temp(struct radeon_device *rdev);
188extern int sumo_get_temp(struct radeon_device *rdev);
3ce0a23d 189
771fe6b9
JG		 190/*
191 * Fences.
192 */
193struct radeon_fence_driver {
194 uint32_t scratch_reg;
195 atomic_t seq;
196 uint32_t last_seq;
225758d8
JG		 197 unsigned long last_jiffies;
198 unsigned long last_timeout;
771fe6b9 199 wait_queue_head_t queue;
771fe6b9 200 struct list_head created;
851a6bd9 201 struct list_head emitted;
771fe6b9 202 struct list_head signaled;
0a0c7596 203 bool initialized;
771fe6b9
JG		 204};
205
206struct radeon_fence {
207 struct radeon_device *rdev;
208 struct kref kref;
209 struct list_head list;
210 /* protected by radeon_fence.lock */
211 uint32_t seq;
851a6bd9 212 bool emitted;
771fe6b9 213 bool signaled;
7465280c
AD		 214 /* RB, DMA, etc. */
215 int ring;
771fe6b9
JG		 216};
217
7465280c 218int radeon_fence_driver_init(struct radeon_device *rdev, int num_rings);
771fe6b9 219void radeon_fence_driver_fini(struct radeon_device *rdev);
7465280c 220int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
771fe6b9 221int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
7465280c 222void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 223bool radeon_fence_signaled(struct radeon_fence *fence);
224int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
7465280c
AD		 225int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
226int radeon_fence_wait_last(struct radeon_device *rdev, int ring);
771fe6b9
JG		 227struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
228void radeon_fence_unref(struct radeon_fence **fence);
229
15d3332f
CK		 230/*
231 * Semaphores.
232 */
7b1f2485
CK		 233struct radeon_cp;
234
15d3332f
CK		 235struct radeon_semaphore_driver {
236 rwlock_t lock;
237 struct list_head free;
238};
239
240struct radeon_semaphore {
241 struct radeon_bo *robj;
242 struct list_head list;
243 uint64_t gpu_addr;
244};
245
246void radeon_semaphore_driver_fini(struct radeon_device *rdev);
247int radeon_semaphore_create(struct radeon_device *rdev,
248 struct radeon_semaphore **semaphore);
249void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
250 struct radeon_semaphore *semaphore);
251void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
252 struct radeon_semaphore *semaphore);
253void radeon_semaphore_free(struct radeon_device *rdev,
254 struct radeon_semaphore *semaphore);
255
e024e110
DA		 256/*
257 * Tiling registers
258 */
259struct radeon_surface_reg {
4c788679 260 struct radeon_bo *bo;
e024e110
DA		 261};
262
263#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 264
265/*
4c788679 266 * TTM.
771fe6b9 267 */
4c788679
JG		 268struct radeon_mman {
269 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 270 struct drm_global_reference mem_global_ref;
4c788679 271 struct ttm_bo_device bdev;
0a0c7596
JG		 272 bool mem_global_referenced;
273 bool initialized;
4c788679
JG		 274};
275
276struct radeon_bo {
277 /* Protected by gem.mutex */
278 struct list_head list;
279 /* Protected by tbo.reserved */
312ea8da
JG		 280 u32 placements[3];
281 struct ttm_placement placement;
4c788679
JG		 282 struct ttm_buffer_object tbo;
283 struct ttm_bo_kmap_obj kmap;
284 unsigned pin_count;
285 void *kptr;
286 u32 tiling_flags;
287 u32 pitch;
288 int surface_reg;
289 /* Constant after initialization */
290 struct radeon_device *rdev;
441921d5 291 struct drm_gem_object gem_base;
4c788679 292};
7e4d15d9 293#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 294
4c788679 295struct radeon_bo_list {
147666fb 296 struct ttm_validate_buffer tv;
4c788679 297 struct radeon_bo *bo;
771fe6b9
JG		 298 uint64_t gpu_offset;
299 unsigned rdomain;
300 unsigned wdomain;
4c788679 301 u32 tiling_flags;
771fe6b9
JG		 302};
303
771fe6b9
JG		 304/*
305 * GEM objects.
306 */
307struct radeon_gem {
4c788679 308 struct mutex mutex;
771fe6b9
JG		 309 struct list_head objects;
310};
311
312int radeon_gem_init(struct radeon_device *rdev);
313void radeon_gem_fini(struct radeon_device *rdev);
314int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 315 int alignment, int initial_domain,
316 bool discardable, bool kernel,
317 struct drm_gem_object **obj);
771fe6b9
JG		 318int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
319 uint64_t *gpu_addr);
320void radeon_gem_object_unpin(struct drm_gem_object *obj);
321
ff72145b
DA		 322int radeon_mode_dumb_create(struct drm_file *file_priv,
323 struct drm_device *dev,
324 struct drm_mode_create_dumb *args);
325int radeon_mode_dumb_mmap(struct drm_file *filp,
326 struct drm_device *dev,
327 uint32_t handle, uint64_t *offset_p);
328int radeon_mode_dumb_destroy(struct drm_file *file_priv,
329 struct drm_device *dev,
330 uint32_t handle);
771fe6b9
JG		 331
332/*
333 * GART structures, functions & helpers
334 */
335struct radeon_mc;
336
a77f1718 337#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 338#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 339#define RADEON_GPU_PAGE_SHIFT 12
a77f1718 340
771fe6b9
JG		 341struct radeon_gart {
342 dma_addr_t table_addr;
c9a1be96
JG		 343 struct radeon_bo *robj;
344 void *ptr;
771fe6b9
JG		 345 unsigned num_gpu_pages;
346 unsigned num_cpu_pages;
347 unsigned table_size;
771fe6b9
JG		 348 struct page **pages;
349 dma_addr_t *pages_addr;
350 bool ready;
351};
352
353int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
354void radeon_gart_table_ram_free(struct radeon_device *rdev);
355int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
356void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 357int radeon_gart_table_vram_pin(struct radeon_device *rdev);
358void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 359int radeon_gart_init(struct radeon_device *rdev);
360void radeon_gart_fini(struct radeon_device *rdev);
361void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
362 int pages);
363int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516
KRW		 364 int pages, struct page **pagelist,
365 dma_addr_t *dma_addr);
c9a1be96 366void radeon_gart_restore(struct radeon_device *rdev);
771fe6b9
JG		 367
368
369/*
370 * GPU MC structures, functions & helpers
371 */
372struct radeon_mc {
373 resource_size_t aper_size;
374 resource_size_t aper_base;
375 resource_size_t agp_base;
7a50f01a
DA		 376 /* for some chips with <= 32MB we need to lie
377 * about vram size near mc fb location */
3ce0a23d 378 u64 mc_vram_size;
d594e46a 379 u64 visible_vram_size;
3ce0a23d
JG		 380 u64 gtt_size;
381 u64 gtt_start;
382 u64 gtt_end;
3ce0a23d
JG		 383 u64 vram_start;
384 u64 vram_end;
771fe6b9 385 unsigned vram_width;
3ce0a23d 386 u64 real_vram_size;
771fe6b9
JG		 387 int vram_mtrr;
388 bool vram_is_ddr;
d594e46a 389 bool igp_sideport_enabled;
8d369bb1 390 u64 gtt_base_align;
771fe6b9
JG		 391};
392
06b6476d
AD		 393bool radeon_combios_sideport_present(struct radeon_device *rdev);
394bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 395
396/*
397 * GPU scratch registers structures, functions & helpers
398 */
399struct radeon_scratch {
400 unsigned num_reg;
724c80e1 401 uint32_t reg_base;
771fe6b9
JG		 402 bool free[32];
403 uint32_t reg[32];
404};
405
406int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
407void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
408
409
410/*
411 * IRQS.
412 */
6f34be50
AD		 413
414struct radeon_unpin_work {
415 struct work_struct work;
416 struct radeon_device *rdev;
417 int crtc_id;
418 struct radeon_fence *fence;
419 struct drm_pending_vblank_event *event;
420 struct radeon_bo *old_rbo;
421 u64 new_crtc_base;
422};
423
424struct r500_irq_stat_regs {
425 u32 disp_int;
426};
427
428struct r600_irq_stat_regs {
429 u32 disp_int;
430 u32 disp_int_cont;
431 u32 disp_int_cont2;
432 u32 d1grph_int;
433 u32 d2grph_int;
434};
435
436struct evergreen_irq_stat_regs {
437 u32 disp_int;
438 u32 disp_int_cont;
439 u32 disp_int_cont2;
440 u32 disp_int_cont3;
441 u32 disp_int_cont4;
442 u32 disp_int_cont5;
443 u32 d1grph_int;
444 u32 d2grph_int;
445 u32 d3grph_int;
446 u32 d4grph_int;
447 u32 d5grph_int;
448 u32 d6grph_int;
449};
450
451union radeon_irq_stat_regs {
452 struct r500_irq_stat_regs r500;
453 struct r600_irq_stat_regs r600;
454 struct evergreen_irq_stat_regs evergreen;
455};
456
54bd5206
IH		 457#define RADEON_MAX_HPD_PINS 6
458#define RADEON_MAX_CRTCS 6
459#define RADEON_MAX_HDMI_BLOCKS 2
460
771fe6b9
JG		 461struct radeon_irq {
462 bool installed;
463 bool sw_int;
54bd5206
IH		 464 bool crtc_vblank_int[RADEON_MAX_CRTCS];
465 bool pflip[RADEON_MAX_CRTCS];
73a6d3fc 466 wait_queue_head_t vblank_queue;
54bd5206 467 bool hpd[RADEON_MAX_HPD_PINS];
2031f77c
AD		 468 bool gui_idle;
469 bool gui_idle_acked;
470 wait_queue_head_t idle_queue;
54bd5206 471 bool hdmi[RADEON_MAX_HDMI_BLOCKS];
1614f8b1
DA		 472 spinlock_t sw_lock;
473 int sw_refcount;
6f34be50 474 union radeon_irq_stat_regs stat_regs;
54bd5206
IH		 475 spinlock_t pflip_lock[RADEON_MAX_CRTCS];
476 int pflip_refcount[RADEON_MAX_CRTCS];
771fe6b9
JG		 477};
478
479int radeon_irq_kms_init(struct radeon_device *rdev);
480void radeon_irq_kms_fini(struct radeon_device *rdev);
1614f8b1
DA		 481void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
482void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
6f34be50
AD		 483void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
484void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 485
486/*
487 * CP & ring.
488 */
7465280c
AD		 489
490/* max number of rings */
491#define RADEON_NUM_RINGS 3
492
493/* internal ring indices */
494/* r1xx+ has gfx CP ring */
495#define RADEON_RING_TYPE_GFX_INDEX 0
496
497/* cayman has 2 compute CP rings */
498#define CAYMAN_RING_TYPE_CP1_INDEX 1
499#define CAYMAN_RING_TYPE_CP2_INDEX 2
500
771fe6b9
JG		 501struct radeon_ib {
502 struct list_head list;
e821767b 503 unsigned idx;
771fe6b9
JG		 504 uint64_t gpu_addr;
505 struct radeon_fence *fence;
e821767b 506 uint32_t *ptr;
771fe6b9 507 uint32_t length_dw;
e821767b 508 bool free;
771fe6b9
JG		 509};
510
ecb114a1
DA		 511/*
512 * locking -
513 * mutex protects scheduled_ibs, ready, alloc_bm
514 */
771fe6b9
JG		 515struct radeon_ib_pool {
516 struct mutex mutex;
4c788679 517 struct radeon_bo *robj;
9f93ed39 518 struct list_head bogus_ib;
771fe6b9
JG		 519 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
520 bool ready;
e821767b 521 unsigned head_id;
771fe6b9
JG		 522};
523
524struct radeon_cp {
4c788679 525 struct radeon_bo *ring_obj;
771fe6b9
JG		 526 volatile uint32_t *ring;
527 unsigned rptr;
5596a9db
CK		 528 unsigned rptr_offs;
529 unsigned rptr_reg;
771fe6b9
JG		 530 unsigned wptr;
531 unsigned wptr_old;
5596a9db 532 unsigned wptr_reg;
771fe6b9
JG		 533 unsigned ring_size;
534 unsigned ring_free_dw;
535 int count_dw;
536 uint64_t gpu_addr;
537 uint32_t align_mask;
538 uint32_t ptr_mask;
539 struct mutex mutex;
540 bool ready;
541};
542
d8f60cfc
AD		 543/*
544 * R6xx+ IH ring
545 */
546struct r600_ih {
4c788679 547 struct radeon_bo *ring_obj;
d8f60cfc
AD		 548 volatile uint32_t *ring;
549 unsigned rptr;
bf852799 550 unsigned rptr_offs;
d8f60cfc
AD		 551 unsigned wptr;
552 unsigned wptr_old;
553 unsigned ring_size;
554 uint64_t gpu_addr;
d8f60cfc
AD		 555 uint32_t ptr_mask;
556 spinlock_t lock;
557 bool enabled;
558};
559
8eec9d6f
IH		 560struct r600_blit_cp_primitives {
561 void (*set_render_target)(struct radeon_device *rdev, int format,
562 int w, int h, u64 gpu_addr);
563 void (*cp_set_surface_sync)(struct radeon_device *rdev,
564 u32 sync_type, u32 size,
565 u64 mc_addr);
566 void (*set_shaders)(struct radeon_device *rdev);
567 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
568 void (*set_tex_resource)(struct radeon_device *rdev,
569 int format, int w, int h, int pitch,
9bb7703c 570 u64 gpu_addr, u32 size);
8eec9d6f
IH		 571 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
572 int x2, int y2);
573 void (*draw_auto)(struct radeon_device *rdev);
574 void (*set_default_state)(struct radeon_device *rdev);
575};
576
3ce0a23d 577struct r600_blit {
ff82f052 578 struct mutex mutex;
4c788679 579 struct radeon_bo *shader_obj;
8eec9d6f
IH		 580 struct r600_blit_cp_primitives primitives;
581 int max_dim;
582 int ring_size_common;
583 int ring_size_per_loop;
3ce0a23d
JG		 584 u64 shader_gpu_addr;
585 u32 vs_offset, ps_offset;
586 u32 state_offset;
587 u32 state_len;
588 u32 vb_used, vb_total;
589 struct radeon_ib *vb_ib;
590};
591
6ddddfe7
AD		 592void r600_blit_suspend(struct radeon_device *rdev);
593
7b1f2485 594int radeon_ib_get(struct radeon_device *rdev, int ring, struct radeon_ib **ib);
771fe6b9
JG		 595void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
596int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
597int radeon_ib_pool_init(struct radeon_device *rdev);
598void radeon_ib_pool_fini(struct radeon_device *rdev);
599int radeon_ib_test(struct radeon_device *rdev);
9f93ed39 600extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
771fe6b9 601/* Ring access between begin & end cannot sleep */
bf852799 602int radeon_ring_index(struct radeon_device *rdev, struct radeon_cp *cp);
7b1f2485
CK		 603void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_cp *cp);
604int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ndw);
605int radeon_ring_lock(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ndw);
606void radeon_ring_commit(struct radeon_device *rdev, struct radeon_cp *cp);
607void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_cp *cp);
608void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_cp *cp);
609int radeon_ring_test(struct radeon_device *rdev, struct radeon_cp *cp);
5596a9db
CK		 610int radeon_ring_init(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ring_size,
611 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg);
7b1f2485 612void radeon_ring_fini(struct radeon_device *rdev, struct radeon_cp *cp);
771fe6b9
JG		 613
614
615/*
616 * CS.
617 */
618struct radeon_cs_reloc {
619 struct drm_gem_object *gobj;
4c788679
JG		 620 struct radeon_bo *robj;
621 struct radeon_bo_list lobj;
771fe6b9
JG		 622 uint32_t handle;
623 uint32_t flags;
624};
625
626struct radeon_cs_chunk {
627 uint32_t chunk_id;
628 uint32_t length_dw;
513bcb46
DA		 629 int kpage_idx[2];
630 uint32_t *kpage[2];
771fe6b9 631 uint32_t *kdata;
513bcb46
DA		 632 void __user *user_ptr;
633 int last_copied_page;
634 int last_page_index;
771fe6b9
JG		 635};
636
637struct radeon_cs_parser {
c8c15ff1 638 struct device *dev;
771fe6b9
JG		 639 struct radeon_device *rdev;
640 struct drm_file *filp;
641 /* chunks */
642 unsigned nchunks;
643 struct radeon_cs_chunk *chunks;
644 uint64_t *chunks_array;
645 /* IB */
646 unsigned idx;
647 /* relocations */
648 unsigned nrelocs;
649 struct radeon_cs_reloc *relocs;
650 struct radeon_cs_reloc **relocs_ptr;
651 struct list_head validated;
652 /* indices of various chunks */
653 int chunk_ib_idx;
654 int chunk_relocs_idx;
655 struct radeon_ib *ib;
656 void *track;
3ce0a23d 657 unsigned family;
e70f224c
MO		 658 int parser_error;
659 bool keep_tiling_flags;
771fe6b9
JG		 660};
661
513bcb46
DA		 662extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
663extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
ce580fab 664extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
513bcb46 665
771fe6b9
JG		 666struct radeon_cs_packet {
667 unsigned idx;
668 unsigned type;
669 unsigned reg;
670 unsigned opcode;
671 int count;
672 unsigned one_reg_wr;
673};
674
675typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
676 struct radeon_cs_packet *pkt,
677 unsigned idx, unsigned reg);
678typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
679 struct radeon_cs_packet *pkt);
680
681
682/*
683 * AGP
684 */
685int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 686void radeon_agp_resume(struct radeon_device *rdev);
10b06122 687void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 688void radeon_agp_fini(struct radeon_device *rdev);
689
690
691/*
692 * Writeback
693 */
694struct radeon_wb {
4c788679 695 struct radeon_bo *wb_obj;
771fe6b9
JG		 696 volatile uint32_t *wb;
697 uint64_t gpu_addr;
724c80e1 698 bool enabled;
d0f8a854 699 bool use_event;
771fe6b9
JG		 700};
701
724c80e1
AD		 702#define RADEON_WB_SCRATCH_OFFSET 0
703#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 704#define RADEON_WB_CP1_RPTR_OFFSET 1280
705#define RADEON_WB_CP2_RPTR_OFFSET 1536
724c80e1 706#define R600_WB_IH_WPTR_OFFSET 2048
d0f8a854 707#define R600_WB_EVENT_OFFSET 3072
724c80e1 708
c93bb85b
JG		 709/**
710 * struct radeon_pm - power management datas
711 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
712 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
713 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
714 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
715 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
716 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
717 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
718 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
719 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 720 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 721 * @needed_bandwidth: current bandwidth needs
722 *
723 * It keeps track of various data needed to take powermanagement decision.
25985edc 724 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 725 * Equation between gpu/memory clock and available bandwidth is hw dependent
726 * (type of memory, bus size, efficiency, ...)
727 */
ce8f5370
AD		 728
729enum radeon_pm_method {
730 PM_METHOD_PROFILE,
731 PM_METHOD_DYNPM,
732};
733
734enum radeon_dynpm_state {
735 DYNPM_STATE_DISABLED,
736 DYNPM_STATE_MINIMUM,
737 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 738 DYNPM_STATE_ACTIVE,
739 DYNPM_STATE_SUSPENDED,
c913e23a 740};
ce8f5370
AD		 741enum radeon_dynpm_action {
742 DYNPM_ACTION_NONE,
743 DYNPM_ACTION_MINIMUM,
744 DYNPM_ACTION_DOWNCLOCK,
745 DYNPM_ACTION_UPCLOCK,
746 DYNPM_ACTION_DEFAULT
c913e23a 747};
56278a8e
AD		 748
749enum radeon_voltage_type {
750 VOLTAGE_NONE = 0,
751 VOLTAGE_GPIO,
752 VOLTAGE_VDDC,
753 VOLTAGE_SW
754};
755
0ec0e74f
AD		 756enum radeon_pm_state_type {
757 POWER_STATE_TYPE_DEFAULT,
758 POWER_STATE_TYPE_POWERSAVE,
759 POWER_STATE_TYPE_BATTERY,
760 POWER_STATE_TYPE_BALANCED,
761 POWER_STATE_TYPE_PERFORMANCE,
762};
763
ce8f5370
AD		 764enum radeon_pm_profile_type {
765 PM_PROFILE_DEFAULT,
766 PM_PROFILE_AUTO,
767 PM_PROFILE_LOW,
c9e75b21 768 PM_PROFILE_MID,
ce8f5370
AD		 769 PM_PROFILE_HIGH,
770};
771
772#define PM_PROFILE_DEFAULT_IDX 0
773#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 774#define PM_PROFILE_MID_SH_IDX 2
775#define PM_PROFILE_HIGH_SH_IDX 3
776#define PM_PROFILE_LOW_MH_IDX 4
777#define PM_PROFILE_MID_MH_IDX 5
778#define PM_PROFILE_HIGH_MH_IDX 6
779#define PM_PROFILE_MAX 7
ce8f5370
AD		 780
781struct radeon_pm_profile {
782 int dpms_off_ps_idx;
783 int dpms_on_ps_idx;
784 int dpms_off_cm_idx;
785 int dpms_on_cm_idx;
516d0e46
AD		 786};
787
21a8122a
AD		 788enum radeon_int_thermal_type {
789 THERMAL_TYPE_NONE,
790 THERMAL_TYPE_RV6XX,
791 THERMAL_TYPE_RV770,
792 THERMAL_TYPE_EVERGREEN,
e33df25f 793 THERMAL_TYPE_SUMO,
4fddba1f 794 THERMAL_TYPE_NI,
21a8122a
AD		 795};
796
56278a8e
AD		 797struct radeon_voltage {
798 enum radeon_voltage_type type;
799 /* gpio voltage */
800 struct radeon_gpio_rec gpio;
801 u32 delay; /* delay in usec from voltage drop to sclk change */
802 bool active_high; /* voltage drop is active when bit is high */
803 /* VDDC voltage */
804 u8 vddc_id; /* index into vddc voltage table */
805 u8 vddci_id; /* index into vddci voltage table */
806 bool vddci_enabled;
807 /* r6xx+ sw */
2feea49a
AD		 808 u16 voltage;
809 /* evergreen+ vddci */
810 u16 vddci;
56278a8e
AD		 811};
812
d7311171
AD		 813/* clock mode flags */
814#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
815
56278a8e
AD		 816struct radeon_pm_clock_info {
817 /* memory clock */
818 u32 mclk;
819 /* engine clock */
820 u32 sclk;
821 /* voltage info */
822 struct radeon_voltage voltage;
d7311171 823 /* standardized clock flags */
56278a8e
AD		 824 u32 flags;
825};
826
a48b9b4e 827/* state flags */
d7311171 828#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 829
56278a8e 830struct radeon_power_state {
0ec0e74f 831 enum radeon_pm_state_type type;
8f3f1c9a 832 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 833 /* number of valid clock modes in this power state */
834 int num_clock_modes;
56278a8e 835 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 836 /* standardized state flags */
837 u32 flags;
79daedc9
AD		 838 u32 misc; /* vbios specific flags */
839 u32 misc2; /* vbios specific flags */
840 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 841};
842
27459324
RM		 843/*
844 * Some modes are overclocked by very low value, accept them
845 */
846#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
847
c93bb85b 848struct radeon_pm {
c913e23a 849 struct mutex mutex;
a48b9b4e
AD		 850 u32 active_crtcs;
851 int active_crtc_count;
c913e23a 852 int req_vblank;
839461d3 853 bool vblank_sync;
2031f77c 854 bool gui_idle;
c93bb85b
JG		 855 fixed20_12 max_bandwidth;
856 fixed20_12 igp_sideport_mclk;
857 fixed20_12 igp_system_mclk;
858 fixed20_12 igp_ht_link_clk;
859 fixed20_12 igp_ht_link_width;
860 fixed20_12 k8_bandwidth;
861 fixed20_12 sideport_bandwidth;
862 fixed20_12 ht_bandwidth;
863 fixed20_12 core_bandwidth;
864 fixed20_12 sclk;
f47299c5 865 fixed20_12 mclk;
c93bb85b 866 fixed20_12 needed_bandwidth;
0975b162 867 struct radeon_power_state *power_state;
56278a8e
AD		 868 /* number of valid power states */
869 int num_power_states;
a48b9b4e
AD		 870 int current_power_state_index;
871 int current_clock_mode_index;
872 int requested_power_state_index;
873 int requested_clock_mode_index;
874 int default_power_state_index;
875 u32 current_sclk;
876 u32 current_mclk;
2feea49a
AD		 877 u16 current_vddc;
878 u16 current_vddci;
9ace9f7b
AD		 879 u32 default_sclk;
880 u32 default_mclk;
2feea49a
AD		 881 u16 default_vddc;
882 u16 default_vddci;
29fb52ca 883 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 884 /* selected pm method */
885 enum radeon_pm_method pm_method;
886 /* dynpm power management */
887 struct delayed_work dynpm_idle_work;
888 enum radeon_dynpm_state dynpm_state;
889 enum radeon_dynpm_action dynpm_planned_action;
890 unsigned long dynpm_action_timeout;
891 bool dynpm_can_upclock;
892 bool dynpm_can_downclock;
893 /* profile-based power management */
894 enum radeon_pm_profile_type profile;
895 int profile_index;
896 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 897 /* internal thermal controller on rv6xx+ */
898 enum radeon_int_thermal_type int_thermal_type;
899 struct device *int_hwmon_dev;
c93bb85b
JG		 900};
901
a4c9e2ee
AD		 902int radeon_pm_get_type_index(struct radeon_device *rdev,
903 enum radeon_pm_state_type ps_type,
904 int instance);
771fe6b9
JG		 905
906/*
907 * Benchmarking
908 */
638dd7db 909void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 910
911
ecc0b326
MD		 912/*
913 * Testing
914 */
915void radeon_test_moves(struct radeon_device *rdev);
60a7e396
CK		 916void radeon_test_ring_sync(struct radeon_device *rdev,
917 struct radeon_cp *cpA,
918 struct radeon_cp *cpB);
919void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326
MD		 920
921
771fe6b9
JG		 922/*
923 * Debugfs
924 */
4d8bf9ae
CK		 925struct radeon_debugfs {
926 struct drm_info_list *files;
927 unsigned num_files;
928};
929
771fe6b9
JG		 930int radeon_debugfs_add_files(struct radeon_device *rdev,
931 struct drm_info_list *files,
932 unsigned nfiles);
933int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9
JG		 934
935
936/*
937 * ASIC specific functions.
938 */
939struct radeon_asic {
068a117c 940 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 941 void (*fini)(struct radeon_device *rdev);
942 int (*resume)(struct radeon_device *rdev);
943 int (*suspend)(struct radeon_device *rdev);
28d52043 944 void (*vga_set_state)(struct radeon_device *rdev, bool state);
7b1f2485 945 bool (*gpu_is_lockup)(struct radeon_device *rdev, struct radeon_cp *cp);
a2d07b74 946 int (*asic_reset)(struct radeon_device *rdev);
771fe6b9
JG		 947 void (*gart_tlb_flush)(struct radeon_device *rdev);
948 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
949 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
950 void (*cp_fini)(struct radeon_device *rdev);
951 void (*cp_disable)(struct radeon_device *rdev);
952 void (*ring_start)(struct radeon_device *rdev);
7b1f2485 953 int (*ring_test)(struct radeon_device *rdev, struct radeon_cp *cp);
3ce0a23d 954 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
771fe6b9
JG		 955 int (*irq_set)(struct radeon_device *rdev);
956 int (*irq_process)(struct radeon_device *rdev);
7ed220d7 957 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
771fe6b9 958 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
15d3332f 959 void (*semaphore_ring_emit)(struct radeon_device *rdev,
7b1f2485 960 struct radeon_cp *cp,
15d3332f 961 struct radeon_semaphore *semaphore,
7b1f2485 962 bool emit_wait);
771fe6b9
JG		 963 int (*cs_parse)(struct radeon_cs_parser *p);
964 int (*copy_blit)(struct radeon_device *rdev,
965 uint64_t src_offset,
966 uint64_t dst_offset,
003cefe0 967 unsigned num_gpu_pages,
771fe6b9
JG		 968 struct radeon_fence *fence);
969 int (*copy_dma)(struct radeon_device *rdev,
970 uint64_t src_offset,
971 uint64_t dst_offset,
003cefe0 972 unsigned num_gpu_pages,
771fe6b9
JG		 973 struct radeon_fence *fence);
974 int (*copy)(struct radeon_device *rdev,
975 uint64_t src_offset,
976 uint64_t dst_offset,
003cefe0 977 unsigned num_gpu_pages,
771fe6b9 978 struct radeon_fence *fence);
7433874e 979 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
771fe6b9 980 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
7433874e 981 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
771fe6b9 982 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
c836a412 983 int (*get_pcie_lanes)(struct radeon_device *rdev);
771fe6b9
JG		 984 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
985 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
e024e110
DA		 986 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
987 uint32_t tiling_flags, uint32_t pitch,
988 uint32_t offset, uint32_t obj_size);
9479c54f 989 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
c93bb85b 990 void (*bandwidth_update)(struct radeon_device *rdev);
429770b3
AD		 991 void (*hpd_init)(struct radeon_device *rdev);
992 void (*hpd_fini)(struct radeon_device *rdev);
993 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
994 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
062b389c
JG		 995 /* ioctl hw specific callback. Some hw might want to perform special
996 * operation on specific ioctl. For instance on wait idle some hw
997 * might want to perform and HDP flush through MMIO as it seems that
998 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
999 * through ring.
1000 */
1001 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
def9ba9c 1002 bool (*gui_idle)(struct radeon_device *rdev);
ce8f5370 1003 /* power management */
49e02b73
AD		 1004 void (*pm_misc)(struct radeon_device *rdev);
1005 void (*pm_prepare)(struct radeon_device *rdev);
1006 void (*pm_finish)(struct radeon_device *rdev);
ce8f5370
AD		 1007 void (*pm_init_profile)(struct radeon_device *rdev);
1008 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
6f34be50
AD		 1009 /* pageflipping */
1010 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1011 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1012 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 1013};
1014
21f9a437
JG		 1015/*
1016 * Asic structures
1017 */
225758d8
JG		 1018struct r100_gpu_lockup {
1019 unsigned long last_jiffies;
1020 u32 last_cp_rptr;
1021};
1022
551ebd83 1023struct r100_asic {
225758d8
JG		 1024 const unsigned *reg_safe_bm;
1025 unsigned reg_safe_bm_size;
1026 u32 hdp_cntl;
1027 struct r100_gpu_lockup lockup;
551ebd83
DA		 1028};
1029
21f9a437 1030struct r300_asic {
225758d8
JG		 1031 const unsigned *reg_safe_bm;
1032 unsigned reg_safe_bm_size;
1033 u32 resync_scratch;
1034 u32 hdp_cntl;
1035 struct r100_gpu_lockup lockup;
21f9a437
JG		 1036};
1037
1038struct r600_asic {
225758d8
JG		 1039 unsigned max_pipes;
1040 unsigned max_tile_pipes;
1041 unsigned max_simds;
1042 unsigned max_backends;
1043 unsigned max_gprs;
1044 unsigned max_threads;
1045 unsigned max_stack_entries;
1046 unsigned max_hw_contexts;
1047 unsigned max_gs_threads;
1048 unsigned sx_max_export_size;
1049 unsigned sx_max_export_pos_size;
1050 unsigned sx_max_export_smx_size;
1051 unsigned sq_num_cf_insts;
1052 unsigned tiling_nbanks;
1053 unsigned tiling_npipes;
1054 unsigned tiling_group_size;
e7aeeba6 1055 unsigned tile_config;
e55b9422 1056 unsigned backend_map;
225758d8 1057 struct r100_gpu_lockup lockup;
21f9a437
JG		 1058};
1059
1060struct rv770_asic {
225758d8
JG		 1061 unsigned max_pipes;
1062 unsigned max_tile_pipes;
1063 unsigned max_simds;
1064 unsigned max_backends;
1065 unsigned max_gprs;
1066 unsigned max_threads;
1067 unsigned max_stack_entries;
1068 unsigned max_hw_contexts;
1069 unsigned max_gs_threads;
1070 unsigned sx_max_export_size;
1071 unsigned sx_max_export_pos_size;
1072 unsigned sx_max_export_smx_size;
1073 unsigned sq_num_cf_insts;
1074 unsigned sx_num_of_sets;
1075 unsigned sc_prim_fifo_size;
1076 unsigned sc_hiz_tile_fifo_size;
1077 unsigned sc_earlyz_tile_fifo_fize;
1078 unsigned tiling_nbanks;
1079 unsigned tiling_npipes;
1080 unsigned tiling_group_size;
e7aeeba6 1081 unsigned tile_config;
e55b9422 1082 unsigned backend_map;
225758d8 1083 struct r100_gpu_lockup lockup;
21f9a437
JG		 1084};
1085
32fcdbf4
AD		 1086struct evergreen_asic {
1087 unsigned num_ses;
1088 unsigned max_pipes;
1089 unsigned max_tile_pipes;
1090 unsigned max_simds;
1091 unsigned max_backends;
1092 unsigned max_gprs;
1093 unsigned max_threads;
1094 unsigned max_stack_entries;
1095 unsigned max_hw_contexts;
1096 unsigned max_gs_threads;
1097 unsigned sx_max_export_size;
1098 unsigned sx_max_export_pos_size;
1099 unsigned sx_max_export_smx_size;
1100 unsigned sq_num_cf_insts;
1101 unsigned sx_num_of_sets;
1102 unsigned sc_prim_fifo_size;
1103 unsigned sc_hiz_tile_fifo_size;
1104 unsigned sc_earlyz_tile_fifo_size;
1105 unsigned tiling_nbanks;
1106 unsigned tiling_npipes;
1107 unsigned tiling_group_size;
e7aeeba6 1108 unsigned tile_config;
e55b9422 1109 unsigned backend_map;
17db7042 1110 struct r100_gpu_lockup lockup;
32fcdbf4
AD		 1111};
1112
fecf1d07
AD		 1113struct cayman_asic {
1114 unsigned max_shader_engines;
1115 unsigned max_pipes_per_simd;
1116 unsigned max_tile_pipes;
1117 unsigned max_simds_per_se;
1118 unsigned max_backends_per_se;
1119 unsigned max_texture_channel_caches;
1120 unsigned max_gprs;
1121 unsigned max_threads;
1122 unsigned max_gs_threads;
1123 unsigned max_stack_entries;
1124 unsigned sx_num_of_sets;
1125 unsigned sx_max_export_size;
1126 unsigned sx_max_export_pos_size;
1127 unsigned sx_max_export_smx_size;
1128 unsigned max_hw_contexts;
1129 unsigned sq_num_cf_insts;
1130 unsigned sc_prim_fifo_size;
1131 unsigned sc_hiz_tile_fifo_size;
1132 unsigned sc_earlyz_tile_fifo_size;
1133
1134 unsigned num_shader_engines;
1135 unsigned num_shader_pipes_per_simd;
1136 unsigned num_tile_pipes;
1137 unsigned num_simds_per_se;
1138 unsigned num_backends_per_se;
1139 unsigned backend_disable_mask_per_asic;
1140 unsigned backend_map;
1141 unsigned num_texture_channel_caches;
1142 unsigned mem_max_burst_length_bytes;
1143 unsigned mem_row_size_in_kb;
1144 unsigned shader_engine_tile_size;
1145 unsigned num_gpus;
1146 unsigned multi_gpu_tile_size;
1147
1148 unsigned tile_config;
1149 struct r100_gpu_lockup lockup;
1150};
1151
068a117c
JG		 1152union radeon_asic_config {
1153 struct r300_asic r300;
551ebd83 1154 struct r100_asic r100;
3ce0a23d
JG		 1155 struct r600_asic r600;
1156 struct rv770_asic rv770;
32fcdbf4 1157 struct evergreen_asic evergreen;
fecf1d07 1158 struct cayman_asic cayman;
068a117c
JG		 1159};
1160
0a10c851
DV		 1161/*
1162 * asic initizalization from radeon_asic.c
1163 */
1164void radeon_agp_disable(struct radeon_device *rdev);
1165int radeon_asic_init(struct radeon_device *rdev);
1166
771fe6b9
JG		 1167
1168/*
1169 * IOCTL.
1170 */
1171int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1172 struct drm_file *filp);
1173int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1174 struct drm_file *filp);
1175int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1176 struct drm_file *file_priv);
1177int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1178 struct drm_file *file_priv);
1179int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1180 struct drm_file *file_priv);
1181int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1182 struct drm_file *file_priv);
1183int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1184 struct drm_file *filp);
1185int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1186 struct drm_file *filp);
1187int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1188 struct drm_file *filp);
1189int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1190 struct drm_file *filp);
1191int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 1192int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1193 struct drm_file *filp);
1194int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1195 struct drm_file *filp);
771fe6b9 1196
16cdf04d
AD		 1197/* VRAM scratch page for HDP bug, default vram page */
1198struct r600_vram_scratch {
87cbf8f2
AD		 1199 struct radeon_bo *robj;
1200 volatile uint32_t *ptr;
16cdf04d 1201 u64 gpu_addr;
87cbf8f2 1202};
771fe6b9 1203
7a1619b9
MD		 1204
1205/*
1206 * Mutex which allows recursive locking from the same process.
1207 */
1208struct radeon_mutex {
1209 struct mutex mutex;
1210 struct task_struct *owner;
1211 int level;
1212};
1213
1214static inline void radeon_mutex_init(struct radeon_mutex *mutex)
1215{
1216 mutex_init(&mutex->mutex);
1217 mutex->owner = NULL;
1218 mutex->level = 0;
1219}
1220
1221static inline void radeon_mutex_lock(struct radeon_mutex *mutex)
1222{
1223 if (mutex_trylock(&mutex->mutex)) {
1224 /* The mutex was unlocked before, so it's ours now */
1225 mutex->owner = current;
1226 } else if (mutex->owner != current) {
1227 /* Another process locked the mutex, take it */
1228 mutex_lock(&mutex->mutex);
1229 mutex->owner = current;
1230 }
1231 /* Otherwise the mutex was already locked by this process */
1232
1233 mutex->level++;
1234}
1235
1236static inline void radeon_mutex_unlock(struct radeon_mutex *mutex)
1237{
1238 if (--mutex->level > 0)
1239 return;
1240
1241 mutex->owner = NULL;
1242 mutex_unlock(&mutex->mutex);
1243}
1244
1245
771fe6b9
JG		 1246/*
1247 * Core structure, functions and helpers.
1248 */
1249typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1250typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1251
1252struct radeon_device {
9f022ddf 1253 struct device *dev;
771fe6b9
JG		 1254 struct drm_device *ddev;
1255 struct pci_dev *pdev;
1256 /* ASIC */
068a117c 1257 union radeon_asic_config config;
771fe6b9
JG		 1258 enum radeon_family family;
1259 unsigned long flags;
1260 int usec_timeout;
1261 enum radeon_pll_errata pll_errata;
1262 int num_gb_pipes;
f779b3e5 1263 int num_z_pipes;
771fe6b9
JG		 1264 int disp_priority;
1265 /* BIOS */
1266 uint8_t *bios;
1267 bool is_atom_bios;
1268 uint16_t bios_header_start;
4c788679 1269 struct radeon_bo *stollen_vga_memory;
771fe6b9 1270 /* Register mmio */
4c9bc75c
DA		 1271 resource_size_t rmmio_base;
1272 resource_size_t rmmio_size;
a0533fbf 1273 void __iomem *rmmio;
771fe6b9
JG		 1274 radeon_rreg_t mc_rreg;
1275 radeon_wreg_t mc_wreg;
1276 radeon_rreg_t pll_rreg;
1277 radeon_wreg_t pll_wreg;
de1b2898 1278 uint32_t pcie_reg_mask;
771fe6b9
JG		 1279 radeon_rreg_t pciep_rreg;
1280 radeon_wreg_t pciep_wreg;
351a52a2
AD		 1281 /* io port */
1282 void __iomem *rio_mem;
1283 resource_size_t rio_mem_size;
771fe6b9
JG		 1284 struct radeon_clock clock;
1285 struct radeon_mc mc;
1286 struct radeon_gart gart;
1287 struct radeon_mode_info mode_info;
1288 struct radeon_scratch scratch;
1289 struct radeon_mman mman;
7465280c
AD		 1290 rwlock_t fence_lock;
1291 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
15d3332f 1292 struct radeon_semaphore_driver semaphore_drv;
bf852799 1293 struct radeon_cp cp[RADEON_NUM_RINGS];
771fe6b9
JG		 1294 struct radeon_ib_pool ib_pool;
1295 struct radeon_irq irq;
1296 struct radeon_asic *asic;
1297 struct radeon_gem gem;
c93bb85b 1298 struct radeon_pm pm;
f657c2a7 1299 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
7a1619b9 1300 struct radeon_mutex cs_mutex;
771fe6b9 1301 struct radeon_wb wb;
3ce0a23d 1302 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 1303 bool gpu_lockup;
1304 bool shutdown;
1305 bool suspend;
ad49f501 1306 bool need_dma32;
733289c2 1307 bool accel_working;
e024e110 1308 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 1309 const struct firmware *me_fw; /* all family ME firmware */
1310 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 1311 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 1312 const struct firmware *mc_fw; /* NI MC firmware */
3ce0a23d 1313 struct r600_blit r600_blit;
16cdf04d 1314 struct r600_vram_scratch vram_scratch;
3e5cb98d 1315 int msi_enabled; /* msi enabled */
d8f60cfc 1316 struct r600_ih ih; /* r6/700 interrupt ring */
d4877cf2 1317 struct work_struct hotplug_work;
18917b60 1318 int num_crtc; /* number of crtcs */
40bacf16 1319 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
5876dd24 1320 struct mutex vram_mutex;
dafc3bd5
CK		 1321
1322 /* audio stuff */
7eea7e9e 1323 bool audio_enabled;
dafc3bd5
CK		 1324 struct timer_list audio_timer;
1325 int audio_channels;
1326 int audio_rate;
1327 int audio_bits_per_sample;
1328 uint8_t audio_status_bits;
1329 uint8_t audio_category_code;
6a9ee8af 1330
ce8f5370 1331 struct notifier_block acpi_nb;
9eba4a93 1332 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 1333 struct drm_file *hyperz_filp;
9eba4a93 1334 struct drm_file *cmask_filp;
f376b94f
AD		 1335 /* i2c buses */
1336 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 1337 /* debugfs */
1338 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1339 unsigned debugfs_count;
771fe6b9
JG		 1340};
1341
1342int radeon_device_init(struct radeon_device *rdev,
1343 struct drm_device *ddev,
1344 struct pci_dev *pdev,
1345 uint32_t flags);
1346void radeon_device_fini(struct radeon_device *rdev);
1347int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1348
6fcbef7a
AK		 1349uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1350void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1351u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1352void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 1353
4c788679
JG		 1354/*
1355 * Cast helper
1356 */
1357#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 1358
1359/*
1360 * Registers read & write functions.
1361 */
a0533fbf
BH		 1362#define RREG8(reg) readb((rdev->rmmio) + (reg))
1363#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1364#define RREG16(reg) readw((rdev->rmmio) + (reg))
1365#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
de1b2898 1366#define RREG32(reg) r100_mm_rreg(rdev, (reg))
3ce0a23d 1367#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
de1b2898 1368#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
771fe6b9
JG		 1369#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1370#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1371#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1372#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1373#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1374#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 1375#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1376#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
aa5120d2
RM		 1377#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1378#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
771fe6b9
JG		 1379#define WREG32_P(reg, val, mask) \
1380 do { \
1381 uint32_t tmp_ = RREG32(reg); \
1382 tmp_ &= (mask); \
1383 tmp_ |= ((val) & ~(mask)); \
1384 WREG32(reg, tmp_); \
1385 } while (0)
1386#define WREG32_PLL_P(reg, val, mask) \
1387 do { \
1388 uint32_t tmp_ = RREG32_PLL(reg); \
1389 tmp_ &= (mask); \
1390 tmp_ |= ((val) & ~(mask)); \
1391 WREG32_PLL(reg, tmp_); \
1392 } while (0)
3ce0a23d 1393#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
351a52a2
AD		 1394#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1395#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 1396
de1b2898
DA		 1397/*
1398 * Indirect registers accessor
1399 */
1400static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1401{
1402 uint32_t r;
1403
1404 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1405 r = RREG32(RADEON_PCIE_DATA);
1406 return r;
1407}
1408
1409static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1410{
1411 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1412 WREG32(RADEON_PCIE_DATA, (v));
1413}
1414
771fe6b9
JG		 1415void r100_pll_errata_after_index(struct radeon_device *rdev);
1416
1417
1418/*
1419 * ASICs helpers.
1420 */
b995e433
DA		 1421#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1422 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 1423#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1424 (rdev->family == CHIP_RV200) || \
1425 (rdev->family == CHIP_RS100) || \
1426 (rdev->family == CHIP_RS200) || \
1427 (rdev->family == CHIP_RV250) || \
1428 (rdev->family == CHIP_RV280) || \
1429 (rdev->family == CHIP_RS300))
1430#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1431 (rdev->family == CHIP_RV350) || \
1432 (rdev->family == CHIP_R350) || \
1433 (rdev->family == CHIP_RV380) || \
1434 (rdev->family == CHIP_R420) || \
1435 (rdev->family == CHIP_R423) || \
1436 (rdev->family == CHIP_RV410) || \
1437 (rdev->family == CHIP_RS400) || \
1438 (rdev->family == CHIP_RS480))
3313e3d4
AD		 1439#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1440 (rdev->ddev->pdev->device == 0x9443) || \
1441 (rdev->ddev->pdev->device == 0x944B) || \
1442 (rdev->ddev->pdev->device == 0x9506) || \
1443 (rdev->ddev->pdev->device == 0x9509) || \
1444 (rdev->ddev->pdev->device == 0x950F) || \
1445 (rdev->ddev->pdev->device == 0x689C) || \
1446 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 1447#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 1448#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1449 (rdev->family == CHIP_RS690) || \
1450 (rdev->family == CHIP_RS740) || \
1451 (rdev->family >= CHIP_R600))
771fe6b9
JG		 1452#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1453#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 1454#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 1455#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1456 (rdev->flags & RADEON_IS_IGP))
1fe18305 1457#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
771fe6b9
JG		 1458
1459/*
1460 * BIOS helpers.
1461 */
1462#define RBIOS8(i) (rdev->bios[i])
1463#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1464#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1465
1466int radeon_combios_init(struct radeon_device *rdev);
1467void radeon_combios_fini(struct radeon_device *rdev);
1468int radeon_atombios_init(struct radeon_device *rdev);
1469void radeon_atombios_fini(struct radeon_device *rdev);
1470
1471
1472/*
1473 * RING helpers.
1474 */
ce580fab 1475#if DRM_DEBUG_CODE == 0
7b1f2485 1476static inline void radeon_ring_write(struct radeon_cp *cp, uint32_t v)
771fe6b9 1477{
7b1f2485
CK		 1478 cp->ring[cp->wptr++] = v;
1479 cp->wptr &= cp->ptr_mask;
1480 cp->count_dw--;
1481 cp->ring_free_dw--;
771fe6b9 1482}
ce580fab
AK		 1483#else
1484/* With debugging this is just too big to inline */
7b1f2485 1485void radeon_ring_write(struct radeon_cp *cp, uint32_t v);
ce580fab 1486#endif
771fe6b9
JG		 1487
1488/*
1489 * ASICs macro.
1490 */
068a117c 1491#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 1492#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1493#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1494#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
771fe6b9 1495#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
28d52043 1496#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
7b1f2485 1497#define radeon_gpu_is_lockup(rdev, cp) (rdev)->asic->gpu_is_lockup((rdev), (cp))
a2d07b74 1498#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
771fe6b9
JG		 1499#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1500#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
771fe6b9 1501#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
7b1f2485 1502#define radeon_ring_test(rdev, cp) (rdev)->asic->ring_test((rdev), (cp))
3ce0a23d 1503#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
771fe6b9
JG		 1504#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1505#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
7ed220d7 1506#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
771fe6b9 1507#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
7b1f2485 1508#define radeon_semaphore_ring_emit(rdev, cp, semaphore, emit_wait) (rdev)->asic->semaphore_ring_emit((rdev), (cp), (semaphore), (emit_wait))
771fe6b9
JG		 1509#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1510#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1511#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
7433874e 1512#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
771fe6b9 1513#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
7433874e 1514#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
93e7de7b 1515#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
c836a412 1516#define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
771fe6b9
JG		 1517#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1518#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
e024e110
DA		 1519#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1520#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
c93bb85b 1521#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
429770b3
AD		 1522#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1523#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1524#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1525#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
def9ba9c 1526#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a424816f
AD		 1527#define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1528#define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1529#define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
ce8f5370
AD		 1530#define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1531#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
6f34be50
AD		 1532#define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc))
1533#define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base))
1534#define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc))
771fe6b9 1535
6cf8a3f5 1536/* Common functions */
700a0cc0 1537/* AGP */
90aca4d2 1538extern int radeon_gpu_reset(struct radeon_device *rdev);
700a0cc0 1539extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 1540extern int radeon_modeset_init(struct radeon_device *rdev);
1541extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 1542extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 1543extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 1544extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 1545extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 1546extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 1547extern void radeon_wb_fini(struct radeon_device *rdev);
1548extern int radeon_wb_init(struct radeon_device *rdev);
1549extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 1550extern void radeon_surface_init(struct radeon_device *rdev);
1551extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 1552extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 1553extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 1554extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 1555extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 1556extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1557extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
6a9ee8af
DA		 1558extern int radeon_resume_kms(struct drm_device *dev);
1559extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
53595338 1560extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
6cf8a3f5 1561
16cdf04d
AD		 1562/*
1563 * R600 vram scratch functions
1564 */
1565int r600_vram_scratch_init(struct radeon_device *rdev);
1566void r600_vram_scratch_fini(struct radeon_device *rdev);
1567
3574dda4
DV		 1568/*
1569 * r600 functions used by radeon_encoder.c
1570 */
2cd6218c
RM		 1571extern void r600_hdmi_enable(struct drm_encoder *encoder);
1572extern void r600_hdmi_disable(struct drm_encoder *encoder);
dafc3bd5 1573extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
fe251e2f 1574
0af62b01 1575extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 1576extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 1577
d7a2952f
AM		 1578/* radeon_acpi.c */
1579#if defined(CONFIG_ACPI)
1580extern int radeon_acpi_init(struct radeon_device *rdev);
1581#else
1582static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1583#endif
1584
4c788679
JG		 1585#include "radeon_object.h"
1586
771fe6b9 1587#endif
Linux kernel - Deliverables
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