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Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
a18cee15 96extern int radeon_msi;
3368ff0c 97extern int radeon_lockup_timeout;
a0a53aa8 98extern int radeon_fastfb;
da321c8a 99extern int radeon_dpm;
1294d4a3 100extern int radeon_aspm;
10ebc0bc 101extern int radeon_runtime_pm;
363eb0b4 102extern int radeon_hard_reset;
c1c44132 103extern int radeon_vm_size;
4510fb98 104extern int radeon_vm_block_size;
a624f429 105extern int radeon_deep_color;
771fe6b9
JG		 106
107/*
108 * Copy from radeon_drv.h so we don't have to include both and have conflicting
109 * symbol;
110 */
bb635567
JG		 111#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
112#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 113/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 114#define RADEON_IB_POOL_SIZE 16
115#define RADEON_DEBUGFS_MAX_COMPONENTS 32
116#define RADEONFB_CONN_LIMIT 4
117#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 118
bb635567
JG		 119/* fence seq are set to this number when signaled */
120#define RADEON_FENCE_SIGNALED_SEQ 0LL
1b37078b
AD		 121
122/* internal ring indices */
123/* r1xx+ has gfx CP ring */
d93f7937 124#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 125
126/* cayman has 2 compute CP rings */
d93f7937
CK		 127#define CAYMAN_RING_TYPE_CP1_INDEX 1
128#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 129
4d75658b
AD		 130/* R600+ has an async dma ring */
131#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 132/* cayman add a second async dma ring */
133#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 134
f2ba57b5 135/* R600+ */
d93f7937
CK		 136#define R600_RING_TYPE_UVD_INDEX 5
137
138/* TN+ */
139#define TN_RING_TYPE_VCE1_INDEX 6
140#define TN_RING_TYPE_VCE2_INDEX 7
141
142/* max number of rings */
143#define RADEON_NUM_RINGS 8
f2ba57b5 144
1c61eae4
CK		 145/* number of hw syncs before falling back on blocking */
146#define RADEON_NUM_SYNCS 4
f2ba57b5 147
8f53492f
CK		 148/* number of hw syncs before falling back on blocking */
149#define RADEON_NUM_SYNCS 4
150
721604a1 151/* hardcode those limit for now */
ca19f21e 152#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 153#define RADEON_VA_RESERVED_SIZE (8 << 20)
154#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 155
1a0041b8
AD		 156/* hard reset data */
157#define RADEON_ASIC_RESET_DATA 0x39d5e86b
158
ec46c76d
AD		 159/* reset flags */
160#define RADEON_RESET_GFX (1 << 0)
161#define RADEON_RESET_COMPUTE (1 << 1)
162#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 163#define RADEON_RESET_CP (1 << 3)
164#define RADEON_RESET_GRBM (1 << 4)
165#define RADEON_RESET_DMA1 (1 << 5)
166#define RADEON_RESET_RLC (1 << 6)
167#define RADEON_RESET_SEM (1 << 7)
168#define RADEON_RESET_IH (1 << 8)
169#define RADEON_RESET_VMC (1 << 9)
170#define RADEON_RESET_MC (1 << 10)
171#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 172
22c775ce
AD		 173/* CG block flags */
174#define RADEON_CG_BLOCK_GFX (1 << 0)
175#define RADEON_CG_BLOCK_MC (1 << 1)
176#define RADEON_CG_BLOCK_SDMA (1 << 2)
177#define RADEON_CG_BLOCK_UVD (1 << 3)
178#define RADEON_CG_BLOCK_VCE (1 << 4)
179#define RADEON_CG_BLOCK_HDP (1 << 5)
e16866ec 180#define RADEON_CG_BLOCK_BIF (1 << 6)
22c775ce 181
64d8a728
AD		 182/* CG flags */
183#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
184#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
185#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
186#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
187#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
188#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
189#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
190#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
191#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
192#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
193#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
194#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
195#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
196#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
197#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
198#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
199#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
200
201/* PG flags */
2b19d17f 202#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
64d8a728
AD		 203#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
204#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
205#define RADEON_PG_SUPPORT_UVD (1 << 3)
206#define RADEON_PG_SUPPORT_VCE (1 << 4)
207#define RADEON_PG_SUPPORT_CP (1 << 5)
208#define RADEON_PG_SUPPORT_GDS (1 << 6)
209#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
210#define RADEON_PG_SUPPORT_SDMA (1 << 8)
211#define RADEON_PG_SUPPORT_ACP (1 << 9)
212#define RADEON_PG_SUPPORT_SAMU (1 << 10)
213
9e05fa1d
AD		 214/* max cursor sizes (in pixels) */
215#define CURSOR_WIDTH 64
216#define CURSOR_HEIGHT 64
217
218#define CIK_CURSOR_WIDTH 128
219#define CIK_CURSOR_HEIGHT 128
220
771fe6b9
JG		 221/*
222 * Errata workarounds.
223 */
224enum radeon_pll_errata {
225 CHIP_ERRATA_R300_CG = 0x00000001,
226 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
227 CHIP_ERRATA_PLL_DELAY = 0x00000004
228};
229
230
231struct radeon_device;
232
233
234/*
235 * BIOS.
236 */
237bool radeon_get_bios(struct radeon_device *rdev);
238
239/*
3ce0a23d 240 * Dummy page
771fe6b9 241 */
3ce0a23d
JG		 242struct radeon_dummy_page {
243 struct page *page;
244 dma_addr_t addr;
245};
246int radeon_dummy_page_init(struct radeon_device *rdev);
247void radeon_dummy_page_fini(struct radeon_device *rdev);
248
771fe6b9 249
3ce0a23d
JG		 250/*
251 * Clocks
252 */
771fe6b9
JG		 253struct radeon_clock {
254 struct radeon_pll p1pll;
255 struct radeon_pll p2pll;
bcc1c2a1 256 struct radeon_pll dcpll;
771fe6b9
JG		 257 struct radeon_pll spll;
258 struct radeon_pll mpll;
259 /* 10 Khz units */
260 uint32_t default_mclk;
261 uint32_t default_sclk;
bcc1c2a1 262 uint32_t default_dispclk;
4489cd62 263 uint32_t current_dispclk;
bcc1c2a1 264 uint32_t dp_extclk;
b20f9bef 265 uint32_t max_pixel_clock;
771fe6b9
JG		 266};
267
7433874e
RM		 268/*
269 * Power management
270 */
271int radeon_pm_init(struct radeon_device *rdev);
914a8987 272int radeon_pm_late_init(struct radeon_device *rdev);
29fb52ca 273void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 274void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 275void radeon_pm_suspend(struct radeon_device *rdev);
276void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 277void radeon_combios_get_power_modes(struct radeon_device *rdev);
278void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 279int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
280 u8 clock_type,
281 u32 clock,
282 bool strobe_mode,
283 struct atom_clock_dividers *dividers);
eaa778af
AD		 284int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
285 u32 clock,
286 bool strobe_mode,
287 struct atom_mpll_param *mpll_param);
8a83ec5e 288void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 289int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
290 u16 voltage_level, u8 voltage_type,
291 u32 *gpio_value, u32 *gpio_mask);
292void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
293 u32 eng_clock, u32 mem_clock);
294int radeon_atom_get_voltage_step(struct radeon_device *rdev,
295 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 296int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
297 u16 voltage_id, u16 *voltage);
beb79f40
AD		 298int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
299 u16 *voltage,
300 u16 leakage_idx);
cc8dbbb4
AD		 301int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
302 u16 *leakage_id);
303int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
304 u16 *vddc, u16 *vddci,
305 u16 virtual_voltage_id,
306 u16 vbios_voltage_id);
ae5b0abb
AD		 307int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
308 u8 voltage_type,
309 u16 nominal_voltage,
310 u16 *true_voltage);
311int radeon_atom_get_min_voltage(struct radeon_device *rdev,
312 u8 voltage_type, u16 *min_voltage);
313int radeon_atom_get_max_voltage(struct radeon_device *rdev,
314 u8 voltage_type, u16 *max_voltage);
315int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 316 u8 voltage_type, u8 voltage_mode,
ae5b0abb 317 struct atom_voltage_table *voltage_table);
58653abd
AD		 318bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
319 u8 voltage_type, u8 voltage_mode);
ae5b0abb
AD		 320void radeon_atom_update_memory_dll(struct radeon_device *rdev,
321 u32 mem_clock);
322void radeon_atom_set_ac_timing(struct radeon_device *rdev,
323 u32 mem_clock);
324int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
325 u8 module_index,
326 struct atom_mc_reg_table *reg_table);
327int radeon_atom_get_memory_info(struct radeon_device *rdev,
328 u8 module_index, struct atom_memory_info *mem_info);
329int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
330 bool gddr5, u8 module_index,
331 struct atom_memory_clock_range_table *mclk_range_table);
332int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
333 u16 voltage_id, u16 *voltage);
f892034a 334void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 335extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
336 unsigned *bankh, unsigned *mtaspect,
337 unsigned *tile_split);
3ce0a23d 338
771fe6b9
JG		 339/*
340 * Fences.
341 */
342struct radeon_fence_driver {
343 uint32_t scratch_reg;
30eb77f4
JG		 344 uint64_t gpu_addr;
345 volatile uint32_t *cpu_addr;
68e250b7
CK		 346 /* sync_seq is protected by ring emission lock */
347 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 348 atomic64_t last_seq;
0a0c7596 349 bool initialized;
771fe6b9
JG		 350};
351
352struct radeon_fence {
353 struct radeon_device *rdev;
354 struct kref kref;
771fe6b9 355 /* protected by radeon_fence.lock */
bb635567 356 uint64_t seq;
7465280c 357 /* RB, DMA, etc. */
bb635567 358 unsigned ring;
771fe6b9
JG		 359};
360
30eb77f4
JG		 361int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
362int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 363void radeon_fence_driver_fini(struct radeon_device *rdev);
76903b96 364void radeon_fence_driver_force_completion(struct radeon_device *rdev);
876dc9f3 365int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 366void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 367bool radeon_fence_signaled(struct radeon_fence *fence);
368int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
37615527
CK		 369int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
370int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
0085c950
JG		 371int radeon_fence_wait_any(struct radeon_device *rdev,
372 struct radeon_fence **fences,
373 bool intr);
771fe6b9
JG		 374struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
375void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 376unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 377bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
378void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
379static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
380 struct radeon_fence *b)
381{
382 if (!a) {
383 return b;
384 }
385
386 if (!b) {
387 return a;
388 }
389
390 BUG_ON(a->ring != b->ring);
391
392 if (a->seq > b->seq) {
393 return a;
394 } else {
395 return b;
396 }
397}
771fe6b9 398
ee60e29f
CK		 399static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
400 struct radeon_fence *b)
401{
402 if (!a) {
403 return false;
404 }
405
406 if (!b) {
407 return true;
408 }
409
410 BUG_ON(a->ring != b->ring);
411
412 return a->seq < b->seq;
413}
414
e024e110
DA		 415/*
416 * Tiling registers
417 */
418struct radeon_surface_reg {
4c788679 419 struct radeon_bo *bo;
e024e110
DA		 420};
421
422#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 423
424/*
4c788679 425 * TTM.
771fe6b9 426 */
4c788679
JG		 427struct radeon_mman {
428 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 429 struct drm_global_reference mem_global_ref;
4c788679 430 struct ttm_bo_device bdev;
0a0c7596
JG		 431 bool mem_global_referenced;
432 bool initialized;
2014b569
CK		 433
434#if defined(CONFIG_DEBUG_FS)
435 struct dentry *vram;
dd66d20e 436 struct dentry *gtt;
2014b569 437#endif
4c788679
JG		 438};
439
721604a1
JG		 440/* bo virtual address in a specific vm */
441struct radeon_bo_va {
e971bd5e 442 /* protected by bo being reserved */
721604a1 443 struct list_head bo_list;
721604a1
JG		 444 uint64_t soffset;
445 uint64_t eoffset;
446 uint32_t flags;
447 bool valid;
e971bd5e
CK		 448 unsigned ref_count;
449
450 /* protected by vm mutex */
451 struct list_head vm_list;
452
453 /* constant after initialization */
454 struct radeon_vm *vm;
455 struct radeon_bo *bo;
721604a1
JG		 456};
457
4c788679
JG		 458struct radeon_bo {
459 /* Protected by gem.mutex */
460 struct list_head list;
461 /* Protected by tbo.reserved */
bda72d58 462 u32 initial_domain;
312ea8da
JG		 463 u32 placements[3];
464 struct ttm_placement placement;
4c788679
JG		 465 struct ttm_buffer_object tbo;
466 struct ttm_bo_kmap_obj kmap;
467 unsigned pin_count;
468 void *kptr;
469 u32 tiling_flags;
470 u32 pitch;
471 int surface_reg;
721604a1
JG		 472 /* list of all virtual address to which this bo
473 * is associated to
474 */
475 struct list_head va;
4c788679
JG		 476 /* Constant after initialization */
477 struct radeon_device *rdev;
441921d5 478 struct drm_gem_object gem_base;
63bc620b 479
409851f4
JG		 480 struct ttm_bo_kmap_obj dma_buf_vmap;
481 pid_t pid;
4c788679 482};
7e4d15d9 483#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 484
409851f4
JG		 485int radeon_gem_debugfs_init(struct radeon_device *rdev);
486
b15ba512
JG		 487/* sub-allocation manager, it has to be protected by another lock.
488 * By conception this is an helper for other part of the driver
489 * like the indirect buffer or semaphore, which both have their
490 * locking.
491 *
492 * Principe is simple, we keep a list of sub allocation in offset
493 * order (first entry has offset == 0, last entry has the highest
494 * offset).
495 *
496 * When allocating new object we first check if there is room at
497 * the end total_size - (last_object_offset + last_object_size) >=
498 * alloc_size. If so we allocate new object there.
499 *
500 * When there is not enough room at the end, we start waiting for
501 * each sub object until we reach object_offset+object_size >=
502 * alloc_size, this object then become the sub object we return.
503 *
504 * Alignment can't be bigger than page size.
505 *
506 * Hole are not considered for allocation to keep things simple.
507 * Assumption is that there won't be hole (all object on same
508 * alignment).
509 */
510struct radeon_sa_manager {
bfb38d35 511 wait_queue_head_t wq;
b15ba512 512 struct radeon_bo *bo;
c3b7fe8b
CK		 513 struct list_head *hole;
514 struct list_head flist[RADEON_NUM_RINGS];
515 struct list_head olist;
b15ba512
JG		 516 unsigned size;
517 uint64_t gpu_addr;
518 void *cpu_ptr;
519 uint32_t domain;
6c4f978b 520 uint32_t align;
b15ba512
JG		 521};
522
523struct radeon_sa_bo;
524
525/* sub-allocation buffer */
526struct radeon_sa_bo {
c3b7fe8b
CK		 527 struct list_head olist;
528 struct list_head flist;
b15ba512 529 struct radeon_sa_manager *manager;
e6661a96
CK		 530 unsigned soffset;
531 unsigned eoffset;
557017a0 532 struct radeon_fence *fence;
b15ba512
JG		 533};
534
771fe6b9
JG		 535/*
536 * GEM objects.
537 */
538struct radeon_gem {
4c788679 539 struct mutex mutex;
771fe6b9
JG		 540 struct list_head objects;
541};
542
543int radeon_gem_init(struct radeon_device *rdev);
544void radeon_gem_fini(struct radeon_device *rdev);
545int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 546 int alignment, int initial_domain,
547 bool discardable, bool kernel,
548 struct drm_gem_object **obj);
771fe6b9 549
ff72145b
DA		 550int radeon_mode_dumb_create(struct drm_file *file_priv,
551 struct drm_device *dev,
552 struct drm_mode_create_dumb *args);
553int radeon_mode_dumb_mmap(struct drm_file *filp,
554 struct drm_device *dev,
555 uint32_t handle, uint64_t *offset_p);
771fe6b9 556
c1341e52
JG		 557/*
558 * Semaphores.
559 */
c1341e52 560struct radeon_semaphore {
a8c05940
JG		 561 struct radeon_sa_bo *sa_bo;
562 signed waiters;
c1341e52 563 uint64_t gpu_addr;
1654b817 564 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
c1341e52
JG		 565};
566
c1341e52
JG		 567int radeon_semaphore_create(struct radeon_device *rdev,
568 struct radeon_semaphore **semaphore);
1654b817 569bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
c1341e52 570 struct radeon_semaphore *semaphore);
1654b817 571bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
c1341e52 572 struct radeon_semaphore *semaphore);
1654b817
CK		 573void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
574 struct radeon_fence *fence);
8f676c4c
CK		 575int radeon_semaphore_sync_rings(struct radeon_device *rdev,
576 struct radeon_semaphore *semaphore,
1654b817 577 int waiting_ring);
c1341e52 578void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 579 struct radeon_semaphore **semaphore,
a8c05940 580 struct radeon_fence *fence);
c1341e52 581
771fe6b9
JG		 582/*
583 * GART structures, functions & helpers
584 */
585struct radeon_mc;
586
a77f1718 587#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 588#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 589#define RADEON_GPU_PAGE_SHIFT 12
721604a1 590#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 591
771fe6b9
JG		 592struct radeon_gart {
593 dma_addr_t table_addr;
c9a1be96
JG		 594 struct radeon_bo *robj;
595 void *ptr;
771fe6b9
JG		 596 unsigned num_gpu_pages;
597 unsigned num_cpu_pages;
598 unsigned table_size;
771fe6b9
JG		 599 struct page **pages;
600 dma_addr_t *pages_addr;
601 bool ready;
602};
603
604int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
605void radeon_gart_table_ram_free(struct radeon_device *rdev);
606int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
607void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 608int radeon_gart_table_vram_pin(struct radeon_device *rdev);
609void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 610int radeon_gart_init(struct radeon_device *rdev);
611void radeon_gart_fini(struct radeon_device *rdev);
612void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
613 int pages);
614int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516
KRW		 615 int pages, struct page **pagelist,
616 dma_addr_t *dma_addr);
c9a1be96 617void radeon_gart_restore(struct radeon_device *rdev);
771fe6b9
JG		 618
619
620/*
621 * GPU MC structures, functions & helpers
622 */
623struct radeon_mc {
624 resource_size_t aper_size;
625 resource_size_t aper_base;
626 resource_size_t agp_base;
7a50f01a
DA		 627 /* for some chips with <= 32MB we need to lie
628 * about vram size near mc fb location */
3ce0a23d 629 u64 mc_vram_size;
d594e46a 630 u64 visible_vram_size;
3ce0a23d
JG		 631 u64 gtt_size;
632 u64 gtt_start;
633 u64 gtt_end;
3ce0a23d
JG		 634 u64 vram_start;
635 u64 vram_end;
771fe6b9 636 unsigned vram_width;
3ce0a23d 637 u64 real_vram_size;
771fe6b9
JG		 638 int vram_mtrr;
639 bool vram_is_ddr;
d594e46a 640 bool igp_sideport_enabled;
8d369bb1 641 u64 gtt_base_align;
9ed8b1f9 642 u64 mc_mask;
771fe6b9
JG		 643};
644
06b6476d
AD		 645bool radeon_combios_sideport_present(struct radeon_device *rdev);
646bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 647
648/*
649 * GPU scratch registers structures, functions & helpers
650 */
651struct radeon_scratch {
652 unsigned num_reg;
724c80e1 653 uint32_t reg_base;
771fe6b9
JG		 654 bool free[32];
655 uint32_t reg[32];
656};
657
658int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
659void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
660
75efdee1
AD		 661/*
662 * GPU doorbell structures, functions & helpers
663 */
d5754ab8
AL		 664#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
665
75efdee1 666struct radeon_doorbell {
75efdee1 667 /* doorbell mmio */
d5754ab8
AL		 668 resource_size_t base;
669 resource_size_t size;
670 u32 __iomem *ptr;
671 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
672 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
75efdee1
AD		 673};
674
675int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
676void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771fe6b9
JG		 677
678/*
679 * IRQS.
680 */
6f34be50 681
fa7f517c
CK		 682struct radeon_flip_work {
683 struct work_struct flip_work;
684 struct work_struct unpin_work;
685 struct radeon_device *rdev;
686 int crtc_id;
c60381bd 687 uint64_t base;
6f34be50 688 struct drm_pending_vblank_event *event;
fa7f517c 689 struct radeon_bo *old_rbo;
fa7f517c 690 struct radeon_fence *fence;
6f34be50
AD		 691};
692
693struct r500_irq_stat_regs {
694 u32 disp_int;
f122c610 695 u32 hdmi0_status;
6f34be50
AD		 696};
697
698struct r600_irq_stat_regs {
699 u32 disp_int;
700 u32 disp_int_cont;
701 u32 disp_int_cont2;
702 u32 d1grph_int;
703 u32 d2grph_int;
f122c610
AD		 704 u32 hdmi0_status;
705 u32 hdmi1_status;
6f34be50
AD		 706};
707
708struct evergreen_irq_stat_regs {
709 u32 disp_int;
710 u32 disp_int_cont;
711 u32 disp_int_cont2;
712 u32 disp_int_cont3;
713 u32 disp_int_cont4;
714 u32 disp_int_cont5;
715 u32 d1grph_int;
716 u32 d2grph_int;
717 u32 d3grph_int;
718 u32 d4grph_int;
719 u32 d5grph_int;
720 u32 d6grph_int;
f122c610
AD		 721 u32 afmt_status1;
722 u32 afmt_status2;
723 u32 afmt_status3;
724 u32 afmt_status4;
725 u32 afmt_status5;
726 u32 afmt_status6;
6f34be50
AD		 727};
728
a59781bb
AD		 729struct cik_irq_stat_regs {
730 u32 disp_int;
731 u32 disp_int_cont;
732 u32 disp_int_cont2;
733 u32 disp_int_cont3;
734 u32 disp_int_cont4;
735 u32 disp_int_cont5;
736 u32 disp_int_cont6;
f5d636d2
CK		 737 u32 d1grph_int;
738 u32 d2grph_int;
739 u32 d3grph_int;
740 u32 d4grph_int;
741 u32 d5grph_int;
742 u32 d6grph_int;
a59781bb
AD		 743};
744
6f34be50
AD		 745union radeon_irq_stat_regs {
746 struct r500_irq_stat_regs r500;
747 struct r600_irq_stat_regs r600;
748 struct evergreen_irq_stat_regs evergreen;
a59781bb 749 struct cik_irq_stat_regs cik;
6f34be50
AD		 750};
751
771fe6b9 752struct radeon_irq {
fb98257a
CK		 753 bool installed;
754 spinlock_t lock;
736fc37f 755 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 756 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 757 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 758 wait_queue_head_t vblank_queue;
759 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 760 bool afmt[RADEON_MAX_AFMT_BLOCKS];
761 union radeon_irq_stat_regs stat_regs;
4a6369e9 762 bool dpm_thermal;
771fe6b9
JG		 763};
764
765int radeon_irq_kms_init(struct radeon_device *rdev);
766void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b
AD		 767void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
768void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 769void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
770void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 771void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
772void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
773void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
774void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 775
776/*
e32eb50d 777 * CP & rings.
771fe6b9 778 */
7465280c 779
771fe6b9 780struct radeon_ib {
68470ae7
JG		 781 struct radeon_sa_bo *sa_bo;
782 uint32_t length_dw;
783 uint64_t gpu_addr;
784 uint32_t *ptr;
876dc9f3 785 int ring;
68470ae7 786 struct radeon_fence *fence;
4bf3dd92 787 struct radeon_vm *vm;
68470ae7
JG		 788 bool is_const_ib;
789 struct radeon_semaphore *semaphore;
771fe6b9
JG		 790};
791
e32eb50d 792struct radeon_ring {
4c788679 793 struct radeon_bo *ring_obj;
771fe6b9 794 volatile uint32_t *ring;
5596a9db 795 unsigned rptr_offs;
45df6803 796 unsigned rptr_save_reg;
89d35807
AD		 797 u64 next_rptr_gpu_addr;
798 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 799 unsigned wptr;
800 unsigned wptr_old;
801 unsigned ring_size;
802 unsigned ring_free_dw;
803 int count_dw;
aee4aa73
CK		 804 atomic_t last_rptr;
805 atomic64_t last_activity;
771fe6b9
JG		 806 uint64_t gpu_addr;
807 uint32_t align_mask;
808 uint32_t ptr_mask;
771fe6b9 809 bool ready;
78c5560a 810 u32 nop;
8b25ed34 811 u32 idx;
5f0839c1
JG		 812 u64 last_semaphore_signal_addr;
813 u64 last_semaphore_wait_addr;
963e81f9
AD		 814 /* for CIK queues */
815 u32 me;
816 u32 pipe;
817 u32 queue;
818 struct radeon_bo *mqd_obj;
d5754ab8 819 u32 doorbell_index;
963e81f9
AD		 820 unsigned wptr_offs;
821};
822
823struct radeon_mec {
824 struct radeon_bo *hpd_eop_obj;
825 u64 hpd_eop_gpu_addr;
826 u32 num_pipe;
827 u32 num_mec;
828 u32 num_queue;
771fe6b9
JG		 829};
830
721604a1
JG		 831/*
832 * VM
833 */
ee60e29f 834
fa87e62d 835/* maximum number of VMIDs */
ee60e29f
CK		 836#define RADEON_NUM_VM 16
837
fa87e62d 838/* number of entries in page table */
4510fb98 839#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
fa87e62d 840
1c01103c
AD		 841/* PTBs (Page Table Blocks) need to be aligned to 32K */
842#define RADEON_VM_PTB_ALIGN_SIZE 32768
843#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
844#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
845
24c16439
CK		 846#define R600_PTE_VALID (1 << 0)
847#define R600_PTE_SYSTEM (1 << 1)
848#define R600_PTE_SNOOPED (1 << 2)
849#define R600_PTE_READABLE (1 << 5)
850#define R600_PTE_WRITEABLE (1 << 6)
851
ec3dbbcb
CK		 852/* PTE (Page Table Entry) fragment field for different page sizes */
853#define R600_PTE_FRAG_4KB (0 << 7)
854#define R600_PTE_FRAG_64KB (4 << 7)
855#define R600_PTE_FRAG_256KB (6 << 7)
856
0e97703c
CK		 857/* flags used for GART page table entries on R600+ */
858#define R600_PTE_GART ( R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED \
859 | R600_PTE_READABLE | R600_PTE_WRITEABLE)
860
6d2f2944
CK		 861struct radeon_vm_pt {
862 struct radeon_bo *bo;
863 uint64_t addr;
864};
865
721604a1 866struct radeon_vm {
721604a1 867 struct list_head va;
ee60e29f 868 unsigned id;
90a51a32
CK		 869
870 /* contains the page directory */
6d2f2944 871 struct radeon_bo *page_directory;
90a51a32 872 uint64_t pd_gpu_addr;
6d2f2944 873 unsigned max_pde_used;
90a51a32
CK		 874
875 /* array of page tables, one for each page directory entry */
6d2f2944 876 struct radeon_vm_pt *page_tables;
90a51a32 877
721604a1
JG		 878 struct mutex mutex;
879 /* last fence for cs using this vm */
880 struct radeon_fence *fence;
9b40e5d8
CK		 881 /* last flush or NULL if we still need to flush */
882 struct radeon_fence *last_flush;
593b2635
CK		 883 /* last use of vmid */
884 struct radeon_fence *last_id_use;
721604a1
JG		 885};
886
721604a1 887struct radeon_vm_manager {
ee60e29f 888 struct radeon_fence *active[RADEON_NUM_VM];
721604a1 889 uint32_t max_pfn;
721604a1
JG		 890 /* number of VMIDs */
891 unsigned nvm;
892 /* vram base address for page table entry */
893 u64 vram_base_offset;
67e915e4
AD		 894 /* is vm enabled? */
895 bool enabled;
721604a1
JG		 896};
897
898/*
899 * file private structure
900 */
901struct radeon_fpriv {
902 struct radeon_vm vm;
903};
904
d8f60cfc
AD		 905/*
906 * R6xx+ IH ring
907 */
908struct r600_ih {
4c788679 909 struct radeon_bo *ring_obj;
d8f60cfc
AD		 910 volatile uint32_t *ring;
911 unsigned rptr;
d8f60cfc
AD		 912 unsigned ring_size;
913 uint64_t gpu_addr;
d8f60cfc 914 uint32_t ptr_mask;
c20dc369 915 atomic_t lock;
d8f60cfc
AD		 916 bool enabled;
917};
918
347e7592 919/*
2948f5e6 920 * RLC stuff
347e7592 921 */
2948f5e6
AD		 922#include "clearstate_defs.h"
923
924struct radeon_rlc {
347e7592
AD		 925 /* for power gating */
926 struct radeon_bo *save_restore_obj;
927 uint64_t save_restore_gpu_addr;
2948f5e6 928 volatile uint32_t *sr_ptr;
1fd11777 929 const u32 *reg_list;
2948f5e6 930 u32 reg_list_size;
347e7592
AD		 931 /* for clear state */
932 struct radeon_bo *clear_state_obj;
933 uint64_t clear_state_gpu_addr;
2948f5e6 934 volatile uint32_t *cs_ptr;
1fd11777 935 const struct cs_section_def *cs_data;
22c775ce
AD		 936 u32 clear_state_size;
937 /* for cp tables */
938 struct radeon_bo *cp_table_obj;
939 uint64_t cp_table_gpu_addr;
940 volatile uint32_t *cp_table_ptr;
941 u32 cp_table_size;
347e7592
AD		 942};
943
69e130a6 944int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 945 struct radeon_ib *ib, struct radeon_vm *vm,
946 unsigned size);
f2e39221 947void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
4ef72566
CK		 948int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
949 struct radeon_ib *const_ib);
771fe6b9
JG		 950int radeon_ib_pool_init(struct radeon_device *rdev);
951void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 952int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 953/* Ring access between begin & end cannot sleep */
89d35807
AD		 954bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
955 struct radeon_ring *ring);
e32eb50d
CK		 956void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
957int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
958int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
959void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
960void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
d6999bc7 961void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 962void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
963int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
ff212f25
CK		 964void radeon_ring_lockup_update(struct radeon_device *rdev,
965 struct radeon_ring *ring);
069211e5 966bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 967unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
968 uint32_t **data);
969int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
970 unsigned size, uint32_t *data);
e32eb50d 971int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
ea31bf69 972 unsigned rptr_offs, u32 nop);
e32eb50d 973void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 974
975
4d75658b
AD		 976/* r600 async dma */
977void r600_dma_stop(struct radeon_device *rdev);
978int r600_dma_resume(struct radeon_device *rdev);
979void r600_dma_fini(struct radeon_device *rdev);
980
8c5fd7ef
AD		 981void cayman_dma_stop(struct radeon_device *rdev);
982int cayman_dma_resume(struct radeon_device *rdev);
983void cayman_dma_fini(struct radeon_device *rdev);
984
771fe6b9
JG		 985/*
986 * CS.
987 */
988struct radeon_cs_reloc {
989 struct drm_gem_object *gobj;
4c788679 990 struct radeon_bo *robj;
df0af440
CK		 991 struct ttm_validate_buffer tv;
992 uint64_t gpu_offset;
ce6758c8
CK		 993 unsigned prefered_domains;
994 unsigned allowed_domains;
df0af440 995 uint32_t tiling_flags;
771fe6b9 996 uint32_t handle;
771fe6b9
JG		 997};
998
999struct radeon_cs_chunk {
1000 uint32_t chunk_id;
1001 uint32_t length_dw;
1002 uint32_t *kdata;
721604a1 1003 void __user *user_ptr;
771fe6b9
JG		 1004};
1005
1006struct radeon_cs_parser {
c8c15ff1 1007 struct device *dev;
771fe6b9
JG		 1008 struct radeon_device *rdev;
1009 struct drm_file *filp;
1010 /* chunks */
1011 unsigned nchunks;
1012 struct radeon_cs_chunk *chunks;
1013 uint64_t *chunks_array;
1014 /* IB */
1015 unsigned idx;
1016 /* relocations */
1017 unsigned nrelocs;
1018 struct radeon_cs_reloc *relocs;
1019 struct radeon_cs_reloc **relocs_ptr;
df0af440 1020 struct radeon_cs_reloc *vm_bos;
771fe6b9 1021 struct list_head validated;
cf4ccd01 1022 unsigned dma_reloc_idx;
771fe6b9
JG		 1023 /* indices of various chunks */
1024 int chunk_ib_idx;
1025 int chunk_relocs_idx;
721604a1 1026 int chunk_flags_idx;
dfcf5f36 1027 int chunk_const_ib_idx;
f2e39221
JG		 1028 struct radeon_ib ib;
1029 struct radeon_ib const_ib;
771fe6b9 1030 void *track;
3ce0a23d 1031 unsigned family;
e70f224c 1032 int parser_error;
721604a1
JG		 1033 u32 cs_flags;
1034 u32 ring;
1035 s32 priority;
ecff665f 1036 struct ww_acquire_ctx ticket;
771fe6b9
JG		 1037};
1038
28a326c5
ML		 1039static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1040{
1041 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1042
1043 if (ibc->kdata)
1044 return ibc->kdata[idx];
1045 return p->ib.ptr[idx];
1046}
1047
513bcb46 1048
771fe6b9
JG		 1049struct radeon_cs_packet {
1050 unsigned idx;
1051 unsigned type;
1052 unsigned reg;
1053 unsigned opcode;
1054 int count;
1055 unsigned one_reg_wr;
1056};
1057
1058typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1059 struct radeon_cs_packet *pkt,
1060 unsigned idx, unsigned reg);
1061typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1062 struct radeon_cs_packet *pkt);
1063
1064
1065/*
1066 * AGP
1067 */
1068int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1069void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1070void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1071void radeon_agp_fini(struct radeon_device *rdev);
1072
1073
1074/*
1075 * Writeback
1076 */
1077struct radeon_wb {
4c788679 1078 struct radeon_bo *wb_obj;
771fe6b9
JG		 1079 volatile uint32_t *wb;
1080 uint64_t gpu_addr;
724c80e1 1081 bool enabled;
d0f8a854 1082 bool use_event;
771fe6b9
JG		 1083};
1084
724c80e1 1085#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1086#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1087#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1088#define RADEON_WB_CP1_RPTR_OFFSET 1280
1089#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1090#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1091#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1092#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1093#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1094#define CIK_WB_CP1_WPTR_OFFSET 3328
1095#define CIK_WB_CP2_WPTR_OFFSET 3584
724c80e1 1096
c93bb85b
JG		 1097/**
1098 * struct radeon_pm - power management datas
1099 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1100 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1101 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1102 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1103 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1104 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1105 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1106 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1107 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1108 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1109 * @needed_bandwidth: current bandwidth needs
1110 *
1111 * It keeps track of various data needed to take powermanagement decision.
25985edc 1112 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1113 * Equation between gpu/memory clock and available bandwidth is hw dependent
1114 * (type of memory, bus size, efficiency, ...)
1115 */
ce8f5370
AD		 1116
1117enum radeon_pm_method {
1118 PM_METHOD_PROFILE,
1119 PM_METHOD_DYNPM,
da321c8a 1120 PM_METHOD_DPM,
ce8f5370
AD		 1121};
1122
1123enum radeon_dynpm_state {
1124 DYNPM_STATE_DISABLED,
1125 DYNPM_STATE_MINIMUM,
1126 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1127 DYNPM_STATE_ACTIVE,
1128 DYNPM_STATE_SUSPENDED,
c913e23a 1129};
ce8f5370
AD		 1130enum radeon_dynpm_action {
1131 DYNPM_ACTION_NONE,
1132 DYNPM_ACTION_MINIMUM,
1133 DYNPM_ACTION_DOWNCLOCK,
1134 DYNPM_ACTION_UPCLOCK,
1135 DYNPM_ACTION_DEFAULT
c913e23a 1136};
56278a8e
AD		 1137
1138enum radeon_voltage_type {
1139 VOLTAGE_NONE = 0,
1140 VOLTAGE_GPIO,
1141 VOLTAGE_VDDC,
1142 VOLTAGE_SW
1143};
1144
0ec0e74f 1145enum radeon_pm_state_type {
da321c8a 1146 /* not used for dpm */
0ec0e74f
AD		 1147 POWER_STATE_TYPE_DEFAULT,
1148 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1149 /* user selectable states */
0ec0e74f
AD		 1150 POWER_STATE_TYPE_BATTERY,
1151 POWER_STATE_TYPE_BALANCED,
1152 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1153 /* internal states */
1154 POWER_STATE_TYPE_INTERNAL_UVD,
1155 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1156 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1157 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1158 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1159 POWER_STATE_TYPE_INTERNAL_BOOT,
1160 POWER_STATE_TYPE_INTERNAL_THERMAL,
1161 POWER_STATE_TYPE_INTERNAL_ACPI,
1162 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1163 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1164};
1165
ce8f5370
AD		 1166enum radeon_pm_profile_type {
1167 PM_PROFILE_DEFAULT,
1168 PM_PROFILE_AUTO,
1169 PM_PROFILE_LOW,
c9e75b21 1170 PM_PROFILE_MID,
ce8f5370
AD		 1171 PM_PROFILE_HIGH,
1172};
1173
1174#define PM_PROFILE_DEFAULT_IDX 0
1175#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1176#define PM_PROFILE_MID_SH_IDX 2
1177#define PM_PROFILE_HIGH_SH_IDX 3
1178#define PM_PROFILE_LOW_MH_IDX 4
1179#define PM_PROFILE_MID_MH_IDX 5
1180#define PM_PROFILE_HIGH_MH_IDX 6
1181#define PM_PROFILE_MAX 7
ce8f5370
AD		 1182
1183struct radeon_pm_profile {
1184 int dpms_off_ps_idx;
1185 int dpms_on_ps_idx;
1186 int dpms_off_cm_idx;
1187 int dpms_on_cm_idx;
516d0e46
AD		 1188};
1189
21a8122a
AD		 1190enum radeon_int_thermal_type {
1191 THERMAL_TYPE_NONE,
da321c8a
AD		 1192 THERMAL_TYPE_EXTERNAL,
1193 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1194 THERMAL_TYPE_RV6XX,
1195 THERMAL_TYPE_RV770,
da321c8a 1196 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1197 THERMAL_TYPE_EVERGREEN,
e33df25f 1198 THERMAL_TYPE_SUMO,
4fddba1f 1199 THERMAL_TYPE_NI,
14607d08 1200 THERMAL_TYPE_SI,
da321c8a 1201 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1202 THERMAL_TYPE_CI,
16fbe00d 1203 THERMAL_TYPE_KV,
21a8122a
AD		 1204};
1205
56278a8e
AD		 1206struct radeon_voltage {
1207 enum radeon_voltage_type type;
1208 /* gpio voltage */
1209 struct radeon_gpio_rec gpio;
1210 u32 delay; /* delay in usec from voltage drop to sclk change */
1211 bool active_high; /* voltage drop is active when bit is high */
1212 /* VDDC voltage */
1213 u8 vddc_id; /* index into vddc voltage table */
1214 u8 vddci_id; /* index into vddci voltage table */
1215 bool vddci_enabled;
1216 /* r6xx+ sw */
2feea49a
AD		 1217 u16 voltage;
1218 /* evergreen+ vddci */
1219 u16 vddci;
56278a8e
AD		 1220};
1221
d7311171
AD		 1222/* clock mode flags */
1223#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1224
56278a8e
AD		 1225struct radeon_pm_clock_info {
1226 /* memory clock */
1227 u32 mclk;
1228 /* engine clock */
1229 u32 sclk;
1230 /* voltage info */
1231 struct radeon_voltage voltage;
d7311171 1232 /* standardized clock flags */
56278a8e
AD		 1233 u32 flags;
1234};
1235
a48b9b4e 1236/* state flags */
d7311171 1237#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1238
56278a8e 1239struct radeon_power_state {
0ec0e74f 1240 enum radeon_pm_state_type type;
8f3f1c9a 1241 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1242 /* number of valid clock modes in this power state */
1243 int num_clock_modes;
56278a8e 1244 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1245 /* standardized state flags */
1246 u32 flags;
79daedc9
AD		 1247 u32 misc; /* vbios specific flags */
1248 u32 misc2; /* vbios specific flags */
1249 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1250};
1251
27459324
RM		 1252/*
1253 * Some modes are overclocked by very low value, accept them
1254 */
1255#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1256
2e9d4c05
AD		 1257enum radeon_dpm_auto_throttle_src {
1258 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1259 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1260};
1261
1262enum radeon_dpm_event_src {
1263 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1264 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1265 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1266 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1267 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1268};
1269
58bd2a88
AD		 1270#define RADEON_MAX_VCE_LEVELS 6
1271
b62d628b
AD		 1272enum radeon_vce_level {
1273 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1274 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1275 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1276 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1277 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1278 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1279};
1280
da321c8a
AD		 1281struct radeon_ps {
1282 u32 caps; /* vbios flags */
1283 u32 class; /* vbios flags */
1284 u32 class2; /* vbios flags */
1285 /* UVD clocks */
1286 u32 vclk;
1287 u32 dclk;
c4453e66
AD		 1288 /* VCE clocks */
1289 u32 evclk;
1290 u32 ecclk;
b62d628b
AD		 1291 bool vce_active;
1292 enum radeon_vce_level vce_level;
da321c8a
AD		 1293 /* asic priv */
1294 void *ps_priv;
1295};
1296
1297struct radeon_dpm_thermal {
1298 /* thermal interrupt work */
1299 struct work_struct work;
1300 /* low temperature threshold */
1301 int min_temp;
1302 /* high temperature threshold */
1303 int max_temp;
1304 /* was interrupt low to high or high to low */
1305 bool high_to_low;
1306};
1307
d22b7e40
AD		 1308enum radeon_clk_action
1309{
1310 RADEON_SCLK_UP = 1,
1311 RADEON_SCLK_DOWN
1312};
1313
1314struct radeon_blacklist_clocks
1315{
1316 u32 sclk;
1317 u32 mclk;
1318 enum radeon_clk_action action;
1319};
1320
61b7d601
AD		 1321struct radeon_clock_and_voltage_limits {
1322 u32 sclk;
1323 u32 mclk;
cdf6e805
AD		 1324 u16 vddc;
1325 u16 vddci;
61b7d601
AD		 1326};
1327
1328struct radeon_clock_array {
1329 u32 count;
1330 u32 *values;
1331};
1332
1333struct radeon_clock_voltage_dependency_entry {
1334 u32 clk;
1335 u16 v;
1336};
1337
1338struct radeon_clock_voltage_dependency_table {
1339 u32 count;
1340 struct radeon_clock_voltage_dependency_entry *entries;
1341};
1342
ef976ec4
AD		 1343union radeon_cac_leakage_entry {
1344 struct {
1345 u16 vddc;
1346 u32 leakage;
1347 };
1348 struct {
1349 u16 vddc1;
1350 u16 vddc2;
1351 u16 vddc3;
1352 };
61b7d601
AD		 1353};
1354
1355struct radeon_cac_leakage_table {
1356 u32 count;
ef976ec4 1357 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1358};
1359
929ee7a8
AD		 1360struct radeon_phase_shedding_limits_entry {
1361 u16 voltage;
1362 u32 sclk;
1363 u32 mclk;
1364};
1365
1366struct radeon_phase_shedding_limits_table {
1367 u32 count;
1368 struct radeon_phase_shedding_limits_entry *entries;
1369};
1370
84a9d9ee
AD		 1371struct radeon_uvd_clock_voltage_dependency_entry {
1372 u32 vclk;
1373 u32 dclk;
1374 u16 v;
1375};
1376
1377struct radeon_uvd_clock_voltage_dependency_table {
1378 u8 count;
1379 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1380};
1381
d29f013b
AD		 1382struct radeon_vce_clock_voltage_dependency_entry {
1383 u32 ecclk;
1384 u32 evclk;
1385 u16 v;
1386};
1387
1388struct radeon_vce_clock_voltage_dependency_table {
1389 u8 count;
1390 struct radeon_vce_clock_voltage_dependency_entry *entries;
1391};
1392
a5cb318e
AD		 1393struct radeon_ppm_table {
1394 u8 ppm_design;
1395 u16 cpu_core_number;
1396 u32 platform_tdp;
1397 u32 small_ac_platform_tdp;
1398 u32 platform_tdc;
1399 u32 small_ac_platform_tdc;
1400 u32 apu_tdp;
1401 u32 dgpu_tdp;
1402 u32 dgpu_ulv_power;
1403 u32 tj_max;
1404};
1405
58cb7632
AD		 1406struct radeon_cac_tdp_table {
1407 u16 tdp;
1408 u16 configurable_tdp;
1409 u16 tdc;
1410 u16 battery_power_limit;
1411 u16 small_power_limit;
1412 u16 low_cac_leakage;
1413 u16 high_cac_leakage;
1414 u16 maximum_power_delivery_limit;
1415};
1416
61b7d601
AD		 1417struct radeon_dpm_dynamic_state {
1418 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1419 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1420 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1421 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1422 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1423 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1424 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1425 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1426 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1427 struct radeon_clock_array valid_sclk_values;
1428 struct radeon_clock_array valid_mclk_values;
1429 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1430 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1431 u32 mclk_sclk_ratio;
1432 u32 sclk_mclk_delta;
1433 u16 vddc_vddci_delta;
1434 u16 min_vddc_for_pcie_gen2;
1435 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1436 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1437 struct radeon_ppm_table *ppm_table;
58cb7632 1438 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1439};
1440
1441struct radeon_dpm_fan {
1442 u16 t_min;
1443 u16 t_med;
1444 u16 t_high;
1445 u16 pwm_min;
1446 u16 pwm_med;
1447 u16 pwm_high;
1448 u8 t_hyst;
1449 u32 cycle_delay;
1450 u16 t_max;
1451 bool ucode_fan_control;
1452};
1453
32ce4652
AD		 1454enum radeon_pcie_gen {
1455 RADEON_PCIE_GEN1 = 0,
1456 RADEON_PCIE_GEN2 = 1,
1457 RADEON_PCIE_GEN3 = 2,
1458 RADEON_PCIE_GEN_INVALID = 0xffff
1459};
1460
70d01a5e
AD		 1461enum radeon_dpm_forced_level {
1462 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1463 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1464 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1465};
1466
58bd2a88
AD		 1467struct radeon_vce_state {
1468 /* vce clocks */
1469 u32 evclk;
1470 u32 ecclk;
1471 /* gpu clocks */
1472 u32 sclk;
1473 u32 mclk;
1474 u8 clk_idx;
1475 u8 pstate;
1476};
1477
da321c8a
AD		 1478struct radeon_dpm {
1479 struct radeon_ps *ps;
1480 /* number of valid power states */
1481 int num_ps;
1482 /* current power state that is active */
1483 struct radeon_ps *current_ps;
1484 /* requested power state */
1485 struct radeon_ps *requested_ps;
1486 /* boot up power state */
1487 struct radeon_ps *boot_ps;
1488 /* default uvd power state */
1489 struct radeon_ps *uvd_ps;
58bd2a88
AD		 1490 /* vce requirements */
1491 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1492 enum radeon_vce_level vce_level;
da321c8a
AD		 1493 enum radeon_pm_state_type state;
1494 enum radeon_pm_state_type user_state;
1495 u32 platform_caps;
1496 u32 voltage_response_time;
1497 u32 backbias_response_time;
1498 void *priv;
1499 u32 new_active_crtcs;
1500 int new_active_crtc_count;
1501 u32 current_active_crtcs;
1502 int current_active_crtc_count;
61b7d601
AD		 1503 struct radeon_dpm_dynamic_state dyn_state;
1504 struct radeon_dpm_fan fan;
1505 u32 tdp_limit;
1506 u32 near_tdp_limit;
a9e61410 1507 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1508 u32 sq_ramping_threshold;
1509 u32 cac_leakage;
1510 u16 tdp_od_limit;
1511 u32 tdp_adjustment;
1512 u16 load_line_slope;
1513 bool power_control;
5ca302f7 1514 bool ac_power;
da321c8a
AD		 1515 /* special states active */
1516 bool thermal_active;
8a227555 1517 bool uvd_active;
b62d628b 1518 bool vce_active;
da321c8a
AD		 1519 /* thermal handling */
1520 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1521 /* forced levels */
1522 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1523 /* track UVD streams */
1524 unsigned sd;
1525 unsigned hd;
da321c8a
AD		 1526};
1527
ce3537d5 1528void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
03afe6f6 1529void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
da321c8a 1530
c93bb85b 1531struct radeon_pm {
c913e23a 1532 struct mutex mutex;
db7fce39
CK		 1533 /* write locked while reprogramming mclk */
1534 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1535 u32 active_crtcs;
1536 int active_crtc_count;
c913e23a 1537 int req_vblank;
839461d3 1538 bool vblank_sync;
c93bb85b
JG		 1539 fixed20_12 max_bandwidth;
1540 fixed20_12 igp_sideport_mclk;
1541 fixed20_12 igp_system_mclk;
1542 fixed20_12 igp_ht_link_clk;
1543 fixed20_12 igp_ht_link_width;
1544 fixed20_12 k8_bandwidth;
1545 fixed20_12 sideport_bandwidth;
1546 fixed20_12 ht_bandwidth;
1547 fixed20_12 core_bandwidth;
1548 fixed20_12 sclk;
f47299c5 1549 fixed20_12 mclk;
c93bb85b 1550 fixed20_12 needed_bandwidth;
0975b162 1551 struct radeon_power_state *power_state;
56278a8e
AD		 1552 /* number of valid power states */
1553 int num_power_states;
a48b9b4e
AD		 1554 int current_power_state_index;
1555 int current_clock_mode_index;
1556 int requested_power_state_index;
1557 int requested_clock_mode_index;
1558 int default_power_state_index;
1559 u32 current_sclk;
1560 u32 current_mclk;
2feea49a
AD		 1561 u16 current_vddc;
1562 u16 current_vddci;
9ace9f7b
AD		 1563 u32 default_sclk;
1564 u32 default_mclk;
2feea49a
AD		 1565 u16 default_vddc;
1566 u16 default_vddci;
29fb52ca 1567 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1568 /* selected pm method */
1569 enum radeon_pm_method pm_method;
1570 /* dynpm power management */
1571 struct delayed_work dynpm_idle_work;
1572 enum radeon_dynpm_state dynpm_state;
1573 enum radeon_dynpm_action dynpm_planned_action;
1574 unsigned long dynpm_action_timeout;
1575 bool dynpm_can_upclock;
1576 bool dynpm_can_downclock;
1577 /* profile-based power management */
1578 enum radeon_pm_profile_type profile;
1579 int profile_index;
1580 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1581 /* internal thermal controller on rv6xx+ */
1582 enum radeon_int_thermal_type int_thermal_type;
1583 struct device *int_hwmon_dev;
da321c8a
AD		 1584 /* dpm */
1585 bool dpm_enabled;
1586 struct radeon_dpm dpm;
c93bb85b
JG		 1587};
1588
a4c9e2ee
AD		 1589int radeon_pm_get_type_index(struct radeon_device *rdev,
1590 enum radeon_pm_state_type ps_type,
1591 int instance);
f2ba57b5
CK		 1592/*
1593 * UVD
1594 */
1595#define RADEON_MAX_UVD_HANDLES 10
1596#define RADEON_UVD_STACK_SIZE (1024*1024)
1597#define RADEON_UVD_HEAP_SIZE (1024*1024)
1598
1599struct radeon_uvd {
1600 struct radeon_bo *vcpu_bo;
1601 void *cpu_addr;
1602 uint64_t gpu_addr;
9cc2e0e9 1603 void *saved_bo;
f2ba57b5
CK		 1604 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1605 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1606 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1607 struct delayed_work idle_work;
f2ba57b5
CK		 1608};
1609
1610int radeon_uvd_init(struct radeon_device *rdev);
1611void radeon_uvd_fini(struct radeon_device *rdev);
1612int radeon_uvd_suspend(struct radeon_device *rdev);
1613int radeon_uvd_resume(struct radeon_device *rdev);
1614int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1615 uint32_t handle, struct radeon_fence **fence);
1616int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1617 uint32_t handle, struct radeon_fence **fence);
1618void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1619void radeon_uvd_free_handles(struct radeon_device *rdev,
1620 struct drm_file *filp);
1621int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1622void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1623int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1624 unsigned vclk, unsigned dclk,
1625 unsigned vco_min, unsigned vco_max,
1626 unsigned fb_factor, unsigned fb_mask,
1627 unsigned pd_min, unsigned pd_max,
1628 unsigned pd_even,
1629 unsigned *optimal_fb_div,
1630 unsigned *optimal_vclk_div,
1631 unsigned *optimal_dclk_div);
1632int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1633 unsigned cg_upll_func_cntl);
771fe6b9 1634
d93f7937
CK		 1635/*
1636 * VCE
1637 */
1638#define RADEON_MAX_VCE_HANDLES 16
1639#define RADEON_VCE_STACK_SIZE (1024*1024)
1640#define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1641
1642struct radeon_vce {
1643 struct radeon_bo *vcpu_bo;
d93f7937 1644 uint64_t gpu_addr;
98ccc291
CK		 1645 unsigned fw_version;
1646 unsigned fb_version;
d93f7937
CK		 1647 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1648 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
2fc5703a 1649 unsigned img_size[RADEON_MAX_VCE_HANDLES];
03afe6f6 1650 struct delayed_work idle_work;
d93f7937
CK		 1651};
1652
1653int radeon_vce_init(struct radeon_device *rdev);
1654void radeon_vce_fini(struct radeon_device *rdev);
1655int radeon_vce_suspend(struct radeon_device *rdev);
1656int radeon_vce_resume(struct radeon_device *rdev);
1657int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1658 uint32_t handle, struct radeon_fence **fence);
1659int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1660 uint32_t handle, struct radeon_fence **fence);
1661void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
03afe6f6 1662void radeon_vce_note_usage(struct radeon_device *rdev);
2fc5703a 1663int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
d93f7937
CK		 1664int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1665bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1666 struct radeon_ring *ring,
1667 struct radeon_semaphore *semaphore,
1668 bool emit_wait);
1669void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1670void radeon_vce_fence_emit(struct radeon_device *rdev,
1671 struct radeon_fence *fence);
1672int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1673int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1674
b530602f 1675struct r600_audio_pin {
a92553ab
RM		 1676 int channels;
1677 int rate;
1678 int bits_per_sample;
1679 u8 status_bits;
1680 u8 category_code;
b530602f
AD		 1681 u32 offset;
1682 bool connected;
1683 u32 id;
1684};
1685
1686struct r600_audio {
1687 bool enabled;
1688 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1689 int num_pins;
a92553ab
RM		 1690};
1691
771fe6b9
JG		 1692/*
1693 * Benchmarking
1694 */
638dd7db 1695void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1696
1697
ecc0b326
MD		 1698/*
1699 * Testing
1700 */
1701void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1702void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1703 struct radeon_ring *cpA,
1704 struct radeon_ring *cpB);
60a7e396 1705void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326
MD		 1706
1707
771fe6b9
JG		 1708/*
1709 * Debugfs
1710 */
4d8bf9ae
CK		 1711struct radeon_debugfs {
1712 struct drm_info_list *files;
1713 unsigned num_files;
1714};
1715
771fe6b9
JG		 1716int radeon_debugfs_add_files(struct radeon_device *rdev,
1717 struct drm_info_list *files,
1718 unsigned nfiles);
1719int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1720
76a0df85
CK		 1721/*
1722 * ASIC ring specific functions.
1723 */
1724struct radeon_asic_ring {
1725 /* ring read/write ptr handling */
1726 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1727 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1728 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1729
1730 /* validating and patching of IBs */
1731 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1732 int (*cs_parse)(struct radeon_cs_parser *p);
1733
1734 /* command emmit functions */
1735 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1736 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1654b817 1737 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
76a0df85
CK		 1738 struct radeon_semaphore *semaphore, bool emit_wait);
1739 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1740
1741 /* testing functions */
1742 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1743 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1744 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1745
1746 /* deprecated */
1747 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1748};
771fe6b9
JG		 1749
1750/*
1751 * ASIC specific functions.
1752 */
1753struct radeon_asic {
068a117c 1754 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1755 void (*fini)(struct radeon_device *rdev);
1756 int (*resume)(struct radeon_device *rdev);
1757 int (*suspend)(struct radeon_device *rdev);
28d52043 1758 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1759 int (*asic_reset)(struct radeon_device *rdev);
54e88e06
AD		 1760 /* ioctl hw specific callback. Some hw might want to perform special
1761 * operation on specific ioctl. For instance on wait idle some hw
1762 * might want to perform and HDP flush through MMIO as it seems that
1763 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1764 * through ring.
1765 */
1766 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1767 /* check if 3D engine is idle */
1768 bool (*gui_idle)(struct radeon_device *rdev);
1769 /* wait for mc_idle */
1770 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1771 /* get the reference clock */
1772 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1773 /* get the gpu clock counter */
1774 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1775 /* gart */
c5b3b850
AD		 1776 struct {
1777 void (*tlb_flush)(struct radeon_device *rdev);
7f90fc96
CK		 1778 void (*set_page)(struct radeon_device *rdev, unsigned i,
1779 uint64_t addr);
c5b3b850 1780 } gart;
05b07147
CK		 1781 struct {
1782 int (*init)(struct radeon_device *rdev);
1783 void (*fini)(struct radeon_device *rdev);
43f1214a
AD		 1784 void (*set_page)(struct radeon_device *rdev,
1785 struct radeon_ib *ib,
1786 uint64_t pe,
dce34bfd
CK		 1787 uint64_t addr, unsigned count,
1788 uint32_t incr, uint32_t flags);
05b07147 1789 } vm;
54e88e06 1790 /* ring specific callbacks */
76a0df85 1791 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1792 /* irqs */
b35ea4ab
AD		 1793 struct {
1794 int (*set)(struct radeon_device *rdev);
1795 int (*process)(struct radeon_device *rdev);
1796 } irq;
54e88e06 1797 /* displays */
c79a49ca
AD		 1798 struct {
1799 /* display watermarks */
1800 void (*bandwidth_update)(struct radeon_device *rdev);
1801 /* get frame count */
1802 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1803 /* wait for vblank */
1804 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1805 /* set backlight level */
1806 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1807 /* get backlight level */
1808 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1809 /* audio callbacks */
1810 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1811 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1812 } display;
54e88e06 1813 /* copy functions for bo handling */
27cd7769
AD		 1814 struct {
1815 int (*blit)(struct radeon_device *rdev,
1816 uint64_t src_offset,
1817 uint64_t dst_offset,
1818 unsigned num_gpu_pages,
876dc9f3 1819 struct radeon_fence **fence);
27cd7769
AD		 1820 u32 blit_ring_index;
1821 int (*dma)(struct radeon_device *rdev,
1822 uint64_t src_offset,
1823 uint64_t dst_offset,
1824 unsigned num_gpu_pages,
876dc9f3 1825 struct radeon_fence **fence);
27cd7769
AD		 1826 u32 dma_ring_index;
1827 /* method used for bo copy */
1828 int (*copy)(struct radeon_device *rdev,
1829 uint64_t src_offset,
1830 uint64_t dst_offset,
1831 unsigned num_gpu_pages,
876dc9f3 1832 struct radeon_fence **fence);
27cd7769
AD		 1833 /* ring used for bo copies */
1834 u32 copy_ring_index;
1835 } copy;
54e88e06 1836 /* surfaces */
9e6f3d02
AD		 1837 struct {
1838 int (*set_reg)(struct radeon_device *rdev, int reg,
1839 uint32_t tiling_flags, uint32_t pitch,
1840 uint32_t offset, uint32_t obj_size);
1841 void (*clear_reg)(struct radeon_device *rdev, int reg);
1842 } surface;
54e88e06 1843 /* hotplug detect */
901ea57d
AD		 1844 struct {
1845 void (*init)(struct radeon_device *rdev);
1846 void (*fini)(struct radeon_device *rdev);
1847 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1848 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1849 } hpd;
da321c8a 1850 /* static power management */
a02fa397
AD		 1851 struct {
1852 void (*misc)(struct radeon_device *rdev);
1853 void (*prepare)(struct radeon_device *rdev);
1854 void (*finish)(struct radeon_device *rdev);
1855 void (*init_profile)(struct radeon_device *rdev);
1856 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1857 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1858 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1859 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1860 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1861 int (*get_pcie_lanes)(struct radeon_device *rdev);
1862 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1863 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1864 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
b59b7333 1865 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
6bd1c385 1866 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1867 } pm;
da321c8a
AD		 1868 /* dynamic power management */
1869 struct {
1870 int (*init)(struct radeon_device *rdev);
1871 void (*setup_asic)(struct radeon_device *rdev);
1872 int (*enable)(struct radeon_device *rdev);
914a8987 1873 int (*late_enable)(struct radeon_device *rdev);
da321c8a 1874 void (*disable)(struct radeon_device *rdev);
84dd1928 1875 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1876 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1877 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1878 void (*display_configuration_changed)(struct radeon_device *rdev);
1879 void (*fini)(struct radeon_device *rdev);
1880 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1881 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1882 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1883 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1884 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1885 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1886 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1c71bda0 1887 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
da321c8a 1888 } dpm;
6f34be50 1889 /* pageflipping */
0f9e006c 1890 struct {
157fa14d
CK		 1891 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1892 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
0f9e006c 1893 } pflip;
771fe6b9
JG		 1894};
1895
21f9a437
JG		 1896/*
1897 * Asic structures
1898 */
551ebd83 1899struct r100_asic {
225758d8
JG		 1900 const unsigned *reg_safe_bm;
1901 unsigned reg_safe_bm_size;
1902 u32 hdp_cntl;
551ebd83
DA		 1903};
1904
21f9a437 1905struct r300_asic {
225758d8
JG		 1906 const unsigned *reg_safe_bm;
1907 unsigned reg_safe_bm_size;
1908 u32 resync_scratch;
1909 u32 hdp_cntl;
21f9a437
JG		 1910};
1911
1912struct r600_asic {
225758d8
JG		 1913 unsigned max_pipes;
1914 unsigned max_tile_pipes;
1915 unsigned max_simds;
1916 unsigned max_backends;
1917 unsigned max_gprs;
1918 unsigned max_threads;
1919 unsigned max_stack_entries;
1920 unsigned max_hw_contexts;
1921 unsigned max_gs_threads;
1922 unsigned sx_max_export_size;
1923 unsigned sx_max_export_pos_size;
1924 unsigned sx_max_export_smx_size;
1925 unsigned sq_num_cf_insts;
1926 unsigned tiling_nbanks;
1927 unsigned tiling_npipes;
1928 unsigned tiling_group_size;
e7aeeba6 1929 unsigned tile_config;
e55b9422 1930 unsigned backend_map;
65fcf668 1931 unsigned active_simds;
21f9a437
JG		 1932};
1933
1934struct rv770_asic {
225758d8
JG		 1935 unsigned max_pipes;
1936 unsigned max_tile_pipes;
1937 unsigned max_simds;
1938 unsigned max_backends;
1939 unsigned max_gprs;
1940 unsigned max_threads;
1941 unsigned max_stack_entries;
1942 unsigned max_hw_contexts;
1943 unsigned max_gs_threads;
1944 unsigned sx_max_export_size;
1945 unsigned sx_max_export_pos_size;
1946 unsigned sx_max_export_smx_size;
1947 unsigned sq_num_cf_insts;
1948 unsigned sx_num_of_sets;
1949 unsigned sc_prim_fifo_size;
1950 unsigned sc_hiz_tile_fifo_size;
1951 unsigned sc_earlyz_tile_fifo_fize;
1952 unsigned tiling_nbanks;
1953 unsigned tiling_npipes;
1954 unsigned tiling_group_size;
e7aeeba6 1955 unsigned tile_config;
e55b9422 1956 unsigned backend_map;
65fcf668 1957 unsigned active_simds;
21f9a437
JG		 1958};
1959
32fcdbf4
AD		 1960struct evergreen_asic {
1961 unsigned num_ses;
1962 unsigned max_pipes;
1963 unsigned max_tile_pipes;
1964 unsigned max_simds;
1965 unsigned max_backends;
1966 unsigned max_gprs;
1967 unsigned max_threads;
1968 unsigned max_stack_entries;
1969 unsigned max_hw_contexts;
1970 unsigned max_gs_threads;
1971 unsigned sx_max_export_size;
1972 unsigned sx_max_export_pos_size;
1973 unsigned sx_max_export_smx_size;
1974 unsigned sq_num_cf_insts;
1975 unsigned sx_num_of_sets;
1976 unsigned sc_prim_fifo_size;
1977 unsigned sc_hiz_tile_fifo_size;
1978 unsigned sc_earlyz_tile_fifo_size;
1979 unsigned tiling_nbanks;
1980 unsigned tiling_npipes;
1981 unsigned tiling_group_size;
e7aeeba6 1982 unsigned tile_config;
e55b9422 1983 unsigned backend_map;
65fcf668 1984 unsigned active_simds;
32fcdbf4
AD		 1985};
1986
fecf1d07
AD		 1987struct cayman_asic {
1988 unsigned max_shader_engines;
1989 unsigned max_pipes_per_simd;
1990 unsigned max_tile_pipes;
1991 unsigned max_simds_per_se;
1992 unsigned max_backends_per_se;
1993 unsigned max_texture_channel_caches;
1994 unsigned max_gprs;
1995 unsigned max_threads;
1996 unsigned max_gs_threads;
1997 unsigned max_stack_entries;
1998 unsigned sx_num_of_sets;
1999 unsigned sx_max_export_size;
2000 unsigned sx_max_export_pos_size;
2001 unsigned sx_max_export_smx_size;
2002 unsigned max_hw_contexts;
2003 unsigned sq_num_cf_insts;
2004 unsigned sc_prim_fifo_size;
2005 unsigned sc_hiz_tile_fifo_size;
2006 unsigned sc_earlyz_tile_fifo_size;
2007
2008 unsigned num_shader_engines;
2009 unsigned num_shader_pipes_per_simd;
2010 unsigned num_tile_pipes;
2011 unsigned num_simds_per_se;
2012 unsigned num_backends_per_se;
2013 unsigned backend_disable_mask_per_asic;
2014 unsigned backend_map;
2015 unsigned num_texture_channel_caches;
2016 unsigned mem_max_burst_length_bytes;
2017 unsigned mem_row_size_in_kb;
2018 unsigned shader_engine_tile_size;
2019 unsigned num_gpus;
2020 unsigned multi_gpu_tile_size;
2021
2022 unsigned tile_config;
65fcf668 2023 unsigned active_simds;
fecf1d07
AD		 2024};
2025
0a96d72b
AD		 2026struct si_asic {
2027 unsigned max_shader_engines;
0a96d72b 2028 unsigned max_tile_pipes;
1a8ca750
AD		 2029 unsigned max_cu_per_sh;
2030 unsigned max_sh_per_se;
0a96d72b
AD		 2031 unsigned max_backends_per_se;
2032 unsigned max_texture_channel_caches;
2033 unsigned max_gprs;
2034 unsigned max_gs_threads;
2035 unsigned max_hw_contexts;
2036 unsigned sc_prim_fifo_size_frontend;
2037 unsigned sc_prim_fifo_size_backend;
2038 unsigned sc_hiz_tile_fifo_size;
2039 unsigned sc_earlyz_tile_fifo_size;
2040
0a96d72b 2041 unsigned num_tile_pipes;
439a1cff 2042 unsigned backend_enable_mask;
0a96d72b
AD		 2043 unsigned backend_disable_mask_per_asic;
2044 unsigned backend_map;
2045 unsigned num_texture_channel_caches;
2046 unsigned mem_max_burst_length_bytes;
2047 unsigned mem_row_size_in_kb;
2048 unsigned shader_engine_tile_size;
2049 unsigned num_gpus;
2050 unsigned multi_gpu_tile_size;
2051
2052 unsigned tile_config;
64d7b8be 2053 uint32_t tile_mode_array[32];
65fcf668 2054 uint32_t active_cus;
0a96d72b
AD		 2055};
2056
8cc1a532
AD		 2057struct cik_asic {
2058 unsigned max_shader_engines;
2059 unsigned max_tile_pipes;
2060 unsigned max_cu_per_sh;
2061 unsigned max_sh_per_se;
2062 unsigned max_backends_per_se;
2063 unsigned max_texture_channel_caches;
2064 unsigned max_gprs;
2065 unsigned max_gs_threads;
2066 unsigned max_hw_contexts;
2067 unsigned sc_prim_fifo_size_frontend;
2068 unsigned sc_prim_fifo_size_backend;
2069 unsigned sc_hiz_tile_fifo_size;
2070 unsigned sc_earlyz_tile_fifo_size;
2071
2072 unsigned num_tile_pipes;
439a1cff 2073 unsigned backend_enable_mask;
8cc1a532
AD		 2074 unsigned backend_disable_mask_per_asic;
2075 unsigned backend_map;
2076 unsigned num_texture_channel_caches;
2077 unsigned mem_max_burst_length_bytes;
2078 unsigned mem_row_size_in_kb;
2079 unsigned shader_engine_tile_size;
2080 unsigned num_gpus;
2081 unsigned multi_gpu_tile_size;
2082
2083 unsigned tile_config;
39aee490 2084 uint32_t tile_mode_array[32];
32f79a8a 2085 uint32_t macrotile_mode_array[16];
65fcf668 2086 uint32_t active_cus;
8cc1a532
AD		 2087};
2088
068a117c
JG		 2089union radeon_asic_config {
2090 struct r300_asic r300;
551ebd83 2091 struct r100_asic r100;
3ce0a23d
JG		 2092 struct r600_asic r600;
2093 struct rv770_asic rv770;
32fcdbf4 2094 struct evergreen_asic evergreen;
fecf1d07 2095 struct cayman_asic cayman;
0a96d72b 2096 struct si_asic si;
8cc1a532 2097 struct cik_asic cik;
068a117c
JG		 2098};
2099
0a10c851
DV		 2100/*
2101 * asic initizalization from radeon_asic.c
2102 */
2103void radeon_agp_disable(struct radeon_device *rdev);
2104int radeon_asic_init(struct radeon_device *rdev);
2105
771fe6b9
JG		 2106
2107/*
2108 * IOCTL.
2109 */
2110int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2111 struct drm_file *filp);
2112int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2113 struct drm_file *filp);
2114int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2115 struct drm_file *file_priv);
2116int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2117 struct drm_file *file_priv);
2118int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2119 struct drm_file *file_priv);
2120int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2121 struct drm_file *file_priv);
2122int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2123 struct drm_file *filp);
2124int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2125 struct drm_file *filp);
2126int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2127 struct drm_file *filp);
2128int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2129 struct drm_file *filp);
721604a1
JG		 2130int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2131 struct drm_file *filp);
bda72d58
MO		 2132int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2133 struct drm_file *filp);
771fe6b9 2134int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 2135int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2136 struct drm_file *filp);
2137int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2138 struct drm_file *filp);
771fe6b9 2139
16cdf04d
AD		 2140/* VRAM scratch page for HDP bug, default vram page */
2141struct r600_vram_scratch {
87cbf8f2
AD		 2142 struct radeon_bo *robj;
2143 volatile uint32_t *ptr;
16cdf04d 2144 u64 gpu_addr;
87cbf8f2 2145};
771fe6b9 2146
fd64ca8a
LT		 2147/*
2148 * ACPI
2149 */
2150struct radeon_atif_notification_cfg {
2151 bool enabled;
2152 int command_code;
2153};
2154
2155struct radeon_atif_notifications {
2156 bool display_switch;
2157 bool expansion_mode_change;
2158 bool thermal_state;
2159 bool forced_power_state;
2160 bool system_power_state;
2161 bool display_conf_change;
2162 bool px_gfx_switch;
2163 bool brightness_change;
2164 bool dgpu_display_event;
2165};
2166
2167struct radeon_atif_functions {
2168 bool system_params;
2169 bool sbios_requests;
2170 bool select_active_disp;
2171 bool lid_state;
2172 bool get_tv_standard;
2173 bool set_tv_standard;
2174 bool get_panel_expansion_mode;
2175 bool set_panel_expansion_mode;
2176 bool temperature_change;
2177 bool graphics_device_types;
2178};
2179
2180struct radeon_atif {
2181 struct radeon_atif_notifications notifications;
2182 struct radeon_atif_functions functions;
2183 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2184 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2185};
7a1619b9 2186
e3a15920
AD		 2187struct radeon_atcs_functions {
2188 bool get_ext_state;
2189 bool pcie_perf_req;
2190 bool pcie_dev_rdy;
2191 bool pcie_bus_width;
2192};
2193
2194struct radeon_atcs {
2195 struct radeon_atcs_functions functions;
2196};
2197
771fe6b9
JG		 2198/*
2199 * Core structure, functions and helpers.
2200 */
2201typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2202typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2203
2204struct radeon_device {
9f022ddf 2205 struct device *dev;
771fe6b9
JG		 2206 struct drm_device *ddev;
2207 struct pci_dev *pdev;
dee53e7f 2208 struct rw_semaphore exclusive_lock;
771fe6b9 2209 /* ASIC */
068a117c 2210 union radeon_asic_config config;
771fe6b9
JG		 2211 enum radeon_family family;
2212 unsigned long flags;
2213 int usec_timeout;
2214 enum radeon_pll_errata pll_errata;
2215 int num_gb_pipes;
f779b3e5 2216 int num_z_pipes;
771fe6b9
JG		 2217 int disp_priority;
2218 /* BIOS */
2219 uint8_t *bios;
2220 bool is_atom_bios;
2221 uint16_t bios_header_start;
4c788679 2222 struct radeon_bo *stollen_vga_memory;
771fe6b9 2223 /* Register mmio */
4c9bc75c
DA		 2224 resource_size_t rmmio_base;
2225 resource_size_t rmmio_size;
2c385151
DV		 2226 /* protects concurrent MM_INDEX/DATA based register access */
2227 spinlock_t mmio_idx_lock;
fe78118c
AD		 2228 /* protects concurrent SMC based register access */
2229 spinlock_t smc_idx_lock;
0a5b7b0b
AD		 2230 /* protects concurrent PLL register access */
2231 spinlock_t pll_idx_lock;
2232 /* protects concurrent MC register access */
2233 spinlock_t mc_idx_lock;
2234 /* protects concurrent PCIE register access */
2235 spinlock_t pcie_idx_lock;
2236 /* protects concurrent PCIE_PORT register access */
2237 spinlock_t pciep_idx_lock;
2238 /* protects concurrent PIF register access */
2239 spinlock_t pif_idx_lock;
2240 /* protects concurrent CG register access */
2241 spinlock_t cg_idx_lock;
2242 /* protects concurrent UVD register access */
2243 spinlock_t uvd_idx_lock;
2244 /* protects concurrent RCU register access */
2245 spinlock_t rcu_idx_lock;
2246 /* protects concurrent DIDT register access */
2247 spinlock_t didt_idx_lock;
2248 /* protects concurrent ENDPOINT (audio) register access */
2249 spinlock_t end_idx_lock;
a0533fbf 2250 void __iomem *rmmio;
771fe6b9
JG		 2251 radeon_rreg_t mc_rreg;
2252 radeon_wreg_t mc_wreg;
2253 radeon_rreg_t pll_rreg;
2254 radeon_wreg_t pll_wreg;
de1b2898 2255 uint32_t pcie_reg_mask;
771fe6b9
JG		 2256 radeon_rreg_t pciep_rreg;
2257 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2258 /* io port */
2259 void __iomem *rio_mem;
2260 resource_size_t rio_mem_size;
771fe6b9
JG		 2261 struct radeon_clock clock;
2262 struct radeon_mc mc;
2263 struct radeon_gart gart;
2264 struct radeon_mode_info mode_info;
2265 struct radeon_scratch scratch;
75efdee1 2266 struct radeon_doorbell doorbell;
771fe6b9 2267 struct radeon_mman mman;
7465280c 2268 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2269 wait_queue_head_t fence_queue;
d6999bc7 2270 struct mutex ring_lock;
e32eb50d 2271 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2272 bool ib_pool_ready;
2273 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2274 struct radeon_irq irq;
2275 struct radeon_asic *asic;
2276 struct radeon_gem gem;
c93bb85b 2277 struct radeon_pm pm;
f2ba57b5 2278 struct radeon_uvd uvd;
d93f7937 2279 struct radeon_vce vce;
f657c2a7 2280 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2281 struct radeon_wb wb;
3ce0a23d 2282 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2283 bool shutdown;
2284 bool suspend;
ad49f501 2285 bool need_dma32;
733289c2 2286 bool accel_working;
a0a53aa8 2287 bool fastfb_working; /* IGP feature*/
f9eaf9ae 2288 bool needs_reset;
e024e110 2289 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2290 const struct firmware *me_fw; /* all family ME firmware */
2291 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2292 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2293 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2294 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2295 const struct firmware *mec_fw; /* CIK MEC firmware */
21a93e13 2296 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2297 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2298 const struct firmware *uvd_fw; /* UVD firmware */
d93f7937 2299 const struct firmware *vce_fw; /* VCE firmware */
16cdf04d 2300 struct r600_vram_scratch vram_scratch;
3e5cb98d 2301 int msi_enabled; /* msi enabled */
d8f60cfc 2302 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2303 struct radeon_rlc rlc;
963e81f9 2304 struct radeon_mec mec;
d4877cf2 2305 struct work_struct hotplug_work;
f122c610 2306 struct work_struct audio_work;
8f61b34c 2307 struct work_struct reset_work;
18917b60 2308 int num_crtc; /* number of crtcs */
40bacf16 2309 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
948bee3f 2310 bool has_uvd;
b530602f 2311 struct r600_audio audio; /* audio stuff */
ce8f5370 2312 struct notifier_block acpi_nb;
9eba4a93 2313 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2314 struct drm_file *hyperz_filp;
9eba4a93 2315 struct drm_file *cmask_filp;
f376b94f
AD		 2316 /* i2c buses */
2317 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2318 /* debugfs */
2319 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2320 unsigned debugfs_count;
721604a1
JG		 2321 /* virtual memory */
2322 struct radeon_vm_manager vm_manager;
6759a0a7 2323 struct mutex gpu_clock_mutex;
67e8e3f9
MO		 2324 /* memory stats */
2325 atomic64_t vram_usage;
2326 atomic64_t gtt_usage;
2327 atomic64_t num_bytes_moved;
fd64ca8a
LT		 2328 /* ACPI interface */
2329 struct radeon_atif atif;
e3a15920 2330 struct radeon_atcs atcs;
f61d5b46
AD		 2331 /* srbm instance registers */
2332 struct mutex srbm_mutex;
64d8a728
AD		 2333 /* clock, powergating flags */
2334 u32 cg_flags;
2335 u32 pg_flags;
10ebc0bc
DA		 2336
2337 struct dev_pm_domain vga_pm_domain;
2338 bool have_disp_power_ref;
771fe6b9
JG		 2339};
2340
90c4cde9 2341bool radeon_is_px(struct drm_device *dev);
771fe6b9
JG		 2342int radeon_device_init(struct radeon_device *rdev,
2343 struct drm_device *ddev,
2344 struct pci_dev *pdev,
2345 uint32_t flags);
2346void radeon_device_fini(struct radeon_device *rdev);
2347int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2348
2ef9bdfe
DV		 2349uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2350 bool always_indirect);
2351void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2352 bool always_indirect);
6fcbef7a
AK		 2353u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2354void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2355
d5754ab8
AL		 2356u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2357void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
75efdee1 2358
4c788679
JG		 2359/*
2360 * Cast helper
2361 */
2362#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 2363
2364/*
2365 * Registers read & write functions.
2366 */
a0533fbf
BH		 2367#define RREG8(reg) readb((rdev->rmmio) + (reg))
2368#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2369#define RREG16(reg) readw((rdev->rmmio) + (reg))
2370#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2371#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2372#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2373#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2374#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2375#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2376#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2377#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2378#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2379#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2380#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2381#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2382#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2383#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2384#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2385#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2386#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2387#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2388#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2389#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2390#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2391#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2392#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2393#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2394#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2395#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2396#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2397#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2398#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2399#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2400#define WREG32_P(reg, val, mask) \
2401 do { \
2402 uint32_t tmp_ = RREG32(reg); \
2403 tmp_ &= (mask); \
2404 tmp_ |= ((val) & ~(mask)); \
2405 WREG32(reg, tmp_); \
2406 } while (0)
d5169fc4 2407#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2408#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2409#define WREG32_PLL_P(reg, val, mask) \
2410 do { \
2411 uint32_t tmp_ = RREG32_PLL(reg); \
2412 tmp_ &= (mask); \
2413 tmp_ |= ((val) & ~(mask)); \
2414 WREG32_PLL(reg, tmp_); \
2415 } while (0)
2ef9bdfe 2416#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2417#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2418#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2419
d5754ab8
AL		 2420#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2421#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
75efdee1 2422
de1b2898
DA		 2423/*
2424 * Indirect registers accessor
2425 */
2426static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2427{
0a5b7b0b 2428 unsigned long flags;
de1b2898
DA		 2429 uint32_t r;
2430
0a5b7b0b 2431 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2432 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2433 r = RREG32(RADEON_PCIE_DATA);
0a5b7b0b 2434 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2435 return r;
2436}
2437
2438static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2439{
0a5b7b0b
AD		 2440 unsigned long flags;
2441
2442 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2443 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2444 WREG32(RADEON_PCIE_DATA, (v));
0a5b7b0b 2445 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2446}
2447
1d5d0c34
AD		 2448static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2449{
fe78118c 2450 unsigned long flags;
1d5d0c34
AD		 2451 u32 r;
2452
fe78118c 2453 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2454 WREG32(TN_SMC_IND_INDEX_0, (reg));
2455 r = RREG32(TN_SMC_IND_DATA_0);
fe78118c 2456 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2457 return r;
2458}
2459
2460static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2461{
fe78118c
AD		 2462 unsigned long flags;
2463
2464 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2465 WREG32(TN_SMC_IND_INDEX_0, (reg));
2466 WREG32(TN_SMC_IND_DATA_0, (v));
fe78118c 2467 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2468}
2469
ff82bbc4
AD		 2470static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2471{
0a5b7b0b 2472 unsigned long flags;
ff82bbc4
AD		 2473 u32 r;
2474
0a5b7b0b 2475 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2476 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2477 r = RREG32(R600_RCU_DATA);
0a5b7b0b 2478 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2479 return r;
2480}
2481
2482static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2483{
0a5b7b0b
AD		 2484 unsigned long flags;
2485
2486 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2487 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2488 WREG32(R600_RCU_DATA, (v));
0a5b7b0b 2489 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2490}
2491
46f9564a
AD		 2492static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2493{
0a5b7b0b 2494 unsigned long flags;
46f9564a
AD		 2495 u32 r;
2496
0a5b7b0b 2497 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2498 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2499 r = RREG32(EVERGREEN_CG_IND_DATA);
0a5b7b0b 2500 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2501 return r;
2502}
2503
2504static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2505{
0a5b7b0b
AD		 2506 unsigned long flags;
2507
2508 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2509 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2510 WREG32(EVERGREEN_CG_IND_DATA, (v));
0a5b7b0b 2511 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2512}
2513
792edd69
AD		 2514static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2515{
0a5b7b0b 2516 unsigned long flags;
792edd69
AD		 2517 u32 r;
2518
0a5b7b0b 2519 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2520 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2521 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
0a5b7b0b 2522 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2523 return r;
2524}
2525
2526static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2527{
0a5b7b0b
AD		 2528 unsigned long flags;
2529
2530 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2531 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2532 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
0a5b7b0b 2533 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2534}
2535
2536static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2537{
0a5b7b0b 2538 unsigned long flags;
792edd69
AD		 2539 u32 r;
2540
0a5b7b0b 2541 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2542 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2543 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
0a5b7b0b 2544 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2545 return r;
2546}
2547
2548static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2549{
0a5b7b0b
AD		 2550 unsigned long flags;
2551
2552 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2553 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2554 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
0a5b7b0b 2555 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2556}
2557
93656cdd
AD		 2558static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2559{
0a5b7b0b 2560 unsigned long flags;
93656cdd
AD		 2561 u32 r;
2562
0a5b7b0b 2563 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2564 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2565 r = RREG32(R600_UVD_CTX_DATA);
0a5b7b0b 2566 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2567 return r;
2568}
2569
2570static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2571{
0a5b7b0b
AD		 2572 unsigned long flags;
2573
2574 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2575 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2576 WREG32(R600_UVD_CTX_DATA, (v));
0a5b7b0b 2577 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2578}
2579
1d58234d
AD		 2580
2581static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2582{
0a5b7b0b 2583 unsigned long flags;
1d58234d
AD		 2584 u32 r;
2585
0a5b7b0b 2586 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2587 WREG32(CIK_DIDT_IND_INDEX, (reg));
2588 r = RREG32(CIK_DIDT_IND_DATA);
0a5b7b0b 2589 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2590 return r;
2591}
2592
2593static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2594{
0a5b7b0b
AD		 2595 unsigned long flags;
2596
2597 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2598 WREG32(CIK_DIDT_IND_INDEX, (reg));
2599 WREG32(CIK_DIDT_IND_DATA, (v));
0a5b7b0b 2600 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2601}
2602
771fe6b9
JG		 2603void r100_pll_errata_after_index(struct radeon_device *rdev);
2604
2605
2606/*
2607 * ASICs helpers.
2608 */
b995e433
DA		 2609#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2610 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2611#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2612 (rdev->family == CHIP_RV200) || \
2613 (rdev->family == CHIP_RS100) || \
2614 (rdev->family == CHIP_RS200) || \
2615 (rdev->family == CHIP_RV250) || \
2616 (rdev->family == CHIP_RV280) || \
2617 (rdev->family == CHIP_RS300))
2618#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2619 (rdev->family == CHIP_RV350) || \
2620 (rdev->family == CHIP_R350) || \
2621 (rdev->family == CHIP_RV380) || \
2622 (rdev->family == CHIP_R420) || \
2623 (rdev->family == CHIP_R423) || \
2624 (rdev->family == CHIP_RV410) || \
2625 (rdev->family == CHIP_RS400) || \
2626 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2627#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2628 (rdev->ddev->pdev->device == 0x9443) || \
2629 (rdev->ddev->pdev->device == 0x944B) || \
2630 (rdev->ddev->pdev->device == 0x9506) || \
2631 (rdev->ddev->pdev->device == 0x9509) || \
2632 (rdev->ddev->pdev->device == 0x950F) || \
2633 (rdev->ddev->pdev->device == 0x689C) || \
2634 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2635#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2636#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2637 (rdev->family == CHIP_RS690) || \
2638 (rdev->family == CHIP_RS740) || \
2639 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2640#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2641#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2642#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2643#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2644 (rdev->flags & RADEON_IS_IGP))
1fe18305 2645#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2646#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2647#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2648 (rdev->flags & RADEON_IS_IGP))
624d3524 2649#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2650#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2651#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
be0949f5
AD		 2652#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2653#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
89d2618d
AD		 2654#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2655 (rdev->family == CHIP_MULLINS))
771fe6b9 2656
dc50ba7f
AD		 2657#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2658 (rdev->ddev->pdev->device == 0x6850) || \
2659 (rdev->ddev->pdev->device == 0x6858) || \
2660 (rdev->ddev->pdev->device == 0x6859) || \
2661 (rdev->ddev->pdev->device == 0x6840) || \
2662 (rdev->ddev->pdev->device == 0x6841) || \
2663 (rdev->ddev->pdev->device == 0x6842) || \
2664 (rdev->ddev->pdev->device == 0x6843))
2665
771fe6b9
JG		 2666/*
2667 * BIOS helpers.
2668 */
2669#define RBIOS8(i) (rdev->bios[i])
2670#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2671#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2672
2673int radeon_combios_init(struct radeon_device *rdev);
2674void radeon_combios_fini(struct radeon_device *rdev);
2675int radeon_atombios_init(struct radeon_device *rdev);
2676void radeon_atombios_fini(struct radeon_device *rdev);
2677
2678
2679/*
2680 * RING helpers.
2681 */
ce580fab 2682#if DRM_DEBUG_CODE == 0
e32eb50d 2683static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2684{
e32eb50d
CK		 2685 ring->ring[ring->wptr++] = v;
2686 ring->wptr &= ring->ptr_mask;
2687 ring->count_dw--;
2688 ring->ring_free_dw--;
771fe6b9 2689}
ce580fab
AK		 2690#else
2691/* With debugging this is just too big to inline */
e32eb50d 2692void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
ce580fab 2693#endif
771fe6b9
JG		 2694
2695/*
2696 * ASICs macro.
2697 */
068a117c 2698#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2699#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2700#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2701#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2702#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2703#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2704#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850
AD		 2705#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2706#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
05b07147
CK		 2707#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2708#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
43f1214a 2709#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
76a0df85
CK		 2710#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2711#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2712#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2713#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2714#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2715#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2716#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2717#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2718#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2719#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2720#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2721#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2722#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2723#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2724#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2725#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2726#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2727#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2728#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
27cd7769
AD		 2729#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2730#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2731#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2732#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2733#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2734#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2735#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2736#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2737#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2738#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2739#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2740#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2741#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2742#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
b59b7333 2743#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
6bd1c385 2744#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2745#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2746#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2747#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2748#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2749#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2750#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2751#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2752#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2753#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2754#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2755#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2756#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2757#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8 2758#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
157fa14d 2759#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
69b62ad8
AD		 2760#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2761#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2762#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2763#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2764#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2765#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2766#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
914a8987 2767#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
da321c8a 2768#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2769#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2770#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2771#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2772#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2773#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2774#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2775#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2776#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2777#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2778#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2779#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2780#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
1c71bda0 2781#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
771fe6b9 2782
6cf8a3f5 2783/* Common functions */
700a0cc0 2784/* AGP */
90aca4d2 2785extern int radeon_gpu_reset(struct radeon_device *rdev);
1a0041b8 2786extern void radeon_pci_config_reset(struct radeon_device *rdev);
410a3418 2787extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2788extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2789extern int radeon_modeset_init(struct radeon_device *rdev);
2790extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2791extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2792extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2793extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2794extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2795extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2796extern void radeon_wb_fini(struct radeon_device *rdev);
2797extern int radeon_wb_init(struct radeon_device *rdev);
2798extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2799extern void radeon_surface_init(struct radeon_device *rdev);
2800extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2801extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2802extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2803extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2804extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 2805extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2806extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
10ebc0bc
DA		 2807extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2808extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
53595338 2809extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2810extern void radeon_program_register_sequence(struct radeon_device *rdev,
2811 const u32 *registers,
2812 const u32 array_size);
6cf8a3f5 2813
721604a1
JG		 2814/*
2815 * vm
2816 */
2817int radeon_vm_manager_init(struct radeon_device *rdev);
2818void radeon_vm_manager_fini(struct radeon_device *rdev);
6d2f2944 2819int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2820void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
df0af440
CK		 2821struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2822 struct radeon_vm *vm,
2823 struct list_head *head);
ee60e29f
CK		 2824struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2825 struct radeon_vm *vm, int ring);
fa688343
CK		 2826void radeon_vm_flush(struct radeon_device *rdev,
2827 struct radeon_vm *vm,
2828 int ring);
ee60e29f
CK		 2829void radeon_vm_fence(struct radeon_device *rdev,
2830 struct radeon_vm *vm,
2831 struct radeon_fence *fence);
dce34bfd 2832uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
6d2f2944
CK		 2833int radeon_vm_update_page_directory(struct radeon_device *rdev,
2834 struct radeon_vm *vm);
9c57a6bd
CK		 2835int radeon_vm_bo_update(struct radeon_device *rdev,
2836 struct radeon_vm *vm,
2837 struct radeon_bo *bo,
2838 struct ttm_mem_reg *mem);
721604a1
JG		 2839void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2840 struct radeon_bo *bo);
421ca7ab
CK		 2841struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2842 struct radeon_bo *bo);
e971bd5e
CK		 2843struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2844 struct radeon_vm *vm,
2845 struct radeon_bo *bo);
2846int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2847 struct radeon_bo_va *bo_va,
2848 uint64_t offset,
2849 uint32_t flags);
721604a1 2850int radeon_vm_bo_rmv(struct radeon_device *rdev,
e971bd5e 2851 struct radeon_bo_va *bo_va);
721604a1 2852
f122c610
AD		 2853/* audio */
2854void r600_audio_update_hdmi(struct work_struct *work);
b530602f
AD		 2855struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2856struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
832eafaf
AD		 2857void r600_audio_enable(struct radeon_device *rdev,
2858 struct r600_audio_pin *pin,
2859 bool enable);
2860void dce6_audio_enable(struct radeon_device *rdev,
2861 struct r600_audio_pin *pin,
2862 bool enable);
721604a1 2863
16cdf04d
AD		 2864/*
2865 * R600 vram scratch functions
2866 */
2867int r600_vram_scratch_init(struct radeon_device *rdev);
2868void r600_vram_scratch_fini(struct radeon_device *rdev);
2869
285484e2
JG		 2870/*
2871 * r600 cs checking helper
2872 */
2873unsigned r600_mip_minify(unsigned size, unsigned level);
2874bool r600_fmt_is_valid_color(u32 format);
2875bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2876int r600_fmt_get_blocksize(u32 format);
2877int r600_fmt_get_nblocksx(u32 format, u32 w);
2878int r600_fmt_get_nblocksy(u32 format, u32 h);
2879
3574dda4
DV		 2880/*
2881 * r600 functions used by radeon_encoder.c
2882 */
1b688d08
RM		 2883struct radeon_hdmi_acr {
2884 u32 clock;
2885
2886 int n_32khz;
2887 int cts_32khz;
2888
2889 int n_44_1khz;
2890 int cts_44_1khz;
2891
2892 int n_48khz;
2893 int cts_48khz;
2894
2895};
2896
e55d3e6c
RM		 2897extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2898
416a2bd2
AD		 2899extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2900 u32 tiling_pipe_num,
2901 u32 max_rb_num,
2902 u32 total_max_rb_num,
2903 u32 enabled_rb_mask);
fe251e2f 2904
e55d3e6c
RM		 2905/*
2906 * evergreen functions used by radeon_encoder.c
2907 */
2908
0af62b01 2909extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2910extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2911
c4917074
AD		 2912/* radeon_acpi.c */
2913#if defined(CONFIG_ACPI)
2914extern int radeon_acpi_init(struct radeon_device *rdev);
2915extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2916extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2917extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2918 u8 perf_req, bool advertise);
dc50ba7f 2919extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2920#else
2921static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2922static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2923#endif
d7a2952f 2924
c38f34b5
IH		 2925int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2926 struct radeon_cs_packet *pkt,
2927 unsigned idx);
9ffb7a6d 2928bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2929void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2930 struct radeon_cs_packet *pkt);
e9716993
IH		 2931int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2932 struct radeon_cs_reloc **cs_reloc,
2933 int nomm);
40592a17
IH		 2934int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2935 uint32_t *vline_start_end,
2936 uint32_t *vline_status);
c38f34b5 2937
4c788679
JG		 2938#include "radeon_object.h"
2939
771fe6b9 2940#endif
Linux kernel - Deliverables
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