projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon: convert to pmops
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
a18cee15 96extern int radeon_msi;
3368ff0c 97extern int radeon_lockup_timeout;
a0a53aa8 98extern int radeon_fastfb;
da321c8a 99extern int radeon_dpm;
1294d4a3 100extern int radeon_aspm;
771fe6b9
JG		 101
102/*
103 * Copy from radeon_drv.h so we don't have to include both and have conflicting
104 * symbol;
105 */
bb635567
JG		 106#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
107#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 108/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 109#define RADEON_IB_POOL_SIZE 16
110#define RADEON_DEBUGFS_MAX_COMPONENTS 32
111#define RADEONFB_CONN_LIMIT 4
112#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 113
1b37078b 114/* max number of rings */
f2ba57b5 115#define RADEON_NUM_RINGS 6
bb635567
JG		 116
117/* fence seq are set to this number when signaled */
118#define RADEON_FENCE_SIGNALED_SEQ 0LL
1b37078b
AD		 119
120/* internal ring indices */
121/* r1xx+ has gfx CP ring */
f2ba57b5 122#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 123
124/* cayman has 2 compute CP rings */
f2ba57b5
CK		 125#define CAYMAN_RING_TYPE_CP1_INDEX 1
126#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 127
4d75658b
AD		 128/* R600+ has an async dma ring */
129#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 130/* cayman add a second async dma ring */
131#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 132
f2ba57b5
CK		 133/* R600+ */
134#define R600_RING_TYPE_UVD_INDEX 5
135
721604a1 136/* hardcode those limit for now */
ca19f21e 137#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 138#define RADEON_VA_RESERVED_SIZE (8 << 20)
139#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 140
ec46c76d
AD		 141/* reset flags */
142#define RADEON_RESET_GFX (1 << 0)
143#define RADEON_RESET_COMPUTE (1 << 1)
144#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 145#define RADEON_RESET_CP (1 << 3)
146#define RADEON_RESET_GRBM (1 << 4)
147#define RADEON_RESET_DMA1 (1 << 5)
148#define RADEON_RESET_RLC (1 << 6)
149#define RADEON_RESET_SEM (1 << 7)
150#define RADEON_RESET_IH (1 << 8)
151#define RADEON_RESET_VMC (1 << 9)
152#define RADEON_RESET_MC (1 << 10)
153#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 154
22c775ce
AD		 155/* CG block flags */
156#define RADEON_CG_BLOCK_GFX (1 << 0)
157#define RADEON_CG_BLOCK_MC (1 << 1)
158#define RADEON_CG_BLOCK_SDMA (1 << 2)
159#define RADEON_CG_BLOCK_UVD (1 << 3)
160#define RADEON_CG_BLOCK_VCE (1 << 4)
161#define RADEON_CG_BLOCK_HDP (1 << 5)
e16866ec 162#define RADEON_CG_BLOCK_BIF (1 << 6)
22c775ce 163
64d8a728
AD		 164/* CG flags */
165#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
166#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
167#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
168#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
169#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
170#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
171#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
172#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
173#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
174#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
175#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
176#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
177#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
178#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
179#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
180#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
181#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
182
183/* PG flags */
2b19d17f 184#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
64d8a728
AD		 185#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
186#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
187#define RADEON_PG_SUPPORT_UVD (1 << 3)
188#define RADEON_PG_SUPPORT_VCE (1 << 4)
189#define RADEON_PG_SUPPORT_CP (1 << 5)
190#define RADEON_PG_SUPPORT_GDS (1 << 6)
191#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
192#define RADEON_PG_SUPPORT_SDMA (1 << 8)
193#define RADEON_PG_SUPPORT_ACP (1 << 9)
194#define RADEON_PG_SUPPORT_SAMU (1 << 10)
195
9e05fa1d
AD		 196/* max cursor sizes (in pixels) */
197#define CURSOR_WIDTH 64
198#define CURSOR_HEIGHT 64
199
200#define CIK_CURSOR_WIDTH 128
201#define CIK_CURSOR_HEIGHT 128
202
771fe6b9
JG		 203/*
204 * Errata workarounds.
205 */
206enum radeon_pll_errata {
207 CHIP_ERRATA_R300_CG = 0x00000001,
208 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
209 CHIP_ERRATA_PLL_DELAY = 0x00000004
210};
211
212
213struct radeon_device;
214
215
216/*
217 * BIOS.
218 */
219bool radeon_get_bios(struct radeon_device *rdev);
220
221/*
3ce0a23d 222 * Dummy page
771fe6b9 223 */
3ce0a23d
JG		 224struct radeon_dummy_page {
225 struct page *page;
226 dma_addr_t addr;
227};
228int radeon_dummy_page_init(struct radeon_device *rdev);
229void radeon_dummy_page_fini(struct radeon_device *rdev);
230
771fe6b9 231
3ce0a23d
JG		 232/*
233 * Clocks
234 */
771fe6b9
JG		 235struct radeon_clock {
236 struct radeon_pll p1pll;
237 struct radeon_pll p2pll;
bcc1c2a1 238 struct radeon_pll dcpll;
771fe6b9
JG		 239 struct radeon_pll spll;
240 struct radeon_pll mpll;
241 /* 10 Khz units */
242 uint32_t default_mclk;
243 uint32_t default_sclk;
bcc1c2a1 244 uint32_t default_dispclk;
4489cd62 245 uint32_t current_dispclk;
bcc1c2a1 246 uint32_t dp_extclk;
b20f9bef 247 uint32_t max_pixel_clock;
771fe6b9
JG		 248};
249
7433874e
RM		 250/*
251 * Power management
252 */
253int radeon_pm_init(struct radeon_device *rdev);
29fb52ca 254void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 255void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 256void radeon_pm_suspend(struct radeon_device *rdev);
257void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 258void radeon_combios_get_power_modes(struct radeon_device *rdev);
259void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 260int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
261 u8 clock_type,
262 u32 clock,
263 bool strobe_mode,
264 struct atom_clock_dividers *dividers);
eaa778af
AD		 265int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
266 u32 clock,
267 bool strobe_mode,
268 struct atom_mpll_param *mpll_param);
8a83ec5e 269void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 270int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
271 u16 voltage_level, u8 voltage_type,
272 u32 *gpio_value, u32 *gpio_mask);
273void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
274 u32 eng_clock, u32 mem_clock);
275int radeon_atom_get_voltage_step(struct radeon_device *rdev,
276 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 277int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
278 u16 voltage_id, u16 *voltage);
beb79f40
AD		 279int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
280 u16 *voltage,
281 u16 leakage_idx);
cc8dbbb4
AD		 282int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
283 u16 *leakage_id);
284int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
285 u16 *vddc, u16 *vddci,
286 u16 virtual_voltage_id,
287 u16 vbios_voltage_id);
ae5b0abb
AD		 288int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
289 u8 voltage_type,
290 u16 nominal_voltage,
291 u16 *true_voltage);
292int radeon_atom_get_min_voltage(struct radeon_device *rdev,
293 u8 voltage_type, u16 *min_voltage);
294int radeon_atom_get_max_voltage(struct radeon_device *rdev,
295 u8 voltage_type, u16 *max_voltage);
296int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 297 u8 voltage_type, u8 voltage_mode,
ae5b0abb 298 struct atom_voltage_table *voltage_table);
58653abd
AD		 299bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
300 u8 voltage_type, u8 voltage_mode);
ae5b0abb
AD		 301void radeon_atom_update_memory_dll(struct radeon_device *rdev,
302 u32 mem_clock);
303void radeon_atom_set_ac_timing(struct radeon_device *rdev,
304 u32 mem_clock);
305int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
306 u8 module_index,
307 struct atom_mc_reg_table *reg_table);
308int radeon_atom_get_memory_info(struct radeon_device *rdev,
309 u8 module_index, struct atom_memory_info *mem_info);
310int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
311 bool gddr5, u8 module_index,
312 struct atom_memory_clock_range_table *mclk_range_table);
313int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
314 u16 voltage_id, u16 *voltage);
f892034a 315void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 316extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
317 unsigned *bankh, unsigned *mtaspect,
318 unsigned *tile_split);
3ce0a23d 319
771fe6b9
JG		 320/*
321 * Fences.
322 */
323struct radeon_fence_driver {
324 uint32_t scratch_reg;
30eb77f4
JG		 325 uint64_t gpu_addr;
326 volatile uint32_t *cpu_addr;
68e250b7
CK		 327 /* sync_seq is protected by ring emission lock */
328 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 329 atomic64_t last_seq;
36abacae 330 unsigned long last_activity;
0a0c7596 331 bool initialized;
771fe6b9
JG		 332};
333
334struct radeon_fence {
335 struct radeon_device *rdev;
336 struct kref kref;
771fe6b9 337 /* protected by radeon_fence.lock */
bb635567 338 uint64_t seq;
7465280c 339 /* RB, DMA, etc. */
bb635567 340 unsigned ring;
771fe6b9
JG		 341};
342
30eb77f4
JG		 343int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
344int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 345void radeon_fence_driver_fini(struct radeon_device *rdev);
76903b96 346void radeon_fence_driver_force_completion(struct radeon_device *rdev);
876dc9f3 347int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 348void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 349bool radeon_fence_signaled(struct radeon_fence *fence);
350int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
8a47cc9e 351int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
5f8f635e 352int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
0085c950
JG		 353int radeon_fence_wait_any(struct radeon_device *rdev,
354 struct radeon_fence **fences,
355 bool intr);
771fe6b9
JG		 356struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
357void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 358unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 359bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
360void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
361static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
362 struct radeon_fence *b)
363{
364 if (!a) {
365 return b;
366 }
367
368 if (!b) {
369 return a;
370 }
371
372 BUG_ON(a->ring != b->ring);
373
374 if (a->seq > b->seq) {
375 return a;
376 } else {
377 return b;
378 }
379}
771fe6b9 380
ee60e29f
CK		 381static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
382 struct radeon_fence *b)
383{
384 if (!a) {
385 return false;
386 }
387
388 if (!b) {
389 return true;
390 }
391
392 BUG_ON(a->ring != b->ring);
393
394 return a->seq < b->seq;
395}
396
e024e110
DA		 397/*
398 * Tiling registers
399 */
400struct radeon_surface_reg {
4c788679 401 struct radeon_bo *bo;
e024e110
DA		 402};
403
404#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 405
406/*
4c788679 407 * TTM.
771fe6b9 408 */
4c788679
JG		 409struct radeon_mman {
410 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 411 struct drm_global_reference mem_global_ref;
4c788679 412 struct ttm_bo_device bdev;
0a0c7596
JG		 413 bool mem_global_referenced;
414 bool initialized;
4c788679
JG		 415};
416
721604a1
JG		 417/* bo virtual address in a specific vm */
418struct radeon_bo_va {
e971bd5e 419 /* protected by bo being reserved */
721604a1 420 struct list_head bo_list;
721604a1
JG		 421 uint64_t soffset;
422 uint64_t eoffset;
423 uint32_t flags;
424 bool valid;
e971bd5e
CK		 425 unsigned ref_count;
426
427 /* protected by vm mutex */
428 struct list_head vm_list;
429
430 /* constant after initialization */
431 struct radeon_vm *vm;
432 struct radeon_bo *bo;
721604a1
JG		 433};
434
4c788679
JG		 435struct radeon_bo {
436 /* Protected by gem.mutex */
437 struct list_head list;
438 /* Protected by tbo.reserved */
312ea8da
JG		 439 u32 placements[3];
440 struct ttm_placement placement;
4c788679
JG		 441 struct ttm_buffer_object tbo;
442 struct ttm_bo_kmap_obj kmap;
443 unsigned pin_count;
444 void *kptr;
445 u32 tiling_flags;
446 u32 pitch;
447 int surface_reg;
721604a1
JG		 448 /* list of all virtual address to which this bo
449 * is associated to
450 */
451 struct list_head va;
4c788679
JG		 452 /* Constant after initialization */
453 struct radeon_device *rdev;
441921d5 454 struct drm_gem_object gem_base;
63bc620b 455
409851f4
JG		 456 struct ttm_bo_kmap_obj dma_buf_vmap;
457 pid_t pid;
4c788679 458};
7e4d15d9 459#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 460
4c788679 461struct radeon_bo_list {
147666fb 462 struct ttm_validate_buffer tv;
4c788679 463 struct radeon_bo *bo;
771fe6b9 464 uint64_t gpu_offset;
4474f3a9
CK		 465 bool written;
466 unsigned domain;
467 unsigned alt_domain;
4c788679 468 u32 tiling_flags;
771fe6b9
JG		 469};
470
409851f4
JG		 471int radeon_gem_debugfs_init(struct radeon_device *rdev);
472
b15ba512
JG		 473/* sub-allocation manager, it has to be protected by another lock.
474 * By conception this is an helper for other part of the driver
475 * like the indirect buffer or semaphore, which both have their
476 * locking.
477 *
478 * Principe is simple, we keep a list of sub allocation in offset
479 * order (first entry has offset == 0, last entry has the highest
480 * offset).
481 *
482 * When allocating new object we first check if there is room at
483 * the end total_size - (last_object_offset + last_object_size) >=
484 * alloc_size. If so we allocate new object there.
485 *
486 * When there is not enough room at the end, we start waiting for
487 * each sub object until we reach object_offset+object_size >=
488 * alloc_size, this object then become the sub object we return.
489 *
490 * Alignment can't be bigger than page size.
491 *
492 * Hole are not considered for allocation to keep things simple.
493 * Assumption is that there won't be hole (all object on same
494 * alignment).
495 */
496struct radeon_sa_manager {
bfb38d35 497 wait_queue_head_t wq;
b15ba512 498 struct radeon_bo *bo;
c3b7fe8b
CK		 499 struct list_head *hole;
500 struct list_head flist[RADEON_NUM_RINGS];
501 struct list_head olist;
b15ba512
JG		 502 unsigned size;
503 uint64_t gpu_addr;
504 void *cpu_ptr;
505 uint32_t domain;
6c4f978b 506 uint32_t align;
b15ba512
JG		 507};
508
509struct radeon_sa_bo;
510
511/* sub-allocation buffer */
512struct radeon_sa_bo {
c3b7fe8b
CK		 513 struct list_head olist;
514 struct list_head flist;
b15ba512 515 struct radeon_sa_manager *manager;
e6661a96
CK		 516 unsigned soffset;
517 unsigned eoffset;
557017a0 518 struct radeon_fence *fence;
b15ba512
JG		 519};
520
771fe6b9
JG		 521/*
522 * GEM objects.
523 */
524struct radeon_gem {
4c788679 525 struct mutex mutex;
771fe6b9
JG		 526 struct list_head objects;
527};
528
529int radeon_gem_init(struct radeon_device *rdev);
530void radeon_gem_fini(struct radeon_device *rdev);
531int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 532 int alignment, int initial_domain,
533 bool discardable, bool kernel,
534 struct drm_gem_object **obj);
771fe6b9 535
ff72145b
DA		 536int radeon_mode_dumb_create(struct drm_file *file_priv,
537 struct drm_device *dev,
538 struct drm_mode_create_dumb *args);
539int radeon_mode_dumb_mmap(struct drm_file *filp,
540 struct drm_device *dev,
541 uint32_t handle, uint64_t *offset_p);
771fe6b9 542
c1341e52
JG		 543/*
544 * Semaphores.
545 */
c1341e52
JG		 546/* everything here is constant */
547struct radeon_semaphore {
a8c05940
JG		 548 struct radeon_sa_bo *sa_bo;
549 signed waiters;
c1341e52 550 uint64_t gpu_addr;
c1341e52
JG		 551};
552
c1341e52
JG		 553int radeon_semaphore_create(struct radeon_device *rdev,
554 struct radeon_semaphore **semaphore);
555void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
556 struct radeon_semaphore *semaphore);
557void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
558 struct radeon_semaphore *semaphore);
8f676c4c
CK		 559int radeon_semaphore_sync_rings(struct radeon_device *rdev,
560 struct radeon_semaphore *semaphore,
220907d9 561 int signaler, int waiter);
c1341e52 562void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 563 struct radeon_semaphore **semaphore,
a8c05940 564 struct radeon_fence *fence);
c1341e52 565
771fe6b9
JG		 566/*
567 * GART structures, functions & helpers
568 */
569struct radeon_mc;
570
a77f1718 571#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 572#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 573#define RADEON_GPU_PAGE_SHIFT 12
721604a1 574#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 575
771fe6b9
JG		 576struct radeon_gart {
577 dma_addr_t table_addr;
c9a1be96
JG		 578 struct radeon_bo *robj;
579 void *ptr;
771fe6b9
JG		 580 unsigned num_gpu_pages;
581 unsigned num_cpu_pages;
582 unsigned table_size;
771fe6b9
JG		 583 struct page **pages;
584 dma_addr_t *pages_addr;
585 bool ready;
586};
587
588int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
589void radeon_gart_table_ram_free(struct radeon_device *rdev);
590int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
591void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 592int radeon_gart_table_vram_pin(struct radeon_device *rdev);
593void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 594int radeon_gart_init(struct radeon_device *rdev);
595void radeon_gart_fini(struct radeon_device *rdev);
596void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
597 int pages);
598int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516
KRW		 599 int pages, struct page **pagelist,
600 dma_addr_t *dma_addr);
c9a1be96 601void radeon_gart_restore(struct radeon_device *rdev);
771fe6b9
JG		 602
603
604/*
605 * GPU MC structures, functions & helpers
606 */
607struct radeon_mc {
608 resource_size_t aper_size;
609 resource_size_t aper_base;
610 resource_size_t agp_base;
7a50f01a
DA		 611 /* for some chips with <= 32MB we need to lie
612 * about vram size near mc fb location */
3ce0a23d 613 u64 mc_vram_size;
d594e46a 614 u64 visible_vram_size;
3ce0a23d
JG		 615 u64 gtt_size;
616 u64 gtt_start;
617 u64 gtt_end;
3ce0a23d
JG		 618 u64 vram_start;
619 u64 vram_end;
771fe6b9 620 unsigned vram_width;
3ce0a23d 621 u64 real_vram_size;
771fe6b9
JG		 622 int vram_mtrr;
623 bool vram_is_ddr;
d594e46a 624 bool igp_sideport_enabled;
8d369bb1 625 u64 gtt_base_align;
9ed8b1f9 626 u64 mc_mask;
771fe6b9
JG		 627};
628
06b6476d
AD		 629bool radeon_combios_sideport_present(struct radeon_device *rdev);
630bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 631
632/*
633 * GPU scratch registers structures, functions & helpers
634 */
635struct radeon_scratch {
636 unsigned num_reg;
724c80e1 637 uint32_t reg_base;
771fe6b9
JG		 638 bool free[32];
639 uint32_t reg[32];
640};
641
642int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
643void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
644
75efdee1
AD		 645/*
646 * GPU doorbell structures, functions & helpers
647 */
648struct radeon_doorbell {
649 u32 num_pages;
650 bool free[1024];
651 /* doorbell mmio */
652 resource_size_t base;
653 resource_size_t size;
654 void __iomem *ptr;
655};
656
657int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
658void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771fe6b9
JG		 659
660/*
661 * IRQS.
662 */
6f34be50
AD		 663
664struct radeon_unpin_work {
665 struct work_struct work;
666 struct radeon_device *rdev;
667 int crtc_id;
668 struct radeon_fence *fence;
669 struct drm_pending_vblank_event *event;
670 struct radeon_bo *old_rbo;
671 u64 new_crtc_base;
672};
673
674struct r500_irq_stat_regs {
675 u32 disp_int;
f122c610 676 u32 hdmi0_status;
6f34be50
AD		 677};
678
679struct r600_irq_stat_regs {
680 u32 disp_int;
681 u32 disp_int_cont;
682 u32 disp_int_cont2;
683 u32 d1grph_int;
684 u32 d2grph_int;
f122c610
AD		 685 u32 hdmi0_status;
686 u32 hdmi1_status;
6f34be50
AD		 687};
688
689struct evergreen_irq_stat_regs {
690 u32 disp_int;
691 u32 disp_int_cont;
692 u32 disp_int_cont2;
693 u32 disp_int_cont3;
694 u32 disp_int_cont4;
695 u32 disp_int_cont5;
696 u32 d1grph_int;
697 u32 d2grph_int;
698 u32 d3grph_int;
699 u32 d4grph_int;
700 u32 d5grph_int;
701 u32 d6grph_int;
f122c610
AD		 702 u32 afmt_status1;
703 u32 afmt_status2;
704 u32 afmt_status3;
705 u32 afmt_status4;
706 u32 afmt_status5;
707 u32 afmt_status6;
6f34be50
AD		 708};
709
a59781bb
AD		 710struct cik_irq_stat_regs {
711 u32 disp_int;
712 u32 disp_int_cont;
713 u32 disp_int_cont2;
714 u32 disp_int_cont3;
715 u32 disp_int_cont4;
716 u32 disp_int_cont5;
717 u32 disp_int_cont6;
718};
719
6f34be50
AD		 720union radeon_irq_stat_regs {
721 struct r500_irq_stat_regs r500;
722 struct r600_irq_stat_regs r600;
723 struct evergreen_irq_stat_regs evergreen;
a59781bb 724 struct cik_irq_stat_regs cik;
6f34be50
AD		 725};
726
54bd5206
IH		 727#define RADEON_MAX_HPD_PINS 6
728#define RADEON_MAX_CRTCS 6
b530602f 729#define RADEON_MAX_AFMT_BLOCKS 7
54bd5206 730
771fe6b9 731struct radeon_irq {
fb98257a
CK		 732 bool installed;
733 spinlock_t lock;
736fc37f 734 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 735 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 736 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 737 wait_queue_head_t vblank_queue;
738 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 739 bool afmt[RADEON_MAX_AFMT_BLOCKS];
740 union radeon_irq_stat_regs stat_regs;
4a6369e9 741 bool dpm_thermal;
771fe6b9
JG		 742};
743
744int radeon_irq_kms_init(struct radeon_device *rdev);
745void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b
AD		 746void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
747void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 748void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
749void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 750void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
751void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
752void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
753void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 754
755/*
e32eb50d 756 * CP & rings.
771fe6b9 757 */
7465280c 758
771fe6b9 759struct radeon_ib {
68470ae7
JG		 760 struct radeon_sa_bo *sa_bo;
761 uint32_t length_dw;
762 uint64_t gpu_addr;
763 uint32_t *ptr;
876dc9f3 764 int ring;
68470ae7 765 struct radeon_fence *fence;
4bf3dd92 766 struct radeon_vm *vm;
68470ae7 767 bool is_const_ib;
220907d9 768 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
68470ae7 769 struct radeon_semaphore *semaphore;
771fe6b9
JG		 770};
771
e32eb50d 772struct radeon_ring {
4c788679 773 struct radeon_bo *ring_obj;
771fe6b9
JG		 774 volatile uint32_t *ring;
775 unsigned rptr;
5596a9db
CK		 776 unsigned rptr_offs;
777 unsigned rptr_reg;
45df6803 778 unsigned rptr_save_reg;
89d35807
AD		 779 u64 next_rptr_gpu_addr;
780 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 781 unsigned wptr;
782 unsigned wptr_old;
5596a9db 783 unsigned wptr_reg;
771fe6b9
JG		 784 unsigned ring_size;
785 unsigned ring_free_dw;
786 int count_dw;
069211e5
CK		 787 unsigned long last_activity;
788 unsigned last_rptr;
771fe6b9
JG		 789 uint64_t gpu_addr;
790 uint32_t align_mask;
791 uint32_t ptr_mask;
771fe6b9 792 bool ready;
78c5560a 793 u32 nop;
8b25ed34 794 u32 idx;
5f0839c1
JG		 795 u64 last_semaphore_signal_addr;
796 u64 last_semaphore_wait_addr;
963e81f9
AD		 797 /* for CIK queues */
798 u32 me;
799 u32 pipe;
800 u32 queue;
801 struct radeon_bo *mqd_obj;
802 u32 doorbell_page_num;
803 u32 doorbell_offset;
804 unsigned wptr_offs;
805};
806
807struct radeon_mec {
808 struct radeon_bo *hpd_eop_obj;
809 u64 hpd_eop_gpu_addr;
810 u32 num_pipe;
811 u32 num_mec;
812 u32 num_queue;
771fe6b9
JG		 813};
814
721604a1
JG		 815/*
816 * VM
817 */
ee60e29f 818
fa87e62d 819/* maximum number of VMIDs */
ee60e29f
CK		 820#define RADEON_NUM_VM 16
821
fa87e62d
DC		 822/* defines number of bits in page table versus page directory,
823 * a page is 4KB so we have 12 bits offset, 9 bits in the page
824 * table and the remaining 19 bits are in the page directory */
825#define RADEON_VM_BLOCK_SIZE 9
826
827/* number of entries in page table */
828#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
829
1c01103c
AD		 830/* PTBs (Page Table Blocks) need to be aligned to 32K */
831#define RADEON_VM_PTB_ALIGN_SIZE 32768
832#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
833#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
834
721604a1
JG		 835struct radeon_vm {
836 struct list_head list;
837 struct list_head va;
ee60e29f 838 unsigned id;
90a51a32
CK		 839
840 /* contains the page directory */
841 struct radeon_sa_bo *page_directory;
842 uint64_t pd_gpu_addr;
843
844 /* array of page tables, one for each page directory entry */
845 struct radeon_sa_bo **page_tables;
846
721604a1
JG		 847 struct mutex mutex;
848 /* last fence for cs using this vm */
849 struct radeon_fence *fence;
9b40e5d8
CK		 850 /* last flush or NULL if we still need to flush */
851 struct radeon_fence *last_flush;
721604a1
JG		 852};
853
721604a1 854struct radeon_vm_manager {
36ff39c4 855 struct mutex lock;
721604a1 856 struct list_head lru_vm;
ee60e29f 857 struct radeon_fence *active[RADEON_NUM_VM];
721604a1
JG		 858 struct radeon_sa_manager sa_manager;
859 uint32_t max_pfn;
721604a1
JG		 860 /* number of VMIDs */
861 unsigned nvm;
862 /* vram base address for page table entry */
863 u64 vram_base_offset;
67e915e4
AD		 864 /* is vm enabled? */
865 bool enabled;
721604a1
JG		 866};
867
868/*
869 * file private structure
870 */
871struct radeon_fpriv {
872 struct radeon_vm vm;
873};
874
d8f60cfc
AD		 875/*
876 * R6xx+ IH ring
877 */
878struct r600_ih {
4c788679 879 struct radeon_bo *ring_obj;
d8f60cfc
AD		 880 volatile uint32_t *ring;
881 unsigned rptr;
d8f60cfc
AD		 882 unsigned ring_size;
883 uint64_t gpu_addr;
d8f60cfc 884 uint32_t ptr_mask;
c20dc369 885 atomic_t lock;
d8f60cfc
AD		 886 bool enabled;
887};
888
347e7592 889/*
2948f5e6 890 * RLC stuff
347e7592 891 */
2948f5e6
AD		 892#include "clearstate_defs.h"
893
894struct radeon_rlc {
347e7592
AD		 895 /* for power gating */
896 struct radeon_bo *save_restore_obj;
897 uint64_t save_restore_gpu_addr;
2948f5e6 898 volatile uint32_t *sr_ptr;
1fd11777 899 const u32 *reg_list;
2948f5e6 900 u32 reg_list_size;
347e7592
AD		 901 /* for clear state */
902 struct radeon_bo *clear_state_obj;
903 uint64_t clear_state_gpu_addr;
2948f5e6 904 volatile uint32_t *cs_ptr;
1fd11777 905 const struct cs_section_def *cs_data;
22c775ce
AD		 906 u32 clear_state_size;
907 /* for cp tables */
908 struct radeon_bo *cp_table_obj;
909 uint64_t cp_table_gpu_addr;
910 volatile uint32_t *cp_table_ptr;
911 u32 cp_table_size;
347e7592
AD		 912};
913
69e130a6 914int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 915 struct radeon_ib *ib, struct radeon_vm *vm,
916 unsigned size);
f2e39221 917void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
43f1214a 918void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
4ef72566
CK		 919int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
920 struct radeon_ib *const_ib);
771fe6b9
JG		 921int radeon_ib_pool_init(struct radeon_device *rdev);
922void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 923int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 924/* Ring access between begin & end cannot sleep */
89d35807
AD		 925bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
926 struct radeon_ring *ring);
e32eb50d
CK		 927void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
928int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
929int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
930void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
931void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
d6999bc7 932void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 933void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
934int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
7b9ef16b 935void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
069211e5
CK		 936void radeon_ring_lockup_update(struct radeon_ring *ring);
937bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 938unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
939 uint32_t **data);
940int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
941 unsigned size, uint32_t *data);
e32eb50d 942int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
2e1e6dad 943 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, u32 nop);
e32eb50d 944void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 945
946
4d75658b
AD		 947/* r600 async dma */
948void r600_dma_stop(struct radeon_device *rdev);
949int r600_dma_resume(struct radeon_device *rdev);
950void r600_dma_fini(struct radeon_device *rdev);
951
8c5fd7ef
AD		 952void cayman_dma_stop(struct radeon_device *rdev);
953int cayman_dma_resume(struct radeon_device *rdev);
954void cayman_dma_fini(struct radeon_device *rdev);
955
771fe6b9
JG		 956/*
957 * CS.
958 */
959struct radeon_cs_reloc {
960 struct drm_gem_object *gobj;
4c788679
JG		 961 struct radeon_bo *robj;
962 struct radeon_bo_list lobj;
771fe6b9
JG		 963 uint32_t handle;
964 uint32_t flags;
965};
966
967struct radeon_cs_chunk {
968 uint32_t chunk_id;
969 uint32_t length_dw;
721604a1
JG		 970 int kpage_idx[2];
971 uint32_t *kpage[2];
771fe6b9 972 uint32_t *kdata;
721604a1
JG		 973 void __user *user_ptr;
974 int last_copied_page;
975 int last_page_index;
771fe6b9
JG		 976};
977
978struct radeon_cs_parser {
c8c15ff1 979 struct device *dev;
771fe6b9
JG		 980 struct radeon_device *rdev;
981 struct drm_file *filp;
982 /* chunks */
983 unsigned nchunks;
984 struct radeon_cs_chunk *chunks;
985 uint64_t *chunks_array;
986 /* IB */
987 unsigned idx;
988 /* relocations */
989 unsigned nrelocs;
990 struct radeon_cs_reloc *relocs;
991 struct radeon_cs_reloc **relocs_ptr;
992 struct list_head validated;
cf4ccd01 993 unsigned dma_reloc_idx;
771fe6b9
JG		 994 /* indices of various chunks */
995 int chunk_ib_idx;
996 int chunk_relocs_idx;
721604a1 997 int chunk_flags_idx;
dfcf5f36 998 int chunk_const_ib_idx;
f2e39221
JG		 999 struct radeon_ib ib;
1000 struct radeon_ib const_ib;
771fe6b9 1001 void *track;
3ce0a23d 1002 unsigned family;
e70f224c 1003 int parser_error;
721604a1
JG		 1004 u32 cs_flags;
1005 u32 ring;
1006 s32 priority;
ecff665f 1007 struct ww_acquire_ctx ticket;
771fe6b9
JG		 1008};
1009
513bcb46 1010extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
ce580fab 1011extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
513bcb46 1012
771fe6b9
JG		 1013struct radeon_cs_packet {
1014 unsigned idx;
1015 unsigned type;
1016 unsigned reg;
1017 unsigned opcode;
1018 int count;
1019 unsigned one_reg_wr;
1020};
1021
1022typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1023 struct radeon_cs_packet *pkt,
1024 unsigned idx, unsigned reg);
1025typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1026 struct radeon_cs_packet *pkt);
1027
1028
1029/*
1030 * AGP
1031 */
1032int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1033void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1034void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1035void radeon_agp_fini(struct radeon_device *rdev);
1036
1037
1038/*
1039 * Writeback
1040 */
1041struct radeon_wb {
4c788679 1042 struct radeon_bo *wb_obj;
771fe6b9
JG		 1043 volatile uint32_t *wb;
1044 uint64_t gpu_addr;
724c80e1 1045 bool enabled;
d0f8a854 1046 bool use_event;
771fe6b9
JG		 1047};
1048
724c80e1 1049#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1050#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1051#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1052#define RADEON_WB_CP1_RPTR_OFFSET 1280
1053#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1054#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1055#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1056#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1057#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1058#define CIK_WB_CP1_WPTR_OFFSET 3328
1059#define CIK_WB_CP2_WPTR_OFFSET 3584
724c80e1 1060
c93bb85b
JG		 1061/**
1062 * struct radeon_pm - power management datas
1063 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1064 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1065 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1066 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1067 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1068 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1069 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1070 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1071 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1072 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1073 * @needed_bandwidth: current bandwidth needs
1074 *
1075 * It keeps track of various data needed to take powermanagement decision.
25985edc 1076 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1077 * Equation between gpu/memory clock and available bandwidth is hw dependent
1078 * (type of memory, bus size, efficiency, ...)
1079 */
ce8f5370
AD		 1080
1081enum radeon_pm_method {
1082 PM_METHOD_PROFILE,
1083 PM_METHOD_DYNPM,
da321c8a 1084 PM_METHOD_DPM,
ce8f5370
AD		 1085};
1086
1087enum radeon_dynpm_state {
1088 DYNPM_STATE_DISABLED,
1089 DYNPM_STATE_MINIMUM,
1090 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1091 DYNPM_STATE_ACTIVE,
1092 DYNPM_STATE_SUSPENDED,
c913e23a 1093};
ce8f5370
AD		 1094enum radeon_dynpm_action {
1095 DYNPM_ACTION_NONE,
1096 DYNPM_ACTION_MINIMUM,
1097 DYNPM_ACTION_DOWNCLOCK,
1098 DYNPM_ACTION_UPCLOCK,
1099 DYNPM_ACTION_DEFAULT
c913e23a 1100};
56278a8e
AD		 1101
1102enum radeon_voltage_type {
1103 VOLTAGE_NONE = 0,
1104 VOLTAGE_GPIO,
1105 VOLTAGE_VDDC,
1106 VOLTAGE_SW
1107};
1108
0ec0e74f 1109enum radeon_pm_state_type {
da321c8a 1110 /* not used for dpm */
0ec0e74f
AD		 1111 POWER_STATE_TYPE_DEFAULT,
1112 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1113 /* user selectable states */
0ec0e74f
AD		 1114 POWER_STATE_TYPE_BATTERY,
1115 POWER_STATE_TYPE_BALANCED,
1116 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1117 /* internal states */
1118 POWER_STATE_TYPE_INTERNAL_UVD,
1119 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1120 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1121 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1122 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1123 POWER_STATE_TYPE_INTERNAL_BOOT,
1124 POWER_STATE_TYPE_INTERNAL_THERMAL,
1125 POWER_STATE_TYPE_INTERNAL_ACPI,
1126 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1127 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1128};
1129
ce8f5370
AD		 1130enum radeon_pm_profile_type {
1131 PM_PROFILE_DEFAULT,
1132 PM_PROFILE_AUTO,
1133 PM_PROFILE_LOW,
c9e75b21 1134 PM_PROFILE_MID,
ce8f5370
AD		 1135 PM_PROFILE_HIGH,
1136};
1137
1138#define PM_PROFILE_DEFAULT_IDX 0
1139#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1140#define PM_PROFILE_MID_SH_IDX 2
1141#define PM_PROFILE_HIGH_SH_IDX 3
1142#define PM_PROFILE_LOW_MH_IDX 4
1143#define PM_PROFILE_MID_MH_IDX 5
1144#define PM_PROFILE_HIGH_MH_IDX 6
1145#define PM_PROFILE_MAX 7
ce8f5370
AD		 1146
1147struct radeon_pm_profile {
1148 int dpms_off_ps_idx;
1149 int dpms_on_ps_idx;
1150 int dpms_off_cm_idx;
1151 int dpms_on_cm_idx;
516d0e46
AD		 1152};
1153
21a8122a
AD		 1154enum radeon_int_thermal_type {
1155 THERMAL_TYPE_NONE,
da321c8a
AD		 1156 THERMAL_TYPE_EXTERNAL,
1157 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1158 THERMAL_TYPE_RV6XX,
1159 THERMAL_TYPE_RV770,
da321c8a 1160 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1161 THERMAL_TYPE_EVERGREEN,
e33df25f 1162 THERMAL_TYPE_SUMO,
4fddba1f 1163 THERMAL_TYPE_NI,
14607d08 1164 THERMAL_TYPE_SI,
da321c8a 1165 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1166 THERMAL_TYPE_CI,
16fbe00d 1167 THERMAL_TYPE_KV,
21a8122a
AD		 1168};
1169
56278a8e
AD		 1170struct radeon_voltage {
1171 enum radeon_voltage_type type;
1172 /* gpio voltage */
1173 struct radeon_gpio_rec gpio;
1174 u32 delay; /* delay in usec from voltage drop to sclk change */
1175 bool active_high; /* voltage drop is active when bit is high */
1176 /* VDDC voltage */
1177 u8 vddc_id; /* index into vddc voltage table */
1178 u8 vddci_id; /* index into vddci voltage table */
1179 bool vddci_enabled;
1180 /* r6xx+ sw */
2feea49a
AD		 1181 u16 voltage;
1182 /* evergreen+ vddci */
1183 u16 vddci;
56278a8e
AD		 1184};
1185
d7311171
AD		 1186/* clock mode flags */
1187#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1188
56278a8e
AD		 1189struct radeon_pm_clock_info {
1190 /* memory clock */
1191 u32 mclk;
1192 /* engine clock */
1193 u32 sclk;
1194 /* voltage info */
1195 struct radeon_voltage voltage;
d7311171 1196 /* standardized clock flags */
56278a8e
AD		 1197 u32 flags;
1198};
1199
a48b9b4e 1200/* state flags */
d7311171 1201#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1202
56278a8e 1203struct radeon_power_state {
0ec0e74f 1204 enum radeon_pm_state_type type;
8f3f1c9a 1205 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1206 /* number of valid clock modes in this power state */
1207 int num_clock_modes;
56278a8e 1208 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1209 /* standardized state flags */
1210 u32 flags;
79daedc9
AD		 1211 u32 misc; /* vbios specific flags */
1212 u32 misc2; /* vbios specific flags */
1213 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1214};
1215
27459324
RM		 1216/*
1217 * Some modes are overclocked by very low value, accept them
1218 */
1219#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1220
2e9d4c05
AD		 1221enum radeon_dpm_auto_throttle_src {
1222 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1223 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1224};
1225
1226enum radeon_dpm_event_src {
1227 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1228 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1229 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1230 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1231 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1232};
1233
da321c8a
AD		 1234struct radeon_ps {
1235 u32 caps; /* vbios flags */
1236 u32 class; /* vbios flags */
1237 u32 class2; /* vbios flags */
1238 /* UVD clocks */
1239 u32 vclk;
1240 u32 dclk;
c4453e66
AD		 1241 /* VCE clocks */
1242 u32 evclk;
1243 u32 ecclk;
da321c8a
AD		 1244 /* asic priv */
1245 void *ps_priv;
1246};
1247
1248struct radeon_dpm_thermal {
1249 /* thermal interrupt work */
1250 struct work_struct work;
1251 /* low temperature threshold */
1252 int min_temp;
1253 /* high temperature threshold */
1254 int max_temp;
1255 /* was interrupt low to high or high to low */
1256 bool high_to_low;
1257};
1258
d22b7e40
AD		 1259enum radeon_clk_action
1260{
1261 RADEON_SCLK_UP = 1,
1262 RADEON_SCLK_DOWN
1263};
1264
1265struct radeon_blacklist_clocks
1266{
1267 u32 sclk;
1268 u32 mclk;
1269 enum radeon_clk_action action;
1270};
1271
61b7d601
AD		 1272struct radeon_clock_and_voltage_limits {
1273 u32 sclk;
1274 u32 mclk;
1275 u32 vddc;
1276 u32 vddci;
1277};
1278
1279struct radeon_clock_array {
1280 u32 count;
1281 u32 *values;
1282};
1283
1284struct radeon_clock_voltage_dependency_entry {
1285 u32 clk;
1286 u16 v;
1287};
1288
1289struct radeon_clock_voltage_dependency_table {
1290 u32 count;
1291 struct radeon_clock_voltage_dependency_entry *entries;
1292};
1293
ef976ec4
AD		 1294union radeon_cac_leakage_entry {
1295 struct {
1296 u16 vddc;
1297 u32 leakage;
1298 };
1299 struct {
1300 u16 vddc1;
1301 u16 vddc2;
1302 u16 vddc3;
1303 };
61b7d601
AD		 1304};
1305
1306struct radeon_cac_leakage_table {
1307 u32 count;
ef976ec4 1308 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1309};
1310
929ee7a8
AD		 1311struct radeon_phase_shedding_limits_entry {
1312 u16 voltage;
1313 u32 sclk;
1314 u32 mclk;
1315};
1316
1317struct radeon_phase_shedding_limits_table {
1318 u32 count;
1319 struct radeon_phase_shedding_limits_entry *entries;
1320};
1321
84a9d9ee
AD		 1322struct radeon_uvd_clock_voltage_dependency_entry {
1323 u32 vclk;
1324 u32 dclk;
1325 u16 v;
1326};
1327
1328struct radeon_uvd_clock_voltage_dependency_table {
1329 u8 count;
1330 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1331};
1332
d29f013b
AD		 1333struct radeon_vce_clock_voltage_dependency_entry {
1334 u32 ecclk;
1335 u32 evclk;
1336 u16 v;
1337};
1338
1339struct radeon_vce_clock_voltage_dependency_table {
1340 u8 count;
1341 struct radeon_vce_clock_voltage_dependency_entry *entries;
1342};
1343
a5cb318e
AD		 1344struct radeon_ppm_table {
1345 u8 ppm_design;
1346 u16 cpu_core_number;
1347 u32 platform_tdp;
1348 u32 small_ac_platform_tdp;
1349 u32 platform_tdc;
1350 u32 small_ac_platform_tdc;
1351 u32 apu_tdp;
1352 u32 dgpu_tdp;
1353 u32 dgpu_ulv_power;
1354 u32 tj_max;
1355};
1356
58cb7632
AD		 1357struct radeon_cac_tdp_table {
1358 u16 tdp;
1359 u16 configurable_tdp;
1360 u16 tdc;
1361 u16 battery_power_limit;
1362 u16 small_power_limit;
1363 u16 low_cac_leakage;
1364 u16 high_cac_leakage;
1365 u16 maximum_power_delivery_limit;
1366};
1367
61b7d601
AD		 1368struct radeon_dpm_dynamic_state {
1369 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1370 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1371 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1372 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1373 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1374 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1375 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1376 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1377 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1378 struct radeon_clock_array valid_sclk_values;
1379 struct radeon_clock_array valid_mclk_values;
1380 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1381 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1382 u32 mclk_sclk_ratio;
1383 u32 sclk_mclk_delta;
1384 u16 vddc_vddci_delta;
1385 u16 min_vddc_for_pcie_gen2;
1386 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1387 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1388 struct radeon_ppm_table *ppm_table;
58cb7632 1389 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1390};
1391
1392struct radeon_dpm_fan {
1393 u16 t_min;
1394 u16 t_med;
1395 u16 t_high;
1396 u16 pwm_min;
1397 u16 pwm_med;
1398 u16 pwm_high;
1399 u8 t_hyst;
1400 u32 cycle_delay;
1401 u16 t_max;
1402 bool ucode_fan_control;
1403};
1404
32ce4652
AD		 1405enum radeon_pcie_gen {
1406 RADEON_PCIE_GEN1 = 0,
1407 RADEON_PCIE_GEN2 = 1,
1408 RADEON_PCIE_GEN3 = 2,
1409 RADEON_PCIE_GEN_INVALID = 0xffff
1410};
1411
70d01a5e
AD		 1412enum radeon_dpm_forced_level {
1413 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1414 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1415 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1416};
1417
da321c8a
AD		 1418struct radeon_dpm {
1419 struct radeon_ps *ps;
1420 /* number of valid power states */
1421 int num_ps;
1422 /* current power state that is active */
1423 struct radeon_ps *current_ps;
1424 /* requested power state */
1425 struct radeon_ps *requested_ps;
1426 /* boot up power state */
1427 struct radeon_ps *boot_ps;
1428 /* default uvd power state */
1429 struct radeon_ps *uvd_ps;
1430 enum radeon_pm_state_type state;
1431 enum radeon_pm_state_type user_state;
1432 u32 platform_caps;
1433 u32 voltage_response_time;
1434 u32 backbias_response_time;
1435 void *priv;
1436 u32 new_active_crtcs;
1437 int new_active_crtc_count;
1438 u32 current_active_crtcs;
1439 int current_active_crtc_count;
61b7d601
AD		 1440 struct radeon_dpm_dynamic_state dyn_state;
1441 struct radeon_dpm_fan fan;
1442 u32 tdp_limit;
1443 u32 near_tdp_limit;
a9e61410 1444 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1445 u32 sq_ramping_threshold;
1446 u32 cac_leakage;
1447 u16 tdp_od_limit;
1448 u32 tdp_adjustment;
1449 u16 load_line_slope;
1450 bool power_control;
5ca302f7 1451 bool ac_power;
da321c8a
AD		 1452 /* special states active */
1453 bool thermal_active;
8a227555 1454 bool uvd_active;
da321c8a
AD		 1455 /* thermal handling */
1456 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1457 /* forced levels */
1458 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1459 /* track UVD streams */
1460 unsigned sd;
1461 unsigned hd;
da321c8a
AD		 1462};
1463
ce3537d5 1464void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
da321c8a 1465
c93bb85b 1466struct radeon_pm {
c913e23a 1467 struct mutex mutex;
db7fce39
CK		 1468 /* write locked while reprogramming mclk */
1469 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1470 u32 active_crtcs;
1471 int active_crtc_count;
c913e23a 1472 int req_vblank;
839461d3 1473 bool vblank_sync;
c93bb85b
JG		 1474 fixed20_12 max_bandwidth;
1475 fixed20_12 igp_sideport_mclk;
1476 fixed20_12 igp_system_mclk;
1477 fixed20_12 igp_ht_link_clk;
1478 fixed20_12 igp_ht_link_width;
1479 fixed20_12 k8_bandwidth;
1480 fixed20_12 sideport_bandwidth;
1481 fixed20_12 ht_bandwidth;
1482 fixed20_12 core_bandwidth;
1483 fixed20_12 sclk;
f47299c5 1484 fixed20_12 mclk;
c93bb85b 1485 fixed20_12 needed_bandwidth;
0975b162 1486 struct radeon_power_state *power_state;
56278a8e
AD		 1487 /* number of valid power states */
1488 int num_power_states;
a48b9b4e
AD		 1489 int current_power_state_index;
1490 int current_clock_mode_index;
1491 int requested_power_state_index;
1492 int requested_clock_mode_index;
1493 int default_power_state_index;
1494 u32 current_sclk;
1495 u32 current_mclk;
2feea49a
AD		 1496 u16 current_vddc;
1497 u16 current_vddci;
9ace9f7b
AD		 1498 u32 default_sclk;
1499 u32 default_mclk;
2feea49a
AD		 1500 u16 default_vddc;
1501 u16 default_vddci;
29fb52ca 1502 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1503 /* selected pm method */
1504 enum radeon_pm_method pm_method;
1505 /* dynpm power management */
1506 struct delayed_work dynpm_idle_work;
1507 enum radeon_dynpm_state dynpm_state;
1508 enum radeon_dynpm_action dynpm_planned_action;
1509 unsigned long dynpm_action_timeout;
1510 bool dynpm_can_upclock;
1511 bool dynpm_can_downclock;
1512 /* profile-based power management */
1513 enum radeon_pm_profile_type profile;
1514 int profile_index;
1515 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1516 /* internal thermal controller on rv6xx+ */
1517 enum radeon_int_thermal_type int_thermal_type;
1518 struct device *int_hwmon_dev;
da321c8a
AD		 1519 /* dpm */
1520 bool dpm_enabled;
1521 struct radeon_dpm dpm;
c93bb85b
JG		 1522};
1523
a4c9e2ee
AD		 1524int radeon_pm_get_type_index(struct radeon_device *rdev,
1525 enum radeon_pm_state_type ps_type,
1526 int instance);
f2ba57b5
CK		 1527/*
1528 * UVD
1529 */
1530#define RADEON_MAX_UVD_HANDLES 10
1531#define RADEON_UVD_STACK_SIZE (1024*1024)
1532#define RADEON_UVD_HEAP_SIZE (1024*1024)
1533
1534struct radeon_uvd {
1535 struct radeon_bo *vcpu_bo;
1536 void *cpu_addr;
1537 uint64_t gpu_addr;
9cc2e0e9 1538 void *saved_bo;
f2ba57b5
CK		 1539 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1540 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1541 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1542 struct delayed_work idle_work;
f2ba57b5
CK		 1543};
1544
1545int radeon_uvd_init(struct radeon_device *rdev);
1546void radeon_uvd_fini(struct radeon_device *rdev);
1547int radeon_uvd_suspend(struct radeon_device *rdev);
1548int radeon_uvd_resume(struct radeon_device *rdev);
1549int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1550 uint32_t handle, struct radeon_fence **fence);
1551int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1552 uint32_t handle, struct radeon_fence **fence);
1553void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1554void radeon_uvd_free_handles(struct radeon_device *rdev,
1555 struct drm_file *filp);
1556int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1557void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1558int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1559 unsigned vclk, unsigned dclk,
1560 unsigned vco_min, unsigned vco_max,
1561 unsigned fb_factor, unsigned fb_mask,
1562 unsigned pd_min, unsigned pd_max,
1563 unsigned pd_even,
1564 unsigned *optimal_fb_div,
1565 unsigned *optimal_vclk_div,
1566 unsigned *optimal_dclk_div);
1567int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1568 unsigned cg_upll_func_cntl);
771fe6b9 1569
b530602f 1570struct r600_audio_pin {
a92553ab
RM		 1571 int channels;
1572 int rate;
1573 int bits_per_sample;
1574 u8 status_bits;
1575 u8 category_code;
b530602f
AD		 1576 u32 offset;
1577 bool connected;
1578 u32 id;
1579};
1580
1581struct r600_audio {
1582 bool enabled;
1583 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1584 int num_pins;
a92553ab
RM		 1585};
1586
771fe6b9
JG		 1587/*
1588 * Benchmarking
1589 */
638dd7db 1590void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1591
1592
ecc0b326
MD		 1593/*
1594 * Testing
1595 */
1596void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1597void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1598 struct radeon_ring *cpA,
1599 struct radeon_ring *cpB);
60a7e396 1600void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326
MD		 1601
1602
771fe6b9
JG		 1603/*
1604 * Debugfs
1605 */
4d8bf9ae
CK		 1606struct radeon_debugfs {
1607 struct drm_info_list *files;
1608 unsigned num_files;
1609};
1610
771fe6b9
JG		 1611int radeon_debugfs_add_files(struct radeon_device *rdev,
1612 struct drm_info_list *files,
1613 unsigned nfiles);
1614int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1615
76a0df85
CK		 1616/*
1617 * ASIC ring specific functions.
1618 */
1619struct radeon_asic_ring {
1620 /* ring read/write ptr handling */
1621 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1622 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1623 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1624
1625 /* validating and patching of IBs */
1626 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1627 int (*cs_parse)(struct radeon_cs_parser *p);
1628
1629 /* command emmit functions */
1630 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1631 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1632 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1633 struct radeon_semaphore *semaphore, bool emit_wait);
1634 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1635
1636 /* testing functions */
1637 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1638 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1639 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1640
1641 /* deprecated */
1642 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1643};
771fe6b9
JG		 1644
1645/*
1646 * ASIC specific functions.
1647 */
1648struct radeon_asic {
068a117c 1649 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1650 void (*fini)(struct radeon_device *rdev);
1651 int (*resume)(struct radeon_device *rdev);
1652 int (*suspend)(struct radeon_device *rdev);
28d52043 1653 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1654 int (*asic_reset)(struct radeon_device *rdev);
54e88e06
AD		 1655 /* ioctl hw specific callback. Some hw might want to perform special
1656 * operation on specific ioctl. For instance on wait idle some hw
1657 * might want to perform and HDP flush through MMIO as it seems that
1658 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1659 * through ring.
1660 */
1661 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1662 /* check if 3D engine is idle */
1663 bool (*gui_idle)(struct radeon_device *rdev);
1664 /* wait for mc_idle */
1665 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1666 /* get the reference clock */
1667 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1668 /* get the gpu clock counter */
1669 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1670 /* gart */
c5b3b850
AD		 1671 struct {
1672 void (*tlb_flush)(struct radeon_device *rdev);
1673 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1674 } gart;
05b07147
CK		 1675 struct {
1676 int (*init)(struct radeon_device *rdev);
1677 void (*fini)(struct radeon_device *rdev);
2a6f1abb
CK		 1678
1679 u32 pt_ring_index;
43f1214a
AD		 1680 void (*set_page)(struct radeon_device *rdev,
1681 struct radeon_ib *ib,
1682 uint64_t pe,
dce34bfd
CK		 1683 uint64_t addr, unsigned count,
1684 uint32_t incr, uint32_t flags);
05b07147 1685 } vm;
54e88e06 1686 /* ring specific callbacks */
76a0df85 1687 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1688 /* irqs */
b35ea4ab
AD		 1689 struct {
1690 int (*set)(struct radeon_device *rdev);
1691 int (*process)(struct radeon_device *rdev);
1692 } irq;
54e88e06 1693 /* displays */
c79a49ca
AD		 1694 struct {
1695 /* display watermarks */
1696 void (*bandwidth_update)(struct radeon_device *rdev);
1697 /* get frame count */
1698 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1699 /* wait for vblank */
1700 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1701 /* set backlight level */
1702 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1703 /* get backlight level */
1704 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1705 /* audio callbacks */
1706 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1707 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1708 } display;
54e88e06 1709 /* copy functions for bo handling */
27cd7769
AD		 1710 struct {
1711 int (*blit)(struct radeon_device *rdev,
1712 uint64_t src_offset,
1713 uint64_t dst_offset,
1714 unsigned num_gpu_pages,
876dc9f3 1715 struct radeon_fence **fence);
27cd7769
AD		 1716 u32 blit_ring_index;
1717 int (*dma)(struct radeon_device *rdev,
1718 uint64_t src_offset,
1719 uint64_t dst_offset,
1720 unsigned num_gpu_pages,
876dc9f3 1721 struct radeon_fence **fence);
27cd7769
AD		 1722 u32 dma_ring_index;
1723 /* method used for bo copy */
1724 int (*copy)(struct radeon_device *rdev,
1725 uint64_t src_offset,
1726 uint64_t dst_offset,
1727 unsigned num_gpu_pages,
876dc9f3 1728 struct radeon_fence **fence);
27cd7769
AD		 1729 /* ring used for bo copies */
1730 u32 copy_ring_index;
1731 } copy;
54e88e06 1732 /* surfaces */
9e6f3d02
AD		 1733 struct {
1734 int (*set_reg)(struct radeon_device *rdev, int reg,
1735 uint32_t tiling_flags, uint32_t pitch,
1736 uint32_t offset, uint32_t obj_size);
1737 void (*clear_reg)(struct radeon_device *rdev, int reg);
1738 } surface;
54e88e06 1739 /* hotplug detect */
901ea57d
AD		 1740 struct {
1741 void (*init)(struct radeon_device *rdev);
1742 void (*fini)(struct radeon_device *rdev);
1743 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1744 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1745 } hpd;
da321c8a 1746 /* static power management */
a02fa397
AD		 1747 struct {
1748 void (*misc)(struct radeon_device *rdev);
1749 void (*prepare)(struct radeon_device *rdev);
1750 void (*finish)(struct radeon_device *rdev);
1751 void (*init_profile)(struct radeon_device *rdev);
1752 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1753 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1754 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1755 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1756 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1757 int (*get_pcie_lanes)(struct radeon_device *rdev);
1758 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1759 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1760 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
6bd1c385 1761 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1762 } pm;
da321c8a
AD		 1763 /* dynamic power management */
1764 struct {
1765 int (*init)(struct radeon_device *rdev);
1766 void (*setup_asic)(struct radeon_device *rdev);
1767 int (*enable)(struct radeon_device *rdev);
1768 void (*disable)(struct radeon_device *rdev);
84dd1928 1769 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1770 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1771 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1772 void (*display_configuration_changed)(struct radeon_device *rdev);
1773 void (*fini)(struct radeon_device *rdev);
1774 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1775 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1776 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1777 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1778 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1779 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1780 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1c71bda0 1781 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
da321c8a 1782 } dpm;
6f34be50 1783 /* pageflipping */
0f9e006c
AD		 1784 struct {
1785 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1786 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1787 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1788 } pflip;
771fe6b9
JG		 1789};
1790
21f9a437
JG		 1791/*
1792 * Asic structures
1793 */
551ebd83 1794struct r100_asic {
225758d8
JG		 1795 const unsigned *reg_safe_bm;
1796 unsigned reg_safe_bm_size;
1797 u32 hdp_cntl;
551ebd83
DA		 1798};
1799
21f9a437 1800struct r300_asic {
225758d8
JG		 1801 const unsigned *reg_safe_bm;
1802 unsigned reg_safe_bm_size;
1803 u32 resync_scratch;
1804 u32 hdp_cntl;
21f9a437
JG		 1805};
1806
1807struct r600_asic {
225758d8
JG		 1808 unsigned max_pipes;
1809 unsigned max_tile_pipes;
1810 unsigned max_simds;
1811 unsigned max_backends;
1812 unsigned max_gprs;
1813 unsigned max_threads;
1814 unsigned max_stack_entries;
1815 unsigned max_hw_contexts;
1816 unsigned max_gs_threads;
1817 unsigned sx_max_export_size;
1818 unsigned sx_max_export_pos_size;
1819 unsigned sx_max_export_smx_size;
1820 unsigned sq_num_cf_insts;
1821 unsigned tiling_nbanks;
1822 unsigned tiling_npipes;
1823 unsigned tiling_group_size;
e7aeeba6 1824 unsigned tile_config;
e55b9422 1825 unsigned backend_map;
21f9a437
JG		 1826};
1827
1828struct rv770_asic {
225758d8
JG		 1829 unsigned max_pipes;
1830 unsigned max_tile_pipes;
1831 unsigned max_simds;
1832 unsigned max_backends;
1833 unsigned max_gprs;
1834 unsigned max_threads;
1835 unsigned max_stack_entries;
1836 unsigned max_hw_contexts;
1837 unsigned max_gs_threads;
1838 unsigned sx_max_export_size;
1839 unsigned sx_max_export_pos_size;
1840 unsigned sx_max_export_smx_size;
1841 unsigned sq_num_cf_insts;
1842 unsigned sx_num_of_sets;
1843 unsigned sc_prim_fifo_size;
1844 unsigned sc_hiz_tile_fifo_size;
1845 unsigned sc_earlyz_tile_fifo_fize;
1846 unsigned tiling_nbanks;
1847 unsigned tiling_npipes;
1848 unsigned tiling_group_size;
e7aeeba6 1849 unsigned tile_config;
e55b9422 1850 unsigned backend_map;
21f9a437
JG		 1851};
1852
32fcdbf4
AD		 1853struct evergreen_asic {
1854 unsigned num_ses;
1855 unsigned max_pipes;
1856 unsigned max_tile_pipes;
1857 unsigned max_simds;
1858 unsigned max_backends;
1859 unsigned max_gprs;
1860 unsigned max_threads;
1861 unsigned max_stack_entries;
1862 unsigned max_hw_contexts;
1863 unsigned max_gs_threads;
1864 unsigned sx_max_export_size;
1865 unsigned sx_max_export_pos_size;
1866 unsigned sx_max_export_smx_size;
1867 unsigned sq_num_cf_insts;
1868 unsigned sx_num_of_sets;
1869 unsigned sc_prim_fifo_size;
1870 unsigned sc_hiz_tile_fifo_size;
1871 unsigned sc_earlyz_tile_fifo_size;
1872 unsigned tiling_nbanks;
1873 unsigned tiling_npipes;
1874 unsigned tiling_group_size;
e7aeeba6 1875 unsigned tile_config;
e55b9422 1876 unsigned backend_map;
32fcdbf4
AD		 1877};
1878
fecf1d07
AD		 1879struct cayman_asic {
1880 unsigned max_shader_engines;
1881 unsigned max_pipes_per_simd;
1882 unsigned max_tile_pipes;
1883 unsigned max_simds_per_se;
1884 unsigned max_backends_per_se;
1885 unsigned max_texture_channel_caches;
1886 unsigned max_gprs;
1887 unsigned max_threads;
1888 unsigned max_gs_threads;
1889 unsigned max_stack_entries;
1890 unsigned sx_num_of_sets;
1891 unsigned sx_max_export_size;
1892 unsigned sx_max_export_pos_size;
1893 unsigned sx_max_export_smx_size;
1894 unsigned max_hw_contexts;
1895 unsigned sq_num_cf_insts;
1896 unsigned sc_prim_fifo_size;
1897 unsigned sc_hiz_tile_fifo_size;
1898 unsigned sc_earlyz_tile_fifo_size;
1899
1900 unsigned num_shader_engines;
1901 unsigned num_shader_pipes_per_simd;
1902 unsigned num_tile_pipes;
1903 unsigned num_simds_per_se;
1904 unsigned num_backends_per_se;
1905 unsigned backend_disable_mask_per_asic;
1906 unsigned backend_map;
1907 unsigned num_texture_channel_caches;
1908 unsigned mem_max_burst_length_bytes;
1909 unsigned mem_row_size_in_kb;
1910 unsigned shader_engine_tile_size;
1911 unsigned num_gpus;
1912 unsigned multi_gpu_tile_size;
1913
1914 unsigned tile_config;
fecf1d07
AD		 1915};
1916
0a96d72b
AD		 1917struct si_asic {
1918 unsigned max_shader_engines;
0a96d72b 1919 unsigned max_tile_pipes;
1a8ca750
AD		 1920 unsigned max_cu_per_sh;
1921 unsigned max_sh_per_se;
0a96d72b
AD		 1922 unsigned max_backends_per_se;
1923 unsigned max_texture_channel_caches;
1924 unsigned max_gprs;
1925 unsigned max_gs_threads;
1926 unsigned max_hw_contexts;
1927 unsigned sc_prim_fifo_size_frontend;
1928 unsigned sc_prim_fifo_size_backend;
1929 unsigned sc_hiz_tile_fifo_size;
1930 unsigned sc_earlyz_tile_fifo_size;
1931
0a96d72b
AD		 1932 unsigned num_tile_pipes;
1933 unsigned num_backends_per_se;
1934 unsigned backend_disable_mask_per_asic;
1935 unsigned backend_map;
1936 unsigned num_texture_channel_caches;
1937 unsigned mem_max_burst_length_bytes;
1938 unsigned mem_row_size_in_kb;
1939 unsigned shader_engine_tile_size;
1940 unsigned num_gpus;
1941 unsigned multi_gpu_tile_size;
1942
1943 unsigned tile_config;
64d7b8be 1944 uint32_t tile_mode_array[32];
0a96d72b
AD		 1945};
1946
8cc1a532
AD		 1947struct cik_asic {
1948 unsigned max_shader_engines;
1949 unsigned max_tile_pipes;
1950 unsigned max_cu_per_sh;
1951 unsigned max_sh_per_se;
1952 unsigned max_backends_per_se;
1953 unsigned max_texture_channel_caches;
1954 unsigned max_gprs;
1955 unsigned max_gs_threads;
1956 unsigned max_hw_contexts;
1957 unsigned sc_prim_fifo_size_frontend;
1958 unsigned sc_prim_fifo_size_backend;
1959 unsigned sc_hiz_tile_fifo_size;
1960 unsigned sc_earlyz_tile_fifo_size;
1961
1962 unsigned num_tile_pipes;
1963 unsigned num_backends_per_se;
1964 unsigned backend_disable_mask_per_asic;
1965 unsigned backend_map;
1966 unsigned num_texture_channel_caches;
1967 unsigned mem_max_burst_length_bytes;
1968 unsigned mem_row_size_in_kb;
1969 unsigned shader_engine_tile_size;
1970 unsigned num_gpus;
1971 unsigned multi_gpu_tile_size;
1972
1973 unsigned tile_config;
39aee490 1974 uint32_t tile_mode_array[32];
8cc1a532
AD		 1975};
1976
068a117c
JG		 1977union radeon_asic_config {
1978 struct r300_asic r300;
551ebd83 1979 struct r100_asic r100;
3ce0a23d
JG		 1980 struct r600_asic r600;
1981 struct rv770_asic rv770;
32fcdbf4 1982 struct evergreen_asic evergreen;
fecf1d07 1983 struct cayman_asic cayman;
0a96d72b 1984 struct si_asic si;
8cc1a532 1985 struct cik_asic cik;
068a117c
JG		 1986};
1987
0a10c851
DV		 1988/*
1989 * asic initizalization from radeon_asic.c
1990 */
1991void radeon_agp_disable(struct radeon_device *rdev);
1992int radeon_asic_init(struct radeon_device *rdev);
1993
771fe6b9
JG		 1994
1995/*
1996 * IOCTL.
1997 */
1998int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1999 struct drm_file *filp);
2000int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2001 struct drm_file *filp);
2002int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2003 struct drm_file *file_priv);
2004int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2005 struct drm_file *file_priv);
2006int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2007 struct drm_file *file_priv);
2008int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2009 struct drm_file *file_priv);
2010int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2011 struct drm_file *filp);
2012int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2013 struct drm_file *filp);
2014int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2015 struct drm_file *filp);
2016int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2017 struct drm_file *filp);
721604a1
JG		 2018int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2019 struct drm_file *filp);
771fe6b9 2020int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 2021int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2022 struct drm_file *filp);
2023int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2024 struct drm_file *filp);
771fe6b9 2025
16cdf04d
AD		 2026/* VRAM scratch page for HDP bug, default vram page */
2027struct r600_vram_scratch {
87cbf8f2
AD		 2028 struct radeon_bo *robj;
2029 volatile uint32_t *ptr;
16cdf04d 2030 u64 gpu_addr;
87cbf8f2 2031};
771fe6b9 2032
fd64ca8a
LT		 2033/*
2034 * ACPI
2035 */
2036struct radeon_atif_notification_cfg {
2037 bool enabled;
2038 int command_code;
2039};
2040
2041struct radeon_atif_notifications {
2042 bool display_switch;
2043 bool expansion_mode_change;
2044 bool thermal_state;
2045 bool forced_power_state;
2046 bool system_power_state;
2047 bool display_conf_change;
2048 bool px_gfx_switch;
2049 bool brightness_change;
2050 bool dgpu_display_event;
2051};
2052
2053struct radeon_atif_functions {
2054 bool system_params;
2055 bool sbios_requests;
2056 bool select_active_disp;
2057 bool lid_state;
2058 bool get_tv_standard;
2059 bool set_tv_standard;
2060 bool get_panel_expansion_mode;
2061 bool set_panel_expansion_mode;
2062 bool temperature_change;
2063 bool graphics_device_types;
2064};
2065
2066struct radeon_atif {
2067 struct radeon_atif_notifications notifications;
2068 struct radeon_atif_functions functions;
2069 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2070 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2071};
7a1619b9 2072
e3a15920
AD		 2073struct radeon_atcs_functions {
2074 bool get_ext_state;
2075 bool pcie_perf_req;
2076 bool pcie_dev_rdy;
2077 bool pcie_bus_width;
2078};
2079
2080struct radeon_atcs {
2081 struct radeon_atcs_functions functions;
2082};
2083
771fe6b9
JG		 2084/*
2085 * Core structure, functions and helpers.
2086 */
2087typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2088typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2089
2090struct radeon_device {
9f022ddf 2091 struct device *dev;
771fe6b9
JG		 2092 struct drm_device *ddev;
2093 struct pci_dev *pdev;
dee53e7f 2094 struct rw_semaphore exclusive_lock;
771fe6b9 2095 /* ASIC */
068a117c 2096 union radeon_asic_config config;
771fe6b9
JG		 2097 enum radeon_family family;
2098 unsigned long flags;
2099 int usec_timeout;
2100 enum radeon_pll_errata pll_errata;
2101 int num_gb_pipes;
f779b3e5 2102 int num_z_pipes;
771fe6b9
JG		 2103 int disp_priority;
2104 /* BIOS */
2105 uint8_t *bios;
2106 bool is_atom_bios;
2107 uint16_t bios_header_start;
4c788679 2108 struct radeon_bo *stollen_vga_memory;
771fe6b9 2109 /* Register mmio */
4c9bc75c
DA		 2110 resource_size_t rmmio_base;
2111 resource_size_t rmmio_size;
2c385151
DV		 2112 /* protects concurrent MM_INDEX/DATA based register access */
2113 spinlock_t mmio_idx_lock;
fe78118c
AD		 2114 /* protects concurrent SMC based register access */
2115 spinlock_t smc_idx_lock;
0a5b7b0b
AD		 2116 /* protects concurrent PLL register access */
2117 spinlock_t pll_idx_lock;
2118 /* protects concurrent MC register access */
2119 spinlock_t mc_idx_lock;
2120 /* protects concurrent PCIE register access */
2121 spinlock_t pcie_idx_lock;
2122 /* protects concurrent PCIE_PORT register access */
2123 spinlock_t pciep_idx_lock;
2124 /* protects concurrent PIF register access */
2125 spinlock_t pif_idx_lock;
2126 /* protects concurrent CG register access */
2127 spinlock_t cg_idx_lock;
2128 /* protects concurrent UVD register access */
2129 spinlock_t uvd_idx_lock;
2130 /* protects concurrent RCU register access */
2131 spinlock_t rcu_idx_lock;
2132 /* protects concurrent DIDT register access */
2133 spinlock_t didt_idx_lock;
2134 /* protects concurrent ENDPOINT (audio) register access */
2135 spinlock_t end_idx_lock;
a0533fbf 2136 void __iomem *rmmio;
771fe6b9
JG		 2137 radeon_rreg_t mc_rreg;
2138 radeon_wreg_t mc_wreg;
2139 radeon_rreg_t pll_rreg;
2140 radeon_wreg_t pll_wreg;
de1b2898 2141 uint32_t pcie_reg_mask;
771fe6b9
JG		 2142 radeon_rreg_t pciep_rreg;
2143 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2144 /* io port */
2145 void __iomem *rio_mem;
2146 resource_size_t rio_mem_size;
771fe6b9
JG		 2147 struct radeon_clock clock;
2148 struct radeon_mc mc;
2149 struct radeon_gart gart;
2150 struct radeon_mode_info mode_info;
2151 struct radeon_scratch scratch;
75efdee1 2152 struct radeon_doorbell doorbell;
771fe6b9 2153 struct radeon_mman mman;
7465280c 2154 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2155 wait_queue_head_t fence_queue;
d6999bc7 2156 struct mutex ring_lock;
e32eb50d 2157 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2158 bool ib_pool_ready;
2159 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2160 struct radeon_irq irq;
2161 struct radeon_asic *asic;
2162 struct radeon_gem gem;
c93bb85b 2163 struct radeon_pm pm;
f2ba57b5 2164 struct radeon_uvd uvd;
f657c2a7 2165 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2166 struct radeon_wb wb;
3ce0a23d 2167 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2168 bool shutdown;
2169 bool suspend;
ad49f501 2170 bool need_dma32;
733289c2 2171 bool accel_working;
a0a53aa8 2172 bool fastfb_working; /* IGP feature*/
e024e110 2173 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2174 const struct firmware *me_fw; /* all family ME firmware */
2175 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2176 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2177 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2178 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2179 const struct firmware *mec_fw; /* CIK MEC firmware */
21a93e13 2180 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2181 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2182 const struct firmware *uvd_fw; /* UVD firmware */
16cdf04d 2183 struct r600_vram_scratch vram_scratch;
3e5cb98d 2184 int msi_enabled; /* msi enabled */
d8f60cfc 2185 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2186 struct radeon_rlc rlc;
963e81f9 2187 struct radeon_mec mec;
d4877cf2 2188 struct work_struct hotplug_work;
f122c610 2189 struct work_struct audio_work;
8f61b34c 2190 struct work_struct reset_work;
18917b60 2191 int num_crtc; /* number of crtcs */
40bacf16 2192 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
948bee3f 2193 bool has_uvd;
b530602f 2194 struct r600_audio audio; /* audio stuff */
ce8f5370 2195 struct notifier_block acpi_nb;
9eba4a93 2196 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2197 struct drm_file *hyperz_filp;
9eba4a93 2198 struct drm_file *cmask_filp;
f376b94f
AD		 2199 /* i2c buses */
2200 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2201 /* debugfs */
2202 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2203 unsigned debugfs_count;
721604a1
JG		 2204 /* virtual memory */
2205 struct radeon_vm_manager vm_manager;
6759a0a7 2206 struct mutex gpu_clock_mutex;
fd64ca8a
LT		 2207 /* ACPI interface */
2208 struct radeon_atif atif;
e3a15920 2209 struct radeon_atcs atcs;
f61d5b46
AD		 2210 /* srbm instance registers */
2211 struct mutex srbm_mutex;
64d8a728
AD		 2212 /* clock, powergating flags */
2213 u32 cg_flags;
2214 u32 pg_flags;
771fe6b9
JG		 2215};
2216
2217int radeon_device_init(struct radeon_device *rdev,
2218 struct drm_device *ddev,
2219 struct pci_dev *pdev,
2220 uint32_t flags);
2221void radeon_device_fini(struct radeon_device *rdev);
2222int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2223
2ef9bdfe
DV		 2224uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2225 bool always_indirect);
2226void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2227 bool always_indirect);
6fcbef7a
AK		 2228u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2229void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2230
75efdee1
AD		 2231u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset);
2232void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
2233
4c788679
JG		 2234/*
2235 * Cast helper
2236 */
2237#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 2238
2239/*
2240 * Registers read & write functions.
2241 */
a0533fbf
BH		 2242#define RREG8(reg) readb((rdev->rmmio) + (reg))
2243#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2244#define RREG16(reg) readw((rdev->rmmio) + (reg))
2245#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2246#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2247#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2248#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2249#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2250#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2251#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2252#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2253#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2254#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2255#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2256#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2257#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2258#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2259#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2260#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2261#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2262#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2263#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2264#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2265#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2266#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2267#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2268#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2269#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2270#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2271#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2272#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2273#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2274#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2275#define WREG32_P(reg, val, mask) \
2276 do { \
2277 uint32_t tmp_ = RREG32(reg); \
2278 tmp_ &= (mask); \
2279 tmp_ |= ((val) & ~(mask)); \
2280 WREG32(reg, tmp_); \
2281 } while (0)
d5169fc4 2282#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2283#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2284#define WREG32_PLL_P(reg, val, mask) \
2285 do { \
2286 uint32_t tmp_ = RREG32_PLL(reg); \
2287 tmp_ &= (mask); \
2288 tmp_ |= ((val) & ~(mask)); \
2289 WREG32_PLL(reg, tmp_); \
2290 } while (0)
2ef9bdfe 2291#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2292#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2293#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2294
75efdee1
AD		 2295#define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset))
2296#define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v))
2297
de1b2898
DA		 2298/*
2299 * Indirect registers accessor
2300 */
2301static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2302{
0a5b7b0b 2303 unsigned long flags;
de1b2898
DA		 2304 uint32_t r;
2305
0a5b7b0b 2306 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2307 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2308 r = RREG32(RADEON_PCIE_DATA);
0a5b7b0b 2309 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2310 return r;
2311}
2312
2313static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2314{
0a5b7b0b
AD		 2315 unsigned long flags;
2316
2317 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2318 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2319 WREG32(RADEON_PCIE_DATA, (v));
0a5b7b0b 2320 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2321}
2322
1d5d0c34
AD		 2323static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2324{
fe78118c 2325 unsigned long flags;
1d5d0c34
AD		 2326 u32 r;
2327
fe78118c 2328 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2329 WREG32(TN_SMC_IND_INDEX_0, (reg));
2330 r = RREG32(TN_SMC_IND_DATA_0);
fe78118c 2331 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2332 return r;
2333}
2334
2335static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2336{
fe78118c
AD		 2337 unsigned long flags;
2338
2339 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2340 WREG32(TN_SMC_IND_INDEX_0, (reg));
2341 WREG32(TN_SMC_IND_DATA_0, (v));
fe78118c 2342 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2343}
2344
ff82bbc4
AD		 2345static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2346{
0a5b7b0b 2347 unsigned long flags;
ff82bbc4
AD		 2348 u32 r;
2349
0a5b7b0b 2350 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2351 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2352 r = RREG32(R600_RCU_DATA);
0a5b7b0b 2353 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2354 return r;
2355}
2356
2357static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2358{
0a5b7b0b
AD		 2359 unsigned long flags;
2360
2361 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2362 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2363 WREG32(R600_RCU_DATA, (v));
0a5b7b0b 2364 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2365}
2366
46f9564a
AD		 2367static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2368{
0a5b7b0b 2369 unsigned long flags;
46f9564a
AD		 2370 u32 r;
2371
0a5b7b0b 2372 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2373 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2374 r = RREG32(EVERGREEN_CG_IND_DATA);
0a5b7b0b 2375 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2376 return r;
2377}
2378
2379static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2380{
0a5b7b0b
AD		 2381 unsigned long flags;
2382
2383 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2384 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2385 WREG32(EVERGREEN_CG_IND_DATA, (v));
0a5b7b0b 2386 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2387}
2388
792edd69
AD		 2389static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2390{
0a5b7b0b 2391 unsigned long flags;
792edd69
AD		 2392 u32 r;
2393
0a5b7b0b 2394 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2395 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2396 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
0a5b7b0b 2397 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2398 return r;
2399}
2400
2401static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2402{
0a5b7b0b
AD		 2403 unsigned long flags;
2404
2405 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2406 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2407 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
0a5b7b0b 2408 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2409}
2410
2411static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2412{
0a5b7b0b 2413 unsigned long flags;
792edd69
AD		 2414 u32 r;
2415
0a5b7b0b 2416 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2417 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2418 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
0a5b7b0b 2419 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2420 return r;
2421}
2422
2423static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2424{
0a5b7b0b
AD		 2425 unsigned long flags;
2426
2427 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2428 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2429 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
0a5b7b0b 2430 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2431}
2432
93656cdd
AD		 2433static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2434{
0a5b7b0b 2435 unsigned long flags;
93656cdd
AD		 2436 u32 r;
2437
0a5b7b0b 2438 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2439 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2440 r = RREG32(R600_UVD_CTX_DATA);
0a5b7b0b 2441 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2442 return r;
2443}
2444
2445static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2446{
0a5b7b0b
AD		 2447 unsigned long flags;
2448
2449 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2450 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2451 WREG32(R600_UVD_CTX_DATA, (v));
0a5b7b0b 2452 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2453}
2454
1d58234d
AD		 2455
2456static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2457{
0a5b7b0b 2458 unsigned long flags;
1d58234d
AD		 2459 u32 r;
2460
0a5b7b0b 2461 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2462 WREG32(CIK_DIDT_IND_INDEX, (reg));
2463 r = RREG32(CIK_DIDT_IND_DATA);
0a5b7b0b 2464 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2465 return r;
2466}
2467
2468static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2469{
0a5b7b0b
AD		 2470 unsigned long flags;
2471
2472 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2473 WREG32(CIK_DIDT_IND_INDEX, (reg));
2474 WREG32(CIK_DIDT_IND_DATA, (v));
0a5b7b0b 2475 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2476}
2477
771fe6b9
JG		 2478void r100_pll_errata_after_index(struct radeon_device *rdev);
2479
2480
2481/*
2482 * ASICs helpers.
2483 */
b995e433
DA		 2484#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2485 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2486#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2487 (rdev->family == CHIP_RV200) || \
2488 (rdev->family == CHIP_RS100) || \
2489 (rdev->family == CHIP_RS200) || \
2490 (rdev->family == CHIP_RV250) || \
2491 (rdev->family == CHIP_RV280) || \
2492 (rdev->family == CHIP_RS300))
2493#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2494 (rdev->family == CHIP_RV350) || \
2495 (rdev->family == CHIP_R350) || \
2496 (rdev->family == CHIP_RV380) || \
2497 (rdev->family == CHIP_R420) || \
2498 (rdev->family == CHIP_R423) || \
2499 (rdev->family == CHIP_RV410) || \
2500 (rdev->family == CHIP_RS400) || \
2501 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2502#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2503 (rdev->ddev->pdev->device == 0x9443) || \
2504 (rdev->ddev->pdev->device == 0x944B) || \
2505 (rdev->ddev->pdev->device == 0x9506) || \
2506 (rdev->ddev->pdev->device == 0x9509) || \
2507 (rdev->ddev->pdev->device == 0x950F) || \
2508 (rdev->ddev->pdev->device == 0x689C) || \
2509 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2510#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2511#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2512 (rdev->family == CHIP_RS690) || \
2513 (rdev->family == CHIP_RS740) || \
2514 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2515#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2516#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2517#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2518#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2519 (rdev->flags & RADEON_IS_IGP))
1fe18305 2520#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2521#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2522#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2523 (rdev->flags & RADEON_IS_IGP))
624d3524 2524#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2525#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2526#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
771fe6b9 2527
dc50ba7f
AD		 2528#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2529 (rdev->ddev->pdev->device == 0x6850) || \
2530 (rdev->ddev->pdev->device == 0x6858) || \
2531 (rdev->ddev->pdev->device == 0x6859) || \
2532 (rdev->ddev->pdev->device == 0x6840) || \
2533 (rdev->ddev->pdev->device == 0x6841) || \
2534 (rdev->ddev->pdev->device == 0x6842) || \
2535 (rdev->ddev->pdev->device == 0x6843))
2536
771fe6b9
JG		 2537/*
2538 * BIOS helpers.
2539 */
2540#define RBIOS8(i) (rdev->bios[i])
2541#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2542#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2543
2544int radeon_combios_init(struct radeon_device *rdev);
2545void radeon_combios_fini(struct radeon_device *rdev);
2546int radeon_atombios_init(struct radeon_device *rdev);
2547void radeon_atombios_fini(struct radeon_device *rdev);
2548
2549
2550/*
2551 * RING helpers.
2552 */
ce580fab 2553#if DRM_DEBUG_CODE == 0
e32eb50d 2554static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2555{
e32eb50d
CK		 2556 ring->ring[ring->wptr++] = v;
2557 ring->wptr &= ring->ptr_mask;
2558 ring->count_dw--;
2559 ring->ring_free_dw--;
771fe6b9 2560}
ce580fab
AK		 2561#else
2562/* With debugging this is just too big to inline */
e32eb50d 2563void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
ce580fab 2564#endif
771fe6b9
JG		 2565
2566/*
2567 * ASICs macro.
2568 */
068a117c 2569#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2570#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2571#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2572#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2573#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2574#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2575#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850
AD		 2576#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2577#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
05b07147
CK		 2578#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2579#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
43f1214a 2580#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
76a0df85
CK		 2581#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2582#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2583#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2584#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2585#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2586#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2587#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2588#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2589#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2590#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2591#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2592#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2593#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2594#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2595#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2596#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2597#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2598#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2599#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
27cd7769
AD		 2600#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2601#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2602#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2603#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2604#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2605#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2606#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2607#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2608#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2609#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2610#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2611#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2612#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2613#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
6bd1c385 2614#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2615#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2616#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2617#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2618#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2619#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2620#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2621#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2622#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2623#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2624#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2625#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2626#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2627#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8
AD		 2628#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2629#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2630#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2631#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2632#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2633#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2634#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2635#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2636#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2637#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2638#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2639#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2640#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2641#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2642#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2643#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2644#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2645#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2646#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2647#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2648#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2649#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2650#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
1c71bda0 2651#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
771fe6b9 2652
6cf8a3f5 2653/* Common functions */
700a0cc0 2654/* AGP */
90aca4d2 2655extern int radeon_gpu_reset(struct radeon_device *rdev);
410a3418 2656extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2657extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2658extern int radeon_modeset_init(struct radeon_device *rdev);
2659extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2660extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2661extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2662extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2663extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2664extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2665extern void radeon_wb_fini(struct radeon_device *rdev);
2666extern int radeon_wb_init(struct radeon_device *rdev);
2667extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2668extern void radeon_surface_init(struct radeon_device *rdev);
2669extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2670extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2671extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2672extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2673extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 2674extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2675extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
7473e830
DA		 2676extern int radeon_resume_kms(struct drm_device *dev, bool resume);
2677extern int radeon_suspend_kms(struct drm_device *dev, bool suspend);
53595338 2678extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2679extern void radeon_program_register_sequence(struct radeon_device *rdev,
2680 const u32 *registers,
2681 const u32 array_size);
6cf8a3f5 2682
721604a1
JG		 2683/*
2684 * vm
2685 */
2686int radeon_vm_manager_init(struct radeon_device *rdev);
2687void radeon_vm_manager_fini(struct radeon_device *rdev);
d72d43cf 2688void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2689void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
ddf03f5c 2690int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
13e55c38 2691void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
ee60e29f
CK		 2692struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2693 struct radeon_vm *vm, int ring);
2694void radeon_vm_fence(struct radeon_device *rdev,
2695 struct radeon_vm *vm,
2696 struct radeon_fence *fence);
dce34bfd 2697uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
721604a1
JG		 2698int radeon_vm_bo_update_pte(struct radeon_device *rdev,
2699 struct radeon_vm *vm,
2700 struct radeon_bo *bo,
2701 struct ttm_mem_reg *mem);
2702void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2703 struct radeon_bo *bo);
421ca7ab
CK		 2704struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2705 struct radeon_bo *bo);
e971bd5e
CK		 2706struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2707 struct radeon_vm *vm,
2708 struct radeon_bo *bo);
2709int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2710 struct radeon_bo_va *bo_va,
2711 uint64_t offset,
2712 uint32_t flags);
721604a1 2713int radeon_vm_bo_rmv(struct radeon_device *rdev,
e971bd5e 2714 struct radeon_bo_va *bo_va);
721604a1 2715
f122c610
AD		 2716/* audio */
2717void r600_audio_update_hdmi(struct work_struct *work);
b530602f
AD		 2718struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2719struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
721604a1 2720
16cdf04d
AD		 2721/*
2722 * R600 vram scratch functions
2723 */
2724int r600_vram_scratch_init(struct radeon_device *rdev);
2725void r600_vram_scratch_fini(struct radeon_device *rdev);
2726
285484e2
JG		 2727/*
2728 * r600 cs checking helper
2729 */
2730unsigned r600_mip_minify(unsigned size, unsigned level);
2731bool r600_fmt_is_valid_color(u32 format);
2732bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2733int r600_fmt_get_blocksize(u32 format);
2734int r600_fmt_get_nblocksx(u32 format, u32 w);
2735int r600_fmt_get_nblocksy(u32 format, u32 h);
2736
3574dda4
DV		 2737/*
2738 * r600 functions used by radeon_encoder.c
2739 */
1b688d08
RM		 2740struct radeon_hdmi_acr {
2741 u32 clock;
2742
2743 int n_32khz;
2744 int cts_32khz;
2745
2746 int n_44_1khz;
2747 int cts_44_1khz;
2748
2749 int n_48khz;
2750 int cts_48khz;
2751
2752};
2753
e55d3e6c
RM		 2754extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2755
416a2bd2
AD		 2756extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2757 u32 tiling_pipe_num,
2758 u32 max_rb_num,
2759 u32 total_max_rb_num,
2760 u32 enabled_rb_mask);
fe251e2f 2761
e55d3e6c
RM		 2762/*
2763 * evergreen functions used by radeon_encoder.c
2764 */
2765
0af62b01 2766extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2767extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2768
c4917074
AD		 2769/* radeon_acpi.c */
2770#if defined(CONFIG_ACPI)
2771extern int radeon_acpi_init(struct radeon_device *rdev);
2772extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2773extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2774extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2775 u8 perf_req, bool advertise);
dc50ba7f 2776extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2777#else
2778static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2779static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2780#endif
d7a2952f 2781
c38f34b5
IH		 2782int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2783 struct radeon_cs_packet *pkt,
2784 unsigned idx);
9ffb7a6d 2785bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2786void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2787 struct radeon_cs_packet *pkt);
e9716993
IH		 2788int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2789 struct radeon_cs_reloc **cs_reloc,
2790 int nomm);
40592a17
IH		 2791int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2792 uint32_t *vline_start_end,
2793 uint32_t *vline_status);
c38f34b5 2794
4c788679
JG		 2795#include "radeon_object.h"
2796
771fe6b9 2797#endif
Linux kernel - Deliverables
This page took 0.501672 seconds and 5 git commands to generate.