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drm/radeon: remove drm_vblank_get|put from pflip handling
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
a18cee15 96extern int radeon_msi;
3368ff0c 97extern int radeon_lockup_timeout;
a0a53aa8 98extern int radeon_fastfb;
da321c8a 99extern int radeon_dpm;
1294d4a3 100extern int radeon_aspm;
10ebc0bc 101extern int radeon_runtime_pm;
363eb0b4 102extern int radeon_hard_reset;
771fe6b9
JG		 103
104/*
105 * Copy from radeon_drv.h so we don't have to include both and have conflicting
106 * symbol;
107 */
bb635567
JG		 108#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
109#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 110/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 111#define RADEON_IB_POOL_SIZE 16
112#define RADEON_DEBUGFS_MAX_COMPONENTS 32
113#define RADEONFB_CONN_LIMIT 4
114#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 115
bb635567
JG		 116/* fence seq are set to this number when signaled */
117#define RADEON_FENCE_SIGNALED_SEQ 0LL
1b37078b
AD		 118
119/* internal ring indices */
120/* r1xx+ has gfx CP ring */
d93f7937 121#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 122
123/* cayman has 2 compute CP rings */
d93f7937
CK		 124#define CAYMAN_RING_TYPE_CP1_INDEX 1
125#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 126
4d75658b
AD		 127/* R600+ has an async dma ring */
128#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 129/* cayman add a second async dma ring */
130#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 131
f2ba57b5 132/* R600+ */
d93f7937
CK		 133#define R600_RING_TYPE_UVD_INDEX 5
134
135/* TN+ */
136#define TN_RING_TYPE_VCE1_INDEX 6
137#define TN_RING_TYPE_VCE2_INDEX 7
138
139/* max number of rings */
140#define RADEON_NUM_RINGS 8
f2ba57b5 141
1c61eae4
CK		 142/* number of hw syncs before falling back on blocking */
143#define RADEON_NUM_SYNCS 4
f2ba57b5 144
8f53492f
CK		 145/* number of hw syncs before falling back on blocking */
146#define RADEON_NUM_SYNCS 4
147
721604a1 148/* hardcode those limit for now */
ca19f21e 149#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 150#define RADEON_VA_RESERVED_SIZE (8 << 20)
151#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 152
1a0041b8
AD		 153/* hard reset data */
154#define RADEON_ASIC_RESET_DATA 0x39d5e86b
155
ec46c76d
AD		 156/* reset flags */
157#define RADEON_RESET_GFX (1 << 0)
158#define RADEON_RESET_COMPUTE (1 << 1)
159#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 160#define RADEON_RESET_CP (1 << 3)
161#define RADEON_RESET_GRBM (1 << 4)
162#define RADEON_RESET_DMA1 (1 << 5)
163#define RADEON_RESET_RLC (1 << 6)
164#define RADEON_RESET_SEM (1 << 7)
165#define RADEON_RESET_IH (1 << 8)
166#define RADEON_RESET_VMC (1 << 9)
167#define RADEON_RESET_MC (1 << 10)
168#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 169
22c775ce
AD		 170/* CG block flags */
171#define RADEON_CG_BLOCK_GFX (1 << 0)
172#define RADEON_CG_BLOCK_MC (1 << 1)
173#define RADEON_CG_BLOCK_SDMA (1 << 2)
174#define RADEON_CG_BLOCK_UVD (1 << 3)
175#define RADEON_CG_BLOCK_VCE (1 << 4)
176#define RADEON_CG_BLOCK_HDP (1 << 5)
e16866ec 177#define RADEON_CG_BLOCK_BIF (1 << 6)
22c775ce 178
64d8a728
AD		 179/* CG flags */
180#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
181#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
182#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
183#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
184#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
185#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
186#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
187#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
188#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
189#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
190#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
191#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
192#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
193#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
194#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
195#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
196#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
197
198/* PG flags */
2b19d17f 199#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
64d8a728
AD		 200#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
201#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
202#define RADEON_PG_SUPPORT_UVD (1 << 3)
203#define RADEON_PG_SUPPORT_VCE (1 << 4)
204#define RADEON_PG_SUPPORT_CP (1 << 5)
205#define RADEON_PG_SUPPORT_GDS (1 << 6)
206#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
207#define RADEON_PG_SUPPORT_SDMA (1 << 8)
208#define RADEON_PG_SUPPORT_ACP (1 << 9)
209#define RADEON_PG_SUPPORT_SAMU (1 << 10)
210
9e05fa1d
AD		 211/* max cursor sizes (in pixels) */
212#define CURSOR_WIDTH 64
213#define CURSOR_HEIGHT 64
214
215#define CIK_CURSOR_WIDTH 128
216#define CIK_CURSOR_HEIGHT 128
217
771fe6b9
JG		 218/*
219 * Errata workarounds.
220 */
221enum radeon_pll_errata {
222 CHIP_ERRATA_R300_CG = 0x00000001,
223 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
224 CHIP_ERRATA_PLL_DELAY = 0x00000004
225};
226
227
228struct radeon_device;
229
230
231/*
232 * BIOS.
233 */
234bool radeon_get_bios(struct radeon_device *rdev);
235
236/*
3ce0a23d 237 * Dummy page
771fe6b9 238 */
3ce0a23d
JG		 239struct radeon_dummy_page {
240 struct page *page;
241 dma_addr_t addr;
242};
243int radeon_dummy_page_init(struct radeon_device *rdev);
244void radeon_dummy_page_fini(struct radeon_device *rdev);
245
771fe6b9 246
3ce0a23d
JG		 247/*
248 * Clocks
249 */
771fe6b9
JG		 250struct radeon_clock {
251 struct radeon_pll p1pll;
252 struct radeon_pll p2pll;
bcc1c2a1 253 struct radeon_pll dcpll;
771fe6b9
JG		 254 struct radeon_pll spll;
255 struct radeon_pll mpll;
256 /* 10 Khz units */
257 uint32_t default_mclk;
258 uint32_t default_sclk;
bcc1c2a1 259 uint32_t default_dispclk;
4489cd62 260 uint32_t current_dispclk;
bcc1c2a1 261 uint32_t dp_extclk;
b20f9bef 262 uint32_t max_pixel_clock;
771fe6b9
JG		 263};
264
7433874e
RM		 265/*
266 * Power management
267 */
268int radeon_pm_init(struct radeon_device *rdev);
914a8987 269int radeon_pm_late_init(struct radeon_device *rdev);
29fb52ca 270void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 271void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 272void radeon_pm_suspend(struct radeon_device *rdev);
273void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 274void radeon_combios_get_power_modes(struct radeon_device *rdev);
275void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 276int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
277 u8 clock_type,
278 u32 clock,
279 bool strobe_mode,
280 struct atom_clock_dividers *dividers);
eaa778af
AD		 281int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
282 u32 clock,
283 bool strobe_mode,
284 struct atom_mpll_param *mpll_param);
8a83ec5e 285void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 286int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
287 u16 voltage_level, u8 voltage_type,
288 u32 *gpio_value, u32 *gpio_mask);
289void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
290 u32 eng_clock, u32 mem_clock);
291int radeon_atom_get_voltage_step(struct radeon_device *rdev,
292 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 293int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
294 u16 voltage_id, u16 *voltage);
beb79f40
AD		 295int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
296 u16 *voltage,
297 u16 leakage_idx);
cc8dbbb4
AD		 298int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
299 u16 *leakage_id);
300int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
301 u16 *vddc, u16 *vddci,
302 u16 virtual_voltage_id,
303 u16 vbios_voltage_id);
ae5b0abb
AD		 304int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
305 u8 voltage_type,
306 u16 nominal_voltage,
307 u16 *true_voltage);
308int radeon_atom_get_min_voltage(struct radeon_device *rdev,
309 u8 voltage_type, u16 *min_voltage);
310int radeon_atom_get_max_voltage(struct radeon_device *rdev,
311 u8 voltage_type, u16 *max_voltage);
312int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 313 u8 voltage_type, u8 voltage_mode,
ae5b0abb 314 struct atom_voltage_table *voltage_table);
58653abd
AD		 315bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
316 u8 voltage_type, u8 voltage_mode);
ae5b0abb
AD		 317void radeon_atom_update_memory_dll(struct radeon_device *rdev,
318 u32 mem_clock);
319void radeon_atom_set_ac_timing(struct radeon_device *rdev,
320 u32 mem_clock);
321int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
322 u8 module_index,
323 struct atom_mc_reg_table *reg_table);
324int radeon_atom_get_memory_info(struct radeon_device *rdev,
325 u8 module_index, struct atom_memory_info *mem_info);
326int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
327 bool gddr5, u8 module_index,
328 struct atom_memory_clock_range_table *mclk_range_table);
329int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
330 u16 voltage_id, u16 *voltage);
f892034a 331void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 332extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
333 unsigned *bankh, unsigned *mtaspect,
334 unsigned *tile_split);
3ce0a23d 335
771fe6b9
JG		 336/*
337 * Fences.
338 */
339struct radeon_fence_driver {
340 uint32_t scratch_reg;
30eb77f4
JG		 341 uint64_t gpu_addr;
342 volatile uint32_t *cpu_addr;
68e250b7
CK		 343 /* sync_seq is protected by ring emission lock */
344 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 345 atomic64_t last_seq;
0a0c7596 346 bool initialized;
771fe6b9
JG		 347};
348
349struct radeon_fence {
350 struct radeon_device *rdev;
351 struct kref kref;
771fe6b9 352 /* protected by radeon_fence.lock */
bb635567 353 uint64_t seq;
7465280c 354 /* RB, DMA, etc. */
bb635567 355 unsigned ring;
771fe6b9
JG		 356};
357
30eb77f4
JG		 358int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
359int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 360void radeon_fence_driver_fini(struct radeon_device *rdev);
76903b96 361void radeon_fence_driver_force_completion(struct radeon_device *rdev);
876dc9f3 362int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 363void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 364bool radeon_fence_signaled(struct radeon_fence *fence);
365int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
37615527
CK		 366int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
367int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
0085c950
JG		 368int radeon_fence_wait_any(struct radeon_device *rdev,
369 struct radeon_fence **fences,
370 bool intr);
771fe6b9
JG		 371struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
372void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 373unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 374bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
375void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
376static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
377 struct radeon_fence *b)
378{
379 if (!a) {
380 return b;
381 }
382
383 if (!b) {
384 return a;
385 }
386
387 BUG_ON(a->ring != b->ring);
388
389 if (a->seq > b->seq) {
390 return a;
391 } else {
392 return b;
393 }
394}
771fe6b9 395
ee60e29f
CK		 396static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
397 struct radeon_fence *b)
398{
399 if (!a) {
400 return false;
401 }
402
403 if (!b) {
404 return true;
405 }
406
407 BUG_ON(a->ring != b->ring);
408
409 return a->seq < b->seq;
410}
411
e024e110
DA		 412/*
413 * Tiling registers
414 */
415struct radeon_surface_reg {
4c788679 416 struct radeon_bo *bo;
e024e110
DA		 417};
418
419#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 420
421/*
4c788679 422 * TTM.
771fe6b9 423 */
4c788679
JG		 424struct radeon_mman {
425 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 426 struct drm_global_reference mem_global_ref;
4c788679 427 struct ttm_bo_device bdev;
0a0c7596
JG		 428 bool mem_global_referenced;
429 bool initialized;
2014b569
CK		 430
431#if defined(CONFIG_DEBUG_FS)
432 struct dentry *vram;
dd66d20e 433 struct dentry *gtt;
2014b569 434#endif
4c788679
JG		 435};
436
721604a1
JG		 437/* bo virtual address in a specific vm */
438struct radeon_bo_va {
e971bd5e 439 /* protected by bo being reserved */
721604a1 440 struct list_head bo_list;
721604a1
JG		 441 uint64_t soffset;
442 uint64_t eoffset;
443 uint32_t flags;
444 bool valid;
e971bd5e
CK		 445 unsigned ref_count;
446
447 /* protected by vm mutex */
448 struct list_head vm_list;
449
450 /* constant after initialization */
451 struct radeon_vm *vm;
452 struct radeon_bo *bo;
721604a1
JG		 453};
454
4c788679
JG		 455struct radeon_bo {
456 /* Protected by gem.mutex */
457 struct list_head list;
458 /* Protected by tbo.reserved */
bda72d58 459 u32 initial_domain;
312ea8da
JG		 460 u32 placements[3];
461 struct ttm_placement placement;
4c788679
JG		 462 struct ttm_buffer_object tbo;
463 struct ttm_bo_kmap_obj kmap;
464 unsigned pin_count;
465 void *kptr;
466 u32 tiling_flags;
467 u32 pitch;
468 int surface_reg;
721604a1
JG		 469 /* list of all virtual address to which this bo
470 * is associated to
471 */
472 struct list_head va;
4c788679
JG		 473 /* Constant after initialization */
474 struct radeon_device *rdev;
441921d5 475 struct drm_gem_object gem_base;
63bc620b 476
409851f4
JG		 477 struct ttm_bo_kmap_obj dma_buf_vmap;
478 pid_t pid;
4c788679 479};
7e4d15d9 480#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 481
409851f4
JG		 482int radeon_gem_debugfs_init(struct radeon_device *rdev);
483
b15ba512
JG		 484/* sub-allocation manager, it has to be protected by another lock.
485 * By conception this is an helper for other part of the driver
486 * like the indirect buffer or semaphore, which both have their
487 * locking.
488 *
489 * Principe is simple, we keep a list of sub allocation in offset
490 * order (first entry has offset == 0, last entry has the highest
491 * offset).
492 *
493 * When allocating new object we first check if there is room at
494 * the end total_size - (last_object_offset + last_object_size) >=
495 * alloc_size. If so we allocate new object there.
496 *
497 * When there is not enough room at the end, we start waiting for
498 * each sub object until we reach object_offset+object_size >=
499 * alloc_size, this object then become the sub object we return.
500 *
501 * Alignment can't be bigger than page size.
502 *
503 * Hole are not considered for allocation to keep things simple.
504 * Assumption is that there won't be hole (all object on same
505 * alignment).
506 */
507struct radeon_sa_manager {
bfb38d35 508 wait_queue_head_t wq;
b15ba512 509 struct radeon_bo *bo;
c3b7fe8b
CK		 510 struct list_head *hole;
511 struct list_head flist[RADEON_NUM_RINGS];
512 struct list_head olist;
b15ba512
JG		 513 unsigned size;
514 uint64_t gpu_addr;
515 void *cpu_ptr;
516 uint32_t domain;
6c4f978b 517 uint32_t align;
b15ba512
JG		 518};
519
520struct radeon_sa_bo;
521
522/* sub-allocation buffer */
523struct radeon_sa_bo {
c3b7fe8b
CK		 524 struct list_head olist;
525 struct list_head flist;
b15ba512 526 struct radeon_sa_manager *manager;
e6661a96
CK		 527 unsigned soffset;
528 unsigned eoffset;
557017a0 529 struct radeon_fence *fence;
b15ba512
JG		 530};
531
771fe6b9
JG		 532/*
533 * GEM objects.
534 */
535struct radeon_gem {
4c788679 536 struct mutex mutex;
771fe6b9
JG		 537 struct list_head objects;
538};
539
540int radeon_gem_init(struct radeon_device *rdev);
541void radeon_gem_fini(struct radeon_device *rdev);
542int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 543 int alignment, int initial_domain,
544 bool discardable, bool kernel,
545 struct drm_gem_object **obj);
771fe6b9 546
ff72145b
DA		 547int radeon_mode_dumb_create(struct drm_file *file_priv,
548 struct drm_device *dev,
549 struct drm_mode_create_dumb *args);
550int radeon_mode_dumb_mmap(struct drm_file *filp,
551 struct drm_device *dev,
552 uint32_t handle, uint64_t *offset_p);
771fe6b9 553
c1341e52
JG		 554/*
555 * Semaphores.
556 */
c1341e52 557struct radeon_semaphore {
a8c05940
JG		 558 struct radeon_sa_bo *sa_bo;
559 signed waiters;
c1341e52 560 uint64_t gpu_addr;
1654b817 561 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
c1341e52
JG		 562};
563
c1341e52
JG		 564int radeon_semaphore_create(struct radeon_device *rdev,
565 struct radeon_semaphore **semaphore);
1654b817 566bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
c1341e52 567 struct radeon_semaphore *semaphore);
1654b817 568bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
c1341e52 569 struct radeon_semaphore *semaphore);
1654b817
CK		 570void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
571 struct radeon_fence *fence);
8f676c4c
CK		 572int radeon_semaphore_sync_rings(struct radeon_device *rdev,
573 struct radeon_semaphore *semaphore,
1654b817 574 int waiting_ring);
c1341e52 575void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 576 struct radeon_semaphore **semaphore,
a8c05940 577 struct radeon_fence *fence);
c1341e52 578
771fe6b9
JG		 579/*
580 * GART structures, functions & helpers
581 */
582struct radeon_mc;
583
a77f1718 584#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 585#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 586#define RADEON_GPU_PAGE_SHIFT 12
721604a1 587#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 588
771fe6b9
JG		 589struct radeon_gart {
590 dma_addr_t table_addr;
c9a1be96
JG		 591 struct radeon_bo *robj;
592 void *ptr;
771fe6b9
JG		 593 unsigned num_gpu_pages;
594 unsigned num_cpu_pages;
595 unsigned table_size;
771fe6b9
JG		 596 struct page **pages;
597 dma_addr_t *pages_addr;
598 bool ready;
599};
600
601int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
602void radeon_gart_table_ram_free(struct radeon_device *rdev);
603int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
604void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 605int radeon_gart_table_vram_pin(struct radeon_device *rdev);
606void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 607int radeon_gart_init(struct radeon_device *rdev);
608void radeon_gart_fini(struct radeon_device *rdev);
609void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
610 int pages);
611int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516
KRW		 612 int pages, struct page **pagelist,
613 dma_addr_t *dma_addr);
c9a1be96 614void radeon_gart_restore(struct radeon_device *rdev);
771fe6b9
JG		 615
616
617/*
618 * GPU MC structures, functions & helpers
619 */
620struct radeon_mc {
621 resource_size_t aper_size;
622 resource_size_t aper_base;
623 resource_size_t agp_base;
7a50f01a
DA		 624 /* for some chips with <= 32MB we need to lie
625 * about vram size near mc fb location */
3ce0a23d 626 u64 mc_vram_size;
d594e46a 627 u64 visible_vram_size;
3ce0a23d
JG		 628 u64 gtt_size;
629 u64 gtt_start;
630 u64 gtt_end;
3ce0a23d
JG		 631 u64 vram_start;
632 u64 vram_end;
771fe6b9 633 unsigned vram_width;
3ce0a23d 634 u64 real_vram_size;
771fe6b9
JG		 635 int vram_mtrr;
636 bool vram_is_ddr;
d594e46a 637 bool igp_sideport_enabled;
8d369bb1 638 u64 gtt_base_align;
9ed8b1f9 639 u64 mc_mask;
771fe6b9
JG		 640};
641
06b6476d
AD		 642bool radeon_combios_sideport_present(struct radeon_device *rdev);
643bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 644
645/*
646 * GPU scratch registers structures, functions & helpers
647 */
648struct radeon_scratch {
649 unsigned num_reg;
724c80e1 650 uint32_t reg_base;
771fe6b9
JG		 651 bool free[32];
652 uint32_t reg[32];
653};
654
655int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
656void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
657
75efdee1
AD		 658/*
659 * GPU doorbell structures, functions & helpers
660 */
d5754ab8
AL		 661#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
662
75efdee1 663struct radeon_doorbell {
75efdee1 664 /* doorbell mmio */
d5754ab8
AL		 665 resource_size_t base;
666 resource_size_t size;
667 u32 __iomem *ptr;
668 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
669 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
75efdee1
AD		 670};
671
672int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
673void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771fe6b9
JG		 674
675/*
676 * IRQS.
677 */
6f34be50
AD		 678
679struct radeon_unpin_work {
680 struct work_struct work;
681 struct radeon_device *rdev;
682 int crtc_id;
683 struct radeon_fence *fence;
684 struct drm_pending_vblank_event *event;
685 struct radeon_bo *old_rbo;
686 u64 new_crtc_base;
687};
688
689struct r500_irq_stat_regs {
690 u32 disp_int;
f122c610 691 u32 hdmi0_status;
6f34be50
AD		 692};
693
694struct r600_irq_stat_regs {
695 u32 disp_int;
696 u32 disp_int_cont;
697 u32 disp_int_cont2;
698 u32 d1grph_int;
699 u32 d2grph_int;
f122c610
AD		 700 u32 hdmi0_status;
701 u32 hdmi1_status;
6f34be50
AD		 702};
703
704struct evergreen_irq_stat_regs {
705 u32 disp_int;
706 u32 disp_int_cont;
707 u32 disp_int_cont2;
708 u32 disp_int_cont3;
709 u32 disp_int_cont4;
710 u32 disp_int_cont5;
711 u32 d1grph_int;
712 u32 d2grph_int;
713 u32 d3grph_int;
714 u32 d4grph_int;
715 u32 d5grph_int;
716 u32 d6grph_int;
f122c610
AD		 717 u32 afmt_status1;
718 u32 afmt_status2;
719 u32 afmt_status3;
720 u32 afmt_status4;
721 u32 afmt_status5;
722 u32 afmt_status6;
6f34be50
AD		 723};
724
a59781bb
AD		 725struct cik_irq_stat_regs {
726 u32 disp_int;
727 u32 disp_int_cont;
728 u32 disp_int_cont2;
729 u32 disp_int_cont3;
730 u32 disp_int_cont4;
731 u32 disp_int_cont5;
732 u32 disp_int_cont6;
733};
734
6f34be50
AD		 735union radeon_irq_stat_regs {
736 struct r500_irq_stat_regs r500;
737 struct r600_irq_stat_regs r600;
738 struct evergreen_irq_stat_regs evergreen;
a59781bb 739 struct cik_irq_stat_regs cik;
6f34be50
AD		 740};
741
be0949f5 742#define RADEON_MAX_HPD_PINS 7
54bd5206 743#define RADEON_MAX_CRTCS 6
b530602f 744#define RADEON_MAX_AFMT_BLOCKS 7
54bd5206 745
771fe6b9 746struct radeon_irq {
fb98257a
CK		 747 bool installed;
748 spinlock_t lock;
736fc37f 749 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 750 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 751 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 752 wait_queue_head_t vblank_queue;
753 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 754 bool afmt[RADEON_MAX_AFMT_BLOCKS];
755 union radeon_irq_stat_regs stat_regs;
4a6369e9 756 bool dpm_thermal;
771fe6b9
JG		 757};
758
759int radeon_irq_kms_init(struct radeon_device *rdev);
760void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b
AD		 761void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
762void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 763void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
764void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 765void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
766void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
767void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
768void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 769
770/*
e32eb50d 771 * CP & rings.
771fe6b9 772 */
7465280c 773
771fe6b9 774struct radeon_ib {
68470ae7
JG		 775 struct radeon_sa_bo *sa_bo;
776 uint32_t length_dw;
777 uint64_t gpu_addr;
778 uint32_t *ptr;
876dc9f3 779 int ring;
68470ae7 780 struct radeon_fence *fence;
4bf3dd92 781 struct radeon_vm *vm;
68470ae7
JG		 782 bool is_const_ib;
783 struct radeon_semaphore *semaphore;
771fe6b9
JG		 784};
785
e32eb50d 786struct radeon_ring {
4c788679 787 struct radeon_bo *ring_obj;
771fe6b9 788 volatile uint32_t *ring;
5596a9db 789 unsigned rptr_offs;
45df6803 790 unsigned rptr_save_reg;
89d35807
AD		 791 u64 next_rptr_gpu_addr;
792 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 793 unsigned wptr;
794 unsigned wptr_old;
795 unsigned ring_size;
796 unsigned ring_free_dw;
797 int count_dw;
aee4aa73
CK		 798 atomic_t last_rptr;
799 atomic64_t last_activity;
771fe6b9
JG		 800 uint64_t gpu_addr;
801 uint32_t align_mask;
802 uint32_t ptr_mask;
771fe6b9 803 bool ready;
78c5560a 804 u32 nop;
8b25ed34 805 u32 idx;
5f0839c1
JG		 806 u64 last_semaphore_signal_addr;
807 u64 last_semaphore_wait_addr;
963e81f9
AD		 808 /* for CIK queues */
809 u32 me;
810 u32 pipe;
811 u32 queue;
812 struct radeon_bo *mqd_obj;
d5754ab8 813 u32 doorbell_index;
963e81f9
AD		 814 unsigned wptr_offs;
815};
816
817struct radeon_mec {
818 struct radeon_bo *hpd_eop_obj;
819 u64 hpd_eop_gpu_addr;
820 u32 num_pipe;
821 u32 num_mec;
822 u32 num_queue;
771fe6b9
JG		 823};
824
721604a1
JG		 825/*
826 * VM
827 */
ee60e29f 828
fa87e62d 829/* maximum number of VMIDs */
ee60e29f
CK		 830#define RADEON_NUM_VM 16
831
fa87e62d
DC		 832/* defines number of bits in page table versus page directory,
833 * a page is 4KB so we have 12 bits offset, 9 bits in the page
834 * table and the remaining 19 bits are in the page directory */
835#define RADEON_VM_BLOCK_SIZE 9
836
837/* number of entries in page table */
838#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
839
1c01103c
AD		 840/* PTBs (Page Table Blocks) need to be aligned to 32K */
841#define RADEON_VM_PTB_ALIGN_SIZE 32768
842#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
843#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
844
24c16439
CK		 845#define R600_PTE_VALID (1 << 0)
846#define R600_PTE_SYSTEM (1 << 1)
847#define R600_PTE_SNOOPED (1 << 2)
848#define R600_PTE_READABLE (1 << 5)
849#define R600_PTE_WRITEABLE (1 << 6)
850
ec3dbbcb
CK		 851/* PTE (Page Table Entry) fragment field for different page sizes */
852#define R600_PTE_FRAG_4KB (0 << 7)
853#define R600_PTE_FRAG_64KB (4 << 7)
854#define R600_PTE_FRAG_256KB (6 << 7)
855
6d2f2944
CK		 856struct radeon_vm_pt {
857 struct radeon_bo *bo;
858 uint64_t addr;
859};
860
721604a1 861struct radeon_vm {
721604a1 862 struct list_head va;
ee60e29f 863 unsigned id;
90a51a32
CK		 864
865 /* contains the page directory */
6d2f2944 866 struct radeon_bo *page_directory;
90a51a32 867 uint64_t pd_gpu_addr;
6d2f2944 868 unsigned max_pde_used;
90a51a32
CK		 869
870 /* array of page tables, one for each page directory entry */
6d2f2944 871 struct radeon_vm_pt *page_tables;
90a51a32 872
721604a1
JG		 873 struct mutex mutex;
874 /* last fence for cs using this vm */
875 struct radeon_fence *fence;
9b40e5d8
CK		 876 /* last flush or NULL if we still need to flush */
877 struct radeon_fence *last_flush;
593b2635
CK		 878 /* last use of vmid */
879 struct radeon_fence *last_id_use;
721604a1
JG		 880};
881
721604a1 882struct radeon_vm_manager {
ee60e29f 883 struct radeon_fence *active[RADEON_NUM_VM];
721604a1 884 uint32_t max_pfn;
721604a1
JG		 885 /* number of VMIDs */
886 unsigned nvm;
887 /* vram base address for page table entry */
888 u64 vram_base_offset;
67e915e4
AD		 889 /* is vm enabled? */
890 bool enabled;
721604a1
JG		 891};
892
893/*
894 * file private structure
895 */
896struct radeon_fpriv {
897 struct radeon_vm vm;
898};
899
d8f60cfc
AD		 900/*
901 * R6xx+ IH ring
902 */
903struct r600_ih {
4c788679 904 struct radeon_bo *ring_obj;
d8f60cfc
AD		 905 volatile uint32_t *ring;
906 unsigned rptr;
d8f60cfc
AD		 907 unsigned ring_size;
908 uint64_t gpu_addr;
d8f60cfc 909 uint32_t ptr_mask;
c20dc369 910 atomic_t lock;
d8f60cfc
AD		 911 bool enabled;
912};
913
347e7592 914/*
2948f5e6 915 * RLC stuff
347e7592 916 */
2948f5e6
AD		 917#include "clearstate_defs.h"
918
919struct radeon_rlc {
347e7592
AD		 920 /* for power gating */
921 struct radeon_bo *save_restore_obj;
922 uint64_t save_restore_gpu_addr;
2948f5e6 923 volatile uint32_t *sr_ptr;
1fd11777 924 const u32 *reg_list;
2948f5e6 925 u32 reg_list_size;
347e7592
AD		 926 /* for clear state */
927 struct radeon_bo *clear_state_obj;
928 uint64_t clear_state_gpu_addr;
2948f5e6 929 volatile uint32_t *cs_ptr;
1fd11777 930 const struct cs_section_def *cs_data;
22c775ce
AD		 931 u32 clear_state_size;
932 /* for cp tables */
933 struct radeon_bo *cp_table_obj;
934 uint64_t cp_table_gpu_addr;
935 volatile uint32_t *cp_table_ptr;
936 u32 cp_table_size;
347e7592
AD		 937};
938
69e130a6 939int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 940 struct radeon_ib *ib, struct radeon_vm *vm,
941 unsigned size);
f2e39221 942void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
4ef72566
CK		 943int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
944 struct radeon_ib *const_ib);
771fe6b9
JG		 945int radeon_ib_pool_init(struct radeon_device *rdev);
946void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 947int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 948/* Ring access between begin & end cannot sleep */
89d35807
AD		 949bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
950 struct radeon_ring *ring);
e32eb50d
CK		 951void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
952int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
953int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
954void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
955void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
d6999bc7 956void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 957void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
958int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
ff212f25
CK		 959void radeon_ring_lockup_update(struct radeon_device *rdev,
960 struct radeon_ring *ring);
069211e5 961bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 962unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
963 uint32_t **data);
964int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
965 unsigned size, uint32_t *data);
e32eb50d 966int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
ea31bf69 967 unsigned rptr_offs, u32 nop);
e32eb50d 968void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 969
970
4d75658b
AD		 971/* r600 async dma */
972void r600_dma_stop(struct radeon_device *rdev);
973int r600_dma_resume(struct radeon_device *rdev);
974void r600_dma_fini(struct radeon_device *rdev);
975
8c5fd7ef
AD		 976void cayman_dma_stop(struct radeon_device *rdev);
977int cayman_dma_resume(struct radeon_device *rdev);
978void cayman_dma_fini(struct radeon_device *rdev);
979
771fe6b9
JG		 980/*
981 * CS.
982 */
983struct radeon_cs_reloc {
984 struct drm_gem_object *gobj;
4c788679 985 struct radeon_bo *robj;
df0af440
CK		 986 struct ttm_validate_buffer tv;
987 uint64_t gpu_offset;
988 unsigned domain;
989 unsigned alt_domain;
990 uint32_t tiling_flags;
771fe6b9 991 uint32_t handle;
771fe6b9
JG		 992};
993
994struct radeon_cs_chunk {
995 uint32_t chunk_id;
996 uint32_t length_dw;
997 uint32_t *kdata;
721604a1 998 void __user *user_ptr;
771fe6b9
JG		 999};
1000
1001struct radeon_cs_parser {
c8c15ff1 1002 struct device *dev;
771fe6b9
JG		 1003 struct radeon_device *rdev;
1004 struct drm_file *filp;
1005 /* chunks */
1006 unsigned nchunks;
1007 struct radeon_cs_chunk *chunks;
1008 uint64_t *chunks_array;
1009 /* IB */
1010 unsigned idx;
1011 /* relocations */
1012 unsigned nrelocs;
1013 struct radeon_cs_reloc *relocs;
1014 struct radeon_cs_reloc **relocs_ptr;
df0af440 1015 struct radeon_cs_reloc *vm_bos;
771fe6b9 1016 struct list_head validated;
cf4ccd01 1017 unsigned dma_reloc_idx;
771fe6b9
JG		 1018 /* indices of various chunks */
1019 int chunk_ib_idx;
1020 int chunk_relocs_idx;
721604a1 1021 int chunk_flags_idx;
dfcf5f36 1022 int chunk_const_ib_idx;
f2e39221
JG		 1023 struct radeon_ib ib;
1024 struct radeon_ib const_ib;
771fe6b9 1025 void *track;
3ce0a23d 1026 unsigned family;
e70f224c 1027 int parser_error;
721604a1
JG		 1028 u32 cs_flags;
1029 u32 ring;
1030 s32 priority;
ecff665f 1031 struct ww_acquire_ctx ticket;
771fe6b9
JG		 1032};
1033
28a326c5
ML		 1034static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1035{
1036 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1037
1038 if (ibc->kdata)
1039 return ibc->kdata[idx];
1040 return p->ib.ptr[idx];
1041}
1042
513bcb46 1043
771fe6b9
JG		 1044struct radeon_cs_packet {
1045 unsigned idx;
1046 unsigned type;
1047 unsigned reg;
1048 unsigned opcode;
1049 int count;
1050 unsigned one_reg_wr;
1051};
1052
1053typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1054 struct radeon_cs_packet *pkt,
1055 unsigned idx, unsigned reg);
1056typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1057 struct radeon_cs_packet *pkt);
1058
1059
1060/*
1061 * AGP
1062 */
1063int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1064void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1065void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1066void radeon_agp_fini(struct radeon_device *rdev);
1067
1068
1069/*
1070 * Writeback
1071 */
1072struct radeon_wb {
4c788679 1073 struct radeon_bo *wb_obj;
771fe6b9
JG		 1074 volatile uint32_t *wb;
1075 uint64_t gpu_addr;
724c80e1 1076 bool enabled;
d0f8a854 1077 bool use_event;
771fe6b9
JG		 1078};
1079
724c80e1 1080#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1081#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1082#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1083#define RADEON_WB_CP1_RPTR_OFFSET 1280
1084#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1085#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1086#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1087#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1088#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1089#define CIK_WB_CP1_WPTR_OFFSET 3328
1090#define CIK_WB_CP2_WPTR_OFFSET 3584
724c80e1 1091
c93bb85b
JG		 1092/**
1093 * struct radeon_pm - power management datas
1094 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1095 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1096 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1097 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1098 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1099 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1100 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1101 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1102 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1103 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1104 * @needed_bandwidth: current bandwidth needs
1105 *
1106 * It keeps track of various data needed to take powermanagement decision.
25985edc 1107 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1108 * Equation between gpu/memory clock and available bandwidth is hw dependent
1109 * (type of memory, bus size, efficiency, ...)
1110 */
ce8f5370
AD		 1111
1112enum radeon_pm_method {
1113 PM_METHOD_PROFILE,
1114 PM_METHOD_DYNPM,
da321c8a 1115 PM_METHOD_DPM,
ce8f5370
AD		 1116};
1117
1118enum radeon_dynpm_state {
1119 DYNPM_STATE_DISABLED,
1120 DYNPM_STATE_MINIMUM,
1121 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1122 DYNPM_STATE_ACTIVE,
1123 DYNPM_STATE_SUSPENDED,
c913e23a 1124};
ce8f5370
AD		 1125enum radeon_dynpm_action {
1126 DYNPM_ACTION_NONE,
1127 DYNPM_ACTION_MINIMUM,
1128 DYNPM_ACTION_DOWNCLOCK,
1129 DYNPM_ACTION_UPCLOCK,
1130 DYNPM_ACTION_DEFAULT
c913e23a 1131};
56278a8e
AD		 1132
1133enum radeon_voltage_type {
1134 VOLTAGE_NONE = 0,
1135 VOLTAGE_GPIO,
1136 VOLTAGE_VDDC,
1137 VOLTAGE_SW
1138};
1139
0ec0e74f 1140enum radeon_pm_state_type {
da321c8a 1141 /* not used for dpm */
0ec0e74f
AD		 1142 POWER_STATE_TYPE_DEFAULT,
1143 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1144 /* user selectable states */
0ec0e74f
AD		 1145 POWER_STATE_TYPE_BATTERY,
1146 POWER_STATE_TYPE_BALANCED,
1147 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1148 /* internal states */
1149 POWER_STATE_TYPE_INTERNAL_UVD,
1150 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1151 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1152 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1153 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1154 POWER_STATE_TYPE_INTERNAL_BOOT,
1155 POWER_STATE_TYPE_INTERNAL_THERMAL,
1156 POWER_STATE_TYPE_INTERNAL_ACPI,
1157 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1158 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1159};
1160
ce8f5370
AD		 1161enum radeon_pm_profile_type {
1162 PM_PROFILE_DEFAULT,
1163 PM_PROFILE_AUTO,
1164 PM_PROFILE_LOW,
c9e75b21 1165 PM_PROFILE_MID,
ce8f5370
AD		 1166 PM_PROFILE_HIGH,
1167};
1168
1169#define PM_PROFILE_DEFAULT_IDX 0
1170#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1171#define PM_PROFILE_MID_SH_IDX 2
1172#define PM_PROFILE_HIGH_SH_IDX 3
1173#define PM_PROFILE_LOW_MH_IDX 4
1174#define PM_PROFILE_MID_MH_IDX 5
1175#define PM_PROFILE_HIGH_MH_IDX 6
1176#define PM_PROFILE_MAX 7
ce8f5370
AD		 1177
1178struct radeon_pm_profile {
1179 int dpms_off_ps_idx;
1180 int dpms_on_ps_idx;
1181 int dpms_off_cm_idx;
1182 int dpms_on_cm_idx;
516d0e46
AD		 1183};
1184
21a8122a
AD		 1185enum radeon_int_thermal_type {
1186 THERMAL_TYPE_NONE,
da321c8a
AD		 1187 THERMAL_TYPE_EXTERNAL,
1188 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1189 THERMAL_TYPE_RV6XX,
1190 THERMAL_TYPE_RV770,
da321c8a 1191 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1192 THERMAL_TYPE_EVERGREEN,
e33df25f 1193 THERMAL_TYPE_SUMO,
4fddba1f 1194 THERMAL_TYPE_NI,
14607d08 1195 THERMAL_TYPE_SI,
da321c8a 1196 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1197 THERMAL_TYPE_CI,
16fbe00d 1198 THERMAL_TYPE_KV,
21a8122a
AD		 1199};
1200
56278a8e
AD		 1201struct radeon_voltage {
1202 enum radeon_voltage_type type;
1203 /* gpio voltage */
1204 struct radeon_gpio_rec gpio;
1205 u32 delay; /* delay in usec from voltage drop to sclk change */
1206 bool active_high; /* voltage drop is active when bit is high */
1207 /* VDDC voltage */
1208 u8 vddc_id; /* index into vddc voltage table */
1209 u8 vddci_id; /* index into vddci voltage table */
1210 bool vddci_enabled;
1211 /* r6xx+ sw */
2feea49a
AD		 1212 u16 voltage;
1213 /* evergreen+ vddci */
1214 u16 vddci;
56278a8e
AD		 1215};
1216
d7311171
AD		 1217/* clock mode flags */
1218#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1219
56278a8e
AD		 1220struct radeon_pm_clock_info {
1221 /* memory clock */
1222 u32 mclk;
1223 /* engine clock */
1224 u32 sclk;
1225 /* voltage info */
1226 struct radeon_voltage voltage;
d7311171 1227 /* standardized clock flags */
56278a8e
AD		 1228 u32 flags;
1229};
1230
a48b9b4e 1231/* state flags */
d7311171 1232#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1233
56278a8e 1234struct radeon_power_state {
0ec0e74f 1235 enum radeon_pm_state_type type;
8f3f1c9a 1236 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1237 /* number of valid clock modes in this power state */
1238 int num_clock_modes;
56278a8e 1239 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1240 /* standardized state flags */
1241 u32 flags;
79daedc9
AD		 1242 u32 misc; /* vbios specific flags */
1243 u32 misc2; /* vbios specific flags */
1244 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1245};
1246
27459324
RM		 1247/*
1248 * Some modes are overclocked by very low value, accept them
1249 */
1250#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1251
2e9d4c05
AD		 1252enum radeon_dpm_auto_throttle_src {
1253 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1254 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1255};
1256
1257enum radeon_dpm_event_src {
1258 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1259 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1260 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1261 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1262 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1263};
1264
58bd2a88
AD		 1265#define RADEON_MAX_VCE_LEVELS 6
1266
b62d628b
AD		 1267enum radeon_vce_level {
1268 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1269 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1270 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1271 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1272 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1273 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1274};
1275
da321c8a
AD		 1276struct radeon_ps {
1277 u32 caps; /* vbios flags */
1278 u32 class; /* vbios flags */
1279 u32 class2; /* vbios flags */
1280 /* UVD clocks */
1281 u32 vclk;
1282 u32 dclk;
c4453e66
AD		 1283 /* VCE clocks */
1284 u32 evclk;
1285 u32 ecclk;
b62d628b
AD		 1286 bool vce_active;
1287 enum radeon_vce_level vce_level;
da321c8a
AD		 1288 /* asic priv */
1289 void *ps_priv;
1290};
1291
1292struct radeon_dpm_thermal {
1293 /* thermal interrupt work */
1294 struct work_struct work;
1295 /* low temperature threshold */
1296 int min_temp;
1297 /* high temperature threshold */
1298 int max_temp;
1299 /* was interrupt low to high or high to low */
1300 bool high_to_low;
1301};
1302
d22b7e40
AD		 1303enum radeon_clk_action
1304{
1305 RADEON_SCLK_UP = 1,
1306 RADEON_SCLK_DOWN
1307};
1308
1309struct radeon_blacklist_clocks
1310{
1311 u32 sclk;
1312 u32 mclk;
1313 enum radeon_clk_action action;
1314};
1315
61b7d601
AD		 1316struct radeon_clock_and_voltage_limits {
1317 u32 sclk;
1318 u32 mclk;
cdf6e805
AD		 1319 u16 vddc;
1320 u16 vddci;
61b7d601
AD		 1321};
1322
1323struct radeon_clock_array {
1324 u32 count;
1325 u32 *values;
1326};
1327
1328struct radeon_clock_voltage_dependency_entry {
1329 u32 clk;
1330 u16 v;
1331};
1332
1333struct radeon_clock_voltage_dependency_table {
1334 u32 count;
1335 struct radeon_clock_voltage_dependency_entry *entries;
1336};
1337
ef976ec4
AD		 1338union radeon_cac_leakage_entry {
1339 struct {
1340 u16 vddc;
1341 u32 leakage;
1342 };
1343 struct {
1344 u16 vddc1;
1345 u16 vddc2;
1346 u16 vddc3;
1347 };
61b7d601
AD		 1348};
1349
1350struct radeon_cac_leakage_table {
1351 u32 count;
ef976ec4 1352 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1353};
1354
929ee7a8
AD		 1355struct radeon_phase_shedding_limits_entry {
1356 u16 voltage;
1357 u32 sclk;
1358 u32 mclk;
1359};
1360
1361struct radeon_phase_shedding_limits_table {
1362 u32 count;
1363 struct radeon_phase_shedding_limits_entry *entries;
1364};
1365
84a9d9ee
AD		 1366struct radeon_uvd_clock_voltage_dependency_entry {
1367 u32 vclk;
1368 u32 dclk;
1369 u16 v;
1370};
1371
1372struct radeon_uvd_clock_voltage_dependency_table {
1373 u8 count;
1374 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1375};
1376
d29f013b
AD		 1377struct radeon_vce_clock_voltage_dependency_entry {
1378 u32 ecclk;
1379 u32 evclk;
1380 u16 v;
1381};
1382
1383struct radeon_vce_clock_voltage_dependency_table {
1384 u8 count;
1385 struct radeon_vce_clock_voltage_dependency_entry *entries;
1386};
1387
a5cb318e
AD		 1388struct radeon_ppm_table {
1389 u8 ppm_design;
1390 u16 cpu_core_number;
1391 u32 platform_tdp;
1392 u32 small_ac_platform_tdp;
1393 u32 platform_tdc;
1394 u32 small_ac_platform_tdc;
1395 u32 apu_tdp;
1396 u32 dgpu_tdp;
1397 u32 dgpu_ulv_power;
1398 u32 tj_max;
1399};
1400
58cb7632
AD		 1401struct radeon_cac_tdp_table {
1402 u16 tdp;
1403 u16 configurable_tdp;
1404 u16 tdc;
1405 u16 battery_power_limit;
1406 u16 small_power_limit;
1407 u16 low_cac_leakage;
1408 u16 high_cac_leakage;
1409 u16 maximum_power_delivery_limit;
1410};
1411
61b7d601
AD		 1412struct radeon_dpm_dynamic_state {
1413 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1414 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1415 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1416 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1417 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1418 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1419 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1420 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1421 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1422 struct radeon_clock_array valid_sclk_values;
1423 struct radeon_clock_array valid_mclk_values;
1424 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1425 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1426 u32 mclk_sclk_ratio;
1427 u32 sclk_mclk_delta;
1428 u16 vddc_vddci_delta;
1429 u16 min_vddc_for_pcie_gen2;
1430 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1431 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1432 struct radeon_ppm_table *ppm_table;
58cb7632 1433 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1434};
1435
1436struct radeon_dpm_fan {
1437 u16 t_min;
1438 u16 t_med;
1439 u16 t_high;
1440 u16 pwm_min;
1441 u16 pwm_med;
1442 u16 pwm_high;
1443 u8 t_hyst;
1444 u32 cycle_delay;
1445 u16 t_max;
1446 bool ucode_fan_control;
1447};
1448
32ce4652
AD		 1449enum radeon_pcie_gen {
1450 RADEON_PCIE_GEN1 = 0,
1451 RADEON_PCIE_GEN2 = 1,
1452 RADEON_PCIE_GEN3 = 2,
1453 RADEON_PCIE_GEN_INVALID = 0xffff
1454};
1455
70d01a5e
AD		 1456enum radeon_dpm_forced_level {
1457 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1458 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1459 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1460};
1461
58bd2a88
AD		 1462struct radeon_vce_state {
1463 /* vce clocks */
1464 u32 evclk;
1465 u32 ecclk;
1466 /* gpu clocks */
1467 u32 sclk;
1468 u32 mclk;
1469 u8 clk_idx;
1470 u8 pstate;
1471};
1472
da321c8a
AD		 1473struct radeon_dpm {
1474 struct radeon_ps *ps;
1475 /* number of valid power states */
1476 int num_ps;
1477 /* current power state that is active */
1478 struct radeon_ps *current_ps;
1479 /* requested power state */
1480 struct radeon_ps *requested_ps;
1481 /* boot up power state */
1482 struct radeon_ps *boot_ps;
1483 /* default uvd power state */
1484 struct radeon_ps *uvd_ps;
58bd2a88
AD		 1485 /* vce requirements */
1486 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1487 enum radeon_vce_level vce_level;
da321c8a
AD		 1488 enum radeon_pm_state_type state;
1489 enum radeon_pm_state_type user_state;
1490 u32 platform_caps;
1491 u32 voltage_response_time;
1492 u32 backbias_response_time;
1493 void *priv;
1494 u32 new_active_crtcs;
1495 int new_active_crtc_count;
1496 u32 current_active_crtcs;
1497 int current_active_crtc_count;
61b7d601
AD		 1498 struct radeon_dpm_dynamic_state dyn_state;
1499 struct radeon_dpm_fan fan;
1500 u32 tdp_limit;
1501 u32 near_tdp_limit;
a9e61410 1502 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1503 u32 sq_ramping_threshold;
1504 u32 cac_leakage;
1505 u16 tdp_od_limit;
1506 u32 tdp_adjustment;
1507 u16 load_line_slope;
1508 bool power_control;
5ca302f7 1509 bool ac_power;
da321c8a
AD		 1510 /* special states active */
1511 bool thermal_active;
8a227555 1512 bool uvd_active;
b62d628b 1513 bool vce_active;
da321c8a
AD		 1514 /* thermal handling */
1515 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1516 /* forced levels */
1517 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1518 /* track UVD streams */
1519 unsigned sd;
1520 unsigned hd;
da321c8a
AD		 1521};
1522
ce3537d5 1523void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
03afe6f6 1524void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
da321c8a 1525
c93bb85b 1526struct radeon_pm {
c913e23a 1527 struct mutex mutex;
db7fce39
CK		 1528 /* write locked while reprogramming mclk */
1529 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1530 u32 active_crtcs;
1531 int active_crtc_count;
c913e23a 1532 int req_vblank;
839461d3 1533 bool vblank_sync;
c93bb85b
JG		 1534 fixed20_12 max_bandwidth;
1535 fixed20_12 igp_sideport_mclk;
1536 fixed20_12 igp_system_mclk;
1537 fixed20_12 igp_ht_link_clk;
1538 fixed20_12 igp_ht_link_width;
1539 fixed20_12 k8_bandwidth;
1540 fixed20_12 sideport_bandwidth;
1541 fixed20_12 ht_bandwidth;
1542 fixed20_12 core_bandwidth;
1543 fixed20_12 sclk;
f47299c5 1544 fixed20_12 mclk;
c93bb85b 1545 fixed20_12 needed_bandwidth;
0975b162 1546 struct radeon_power_state *power_state;
56278a8e
AD		 1547 /* number of valid power states */
1548 int num_power_states;
a48b9b4e
AD		 1549 int current_power_state_index;
1550 int current_clock_mode_index;
1551 int requested_power_state_index;
1552 int requested_clock_mode_index;
1553 int default_power_state_index;
1554 u32 current_sclk;
1555 u32 current_mclk;
2feea49a
AD		 1556 u16 current_vddc;
1557 u16 current_vddci;
9ace9f7b
AD		 1558 u32 default_sclk;
1559 u32 default_mclk;
2feea49a
AD		 1560 u16 default_vddc;
1561 u16 default_vddci;
29fb52ca 1562 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1563 /* selected pm method */
1564 enum radeon_pm_method pm_method;
1565 /* dynpm power management */
1566 struct delayed_work dynpm_idle_work;
1567 enum radeon_dynpm_state dynpm_state;
1568 enum radeon_dynpm_action dynpm_planned_action;
1569 unsigned long dynpm_action_timeout;
1570 bool dynpm_can_upclock;
1571 bool dynpm_can_downclock;
1572 /* profile-based power management */
1573 enum radeon_pm_profile_type profile;
1574 int profile_index;
1575 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1576 /* internal thermal controller on rv6xx+ */
1577 enum radeon_int_thermal_type int_thermal_type;
1578 struct device *int_hwmon_dev;
da321c8a
AD		 1579 /* dpm */
1580 bool dpm_enabled;
1581 struct radeon_dpm dpm;
c93bb85b
JG		 1582};
1583
a4c9e2ee
AD		 1584int radeon_pm_get_type_index(struct radeon_device *rdev,
1585 enum radeon_pm_state_type ps_type,
1586 int instance);
f2ba57b5
CK		 1587/*
1588 * UVD
1589 */
1590#define RADEON_MAX_UVD_HANDLES 10
1591#define RADEON_UVD_STACK_SIZE (1024*1024)
1592#define RADEON_UVD_HEAP_SIZE (1024*1024)
1593
1594struct radeon_uvd {
1595 struct radeon_bo *vcpu_bo;
1596 void *cpu_addr;
1597 uint64_t gpu_addr;
9cc2e0e9 1598 void *saved_bo;
f2ba57b5
CK		 1599 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1600 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1601 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1602 struct delayed_work idle_work;
f2ba57b5
CK		 1603};
1604
1605int radeon_uvd_init(struct radeon_device *rdev);
1606void radeon_uvd_fini(struct radeon_device *rdev);
1607int radeon_uvd_suspend(struct radeon_device *rdev);
1608int radeon_uvd_resume(struct radeon_device *rdev);
1609int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1610 uint32_t handle, struct radeon_fence **fence);
1611int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1612 uint32_t handle, struct radeon_fence **fence);
1613void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1614void radeon_uvd_free_handles(struct radeon_device *rdev,
1615 struct drm_file *filp);
1616int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1617void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1618int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1619 unsigned vclk, unsigned dclk,
1620 unsigned vco_min, unsigned vco_max,
1621 unsigned fb_factor, unsigned fb_mask,
1622 unsigned pd_min, unsigned pd_max,
1623 unsigned pd_even,
1624 unsigned *optimal_fb_div,
1625 unsigned *optimal_vclk_div,
1626 unsigned *optimal_dclk_div);
1627int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1628 unsigned cg_upll_func_cntl);
771fe6b9 1629
d93f7937
CK		 1630/*
1631 * VCE
1632 */
1633#define RADEON_MAX_VCE_HANDLES 16
1634#define RADEON_VCE_STACK_SIZE (1024*1024)
1635#define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1636
1637struct radeon_vce {
1638 struct radeon_bo *vcpu_bo;
d93f7937 1639 uint64_t gpu_addr;
98ccc291
CK		 1640 unsigned fw_version;
1641 unsigned fb_version;
d93f7937
CK		 1642 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1643 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
03afe6f6 1644 struct delayed_work idle_work;
d93f7937
CK		 1645};
1646
1647int radeon_vce_init(struct radeon_device *rdev);
1648void radeon_vce_fini(struct radeon_device *rdev);
1649int radeon_vce_suspend(struct radeon_device *rdev);
1650int radeon_vce_resume(struct radeon_device *rdev);
1651int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1652 uint32_t handle, struct radeon_fence **fence);
1653int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1654 uint32_t handle, struct radeon_fence **fence);
1655void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
03afe6f6 1656void radeon_vce_note_usage(struct radeon_device *rdev);
d93f7937
CK		 1657int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi);
1658int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1659bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1660 struct radeon_ring *ring,
1661 struct radeon_semaphore *semaphore,
1662 bool emit_wait);
1663void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1664void radeon_vce_fence_emit(struct radeon_device *rdev,
1665 struct radeon_fence *fence);
1666int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1667int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1668
b530602f 1669struct r600_audio_pin {
a92553ab
RM		 1670 int channels;
1671 int rate;
1672 int bits_per_sample;
1673 u8 status_bits;
1674 u8 category_code;
b530602f
AD		 1675 u32 offset;
1676 bool connected;
1677 u32 id;
1678};
1679
1680struct r600_audio {
1681 bool enabled;
1682 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1683 int num_pins;
a92553ab
RM		 1684};
1685
771fe6b9
JG		 1686/*
1687 * Benchmarking
1688 */
638dd7db 1689void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1690
1691
ecc0b326
MD		 1692/*
1693 * Testing
1694 */
1695void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1696void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1697 struct radeon_ring *cpA,
1698 struct radeon_ring *cpB);
60a7e396 1699void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326
MD		 1700
1701
771fe6b9
JG		 1702/*
1703 * Debugfs
1704 */
4d8bf9ae
CK		 1705struct radeon_debugfs {
1706 struct drm_info_list *files;
1707 unsigned num_files;
1708};
1709
771fe6b9
JG		 1710int radeon_debugfs_add_files(struct radeon_device *rdev,
1711 struct drm_info_list *files,
1712 unsigned nfiles);
1713int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1714
76a0df85
CK		 1715/*
1716 * ASIC ring specific functions.
1717 */
1718struct radeon_asic_ring {
1719 /* ring read/write ptr handling */
1720 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1721 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1722 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1723
1724 /* validating and patching of IBs */
1725 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1726 int (*cs_parse)(struct radeon_cs_parser *p);
1727
1728 /* command emmit functions */
1729 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1730 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1654b817 1731 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
76a0df85
CK		 1732 struct radeon_semaphore *semaphore, bool emit_wait);
1733 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1734
1735 /* testing functions */
1736 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1737 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1738 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1739
1740 /* deprecated */
1741 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1742};
771fe6b9
JG		 1743
1744/*
1745 * ASIC specific functions.
1746 */
1747struct radeon_asic {
068a117c 1748 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1749 void (*fini)(struct radeon_device *rdev);
1750 int (*resume)(struct radeon_device *rdev);
1751 int (*suspend)(struct radeon_device *rdev);
28d52043 1752 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1753 int (*asic_reset)(struct radeon_device *rdev);
54e88e06
AD		 1754 /* ioctl hw specific callback. Some hw might want to perform special
1755 * operation on specific ioctl. For instance on wait idle some hw
1756 * might want to perform and HDP flush through MMIO as it seems that
1757 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1758 * through ring.
1759 */
1760 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1761 /* check if 3D engine is idle */
1762 bool (*gui_idle)(struct radeon_device *rdev);
1763 /* wait for mc_idle */
1764 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1765 /* get the reference clock */
1766 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1767 /* get the gpu clock counter */
1768 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1769 /* gart */
c5b3b850
AD		 1770 struct {
1771 void (*tlb_flush)(struct radeon_device *rdev);
1772 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1773 } gart;
05b07147
CK		 1774 struct {
1775 int (*init)(struct radeon_device *rdev);
1776 void (*fini)(struct radeon_device *rdev);
43f1214a
AD		 1777 void (*set_page)(struct radeon_device *rdev,
1778 struct radeon_ib *ib,
1779 uint64_t pe,
dce34bfd
CK		 1780 uint64_t addr, unsigned count,
1781 uint32_t incr, uint32_t flags);
05b07147 1782 } vm;
54e88e06 1783 /* ring specific callbacks */
76a0df85 1784 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1785 /* irqs */
b35ea4ab
AD		 1786 struct {
1787 int (*set)(struct radeon_device *rdev);
1788 int (*process)(struct radeon_device *rdev);
1789 } irq;
54e88e06 1790 /* displays */
c79a49ca
AD		 1791 struct {
1792 /* display watermarks */
1793 void (*bandwidth_update)(struct radeon_device *rdev);
1794 /* get frame count */
1795 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1796 /* wait for vblank */
1797 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1798 /* set backlight level */
1799 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1800 /* get backlight level */
1801 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1802 /* audio callbacks */
1803 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1804 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1805 } display;
54e88e06 1806 /* copy functions for bo handling */
27cd7769
AD		 1807 struct {
1808 int (*blit)(struct radeon_device *rdev,
1809 uint64_t src_offset,
1810 uint64_t dst_offset,
1811 unsigned num_gpu_pages,
876dc9f3 1812 struct radeon_fence **fence);
27cd7769
AD		 1813 u32 blit_ring_index;
1814 int (*dma)(struct radeon_device *rdev,
1815 uint64_t src_offset,
1816 uint64_t dst_offset,
1817 unsigned num_gpu_pages,
876dc9f3 1818 struct radeon_fence **fence);
27cd7769
AD		 1819 u32 dma_ring_index;
1820 /* method used for bo copy */
1821 int (*copy)(struct radeon_device *rdev,
1822 uint64_t src_offset,
1823 uint64_t dst_offset,
1824 unsigned num_gpu_pages,
876dc9f3 1825 struct radeon_fence **fence);
27cd7769
AD		 1826 /* ring used for bo copies */
1827 u32 copy_ring_index;
1828 } copy;
54e88e06 1829 /* surfaces */
9e6f3d02
AD		 1830 struct {
1831 int (*set_reg)(struct radeon_device *rdev, int reg,
1832 uint32_t tiling_flags, uint32_t pitch,
1833 uint32_t offset, uint32_t obj_size);
1834 void (*clear_reg)(struct radeon_device *rdev, int reg);
1835 } surface;
54e88e06 1836 /* hotplug detect */
901ea57d
AD		 1837 struct {
1838 void (*init)(struct radeon_device *rdev);
1839 void (*fini)(struct radeon_device *rdev);
1840 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1841 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1842 } hpd;
da321c8a 1843 /* static power management */
a02fa397
AD		 1844 struct {
1845 void (*misc)(struct radeon_device *rdev);
1846 void (*prepare)(struct radeon_device *rdev);
1847 void (*finish)(struct radeon_device *rdev);
1848 void (*init_profile)(struct radeon_device *rdev);
1849 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1850 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1851 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1852 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1853 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1854 int (*get_pcie_lanes)(struct radeon_device *rdev);
1855 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1856 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1857 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
b59b7333 1858 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
6bd1c385 1859 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1860 } pm;
da321c8a
AD		 1861 /* dynamic power management */
1862 struct {
1863 int (*init)(struct radeon_device *rdev);
1864 void (*setup_asic)(struct radeon_device *rdev);
1865 int (*enable)(struct radeon_device *rdev);
914a8987 1866 int (*late_enable)(struct radeon_device *rdev);
da321c8a 1867 void (*disable)(struct radeon_device *rdev);
84dd1928 1868 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1869 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1870 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1871 void (*display_configuration_changed)(struct radeon_device *rdev);
1872 void (*fini)(struct radeon_device *rdev);
1873 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1874 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1875 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1876 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1877 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1878 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1879 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1c71bda0 1880 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
da321c8a 1881 } dpm;
6f34be50 1882 /* pageflipping */
0f9e006c 1883 struct {
0f9e006c 1884 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
0f9e006c 1885 } pflip;
771fe6b9
JG		 1886};
1887
21f9a437
JG		 1888/*
1889 * Asic structures
1890 */
551ebd83 1891struct r100_asic {
225758d8
JG		 1892 const unsigned *reg_safe_bm;
1893 unsigned reg_safe_bm_size;
1894 u32 hdp_cntl;
551ebd83
DA		 1895};
1896
21f9a437 1897struct r300_asic {
225758d8
JG		 1898 const unsigned *reg_safe_bm;
1899 unsigned reg_safe_bm_size;
1900 u32 resync_scratch;
1901 u32 hdp_cntl;
21f9a437
JG		 1902};
1903
1904struct r600_asic {
225758d8
JG		 1905 unsigned max_pipes;
1906 unsigned max_tile_pipes;
1907 unsigned max_simds;
1908 unsigned max_backends;
1909 unsigned max_gprs;
1910 unsigned max_threads;
1911 unsigned max_stack_entries;
1912 unsigned max_hw_contexts;
1913 unsigned max_gs_threads;
1914 unsigned sx_max_export_size;
1915 unsigned sx_max_export_pos_size;
1916 unsigned sx_max_export_smx_size;
1917 unsigned sq_num_cf_insts;
1918 unsigned tiling_nbanks;
1919 unsigned tiling_npipes;
1920 unsigned tiling_group_size;
e7aeeba6 1921 unsigned tile_config;
e55b9422 1922 unsigned backend_map;
21f9a437
JG		 1923};
1924
1925struct rv770_asic {
225758d8
JG		 1926 unsigned max_pipes;
1927 unsigned max_tile_pipes;
1928 unsigned max_simds;
1929 unsigned max_backends;
1930 unsigned max_gprs;
1931 unsigned max_threads;
1932 unsigned max_stack_entries;
1933 unsigned max_hw_contexts;
1934 unsigned max_gs_threads;
1935 unsigned sx_max_export_size;
1936 unsigned sx_max_export_pos_size;
1937 unsigned sx_max_export_smx_size;
1938 unsigned sq_num_cf_insts;
1939 unsigned sx_num_of_sets;
1940 unsigned sc_prim_fifo_size;
1941 unsigned sc_hiz_tile_fifo_size;
1942 unsigned sc_earlyz_tile_fifo_fize;
1943 unsigned tiling_nbanks;
1944 unsigned tiling_npipes;
1945 unsigned tiling_group_size;
e7aeeba6 1946 unsigned tile_config;
e55b9422 1947 unsigned backend_map;
21f9a437
JG		 1948};
1949
32fcdbf4
AD		 1950struct evergreen_asic {
1951 unsigned num_ses;
1952 unsigned max_pipes;
1953 unsigned max_tile_pipes;
1954 unsigned max_simds;
1955 unsigned max_backends;
1956 unsigned max_gprs;
1957 unsigned max_threads;
1958 unsigned max_stack_entries;
1959 unsigned max_hw_contexts;
1960 unsigned max_gs_threads;
1961 unsigned sx_max_export_size;
1962 unsigned sx_max_export_pos_size;
1963 unsigned sx_max_export_smx_size;
1964 unsigned sq_num_cf_insts;
1965 unsigned sx_num_of_sets;
1966 unsigned sc_prim_fifo_size;
1967 unsigned sc_hiz_tile_fifo_size;
1968 unsigned sc_earlyz_tile_fifo_size;
1969 unsigned tiling_nbanks;
1970 unsigned tiling_npipes;
1971 unsigned tiling_group_size;
e7aeeba6 1972 unsigned tile_config;
e55b9422 1973 unsigned backend_map;
32fcdbf4
AD		 1974};
1975
fecf1d07
AD		 1976struct cayman_asic {
1977 unsigned max_shader_engines;
1978 unsigned max_pipes_per_simd;
1979 unsigned max_tile_pipes;
1980 unsigned max_simds_per_se;
1981 unsigned max_backends_per_se;
1982 unsigned max_texture_channel_caches;
1983 unsigned max_gprs;
1984 unsigned max_threads;
1985 unsigned max_gs_threads;
1986 unsigned max_stack_entries;
1987 unsigned sx_num_of_sets;
1988 unsigned sx_max_export_size;
1989 unsigned sx_max_export_pos_size;
1990 unsigned sx_max_export_smx_size;
1991 unsigned max_hw_contexts;
1992 unsigned sq_num_cf_insts;
1993 unsigned sc_prim_fifo_size;
1994 unsigned sc_hiz_tile_fifo_size;
1995 unsigned sc_earlyz_tile_fifo_size;
1996
1997 unsigned num_shader_engines;
1998 unsigned num_shader_pipes_per_simd;
1999 unsigned num_tile_pipes;
2000 unsigned num_simds_per_se;
2001 unsigned num_backends_per_se;
2002 unsigned backend_disable_mask_per_asic;
2003 unsigned backend_map;
2004 unsigned num_texture_channel_caches;
2005 unsigned mem_max_burst_length_bytes;
2006 unsigned mem_row_size_in_kb;
2007 unsigned shader_engine_tile_size;
2008 unsigned num_gpus;
2009 unsigned multi_gpu_tile_size;
2010
2011 unsigned tile_config;
fecf1d07
AD		 2012};
2013
0a96d72b
AD		 2014struct si_asic {
2015 unsigned max_shader_engines;
0a96d72b 2016 unsigned max_tile_pipes;
1a8ca750
AD		 2017 unsigned max_cu_per_sh;
2018 unsigned max_sh_per_se;
0a96d72b
AD		 2019 unsigned max_backends_per_se;
2020 unsigned max_texture_channel_caches;
2021 unsigned max_gprs;
2022 unsigned max_gs_threads;
2023 unsigned max_hw_contexts;
2024 unsigned sc_prim_fifo_size_frontend;
2025 unsigned sc_prim_fifo_size_backend;
2026 unsigned sc_hiz_tile_fifo_size;
2027 unsigned sc_earlyz_tile_fifo_size;
2028
0a96d72b 2029 unsigned num_tile_pipes;
439a1cff 2030 unsigned backend_enable_mask;
0a96d72b
AD		 2031 unsigned backend_disable_mask_per_asic;
2032 unsigned backend_map;
2033 unsigned num_texture_channel_caches;
2034 unsigned mem_max_burst_length_bytes;
2035 unsigned mem_row_size_in_kb;
2036 unsigned shader_engine_tile_size;
2037 unsigned num_gpus;
2038 unsigned multi_gpu_tile_size;
2039
2040 unsigned tile_config;
64d7b8be 2041 uint32_t tile_mode_array[32];
0a96d72b
AD		 2042};
2043
8cc1a532
AD		 2044struct cik_asic {
2045 unsigned max_shader_engines;
2046 unsigned max_tile_pipes;
2047 unsigned max_cu_per_sh;
2048 unsigned max_sh_per_se;
2049 unsigned max_backends_per_se;
2050 unsigned max_texture_channel_caches;
2051 unsigned max_gprs;
2052 unsigned max_gs_threads;
2053 unsigned max_hw_contexts;
2054 unsigned sc_prim_fifo_size_frontend;
2055 unsigned sc_prim_fifo_size_backend;
2056 unsigned sc_hiz_tile_fifo_size;
2057 unsigned sc_earlyz_tile_fifo_size;
2058
2059 unsigned num_tile_pipes;
439a1cff 2060 unsigned backend_enable_mask;
8cc1a532
AD		 2061 unsigned backend_disable_mask_per_asic;
2062 unsigned backend_map;
2063 unsigned num_texture_channel_caches;
2064 unsigned mem_max_burst_length_bytes;
2065 unsigned mem_row_size_in_kb;
2066 unsigned shader_engine_tile_size;
2067 unsigned num_gpus;
2068 unsigned multi_gpu_tile_size;
2069
2070 unsigned tile_config;
39aee490 2071 uint32_t tile_mode_array[32];
32f79a8a 2072 uint32_t macrotile_mode_array[16];
8cc1a532
AD		 2073};
2074
068a117c
JG		 2075union radeon_asic_config {
2076 struct r300_asic r300;
551ebd83 2077 struct r100_asic r100;
3ce0a23d
JG		 2078 struct r600_asic r600;
2079 struct rv770_asic rv770;
32fcdbf4 2080 struct evergreen_asic evergreen;
fecf1d07 2081 struct cayman_asic cayman;
0a96d72b 2082 struct si_asic si;
8cc1a532 2083 struct cik_asic cik;
068a117c
JG		 2084};
2085
0a10c851
DV		 2086/*
2087 * asic initizalization from radeon_asic.c
2088 */
2089void radeon_agp_disable(struct radeon_device *rdev);
2090int radeon_asic_init(struct radeon_device *rdev);
2091
771fe6b9
JG		 2092
2093/*
2094 * IOCTL.
2095 */
2096int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2097 struct drm_file *filp);
2098int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2099 struct drm_file *filp);
2100int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2101 struct drm_file *file_priv);
2102int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2103 struct drm_file *file_priv);
2104int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2105 struct drm_file *file_priv);
2106int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2107 struct drm_file *file_priv);
2108int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2109 struct drm_file *filp);
2110int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2111 struct drm_file *filp);
2112int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2113 struct drm_file *filp);
2114int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2115 struct drm_file *filp);
721604a1
JG		 2116int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2117 struct drm_file *filp);
bda72d58
MO		 2118int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2119 struct drm_file *filp);
771fe6b9 2120int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 2121int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2122 struct drm_file *filp);
2123int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2124 struct drm_file *filp);
771fe6b9 2125
16cdf04d
AD		 2126/* VRAM scratch page for HDP bug, default vram page */
2127struct r600_vram_scratch {
87cbf8f2
AD		 2128 struct radeon_bo *robj;
2129 volatile uint32_t *ptr;
16cdf04d 2130 u64 gpu_addr;
87cbf8f2 2131};
771fe6b9 2132
fd64ca8a
LT		 2133/*
2134 * ACPI
2135 */
2136struct radeon_atif_notification_cfg {
2137 bool enabled;
2138 int command_code;
2139};
2140
2141struct radeon_atif_notifications {
2142 bool display_switch;
2143 bool expansion_mode_change;
2144 bool thermal_state;
2145 bool forced_power_state;
2146 bool system_power_state;
2147 bool display_conf_change;
2148 bool px_gfx_switch;
2149 bool brightness_change;
2150 bool dgpu_display_event;
2151};
2152
2153struct radeon_atif_functions {
2154 bool system_params;
2155 bool sbios_requests;
2156 bool select_active_disp;
2157 bool lid_state;
2158 bool get_tv_standard;
2159 bool set_tv_standard;
2160 bool get_panel_expansion_mode;
2161 bool set_panel_expansion_mode;
2162 bool temperature_change;
2163 bool graphics_device_types;
2164};
2165
2166struct radeon_atif {
2167 struct radeon_atif_notifications notifications;
2168 struct radeon_atif_functions functions;
2169 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2170 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2171};
7a1619b9 2172
e3a15920
AD		 2173struct radeon_atcs_functions {
2174 bool get_ext_state;
2175 bool pcie_perf_req;
2176 bool pcie_dev_rdy;
2177 bool pcie_bus_width;
2178};
2179
2180struct radeon_atcs {
2181 struct radeon_atcs_functions functions;
2182};
2183
771fe6b9
JG		 2184/*
2185 * Core structure, functions and helpers.
2186 */
2187typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2188typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2189
2190struct radeon_device {
9f022ddf 2191 struct device *dev;
771fe6b9
JG		 2192 struct drm_device *ddev;
2193 struct pci_dev *pdev;
dee53e7f 2194 struct rw_semaphore exclusive_lock;
771fe6b9 2195 /* ASIC */
068a117c 2196 union radeon_asic_config config;
771fe6b9
JG		 2197 enum radeon_family family;
2198 unsigned long flags;
2199 int usec_timeout;
2200 enum radeon_pll_errata pll_errata;
2201 int num_gb_pipes;
f779b3e5 2202 int num_z_pipes;
771fe6b9
JG		 2203 int disp_priority;
2204 /* BIOS */
2205 uint8_t *bios;
2206 bool is_atom_bios;
2207 uint16_t bios_header_start;
4c788679 2208 struct radeon_bo *stollen_vga_memory;
771fe6b9 2209 /* Register mmio */
4c9bc75c
DA		 2210 resource_size_t rmmio_base;
2211 resource_size_t rmmio_size;
2c385151
DV		 2212 /* protects concurrent MM_INDEX/DATA based register access */
2213 spinlock_t mmio_idx_lock;
fe78118c
AD		 2214 /* protects concurrent SMC based register access */
2215 spinlock_t smc_idx_lock;
0a5b7b0b
AD		 2216 /* protects concurrent PLL register access */
2217 spinlock_t pll_idx_lock;
2218 /* protects concurrent MC register access */
2219 spinlock_t mc_idx_lock;
2220 /* protects concurrent PCIE register access */
2221 spinlock_t pcie_idx_lock;
2222 /* protects concurrent PCIE_PORT register access */
2223 spinlock_t pciep_idx_lock;
2224 /* protects concurrent PIF register access */
2225 spinlock_t pif_idx_lock;
2226 /* protects concurrent CG register access */
2227 spinlock_t cg_idx_lock;
2228 /* protects concurrent UVD register access */
2229 spinlock_t uvd_idx_lock;
2230 /* protects concurrent RCU register access */
2231 spinlock_t rcu_idx_lock;
2232 /* protects concurrent DIDT register access */
2233 spinlock_t didt_idx_lock;
2234 /* protects concurrent ENDPOINT (audio) register access */
2235 spinlock_t end_idx_lock;
a0533fbf 2236 void __iomem *rmmio;
771fe6b9
JG		 2237 radeon_rreg_t mc_rreg;
2238 radeon_wreg_t mc_wreg;
2239 radeon_rreg_t pll_rreg;
2240 radeon_wreg_t pll_wreg;
de1b2898 2241 uint32_t pcie_reg_mask;
771fe6b9
JG		 2242 radeon_rreg_t pciep_rreg;
2243 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2244 /* io port */
2245 void __iomem *rio_mem;
2246 resource_size_t rio_mem_size;
771fe6b9
JG		 2247 struct radeon_clock clock;
2248 struct radeon_mc mc;
2249 struct radeon_gart gart;
2250 struct radeon_mode_info mode_info;
2251 struct radeon_scratch scratch;
75efdee1 2252 struct radeon_doorbell doorbell;
771fe6b9 2253 struct radeon_mman mman;
7465280c 2254 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2255 wait_queue_head_t fence_queue;
d6999bc7 2256 struct mutex ring_lock;
e32eb50d 2257 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2258 bool ib_pool_ready;
2259 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2260 struct radeon_irq irq;
2261 struct radeon_asic *asic;
2262 struct radeon_gem gem;
c93bb85b 2263 struct radeon_pm pm;
f2ba57b5 2264 struct radeon_uvd uvd;
d93f7937 2265 struct radeon_vce vce;
f657c2a7 2266 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2267 struct radeon_wb wb;
3ce0a23d 2268 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2269 bool shutdown;
2270 bool suspend;
ad49f501 2271 bool need_dma32;
733289c2 2272 bool accel_working;
a0a53aa8 2273 bool fastfb_working; /* IGP feature*/
f9eaf9ae 2274 bool needs_reset;
e024e110 2275 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2276 const struct firmware *me_fw; /* all family ME firmware */
2277 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2278 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2279 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2280 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2281 const struct firmware *mec_fw; /* CIK MEC firmware */
21a93e13 2282 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2283 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2284 const struct firmware *uvd_fw; /* UVD firmware */
d93f7937 2285 const struct firmware *vce_fw; /* VCE firmware */
16cdf04d 2286 struct r600_vram_scratch vram_scratch;
3e5cb98d 2287 int msi_enabled; /* msi enabled */
d8f60cfc 2288 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2289 struct radeon_rlc rlc;
963e81f9 2290 struct radeon_mec mec;
d4877cf2 2291 struct work_struct hotplug_work;
f122c610 2292 struct work_struct audio_work;
8f61b34c 2293 struct work_struct reset_work;
18917b60 2294 int num_crtc; /* number of crtcs */
40bacf16 2295 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
948bee3f 2296 bool has_uvd;
b530602f 2297 struct r600_audio audio; /* audio stuff */
ce8f5370 2298 struct notifier_block acpi_nb;
9eba4a93 2299 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2300 struct drm_file *hyperz_filp;
9eba4a93 2301 struct drm_file *cmask_filp;
f376b94f
AD		 2302 /* i2c buses */
2303 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2304 /* debugfs */
2305 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2306 unsigned debugfs_count;
721604a1
JG		 2307 /* virtual memory */
2308 struct radeon_vm_manager vm_manager;
6759a0a7 2309 struct mutex gpu_clock_mutex;
67e8e3f9
MO		 2310 /* memory stats */
2311 atomic64_t vram_usage;
2312 atomic64_t gtt_usage;
2313 atomic64_t num_bytes_moved;
fd64ca8a
LT		 2314 /* ACPI interface */
2315 struct radeon_atif atif;
e3a15920 2316 struct radeon_atcs atcs;
f61d5b46
AD		 2317 /* srbm instance registers */
2318 struct mutex srbm_mutex;
64d8a728
AD		 2319 /* clock, powergating flags */
2320 u32 cg_flags;
2321 u32 pg_flags;
10ebc0bc
DA		 2322
2323 struct dev_pm_domain vga_pm_domain;
2324 bool have_disp_power_ref;
771fe6b9
JG		 2325};
2326
90c4cde9 2327bool radeon_is_px(struct drm_device *dev);
771fe6b9
JG		 2328int radeon_device_init(struct radeon_device *rdev,
2329 struct drm_device *ddev,
2330 struct pci_dev *pdev,
2331 uint32_t flags);
2332void radeon_device_fini(struct radeon_device *rdev);
2333int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2334
2ef9bdfe
DV		 2335uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2336 bool always_indirect);
2337void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2338 bool always_indirect);
6fcbef7a
AK		 2339u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2340void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2341
d5754ab8
AL		 2342u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2343void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
75efdee1 2344
4c788679
JG		 2345/*
2346 * Cast helper
2347 */
2348#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 2349
2350/*
2351 * Registers read & write functions.
2352 */
a0533fbf
BH		 2353#define RREG8(reg) readb((rdev->rmmio) + (reg))
2354#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2355#define RREG16(reg) readw((rdev->rmmio) + (reg))
2356#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2357#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2358#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2359#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2360#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2361#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2362#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2363#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2364#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2365#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2366#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2367#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2368#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2369#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2370#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2371#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2372#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2373#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2374#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2375#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2376#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2377#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2378#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2379#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2380#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2381#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2382#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2383#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2384#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2385#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2386#define WREG32_P(reg, val, mask) \
2387 do { \
2388 uint32_t tmp_ = RREG32(reg); \
2389 tmp_ &= (mask); \
2390 tmp_ |= ((val) & ~(mask)); \
2391 WREG32(reg, tmp_); \
2392 } while (0)
d5169fc4 2393#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2394#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2395#define WREG32_PLL_P(reg, val, mask) \
2396 do { \
2397 uint32_t tmp_ = RREG32_PLL(reg); \
2398 tmp_ &= (mask); \
2399 tmp_ |= ((val) & ~(mask)); \
2400 WREG32_PLL(reg, tmp_); \
2401 } while (0)
2ef9bdfe 2402#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2403#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2404#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2405
d5754ab8
AL		 2406#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2407#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
75efdee1 2408
de1b2898
DA		 2409/*
2410 * Indirect registers accessor
2411 */
2412static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2413{
0a5b7b0b 2414 unsigned long flags;
de1b2898
DA		 2415 uint32_t r;
2416
0a5b7b0b 2417 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2418 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2419 r = RREG32(RADEON_PCIE_DATA);
0a5b7b0b 2420 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2421 return r;
2422}
2423
2424static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2425{
0a5b7b0b
AD		 2426 unsigned long flags;
2427
2428 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2429 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2430 WREG32(RADEON_PCIE_DATA, (v));
0a5b7b0b 2431 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2432}
2433
1d5d0c34
AD		 2434static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2435{
fe78118c 2436 unsigned long flags;
1d5d0c34
AD		 2437 u32 r;
2438
fe78118c 2439 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2440 WREG32(TN_SMC_IND_INDEX_0, (reg));
2441 r = RREG32(TN_SMC_IND_DATA_0);
fe78118c 2442 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2443 return r;
2444}
2445
2446static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2447{
fe78118c
AD		 2448 unsigned long flags;
2449
2450 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2451 WREG32(TN_SMC_IND_INDEX_0, (reg));
2452 WREG32(TN_SMC_IND_DATA_0, (v));
fe78118c 2453 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2454}
2455
ff82bbc4
AD		 2456static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2457{
0a5b7b0b 2458 unsigned long flags;
ff82bbc4
AD		 2459 u32 r;
2460
0a5b7b0b 2461 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2462 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2463 r = RREG32(R600_RCU_DATA);
0a5b7b0b 2464 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2465 return r;
2466}
2467
2468static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2469{
0a5b7b0b
AD		 2470 unsigned long flags;
2471
2472 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2473 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2474 WREG32(R600_RCU_DATA, (v));
0a5b7b0b 2475 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2476}
2477
46f9564a
AD		 2478static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2479{
0a5b7b0b 2480 unsigned long flags;
46f9564a
AD		 2481 u32 r;
2482
0a5b7b0b 2483 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2484 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2485 r = RREG32(EVERGREEN_CG_IND_DATA);
0a5b7b0b 2486 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2487 return r;
2488}
2489
2490static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2491{
0a5b7b0b
AD		 2492 unsigned long flags;
2493
2494 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2495 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2496 WREG32(EVERGREEN_CG_IND_DATA, (v));
0a5b7b0b 2497 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2498}
2499
792edd69
AD		 2500static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2501{
0a5b7b0b 2502 unsigned long flags;
792edd69
AD		 2503 u32 r;
2504
0a5b7b0b 2505 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2506 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2507 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
0a5b7b0b 2508 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2509 return r;
2510}
2511
2512static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2513{
0a5b7b0b
AD		 2514 unsigned long flags;
2515
2516 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2517 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2518 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
0a5b7b0b 2519 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2520}
2521
2522static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2523{
0a5b7b0b 2524 unsigned long flags;
792edd69
AD		 2525 u32 r;
2526
0a5b7b0b 2527 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2528 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2529 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
0a5b7b0b 2530 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2531 return r;
2532}
2533
2534static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2535{
0a5b7b0b
AD		 2536 unsigned long flags;
2537
2538 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2539 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2540 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
0a5b7b0b 2541 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2542}
2543
93656cdd
AD		 2544static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2545{
0a5b7b0b 2546 unsigned long flags;
93656cdd
AD		 2547 u32 r;
2548
0a5b7b0b 2549 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2550 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2551 r = RREG32(R600_UVD_CTX_DATA);
0a5b7b0b 2552 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2553 return r;
2554}
2555
2556static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2557{
0a5b7b0b
AD		 2558 unsigned long flags;
2559
2560 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2561 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2562 WREG32(R600_UVD_CTX_DATA, (v));
0a5b7b0b 2563 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2564}
2565
1d58234d
AD		 2566
2567static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2568{
0a5b7b0b 2569 unsigned long flags;
1d58234d
AD		 2570 u32 r;
2571
0a5b7b0b 2572 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2573 WREG32(CIK_DIDT_IND_INDEX, (reg));
2574 r = RREG32(CIK_DIDT_IND_DATA);
0a5b7b0b 2575 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2576 return r;
2577}
2578
2579static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2580{
0a5b7b0b
AD		 2581 unsigned long flags;
2582
2583 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2584 WREG32(CIK_DIDT_IND_INDEX, (reg));
2585 WREG32(CIK_DIDT_IND_DATA, (v));
0a5b7b0b 2586 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2587}
2588
771fe6b9
JG		 2589void r100_pll_errata_after_index(struct radeon_device *rdev);
2590
2591
2592/*
2593 * ASICs helpers.
2594 */
b995e433
DA		 2595#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2596 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2597#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2598 (rdev->family == CHIP_RV200) || \
2599 (rdev->family == CHIP_RS100) || \
2600 (rdev->family == CHIP_RS200) || \
2601 (rdev->family == CHIP_RV250) || \
2602 (rdev->family == CHIP_RV280) || \
2603 (rdev->family == CHIP_RS300))
2604#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2605 (rdev->family == CHIP_RV350) || \
2606 (rdev->family == CHIP_R350) || \
2607 (rdev->family == CHIP_RV380) || \
2608 (rdev->family == CHIP_R420) || \
2609 (rdev->family == CHIP_R423) || \
2610 (rdev->family == CHIP_RV410) || \
2611 (rdev->family == CHIP_RS400) || \
2612 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2613#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2614 (rdev->ddev->pdev->device == 0x9443) || \
2615 (rdev->ddev->pdev->device == 0x944B) || \
2616 (rdev->ddev->pdev->device == 0x9506) || \
2617 (rdev->ddev->pdev->device == 0x9509) || \
2618 (rdev->ddev->pdev->device == 0x950F) || \
2619 (rdev->ddev->pdev->device == 0x689C) || \
2620 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2621#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2622#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2623 (rdev->family == CHIP_RS690) || \
2624 (rdev->family == CHIP_RS740) || \
2625 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2626#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2627#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2628#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2629#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2630 (rdev->flags & RADEON_IS_IGP))
1fe18305 2631#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2632#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2633#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2634 (rdev->flags & RADEON_IS_IGP))
624d3524 2635#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2636#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2637#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
be0949f5
AD		 2638#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2639#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2640#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI))
771fe6b9 2641
dc50ba7f
AD		 2642#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2643 (rdev->ddev->pdev->device == 0x6850) || \
2644 (rdev->ddev->pdev->device == 0x6858) || \
2645 (rdev->ddev->pdev->device == 0x6859) || \
2646 (rdev->ddev->pdev->device == 0x6840) || \
2647 (rdev->ddev->pdev->device == 0x6841) || \
2648 (rdev->ddev->pdev->device == 0x6842) || \
2649 (rdev->ddev->pdev->device == 0x6843))
2650
771fe6b9
JG		 2651/*
2652 * BIOS helpers.
2653 */
2654#define RBIOS8(i) (rdev->bios[i])
2655#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2656#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2657
2658int radeon_combios_init(struct radeon_device *rdev);
2659void radeon_combios_fini(struct radeon_device *rdev);
2660int radeon_atombios_init(struct radeon_device *rdev);
2661void radeon_atombios_fini(struct radeon_device *rdev);
2662
2663
2664/*
2665 * RING helpers.
2666 */
ce580fab 2667#if DRM_DEBUG_CODE == 0
e32eb50d 2668static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2669{
e32eb50d
CK		 2670 ring->ring[ring->wptr++] = v;
2671 ring->wptr &= ring->ptr_mask;
2672 ring->count_dw--;
2673 ring->ring_free_dw--;
771fe6b9 2674}
ce580fab
AK		 2675#else
2676/* With debugging this is just too big to inline */
e32eb50d 2677void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
ce580fab 2678#endif
771fe6b9
JG		 2679
2680/*
2681 * ASICs macro.
2682 */
068a117c 2683#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2684#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2685#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2686#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2687#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2688#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2689#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850
AD		 2690#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2691#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
05b07147
CK		 2692#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2693#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
43f1214a 2694#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
76a0df85
CK		 2695#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2696#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2697#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2698#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2699#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2700#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2701#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2702#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2703#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2704#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2705#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2706#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2707#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2708#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2709#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2710#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2711#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2712#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2713#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
27cd7769
AD		 2714#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2715#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2716#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2717#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2718#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2719#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2720#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2721#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2722#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2723#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2724#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2725#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2726#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2727#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
b59b7333 2728#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
6bd1c385 2729#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2730#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2731#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2732#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2733#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2734#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2735#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2736#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2737#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2738#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2739#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2740#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2741#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2742#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8 2743#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
69b62ad8
AD		 2744#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2745#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2746#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2747#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2748#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2749#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2750#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
914a8987 2751#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
da321c8a 2752#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2753#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2754#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2755#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2756#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2757#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2758#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2759#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2760#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2761#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2762#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2763#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2764#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
1c71bda0 2765#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
771fe6b9 2766
6cf8a3f5 2767/* Common functions */
700a0cc0 2768/* AGP */
90aca4d2 2769extern int radeon_gpu_reset(struct radeon_device *rdev);
1a0041b8 2770extern void radeon_pci_config_reset(struct radeon_device *rdev);
410a3418 2771extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2772extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2773extern int radeon_modeset_init(struct radeon_device *rdev);
2774extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2775extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2776extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2777extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2778extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2779extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2780extern void radeon_wb_fini(struct radeon_device *rdev);
2781extern int radeon_wb_init(struct radeon_device *rdev);
2782extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2783extern void radeon_surface_init(struct radeon_device *rdev);
2784extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2785extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2786extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2787extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2788extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 2789extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2790extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
10ebc0bc
DA		 2791extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2792extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
53595338 2793extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2794extern void radeon_program_register_sequence(struct radeon_device *rdev,
2795 const u32 *registers,
2796 const u32 array_size);
6cf8a3f5 2797
721604a1
JG		 2798/*
2799 * vm
2800 */
2801int radeon_vm_manager_init(struct radeon_device *rdev);
2802void radeon_vm_manager_fini(struct radeon_device *rdev);
6d2f2944 2803int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2804void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
df0af440
CK		 2805struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2806 struct radeon_vm *vm,
2807 struct list_head *head);
ee60e29f
CK		 2808struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2809 struct radeon_vm *vm, int ring);
fa688343
CK		 2810void radeon_vm_flush(struct radeon_device *rdev,
2811 struct radeon_vm *vm,
2812 int ring);
ee60e29f
CK		 2813void radeon_vm_fence(struct radeon_device *rdev,
2814 struct radeon_vm *vm,
2815 struct radeon_fence *fence);
dce34bfd 2816uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
6d2f2944
CK		 2817int radeon_vm_update_page_directory(struct radeon_device *rdev,
2818 struct radeon_vm *vm);
9c57a6bd
CK		 2819int radeon_vm_bo_update(struct radeon_device *rdev,
2820 struct radeon_vm *vm,
2821 struct radeon_bo *bo,
2822 struct ttm_mem_reg *mem);
721604a1
JG		 2823void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2824 struct radeon_bo *bo);
421ca7ab
CK		 2825struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2826 struct radeon_bo *bo);
e971bd5e
CK		 2827struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2828 struct radeon_vm *vm,
2829 struct radeon_bo *bo);
2830int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2831 struct radeon_bo_va *bo_va,
2832 uint64_t offset,
2833 uint32_t flags);
721604a1 2834int radeon_vm_bo_rmv(struct radeon_device *rdev,
e971bd5e 2835 struct radeon_bo_va *bo_va);
721604a1 2836
f122c610
AD		 2837/* audio */
2838void r600_audio_update_hdmi(struct work_struct *work);
b530602f
AD		 2839struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2840struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
832eafaf
AD		 2841void r600_audio_enable(struct radeon_device *rdev,
2842 struct r600_audio_pin *pin,
2843 bool enable);
2844void dce6_audio_enable(struct radeon_device *rdev,
2845 struct r600_audio_pin *pin,
2846 bool enable);
721604a1 2847
16cdf04d
AD		 2848/*
2849 * R600 vram scratch functions
2850 */
2851int r600_vram_scratch_init(struct radeon_device *rdev);
2852void r600_vram_scratch_fini(struct radeon_device *rdev);
2853
285484e2
JG		 2854/*
2855 * r600 cs checking helper
2856 */
2857unsigned r600_mip_minify(unsigned size, unsigned level);
2858bool r600_fmt_is_valid_color(u32 format);
2859bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2860int r600_fmt_get_blocksize(u32 format);
2861int r600_fmt_get_nblocksx(u32 format, u32 w);
2862int r600_fmt_get_nblocksy(u32 format, u32 h);
2863
3574dda4
DV		 2864/*
2865 * r600 functions used by radeon_encoder.c
2866 */
1b688d08
RM		 2867struct radeon_hdmi_acr {
2868 u32 clock;
2869
2870 int n_32khz;
2871 int cts_32khz;
2872
2873 int n_44_1khz;
2874 int cts_44_1khz;
2875
2876 int n_48khz;
2877 int cts_48khz;
2878
2879};
2880
e55d3e6c
RM		 2881extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2882
416a2bd2
AD		 2883extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2884 u32 tiling_pipe_num,
2885 u32 max_rb_num,
2886 u32 total_max_rb_num,
2887 u32 enabled_rb_mask);
fe251e2f 2888
e55d3e6c
RM		 2889/*
2890 * evergreen functions used by radeon_encoder.c
2891 */
2892
0af62b01 2893extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2894extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2895
c4917074
AD		 2896/* radeon_acpi.c */
2897#if defined(CONFIG_ACPI)
2898extern int radeon_acpi_init(struct radeon_device *rdev);
2899extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2900extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2901extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2902 u8 perf_req, bool advertise);
dc50ba7f 2903extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2904#else
2905static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2906static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2907#endif
d7a2952f 2908
c38f34b5
IH		 2909int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2910 struct radeon_cs_packet *pkt,
2911 unsigned idx);
9ffb7a6d 2912bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2913void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2914 struct radeon_cs_packet *pkt);
e9716993
IH		 2915int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2916 struct radeon_cs_reloc **cs_reloc,
2917 int nomm);
40592a17
IH		 2918int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2919 uint32_t *vline_start_end,
2920 uint32_t *vline_status);
c38f34b5 2921
4c788679
JG		 2922#include "radeon_object.h"
2923
771fe6b9 2924#endif
Linux kernel - Deliverables
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