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drm/radeon: tweak ACCEL_WORKING2 query for the new firmware for hawaii
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
0aea5e4a 67#include <linux/interval_tree.h>
771fe6b9 68
4c788679
JG		 69#include <ttm/ttm_bo_api.h>
70#include <ttm/ttm_bo_driver.h>
71#include <ttm/ttm_placement.h>
72#include <ttm/ttm_module.h>
147666fb 73#include <ttm/ttm_execbuf_util.h>
4c788679 74
c2142715 75#include "radeon_family.h"
771fe6b9
JG		 76#include "radeon_mode.h"
77#include "radeon_reg.h"
771fe6b9
JG		 78
79/*
80 * Modules parameters.
81 */
82extern int radeon_no_wb;
83extern int radeon_modeset;
84extern int radeon_dynclks;
85extern int radeon_r4xx_atom;
86extern int radeon_agpmode;
87extern int radeon_vram_limit;
88extern int radeon_gart_size;
89extern int radeon_benchmarking;
ecc0b326 90extern int radeon_testing;
771fe6b9 91extern int radeon_connector_table;
4ce001ab 92extern int radeon_tv;
dafc3bd5 93extern int radeon_audio;
f46c0120 94extern int radeon_disp_priority;
e2b0a8e1 95extern int radeon_hw_i2c;
d42dd579 96extern int radeon_pcie_gen2;
a18cee15 97extern int radeon_msi;
3368ff0c 98extern int radeon_lockup_timeout;
a0a53aa8 99extern int radeon_fastfb;
da321c8a 100extern int radeon_dpm;
1294d4a3 101extern int radeon_aspm;
10ebc0bc 102extern int radeon_runtime_pm;
363eb0b4 103extern int radeon_hard_reset;
c1c44132 104extern int radeon_vm_size;
4510fb98 105extern int radeon_vm_block_size;
a624f429 106extern int radeon_deep_color;
771fe6b9
JG		 107
108/*
109 * Copy from radeon_drv.h so we don't have to include both and have conflicting
110 * symbol;
111 */
bb635567
JG		 112#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
113#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 114/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 115#define RADEON_IB_POOL_SIZE 16
116#define RADEON_DEBUGFS_MAX_COMPONENTS 32
117#define RADEONFB_CONN_LIMIT 4
118#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 119
bb635567
JG		 120/* fence seq are set to this number when signaled */
121#define RADEON_FENCE_SIGNALED_SEQ 0LL
1b37078b
AD		 122
123/* internal ring indices */
124/* r1xx+ has gfx CP ring */
d93f7937 125#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 126
127/* cayman has 2 compute CP rings */
d93f7937
CK		 128#define CAYMAN_RING_TYPE_CP1_INDEX 1
129#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 130
4d75658b
AD		 131/* R600+ has an async dma ring */
132#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 133/* cayman add a second async dma ring */
134#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 135
f2ba57b5 136/* R600+ */
d93f7937
CK		 137#define R600_RING_TYPE_UVD_INDEX 5
138
139/* TN+ */
140#define TN_RING_TYPE_VCE1_INDEX 6
141#define TN_RING_TYPE_VCE2_INDEX 7
142
143/* max number of rings */
144#define RADEON_NUM_RINGS 8
f2ba57b5 145
1c61eae4
CK		 146/* number of hw syncs before falling back on blocking */
147#define RADEON_NUM_SYNCS 4
f2ba57b5 148
8f53492f
CK		 149/* number of hw syncs before falling back on blocking */
150#define RADEON_NUM_SYNCS 4
151
721604a1 152/* hardcode those limit for now */
ca19f21e 153#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 154#define RADEON_VA_RESERVED_SIZE (8 << 20)
155#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 156
1a0041b8
AD		 157/* hard reset data */
158#define RADEON_ASIC_RESET_DATA 0x39d5e86b
159
ec46c76d
AD		 160/* reset flags */
161#define RADEON_RESET_GFX (1 << 0)
162#define RADEON_RESET_COMPUTE (1 << 1)
163#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 164#define RADEON_RESET_CP (1 << 3)
165#define RADEON_RESET_GRBM (1 << 4)
166#define RADEON_RESET_DMA1 (1 << 5)
167#define RADEON_RESET_RLC (1 << 6)
168#define RADEON_RESET_SEM (1 << 7)
169#define RADEON_RESET_IH (1 << 8)
170#define RADEON_RESET_VMC (1 << 9)
171#define RADEON_RESET_MC (1 << 10)
172#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 173
22c775ce
AD		 174/* CG block flags */
175#define RADEON_CG_BLOCK_GFX (1 << 0)
176#define RADEON_CG_BLOCK_MC (1 << 1)
177#define RADEON_CG_BLOCK_SDMA (1 << 2)
178#define RADEON_CG_BLOCK_UVD (1 << 3)
179#define RADEON_CG_BLOCK_VCE (1 << 4)
180#define RADEON_CG_BLOCK_HDP (1 << 5)
e16866ec 181#define RADEON_CG_BLOCK_BIF (1 << 6)
22c775ce 182
64d8a728
AD		 183/* CG flags */
184#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
185#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
186#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
187#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
188#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
189#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
190#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
191#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
192#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
193#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
194#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
195#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
196#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
197#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
198#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
199#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
200#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
201
202/* PG flags */
2b19d17f 203#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
64d8a728
AD		 204#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
205#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
206#define RADEON_PG_SUPPORT_UVD (1 << 3)
207#define RADEON_PG_SUPPORT_VCE (1 << 4)
208#define RADEON_PG_SUPPORT_CP (1 << 5)
209#define RADEON_PG_SUPPORT_GDS (1 << 6)
210#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
211#define RADEON_PG_SUPPORT_SDMA (1 << 8)
212#define RADEON_PG_SUPPORT_ACP (1 << 9)
213#define RADEON_PG_SUPPORT_SAMU (1 << 10)
214
9e05fa1d
AD		 215/* max cursor sizes (in pixels) */
216#define CURSOR_WIDTH 64
217#define CURSOR_HEIGHT 64
218
219#define CIK_CURSOR_WIDTH 128
220#define CIK_CURSOR_HEIGHT 128
221
771fe6b9
JG		 222/*
223 * Errata workarounds.
224 */
225enum radeon_pll_errata {
226 CHIP_ERRATA_R300_CG = 0x00000001,
227 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
228 CHIP_ERRATA_PLL_DELAY = 0x00000004
229};
230
231
232struct radeon_device;
233
234
235/*
236 * BIOS.
237 */
238bool radeon_get_bios(struct radeon_device *rdev);
239
240/*
3ce0a23d 241 * Dummy page
771fe6b9 242 */
3ce0a23d
JG		 243struct radeon_dummy_page {
244 struct page *page;
245 dma_addr_t addr;
246};
247int radeon_dummy_page_init(struct radeon_device *rdev);
248void radeon_dummy_page_fini(struct radeon_device *rdev);
249
771fe6b9 250
3ce0a23d
JG		 251/*
252 * Clocks
253 */
771fe6b9
JG		 254struct radeon_clock {
255 struct radeon_pll p1pll;
256 struct radeon_pll p2pll;
bcc1c2a1 257 struct radeon_pll dcpll;
771fe6b9
JG		 258 struct radeon_pll spll;
259 struct radeon_pll mpll;
260 /* 10 Khz units */
261 uint32_t default_mclk;
262 uint32_t default_sclk;
bcc1c2a1 263 uint32_t default_dispclk;
4489cd62 264 uint32_t current_dispclk;
bcc1c2a1 265 uint32_t dp_extclk;
b20f9bef 266 uint32_t max_pixel_clock;
771fe6b9
JG		 267};
268
7433874e
RM		 269/*
270 * Power management
271 */
272int radeon_pm_init(struct radeon_device *rdev);
914a8987 273int radeon_pm_late_init(struct radeon_device *rdev);
29fb52ca 274void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 275void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 276void radeon_pm_suspend(struct radeon_device *rdev);
277void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 278void radeon_combios_get_power_modes(struct radeon_device *rdev);
279void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 280int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
281 u8 clock_type,
282 u32 clock,
283 bool strobe_mode,
284 struct atom_clock_dividers *dividers);
eaa778af
AD		 285int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
286 u32 clock,
287 bool strobe_mode,
288 struct atom_mpll_param *mpll_param);
8a83ec5e 289void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 290int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
291 u16 voltage_level, u8 voltage_type,
292 u32 *gpio_value, u32 *gpio_mask);
293void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
294 u32 eng_clock, u32 mem_clock);
295int radeon_atom_get_voltage_step(struct radeon_device *rdev,
296 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 297int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
298 u16 voltage_id, u16 *voltage);
beb79f40
AD		 299int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
300 u16 *voltage,
301 u16 leakage_idx);
cc8dbbb4
AD		 302int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
303 u16 *leakage_id);
304int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
305 u16 *vddc, u16 *vddci,
306 u16 virtual_voltage_id,
307 u16 vbios_voltage_id);
e9f274b2
AD		 308int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
309 u16 virtual_voltage_id,
310 u16 *voltage);
ae5b0abb
AD		 311int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
312 u8 voltage_type,
313 u16 nominal_voltage,
314 u16 *true_voltage);
315int radeon_atom_get_min_voltage(struct radeon_device *rdev,
316 u8 voltage_type, u16 *min_voltage);
317int radeon_atom_get_max_voltage(struct radeon_device *rdev,
318 u8 voltage_type, u16 *max_voltage);
319int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 320 u8 voltage_type, u8 voltage_mode,
ae5b0abb 321 struct atom_voltage_table *voltage_table);
58653abd
AD		 322bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
323 u8 voltage_type, u8 voltage_mode);
636e2582
AD		 324int radeon_atom_get_svi2_info(struct radeon_device *rdev,
325 u8 voltage_type,
326 u8 *svd_gpio_id, u8 *svc_gpio_id);
ae5b0abb
AD		 327void radeon_atom_update_memory_dll(struct radeon_device *rdev,
328 u32 mem_clock);
329void radeon_atom_set_ac_timing(struct radeon_device *rdev,
330 u32 mem_clock);
331int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
332 u8 module_index,
333 struct atom_mc_reg_table *reg_table);
334int radeon_atom_get_memory_info(struct radeon_device *rdev,
335 u8 module_index, struct atom_memory_info *mem_info);
336int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
337 bool gddr5, u8 module_index,
338 struct atom_memory_clock_range_table *mclk_range_table);
339int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
340 u16 voltage_id, u16 *voltage);
f892034a 341void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 342extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
343 unsigned *bankh, unsigned *mtaspect,
344 unsigned *tile_split);
3ce0a23d 345
771fe6b9
JG		 346/*
347 * Fences.
348 */
349struct radeon_fence_driver {
350 uint32_t scratch_reg;
30eb77f4
JG		 351 uint64_t gpu_addr;
352 volatile uint32_t *cpu_addr;
68e250b7
CK		 353 /* sync_seq is protected by ring emission lock */
354 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 355 atomic64_t last_seq;
0a0c7596 356 bool initialized;
771fe6b9
JG		 357};
358
359struct radeon_fence {
360 struct radeon_device *rdev;
361 struct kref kref;
771fe6b9 362 /* protected by radeon_fence.lock */
bb635567 363 uint64_t seq;
7465280c 364 /* RB, DMA, etc. */
bb635567 365 unsigned ring;
771fe6b9
JG		 366};
367
30eb77f4
JG		 368int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
369int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 370void radeon_fence_driver_fini(struct radeon_device *rdev);
76903b96 371void radeon_fence_driver_force_completion(struct radeon_device *rdev);
876dc9f3 372int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 373void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 374bool radeon_fence_signaled(struct radeon_fence *fence);
375int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
37615527
CK		 376int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
377int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
0085c950
JG		 378int radeon_fence_wait_any(struct radeon_device *rdev,
379 struct radeon_fence **fences,
380 bool intr);
771fe6b9
JG		 381struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
382void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 383unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 384bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
385void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
386static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
387 struct radeon_fence *b)
388{
389 if (!a) {
390 return b;
391 }
392
393 if (!b) {
394 return a;
395 }
396
397 BUG_ON(a->ring != b->ring);
398
399 if (a->seq > b->seq) {
400 return a;
401 } else {
402 return b;
403 }
404}
771fe6b9 405
ee60e29f
CK		 406static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
407 struct radeon_fence *b)
408{
409 if (!a) {
410 return false;
411 }
412
413 if (!b) {
414 return true;
415 }
416
417 BUG_ON(a->ring != b->ring);
418
419 return a->seq < b->seq;
420}
421
e024e110
DA		 422/*
423 * Tiling registers
424 */
425struct radeon_surface_reg {
4c788679 426 struct radeon_bo *bo;
e024e110
DA		 427};
428
429#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 430
431/*
4c788679 432 * TTM.
771fe6b9 433 */
4c788679
JG		 434struct radeon_mman {
435 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 436 struct drm_global_reference mem_global_ref;
4c788679 437 struct ttm_bo_device bdev;
0a0c7596
JG		 438 bool mem_global_referenced;
439 bool initialized;
2014b569
CK		 440
441#if defined(CONFIG_DEBUG_FS)
442 struct dentry *vram;
dd66d20e 443 struct dentry *gtt;
2014b569 444#endif
4c788679
JG		 445};
446
721604a1
JG		 447/* bo virtual address in a specific vm */
448struct radeon_bo_va {
e971bd5e 449 /* protected by bo being reserved */
721604a1 450 struct list_head bo_list;
721604a1 451 uint32_t flags;
e31ad969 452 uint64_t addr;
e971bd5e
CK		 453 unsigned ref_count;
454
455 /* protected by vm mutex */
0aea5e4a 456 struct interval_tree_node it;
036bf46a 457 struct list_head vm_status;
e971bd5e
CK		 458
459 /* constant after initialization */
460 struct radeon_vm *vm;
461 struct radeon_bo *bo;
721604a1
JG		 462};
463
4c788679
JG		 464struct radeon_bo {
465 /* Protected by gem.mutex */
466 struct list_head list;
467 /* Protected by tbo.reserved */
bda72d58 468 u32 initial_domain;
312ea8da
JG		 469 u32 placements[3];
470 struct ttm_placement placement;
4c788679
JG		 471 struct ttm_buffer_object tbo;
472 struct ttm_bo_kmap_obj kmap;
02376d82 473 u32 flags;
4c788679
JG		 474 unsigned pin_count;
475 void *kptr;
476 u32 tiling_flags;
477 u32 pitch;
478 int surface_reg;
721604a1
JG		 479 /* list of all virtual address to which this bo
480 * is associated to
481 */
482 struct list_head va;
4c788679
JG		 483 /* Constant after initialization */
484 struct radeon_device *rdev;
441921d5 485 struct drm_gem_object gem_base;
63bc620b 486
409851f4
JG		 487 struct ttm_bo_kmap_obj dma_buf_vmap;
488 pid_t pid;
4c788679 489};
7e4d15d9 490#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 491
409851f4
JG		 492int radeon_gem_debugfs_init(struct radeon_device *rdev);
493
b15ba512
JG		 494/* sub-allocation manager, it has to be protected by another lock.
495 * By conception this is an helper for other part of the driver
496 * like the indirect buffer or semaphore, which both have their
497 * locking.
498 *
499 * Principe is simple, we keep a list of sub allocation in offset
500 * order (first entry has offset == 0, last entry has the highest
501 * offset).
502 *
503 * When allocating new object we first check if there is room at
504 * the end total_size - (last_object_offset + last_object_size) >=
505 * alloc_size. If so we allocate new object there.
506 *
507 * When there is not enough room at the end, we start waiting for
508 * each sub object until we reach object_offset+object_size >=
509 * alloc_size, this object then become the sub object we return.
510 *
511 * Alignment can't be bigger than page size.
512 *
513 * Hole are not considered for allocation to keep things simple.
514 * Assumption is that there won't be hole (all object on same
515 * alignment).
516 */
517struct radeon_sa_manager {
bfb38d35 518 wait_queue_head_t wq;
b15ba512 519 struct radeon_bo *bo;
c3b7fe8b
CK		 520 struct list_head *hole;
521 struct list_head flist[RADEON_NUM_RINGS];
522 struct list_head olist;
b15ba512
JG		 523 unsigned size;
524 uint64_t gpu_addr;
525 void *cpu_ptr;
526 uint32_t domain;
6c4f978b 527 uint32_t align;
b15ba512
JG		 528};
529
530struct radeon_sa_bo;
531
532/* sub-allocation buffer */
533struct radeon_sa_bo {
c3b7fe8b
CK		 534 struct list_head olist;
535 struct list_head flist;
b15ba512 536 struct radeon_sa_manager *manager;
e6661a96
CK		 537 unsigned soffset;
538 unsigned eoffset;
557017a0 539 struct radeon_fence *fence;
b15ba512
JG		 540};
541
771fe6b9
JG		 542/*
543 * GEM objects.
544 */
545struct radeon_gem {
4c788679 546 struct mutex mutex;
771fe6b9
JG		 547 struct list_head objects;
548};
549
550int radeon_gem_init(struct radeon_device *rdev);
551void radeon_gem_fini(struct radeon_device *rdev);
391bfec3 552int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
4c788679 553 int alignment, int initial_domain,
ed5cb43f 554 u32 flags, bool kernel,
4c788679 555 struct drm_gem_object **obj);
771fe6b9 556
ff72145b
DA		 557int radeon_mode_dumb_create(struct drm_file *file_priv,
558 struct drm_device *dev,
559 struct drm_mode_create_dumb *args);
560int radeon_mode_dumb_mmap(struct drm_file *filp,
561 struct drm_device *dev,
562 uint32_t handle, uint64_t *offset_p);
771fe6b9 563
c1341e52
JG		 564/*
565 * Semaphores.
566 */
c1341e52 567struct radeon_semaphore {
a8c05940
JG		 568 struct radeon_sa_bo *sa_bo;
569 signed waiters;
c1341e52 570 uint64_t gpu_addr;
1654b817 571 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
c1341e52
JG		 572};
573
c1341e52
JG		 574int radeon_semaphore_create(struct radeon_device *rdev,
575 struct radeon_semaphore **semaphore);
1654b817 576bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
c1341e52 577 struct radeon_semaphore *semaphore);
1654b817 578bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
c1341e52 579 struct radeon_semaphore *semaphore);
1654b817
CK		 580void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
581 struct radeon_fence *fence);
8f676c4c
CK		 582int radeon_semaphore_sync_rings(struct radeon_device *rdev,
583 struct radeon_semaphore *semaphore,
1654b817 584 int waiting_ring);
c1341e52 585void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 586 struct radeon_semaphore **semaphore,
a8c05940 587 struct radeon_fence *fence);
c1341e52 588
771fe6b9
JG		 589/*
590 * GART structures, functions & helpers
591 */
592struct radeon_mc;
593
a77f1718 594#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 595#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 596#define RADEON_GPU_PAGE_SHIFT 12
721604a1 597#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 598
77497f27
MD		 599#define RADEON_GART_PAGE_DUMMY 0
600#define RADEON_GART_PAGE_VALID (1 << 0)
601#define RADEON_GART_PAGE_READ (1 << 1)
602#define RADEON_GART_PAGE_WRITE (1 << 2)
603#define RADEON_GART_PAGE_SNOOP (1 << 3)
604
771fe6b9
JG		 605struct radeon_gart {
606 dma_addr_t table_addr;
c9a1be96
JG		 607 struct radeon_bo *robj;
608 void *ptr;
771fe6b9
JG		 609 unsigned num_gpu_pages;
610 unsigned num_cpu_pages;
611 unsigned table_size;
771fe6b9
JG		 612 struct page **pages;
613 dma_addr_t *pages_addr;
614 bool ready;
615};
616
617int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
618void radeon_gart_table_ram_free(struct radeon_device *rdev);
619int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
620void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 621int radeon_gart_table_vram_pin(struct radeon_device *rdev);
622void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 623int radeon_gart_init(struct radeon_device *rdev);
624void radeon_gart_fini(struct radeon_device *rdev);
625void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
626 int pages);
627int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516 628 int pages, struct page **pagelist,
77497f27 629 dma_addr_t *dma_addr, uint32_t flags);
771fe6b9
JG		 630
631
632/*
633 * GPU MC structures, functions & helpers
634 */
635struct radeon_mc {
636 resource_size_t aper_size;
637 resource_size_t aper_base;
638 resource_size_t agp_base;
7a50f01a
DA		 639 /* for some chips with <= 32MB we need to lie
640 * about vram size near mc fb location */
3ce0a23d 641 u64 mc_vram_size;
d594e46a 642 u64 visible_vram_size;
3ce0a23d
JG		 643 u64 gtt_size;
644 u64 gtt_start;
645 u64 gtt_end;
3ce0a23d
JG		 646 u64 vram_start;
647 u64 vram_end;
771fe6b9 648 unsigned vram_width;
3ce0a23d 649 u64 real_vram_size;
771fe6b9
JG		 650 int vram_mtrr;
651 bool vram_is_ddr;
d594e46a 652 bool igp_sideport_enabled;
8d369bb1 653 u64 gtt_base_align;
9ed8b1f9 654 u64 mc_mask;
771fe6b9
JG		 655};
656
06b6476d
AD		 657bool radeon_combios_sideport_present(struct radeon_device *rdev);
658bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 659
660/*
661 * GPU scratch registers structures, functions & helpers
662 */
663struct radeon_scratch {
664 unsigned num_reg;
724c80e1 665 uint32_t reg_base;
771fe6b9
JG		 666 bool free[32];
667 uint32_t reg[32];
668};
669
670int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
671void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
672
75efdee1
AD		 673/*
674 * GPU doorbell structures, functions & helpers
675 */
d5754ab8
AL		 676#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
677
75efdee1 678struct radeon_doorbell {
75efdee1 679 /* doorbell mmio */
d5754ab8
AL		 680 resource_size_t base;
681 resource_size_t size;
682 u32 __iomem *ptr;
683 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
684 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
75efdee1
AD		 685};
686
687int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
688void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771fe6b9
JG		 689
690/*
691 * IRQS.
692 */
6f34be50 693
fa7f517c
CK		 694struct radeon_flip_work {
695 struct work_struct flip_work;
696 struct work_struct unpin_work;
697 struct radeon_device *rdev;
698 int crtc_id;
c60381bd 699 uint64_t base;
6f34be50 700 struct drm_pending_vblank_event *event;
fa7f517c 701 struct radeon_bo *old_rbo;
fa7f517c 702 struct radeon_fence *fence;
6f34be50
AD		 703};
704
705struct r500_irq_stat_regs {
706 u32 disp_int;
f122c610 707 u32 hdmi0_status;
6f34be50
AD		 708};
709
710struct r600_irq_stat_regs {
711 u32 disp_int;
712 u32 disp_int_cont;
713 u32 disp_int_cont2;
714 u32 d1grph_int;
715 u32 d2grph_int;
f122c610
AD		 716 u32 hdmi0_status;
717 u32 hdmi1_status;
6f34be50
AD		 718};
719
720struct evergreen_irq_stat_regs {
721 u32 disp_int;
722 u32 disp_int_cont;
723 u32 disp_int_cont2;
724 u32 disp_int_cont3;
725 u32 disp_int_cont4;
726 u32 disp_int_cont5;
727 u32 d1grph_int;
728 u32 d2grph_int;
729 u32 d3grph_int;
730 u32 d4grph_int;
731 u32 d5grph_int;
732 u32 d6grph_int;
f122c610
AD		 733 u32 afmt_status1;
734 u32 afmt_status2;
735 u32 afmt_status3;
736 u32 afmt_status4;
737 u32 afmt_status5;
738 u32 afmt_status6;
6f34be50
AD		 739};
740
a59781bb
AD		 741struct cik_irq_stat_regs {
742 u32 disp_int;
743 u32 disp_int_cont;
744 u32 disp_int_cont2;
745 u32 disp_int_cont3;
746 u32 disp_int_cont4;
747 u32 disp_int_cont5;
748 u32 disp_int_cont6;
f5d636d2
CK		 749 u32 d1grph_int;
750 u32 d2grph_int;
751 u32 d3grph_int;
752 u32 d4grph_int;
753 u32 d5grph_int;
754 u32 d6grph_int;
a59781bb
AD		 755};
756
6f34be50
AD		 757union radeon_irq_stat_regs {
758 struct r500_irq_stat_regs r500;
759 struct r600_irq_stat_regs r600;
760 struct evergreen_irq_stat_regs evergreen;
a59781bb 761 struct cik_irq_stat_regs cik;
6f34be50
AD		 762};
763
771fe6b9 764struct radeon_irq {
fb98257a
CK		 765 bool installed;
766 spinlock_t lock;
736fc37f 767 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 768 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 769 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 770 wait_queue_head_t vblank_queue;
771 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 772 bool afmt[RADEON_MAX_AFMT_BLOCKS];
773 union radeon_irq_stat_regs stat_regs;
4a6369e9 774 bool dpm_thermal;
771fe6b9
JG		 775};
776
777int radeon_irq_kms_init(struct radeon_device *rdev);
778void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b
AD		 779void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
780void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 781void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
782void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 783void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
784void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
785void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
786void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 787
788/*
e32eb50d 789 * CP & rings.
771fe6b9 790 */
7465280c 791
771fe6b9 792struct radeon_ib {
68470ae7
JG		 793 struct radeon_sa_bo *sa_bo;
794 uint32_t length_dw;
795 uint64_t gpu_addr;
796 uint32_t *ptr;
876dc9f3 797 int ring;
68470ae7 798 struct radeon_fence *fence;
4bf3dd92 799 struct radeon_vm *vm;
68470ae7
JG		 800 bool is_const_ib;
801 struct radeon_semaphore *semaphore;
771fe6b9
JG		 802};
803
e32eb50d 804struct radeon_ring {
4c788679 805 struct radeon_bo *ring_obj;
771fe6b9 806 volatile uint32_t *ring;
5596a9db 807 unsigned rptr_offs;
45df6803 808 unsigned rptr_save_reg;
89d35807
AD		 809 u64 next_rptr_gpu_addr;
810 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 811 unsigned wptr;
812 unsigned wptr_old;
813 unsigned ring_size;
814 unsigned ring_free_dw;
815 int count_dw;
aee4aa73
CK		 816 atomic_t last_rptr;
817 atomic64_t last_activity;
771fe6b9
JG		 818 uint64_t gpu_addr;
819 uint32_t align_mask;
820 uint32_t ptr_mask;
771fe6b9 821 bool ready;
78c5560a 822 u32 nop;
8b25ed34 823 u32 idx;
5f0839c1
JG		 824 u64 last_semaphore_signal_addr;
825 u64 last_semaphore_wait_addr;
963e81f9
AD		 826 /* for CIK queues */
827 u32 me;
828 u32 pipe;
829 u32 queue;
830 struct radeon_bo *mqd_obj;
d5754ab8 831 u32 doorbell_index;
963e81f9
AD		 832 unsigned wptr_offs;
833};
834
835struct radeon_mec {
836 struct radeon_bo *hpd_eop_obj;
837 u64 hpd_eop_gpu_addr;
838 u32 num_pipe;
839 u32 num_mec;
840 u32 num_queue;
771fe6b9
JG		 841};
842
721604a1
JG		 843/*
844 * VM
845 */
ee60e29f 846
fa87e62d 847/* maximum number of VMIDs */
ee60e29f
CK		 848#define RADEON_NUM_VM 16
849
fa87e62d 850/* number of entries in page table */
4510fb98 851#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
fa87e62d 852
1c01103c
AD		 853/* PTBs (Page Table Blocks) need to be aligned to 32K */
854#define RADEON_VM_PTB_ALIGN_SIZE 32768
855#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
856#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
857
24c16439
CK		 858#define R600_PTE_VALID (1 << 0)
859#define R600_PTE_SYSTEM (1 << 1)
860#define R600_PTE_SNOOPED (1 << 2)
861#define R600_PTE_READABLE (1 << 5)
862#define R600_PTE_WRITEABLE (1 << 6)
863
ec3dbbcb
CK		 864/* PTE (Page Table Entry) fragment field for different page sizes */
865#define R600_PTE_FRAG_4KB (0 << 7)
866#define R600_PTE_FRAG_64KB (4 << 7)
867#define R600_PTE_FRAG_256KB (6 << 7)
868
33fa9fe3
CK		 869/* flags needed to be set so we can copy directly from the GART table */
870#define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
871 R600_PTE_SYSTEM | R600_PTE_VALID )
0e97703c 872
6d2f2944
CK		 873struct radeon_vm_pt {
874 struct radeon_bo *bo;
875 uint64_t addr;
876};
877
721604a1 878struct radeon_vm {
0aea5e4a 879 struct rb_root va;
ee60e29f 880 unsigned id;
90a51a32 881
e31ad969
CK		 882 /* BOs moved, but not yet updated in the PT */
883 struct list_head invalidated;
884
036bf46a
CK		 885 /* BOs freed, but not yet updated in the PT */
886 struct list_head freed;
887
90a51a32 888 /* contains the page directory */
6d2f2944 889 struct radeon_bo *page_directory;
90a51a32 890 uint64_t pd_gpu_addr;
6d2f2944 891 unsigned max_pde_used;
90a51a32
CK		 892
893 /* array of page tables, one for each page directory entry */
6d2f2944 894 struct radeon_vm_pt *page_tables;
90a51a32 895
cc9e67e3
CK		 896 struct radeon_bo_va *ib_bo_va;
897
721604a1
JG		 898 struct mutex mutex;
899 /* last fence for cs using this vm */
900 struct radeon_fence *fence;
9b40e5d8
CK		 901 /* last flush or NULL if we still need to flush */
902 struct radeon_fence *last_flush;
593b2635
CK		 903 /* last use of vmid */
904 struct radeon_fence *last_id_use;
721604a1
JG		 905};
906
721604a1 907struct radeon_vm_manager {
ee60e29f 908 struct radeon_fence *active[RADEON_NUM_VM];
721604a1 909 uint32_t max_pfn;
721604a1
JG		 910 /* number of VMIDs */
911 unsigned nvm;
912 /* vram base address for page table entry */
913 u64 vram_base_offset;
67e915e4
AD		 914 /* is vm enabled? */
915 bool enabled;
721604a1
JG		 916};
917
918/*
919 * file private structure
920 */
921struct radeon_fpriv {
922 struct radeon_vm vm;
923};
924
d8f60cfc
AD		 925/*
926 * R6xx+ IH ring
927 */
928struct r600_ih {
4c788679 929 struct radeon_bo *ring_obj;
d8f60cfc
AD		 930 volatile uint32_t *ring;
931 unsigned rptr;
d8f60cfc
AD		 932 unsigned ring_size;
933 uint64_t gpu_addr;
d8f60cfc 934 uint32_t ptr_mask;
c20dc369 935 atomic_t lock;
d8f60cfc
AD		 936 bool enabled;
937};
938
347e7592 939/*
2948f5e6 940 * RLC stuff
347e7592 941 */
2948f5e6
AD		 942#include "clearstate_defs.h"
943
944struct radeon_rlc {
347e7592
AD		 945 /* for power gating */
946 struct radeon_bo *save_restore_obj;
947 uint64_t save_restore_gpu_addr;
2948f5e6 948 volatile uint32_t *sr_ptr;
1fd11777 949 const u32 *reg_list;
2948f5e6 950 u32 reg_list_size;
347e7592
AD		 951 /* for clear state */
952 struct radeon_bo *clear_state_obj;
953 uint64_t clear_state_gpu_addr;
2948f5e6 954 volatile uint32_t *cs_ptr;
1fd11777 955 const struct cs_section_def *cs_data;
22c775ce
AD		 956 u32 clear_state_size;
957 /* for cp tables */
958 struct radeon_bo *cp_table_obj;
959 uint64_t cp_table_gpu_addr;
960 volatile uint32_t *cp_table_ptr;
961 u32 cp_table_size;
347e7592
AD		 962};
963
69e130a6 964int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 965 struct radeon_ib *ib, struct radeon_vm *vm,
966 unsigned size);
f2e39221 967void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
4ef72566
CK		 968int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
969 struct radeon_ib *const_ib);
771fe6b9
JG		 970int radeon_ib_pool_init(struct radeon_device *rdev);
971void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 972int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 973/* Ring access between begin & end cannot sleep */
89d35807
AD		 974bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
975 struct radeon_ring *ring);
e32eb50d
CK		 976void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
977int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
978int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
979void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
980void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
d6999bc7 981void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 982void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
983int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
ff212f25
CK		 984void radeon_ring_lockup_update(struct radeon_device *rdev,
985 struct radeon_ring *ring);
069211e5 986bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 987unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
988 uint32_t **data);
989int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
990 unsigned size, uint32_t *data);
e32eb50d 991int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
ea31bf69 992 unsigned rptr_offs, u32 nop);
e32eb50d 993void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 994
995
4d75658b
AD		 996/* r600 async dma */
997void r600_dma_stop(struct radeon_device *rdev);
998int r600_dma_resume(struct radeon_device *rdev);
999void r600_dma_fini(struct radeon_device *rdev);
1000
8c5fd7ef
AD		 1001void cayman_dma_stop(struct radeon_device *rdev);
1002int cayman_dma_resume(struct radeon_device *rdev);
1003void cayman_dma_fini(struct radeon_device *rdev);
1004
771fe6b9
JG		 1005/*
1006 * CS.
1007 */
1008struct radeon_cs_reloc {
1009 struct drm_gem_object *gobj;
4c788679 1010 struct radeon_bo *robj;
df0af440
CK		 1011 struct ttm_validate_buffer tv;
1012 uint64_t gpu_offset;
ce6758c8
CK		 1013 unsigned prefered_domains;
1014 unsigned allowed_domains;
df0af440 1015 uint32_t tiling_flags;
771fe6b9 1016 uint32_t handle;
771fe6b9
JG		 1017};
1018
1019struct radeon_cs_chunk {
1020 uint32_t chunk_id;
1021 uint32_t length_dw;
1022 uint32_t *kdata;
721604a1 1023 void __user *user_ptr;
771fe6b9
JG		 1024};
1025
1026struct radeon_cs_parser {
c8c15ff1 1027 struct device *dev;
771fe6b9
JG		 1028 struct radeon_device *rdev;
1029 struct drm_file *filp;
1030 /* chunks */
1031 unsigned nchunks;
1032 struct radeon_cs_chunk *chunks;
1033 uint64_t *chunks_array;
1034 /* IB */
1035 unsigned idx;
1036 /* relocations */
1037 unsigned nrelocs;
1038 struct radeon_cs_reloc *relocs;
1039 struct radeon_cs_reloc **relocs_ptr;
df0af440 1040 struct radeon_cs_reloc *vm_bos;
771fe6b9 1041 struct list_head validated;
cf4ccd01 1042 unsigned dma_reloc_idx;
771fe6b9
JG		 1043 /* indices of various chunks */
1044 int chunk_ib_idx;
1045 int chunk_relocs_idx;
721604a1 1046 int chunk_flags_idx;
dfcf5f36 1047 int chunk_const_ib_idx;
f2e39221
JG		 1048 struct radeon_ib ib;
1049 struct radeon_ib const_ib;
771fe6b9 1050 void *track;
3ce0a23d 1051 unsigned family;
e70f224c 1052 int parser_error;
721604a1
JG		 1053 u32 cs_flags;
1054 u32 ring;
1055 s32 priority;
ecff665f 1056 struct ww_acquire_ctx ticket;
771fe6b9
JG		 1057};
1058
28a326c5
ML		 1059static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1060{
1061 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1062
1063 if (ibc->kdata)
1064 return ibc->kdata[idx];
1065 return p->ib.ptr[idx];
1066}
1067
513bcb46 1068
771fe6b9
JG		 1069struct radeon_cs_packet {
1070 unsigned idx;
1071 unsigned type;
1072 unsigned reg;
1073 unsigned opcode;
1074 int count;
1075 unsigned one_reg_wr;
1076};
1077
1078typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1079 struct radeon_cs_packet *pkt,
1080 unsigned idx, unsigned reg);
1081typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1082 struct radeon_cs_packet *pkt);
1083
1084
1085/*
1086 * AGP
1087 */
1088int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1089void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1090void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1091void radeon_agp_fini(struct radeon_device *rdev);
1092
1093
1094/*
1095 * Writeback
1096 */
1097struct radeon_wb {
4c788679 1098 struct radeon_bo *wb_obj;
771fe6b9
JG		 1099 volatile uint32_t *wb;
1100 uint64_t gpu_addr;
724c80e1 1101 bool enabled;
d0f8a854 1102 bool use_event;
771fe6b9
JG		 1103};
1104
724c80e1 1105#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1106#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1107#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1108#define RADEON_WB_CP1_RPTR_OFFSET 1280
1109#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1110#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1111#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1112#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1113#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1114#define CIK_WB_CP1_WPTR_OFFSET 3328
1115#define CIK_WB_CP2_WPTR_OFFSET 3584
724c80e1 1116
c93bb85b
JG		 1117/**
1118 * struct radeon_pm - power management datas
1119 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1120 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1121 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1122 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1123 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1124 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1125 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1126 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1127 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1128 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1129 * @needed_bandwidth: current bandwidth needs
1130 *
1131 * It keeps track of various data needed to take powermanagement decision.
25985edc 1132 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1133 * Equation between gpu/memory clock and available bandwidth is hw dependent
1134 * (type of memory, bus size, efficiency, ...)
1135 */
ce8f5370
AD		 1136
1137enum radeon_pm_method {
1138 PM_METHOD_PROFILE,
1139 PM_METHOD_DYNPM,
da321c8a 1140 PM_METHOD_DPM,
ce8f5370
AD		 1141};
1142
1143enum radeon_dynpm_state {
1144 DYNPM_STATE_DISABLED,
1145 DYNPM_STATE_MINIMUM,
1146 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1147 DYNPM_STATE_ACTIVE,
1148 DYNPM_STATE_SUSPENDED,
c913e23a 1149};
ce8f5370
AD		 1150enum radeon_dynpm_action {
1151 DYNPM_ACTION_NONE,
1152 DYNPM_ACTION_MINIMUM,
1153 DYNPM_ACTION_DOWNCLOCK,
1154 DYNPM_ACTION_UPCLOCK,
1155 DYNPM_ACTION_DEFAULT
c913e23a 1156};
56278a8e
AD		 1157
1158enum radeon_voltage_type {
1159 VOLTAGE_NONE = 0,
1160 VOLTAGE_GPIO,
1161 VOLTAGE_VDDC,
1162 VOLTAGE_SW
1163};
1164
0ec0e74f 1165enum radeon_pm_state_type {
da321c8a 1166 /* not used for dpm */
0ec0e74f
AD		 1167 POWER_STATE_TYPE_DEFAULT,
1168 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1169 /* user selectable states */
0ec0e74f
AD		 1170 POWER_STATE_TYPE_BATTERY,
1171 POWER_STATE_TYPE_BALANCED,
1172 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1173 /* internal states */
1174 POWER_STATE_TYPE_INTERNAL_UVD,
1175 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1176 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1177 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1178 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1179 POWER_STATE_TYPE_INTERNAL_BOOT,
1180 POWER_STATE_TYPE_INTERNAL_THERMAL,
1181 POWER_STATE_TYPE_INTERNAL_ACPI,
1182 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1183 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1184};
1185
ce8f5370
AD		 1186enum radeon_pm_profile_type {
1187 PM_PROFILE_DEFAULT,
1188 PM_PROFILE_AUTO,
1189 PM_PROFILE_LOW,
c9e75b21 1190 PM_PROFILE_MID,
ce8f5370
AD		 1191 PM_PROFILE_HIGH,
1192};
1193
1194#define PM_PROFILE_DEFAULT_IDX 0
1195#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1196#define PM_PROFILE_MID_SH_IDX 2
1197#define PM_PROFILE_HIGH_SH_IDX 3
1198#define PM_PROFILE_LOW_MH_IDX 4
1199#define PM_PROFILE_MID_MH_IDX 5
1200#define PM_PROFILE_HIGH_MH_IDX 6
1201#define PM_PROFILE_MAX 7
ce8f5370
AD		 1202
1203struct radeon_pm_profile {
1204 int dpms_off_ps_idx;
1205 int dpms_on_ps_idx;
1206 int dpms_off_cm_idx;
1207 int dpms_on_cm_idx;
516d0e46
AD		 1208};
1209
21a8122a
AD		 1210enum radeon_int_thermal_type {
1211 THERMAL_TYPE_NONE,
da321c8a
AD		 1212 THERMAL_TYPE_EXTERNAL,
1213 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1214 THERMAL_TYPE_RV6XX,
1215 THERMAL_TYPE_RV770,
da321c8a 1216 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1217 THERMAL_TYPE_EVERGREEN,
e33df25f 1218 THERMAL_TYPE_SUMO,
4fddba1f 1219 THERMAL_TYPE_NI,
14607d08 1220 THERMAL_TYPE_SI,
da321c8a 1221 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1222 THERMAL_TYPE_CI,
16fbe00d 1223 THERMAL_TYPE_KV,
21a8122a
AD		 1224};
1225
56278a8e
AD		 1226struct radeon_voltage {
1227 enum radeon_voltage_type type;
1228 /* gpio voltage */
1229 struct radeon_gpio_rec gpio;
1230 u32 delay; /* delay in usec from voltage drop to sclk change */
1231 bool active_high; /* voltage drop is active when bit is high */
1232 /* VDDC voltage */
1233 u8 vddc_id; /* index into vddc voltage table */
1234 u8 vddci_id; /* index into vddci voltage table */
1235 bool vddci_enabled;
1236 /* r6xx+ sw */
2feea49a
AD		 1237 u16 voltage;
1238 /* evergreen+ vddci */
1239 u16 vddci;
56278a8e
AD		 1240};
1241
d7311171
AD		 1242/* clock mode flags */
1243#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1244
56278a8e
AD		 1245struct radeon_pm_clock_info {
1246 /* memory clock */
1247 u32 mclk;
1248 /* engine clock */
1249 u32 sclk;
1250 /* voltage info */
1251 struct radeon_voltage voltage;
d7311171 1252 /* standardized clock flags */
56278a8e
AD		 1253 u32 flags;
1254};
1255
a48b9b4e 1256/* state flags */
d7311171 1257#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1258
56278a8e 1259struct radeon_power_state {
0ec0e74f 1260 enum radeon_pm_state_type type;
8f3f1c9a 1261 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1262 /* number of valid clock modes in this power state */
1263 int num_clock_modes;
56278a8e 1264 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1265 /* standardized state flags */
1266 u32 flags;
79daedc9
AD		 1267 u32 misc; /* vbios specific flags */
1268 u32 misc2; /* vbios specific flags */
1269 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1270};
1271
27459324
RM		 1272/*
1273 * Some modes are overclocked by very low value, accept them
1274 */
1275#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1276
2e9d4c05
AD		 1277enum radeon_dpm_auto_throttle_src {
1278 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1279 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1280};
1281
1282enum radeon_dpm_event_src {
1283 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1284 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1285 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1286 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1287 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1288};
1289
58bd2a88
AD		 1290#define RADEON_MAX_VCE_LEVELS 6
1291
b62d628b
AD		 1292enum radeon_vce_level {
1293 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1294 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1295 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1296 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1297 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1298 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1299};
1300
da321c8a
AD		 1301struct radeon_ps {
1302 u32 caps; /* vbios flags */
1303 u32 class; /* vbios flags */
1304 u32 class2; /* vbios flags */
1305 /* UVD clocks */
1306 u32 vclk;
1307 u32 dclk;
c4453e66
AD		 1308 /* VCE clocks */
1309 u32 evclk;
1310 u32 ecclk;
b62d628b
AD		 1311 bool vce_active;
1312 enum radeon_vce_level vce_level;
da321c8a
AD		 1313 /* asic priv */
1314 void *ps_priv;
1315};
1316
1317struct radeon_dpm_thermal {
1318 /* thermal interrupt work */
1319 struct work_struct work;
1320 /* low temperature threshold */
1321 int min_temp;
1322 /* high temperature threshold */
1323 int max_temp;
1324 /* was interrupt low to high or high to low */
1325 bool high_to_low;
1326};
1327
d22b7e40
AD		 1328enum radeon_clk_action
1329{
1330 RADEON_SCLK_UP = 1,
1331 RADEON_SCLK_DOWN
1332};
1333
1334struct radeon_blacklist_clocks
1335{
1336 u32 sclk;
1337 u32 mclk;
1338 enum radeon_clk_action action;
1339};
1340
61b7d601
AD		 1341struct radeon_clock_and_voltage_limits {
1342 u32 sclk;
1343 u32 mclk;
cdf6e805
AD		 1344 u16 vddc;
1345 u16 vddci;
61b7d601
AD		 1346};
1347
1348struct radeon_clock_array {
1349 u32 count;
1350 u32 *values;
1351};
1352
1353struct radeon_clock_voltage_dependency_entry {
1354 u32 clk;
1355 u16 v;
1356};
1357
1358struct radeon_clock_voltage_dependency_table {
1359 u32 count;
1360 struct radeon_clock_voltage_dependency_entry *entries;
1361};
1362
ef976ec4
AD		 1363union radeon_cac_leakage_entry {
1364 struct {
1365 u16 vddc;
1366 u32 leakage;
1367 };
1368 struct {
1369 u16 vddc1;
1370 u16 vddc2;
1371 u16 vddc3;
1372 };
61b7d601
AD		 1373};
1374
1375struct radeon_cac_leakage_table {
1376 u32 count;
ef976ec4 1377 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1378};
1379
929ee7a8
AD		 1380struct radeon_phase_shedding_limits_entry {
1381 u16 voltage;
1382 u32 sclk;
1383 u32 mclk;
1384};
1385
1386struct radeon_phase_shedding_limits_table {
1387 u32 count;
1388 struct radeon_phase_shedding_limits_entry *entries;
1389};
1390
84a9d9ee
AD		 1391struct radeon_uvd_clock_voltage_dependency_entry {
1392 u32 vclk;
1393 u32 dclk;
1394 u16 v;
1395};
1396
1397struct radeon_uvd_clock_voltage_dependency_table {
1398 u8 count;
1399 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1400};
1401
d29f013b
AD		 1402struct radeon_vce_clock_voltage_dependency_entry {
1403 u32 ecclk;
1404 u32 evclk;
1405 u16 v;
1406};
1407
1408struct radeon_vce_clock_voltage_dependency_table {
1409 u8 count;
1410 struct radeon_vce_clock_voltage_dependency_entry *entries;
1411};
1412
a5cb318e
AD		 1413struct radeon_ppm_table {
1414 u8 ppm_design;
1415 u16 cpu_core_number;
1416 u32 platform_tdp;
1417 u32 small_ac_platform_tdp;
1418 u32 platform_tdc;
1419 u32 small_ac_platform_tdc;
1420 u32 apu_tdp;
1421 u32 dgpu_tdp;
1422 u32 dgpu_ulv_power;
1423 u32 tj_max;
1424};
1425
58cb7632
AD		 1426struct radeon_cac_tdp_table {
1427 u16 tdp;
1428 u16 configurable_tdp;
1429 u16 tdc;
1430 u16 battery_power_limit;
1431 u16 small_power_limit;
1432 u16 low_cac_leakage;
1433 u16 high_cac_leakage;
1434 u16 maximum_power_delivery_limit;
1435};
1436
61b7d601
AD		 1437struct radeon_dpm_dynamic_state {
1438 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1439 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1440 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1441 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1442 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1443 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1444 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1445 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1446 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1447 struct radeon_clock_array valid_sclk_values;
1448 struct radeon_clock_array valid_mclk_values;
1449 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1450 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1451 u32 mclk_sclk_ratio;
1452 u32 sclk_mclk_delta;
1453 u16 vddc_vddci_delta;
1454 u16 min_vddc_for_pcie_gen2;
1455 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1456 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1457 struct radeon_ppm_table *ppm_table;
58cb7632 1458 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1459};
1460
1461struct radeon_dpm_fan {
1462 u16 t_min;
1463 u16 t_med;
1464 u16 t_high;
1465 u16 pwm_min;
1466 u16 pwm_med;
1467 u16 pwm_high;
1468 u8 t_hyst;
1469 u32 cycle_delay;
1470 u16 t_max;
1471 bool ucode_fan_control;
1472};
1473
32ce4652
AD		 1474enum radeon_pcie_gen {
1475 RADEON_PCIE_GEN1 = 0,
1476 RADEON_PCIE_GEN2 = 1,
1477 RADEON_PCIE_GEN3 = 2,
1478 RADEON_PCIE_GEN_INVALID = 0xffff
1479};
1480
70d01a5e
AD		 1481enum radeon_dpm_forced_level {
1482 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1483 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1484 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1485};
1486
58bd2a88
AD		 1487struct radeon_vce_state {
1488 /* vce clocks */
1489 u32 evclk;
1490 u32 ecclk;
1491 /* gpu clocks */
1492 u32 sclk;
1493 u32 mclk;
1494 u8 clk_idx;
1495 u8 pstate;
1496};
1497
da321c8a
AD		 1498struct radeon_dpm {
1499 struct radeon_ps *ps;
1500 /* number of valid power states */
1501 int num_ps;
1502 /* current power state that is active */
1503 struct radeon_ps *current_ps;
1504 /* requested power state */
1505 struct radeon_ps *requested_ps;
1506 /* boot up power state */
1507 struct radeon_ps *boot_ps;
1508 /* default uvd power state */
1509 struct radeon_ps *uvd_ps;
58bd2a88
AD		 1510 /* vce requirements */
1511 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1512 enum radeon_vce_level vce_level;
da321c8a
AD		 1513 enum radeon_pm_state_type state;
1514 enum radeon_pm_state_type user_state;
1515 u32 platform_caps;
1516 u32 voltage_response_time;
1517 u32 backbias_response_time;
1518 void *priv;
1519 u32 new_active_crtcs;
1520 int new_active_crtc_count;
1521 u32 current_active_crtcs;
1522 int current_active_crtc_count;
61b7d601
AD		 1523 struct radeon_dpm_dynamic_state dyn_state;
1524 struct radeon_dpm_fan fan;
1525 u32 tdp_limit;
1526 u32 near_tdp_limit;
a9e61410 1527 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1528 u32 sq_ramping_threshold;
1529 u32 cac_leakage;
1530 u16 tdp_od_limit;
1531 u32 tdp_adjustment;
1532 u16 load_line_slope;
1533 bool power_control;
5ca302f7 1534 bool ac_power;
da321c8a
AD		 1535 /* special states active */
1536 bool thermal_active;
8a227555 1537 bool uvd_active;
b62d628b 1538 bool vce_active;
da321c8a
AD		 1539 /* thermal handling */
1540 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1541 /* forced levels */
1542 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1543 /* track UVD streams */
1544 unsigned sd;
1545 unsigned hd;
da321c8a
AD		 1546};
1547
ce3537d5 1548void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
03afe6f6 1549void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
da321c8a 1550
c93bb85b 1551struct radeon_pm {
c913e23a 1552 struct mutex mutex;
db7fce39
CK		 1553 /* write locked while reprogramming mclk */
1554 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1555 u32 active_crtcs;
1556 int active_crtc_count;
c913e23a 1557 int req_vblank;
839461d3 1558 bool vblank_sync;
c93bb85b
JG		 1559 fixed20_12 max_bandwidth;
1560 fixed20_12 igp_sideport_mclk;
1561 fixed20_12 igp_system_mclk;
1562 fixed20_12 igp_ht_link_clk;
1563 fixed20_12 igp_ht_link_width;
1564 fixed20_12 k8_bandwidth;
1565 fixed20_12 sideport_bandwidth;
1566 fixed20_12 ht_bandwidth;
1567 fixed20_12 core_bandwidth;
1568 fixed20_12 sclk;
f47299c5 1569 fixed20_12 mclk;
c93bb85b 1570 fixed20_12 needed_bandwidth;
0975b162 1571 struct radeon_power_state *power_state;
56278a8e
AD		 1572 /* number of valid power states */
1573 int num_power_states;
a48b9b4e
AD		 1574 int current_power_state_index;
1575 int current_clock_mode_index;
1576 int requested_power_state_index;
1577 int requested_clock_mode_index;
1578 int default_power_state_index;
1579 u32 current_sclk;
1580 u32 current_mclk;
2feea49a
AD		 1581 u16 current_vddc;
1582 u16 current_vddci;
9ace9f7b
AD		 1583 u32 default_sclk;
1584 u32 default_mclk;
2feea49a
AD		 1585 u16 default_vddc;
1586 u16 default_vddci;
29fb52ca 1587 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1588 /* selected pm method */
1589 enum radeon_pm_method pm_method;
1590 /* dynpm power management */
1591 struct delayed_work dynpm_idle_work;
1592 enum radeon_dynpm_state dynpm_state;
1593 enum radeon_dynpm_action dynpm_planned_action;
1594 unsigned long dynpm_action_timeout;
1595 bool dynpm_can_upclock;
1596 bool dynpm_can_downclock;
1597 /* profile-based power management */
1598 enum radeon_pm_profile_type profile;
1599 int profile_index;
1600 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1601 /* internal thermal controller on rv6xx+ */
1602 enum radeon_int_thermal_type int_thermal_type;
1603 struct device *int_hwmon_dev;
da321c8a
AD		 1604 /* dpm */
1605 bool dpm_enabled;
1606 struct radeon_dpm dpm;
c93bb85b
JG		 1607};
1608
a4c9e2ee
AD		 1609int radeon_pm_get_type_index(struct radeon_device *rdev,
1610 enum radeon_pm_state_type ps_type,
1611 int instance);
f2ba57b5
CK		 1612/*
1613 * UVD
1614 */
1615#define RADEON_MAX_UVD_HANDLES 10
1616#define RADEON_UVD_STACK_SIZE (1024*1024)
1617#define RADEON_UVD_HEAP_SIZE (1024*1024)
1618
1619struct radeon_uvd {
1620 struct radeon_bo *vcpu_bo;
1621 void *cpu_addr;
1622 uint64_t gpu_addr;
9cc2e0e9 1623 void *saved_bo;
f2ba57b5
CK		 1624 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1625 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1626 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1627 struct delayed_work idle_work;
f2ba57b5
CK		 1628};
1629
1630int radeon_uvd_init(struct radeon_device *rdev);
1631void radeon_uvd_fini(struct radeon_device *rdev);
1632int radeon_uvd_suspend(struct radeon_device *rdev);
1633int radeon_uvd_resume(struct radeon_device *rdev);
1634int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1635 uint32_t handle, struct radeon_fence **fence);
1636int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1637 uint32_t handle, struct radeon_fence **fence);
1638void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1639void radeon_uvd_free_handles(struct radeon_device *rdev,
1640 struct drm_file *filp);
1641int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1642void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1643int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1644 unsigned vclk, unsigned dclk,
1645 unsigned vco_min, unsigned vco_max,
1646 unsigned fb_factor, unsigned fb_mask,
1647 unsigned pd_min, unsigned pd_max,
1648 unsigned pd_even,
1649 unsigned *optimal_fb_div,
1650 unsigned *optimal_vclk_div,
1651 unsigned *optimal_dclk_div);
1652int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1653 unsigned cg_upll_func_cntl);
771fe6b9 1654
d93f7937
CK		 1655/*
1656 * VCE
1657 */
1658#define RADEON_MAX_VCE_HANDLES 16
1659#define RADEON_VCE_STACK_SIZE (1024*1024)
1660#define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1661
1662struct radeon_vce {
1663 struct radeon_bo *vcpu_bo;
d93f7937 1664 uint64_t gpu_addr;
98ccc291
CK		 1665 unsigned fw_version;
1666 unsigned fb_version;
d93f7937
CK		 1667 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1668 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
2fc5703a 1669 unsigned img_size[RADEON_MAX_VCE_HANDLES];
03afe6f6 1670 struct delayed_work idle_work;
d93f7937
CK		 1671};
1672
1673int radeon_vce_init(struct radeon_device *rdev);
1674void radeon_vce_fini(struct radeon_device *rdev);
1675int radeon_vce_suspend(struct radeon_device *rdev);
1676int radeon_vce_resume(struct radeon_device *rdev);
1677int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1678 uint32_t handle, struct radeon_fence **fence);
1679int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1680 uint32_t handle, struct radeon_fence **fence);
1681void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
03afe6f6 1682void radeon_vce_note_usage(struct radeon_device *rdev);
2fc5703a 1683int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
d93f7937
CK		 1684int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1685bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1686 struct radeon_ring *ring,
1687 struct radeon_semaphore *semaphore,
1688 bool emit_wait);
1689void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1690void radeon_vce_fence_emit(struct radeon_device *rdev,
1691 struct radeon_fence *fence);
1692int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1693int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1694
b530602f 1695struct r600_audio_pin {
a92553ab
RM		 1696 int channels;
1697 int rate;
1698 int bits_per_sample;
1699 u8 status_bits;
1700 u8 category_code;
b530602f
AD		 1701 u32 offset;
1702 bool connected;
1703 u32 id;
1704};
1705
1706struct r600_audio {
1707 bool enabled;
1708 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1709 int num_pins;
a92553ab
RM		 1710};
1711
771fe6b9
JG		 1712/*
1713 * Benchmarking
1714 */
638dd7db 1715void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1716
1717
ecc0b326
MD		 1718/*
1719 * Testing
1720 */
1721void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1722void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1723 struct radeon_ring *cpA,
1724 struct radeon_ring *cpB);
60a7e396 1725void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326
MD		 1726
1727
771fe6b9
JG		 1728/*
1729 * Debugfs
1730 */
4d8bf9ae
CK		 1731struct radeon_debugfs {
1732 struct drm_info_list *files;
1733 unsigned num_files;
1734};
1735
771fe6b9
JG		 1736int radeon_debugfs_add_files(struct radeon_device *rdev,
1737 struct drm_info_list *files,
1738 unsigned nfiles);
1739int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1740
76a0df85
CK		 1741/*
1742 * ASIC ring specific functions.
1743 */
1744struct radeon_asic_ring {
1745 /* ring read/write ptr handling */
1746 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1747 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1748 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1749
1750 /* validating and patching of IBs */
1751 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1752 int (*cs_parse)(struct radeon_cs_parser *p);
1753
1754 /* command emmit functions */
1755 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1756 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
72a9987e 1757 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1654b817 1758 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
76a0df85
CK		 1759 struct radeon_semaphore *semaphore, bool emit_wait);
1760 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1761
1762 /* testing functions */
1763 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1764 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1765 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1766
1767 /* deprecated */
1768 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1769};
771fe6b9
JG		 1770
1771/*
1772 * ASIC specific functions.
1773 */
1774struct radeon_asic {
068a117c 1775 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1776 void (*fini)(struct radeon_device *rdev);
1777 int (*resume)(struct radeon_device *rdev);
1778 int (*suspend)(struct radeon_device *rdev);
28d52043 1779 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1780 int (*asic_reset)(struct radeon_device *rdev);
124764f1
MD		 1781 /* Flush the HDP cache via MMIO */
1782 void (*mmio_hdp_flush)(struct radeon_device *rdev);
54e88e06
AD		 1783 /* check if 3D engine is idle */
1784 bool (*gui_idle)(struct radeon_device *rdev);
1785 /* wait for mc_idle */
1786 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1787 /* get the reference clock */
1788 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1789 /* get the gpu clock counter */
1790 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1791 /* gart */
c5b3b850
AD		 1792 struct {
1793 void (*tlb_flush)(struct radeon_device *rdev);
7f90fc96 1794 void (*set_page)(struct radeon_device *rdev, unsigned i,
77497f27 1795 uint64_t addr, uint32_t flags);
c5b3b850 1796 } gart;
05b07147
CK		 1797 struct {
1798 int (*init)(struct radeon_device *rdev);
1799 void (*fini)(struct radeon_device *rdev);
03f62abd
CK		 1800 void (*copy_pages)(struct radeon_device *rdev,
1801 struct radeon_ib *ib,
1802 uint64_t pe, uint64_t src,
1803 unsigned count);
1804 void (*write_pages)(struct radeon_device *rdev,
1805 struct radeon_ib *ib,
1806 uint64_t pe,
1807 uint64_t addr, unsigned count,
1808 uint32_t incr, uint32_t flags);
1809 void (*set_pages)(struct radeon_device *rdev,
1810 struct radeon_ib *ib,
1811 uint64_t pe,
1812 uint64_t addr, unsigned count,
1813 uint32_t incr, uint32_t flags);
1814 void (*pad_ib)(struct radeon_ib *ib);
05b07147 1815 } vm;
54e88e06 1816 /* ring specific callbacks */
76a0df85 1817 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1818 /* irqs */
b35ea4ab
AD		 1819 struct {
1820 int (*set)(struct radeon_device *rdev);
1821 int (*process)(struct radeon_device *rdev);
1822 } irq;
54e88e06 1823 /* displays */
c79a49ca
AD		 1824 struct {
1825 /* display watermarks */
1826 void (*bandwidth_update)(struct radeon_device *rdev);
1827 /* get frame count */
1828 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1829 /* wait for vblank */
1830 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1831 /* set backlight level */
1832 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1833 /* get backlight level */
1834 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1835 /* audio callbacks */
1836 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1837 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1838 } display;
54e88e06 1839 /* copy functions for bo handling */
27cd7769
AD		 1840 struct {
1841 int (*blit)(struct radeon_device *rdev,
1842 uint64_t src_offset,
1843 uint64_t dst_offset,
1844 unsigned num_gpu_pages,
876dc9f3 1845 struct radeon_fence **fence);
27cd7769
AD		 1846 u32 blit_ring_index;
1847 int (*dma)(struct radeon_device *rdev,
1848 uint64_t src_offset,
1849 uint64_t dst_offset,
1850 unsigned num_gpu_pages,
876dc9f3 1851 struct radeon_fence **fence);
27cd7769
AD		 1852 u32 dma_ring_index;
1853 /* method used for bo copy */
1854 int (*copy)(struct radeon_device *rdev,
1855 uint64_t src_offset,
1856 uint64_t dst_offset,
1857 unsigned num_gpu_pages,
876dc9f3 1858 struct radeon_fence **fence);
27cd7769
AD		 1859 /* ring used for bo copies */
1860 u32 copy_ring_index;
1861 } copy;
54e88e06 1862 /* surfaces */
9e6f3d02
AD		 1863 struct {
1864 int (*set_reg)(struct radeon_device *rdev, int reg,
1865 uint32_t tiling_flags, uint32_t pitch,
1866 uint32_t offset, uint32_t obj_size);
1867 void (*clear_reg)(struct radeon_device *rdev, int reg);
1868 } surface;
54e88e06 1869 /* hotplug detect */
901ea57d
AD		 1870 struct {
1871 void (*init)(struct radeon_device *rdev);
1872 void (*fini)(struct radeon_device *rdev);
1873 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1874 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1875 } hpd;
da321c8a 1876 /* static power management */
a02fa397
AD		 1877 struct {
1878 void (*misc)(struct radeon_device *rdev);
1879 void (*prepare)(struct radeon_device *rdev);
1880 void (*finish)(struct radeon_device *rdev);
1881 void (*init_profile)(struct radeon_device *rdev);
1882 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1883 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1884 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1885 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1886 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1887 int (*get_pcie_lanes)(struct radeon_device *rdev);
1888 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1889 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1890 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
b59b7333 1891 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
6bd1c385 1892 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1893 } pm;
da321c8a
AD		 1894 /* dynamic power management */
1895 struct {
1896 int (*init)(struct radeon_device *rdev);
1897 void (*setup_asic)(struct radeon_device *rdev);
1898 int (*enable)(struct radeon_device *rdev);
914a8987 1899 int (*late_enable)(struct radeon_device *rdev);
da321c8a 1900 void (*disable)(struct radeon_device *rdev);
84dd1928 1901 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1902 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1903 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1904 void (*display_configuration_changed)(struct radeon_device *rdev);
1905 void (*fini)(struct radeon_device *rdev);
1906 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1907 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1908 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1909 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1910 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1911 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1912 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1c71bda0 1913 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
da321c8a 1914 } dpm;
6f34be50 1915 /* pageflipping */
0f9e006c 1916 struct {
157fa14d
CK		 1917 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1918 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
0f9e006c 1919 } pflip;
771fe6b9
JG		 1920};
1921
21f9a437
JG		 1922/*
1923 * Asic structures
1924 */
551ebd83 1925struct r100_asic {
225758d8
JG		 1926 const unsigned *reg_safe_bm;
1927 unsigned reg_safe_bm_size;
1928 u32 hdp_cntl;
551ebd83
DA		 1929};
1930
21f9a437 1931struct r300_asic {
225758d8
JG		 1932 const unsigned *reg_safe_bm;
1933 unsigned reg_safe_bm_size;
1934 u32 resync_scratch;
1935 u32 hdp_cntl;
21f9a437
JG		 1936};
1937
1938struct r600_asic {
225758d8
JG		 1939 unsigned max_pipes;
1940 unsigned max_tile_pipes;
1941 unsigned max_simds;
1942 unsigned max_backends;
1943 unsigned max_gprs;
1944 unsigned max_threads;
1945 unsigned max_stack_entries;
1946 unsigned max_hw_contexts;
1947 unsigned max_gs_threads;
1948 unsigned sx_max_export_size;
1949 unsigned sx_max_export_pos_size;
1950 unsigned sx_max_export_smx_size;
1951 unsigned sq_num_cf_insts;
1952 unsigned tiling_nbanks;
1953 unsigned tiling_npipes;
1954 unsigned tiling_group_size;
e7aeeba6 1955 unsigned tile_config;
e55b9422 1956 unsigned backend_map;
65fcf668 1957 unsigned active_simds;
21f9a437
JG		 1958};
1959
1960struct rv770_asic {
225758d8
JG		 1961 unsigned max_pipes;
1962 unsigned max_tile_pipes;
1963 unsigned max_simds;
1964 unsigned max_backends;
1965 unsigned max_gprs;
1966 unsigned max_threads;
1967 unsigned max_stack_entries;
1968 unsigned max_hw_contexts;
1969 unsigned max_gs_threads;
1970 unsigned sx_max_export_size;
1971 unsigned sx_max_export_pos_size;
1972 unsigned sx_max_export_smx_size;
1973 unsigned sq_num_cf_insts;
1974 unsigned sx_num_of_sets;
1975 unsigned sc_prim_fifo_size;
1976 unsigned sc_hiz_tile_fifo_size;
1977 unsigned sc_earlyz_tile_fifo_fize;
1978 unsigned tiling_nbanks;
1979 unsigned tiling_npipes;
1980 unsigned tiling_group_size;
e7aeeba6 1981 unsigned tile_config;
e55b9422 1982 unsigned backend_map;
65fcf668 1983 unsigned active_simds;
21f9a437
JG		 1984};
1985
32fcdbf4
AD		 1986struct evergreen_asic {
1987 unsigned num_ses;
1988 unsigned max_pipes;
1989 unsigned max_tile_pipes;
1990 unsigned max_simds;
1991 unsigned max_backends;
1992 unsigned max_gprs;
1993 unsigned max_threads;
1994 unsigned max_stack_entries;
1995 unsigned max_hw_contexts;
1996 unsigned max_gs_threads;
1997 unsigned sx_max_export_size;
1998 unsigned sx_max_export_pos_size;
1999 unsigned sx_max_export_smx_size;
2000 unsigned sq_num_cf_insts;
2001 unsigned sx_num_of_sets;
2002 unsigned sc_prim_fifo_size;
2003 unsigned sc_hiz_tile_fifo_size;
2004 unsigned sc_earlyz_tile_fifo_size;
2005 unsigned tiling_nbanks;
2006 unsigned tiling_npipes;
2007 unsigned tiling_group_size;
e7aeeba6 2008 unsigned tile_config;
e55b9422 2009 unsigned backend_map;
65fcf668 2010 unsigned active_simds;
32fcdbf4
AD		 2011};
2012
fecf1d07
AD		 2013struct cayman_asic {
2014 unsigned max_shader_engines;
2015 unsigned max_pipes_per_simd;
2016 unsigned max_tile_pipes;
2017 unsigned max_simds_per_se;
2018 unsigned max_backends_per_se;
2019 unsigned max_texture_channel_caches;
2020 unsigned max_gprs;
2021 unsigned max_threads;
2022 unsigned max_gs_threads;
2023 unsigned max_stack_entries;
2024 unsigned sx_num_of_sets;
2025 unsigned sx_max_export_size;
2026 unsigned sx_max_export_pos_size;
2027 unsigned sx_max_export_smx_size;
2028 unsigned max_hw_contexts;
2029 unsigned sq_num_cf_insts;
2030 unsigned sc_prim_fifo_size;
2031 unsigned sc_hiz_tile_fifo_size;
2032 unsigned sc_earlyz_tile_fifo_size;
2033
2034 unsigned num_shader_engines;
2035 unsigned num_shader_pipes_per_simd;
2036 unsigned num_tile_pipes;
2037 unsigned num_simds_per_se;
2038 unsigned num_backends_per_se;
2039 unsigned backend_disable_mask_per_asic;
2040 unsigned backend_map;
2041 unsigned num_texture_channel_caches;
2042 unsigned mem_max_burst_length_bytes;
2043 unsigned mem_row_size_in_kb;
2044 unsigned shader_engine_tile_size;
2045 unsigned num_gpus;
2046 unsigned multi_gpu_tile_size;
2047
2048 unsigned tile_config;
65fcf668 2049 unsigned active_simds;
fecf1d07
AD		 2050};
2051
0a96d72b
AD		 2052struct si_asic {
2053 unsigned max_shader_engines;
0a96d72b 2054 unsigned max_tile_pipes;
1a8ca750
AD		 2055 unsigned max_cu_per_sh;
2056 unsigned max_sh_per_se;
0a96d72b
AD		 2057 unsigned max_backends_per_se;
2058 unsigned max_texture_channel_caches;
2059 unsigned max_gprs;
2060 unsigned max_gs_threads;
2061 unsigned max_hw_contexts;
2062 unsigned sc_prim_fifo_size_frontend;
2063 unsigned sc_prim_fifo_size_backend;
2064 unsigned sc_hiz_tile_fifo_size;
2065 unsigned sc_earlyz_tile_fifo_size;
2066
0a96d72b 2067 unsigned num_tile_pipes;
439a1cff 2068 unsigned backend_enable_mask;
0a96d72b
AD		 2069 unsigned backend_disable_mask_per_asic;
2070 unsigned backend_map;
2071 unsigned num_texture_channel_caches;
2072 unsigned mem_max_burst_length_bytes;
2073 unsigned mem_row_size_in_kb;
2074 unsigned shader_engine_tile_size;
2075 unsigned num_gpus;
2076 unsigned multi_gpu_tile_size;
2077
2078 unsigned tile_config;
64d7b8be 2079 uint32_t tile_mode_array[32];
65fcf668 2080 uint32_t active_cus;
0a96d72b
AD		 2081};
2082
8cc1a532
AD		 2083struct cik_asic {
2084 unsigned max_shader_engines;
2085 unsigned max_tile_pipes;
2086 unsigned max_cu_per_sh;
2087 unsigned max_sh_per_se;
2088 unsigned max_backends_per_se;
2089 unsigned max_texture_channel_caches;
2090 unsigned max_gprs;
2091 unsigned max_gs_threads;
2092 unsigned max_hw_contexts;
2093 unsigned sc_prim_fifo_size_frontend;
2094 unsigned sc_prim_fifo_size_backend;
2095 unsigned sc_hiz_tile_fifo_size;
2096 unsigned sc_earlyz_tile_fifo_size;
2097
2098 unsigned num_tile_pipes;
439a1cff 2099 unsigned backend_enable_mask;
8cc1a532
AD		 2100 unsigned backend_disable_mask_per_asic;
2101 unsigned backend_map;
2102 unsigned num_texture_channel_caches;
2103 unsigned mem_max_burst_length_bytes;
2104 unsigned mem_row_size_in_kb;
2105 unsigned shader_engine_tile_size;
2106 unsigned num_gpus;
2107 unsigned multi_gpu_tile_size;
2108
2109 unsigned tile_config;
39aee490 2110 uint32_t tile_mode_array[32];
32f79a8a 2111 uint32_t macrotile_mode_array[16];
65fcf668 2112 uint32_t active_cus;
8cc1a532
AD		 2113};
2114
068a117c
JG		 2115union radeon_asic_config {
2116 struct r300_asic r300;
551ebd83 2117 struct r100_asic r100;
3ce0a23d
JG		 2118 struct r600_asic r600;
2119 struct rv770_asic rv770;
32fcdbf4 2120 struct evergreen_asic evergreen;
fecf1d07 2121 struct cayman_asic cayman;
0a96d72b 2122 struct si_asic si;
8cc1a532 2123 struct cik_asic cik;
068a117c
JG		 2124};
2125
0a10c851
DV		 2126/*
2127 * asic initizalization from radeon_asic.c
2128 */
2129void radeon_agp_disable(struct radeon_device *rdev);
2130int radeon_asic_init(struct radeon_device *rdev);
2131
771fe6b9
JG		 2132
2133/*
2134 * IOCTL.
2135 */
2136int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2137 struct drm_file *filp);
2138int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2139 struct drm_file *filp);
2140int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2141 struct drm_file *file_priv);
2142int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2143 struct drm_file *file_priv);
2144int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2145 struct drm_file *file_priv);
2146int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2147 struct drm_file *file_priv);
2148int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2149 struct drm_file *filp);
2150int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2151 struct drm_file *filp);
2152int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2153 struct drm_file *filp);
2154int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2155 struct drm_file *filp);
721604a1
JG		 2156int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2157 struct drm_file *filp);
bda72d58
MO		 2158int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2159 struct drm_file *filp);
771fe6b9 2160int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 2161int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2162 struct drm_file *filp);
2163int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2164 struct drm_file *filp);
771fe6b9 2165
16cdf04d
AD		 2166/* VRAM scratch page for HDP bug, default vram page */
2167struct r600_vram_scratch {
87cbf8f2
AD		 2168 struct radeon_bo *robj;
2169 volatile uint32_t *ptr;
16cdf04d 2170 u64 gpu_addr;
87cbf8f2 2171};
771fe6b9 2172
fd64ca8a
LT		 2173/*
2174 * ACPI
2175 */
2176struct radeon_atif_notification_cfg {
2177 bool enabled;
2178 int command_code;
2179};
2180
2181struct radeon_atif_notifications {
2182 bool display_switch;
2183 bool expansion_mode_change;
2184 bool thermal_state;
2185 bool forced_power_state;
2186 bool system_power_state;
2187 bool display_conf_change;
2188 bool px_gfx_switch;
2189 bool brightness_change;
2190 bool dgpu_display_event;
2191};
2192
2193struct radeon_atif_functions {
2194 bool system_params;
2195 bool sbios_requests;
2196 bool select_active_disp;
2197 bool lid_state;
2198 bool get_tv_standard;
2199 bool set_tv_standard;
2200 bool get_panel_expansion_mode;
2201 bool set_panel_expansion_mode;
2202 bool temperature_change;
2203 bool graphics_device_types;
2204};
2205
2206struct radeon_atif {
2207 struct radeon_atif_notifications notifications;
2208 struct radeon_atif_functions functions;
2209 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2210 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2211};
7a1619b9 2212
e3a15920
AD		 2213struct radeon_atcs_functions {
2214 bool get_ext_state;
2215 bool pcie_perf_req;
2216 bool pcie_dev_rdy;
2217 bool pcie_bus_width;
2218};
2219
2220struct radeon_atcs {
2221 struct radeon_atcs_functions functions;
2222};
2223
771fe6b9
JG		 2224/*
2225 * Core structure, functions and helpers.
2226 */
2227typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2228typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2229
2230struct radeon_device {
9f022ddf 2231 struct device *dev;
771fe6b9
JG		 2232 struct drm_device *ddev;
2233 struct pci_dev *pdev;
dee53e7f 2234 struct rw_semaphore exclusive_lock;
771fe6b9 2235 /* ASIC */
068a117c 2236 union radeon_asic_config config;
771fe6b9
JG		 2237 enum radeon_family family;
2238 unsigned long flags;
2239 int usec_timeout;
2240 enum radeon_pll_errata pll_errata;
2241 int num_gb_pipes;
f779b3e5 2242 int num_z_pipes;
771fe6b9
JG		 2243 int disp_priority;
2244 /* BIOS */
2245 uint8_t *bios;
2246 bool is_atom_bios;
2247 uint16_t bios_header_start;
4c788679 2248 struct radeon_bo *stollen_vga_memory;
771fe6b9 2249 /* Register mmio */
4c9bc75c
DA		 2250 resource_size_t rmmio_base;
2251 resource_size_t rmmio_size;
2c385151
DV		 2252 /* protects concurrent MM_INDEX/DATA based register access */
2253 spinlock_t mmio_idx_lock;
fe78118c
AD		 2254 /* protects concurrent SMC based register access */
2255 spinlock_t smc_idx_lock;
0a5b7b0b
AD		 2256 /* protects concurrent PLL register access */
2257 spinlock_t pll_idx_lock;
2258 /* protects concurrent MC register access */
2259 spinlock_t mc_idx_lock;
2260 /* protects concurrent PCIE register access */
2261 spinlock_t pcie_idx_lock;
2262 /* protects concurrent PCIE_PORT register access */
2263 spinlock_t pciep_idx_lock;
2264 /* protects concurrent PIF register access */
2265 spinlock_t pif_idx_lock;
2266 /* protects concurrent CG register access */
2267 spinlock_t cg_idx_lock;
2268 /* protects concurrent UVD register access */
2269 spinlock_t uvd_idx_lock;
2270 /* protects concurrent RCU register access */
2271 spinlock_t rcu_idx_lock;
2272 /* protects concurrent DIDT register access */
2273 spinlock_t didt_idx_lock;
2274 /* protects concurrent ENDPOINT (audio) register access */
2275 spinlock_t end_idx_lock;
a0533fbf 2276 void __iomem *rmmio;
771fe6b9
JG		 2277 radeon_rreg_t mc_rreg;
2278 radeon_wreg_t mc_wreg;
2279 radeon_rreg_t pll_rreg;
2280 radeon_wreg_t pll_wreg;
de1b2898 2281 uint32_t pcie_reg_mask;
771fe6b9
JG		 2282 radeon_rreg_t pciep_rreg;
2283 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2284 /* io port */
2285 void __iomem *rio_mem;
2286 resource_size_t rio_mem_size;
771fe6b9
JG		 2287 struct radeon_clock clock;
2288 struct radeon_mc mc;
2289 struct radeon_gart gart;
2290 struct radeon_mode_info mode_info;
2291 struct radeon_scratch scratch;
75efdee1 2292 struct radeon_doorbell doorbell;
771fe6b9 2293 struct radeon_mman mman;
7465280c 2294 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2295 wait_queue_head_t fence_queue;
d6999bc7 2296 struct mutex ring_lock;
e32eb50d 2297 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2298 bool ib_pool_ready;
2299 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2300 struct radeon_irq irq;
2301 struct radeon_asic *asic;
2302 struct radeon_gem gem;
c93bb85b 2303 struct radeon_pm pm;
f2ba57b5 2304 struct radeon_uvd uvd;
d93f7937 2305 struct radeon_vce vce;
f657c2a7 2306 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2307 struct radeon_wb wb;
3ce0a23d 2308 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2309 bool shutdown;
2310 bool suspend;
ad49f501 2311 bool need_dma32;
733289c2 2312 bool accel_working;
a0a53aa8 2313 bool fastfb_working; /* IGP feature*/
f9eaf9ae 2314 bool needs_reset;
e024e110 2315 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2316 const struct firmware *me_fw; /* all family ME firmware */
2317 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2318 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2319 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2320 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2321 const struct firmware *mec_fw; /* CIK MEC firmware */
f2c6b0f4 2322 const struct firmware *mec2_fw; /* KV MEC2 firmware */
21a93e13 2323 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2324 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2325 const struct firmware *uvd_fw; /* UVD firmware */
d93f7937 2326 const struct firmware *vce_fw; /* VCE firmware */
629bd33c 2327 bool new_fw;
16cdf04d 2328 struct r600_vram_scratch vram_scratch;
3e5cb98d 2329 int msi_enabled; /* msi enabled */
d8f60cfc 2330 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2331 struct radeon_rlc rlc;
963e81f9 2332 struct radeon_mec mec;
d4877cf2 2333 struct work_struct hotplug_work;
f122c610 2334 struct work_struct audio_work;
8f61b34c 2335 struct work_struct reset_work;
18917b60 2336 int num_crtc; /* number of crtcs */
40bacf16 2337 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
948bee3f 2338 bool has_uvd;
b530602f 2339 struct r600_audio audio; /* audio stuff */
ce8f5370 2340 struct notifier_block acpi_nb;
9eba4a93 2341 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2342 struct drm_file *hyperz_filp;
9eba4a93 2343 struct drm_file *cmask_filp;
f376b94f
AD		 2344 /* i2c buses */
2345 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2346 /* debugfs */
2347 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2348 unsigned debugfs_count;
721604a1
JG		 2349 /* virtual memory */
2350 struct radeon_vm_manager vm_manager;
6759a0a7 2351 struct mutex gpu_clock_mutex;
67e8e3f9
MO		 2352 /* memory stats */
2353 atomic64_t vram_usage;
2354 atomic64_t gtt_usage;
2355 atomic64_t num_bytes_moved;
fd64ca8a
LT		 2356 /* ACPI interface */
2357 struct radeon_atif atif;
e3a15920 2358 struct radeon_atcs atcs;
f61d5b46
AD		 2359 /* srbm instance registers */
2360 struct mutex srbm_mutex;
64d8a728
AD		 2361 /* clock, powergating flags */
2362 u32 cg_flags;
2363 u32 pg_flags;
10ebc0bc
DA		 2364
2365 struct dev_pm_domain vga_pm_domain;
2366 bool have_disp_power_ref;
4807c5a8 2367 u32 px_quirk_flags;
71ecc97e
AD		 2368
2369 /* tracking pinned memory */
2370 u64 vram_pin_size;
2371 u64 gart_pin_size;
771fe6b9
JG		 2372};
2373
90c4cde9 2374bool radeon_is_px(struct drm_device *dev);
771fe6b9
JG		 2375int radeon_device_init(struct radeon_device *rdev,
2376 struct drm_device *ddev,
2377 struct pci_dev *pdev,
2378 uint32_t flags);
2379void radeon_device_fini(struct radeon_device *rdev);
2380int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2381
59bc1d89
LK		 2382#define RADEON_MIN_MMIO_SIZE 0x10000
2383
2384static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2385 bool always_indirect)
2386{
2387 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2388 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2389 return readl(((void __iomem *)rdev->rmmio) + reg);
2390 else {
2391 unsigned long flags;
2392 uint32_t ret;
2393
2394 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2395 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2396 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2397 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2398
2399 return ret;
2400 }
2401}
2402
2403static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2404 bool always_indirect)
2405{
2406 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2407 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2408 else {
2409 unsigned long flags;
2410
2411 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2412 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2413 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2414 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2415 }
2416}
2417
6fcbef7a
AK		 2418u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2419void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2420
d5754ab8
AL		 2421u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2422void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
75efdee1 2423
4c788679
JG		 2424/*
2425 * Cast helper
2426 */
2427#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 2428
2429/*
2430 * Registers read & write functions.
2431 */
a0533fbf
BH		 2432#define RREG8(reg) readb((rdev->rmmio) + (reg))
2433#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2434#define RREG16(reg) readw((rdev->rmmio) + (reg))
2435#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2436#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2437#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2438#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2439#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2440#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2441#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2442#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2443#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2444#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2445#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2446#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2447#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2448#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2449#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2450#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2451#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2452#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2453#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2454#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2455#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2456#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2457#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2458#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2459#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2460#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2461#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2462#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2463#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2464#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2465#define WREG32_P(reg, val, mask) \
2466 do { \
2467 uint32_t tmp_ = RREG32(reg); \
2468 tmp_ &= (mask); \
2469 tmp_ |= ((val) & ~(mask)); \
2470 WREG32(reg, tmp_); \
2471 } while (0)
d5169fc4 2472#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2473#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2474#define WREG32_PLL_P(reg, val, mask) \
2475 do { \
2476 uint32_t tmp_ = RREG32_PLL(reg); \
2477 tmp_ &= (mask); \
2478 tmp_ |= ((val) & ~(mask)); \
2479 WREG32_PLL(reg, tmp_); \
2480 } while (0)
2ef9bdfe 2481#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2482#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2483#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2484
d5754ab8
AL		 2485#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2486#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
75efdee1 2487
de1b2898
DA		 2488/*
2489 * Indirect registers accessor
2490 */
2491static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2492{
0a5b7b0b 2493 unsigned long flags;
de1b2898
DA		 2494 uint32_t r;
2495
0a5b7b0b 2496 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2497 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2498 r = RREG32(RADEON_PCIE_DATA);
0a5b7b0b 2499 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2500 return r;
2501}
2502
2503static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2504{
0a5b7b0b
AD		 2505 unsigned long flags;
2506
2507 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2508 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2509 WREG32(RADEON_PCIE_DATA, (v));
0a5b7b0b 2510 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2511}
2512
1d5d0c34
AD		 2513static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2514{
fe78118c 2515 unsigned long flags;
1d5d0c34
AD		 2516 u32 r;
2517
fe78118c 2518 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2519 WREG32(TN_SMC_IND_INDEX_0, (reg));
2520 r = RREG32(TN_SMC_IND_DATA_0);
fe78118c 2521 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2522 return r;
2523}
2524
2525static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2526{
fe78118c
AD		 2527 unsigned long flags;
2528
2529 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2530 WREG32(TN_SMC_IND_INDEX_0, (reg));
2531 WREG32(TN_SMC_IND_DATA_0, (v));
fe78118c 2532 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2533}
2534
ff82bbc4
AD		 2535static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2536{
0a5b7b0b 2537 unsigned long flags;
ff82bbc4
AD		 2538 u32 r;
2539
0a5b7b0b 2540 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2541 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2542 r = RREG32(R600_RCU_DATA);
0a5b7b0b 2543 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2544 return r;
2545}
2546
2547static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2548{
0a5b7b0b
AD		 2549 unsigned long flags;
2550
2551 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2552 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2553 WREG32(R600_RCU_DATA, (v));
0a5b7b0b 2554 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2555}
2556
46f9564a
AD		 2557static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2558{
0a5b7b0b 2559 unsigned long flags;
46f9564a
AD		 2560 u32 r;
2561
0a5b7b0b 2562 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2563 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2564 r = RREG32(EVERGREEN_CG_IND_DATA);
0a5b7b0b 2565 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2566 return r;
2567}
2568
2569static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2570{
0a5b7b0b
AD		 2571 unsigned long flags;
2572
2573 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2574 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2575 WREG32(EVERGREEN_CG_IND_DATA, (v));
0a5b7b0b 2576 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2577}
2578
792edd69
AD		 2579static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2580{
0a5b7b0b 2581 unsigned long flags;
792edd69
AD		 2582 u32 r;
2583
0a5b7b0b 2584 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2585 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2586 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
0a5b7b0b 2587 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2588 return r;
2589}
2590
2591static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2592{
0a5b7b0b
AD		 2593 unsigned long flags;
2594
2595 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2596 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2597 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
0a5b7b0b 2598 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2599}
2600
2601static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2602{
0a5b7b0b 2603 unsigned long flags;
792edd69
AD		 2604 u32 r;
2605
0a5b7b0b 2606 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2607 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2608 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
0a5b7b0b 2609 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2610 return r;
2611}
2612
2613static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2614{
0a5b7b0b
AD		 2615 unsigned long flags;
2616
2617 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2618 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2619 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
0a5b7b0b 2620 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2621}
2622
93656cdd
AD		 2623static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2624{
0a5b7b0b 2625 unsigned long flags;
93656cdd
AD		 2626 u32 r;
2627
0a5b7b0b 2628 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2629 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2630 r = RREG32(R600_UVD_CTX_DATA);
0a5b7b0b 2631 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2632 return r;
2633}
2634
2635static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2636{
0a5b7b0b
AD		 2637 unsigned long flags;
2638
2639 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2640 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2641 WREG32(R600_UVD_CTX_DATA, (v));
0a5b7b0b 2642 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2643}
2644
1d58234d
AD		 2645
2646static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2647{
0a5b7b0b 2648 unsigned long flags;
1d58234d
AD		 2649 u32 r;
2650
0a5b7b0b 2651 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2652 WREG32(CIK_DIDT_IND_INDEX, (reg));
2653 r = RREG32(CIK_DIDT_IND_DATA);
0a5b7b0b 2654 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2655 return r;
2656}
2657
2658static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2659{
0a5b7b0b
AD		 2660 unsigned long flags;
2661
2662 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2663 WREG32(CIK_DIDT_IND_INDEX, (reg));
2664 WREG32(CIK_DIDT_IND_DATA, (v));
0a5b7b0b 2665 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2666}
2667
771fe6b9
JG		 2668void r100_pll_errata_after_index(struct radeon_device *rdev);
2669
2670
2671/*
2672 * ASICs helpers.
2673 */
b995e433
DA		 2674#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2675 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2676#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2677 (rdev->family == CHIP_RV200) || \
2678 (rdev->family == CHIP_RS100) || \
2679 (rdev->family == CHIP_RS200) || \
2680 (rdev->family == CHIP_RV250) || \
2681 (rdev->family == CHIP_RV280) || \
2682 (rdev->family == CHIP_RS300))
2683#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2684 (rdev->family == CHIP_RV350) || \
2685 (rdev->family == CHIP_R350) || \
2686 (rdev->family == CHIP_RV380) || \
2687 (rdev->family == CHIP_R420) || \
2688 (rdev->family == CHIP_R423) || \
2689 (rdev->family == CHIP_RV410) || \
2690 (rdev->family == CHIP_RS400) || \
2691 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2692#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2693 (rdev->ddev->pdev->device == 0x9443) || \
2694 (rdev->ddev->pdev->device == 0x944B) || \
2695 (rdev->ddev->pdev->device == 0x9506) || \
2696 (rdev->ddev->pdev->device == 0x9509) || \
2697 (rdev->ddev->pdev->device == 0x950F) || \
2698 (rdev->ddev->pdev->device == 0x689C) || \
2699 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2700#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2701#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2702 (rdev->family == CHIP_RS690) || \
2703 (rdev->family == CHIP_RS740) || \
2704 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2705#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2706#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2707#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2708#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2709 (rdev->flags & RADEON_IS_IGP))
1fe18305 2710#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2711#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2712#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2713 (rdev->flags & RADEON_IS_IGP))
624d3524 2714#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2715#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2716#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
be0949f5
AD		 2717#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2718#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
89d2618d
AD		 2719#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2720 (rdev->family == CHIP_MULLINS))
771fe6b9 2721
dc50ba7f
AD		 2722#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2723 (rdev->ddev->pdev->device == 0x6850) || \
2724 (rdev->ddev->pdev->device == 0x6858) || \
2725 (rdev->ddev->pdev->device == 0x6859) || \
2726 (rdev->ddev->pdev->device == 0x6840) || \
2727 (rdev->ddev->pdev->device == 0x6841) || \
2728 (rdev->ddev->pdev->device == 0x6842) || \
2729 (rdev->ddev->pdev->device == 0x6843))
2730
771fe6b9
JG		 2731/*
2732 * BIOS helpers.
2733 */
2734#define RBIOS8(i) (rdev->bios[i])
2735#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2736#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2737
2738int radeon_combios_init(struct radeon_device *rdev);
2739void radeon_combios_fini(struct radeon_device *rdev);
2740int radeon_atombios_init(struct radeon_device *rdev);
2741void radeon_atombios_fini(struct radeon_device *rdev);
2742
2743
2744/*
2745 * RING helpers.
2746 */
ce580fab 2747#if DRM_DEBUG_CODE == 0
e32eb50d 2748static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2749{
e32eb50d
CK		 2750 ring->ring[ring->wptr++] = v;
2751 ring->wptr &= ring->ptr_mask;
2752 ring->count_dw--;
2753 ring->ring_free_dw--;
771fe6b9 2754}
ce580fab
AK		 2755#else
2756/* With debugging this is just too big to inline */
e32eb50d 2757void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
ce580fab 2758#endif
771fe6b9
JG		 2759
2760/*
2761 * ASICs macro.
2762 */
068a117c 2763#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2764#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2765#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2766#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2767#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2768#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2769#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850 2770#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
77497f27 2771#define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f))
05b07147
CK		 2772#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2773#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
03f62abd
CK		 2774#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2775#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2776#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2777#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
76a0df85
CK		 2778#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2779#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2780#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2781#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2782#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2783#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2784#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2785#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2786#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2787#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2788#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2789#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2790#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2791#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2792#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2793#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2794#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2795#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2796#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
27cd7769
AD		 2797#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2798#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2799#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2800#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2801#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2802#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2803#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2804#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2805#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2806#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2807#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2808#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2809#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2810#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
b59b7333 2811#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
6bd1c385 2812#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2813#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2814#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2815#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2816#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2817#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2818#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2819#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2820#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2821#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2822#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2823#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2824#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2825#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8 2826#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
157fa14d 2827#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
69b62ad8
AD		 2828#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2829#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2830#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2831#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2832#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2833#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2834#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
914a8987 2835#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
da321c8a 2836#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2837#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2838#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2839#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2840#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2841#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2842#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2843#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2844#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2845#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2846#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2847#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2848#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
1c71bda0 2849#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
771fe6b9 2850
6cf8a3f5 2851/* Common functions */
700a0cc0 2852/* AGP */
90aca4d2 2853extern int radeon_gpu_reset(struct radeon_device *rdev);
1a0041b8 2854extern void radeon_pci_config_reset(struct radeon_device *rdev);
410a3418 2855extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2856extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2857extern int radeon_modeset_init(struct radeon_device *rdev);
2858extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2859extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2860extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2861extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2862extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2863extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2864extern void radeon_wb_fini(struct radeon_device *rdev);
2865extern int radeon_wb_init(struct radeon_device *rdev);
2866extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2867extern void radeon_surface_init(struct radeon_device *rdev);
2868extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2869extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2870extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2871extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2872extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 2873extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2874extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
10ebc0bc
DA		 2875extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2876extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
53595338 2877extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2878extern void radeon_program_register_sequence(struct radeon_device *rdev,
2879 const u32 *registers,
2880 const u32 array_size);
6cf8a3f5 2881
721604a1
JG		 2882/*
2883 * vm
2884 */
2885int radeon_vm_manager_init(struct radeon_device *rdev);
2886void radeon_vm_manager_fini(struct radeon_device *rdev);
6d2f2944 2887int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2888void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
df0af440
CK		 2889struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2890 struct radeon_vm *vm,
2891 struct list_head *head);
ee60e29f
CK		 2892struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2893 struct radeon_vm *vm, int ring);
fa688343
CK		 2894void radeon_vm_flush(struct radeon_device *rdev,
2895 struct radeon_vm *vm,
2896 int ring);
ee60e29f
CK		 2897void radeon_vm_fence(struct radeon_device *rdev,
2898 struct radeon_vm *vm,
2899 struct radeon_fence *fence);
dce34bfd 2900uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
6d2f2944
CK		 2901int radeon_vm_update_page_directory(struct radeon_device *rdev,
2902 struct radeon_vm *vm);
036bf46a
CK		 2903int radeon_vm_clear_freed(struct radeon_device *rdev,
2904 struct radeon_vm *vm);
e31ad969
CK		 2905int radeon_vm_clear_invalids(struct radeon_device *rdev,
2906 struct radeon_vm *vm);
9c57a6bd 2907int radeon_vm_bo_update(struct radeon_device *rdev,
036bf46a 2908 struct radeon_bo_va *bo_va,
9c57a6bd 2909 struct ttm_mem_reg *mem);
721604a1
JG		 2910void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2911 struct radeon_bo *bo);
421ca7ab
CK		 2912struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2913 struct radeon_bo *bo);
e971bd5e
CK		 2914struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2915 struct radeon_vm *vm,
2916 struct radeon_bo *bo);
2917int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2918 struct radeon_bo_va *bo_va,
2919 uint64_t offset,
2920 uint32_t flags);
036bf46a
CK		 2921void radeon_vm_bo_rmv(struct radeon_device *rdev,
2922 struct radeon_bo_va *bo_va);
721604a1 2923
f122c610
AD		 2924/* audio */
2925void r600_audio_update_hdmi(struct work_struct *work);
b530602f
AD		 2926struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2927struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
832eafaf
AD		 2928void r600_audio_enable(struct radeon_device *rdev,
2929 struct r600_audio_pin *pin,
2930 bool enable);
2931void dce6_audio_enable(struct radeon_device *rdev,
2932 struct r600_audio_pin *pin,
2933 bool enable);
721604a1 2934
16cdf04d
AD		 2935/*
2936 * R600 vram scratch functions
2937 */
2938int r600_vram_scratch_init(struct radeon_device *rdev);
2939void r600_vram_scratch_fini(struct radeon_device *rdev);
2940
285484e2
JG		 2941/*
2942 * r600 cs checking helper
2943 */
2944unsigned r600_mip_minify(unsigned size, unsigned level);
2945bool r600_fmt_is_valid_color(u32 format);
2946bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2947int r600_fmt_get_blocksize(u32 format);
2948int r600_fmt_get_nblocksx(u32 format, u32 w);
2949int r600_fmt_get_nblocksy(u32 format, u32 h);
2950
3574dda4
DV		 2951/*
2952 * r600 functions used by radeon_encoder.c
2953 */
1b688d08
RM		 2954struct radeon_hdmi_acr {
2955 u32 clock;
2956
2957 int n_32khz;
2958 int cts_32khz;
2959
2960 int n_44_1khz;
2961 int cts_44_1khz;
2962
2963 int n_48khz;
2964 int cts_48khz;
2965
2966};
2967
e55d3e6c
RM		 2968extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2969
416a2bd2
AD		 2970extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2971 u32 tiling_pipe_num,
2972 u32 max_rb_num,
2973 u32 total_max_rb_num,
2974 u32 enabled_rb_mask);
fe251e2f 2975
e55d3e6c
RM		 2976/*
2977 * evergreen functions used by radeon_encoder.c
2978 */
2979
0af62b01 2980extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2981extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2982
c4917074
AD		 2983/* radeon_acpi.c */
2984#if defined(CONFIG_ACPI)
2985extern int radeon_acpi_init(struct radeon_device *rdev);
2986extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2987extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2988extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2989 u8 perf_req, bool advertise);
dc50ba7f 2990extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2991#else
2992static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2993static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2994#endif
d7a2952f 2995
c38f34b5
IH		 2996int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2997 struct radeon_cs_packet *pkt,
2998 unsigned idx);
9ffb7a6d 2999bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 3000void radeon_cs_dump_packet(struct radeon_cs_parser *p,
3001 struct radeon_cs_packet *pkt);
e9716993
IH		 3002int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
3003 struct radeon_cs_reloc **cs_reloc,
3004 int nomm);
40592a17
IH		 3005int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
3006 uint32_t *vline_start_end,
3007 uint32_t *vline_status);
c38f34b5 3008
4c788679
JG		 3009#include "radeon_object.h"
3010
771fe6b9 3011#endif
Linux kernel - Deliverables
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