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drm/radeon: use loop for initializing AFMT blocks
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
a18cee15 96extern int radeon_msi;
3368ff0c 97extern int radeon_lockup_timeout;
a0a53aa8 98extern int radeon_fastfb;
da321c8a 99extern int radeon_dpm;
1294d4a3 100extern int radeon_aspm;
771fe6b9
JG		 101
102/*
103 * Copy from radeon_drv.h so we don't have to include both and have conflicting
104 * symbol;
105 */
bb635567
JG		 106#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
107#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 108/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 109#define RADEON_IB_POOL_SIZE 16
110#define RADEON_DEBUGFS_MAX_COMPONENTS 32
111#define RADEONFB_CONN_LIMIT 4
112#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 113
1b37078b 114/* max number of rings */
f2ba57b5 115#define RADEON_NUM_RINGS 6
bb635567
JG		 116
117/* fence seq are set to this number when signaled */
118#define RADEON_FENCE_SIGNALED_SEQ 0LL
1b37078b
AD		 119
120/* internal ring indices */
121/* r1xx+ has gfx CP ring */
f2ba57b5 122#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 123
124/* cayman has 2 compute CP rings */
f2ba57b5
CK		 125#define CAYMAN_RING_TYPE_CP1_INDEX 1
126#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 127
4d75658b
AD		 128/* R600+ has an async dma ring */
129#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 130/* cayman add a second async dma ring */
131#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 132
f2ba57b5
CK		 133/* R600+ */
134#define R600_RING_TYPE_UVD_INDEX 5
135
721604a1 136/* hardcode those limit for now */
ca19f21e 137#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 138#define RADEON_VA_RESERVED_SIZE (8 << 20)
139#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 140
ec46c76d
AD		 141/* reset flags */
142#define RADEON_RESET_GFX (1 << 0)
143#define RADEON_RESET_COMPUTE (1 << 1)
144#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 145#define RADEON_RESET_CP (1 << 3)
146#define RADEON_RESET_GRBM (1 << 4)
147#define RADEON_RESET_DMA1 (1 << 5)
148#define RADEON_RESET_RLC (1 << 6)
149#define RADEON_RESET_SEM (1 << 7)
150#define RADEON_RESET_IH (1 << 8)
151#define RADEON_RESET_VMC (1 << 9)
152#define RADEON_RESET_MC (1 << 10)
153#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 154
22c775ce
AD		 155/* CG block flags */
156#define RADEON_CG_BLOCK_GFX (1 << 0)
157#define RADEON_CG_BLOCK_MC (1 << 1)
158#define RADEON_CG_BLOCK_SDMA (1 << 2)
159#define RADEON_CG_BLOCK_UVD (1 << 3)
160#define RADEON_CG_BLOCK_VCE (1 << 4)
161#define RADEON_CG_BLOCK_HDP (1 << 5)
162
9e05fa1d
AD		 163/* max cursor sizes (in pixels) */
164#define CURSOR_WIDTH 64
165#define CURSOR_HEIGHT 64
166
167#define CIK_CURSOR_WIDTH 128
168#define CIK_CURSOR_HEIGHT 128
169
771fe6b9
JG		 170/*
171 * Errata workarounds.
172 */
173enum radeon_pll_errata {
174 CHIP_ERRATA_R300_CG = 0x00000001,
175 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
176 CHIP_ERRATA_PLL_DELAY = 0x00000004
177};
178
179
180struct radeon_device;
181
182
183/*
184 * BIOS.
185 */
186bool radeon_get_bios(struct radeon_device *rdev);
187
188/*
3ce0a23d 189 * Dummy page
771fe6b9 190 */
3ce0a23d
JG		 191struct radeon_dummy_page {
192 struct page *page;
193 dma_addr_t addr;
194};
195int radeon_dummy_page_init(struct radeon_device *rdev);
196void radeon_dummy_page_fini(struct radeon_device *rdev);
197
771fe6b9 198
3ce0a23d
JG		 199/*
200 * Clocks
201 */
771fe6b9
JG		 202struct radeon_clock {
203 struct radeon_pll p1pll;
204 struct radeon_pll p2pll;
bcc1c2a1 205 struct radeon_pll dcpll;
771fe6b9
JG		 206 struct radeon_pll spll;
207 struct radeon_pll mpll;
208 /* 10 Khz units */
209 uint32_t default_mclk;
210 uint32_t default_sclk;
bcc1c2a1 211 uint32_t default_dispclk;
4489cd62 212 uint32_t current_dispclk;
bcc1c2a1 213 uint32_t dp_extclk;
b20f9bef 214 uint32_t max_pixel_clock;
771fe6b9
JG		 215};
216
7433874e
RM		 217/*
218 * Power management
219 */
220int radeon_pm_init(struct radeon_device *rdev);
29fb52ca 221void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 222void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 223void radeon_pm_suspend(struct radeon_device *rdev);
224void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 225void radeon_combios_get_power_modes(struct radeon_device *rdev);
226void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 227int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
228 u8 clock_type,
229 u32 clock,
230 bool strobe_mode,
231 struct atom_clock_dividers *dividers);
eaa778af
AD		 232int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
233 u32 clock,
234 bool strobe_mode,
235 struct atom_mpll_param *mpll_param);
8a83ec5e 236void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 237int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
238 u16 voltage_level, u8 voltage_type,
239 u32 *gpio_value, u32 *gpio_mask);
240void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
241 u32 eng_clock, u32 mem_clock);
242int radeon_atom_get_voltage_step(struct radeon_device *rdev,
243 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 244int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
245 u16 voltage_id, u16 *voltage);
beb79f40
AD		 246int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
247 u16 *voltage,
248 u16 leakage_idx);
cc8dbbb4
AD		 249int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
250 u16 *leakage_id);
251int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
252 u16 *vddc, u16 *vddci,
253 u16 virtual_voltage_id,
254 u16 vbios_voltage_id);
ae5b0abb
AD		 255int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
256 u8 voltage_type,
257 u16 nominal_voltage,
258 u16 *true_voltage);
259int radeon_atom_get_min_voltage(struct radeon_device *rdev,
260 u8 voltage_type, u16 *min_voltage);
261int radeon_atom_get_max_voltage(struct radeon_device *rdev,
262 u8 voltage_type, u16 *max_voltage);
263int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 264 u8 voltage_type, u8 voltage_mode,
ae5b0abb 265 struct atom_voltage_table *voltage_table);
58653abd
AD		 266bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
267 u8 voltage_type, u8 voltage_mode);
ae5b0abb
AD		 268void radeon_atom_update_memory_dll(struct radeon_device *rdev,
269 u32 mem_clock);
270void radeon_atom_set_ac_timing(struct radeon_device *rdev,
271 u32 mem_clock);
272int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
273 u8 module_index,
274 struct atom_mc_reg_table *reg_table);
275int radeon_atom_get_memory_info(struct radeon_device *rdev,
276 u8 module_index, struct atom_memory_info *mem_info);
277int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
278 bool gddr5, u8 module_index,
279 struct atom_memory_clock_range_table *mclk_range_table);
280int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
281 u16 voltage_id, u16 *voltage);
f892034a 282void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 283extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
284 unsigned *bankh, unsigned *mtaspect,
285 unsigned *tile_split);
3ce0a23d 286
771fe6b9
JG		 287/*
288 * Fences.
289 */
290struct radeon_fence_driver {
291 uint32_t scratch_reg;
30eb77f4
JG		 292 uint64_t gpu_addr;
293 volatile uint32_t *cpu_addr;
68e250b7
CK		 294 /* sync_seq is protected by ring emission lock */
295 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 296 atomic64_t last_seq;
36abacae 297 unsigned long last_activity;
0a0c7596 298 bool initialized;
771fe6b9
JG		 299};
300
301struct radeon_fence {
302 struct radeon_device *rdev;
303 struct kref kref;
771fe6b9 304 /* protected by radeon_fence.lock */
bb635567 305 uint64_t seq;
7465280c 306 /* RB, DMA, etc. */
bb635567 307 unsigned ring;
771fe6b9
JG		 308};
309
30eb77f4
JG		 310int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
311int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 312void radeon_fence_driver_fini(struct radeon_device *rdev);
76903b96 313void radeon_fence_driver_force_completion(struct radeon_device *rdev);
876dc9f3 314int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 315void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 316bool radeon_fence_signaled(struct radeon_fence *fence);
317int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
8a47cc9e 318int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
5f8f635e 319int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
0085c950
JG		 320int radeon_fence_wait_any(struct radeon_device *rdev,
321 struct radeon_fence **fences,
322 bool intr);
771fe6b9
JG		 323struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
324void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 325unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 326bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
327void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
328static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
329 struct radeon_fence *b)
330{
331 if (!a) {
332 return b;
333 }
334
335 if (!b) {
336 return a;
337 }
338
339 BUG_ON(a->ring != b->ring);
340
341 if (a->seq > b->seq) {
342 return a;
343 } else {
344 return b;
345 }
346}
771fe6b9 347
ee60e29f
CK		 348static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
349 struct radeon_fence *b)
350{
351 if (!a) {
352 return false;
353 }
354
355 if (!b) {
356 return true;
357 }
358
359 BUG_ON(a->ring != b->ring);
360
361 return a->seq < b->seq;
362}
363
e024e110
DA		 364/*
365 * Tiling registers
366 */
367struct radeon_surface_reg {
4c788679 368 struct radeon_bo *bo;
e024e110
DA		 369};
370
371#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 372
373/*
4c788679 374 * TTM.
771fe6b9 375 */
4c788679
JG		 376struct radeon_mman {
377 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 378 struct drm_global_reference mem_global_ref;
4c788679 379 struct ttm_bo_device bdev;
0a0c7596
JG		 380 bool mem_global_referenced;
381 bool initialized;
4c788679
JG		 382};
383
721604a1
JG		 384/* bo virtual address in a specific vm */
385struct radeon_bo_va {
e971bd5e 386 /* protected by bo being reserved */
721604a1 387 struct list_head bo_list;
721604a1
JG		 388 uint64_t soffset;
389 uint64_t eoffset;
390 uint32_t flags;
391 bool valid;
e971bd5e
CK		 392 unsigned ref_count;
393
394 /* protected by vm mutex */
395 struct list_head vm_list;
396
397 /* constant after initialization */
398 struct radeon_vm *vm;
399 struct radeon_bo *bo;
721604a1
JG		 400};
401
4c788679
JG		 402struct radeon_bo {
403 /* Protected by gem.mutex */
404 struct list_head list;
405 /* Protected by tbo.reserved */
312ea8da
JG		 406 u32 placements[3];
407 struct ttm_placement placement;
4c788679
JG		 408 struct ttm_buffer_object tbo;
409 struct ttm_bo_kmap_obj kmap;
410 unsigned pin_count;
411 void *kptr;
412 u32 tiling_flags;
413 u32 pitch;
414 int surface_reg;
721604a1
JG		 415 /* list of all virtual address to which this bo
416 * is associated to
417 */
418 struct list_head va;
4c788679
JG		 419 /* Constant after initialization */
420 struct radeon_device *rdev;
441921d5 421 struct drm_gem_object gem_base;
63bc620b 422
409851f4
JG		 423 struct ttm_bo_kmap_obj dma_buf_vmap;
424 pid_t pid;
4c788679 425};
7e4d15d9 426#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 427
4c788679 428struct radeon_bo_list {
147666fb 429 struct ttm_validate_buffer tv;
4c788679 430 struct radeon_bo *bo;
771fe6b9 431 uint64_t gpu_offset;
4474f3a9
CK		 432 bool written;
433 unsigned domain;
434 unsigned alt_domain;
4c788679 435 u32 tiling_flags;
771fe6b9
JG		 436};
437
409851f4
JG		 438int radeon_gem_debugfs_init(struct radeon_device *rdev);
439
b15ba512
JG		 440/* sub-allocation manager, it has to be protected by another lock.
441 * By conception this is an helper for other part of the driver
442 * like the indirect buffer or semaphore, which both have their
443 * locking.
444 *
445 * Principe is simple, we keep a list of sub allocation in offset
446 * order (first entry has offset == 0, last entry has the highest
447 * offset).
448 *
449 * When allocating new object we first check if there is room at
450 * the end total_size - (last_object_offset + last_object_size) >=
451 * alloc_size. If so we allocate new object there.
452 *
453 * When there is not enough room at the end, we start waiting for
454 * each sub object until we reach object_offset+object_size >=
455 * alloc_size, this object then become the sub object we return.
456 *
457 * Alignment can't be bigger than page size.
458 *
459 * Hole are not considered for allocation to keep things simple.
460 * Assumption is that there won't be hole (all object on same
461 * alignment).
462 */
463struct radeon_sa_manager {
bfb38d35 464 wait_queue_head_t wq;
b15ba512 465 struct radeon_bo *bo;
c3b7fe8b
CK		 466 struct list_head *hole;
467 struct list_head flist[RADEON_NUM_RINGS];
468 struct list_head olist;
b15ba512
JG		 469 unsigned size;
470 uint64_t gpu_addr;
471 void *cpu_ptr;
472 uint32_t domain;
6c4f978b 473 uint32_t align;
b15ba512
JG		 474};
475
476struct radeon_sa_bo;
477
478/* sub-allocation buffer */
479struct radeon_sa_bo {
c3b7fe8b
CK		 480 struct list_head olist;
481 struct list_head flist;
b15ba512 482 struct radeon_sa_manager *manager;
e6661a96
CK		 483 unsigned soffset;
484 unsigned eoffset;
557017a0 485 struct radeon_fence *fence;
b15ba512
JG		 486};
487
771fe6b9
JG		 488/*
489 * GEM objects.
490 */
491struct radeon_gem {
4c788679 492 struct mutex mutex;
771fe6b9
JG		 493 struct list_head objects;
494};
495
496int radeon_gem_init(struct radeon_device *rdev);
497void radeon_gem_fini(struct radeon_device *rdev);
498int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 499 int alignment, int initial_domain,
500 bool discardable, bool kernel,
501 struct drm_gem_object **obj);
771fe6b9 502
ff72145b
DA		 503int radeon_mode_dumb_create(struct drm_file *file_priv,
504 struct drm_device *dev,
505 struct drm_mode_create_dumb *args);
506int radeon_mode_dumb_mmap(struct drm_file *filp,
507 struct drm_device *dev,
508 uint32_t handle, uint64_t *offset_p);
509int radeon_mode_dumb_destroy(struct drm_file *file_priv,
510 struct drm_device *dev,
511 uint32_t handle);
771fe6b9 512
c1341e52
JG		 513/*
514 * Semaphores.
515 */
c1341e52
JG		 516/* everything here is constant */
517struct radeon_semaphore {
a8c05940
JG		 518 struct radeon_sa_bo *sa_bo;
519 signed waiters;
c1341e52 520 uint64_t gpu_addr;
c1341e52
JG		 521};
522
c1341e52
JG		 523int radeon_semaphore_create(struct radeon_device *rdev,
524 struct radeon_semaphore **semaphore);
525void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
526 struct radeon_semaphore *semaphore);
527void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
528 struct radeon_semaphore *semaphore);
8f676c4c
CK		 529int radeon_semaphore_sync_rings(struct radeon_device *rdev,
530 struct radeon_semaphore *semaphore,
220907d9 531 int signaler, int waiter);
c1341e52 532void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 533 struct radeon_semaphore **semaphore,
a8c05940 534 struct radeon_fence *fence);
c1341e52 535
771fe6b9
JG		 536/*
537 * GART structures, functions & helpers
538 */
539struct radeon_mc;
540
a77f1718 541#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 542#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 543#define RADEON_GPU_PAGE_SHIFT 12
721604a1 544#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 545
771fe6b9
JG		 546struct radeon_gart {
547 dma_addr_t table_addr;
c9a1be96
JG		 548 struct radeon_bo *robj;
549 void *ptr;
771fe6b9
JG		 550 unsigned num_gpu_pages;
551 unsigned num_cpu_pages;
552 unsigned table_size;
771fe6b9
JG		 553 struct page **pages;
554 dma_addr_t *pages_addr;
555 bool ready;
556};
557
558int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
559void radeon_gart_table_ram_free(struct radeon_device *rdev);
560int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
561void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 562int radeon_gart_table_vram_pin(struct radeon_device *rdev);
563void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 564int radeon_gart_init(struct radeon_device *rdev);
565void radeon_gart_fini(struct radeon_device *rdev);
566void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
567 int pages);
568int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516
KRW		 569 int pages, struct page **pagelist,
570 dma_addr_t *dma_addr);
c9a1be96 571void radeon_gart_restore(struct radeon_device *rdev);
771fe6b9
JG		 572
573
574/*
575 * GPU MC structures, functions & helpers
576 */
577struct radeon_mc {
578 resource_size_t aper_size;
579 resource_size_t aper_base;
580 resource_size_t agp_base;
7a50f01a
DA		 581 /* for some chips with <= 32MB we need to lie
582 * about vram size near mc fb location */
3ce0a23d 583 u64 mc_vram_size;
d594e46a 584 u64 visible_vram_size;
3ce0a23d
JG		 585 u64 gtt_size;
586 u64 gtt_start;
587 u64 gtt_end;
3ce0a23d
JG		 588 u64 vram_start;
589 u64 vram_end;
771fe6b9 590 unsigned vram_width;
3ce0a23d 591 u64 real_vram_size;
771fe6b9
JG		 592 int vram_mtrr;
593 bool vram_is_ddr;
d594e46a 594 bool igp_sideport_enabled;
8d369bb1 595 u64 gtt_base_align;
9ed8b1f9 596 u64 mc_mask;
771fe6b9
JG		 597};
598
06b6476d
AD		 599bool radeon_combios_sideport_present(struct radeon_device *rdev);
600bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 601
602/*
603 * GPU scratch registers structures, functions & helpers
604 */
605struct radeon_scratch {
606 unsigned num_reg;
724c80e1 607 uint32_t reg_base;
771fe6b9
JG		 608 bool free[32];
609 uint32_t reg[32];
610};
611
612int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
613void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
614
75efdee1
AD		 615/*
616 * GPU doorbell structures, functions & helpers
617 */
618struct radeon_doorbell {
619 u32 num_pages;
620 bool free[1024];
621 /* doorbell mmio */
622 resource_size_t base;
623 resource_size_t size;
624 void __iomem *ptr;
625};
626
627int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
628void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771fe6b9
JG		 629
630/*
631 * IRQS.
632 */
6f34be50
AD		 633
634struct radeon_unpin_work {
635 struct work_struct work;
636 struct radeon_device *rdev;
637 int crtc_id;
638 struct radeon_fence *fence;
639 struct drm_pending_vblank_event *event;
640 struct radeon_bo *old_rbo;
641 u64 new_crtc_base;
642};
643
644struct r500_irq_stat_regs {
645 u32 disp_int;
f122c610 646 u32 hdmi0_status;
6f34be50
AD		 647};
648
649struct r600_irq_stat_regs {
650 u32 disp_int;
651 u32 disp_int_cont;
652 u32 disp_int_cont2;
653 u32 d1grph_int;
654 u32 d2grph_int;
f122c610
AD		 655 u32 hdmi0_status;
656 u32 hdmi1_status;
6f34be50
AD		 657};
658
659struct evergreen_irq_stat_regs {
660 u32 disp_int;
661 u32 disp_int_cont;
662 u32 disp_int_cont2;
663 u32 disp_int_cont3;
664 u32 disp_int_cont4;
665 u32 disp_int_cont5;
666 u32 d1grph_int;
667 u32 d2grph_int;
668 u32 d3grph_int;
669 u32 d4grph_int;
670 u32 d5grph_int;
671 u32 d6grph_int;
f122c610
AD		 672 u32 afmt_status1;
673 u32 afmt_status2;
674 u32 afmt_status3;
675 u32 afmt_status4;
676 u32 afmt_status5;
677 u32 afmt_status6;
6f34be50
AD		 678};
679
a59781bb
AD		 680struct cik_irq_stat_regs {
681 u32 disp_int;
682 u32 disp_int_cont;
683 u32 disp_int_cont2;
684 u32 disp_int_cont3;
685 u32 disp_int_cont4;
686 u32 disp_int_cont5;
687 u32 disp_int_cont6;
688};
689
6f34be50
AD		 690union radeon_irq_stat_regs {
691 struct r500_irq_stat_regs r500;
692 struct r600_irq_stat_regs r600;
693 struct evergreen_irq_stat_regs evergreen;
a59781bb 694 struct cik_irq_stat_regs cik;
6f34be50
AD		 695};
696
54bd5206
IH		 697#define RADEON_MAX_HPD_PINS 6
698#define RADEON_MAX_CRTCS 6
f122c610 699#define RADEON_MAX_AFMT_BLOCKS 6
54bd5206 700
771fe6b9 701struct radeon_irq {
fb98257a
CK		 702 bool installed;
703 spinlock_t lock;
736fc37f 704 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 705 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 706 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 707 wait_queue_head_t vblank_queue;
708 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 709 bool afmt[RADEON_MAX_AFMT_BLOCKS];
710 union radeon_irq_stat_regs stat_regs;
4a6369e9 711 bool dpm_thermal;
771fe6b9
JG		 712};
713
714int radeon_irq_kms_init(struct radeon_device *rdev);
715void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b
AD		 716void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
717void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 718void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
719void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 720void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
721void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
722void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
723void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 724
725/*
e32eb50d 726 * CP & rings.
771fe6b9 727 */
7465280c 728
771fe6b9 729struct radeon_ib {
68470ae7
JG		 730 struct radeon_sa_bo *sa_bo;
731 uint32_t length_dw;
732 uint64_t gpu_addr;
733 uint32_t *ptr;
876dc9f3 734 int ring;
68470ae7 735 struct radeon_fence *fence;
4bf3dd92 736 struct radeon_vm *vm;
68470ae7 737 bool is_const_ib;
220907d9 738 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
68470ae7 739 struct radeon_semaphore *semaphore;
771fe6b9
JG		 740};
741
e32eb50d 742struct radeon_ring {
4c788679 743 struct radeon_bo *ring_obj;
771fe6b9
JG		 744 volatile uint32_t *ring;
745 unsigned rptr;
5596a9db
CK		 746 unsigned rptr_offs;
747 unsigned rptr_reg;
45df6803 748 unsigned rptr_save_reg;
89d35807
AD		 749 u64 next_rptr_gpu_addr;
750 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 751 unsigned wptr;
752 unsigned wptr_old;
5596a9db 753 unsigned wptr_reg;
771fe6b9
JG		 754 unsigned ring_size;
755 unsigned ring_free_dw;
756 int count_dw;
069211e5
CK		 757 unsigned long last_activity;
758 unsigned last_rptr;
771fe6b9
JG		 759 uint64_t gpu_addr;
760 uint32_t align_mask;
761 uint32_t ptr_mask;
771fe6b9 762 bool ready;
78c5560a 763 u32 nop;
8b25ed34 764 u32 idx;
5f0839c1
JG		 765 u64 last_semaphore_signal_addr;
766 u64 last_semaphore_wait_addr;
963e81f9
AD		 767 /* for CIK queues */
768 u32 me;
769 u32 pipe;
770 u32 queue;
771 struct radeon_bo *mqd_obj;
772 u32 doorbell_page_num;
773 u32 doorbell_offset;
774 unsigned wptr_offs;
775};
776
777struct radeon_mec {
778 struct radeon_bo *hpd_eop_obj;
779 u64 hpd_eop_gpu_addr;
780 u32 num_pipe;
781 u32 num_mec;
782 u32 num_queue;
771fe6b9
JG		 783};
784
721604a1
JG		 785/*
786 * VM
787 */
ee60e29f 788
fa87e62d 789/* maximum number of VMIDs */
ee60e29f
CK		 790#define RADEON_NUM_VM 16
791
fa87e62d
DC		 792/* defines number of bits in page table versus page directory,
793 * a page is 4KB so we have 12 bits offset, 9 bits in the page
794 * table and the remaining 19 bits are in the page directory */
795#define RADEON_VM_BLOCK_SIZE 9
796
797/* number of entries in page table */
798#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
799
1c01103c
AD		 800/* PTBs (Page Table Blocks) need to be aligned to 32K */
801#define RADEON_VM_PTB_ALIGN_SIZE 32768
802#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
803#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
804
721604a1
JG		 805struct radeon_vm {
806 struct list_head list;
807 struct list_head va;
ee60e29f 808 unsigned id;
90a51a32
CK		 809
810 /* contains the page directory */
811 struct radeon_sa_bo *page_directory;
812 uint64_t pd_gpu_addr;
813
814 /* array of page tables, one for each page directory entry */
815 struct radeon_sa_bo **page_tables;
816
721604a1
JG		 817 struct mutex mutex;
818 /* last fence for cs using this vm */
819 struct radeon_fence *fence;
9b40e5d8
CK		 820 /* last flush or NULL if we still need to flush */
821 struct radeon_fence *last_flush;
721604a1
JG		 822};
823
721604a1 824struct radeon_vm_manager {
36ff39c4 825 struct mutex lock;
721604a1 826 struct list_head lru_vm;
ee60e29f 827 struct radeon_fence *active[RADEON_NUM_VM];
721604a1
JG		 828 struct radeon_sa_manager sa_manager;
829 uint32_t max_pfn;
721604a1
JG		 830 /* number of VMIDs */
831 unsigned nvm;
832 /* vram base address for page table entry */
833 u64 vram_base_offset;
67e915e4
AD		 834 /* is vm enabled? */
835 bool enabled;
721604a1
JG		 836};
837
838/*
839 * file private structure
840 */
841struct radeon_fpriv {
842 struct radeon_vm vm;
843};
844
d8f60cfc
AD		 845/*
846 * R6xx+ IH ring
847 */
848struct r600_ih {
4c788679 849 struct radeon_bo *ring_obj;
d8f60cfc
AD		 850 volatile uint32_t *ring;
851 unsigned rptr;
d8f60cfc
AD		 852 unsigned ring_size;
853 uint64_t gpu_addr;
d8f60cfc 854 uint32_t ptr_mask;
c20dc369 855 atomic_t lock;
d8f60cfc
AD		 856 bool enabled;
857};
858
347e7592 859/*
2948f5e6 860 * RLC stuff
347e7592 861 */
2948f5e6
AD		 862#include "clearstate_defs.h"
863
864struct radeon_rlc {
347e7592
AD		 865 /* for power gating */
866 struct radeon_bo *save_restore_obj;
867 uint64_t save_restore_gpu_addr;
2948f5e6 868 volatile uint32_t *sr_ptr;
1fd11777 869 const u32 *reg_list;
2948f5e6 870 u32 reg_list_size;
347e7592
AD		 871 /* for clear state */
872 struct radeon_bo *clear_state_obj;
873 uint64_t clear_state_gpu_addr;
2948f5e6 874 volatile uint32_t *cs_ptr;
1fd11777 875 const struct cs_section_def *cs_data;
22c775ce
AD		 876 u32 clear_state_size;
877 /* for cp tables */
878 struct radeon_bo *cp_table_obj;
879 uint64_t cp_table_gpu_addr;
880 volatile uint32_t *cp_table_ptr;
881 u32 cp_table_size;
347e7592
AD		 882};
883
69e130a6 884int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 885 struct radeon_ib *ib, struct radeon_vm *vm,
886 unsigned size);
f2e39221 887void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
43f1214a 888void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
4ef72566
CK		 889int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
890 struct radeon_ib *const_ib);
771fe6b9
JG		 891int radeon_ib_pool_init(struct radeon_device *rdev);
892void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 893int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 894/* Ring access between begin & end cannot sleep */
89d35807
AD		 895bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
896 struct radeon_ring *ring);
e32eb50d
CK		 897void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
898int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
899int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
900void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
901void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
d6999bc7 902void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 903void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
904int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
7b9ef16b 905void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
069211e5
CK		 906void radeon_ring_lockup_update(struct radeon_ring *ring);
907bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 908unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
909 uint32_t **data);
910int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
911 unsigned size, uint32_t *data);
e32eb50d 912int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
2e1e6dad 913 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, u32 nop);
e32eb50d 914void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 915
916
4d75658b
AD		 917/* r600 async dma */
918void r600_dma_stop(struct radeon_device *rdev);
919int r600_dma_resume(struct radeon_device *rdev);
920void r600_dma_fini(struct radeon_device *rdev);
921
8c5fd7ef
AD		 922void cayman_dma_stop(struct radeon_device *rdev);
923int cayman_dma_resume(struct radeon_device *rdev);
924void cayman_dma_fini(struct radeon_device *rdev);
925
771fe6b9
JG		 926/*
927 * CS.
928 */
929struct radeon_cs_reloc {
930 struct drm_gem_object *gobj;
4c788679
JG		 931 struct radeon_bo *robj;
932 struct radeon_bo_list lobj;
771fe6b9
JG		 933 uint32_t handle;
934 uint32_t flags;
935};
936
937struct radeon_cs_chunk {
938 uint32_t chunk_id;
939 uint32_t length_dw;
721604a1
JG		 940 int kpage_idx[2];
941 uint32_t *kpage[2];
771fe6b9 942 uint32_t *kdata;
721604a1
JG		 943 void __user *user_ptr;
944 int last_copied_page;
945 int last_page_index;
771fe6b9
JG		 946};
947
948struct radeon_cs_parser {
c8c15ff1 949 struct device *dev;
771fe6b9
JG		 950 struct radeon_device *rdev;
951 struct drm_file *filp;
952 /* chunks */
953 unsigned nchunks;
954 struct radeon_cs_chunk *chunks;
955 uint64_t *chunks_array;
956 /* IB */
957 unsigned idx;
958 /* relocations */
959 unsigned nrelocs;
960 struct radeon_cs_reloc *relocs;
961 struct radeon_cs_reloc **relocs_ptr;
962 struct list_head validated;
cf4ccd01 963 unsigned dma_reloc_idx;
771fe6b9
JG		 964 /* indices of various chunks */
965 int chunk_ib_idx;
966 int chunk_relocs_idx;
721604a1 967 int chunk_flags_idx;
dfcf5f36 968 int chunk_const_ib_idx;
f2e39221
JG		 969 struct radeon_ib ib;
970 struct radeon_ib const_ib;
771fe6b9 971 void *track;
3ce0a23d 972 unsigned family;
e70f224c 973 int parser_error;
721604a1
JG		 974 u32 cs_flags;
975 u32 ring;
976 s32 priority;
ecff665f 977 struct ww_acquire_ctx ticket;
771fe6b9
JG		 978};
979
513bcb46 980extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
ce580fab 981extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
513bcb46 982
771fe6b9
JG		 983struct radeon_cs_packet {
984 unsigned idx;
985 unsigned type;
986 unsigned reg;
987 unsigned opcode;
988 int count;
989 unsigned one_reg_wr;
990};
991
992typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
993 struct radeon_cs_packet *pkt,
994 unsigned idx, unsigned reg);
995typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
996 struct radeon_cs_packet *pkt);
997
998
999/*
1000 * AGP
1001 */
1002int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1003void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1004void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1005void radeon_agp_fini(struct radeon_device *rdev);
1006
1007
1008/*
1009 * Writeback
1010 */
1011struct radeon_wb {
4c788679 1012 struct radeon_bo *wb_obj;
771fe6b9
JG		 1013 volatile uint32_t *wb;
1014 uint64_t gpu_addr;
724c80e1 1015 bool enabled;
d0f8a854 1016 bool use_event;
771fe6b9
JG		 1017};
1018
724c80e1 1019#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1020#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1021#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1022#define RADEON_WB_CP1_RPTR_OFFSET 1280
1023#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1024#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1025#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1026#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1027#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1028#define CIK_WB_CP1_WPTR_OFFSET 3328
1029#define CIK_WB_CP2_WPTR_OFFSET 3584
724c80e1 1030
c93bb85b
JG		 1031/**
1032 * struct radeon_pm - power management datas
1033 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1034 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1035 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1036 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1037 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1038 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1039 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1040 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1041 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1042 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1043 * @needed_bandwidth: current bandwidth needs
1044 *
1045 * It keeps track of various data needed to take powermanagement decision.
25985edc 1046 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1047 * Equation between gpu/memory clock and available bandwidth is hw dependent
1048 * (type of memory, bus size, efficiency, ...)
1049 */
ce8f5370
AD		 1050
1051enum radeon_pm_method {
1052 PM_METHOD_PROFILE,
1053 PM_METHOD_DYNPM,
da321c8a 1054 PM_METHOD_DPM,
ce8f5370
AD		 1055};
1056
1057enum radeon_dynpm_state {
1058 DYNPM_STATE_DISABLED,
1059 DYNPM_STATE_MINIMUM,
1060 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1061 DYNPM_STATE_ACTIVE,
1062 DYNPM_STATE_SUSPENDED,
c913e23a 1063};
ce8f5370
AD		 1064enum radeon_dynpm_action {
1065 DYNPM_ACTION_NONE,
1066 DYNPM_ACTION_MINIMUM,
1067 DYNPM_ACTION_DOWNCLOCK,
1068 DYNPM_ACTION_UPCLOCK,
1069 DYNPM_ACTION_DEFAULT
c913e23a 1070};
56278a8e
AD		 1071
1072enum radeon_voltage_type {
1073 VOLTAGE_NONE = 0,
1074 VOLTAGE_GPIO,
1075 VOLTAGE_VDDC,
1076 VOLTAGE_SW
1077};
1078
0ec0e74f 1079enum radeon_pm_state_type {
da321c8a 1080 /* not used for dpm */
0ec0e74f
AD		 1081 POWER_STATE_TYPE_DEFAULT,
1082 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1083 /* user selectable states */
0ec0e74f
AD		 1084 POWER_STATE_TYPE_BATTERY,
1085 POWER_STATE_TYPE_BALANCED,
1086 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1087 /* internal states */
1088 POWER_STATE_TYPE_INTERNAL_UVD,
1089 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1090 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1091 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1092 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1093 POWER_STATE_TYPE_INTERNAL_BOOT,
1094 POWER_STATE_TYPE_INTERNAL_THERMAL,
1095 POWER_STATE_TYPE_INTERNAL_ACPI,
1096 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1097 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1098};
1099
ce8f5370
AD		 1100enum radeon_pm_profile_type {
1101 PM_PROFILE_DEFAULT,
1102 PM_PROFILE_AUTO,
1103 PM_PROFILE_LOW,
c9e75b21 1104 PM_PROFILE_MID,
ce8f5370
AD		 1105 PM_PROFILE_HIGH,
1106};
1107
1108#define PM_PROFILE_DEFAULT_IDX 0
1109#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1110#define PM_PROFILE_MID_SH_IDX 2
1111#define PM_PROFILE_HIGH_SH_IDX 3
1112#define PM_PROFILE_LOW_MH_IDX 4
1113#define PM_PROFILE_MID_MH_IDX 5
1114#define PM_PROFILE_HIGH_MH_IDX 6
1115#define PM_PROFILE_MAX 7
ce8f5370
AD		 1116
1117struct radeon_pm_profile {
1118 int dpms_off_ps_idx;
1119 int dpms_on_ps_idx;
1120 int dpms_off_cm_idx;
1121 int dpms_on_cm_idx;
516d0e46
AD		 1122};
1123
21a8122a
AD		 1124enum radeon_int_thermal_type {
1125 THERMAL_TYPE_NONE,
da321c8a
AD		 1126 THERMAL_TYPE_EXTERNAL,
1127 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1128 THERMAL_TYPE_RV6XX,
1129 THERMAL_TYPE_RV770,
da321c8a 1130 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1131 THERMAL_TYPE_EVERGREEN,
e33df25f 1132 THERMAL_TYPE_SUMO,
4fddba1f 1133 THERMAL_TYPE_NI,
14607d08 1134 THERMAL_TYPE_SI,
da321c8a 1135 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1136 THERMAL_TYPE_CI,
16fbe00d 1137 THERMAL_TYPE_KV,
21a8122a
AD		 1138};
1139
56278a8e
AD		 1140struct radeon_voltage {
1141 enum radeon_voltage_type type;
1142 /* gpio voltage */
1143 struct radeon_gpio_rec gpio;
1144 u32 delay; /* delay in usec from voltage drop to sclk change */
1145 bool active_high; /* voltage drop is active when bit is high */
1146 /* VDDC voltage */
1147 u8 vddc_id; /* index into vddc voltage table */
1148 u8 vddci_id; /* index into vddci voltage table */
1149 bool vddci_enabled;
1150 /* r6xx+ sw */
2feea49a
AD		 1151 u16 voltage;
1152 /* evergreen+ vddci */
1153 u16 vddci;
56278a8e
AD		 1154};
1155
d7311171
AD		 1156/* clock mode flags */
1157#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1158
56278a8e
AD		 1159struct radeon_pm_clock_info {
1160 /* memory clock */
1161 u32 mclk;
1162 /* engine clock */
1163 u32 sclk;
1164 /* voltage info */
1165 struct radeon_voltage voltage;
d7311171 1166 /* standardized clock flags */
56278a8e
AD		 1167 u32 flags;
1168};
1169
a48b9b4e 1170/* state flags */
d7311171 1171#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1172
56278a8e 1173struct radeon_power_state {
0ec0e74f 1174 enum radeon_pm_state_type type;
8f3f1c9a 1175 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1176 /* number of valid clock modes in this power state */
1177 int num_clock_modes;
56278a8e 1178 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1179 /* standardized state flags */
1180 u32 flags;
79daedc9
AD		 1181 u32 misc; /* vbios specific flags */
1182 u32 misc2; /* vbios specific flags */
1183 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1184};
1185
27459324
RM		 1186/*
1187 * Some modes are overclocked by very low value, accept them
1188 */
1189#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1190
2e9d4c05
AD		 1191enum radeon_dpm_auto_throttle_src {
1192 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1193 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1194};
1195
1196enum radeon_dpm_event_src {
1197 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1198 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1199 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1200 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1201 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1202};
1203
da321c8a
AD		 1204struct radeon_ps {
1205 u32 caps; /* vbios flags */
1206 u32 class; /* vbios flags */
1207 u32 class2; /* vbios flags */
1208 /* UVD clocks */
1209 u32 vclk;
1210 u32 dclk;
c4453e66
AD		 1211 /* VCE clocks */
1212 u32 evclk;
1213 u32 ecclk;
da321c8a
AD		 1214 /* asic priv */
1215 void *ps_priv;
1216};
1217
1218struct radeon_dpm_thermal {
1219 /* thermal interrupt work */
1220 struct work_struct work;
1221 /* low temperature threshold */
1222 int min_temp;
1223 /* high temperature threshold */
1224 int max_temp;
1225 /* was interrupt low to high or high to low */
1226 bool high_to_low;
1227};
1228
d22b7e40
AD		 1229enum radeon_clk_action
1230{
1231 RADEON_SCLK_UP = 1,
1232 RADEON_SCLK_DOWN
1233};
1234
1235struct radeon_blacklist_clocks
1236{
1237 u32 sclk;
1238 u32 mclk;
1239 enum radeon_clk_action action;
1240};
1241
61b7d601
AD		 1242struct radeon_clock_and_voltage_limits {
1243 u32 sclk;
1244 u32 mclk;
1245 u32 vddc;
1246 u32 vddci;
1247};
1248
1249struct radeon_clock_array {
1250 u32 count;
1251 u32 *values;
1252};
1253
1254struct radeon_clock_voltage_dependency_entry {
1255 u32 clk;
1256 u16 v;
1257};
1258
1259struct radeon_clock_voltage_dependency_table {
1260 u32 count;
1261 struct radeon_clock_voltage_dependency_entry *entries;
1262};
1263
ef976ec4
AD		 1264union radeon_cac_leakage_entry {
1265 struct {
1266 u16 vddc;
1267 u32 leakage;
1268 };
1269 struct {
1270 u16 vddc1;
1271 u16 vddc2;
1272 u16 vddc3;
1273 };
61b7d601
AD		 1274};
1275
1276struct radeon_cac_leakage_table {
1277 u32 count;
ef976ec4 1278 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1279};
1280
929ee7a8
AD		 1281struct radeon_phase_shedding_limits_entry {
1282 u16 voltage;
1283 u32 sclk;
1284 u32 mclk;
1285};
1286
1287struct radeon_phase_shedding_limits_table {
1288 u32 count;
1289 struct radeon_phase_shedding_limits_entry *entries;
1290};
1291
84a9d9ee
AD		 1292struct radeon_uvd_clock_voltage_dependency_entry {
1293 u32 vclk;
1294 u32 dclk;
1295 u16 v;
1296};
1297
1298struct radeon_uvd_clock_voltage_dependency_table {
1299 u8 count;
1300 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1301};
1302
d29f013b
AD		 1303struct radeon_vce_clock_voltage_dependency_entry {
1304 u32 ecclk;
1305 u32 evclk;
1306 u16 v;
1307};
1308
1309struct radeon_vce_clock_voltage_dependency_table {
1310 u8 count;
1311 struct radeon_vce_clock_voltage_dependency_entry *entries;
1312};
1313
a5cb318e
AD		 1314struct radeon_ppm_table {
1315 u8 ppm_design;
1316 u16 cpu_core_number;
1317 u32 platform_tdp;
1318 u32 small_ac_platform_tdp;
1319 u32 platform_tdc;
1320 u32 small_ac_platform_tdc;
1321 u32 apu_tdp;
1322 u32 dgpu_tdp;
1323 u32 dgpu_ulv_power;
1324 u32 tj_max;
1325};
1326
58cb7632
AD		 1327struct radeon_cac_tdp_table {
1328 u16 tdp;
1329 u16 configurable_tdp;
1330 u16 tdc;
1331 u16 battery_power_limit;
1332 u16 small_power_limit;
1333 u16 low_cac_leakage;
1334 u16 high_cac_leakage;
1335 u16 maximum_power_delivery_limit;
1336};
1337
61b7d601
AD		 1338struct radeon_dpm_dynamic_state {
1339 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1340 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1341 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1342 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1343 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1344 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1345 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1346 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1347 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1348 struct radeon_clock_array valid_sclk_values;
1349 struct radeon_clock_array valid_mclk_values;
1350 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1351 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1352 u32 mclk_sclk_ratio;
1353 u32 sclk_mclk_delta;
1354 u16 vddc_vddci_delta;
1355 u16 min_vddc_for_pcie_gen2;
1356 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1357 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1358 struct radeon_ppm_table *ppm_table;
58cb7632 1359 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1360};
1361
1362struct radeon_dpm_fan {
1363 u16 t_min;
1364 u16 t_med;
1365 u16 t_high;
1366 u16 pwm_min;
1367 u16 pwm_med;
1368 u16 pwm_high;
1369 u8 t_hyst;
1370 u32 cycle_delay;
1371 u16 t_max;
1372 bool ucode_fan_control;
1373};
1374
32ce4652
AD		 1375enum radeon_pcie_gen {
1376 RADEON_PCIE_GEN1 = 0,
1377 RADEON_PCIE_GEN2 = 1,
1378 RADEON_PCIE_GEN3 = 2,
1379 RADEON_PCIE_GEN_INVALID = 0xffff
1380};
1381
70d01a5e
AD		 1382enum radeon_dpm_forced_level {
1383 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1384 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1385 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1386};
1387
da321c8a
AD		 1388struct radeon_dpm {
1389 struct radeon_ps *ps;
1390 /* number of valid power states */
1391 int num_ps;
1392 /* current power state that is active */
1393 struct radeon_ps *current_ps;
1394 /* requested power state */
1395 struct radeon_ps *requested_ps;
1396 /* boot up power state */
1397 struct radeon_ps *boot_ps;
1398 /* default uvd power state */
1399 struct radeon_ps *uvd_ps;
1400 enum radeon_pm_state_type state;
1401 enum radeon_pm_state_type user_state;
1402 u32 platform_caps;
1403 u32 voltage_response_time;
1404 u32 backbias_response_time;
1405 void *priv;
1406 u32 new_active_crtcs;
1407 int new_active_crtc_count;
1408 u32 current_active_crtcs;
1409 int current_active_crtc_count;
61b7d601
AD		 1410 struct radeon_dpm_dynamic_state dyn_state;
1411 struct radeon_dpm_fan fan;
1412 u32 tdp_limit;
1413 u32 near_tdp_limit;
a9e61410 1414 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1415 u32 sq_ramping_threshold;
1416 u32 cac_leakage;
1417 u16 tdp_od_limit;
1418 u32 tdp_adjustment;
1419 u16 load_line_slope;
1420 bool power_control;
5ca302f7 1421 bool ac_power;
da321c8a
AD		 1422 /* special states active */
1423 bool thermal_active;
8a227555 1424 bool uvd_active;
da321c8a
AD		 1425 /* thermal handling */
1426 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1427 /* forced levels */
1428 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1429 /* track UVD streams */
1430 unsigned sd;
1431 unsigned hd;
da321c8a
AD		 1432};
1433
ce3537d5 1434void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
da321c8a 1435
c93bb85b 1436struct radeon_pm {
c913e23a 1437 struct mutex mutex;
db7fce39
CK		 1438 /* write locked while reprogramming mclk */
1439 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1440 u32 active_crtcs;
1441 int active_crtc_count;
c913e23a 1442 int req_vblank;
839461d3 1443 bool vblank_sync;
c93bb85b
JG		 1444 fixed20_12 max_bandwidth;
1445 fixed20_12 igp_sideport_mclk;
1446 fixed20_12 igp_system_mclk;
1447 fixed20_12 igp_ht_link_clk;
1448 fixed20_12 igp_ht_link_width;
1449 fixed20_12 k8_bandwidth;
1450 fixed20_12 sideport_bandwidth;
1451 fixed20_12 ht_bandwidth;
1452 fixed20_12 core_bandwidth;
1453 fixed20_12 sclk;
f47299c5 1454 fixed20_12 mclk;
c93bb85b 1455 fixed20_12 needed_bandwidth;
0975b162 1456 struct radeon_power_state *power_state;
56278a8e
AD		 1457 /* number of valid power states */
1458 int num_power_states;
a48b9b4e
AD		 1459 int current_power_state_index;
1460 int current_clock_mode_index;
1461 int requested_power_state_index;
1462 int requested_clock_mode_index;
1463 int default_power_state_index;
1464 u32 current_sclk;
1465 u32 current_mclk;
2feea49a
AD		 1466 u16 current_vddc;
1467 u16 current_vddci;
9ace9f7b
AD		 1468 u32 default_sclk;
1469 u32 default_mclk;
2feea49a
AD		 1470 u16 default_vddc;
1471 u16 default_vddci;
29fb52ca 1472 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1473 /* selected pm method */
1474 enum radeon_pm_method pm_method;
1475 /* dynpm power management */
1476 struct delayed_work dynpm_idle_work;
1477 enum radeon_dynpm_state dynpm_state;
1478 enum radeon_dynpm_action dynpm_planned_action;
1479 unsigned long dynpm_action_timeout;
1480 bool dynpm_can_upclock;
1481 bool dynpm_can_downclock;
1482 /* profile-based power management */
1483 enum radeon_pm_profile_type profile;
1484 int profile_index;
1485 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1486 /* internal thermal controller on rv6xx+ */
1487 enum radeon_int_thermal_type int_thermal_type;
1488 struct device *int_hwmon_dev;
da321c8a
AD		 1489 /* dpm */
1490 bool dpm_enabled;
1491 struct radeon_dpm dpm;
c93bb85b
JG		 1492};
1493
a4c9e2ee
AD		 1494int radeon_pm_get_type_index(struct radeon_device *rdev,
1495 enum radeon_pm_state_type ps_type,
1496 int instance);
f2ba57b5
CK		 1497/*
1498 * UVD
1499 */
1500#define RADEON_MAX_UVD_HANDLES 10
1501#define RADEON_UVD_STACK_SIZE (1024*1024)
1502#define RADEON_UVD_HEAP_SIZE (1024*1024)
1503
1504struct radeon_uvd {
1505 struct radeon_bo *vcpu_bo;
1506 void *cpu_addr;
1507 uint64_t gpu_addr;
9cc2e0e9 1508 void *saved_bo;
f2ba57b5
CK		 1509 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1510 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1511 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1512 struct delayed_work idle_work;
f2ba57b5
CK		 1513};
1514
1515int radeon_uvd_init(struct radeon_device *rdev);
1516void radeon_uvd_fini(struct radeon_device *rdev);
1517int radeon_uvd_suspend(struct radeon_device *rdev);
1518int radeon_uvd_resume(struct radeon_device *rdev);
1519int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1520 uint32_t handle, struct radeon_fence **fence);
1521int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1522 uint32_t handle, struct radeon_fence **fence);
1523void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1524void radeon_uvd_free_handles(struct radeon_device *rdev,
1525 struct drm_file *filp);
1526int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1527void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1528int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1529 unsigned vclk, unsigned dclk,
1530 unsigned vco_min, unsigned vco_max,
1531 unsigned fb_factor, unsigned fb_mask,
1532 unsigned pd_min, unsigned pd_max,
1533 unsigned pd_even,
1534 unsigned *optimal_fb_div,
1535 unsigned *optimal_vclk_div,
1536 unsigned *optimal_dclk_div);
1537int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1538 unsigned cg_upll_func_cntl);
771fe6b9 1539
a92553ab 1540struct r600_audio {
a92553ab
RM		 1541 int channels;
1542 int rate;
1543 int bits_per_sample;
1544 u8 status_bits;
1545 u8 category_code;
1546};
1547
771fe6b9
JG		 1548/*
1549 * Benchmarking
1550 */
638dd7db 1551void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1552
1553
ecc0b326
MD		 1554/*
1555 * Testing
1556 */
1557void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1558void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1559 struct radeon_ring *cpA,
1560 struct radeon_ring *cpB);
60a7e396 1561void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326
MD		 1562
1563
771fe6b9
JG		 1564/*
1565 * Debugfs
1566 */
4d8bf9ae
CK		 1567struct radeon_debugfs {
1568 struct drm_info_list *files;
1569 unsigned num_files;
1570};
1571
771fe6b9
JG		 1572int radeon_debugfs_add_files(struct radeon_device *rdev,
1573 struct drm_info_list *files,
1574 unsigned nfiles);
1575int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1576
76a0df85
CK		 1577/*
1578 * ASIC ring specific functions.
1579 */
1580struct radeon_asic_ring {
1581 /* ring read/write ptr handling */
1582 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1583 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1584 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1585
1586 /* validating and patching of IBs */
1587 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1588 int (*cs_parse)(struct radeon_cs_parser *p);
1589
1590 /* command emmit functions */
1591 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1592 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1593 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1594 struct radeon_semaphore *semaphore, bool emit_wait);
1595 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1596
1597 /* testing functions */
1598 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1599 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1600 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1601
1602 /* deprecated */
1603 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1604};
771fe6b9
JG		 1605
1606/*
1607 * ASIC specific functions.
1608 */
1609struct radeon_asic {
068a117c 1610 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1611 void (*fini)(struct radeon_device *rdev);
1612 int (*resume)(struct radeon_device *rdev);
1613 int (*suspend)(struct radeon_device *rdev);
28d52043 1614 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1615 int (*asic_reset)(struct radeon_device *rdev);
54e88e06
AD		 1616 /* ioctl hw specific callback. Some hw might want to perform special
1617 * operation on specific ioctl. For instance on wait idle some hw
1618 * might want to perform and HDP flush through MMIO as it seems that
1619 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1620 * through ring.
1621 */
1622 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1623 /* check if 3D engine is idle */
1624 bool (*gui_idle)(struct radeon_device *rdev);
1625 /* wait for mc_idle */
1626 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1627 /* get the reference clock */
1628 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1629 /* get the gpu clock counter */
1630 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1631 /* gart */
c5b3b850
AD		 1632 struct {
1633 void (*tlb_flush)(struct radeon_device *rdev);
1634 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1635 } gart;
05b07147
CK		 1636 struct {
1637 int (*init)(struct radeon_device *rdev);
1638 void (*fini)(struct radeon_device *rdev);
2a6f1abb
CK		 1639
1640 u32 pt_ring_index;
43f1214a
AD		 1641 void (*set_page)(struct radeon_device *rdev,
1642 struct radeon_ib *ib,
1643 uint64_t pe,
dce34bfd
CK		 1644 uint64_t addr, unsigned count,
1645 uint32_t incr, uint32_t flags);
05b07147 1646 } vm;
54e88e06 1647 /* ring specific callbacks */
76a0df85 1648 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1649 /* irqs */
b35ea4ab
AD		 1650 struct {
1651 int (*set)(struct radeon_device *rdev);
1652 int (*process)(struct radeon_device *rdev);
1653 } irq;
54e88e06 1654 /* displays */
c79a49ca
AD		 1655 struct {
1656 /* display watermarks */
1657 void (*bandwidth_update)(struct radeon_device *rdev);
1658 /* get frame count */
1659 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1660 /* wait for vblank */
1661 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1662 /* set backlight level */
1663 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1664 /* get backlight level */
1665 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1666 /* audio callbacks */
1667 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1668 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1669 } display;
54e88e06 1670 /* copy functions for bo handling */
27cd7769
AD		 1671 struct {
1672 int (*blit)(struct radeon_device *rdev,
1673 uint64_t src_offset,
1674 uint64_t dst_offset,
1675 unsigned num_gpu_pages,
876dc9f3 1676 struct radeon_fence **fence);
27cd7769
AD		 1677 u32 blit_ring_index;
1678 int (*dma)(struct radeon_device *rdev,
1679 uint64_t src_offset,
1680 uint64_t dst_offset,
1681 unsigned num_gpu_pages,
876dc9f3 1682 struct radeon_fence **fence);
27cd7769
AD		 1683 u32 dma_ring_index;
1684 /* method used for bo copy */
1685 int (*copy)(struct radeon_device *rdev,
1686 uint64_t src_offset,
1687 uint64_t dst_offset,
1688 unsigned num_gpu_pages,
876dc9f3 1689 struct radeon_fence **fence);
27cd7769
AD		 1690 /* ring used for bo copies */
1691 u32 copy_ring_index;
1692 } copy;
54e88e06 1693 /* surfaces */
9e6f3d02
AD		 1694 struct {
1695 int (*set_reg)(struct radeon_device *rdev, int reg,
1696 uint32_t tiling_flags, uint32_t pitch,
1697 uint32_t offset, uint32_t obj_size);
1698 void (*clear_reg)(struct radeon_device *rdev, int reg);
1699 } surface;
54e88e06 1700 /* hotplug detect */
901ea57d
AD		 1701 struct {
1702 void (*init)(struct radeon_device *rdev);
1703 void (*fini)(struct radeon_device *rdev);
1704 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1705 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1706 } hpd;
da321c8a 1707 /* static power management */
a02fa397
AD		 1708 struct {
1709 void (*misc)(struct radeon_device *rdev);
1710 void (*prepare)(struct radeon_device *rdev);
1711 void (*finish)(struct radeon_device *rdev);
1712 void (*init_profile)(struct radeon_device *rdev);
1713 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1714 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1715 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1716 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1717 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1718 int (*get_pcie_lanes)(struct radeon_device *rdev);
1719 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1720 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1721 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
6bd1c385 1722 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1723 } pm;
da321c8a
AD		 1724 /* dynamic power management */
1725 struct {
1726 int (*init)(struct radeon_device *rdev);
1727 void (*setup_asic)(struct radeon_device *rdev);
1728 int (*enable)(struct radeon_device *rdev);
1729 void (*disable)(struct radeon_device *rdev);
84dd1928 1730 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1731 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1732 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1733 void (*display_configuration_changed)(struct radeon_device *rdev);
1734 void (*fini)(struct radeon_device *rdev);
1735 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1736 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1737 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1738 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1739 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1740 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1741 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
da321c8a 1742 } dpm;
6f34be50 1743 /* pageflipping */
0f9e006c
AD		 1744 struct {
1745 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1746 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1747 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1748 } pflip;
771fe6b9
JG		 1749};
1750
21f9a437
JG		 1751/*
1752 * Asic structures
1753 */
551ebd83 1754struct r100_asic {
225758d8
JG		 1755 const unsigned *reg_safe_bm;
1756 unsigned reg_safe_bm_size;
1757 u32 hdp_cntl;
551ebd83
DA		 1758};
1759
21f9a437 1760struct r300_asic {
225758d8
JG		 1761 const unsigned *reg_safe_bm;
1762 unsigned reg_safe_bm_size;
1763 u32 resync_scratch;
1764 u32 hdp_cntl;
21f9a437
JG		 1765};
1766
1767struct r600_asic {
225758d8
JG		 1768 unsigned max_pipes;
1769 unsigned max_tile_pipes;
1770 unsigned max_simds;
1771 unsigned max_backends;
1772 unsigned max_gprs;
1773 unsigned max_threads;
1774 unsigned max_stack_entries;
1775 unsigned max_hw_contexts;
1776 unsigned max_gs_threads;
1777 unsigned sx_max_export_size;
1778 unsigned sx_max_export_pos_size;
1779 unsigned sx_max_export_smx_size;
1780 unsigned sq_num_cf_insts;
1781 unsigned tiling_nbanks;
1782 unsigned tiling_npipes;
1783 unsigned tiling_group_size;
e7aeeba6 1784 unsigned tile_config;
e55b9422 1785 unsigned backend_map;
21f9a437
JG		 1786};
1787
1788struct rv770_asic {
225758d8
JG		 1789 unsigned max_pipes;
1790 unsigned max_tile_pipes;
1791 unsigned max_simds;
1792 unsigned max_backends;
1793 unsigned max_gprs;
1794 unsigned max_threads;
1795 unsigned max_stack_entries;
1796 unsigned max_hw_contexts;
1797 unsigned max_gs_threads;
1798 unsigned sx_max_export_size;
1799 unsigned sx_max_export_pos_size;
1800 unsigned sx_max_export_smx_size;
1801 unsigned sq_num_cf_insts;
1802 unsigned sx_num_of_sets;
1803 unsigned sc_prim_fifo_size;
1804 unsigned sc_hiz_tile_fifo_size;
1805 unsigned sc_earlyz_tile_fifo_fize;
1806 unsigned tiling_nbanks;
1807 unsigned tiling_npipes;
1808 unsigned tiling_group_size;
e7aeeba6 1809 unsigned tile_config;
e55b9422 1810 unsigned backend_map;
21f9a437
JG		 1811};
1812
32fcdbf4
AD		 1813struct evergreen_asic {
1814 unsigned num_ses;
1815 unsigned max_pipes;
1816 unsigned max_tile_pipes;
1817 unsigned max_simds;
1818 unsigned max_backends;
1819 unsigned max_gprs;
1820 unsigned max_threads;
1821 unsigned max_stack_entries;
1822 unsigned max_hw_contexts;
1823 unsigned max_gs_threads;
1824 unsigned sx_max_export_size;
1825 unsigned sx_max_export_pos_size;
1826 unsigned sx_max_export_smx_size;
1827 unsigned sq_num_cf_insts;
1828 unsigned sx_num_of_sets;
1829 unsigned sc_prim_fifo_size;
1830 unsigned sc_hiz_tile_fifo_size;
1831 unsigned sc_earlyz_tile_fifo_size;
1832 unsigned tiling_nbanks;
1833 unsigned tiling_npipes;
1834 unsigned tiling_group_size;
e7aeeba6 1835 unsigned tile_config;
e55b9422 1836 unsigned backend_map;
32fcdbf4
AD		 1837};
1838
fecf1d07
AD		 1839struct cayman_asic {
1840 unsigned max_shader_engines;
1841 unsigned max_pipes_per_simd;
1842 unsigned max_tile_pipes;
1843 unsigned max_simds_per_se;
1844 unsigned max_backends_per_se;
1845 unsigned max_texture_channel_caches;
1846 unsigned max_gprs;
1847 unsigned max_threads;
1848 unsigned max_gs_threads;
1849 unsigned max_stack_entries;
1850 unsigned sx_num_of_sets;
1851 unsigned sx_max_export_size;
1852 unsigned sx_max_export_pos_size;
1853 unsigned sx_max_export_smx_size;
1854 unsigned max_hw_contexts;
1855 unsigned sq_num_cf_insts;
1856 unsigned sc_prim_fifo_size;
1857 unsigned sc_hiz_tile_fifo_size;
1858 unsigned sc_earlyz_tile_fifo_size;
1859
1860 unsigned num_shader_engines;
1861 unsigned num_shader_pipes_per_simd;
1862 unsigned num_tile_pipes;
1863 unsigned num_simds_per_se;
1864 unsigned num_backends_per_se;
1865 unsigned backend_disable_mask_per_asic;
1866 unsigned backend_map;
1867 unsigned num_texture_channel_caches;
1868 unsigned mem_max_burst_length_bytes;
1869 unsigned mem_row_size_in_kb;
1870 unsigned shader_engine_tile_size;
1871 unsigned num_gpus;
1872 unsigned multi_gpu_tile_size;
1873
1874 unsigned tile_config;
fecf1d07
AD		 1875};
1876
0a96d72b
AD		 1877struct si_asic {
1878 unsigned max_shader_engines;
0a96d72b 1879 unsigned max_tile_pipes;
1a8ca750
AD		 1880 unsigned max_cu_per_sh;
1881 unsigned max_sh_per_se;
0a96d72b
AD		 1882 unsigned max_backends_per_se;
1883 unsigned max_texture_channel_caches;
1884 unsigned max_gprs;
1885 unsigned max_gs_threads;
1886 unsigned max_hw_contexts;
1887 unsigned sc_prim_fifo_size_frontend;
1888 unsigned sc_prim_fifo_size_backend;
1889 unsigned sc_hiz_tile_fifo_size;
1890 unsigned sc_earlyz_tile_fifo_size;
1891
0a96d72b
AD		 1892 unsigned num_tile_pipes;
1893 unsigned num_backends_per_se;
1894 unsigned backend_disable_mask_per_asic;
1895 unsigned backend_map;
1896 unsigned num_texture_channel_caches;
1897 unsigned mem_max_burst_length_bytes;
1898 unsigned mem_row_size_in_kb;
1899 unsigned shader_engine_tile_size;
1900 unsigned num_gpus;
1901 unsigned multi_gpu_tile_size;
1902
1903 unsigned tile_config;
64d7b8be 1904 uint32_t tile_mode_array[32];
0a96d72b
AD		 1905};
1906
8cc1a532
AD		 1907struct cik_asic {
1908 unsigned max_shader_engines;
1909 unsigned max_tile_pipes;
1910 unsigned max_cu_per_sh;
1911 unsigned max_sh_per_se;
1912 unsigned max_backends_per_se;
1913 unsigned max_texture_channel_caches;
1914 unsigned max_gprs;
1915 unsigned max_gs_threads;
1916 unsigned max_hw_contexts;
1917 unsigned sc_prim_fifo_size_frontend;
1918 unsigned sc_prim_fifo_size_backend;
1919 unsigned sc_hiz_tile_fifo_size;
1920 unsigned sc_earlyz_tile_fifo_size;
1921
1922 unsigned num_tile_pipes;
1923 unsigned num_backends_per_se;
1924 unsigned backend_disable_mask_per_asic;
1925 unsigned backend_map;
1926 unsigned num_texture_channel_caches;
1927 unsigned mem_max_burst_length_bytes;
1928 unsigned mem_row_size_in_kb;
1929 unsigned shader_engine_tile_size;
1930 unsigned num_gpus;
1931 unsigned multi_gpu_tile_size;
1932
1933 unsigned tile_config;
39aee490 1934 uint32_t tile_mode_array[32];
8cc1a532
AD		 1935};
1936
068a117c
JG		 1937union radeon_asic_config {
1938 struct r300_asic r300;
551ebd83 1939 struct r100_asic r100;
3ce0a23d
JG		 1940 struct r600_asic r600;
1941 struct rv770_asic rv770;
32fcdbf4 1942 struct evergreen_asic evergreen;
fecf1d07 1943 struct cayman_asic cayman;
0a96d72b 1944 struct si_asic si;
8cc1a532 1945 struct cik_asic cik;
068a117c
JG		 1946};
1947
0a10c851
DV		 1948/*
1949 * asic initizalization from radeon_asic.c
1950 */
1951void radeon_agp_disable(struct radeon_device *rdev);
1952int radeon_asic_init(struct radeon_device *rdev);
1953
771fe6b9
JG		 1954
1955/*
1956 * IOCTL.
1957 */
1958int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1959 struct drm_file *filp);
1960int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1961 struct drm_file *filp);
1962int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1963 struct drm_file *file_priv);
1964int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1965 struct drm_file *file_priv);
1966int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1967 struct drm_file *file_priv);
1968int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1969 struct drm_file *file_priv);
1970int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1971 struct drm_file *filp);
1972int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1973 struct drm_file *filp);
1974int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1975 struct drm_file *filp);
1976int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1977 struct drm_file *filp);
721604a1
JG		 1978int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
1979 struct drm_file *filp);
771fe6b9 1980int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 1981int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1982 struct drm_file *filp);
1983int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1984 struct drm_file *filp);
771fe6b9 1985
16cdf04d
AD		 1986/* VRAM scratch page for HDP bug, default vram page */
1987struct r600_vram_scratch {
87cbf8f2
AD		 1988 struct radeon_bo *robj;
1989 volatile uint32_t *ptr;
16cdf04d 1990 u64 gpu_addr;
87cbf8f2 1991};
771fe6b9 1992
fd64ca8a
LT		 1993/*
1994 * ACPI
1995 */
1996struct radeon_atif_notification_cfg {
1997 bool enabled;
1998 int command_code;
1999};
2000
2001struct radeon_atif_notifications {
2002 bool display_switch;
2003 bool expansion_mode_change;
2004 bool thermal_state;
2005 bool forced_power_state;
2006 bool system_power_state;
2007 bool display_conf_change;
2008 bool px_gfx_switch;
2009 bool brightness_change;
2010 bool dgpu_display_event;
2011};
2012
2013struct radeon_atif_functions {
2014 bool system_params;
2015 bool sbios_requests;
2016 bool select_active_disp;
2017 bool lid_state;
2018 bool get_tv_standard;
2019 bool set_tv_standard;
2020 bool get_panel_expansion_mode;
2021 bool set_panel_expansion_mode;
2022 bool temperature_change;
2023 bool graphics_device_types;
2024};
2025
2026struct radeon_atif {
2027 struct radeon_atif_notifications notifications;
2028 struct radeon_atif_functions functions;
2029 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2030 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2031};
7a1619b9 2032
e3a15920
AD		 2033struct radeon_atcs_functions {
2034 bool get_ext_state;
2035 bool pcie_perf_req;
2036 bool pcie_dev_rdy;
2037 bool pcie_bus_width;
2038};
2039
2040struct radeon_atcs {
2041 struct radeon_atcs_functions functions;
2042};
2043
771fe6b9
JG		 2044/*
2045 * Core structure, functions and helpers.
2046 */
2047typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2048typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2049
2050struct radeon_device {
9f022ddf 2051 struct device *dev;
771fe6b9
JG		 2052 struct drm_device *ddev;
2053 struct pci_dev *pdev;
dee53e7f 2054 struct rw_semaphore exclusive_lock;
771fe6b9 2055 /* ASIC */
068a117c 2056 union radeon_asic_config config;
771fe6b9
JG		 2057 enum radeon_family family;
2058 unsigned long flags;
2059 int usec_timeout;
2060 enum radeon_pll_errata pll_errata;
2061 int num_gb_pipes;
f779b3e5 2062 int num_z_pipes;
771fe6b9
JG		 2063 int disp_priority;
2064 /* BIOS */
2065 uint8_t *bios;
2066 bool is_atom_bios;
2067 uint16_t bios_header_start;
4c788679 2068 struct radeon_bo *stollen_vga_memory;
771fe6b9 2069 /* Register mmio */
4c9bc75c
DA		 2070 resource_size_t rmmio_base;
2071 resource_size_t rmmio_size;
2c385151
DV		 2072 /* protects concurrent MM_INDEX/DATA based register access */
2073 spinlock_t mmio_idx_lock;
a0533fbf 2074 void __iomem *rmmio;
771fe6b9
JG		 2075 radeon_rreg_t mc_rreg;
2076 radeon_wreg_t mc_wreg;
2077 radeon_rreg_t pll_rreg;
2078 radeon_wreg_t pll_wreg;
de1b2898 2079 uint32_t pcie_reg_mask;
771fe6b9
JG		 2080 radeon_rreg_t pciep_rreg;
2081 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2082 /* io port */
2083 void __iomem *rio_mem;
2084 resource_size_t rio_mem_size;
771fe6b9
JG		 2085 struct radeon_clock clock;
2086 struct radeon_mc mc;
2087 struct radeon_gart gart;
2088 struct radeon_mode_info mode_info;
2089 struct radeon_scratch scratch;
75efdee1 2090 struct radeon_doorbell doorbell;
771fe6b9 2091 struct radeon_mman mman;
7465280c 2092 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2093 wait_queue_head_t fence_queue;
d6999bc7 2094 struct mutex ring_lock;
e32eb50d 2095 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2096 bool ib_pool_ready;
2097 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2098 struct radeon_irq irq;
2099 struct radeon_asic *asic;
2100 struct radeon_gem gem;
c93bb85b 2101 struct radeon_pm pm;
f2ba57b5 2102 struct radeon_uvd uvd;
f657c2a7 2103 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2104 struct radeon_wb wb;
3ce0a23d 2105 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2106 bool shutdown;
2107 bool suspend;
ad49f501 2108 bool need_dma32;
733289c2 2109 bool accel_working;
a0a53aa8 2110 bool fastfb_working; /* IGP feature*/
e024e110 2111 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2112 const struct firmware *me_fw; /* all family ME firmware */
2113 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2114 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2115 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2116 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2117 const struct firmware *mec_fw; /* CIK MEC firmware */
21a93e13 2118 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2119 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2120 const struct firmware *uvd_fw; /* UVD firmware */
16cdf04d 2121 struct r600_vram_scratch vram_scratch;
3e5cb98d 2122 int msi_enabled; /* msi enabled */
d8f60cfc 2123 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2124 struct radeon_rlc rlc;
963e81f9 2125 struct radeon_mec mec;
d4877cf2 2126 struct work_struct hotplug_work;
f122c610 2127 struct work_struct audio_work;
8f61b34c 2128 struct work_struct reset_work;
18917b60 2129 int num_crtc; /* number of crtcs */
40bacf16 2130 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
3299de95 2131 bool audio_enabled;
948bee3f 2132 bool has_uvd;
3299de95 2133 struct r600_audio audio_status; /* audio stuff */
ce8f5370 2134 struct notifier_block acpi_nb;
9eba4a93 2135 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2136 struct drm_file *hyperz_filp;
9eba4a93 2137 struct drm_file *cmask_filp;
f376b94f
AD		 2138 /* i2c buses */
2139 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2140 /* debugfs */
2141 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2142 unsigned debugfs_count;
721604a1
JG		 2143 /* virtual memory */
2144 struct radeon_vm_manager vm_manager;
6759a0a7 2145 struct mutex gpu_clock_mutex;
fd64ca8a
LT		 2146 /* ACPI interface */
2147 struct radeon_atif atif;
e3a15920 2148 struct radeon_atcs atcs;
f61d5b46
AD		 2149 /* srbm instance registers */
2150 struct mutex srbm_mutex;
771fe6b9
JG		 2151};
2152
2153int radeon_device_init(struct radeon_device *rdev,
2154 struct drm_device *ddev,
2155 struct pci_dev *pdev,
2156 uint32_t flags);
2157void radeon_device_fini(struct radeon_device *rdev);
2158int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2159
2ef9bdfe
DV		 2160uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2161 bool always_indirect);
2162void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2163 bool always_indirect);
6fcbef7a
AK		 2164u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2165void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2166
75efdee1
AD		 2167u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset);
2168void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
2169
4c788679
JG		 2170/*
2171 * Cast helper
2172 */
2173#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 2174
2175/*
2176 * Registers read & write functions.
2177 */
a0533fbf
BH		 2178#define RREG8(reg) readb((rdev->rmmio) + (reg))
2179#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2180#define RREG16(reg) readw((rdev->rmmio) + (reg))
2181#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2182#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2183#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2184#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2185#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2186#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2187#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2188#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2189#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2190#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2191#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2192#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2193#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2194#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2195#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2196#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2197#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2198#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2199#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2200#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2201#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2202#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2203#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2204#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2205#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2206#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2207#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2208#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2209#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2210#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2211#define WREG32_P(reg, val, mask) \
2212 do { \
2213 uint32_t tmp_ = RREG32(reg); \
2214 tmp_ &= (mask); \
2215 tmp_ |= ((val) & ~(mask)); \
2216 WREG32(reg, tmp_); \
2217 } while (0)
d5169fc4 2218#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2219#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2220#define WREG32_PLL_P(reg, val, mask) \
2221 do { \
2222 uint32_t tmp_ = RREG32_PLL(reg); \
2223 tmp_ &= (mask); \
2224 tmp_ |= ((val) & ~(mask)); \
2225 WREG32_PLL(reg, tmp_); \
2226 } while (0)
2ef9bdfe 2227#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2228#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2229#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2230
75efdee1
AD		 2231#define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset))
2232#define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v))
2233
de1b2898
DA		 2234/*
2235 * Indirect registers accessor
2236 */
2237static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2238{
2239 uint32_t r;
2240
2241 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2242 r = RREG32(RADEON_PCIE_DATA);
2243 return r;
2244}
2245
2246static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2247{
2248 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2249 WREG32(RADEON_PCIE_DATA, (v));
2250}
2251
1d5d0c34
AD		 2252static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2253{
2254 u32 r;
2255
2256 WREG32(TN_SMC_IND_INDEX_0, (reg));
2257 r = RREG32(TN_SMC_IND_DATA_0);
2258 return r;
2259}
2260
2261static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2262{
2263 WREG32(TN_SMC_IND_INDEX_0, (reg));
2264 WREG32(TN_SMC_IND_DATA_0, (v));
2265}
2266
ff82bbc4
AD		 2267static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2268{
2269 u32 r;
2270
2271 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2272 r = RREG32(R600_RCU_DATA);
2273 return r;
2274}
2275
2276static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2277{
2278 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2279 WREG32(R600_RCU_DATA, (v));
2280}
2281
46f9564a
AD		 2282static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2283{
2284 u32 r;
2285
2286 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2287 r = RREG32(EVERGREEN_CG_IND_DATA);
2288 return r;
2289}
2290
2291static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2292{
2293 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2294 WREG32(EVERGREEN_CG_IND_DATA, (v));
2295}
2296
792edd69
AD		 2297static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2298{
2299 u32 r;
2300
2301 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2302 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2303 return r;
2304}
2305
2306static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2307{
2308 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2309 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2310}
2311
2312static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2313{
2314 u32 r;
2315
2316 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2317 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2318 return r;
2319}
2320
2321static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2322{
2323 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2324 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2325}
2326
93656cdd
AD		 2327static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2328{
2329 u32 r;
2330
2331 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2332 r = RREG32(R600_UVD_CTX_DATA);
2333 return r;
2334}
2335
2336static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2337{
2338 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2339 WREG32(R600_UVD_CTX_DATA, (v));
2340}
2341
1d58234d
AD		 2342
2343static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2344{
2345 u32 r;
2346
2347 WREG32(CIK_DIDT_IND_INDEX, (reg));
2348 r = RREG32(CIK_DIDT_IND_DATA);
2349 return r;
2350}
2351
2352static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2353{
2354 WREG32(CIK_DIDT_IND_INDEX, (reg));
2355 WREG32(CIK_DIDT_IND_DATA, (v));
2356}
2357
771fe6b9
JG		 2358void r100_pll_errata_after_index(struct radeon_device *rdev);
2359
2360
2361/*
2362 * ASICs helpers.
2363 */
b995e433
DA		 2364#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2365 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2366#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2367 (rdev->family == CHIP_RV200) || \
2368 (rdev->family == CHIP_RS100) || \
2369 (rdev->family == CHIP_RS200) || \
2370 (rdev->family == CHIP_RV250) || \
2371 (rdev->family == CHIP_RV280) || \
2372 (rdev->family == CHIP_RS300))
2373#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2374 (rdev->family == CHIP_RV350) || \
2375 (rdev->family == CHIP_R350) || \
2376 (rdev->family == CHIP_RV380) || \
2377 (rdev->family == CHIP_R420) || \
2378 (rdev->family == CHIP_R423) || \
2379 (rdev->family == CHIP_RV410) || \
2380 (rdev->family == CHIP_RS400) || \
2381 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2382#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2383 (rdev->ddev->pdev->device == 0x9443) || \
2384 (rdev->ddev->pdev->device == 0x944B) || \
2385 (rdev->ddev->pdev->device == 0x9506) || \
2386 (rdev->ddev->pdev->device == 0x9509) || \
2387 (rdev->ddev->pdev->device == 0x950F) || \
2388 (rdev->ddev->pdev->device == 0x689C) || \
2389 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2390#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2391#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2392 (rdev->family == CHIP_RS690) || \
2393 (rdev->family == CHIP_RS740) || \
2394 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2395#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2396#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2397#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2398#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2399 (rdev->flags & RADEON_IS_IGP))
1fe18305 2400#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2401#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2402#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2403 (rdev->flags & RADEON_IS_IGP))
624d3524 2404#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2405#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2406#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
771fe6b9 2407
dc50ba7f
AD		 2408#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2409 (rdev->ddev->pdev->device == 0x6850) || \
2410 (rdev->ddev->pdev->device == 0x6858) || \
2411 (rdev->ddev->pdev->device == 0x6859) || \
2412 (rdev->ddev->pdev->device == 0x6840) || \
2413 (rdev->ddev->pdev->device == 0x6841) || \
2414 (rdev->ddev->pdev->device == 0x6842) || \
2415 (rdev->ddev->pdev->device == 0x6843))
2416
771fe6b9
JG		 2417/*
2418 * BIOS helpers.
2419 */
2420#define RBIOS8(i) (rdev->bios[i])
2421#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2422#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2423
2424int radeon_combios_init(struct radeon_device *rdev);
2425void radeon_combios_fini(struct radeon_device *rdev);
2426int radeon_atombios_init(struct radeon_device *rdev);
2427void radeon_atombios_fini(struct radeon_device *rdev);
2428
2429
2430/*
2431 * RING helpers.
2432 */
ce580fab 2433#if DRM_DEBUG_CODE == 0
e32eb50d 2434static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2435{
e32eb50d
CK		 2436 ring->ring[ring->wptr++] = v;
2437 ring->wptr &= ring->ptr_mask;
2438 ring->count_dw--;
2439 ring->ring_free_dw--;
771fe6b9 2440}
ce580fab
AK		 2441#else
2442/* With debugging this is just too big to inline */
e32eb50d 2443void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
ce580fab 2444#endif
771fe6b9
JG		 2445
2446/*
2447 * ASICs macro.
2448 */
068a117c 2449#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2450#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2451#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2452#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2453#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2454#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2455#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850
AD		 2456#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2457#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
05b07147
CK		 2458#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2459#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
43f1214a 2460#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
76a0df85
CK		 2461#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2462#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2463#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2464#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2465#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2466#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2467#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2468#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2469#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2470#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2471#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2472#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2473#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2474#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2475#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2476#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2477#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2478#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2479#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
27cd7769
AD		 2480#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2481#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2482#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2483#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2484#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2485#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2486#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2487#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2488#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2489#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2490#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2491#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2492#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2493#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
6bd1c385 2494#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2495#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2496#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2497#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2498#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2499#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2500#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2501#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2502#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2503#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2504#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2505#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2506#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2507#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8
AD		 2508#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2509#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2510#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2511#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2512#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2513#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2514#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2515#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2516#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2517#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2518#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2519#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2520#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2521#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2522#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2523#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2524#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2525#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2526#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2527#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2528#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2529#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2530#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
771fe6b9 2531
6cf8a3f5 2532/* Common functions */
700a0cc0 2533/* AGP */
90aca4d2 2534extern int radeon_gpu_reset(struct radeon_device *rdev);
410a3418 2535extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2536extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2537extern int radeon_modeset_init(struct radeon_device *rdev);
2538extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2539extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2540extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2541extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2542extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2543extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2544extern void radeon_wb_fini(struct radeon_device *rdev);
2545extern int radeon_wb_init(struct radeon_device *rdev);
2546extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2547extern void radeon_surface_init(struct radeon_device *rdev);
2548extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2549extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2550extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2551extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2552extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 2553extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2554extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
6a9ee8af
DA		 2555extern int radeon_resume_kms(struct drm_device *dev);
2556extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
53595338 2557extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2558extern void radeon_program_register_sequence(struct radeon_device *rdev,
2559 const u32 *registers,
2560 const u32 array_size);
6cf8a3f5 2561
721604a1
JG		 2562/*
2563 * vm
2564 */
2565int radeon_vm_manager_init(struct radeon_device *rdev);
2566void radeon_vm_manager_fini(struct radeon_device *rdev);
d72d43cf 2567void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2568void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
ddf03f5c 2569int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
13e55c38 2570void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
ee60e29f
CK		 2571struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2572 struct radeon_vm *vm, int ring);
2573void radeon_vm_fence(struct radeon_device *rdev,
2574 struct radeon_vm *vm,
2575 struct radeon_fence *fence);
dce34bfd 2576uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
721604a1
JG		 2577int radeon_vm_bo_update_pte(struct radeon_device *rdev,
2578 struct radeon_vm *vm,
2579 struct radeon_bo *bo,
2580 struct ttm_mem_reg *mem);
2581void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2582 struct radeon_bo *bo);
421ca7ab
CK		 2583struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2584 struct radeon_bo *bo);
e971bd5e
CK		 2585struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2586 struct radeon_vm *vm,
2587 struct radeon_bo *bo);
2588int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2589 struct radeon_bo_va *bo_va,
2590 uint64_t offset,
2591 uint32_t flags);
721604a1 2592int radeon_vm_bo_rmv(struct radeon_device *rdev,
e971bd5e 2593 struct radeon_bo_va *bo_va);
721604a1 2594
f122c610
AD		 2595/* audio */
2596void r600_audio_update_hdmi(struct work_struct *work);
721604a1 2597
16cdf04d
AD		 2598/*
2599 * R600 vram scratch functions
2600 */
2601int r600_vram_scratch_init(struct radeon_device *rdev);
2602void r600_vram_scratch_fini(struct radeon_device *rdev);
2603
285484e2
JG		 2604/*
2605 * r600 cs checking helper
2606 */
2607unsigned r600_mip_minify(unsigned size, unsigned level);
2608bool r600_fmt_is_valid_color(u32 format);
2609bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2610int r600_fmt_get_blocksize(u32 format);
2611int r600_fmt_get_nblocksx(u32 format, u32 w);
2612int r600_fmt_get_nblocksy(u32 format, u32 h);
2613
3574dda4
DV		 2614/*
2615 * r600 functions used by radeon_encoder.c
2616 */
1b688d08
RM		 2617struct radeon_hdmi_acr {
2618 u32 clock;
2619
2620 int n_32khz;
2621 int cts_32khz;
2622
2623 int n_44_1khz;
2624 int cts_44_1khz;
2625
2626 int n_48khz;
2627 int cts_48khz;
2628
2629};
2630
e55d3e6c
RM		 2631extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2632
416a2bd2
AD		 2633extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2634 u32 tiling_pipe_num,
2635 u32 max_rb_num,
2636 u32 total_max_rb_num,
2637 u32 enabled_rb_mask);
fe251e2f 2638
e55d3e6c
RM		 2639/*
2640 * evergreen functions used by radeon_encoder.c
2641 */
2642
0af62b01 2643extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2644extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2645
c4917074
AD		 2646/* radeon_acpi.c */
2647#if defined(CONFIG_ACPI)
2648extern int radeon_acpi_init(struct radeon_device *rdev);
2649extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2650extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2651extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2652 u8 perf_req, bool advertise);
dc50ba7f 2653extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2654#else
2655static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2656static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2657#endif
d7a2952f 2658
c38f34b5
IH		 2659int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2660 struct radeon_cs_packet *pkt,
2661 unsigned idx);
9ffb7a6d 2662bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2663void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2664 struct radeon_cs_packet *pkt);
e9716993
IH		 2665int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2666 struct radeon_cs_reloc **cs_reloc,
2667 int nomm);
40592a17
IH		 2668int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2669 uint32_t *vline_start_end,
2670 uint32_t *vline_status);
c38f34b5 2671
4c788679
JG		 2672#include "radeon_object.h"
2673
771fe6b9 2674#endif
Linux kernel - Deliverables
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