Commit | Line | Data |
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771fe6b9 JG |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #ifndef __RADEON_H__ | |
29 | #define __RADEON_H__ | |
30 | ||
771fe6b9 JG |
31 | /* TODO: Here are things that needs to be done : |
32 | * - surface allocator & initializer : (bit like scratch reg) should | |
33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings | |
34 | * related to surface | |
35 | * - WB : write back stuff (do it bit like scratch reg things) | |
36 | * - Vblank : look at Jesse's rework and what we should do | |
37 | * - r600/r700: gart & cp | |
38 | * - cs : clean cs ioctl use bitmap & things like that. | |
39 | * - power management stuff | |
40 | * - Barrier in gart code | |
41 | * - Unmappabled vram ? | |
42 | * - TESTING, TESTING, TESTING | |
43 | */ | |
44 | ||
d39c3b89 JG |
45 | /* Initialization path: |
46 | * We expect that acceleration initialization might fail for various | |
47 | * reasons even thought we work hard to make it works on most | |
48 | * configurations. In order to still have a working userspace in such | |
49 | * situation the init path must succeed up to the memory controller | |
50 | * initialization point. Failure before this point are considered as | |
51 | * fatal error. Here is the init callchain : | |
52 | * radeon_device_init perform common structure, mutex initialization | |
53 | * asic_init setup the GPU memory layout and perform all | |
54 | * one time initialization (failure in this | |
55 | * function are considered fatal) | |
56 | * asic_startup setup the GPU acceleration, in order to | |
57 | * follow guideline the first thing this | |
58 | * function should do is setting the GPU | |
59 | * memory controller (only MC setup failure | |
60 | * are considered as fatal) | |
61 | */ | |
62 | ||
60063497 | 63 | #include <linux/atomic.h> |
771fe6b9 JG |
64 | #include <linux/wait.h> |
65 | #include <linux/list.h> | |
66 | #include <linux/kref.h> | |
67 | ||
4c788679 JG |
68 | #include <ttm/ttm_bo_api.h> |
69 | #include <ttm/ttm_bo_driver.h> | |
70 | #include <ttm/ttm_placement.h> | |
71 | #include <ttm/ttm_module.h> | |
147666fb | 72 | #include <ttm/ttm_execbuf_util.h> |
4c788679 | 73 | |
c2142715 | 74 | #include "radeon_family.h" |
771fe6b9 JG |
75 | #include "radeon_mode.h" |
76 | #include "radeon_reg.h" | |
771fe6b9 JG |
77 | |
78 | /* | |
79 | * Modules parameters. | |
80 | */ | |
81 | extern int radeon_no_wb; | |
82 | extern int radeon_modeset; | |
83 | extern int radeon_dynclks; | |
84 | extern int radeon_r4xx_atom; | |
85 | extern int radeon_agpmode; | |
86 | extern int radeon_vram_limit; | |
87 | extern int radeon_gart_size; | |
88 | extern int radeon_benchmarking; | |
ecc0b326 | 89 | extern int radeon_testing; |
771fe6b9 | 90 | extern int radeon_connector_table; |
4ce001ab | 91 | extern int radeon_tv; |
dafc3bd5 | 92 | extern int radeon_audio; |
f46c0120 | 93 | extern int radeon_disp_priority; |
e2b0a8e1 | 94 | extern int radeon_hw_i2c; |
d42dd579 | 95 | extern int radeon_pcie_gen2; |
a18cee15 | 96 | extern int radeon_msi; |
3368ff0c | 97 | extern int radeon_lockup_timeout; |
a0a53aa8 | 98 | extern int radeon_fastfb; |
771fe6b9 JG |
99 | |
100 | /* | |
101 | * Copy from radeon_drv.h so we don't have to include both and have conflicting | |
102 | * symbol; | |
103 | */ | |
bb635567 JG |
104 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
105 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) | |
e821767b | 106 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
bb635567 JG |
107 | #define RADEON_IB_POOL_SIZE 16 |
108 | #define RADEON_DEBUGFS_MAX_COMPONENTS 32 | |
109 | #define RADEONFB_CONN_LIMIT 4 | |
110 | #define RADEON_BIOS_NUM_SCRATCH 8 | |
771fe6b9 | 111 | |
1b37078b | 112 | /* max number of rings */ |
f2ba57b5 | 113 | #define RADEON_NUM_RINGS 6 |
bb635567 JG |
114 | |
115 | /* fence seq are set to this number when signaled */ | |
116 | #define RADEON_FENCE_SIGNALED_SEQ 0LL | |
1b37078b AD |
117 | |
118 | /* internal ring indices */ | |
119 | /* r1xx+ has gfx CP ring */ | |
f2ba57b5 | 120 | #define RADEON_RING_TYPE_GFX_INDEX 0 |
1b37078b AD |
121 | |
122 | /* cayman has 2 compute CP rings */ | |
f2ba57b5 CK |
123 | #define CAYMAN_RING_TYPE_CP1_INDEX 1 |
124 | #define CAYMAN_RING_TYPE_CP2_INDEX 2 | |
1b37078b | 125 | |
4d75658b AD |
126 | /* R600+ has an async dma ring */ |
127 | #define R600_RING_TYPE_DMA_INDEX 3 | |
f60cbd11 AD |
128 | /* cayman add a second async dma ring */ |
129 | #define CAYMAN_RING_TYPE_DMA1_INDEX 4 | |
4d75658b | 130 | |
f2ba57b5 CK |
131 | /* R600+ */ |
132 | #define R600_RING_TYPE_UVD_INDEX 5 | |
133 | ||
721604a1 | 134 | /* hardcode those limit for now */ |
ca19f21e | 135 | #define RADEON_VA_IB_OFFSET (1 << 20) |
bb635567 JG |
136 | #define RADEON_VA_RESERVED_SIZE (8 << 20) |
137 | #define RADEON_IB_VM_MAX_SIZE (64 << 10) | |
721604a1 | 138 | |
ec46c76d AD |
139 | /* reset flags */ |
140 | #define RADEON_RESET_GFX (1 << 0) | |
141 | #define RADEON_RESET_COMPUTE (1 << 1) | |
142 | #define RADEON_RESET_DMA (1 << 2) | |
9ff0744c AD |
143 | #define RADEON_RESET_CP (1 << 3) |
144 | #define RADEON_RESET_GRBM (1 << 4) | |
145 | #define RADEON_RESET_DMA1 (1 << 5) | |
146 | #define RADEON_RESET_RLC (1 << 6) | |
147 | #define RADEON_RESET_SEM (1 << 7) | |
148 | #define RADEON_RESET_IH (1 << 8) | |
149 | #define RADEON_RESET_VMC (1 << 9) | |
150 | #define RADEON_RESET_MC (1 << 10) | |
151 | #define RADEON_RESET_DISPLAY (1 << 11) | |
ec46c76d | 152 | |
9e05fa1d AD |
153 | /* max cursor sizes (in pixels) */ |
154 | #define CURSOR_WIDTH 64 | |
155 | #define CURSOR_HEIGHT 64 | |
156 | ||
157 | #define CIK_CURSOR_WIDTH 128 | |
158 | #define CIK_CURSOR_HEIGHT 128 | |
159 | ||
771fe6b9 JG |
160 | /* |
161 | * Errata workarounds. | |
162 | */ | |
163 | enum radeon_pll_errata { | |
164 | CHIP_ERRATA_R300_CG = 0x00000001, | |
165 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, | |
166 | CHIP_ERRATA_PLL_DELAY = 0x00000004 | |
167 | }; | |
168 | ||
169 | ||
170 | struct radeon_device; | |
171 | ||
172 | ||
173 | /* | |
174 | * BIOS. | |
175 | */ | |
176 | bool radeon_get_bios(struct radeon_device *rdev); | |
177 | ||
178 | /* | |
3ce0a23d | 179 | * Dummy page |
771fe6b9 | 180 | */ |
3ce0a23d JG |
181 | struct radeon_dummy_page { |
182 | struct page *page; | |
183 | dma_addr_t addr; | |
184 | }; | |
185 | int radeon_dummy_page_init(struct radeon_device *rdev); | |
186 | void radeon_dummy_page_fini(struct radeon_device *rdev); | |
187 | ||
771fe6b9 | 188 | |
3ce0a23d JG |
189 | /* |
190 | * Clocks | |
191 | */ | |
771fe6b9 JG |
192 | struct radeon_clock { |
193 | struct radeon_pll p1pll; | |
194 | struct radeon_pll p2pll; | |
bcc1c2a1 | 195 | struct radeon_pll dcpll; |
771fe6b9 JG |
196 | struct radeon_pll spll; |
197 | struct radeon_pll mpll; | |
198 | /* 10 Khz units */ | |
199 | uint32_t default_mclk; | |
200 | uint32_t default_sclk; | |
bcc1c2a1 AD |
201 | uint32_t default_dispclk; |
202 | uint32_t dp_extclk; | |
b20f9bef | 203 | uint32_t max_pixel_clock; |
771fe6b9 JG |
204 | }; |
205 | ||
7433874e RM |
206 | /* |
207 | * Power management | |
208 | */ | |
209 | int radeon_pm_init(struct radeon_device *rdev); | |
29fb52ca | 210 | void radeon_pm_fini(struct radeon_device *rdev); |
c913e23a | 211 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
ce8f5370 AD |
212 | void radeon_pm_suspend(struct radeon_device *rdev); |
213 | void radeon_pm_resume(struct radeon_device *rdev); | |
56278a8e AD |
214 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
215 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); | |
7062ab67 CK |
216 | int radeon_atom_get_clock_dividers(struct radeon_device *rdev, |
217 | u8 clock_type, | |
218 | u32 clock, | |
219 | bool strobe_mode, | |
220 | struct atom_clock_dividers *dividers); | |
8a83ec5e | 221 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
ae5b0abb AD |
222 | int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, |
223 | u16 voltage_level, u8 voltage_type, | |
224 | u32 *gpio_value, u32 *gpio_mask); | |
225 | void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, | |
226 | u32 eng_clock, u32 mem_clock); | |
227 | int radeon_atom_get_voltage_step(struct radeon_device *rdev, | |
228 | u8 voltage_type, u16 *voltage_step); | |
229 | int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, | |
230 | u8 voltage_type, | |
231 | u16 nominal_voltage, | |
232 | u16 *true_voltage); | |
233 | int radeon_atom_get_min_voltage(struct radeon_device *rdev, | |
234 | u8 voltage_type, u16 *min_voltage); | |
235 | int radeon_atom_get_max_voltage(struct radeon_device *rdev, | |
236 | u8 voltage_type, u16 *max_voltage); | |
237 | int radeon_atom_get_voltage_table(struct radeon_device *rdev, | |
238 | u8 voltage_type, | |
239 | struct atom_voltage_table *voltage_table); | |
240 | bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, u8 voltage_type); | |
241 | void radeon_atom_update_memory_dll(struct radeon_device *rdev, | |
242 | u32 mem_clock); | |
243 | void radeon_atom_set_ac_timing(struct radeon_device *rdev, | |
244 | u32 mem_clock); | |
245 | int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, | |
246 | u8 module_index, | |
247 | struct atom_mc_reg_table *reg_table); | |
248 | int radeon_atom_get_memory_info(struct radeon_device *rdev, | |
249 | u8 module_index, struct atom_memory_info *mem_info); | |
250 | int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, | |
251 | bool gddr5, u8 module_index, | |
252 | struct atom_memory_clock_range_table *mclk_range_table); | |
253 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, | |
254 | u16 voltage_id, u16 *voltage); | |
f892034a | 255 | void rs690_pm_info(struct radeon_device *rdev); |
285484e2 JG |
256 | extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, |
257 | unsigned *bankh, unsigned *mtaspect, | |
258 | unsigned *tile_split); | |
3ce0a23d | 259 | |
771fe6b9 JG |
260 | /* |
261 | * Fences. | |
262 | */ | |
263 | struct radeon_fence_driver { | |
264 | uint32_t scratch_reg; | |
30eb77f4 JG |
265 | uint64_t gpu_addr; |
266 | volatile uint32_t *cpu_addr; | |
68e250b7 CK |
267 | /* sync_seq is protected by ring emission lock */ |
268 | uint64_t sync_seq[RADEON_NUM_RINGS]; | |
bb635567 | 269 | atomic64_t last_seq; |
36abacae | 270 | unsigned long last_activity; |
0a0c7596 | 271 | bool initialized; |
771fe6b9 JG |
272 | }; |
273 | ||
274 | struct radeon_fence { | |
275 | struct radeon_device *rdev; | |
276 | struct kref kref; | |
771fe6b9 | 277 | /* protected by radeon_fence.lock */ |
bb635567 | 278 | uint64_t seq; |
7465280c | 279 | /* RB, DMA, etc. */ |
bb635567 | 280 | unsigned ring; |
771fe6b9 JG |
281 | }; |
282 | ||
30eb77f4 JG |
283 | int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); |
284 | int radeon_fence_driver_init(struct radeon_device *rdev); | |
771fe6b9 | 285 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
76903b96 | 286 | void radeon_fence_driver_force_completion(struct radeon_device *rdev); |
876dc9f3 | 287 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); |
7465280c | 288 | void radeon_fence_process(struct radeon_device *rdev, int ring); |
771fe6b9 JG |
289 | bool radeon_fence_signaled(struct radeon_fence *fence); |
290 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); | |
8a47cc9e | 291 | int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring); |
5f8f635e | 292 | int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring); |
0085c950 JG |
293 | int radeon_fence_wait_any(struct radeon_device *rdev, |
294 | struct radeon_fence **fences, | |
295 | bool intr); | |
771fe6b9 JG |
296 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
297 | void radeon_fence_unref(struct radeon_fence **fence); | |
3b7a2b24 | 298 | unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); |
68e250b7 CK |
299 | bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); |
300 | void radeon_fence_note_sync(struct radeon_fence *fence, int ring); | |
301 | static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, | |
302 | struct radeon_fence *b) | |
303 | { | |
304 | if (!a) { | |
305 | return b; | |
306 | } | |
307 | ||
308 | if (!b) { | |
309 | return a; | |
310 | } | |
311 | ||
312 | BUG_ON(a->ring != b->ring); | |
313 | ||
314 | if (a->seq > b->seq) { | |
315 | return a; | |
316 | } else { | |
317 | return b; | |
318 | } | |
319 | } | |
771fe6b9 | 320 | |
ee60e29f CK |
321 | static inline bool radeon_fence_is_earlier(struct radeon_fence *a, |
322 | struct radeon_fence *b) | |
323 | { | |
324 | if (!a) { | |
325 | return false; | |
326 | } | |
327 | ||
328 | if (!b) { | |
329 | return true; | |
330 | } | |
331 | ||
332 | BUG_ON(a->ring != b->ring); | |
333 | ||
334 | return a->seq < b->seq; | |
335 | } | |
336 | ||
e024e110 DA |
337 | /* |
338 | * Tiling registers | |
339 | */ | |
340 | struct radeon_surface_reg { | |
4c788679 | 341 | struct radeon_bo *bo; |
e024e110 DA |
342 | }; |
343 | ||
344 | #define RADEON_GEM_MAX_SURFACES 8 | |
771fe6b9 JG |
345 | |
346 | /* | |
4c788679 | 347 | * TTM. |
771fe6b9 | 348 | */ |
4c788679 JG |
349 | struct radeon_mman { |
350 | struct ttm_bo_global_ref bo_global_ref; | |
ba4420c2 | 351 | struct drm_global_reference mem_global_ref; |
4c788679 | 352 | struct ttm_bo_device bdev; |
0a0c7596 JG |
353 | bool mem_global_referenced; |
354 | bool initialized; | |
4c788679 JG |
355 | }; |
356 | ||
721604a1 JG |
357 | /* bo virtual address in a specific vm */ |
358 | struct radeon_bo_va { | |
e971bd5e | 359 | /* protected by bo being reserved */ |
721604a1 | 360 | struct list_head bo_list; |
721604a1 JG |
361 | uint64_t soffset; |
362 | uint64_t eoffset; | |
363 | uint32_t flags; | |
364 | bool valid; | |
e971bd5e CK |
365 | unsigned ref_count; |
366 | ||
367 | /* protected by vm mutex */ | |
368 | struct list_head vm_list; | |
369 | ||
370 | /* constant after initialization */ | |
371 | struct radeon_vm *vm; | |
372 | struct radeon_bo *bo; | |
721604a1 JG |
373 | }; |
374 | ||
4c788679 JG |
375 | struct radeon_bo { |
376 | /* Protected by gem.mutex */ | |
377 | struct list_head list; | |
378 | /* Protected by tbo.reserved */ | |
312ea8da JG |
379 | u32 placements[3]; |
380 | struct ttm_placement placement; | |
4c788679 JG |
381 | struct ttm_buffer_object tbo; |
382 | struct ttm_bo_kmap_obj kmap; | |
383 | unsigned pin_count; | |
384 | void *kptr; | |
385 | u32 tiling_flags; | |
386 | u32 pitch; | |
387 | int surface_reg; | |
721604a1 JG |
388 | /* list of all virtual address to which this bo |
389 | * is associated to | |
390 | */ | |
391 | struct list_head va; | |
4c788679 JG |
392 | /* Constant after initialization */ |
393 | struct radeon_device *rdev; | |
441921d5 | 394 | struct drm_gem_object gem_base; |
63bc620b | 395 | |
409851f4 JG |
396 | struct ttm_bo_kmap_obj dma_buf_vmap; |
397 | pid_t pid; | |
4c788679 | 398 | }; |
7e4d15d9 | 399 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
771fe6b9 | 400 | |
4c788679 | 401 | struct radeon_bo_list { |
147666fb | 402 | struct ttm_validate_buffer tv; |
4c788679 | 403 | struct radeon_bo *bo; |
771fe6b9 | 404 | uint64_t gpu_offset; |
4474f3a9 CK |
405 | bool written; |
406 | unsigned domain; | |
407 | unsigned alt_domain; | |
4c788679 | 408 | u32 tiling_flags; |
771fe6b9 JG |
409 | }; |
410 | ||
409851f4 JG |
411 | int radeon_gem_debugfs_init(struct radeon_device *rdev); |
412 | ||
b15ba512 JG |
413 | /* sub-allocation manager, it has to be protected by another lock. |
414 | * By conception this is an helper for other part of the driver | |
415 | * like the indirect buffer or semaphore, which both have their | |
416 | * locking. | |
417 | * | |
418 | * Principe is simple, we keep a list of sub allocation in offset | |
419 | * order (first entry has offset == 0, last entry has the highest | |
420 | * offset). | |
421 | * | |
422 | * When allocating new object we first check if there is room at | |
423 | * the end total_size - (last_object_offset + last_object_size) >= | |
424 | * alloc_size. If so we allocate new object there. | |
425 | * | |
426 | * When there is not enough room at the end, we start waiting for | |
427 | * each sub object until we reach object_offset+object_size >= | |
428 | * alloc_size, this object then become the sub object we return. | |
429 | * | |
430 | * Alignment can't be bigger than page size. | |
431 | * | |
432 | * Hole are not considered for allocation to keep things simple. | |
433 | * Assumption is that there won't be hole (all object on same | |
434 | * alignment). | |
435 | */ | |
436 | struct radeon_sa_manager { | |
bfb38d35 | 437 | wait_queue_head_t wq; |
b15ba512 | 438 | struct radeon_bo *bo; |
c3b7fe8b CK |
439 | struct list_head *hole; |
440 | struct list_head flist[RADEON_NUM_RINGS]; | |
441 | struct list_head olist; | |
b15ba512 JG |
442 | unsigned size; |
443 | uint64_t gpu_addr; | |
444 | void *cpu_ptr; | |
445 | uint32_t domain; | |
446 | }; | |
447 | ||
448 | struct radeon_sa_bo; | |
449 | ||
450 | /* sub-allocation buffer */ | |
451 | struct radeon_sa_bo { | |
c3b7fe8b CK |
452 | struct list_head olist; |
453 | struct list_head flist; | |
b15ba512 | 454 | struct radeon_sa_manager *manager; |
e6661a96 CK |
455 | unsigned soffset; |
456 | unsigned eoffset; | |
557017a0 | 457 | struct radeon_fence *fence; |
b15ba512 JG |
458 | }; |
459 | ||
771fe6b9 JG |
460 | /* |
461 | * GEM objects. | |
462 | */ | |
463 | struct radeon_gem { | |
4c788679 | 464 | struct mutex mutex; |
771fe6b9 JG |
465 | struct list_head objects; |
466 | }; | |
467 | ||
468 | int radeon_gem_init(struct radeon_device *rdev); | |
469 | void radeon_gem_fini(struct radeon_device *rdev); | |
470 | int radeon_gem_object_create(struct radeon_device *rdev, int size, | |
4c788679 JG |
471 | int alignment, int initial_domain, |
472 | bool discardable, bool kernel, | |
473 | struct drm_gem_object **obj); | |
771fe6b9 | 474 | |
ff72145b DA |
475 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
476 | struct drm_device *dev, | |
477 | struct drm_mode_create_dumb *args); | |
478 | int radeon_mode_dumb_mmap(struct drm_file *filp, | |
479 | struct drm_device *dev, | |
480 | uint32_t handle, uint64_t *offset_p); | |
481 | int radeon_mode_dumb_destroy(struct drm_file *file_priv, | |
482 | struct drm_device *dev, | |
483 | uint32_t handle); | |
771fe6b9 | 484 | |
c1341e52 JG |
485 | /* |
486 | * Semaphores. | |
487 | */ | |
c1341e52 JG |
488 | /* everything here is constant */ |
489 | struct radeon_semaphore { | |
a8c05940 JG |
490 | struct radeon_sa_bo *sa_bo; |
491 | signed waiters; | |
c1341e52 | 492 | uint64_t gpu_addr; |
c1341e52 JG |
493 | }; |
494 | ||
c1341e52 JG |
495 | int radeon_semaphore_create(struct radeon_device *rdev, |
496 | struct radeon_semaphore **semaphore); | |
497 | void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, | |
498 | struct radeon_semaphore *semaphore); | |
499 | void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, | |
500 | struct radeon_semaphore *semaphore); | |
8f676c4c CK |
501 | int radeon_semaphore_sync_rings(struct radeon_device *rdev, |
502 | struct radeon_semaphore *semaphore, | |
220907d9 | 503 | int signaler, int waiter); |
c1341e52 | 504 | void radeon_semaphore_free(struct radeon_device *rdev, |
220907d9 | 505 | struct radeon_semaphore **semaphore, |
a8c05940 | 506 | struct radeon_fence *fence); |
c1341e52 | 507 | |
771fe6b9 JG |
508 | /* |
509 | * GART structures, functions & helpers | |
510 | */ | |
511 | struct radeon_mc; | |
512 | ||
a77f1718 | 513 | #define RADEON_GPU_PAGE_SIZE 4096 |
d594e46a | 514 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
003cefe0 | 515 | #define RADEON_GPU_PAGE_SHIFT 12 |
721604a1 | 516 | #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) |
a77f1718 | 517 | |
771fe6b9 JG |
518 | struct radeon_gart { |
519 | dma_addr_t table_addr; | |
c9a1be96 JG |
520 | struct radeon_bo *robj; |
521 | void *ptr; | |
771fe6b9 JG |
522 | unsigned num_gpu_pages; |
523 | unsigned num_cpu_pages; | |
524 | unsigned table_size; | |
771fe6b9 JG |
525 | struct page **pages; |
526 | dma_addr_t *pages_addr; | |
527 | bool ready; | |
528 | }; | |
529 | ||
530 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); | |
531 | void radeon_gart_table_ram_free(struct radeon_device *rdev); | |
532 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); | |
533 | void radeon_gart_table_vram_free(struct radeon_device *rdev); | |
c9a1be96 JG |
534 | int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
535 | void radeon_gart_table_vram_unpin(struct radeon_device *rdev); | |
771fe6b9 JG |
536 | int radeon_gart_init(struct radeon_device *rdev); |
537 | void radeon_gart_fini(struct radeon_device *rdev); | |
538 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, | |
539 | int pages); | |
540 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, | |
c39d3516 KRW |
541 | int pages, struct page **pagelist, |
542 | dma_addr_t *dma_addr); | |
c9a1be96 | 543 | void radeon_gart_restore(struct radeon_device *rdev); |
771fe6b9 JG |
544 | |
545 | ||
546 | /* | |
547 | * GPU MC structures, functions & helpers | |
548 | */ | |
549 | struct radeon_mc { | |
550 | resource_size_t aper_size; | |
551 | resource_size_t aper_base; | |
552 | resource_size_t agp_base; | |
7a50f01a DA |
553 | /* for some chips with <= 32MB we need to lie |
554 | * about vram size near mc fb location */ | |
3ce0a23d | 555 | u64 mc_vram_size; |
d594e46a | 556 | u64 visible_vram_size; |
3ce0a23d JG |
557 | u64 gtt_size; |
558 | u64 gtt_start; | |
559 | u64 gtt_end; | |
3ce0a23d JG |
560 | u64 vram_start; |
561 | u64 vram_end; | |
771fe6b9 | 562 | unsigned vram_width; |
3ce0a23d | 563 | u64 real_vram_size; |
771fe6b9 JG |
564 | int vram_mtrr; |
565 | bool vram_is_ddr; | |
d594e46a | 566 | bool igp_sideport_enabled; |
8d369bb1 | 567 | u64 gtt_base_align; |
9ed8b1f9 | 568 | u64 mc_mask; |
771fe6b9 JG |
569 | }; |
570 | ||
06b6476d AD |
571 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
572 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); | |
771fe6b9 JG |
573 | |
574 | /* | |
575 | * GPU scratch registers structures, functions & helpers | |
576 | */ | |
577 | struct radeon_scratch { | |
578 | unsigned num_reg; | |
724c80e1 | 579 | uint32_t reg_base; |
771fe6b9 JG |
580 | bool free[32]; |
581 | uint32_t reg[32]; | |
582 | }; | |
583 | ||
584 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); | |
585 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); | |
586 | ||
75efdee1 AD |
587 | /* |
588 | * GPU doorbell structures, functions & helpers | |
589 | */ | |
590 | struct radeon_doorbell { | |
591 | u32 num_pages; | |
592 | bool free[1024]; | |
593 | /* doorbell mmio */ | |
594 | resource_size_t base; | |
595 | resource_size_t size; | |
596 | void __iomem *ptr; | |
597 | }; | |
598 | ||
599 | int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); | |
600 | void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); | |
771fe6b9 JG |
601 | |
602 | /* | |
603 | * IRQS. | |
604 | */ | |
6f34be50 AD |
605 | |
606 | struct radeon_unpin_work { | |
607 | struct work_struct work; | |
608 | struct radeon_device *rdev; | |
609 | int crtc_id; | |
610 | struct radeon_fence *fence; | |
611 | struct drm_pending_vblank_event *event; | |
612 | struct radeon_bo *old_rbo; | |
613 | u64 new_crtc_base; | |
614 | }; | |
615 | ||
616 | struct r500_irq_stat_regs { | |
617 | u32 disp_int; | |
f122c610 | 618 | u32 hdmi0_status; |
6f34be50 AD |
619 | }; |
620 | ||
621 | struct r600_irq_stat_regs { | |
622 | u32 disp_int; | |
623 | u32 disp_int_cont; | |
624 | u32 disp_int_cont2; | |
625 | u32 d1grph_int; | |
626 | u32 d2grph_int; | |
f122c610 AD |
627 | u32 hdmi0_status; |
628 | u32 hdmi1_status; | |
6f34be50 AD |
629 | }; |
630 | ||
631 | struct evergreen_irq_stat_regs { | |
632 | u32 disp_int; | |
633 | u32 disp_int_cont; | |
634 | u32 disp_int_cont2; | |
635 | u32 disp_int_cont3; | |
636 | u32 disp_int_cont4; | |
637 | u32 disp_int_cont5; | |
638 | u32 d1grph_int; | |
639 | u32 d2grph_int; | |
640 | u32 d3grph_int; | |
641 | u32 d4grph_int; | |
642 | u32 d5grph_int; | |
643 | u32 d6grph_int; | |
f122c610 AD |
644 | u32 afmt_status1; |
645 | u32 afmt_status2; | |
646 | u32 afmt_status3; | |
647 | u32 afmt_status4; | |
648 | u32 afmt_status5; | |
649 | u32 afmt_status6; | |
6f34be50 AD |
650 | }; |
651 | ||
a59781bb AD |
652 | struct cik_irq_stat_regs { |
653 | u32 disp_int; | |
654 | u32 disp_int_cont; | |
655 | u32 disp_int_cont2; | |
656 | u32 disp_int_cont3; | |
657 | u32 disp_int_cont4; | |
658 | u32 disp_int_cont5; | |
659 | u32 disp_int_cont6; | |
660 | }; | |
661 | ||
6f34be50 AD |
662 | union radeon_irq_stat_regs { |
663 | struct r500_irq_stat_regs r500; | |
664 | struct r600_irq_stat_regs r600; | |
665 | struct evergreen_irq_stat_regs evergreen; | |
a59781bb | 666 | struct cik_irq_stat_regs cik; |
6f34be50 AD |
667 | }; |
668 | ||
54bd5206 IH |
669 | #define RADEON_MAX_HPD_PINS 6 |
670 | #define RADEON_MAX_CRTCS 6 | |
f122c610 | 671 | #define RADEON_MAX_AFMT_BLOCKS 6 |
54bd5206 | 672 | |
771fe6b9 | 673 | struct radeon_irq { |
fb98257a CK |
674 | bool installed; |
675 | spinlock_t lock; | |
736fc37f | 676 | atomic_t ring_int[RADEON_NUM_RINGS]; |
fb98257a | 677 | bool crtc_vblank_int[RADEON_MAX_CRTCS]; |
736fc37f | 678 | atomic_t pflip[RADEON_MAX_CRTCS]; |
fb98257a CK |
679 | wait_queue_head_t vblank_queue; |
680 | bool hpd[RADEON_MAX_HPD_PINS]; | |
fb98257a CK |
681 | bool afmt[RADEON_MAX_AFMT_BLOCKS]; |
682 | union radeon_irq_stat_regs stat_regs; | |
771fe6b9 JG |
683 | }; |
684 | ||
685 | int radeon_irq_kms_init(struct radeon_device *rdev); | |
686 | void radeon_irq_kms_fini(struct radeon_device *rdev); | |
1b37078b AD |
687 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); |
688 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); | |
6f34be50 AD |
689 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
690 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); | |
fb98257a CK |
691 | void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); |
692 | void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); | |
693 | void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); | |
694 | void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); | |
771fe6b9 JG |
695 | |
696 | /* | |
e32eb50d | 697 | * CP & rings. |
771fe6b9 | 698 | */ |
7465280c | 699 | |
771fe6b9 | 700 | struct radeon_ib { |
68470ae7 JG |
701 | struct radeon_sa_bo *sa_bo; |
702 | uint32_t length_dw; | |
703 | uint64_t gpu_addr; | |
704 | uint32_t *ptr; | |
876dc9f3 | 705 | int ring; |
68470ae7 | 706 | struct radeon_fence *fence; |
4bf3dd92 | 707 | struct radeon_vm *vm; |
68470ae7 | 708 | bool is_const_ib; |
220907d9 | 709 | struct radeon_fence *sync_to[RADEON_NUM_RINGS]; |
68470ae7 | 710 | struct radeon_semaphore *semaphore; |
771fe6b9 JG |
711 | }; |
712 | ||
e32eb50d | 713 | struct radeon_ring { |
4c788679 | 714 | struct radeon_bo *ring_obj; |
771fe6b9 JG |
715 | volatile uint32_t *ring; |
716 | unsigned rptr; | |
5596a9db CK |
717 | unsigned rptr_offs; |
718 | unsigned rptr_reg; | |
45df6803 | 719 | unsigned rptr_save_reg; |
89d35807 AD |
720 | u64 next_rptr_gpu_addr; |
721 | volatile u32 *next_rptr_cpu_addr; | |
771fe6b9 JG |
722 | unsigned wptr; |
723 | unsigned wptr_old; | |
5596a9db | 724 | unsigned wptr_reg; |
771fe6b9 JG |
725 | unsigned ring_size; |
726 | unsigned ring_free_dw; | |
727 | int count_dw; | |
069211e5 CK |
728 | unsigned long last_activity; |
729 | unsigned last_rptr; | |
771fe6b9 JG |
730 | uint64_t gpu_addr; |
731 | uint32_t align_mask; | |
732 | uint32_t ptr_mask; | |
771fe6b9 | 733 | bool ready; |
78c5560a AD |
734 | u32 ptr_reg_shift; |
735 | u32 ptr_reg_mask; | |
736 | u32 nop; | |
8b25ed34 | 737 | u32 idx; |
5f0839c1 JG |
738 | u64 last_semaphore_signal_addr; |
739 | u64 last_semaphore_wait_addr; | |
963e81f9 AD |
740 | /* for CIK queues */ |
741 | u32 me; | |
742 | u32 pipe; | |
743 | u32 queue; | |
744 | struct radeon_bo *mqd_obj; | |
745 | u32 doorbell_page_num; | |
746 | u32 doorbell_offset; | |
747 | unsigned wptr_offs; | |
748 | }; | |
749 | ||
750 | struct radeon_mec { | |
751 | struct radeon_bo *hpd_eop_obj; | |
752 | u64 hpd_eop_gpu_addr; | |
753 | u32 num_pipe; | |
754 | u32 num_mec; | |
755 | u32 num_queue; | |
771fe6b9 JG |
756 | }; |
757 | ||
721604a1 JG |
758 | /* |
759 | * VM | |
760 | */ | |
ee60e29f | 761 | |
fa87e62d | 762 | /* maximum number of VMIDs */ |
ee60e29f CK |
763 | #define RADEON_NUM_VM 16 |
764 | ||
fa87e62d DC |
765 | /* defines number of bits in page table versus page directory, |
766 | * a page is 4KB so we have 12 bits offset, 9 bits in the page | |
767 | * table and the remaining 19 bits are in the page directory */ | |
768 | #define RADEON_VM_BLOCK_SIZE 9 | |
769 | ||
770 | /* number of entries in page table */ | |
771 | #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) | |
772 | ||
721604a1 JG |
773 | struct radeon_vm { |
774 | struct list_head list; | |
775 | struct list_head va; | |
ee60e29f | 776 | unsigned id; |
90a51a32 CK |
777 | |
778 | /* contains the page directory */ | |
779 | struct radeon_sa_bo *page_directory; | |
780 | uint64_t pd_gpu_addr; | |
781 | ||
782 | /* array of page tables, one for each page directory entry */ | |
783 | struct radeon_sa_bo **page_tables; | |
784 | ||
721604a1 JG |
785 | struct mutex mutex; |
786 | /* last fence for cs using this vm */ | |
787 | struct radeon_fence *fence; | |
9b40e5d8 CK |
788 | /* last flush or NULL if we still need to flush */ |
789 | struct radeon_fence *last_flush; | |
721604a1 JG |
790 | }; |
791 | ||
721604a1 | 792 | struct radeon_vm_manager { |
36ff39c4 | 793 | struct mutex lock; |
721604a1 | 794 | struct list_head lru_vm; |
ee60e29f | 795 | struct radeon_fence *active[RADEON_NUM_VM]; |
721604a1 JG |
796 | struct radeon_sa_manager sa_manager; |
797 | uint32_t max_pfn; | |
721604a1 JG |
798 | /* number of VMIDs */ |
799 | unsigned nvm; | |
800 | /* vram base address for page table entry */ | |
801 | u64 vram_base_offset; | |
67e915e4 AD |
802 | /* is vm enabled? */ |
803 | bool enabled; | |
721604a1 JG |
804 | }; |
805 | ||
806 | /* | |
807 | * file private structure | |
808 | */ | |
809 | struct radeon_fpriv { | |
810 | struct radeon_vm vm; | |
811 | }; | |
812 | ||
d8f60cfc AD |
813 | /* |
814 | * R6xx+ IH ring | |
815 | */ | |
816 | struct r600_ih { | |
4c788679 | 817 | struct radeon_bo *ring_obj; |
d8f60cfc AD |
818 | volatile uint32_t *ring; |
819 | unsigned rptr; | |
d8f60cfc AD |
820 | unsigned ring_size; |
821 | uint64_t gpu_addr; | |
d8f60cfc | 822 | uint32_t ptr_mask; |
c20dc369 | 823 | atomic_t lock; |
d8f60cfc AD |
824 | bool enabled; |
825 | }; | |
826 | ||
8eec9d6f IH |
827 | struct r600_blit_cp_primitives { |
828 | void (*set_render_target)(struct radeon_device *rdev, int format, | |
829 | int w, int h, u64 gpu_addr); | |
830 | void (*cp_set_surface_sync)(struct radeon_device *rdev, | |
831 | u32 sync_type, u32 size, | |
832 | u64 mc_addr); | |
833 | void (*set_shaders)(struct radeon_device *rdev); | |
834 | void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr); | |
835 | void (*set_tex_resource)(struct radeon_device *rdev, | |
836 | int format, int w, int h, int pitch, | |
9bb7703c | 837 | u64 gpu_addr, u32 size); |
8eec9d6f IH |
838 | void (*set_scissors)(struct radeon_device *rdev, int x1, int y1, |
839 | int x2, int y2); | |
840 | void (*draw_auto)(struct radeon_device *rdev); | |
841 | void (*set_default_state)(struct radeon_device *rdev); | |
842 | }; | |
843 | ||
3ce0a23d | 844 | struct r600_blit { |
4c788679 | 845 | struct radeon_bo *shader_obj; |
8eec9d6f IH |
846 | struct r600_blit_cp_primitives primitives; |
847 | int max_dim; | |
848 | int ring_size_common; | |
849 | int ring_size_per_loop; | |
3ce0a23d JG |
850 | u64 shader_gpu_addr; |
851 | u32 vs_offset, ps_offset; | |
852 | u32 state_offset; | |
853 | u32 state_len; | |
3ce0a23d JG |
854 | }; |
855 | ||
347e7592 | 856 | /* |
2948f5e6 | 857 | * RLC stuff |
347e7592 | 858 | */ |
2948f5e6 AD |
859 | #include "clearstate_defs.h" |
860 | ||
861 | struct radeon_rlc { | |
347e7592 AD |
862 | /* for power gating */ |
863 | struct radeon_bo *save_restore_obj; | |
864 | uint64_t save_restore_gpu_addr; | |
2948f5e6 AD |
865 | volatile uint32_t *sr_ptr; |
866 | u32 *reg_list; | |
867 | u32 reg_list_size; | |
347e7592 AD |
868 | /* for clear state */ |
869 | struct radeon_bo *clear_state_obj; | |
870 | uint64_t clear_state_gpu_addr; | |
2948f5e6 AD |
871 | volatile uint32_t *cs_ptr; |
872 | struct cs_section_def *cs_data; | |
347e7592 AD |
873 | }; |
874 | ||
69e130a6 | 875 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
4bf3dd92 CK |
876 | struct radeon_ib *ib, struct radeon_vm *vm, |
877 | unsigned size); | |
f2e39221 | 878 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); |
43f1214a | 879 | void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence); |
4ef72566 CK |
880 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
881 | struct radeon_ib *const_ib); | |
771fe6b9 JG |
882 | int radeon_ib_pool_init(struct radeon_device *rdev); |
883 | void radeon_ib_pool_fini(struct radeon_device *rdev); | |
7bd560e8 | 884 | int radeon_ib_ring_tests(struct radeon_device *rdev); |
771fe6b9 | 885 | /* Ring access between begin & end cannot sleep */ |
89d35807 AD |
886 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
887 | struct radeon_ring *ring); | |
e32eb50d CK |
888 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); |
889 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); | |
890 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); | |
891 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); | |
892 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); | |
d6999bc7 | 893 | void radeon_ring_undo(struct radeon_ring *ring); |
e32eb50d CK |
894 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); |
895 | int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); | |
7b9ef16b | 896 | void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring); |
069211e5 CK |
897 | void radeon_ring_lockup_update(struct radeon_ring *ring); |
898 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); | |
55d7c221 CK |
899 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, |
900 | uint32_t **data); | |
901 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, | |
902 | unsigned size, uint32_t *data); | |
e32eb50d | 903 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, |
78c5560a AD |
904 | unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, |
905 | u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop); | |
e32eb50d | 906 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); |
771fe6b9 JG |
907 | |
908 | ||
4d75658b AD |
909 | /* r600 async dma */ |
910 | void r600_dma_stop(struct radeon_device *rdev); | |
911 | int r600_dma_resume(struct radeon_device *rdev); | |
912 | void r600_dma_fini(struct radeon_device *rdev); | |
913 | ||
8c5fd7ef AD |
914 | void cayman_dma_stop(struct radeon_device *rdev); |
915 | int cayman_dma_resume(struct radeon_device *rdev); | |
916 | void cayman_dma_fini(struct radeon_device *rdev); | |
917 | ||
771fe6b9 JG |
918 | /* |
919 | * CS. | |
920 | */ | |
921 | struct radeon_cs_reloc { | |
922 | struct drm_gem_object *gobj; | |
4c788679 JG |
923 | struct radeon_bo *robj; |
924 | struct radeon_bo_list lobj; | |
771fe6b9 JG |
925 | uint32_t handle; |
926 | uint32_t flags; | |
927 | }; | |
928 | ||
929 | struct radeon_cs_chunk { | |
930 | uint32_t chunk_id; | |
931 | uint32_t length_dw; | |
721604a1 JG |
932 | int kpage_idx[2]; |
933 | uint32_t *kpage[2]; | |
771fe6b9 | 934 | uint32_t *kdata; |
721604a1 JG |
935 | void __user *user_ptr; |
936 | int last_copied_page; | |
937 | int last_page_index; | |
771fe6b9 JG |
938 | }; |
939 | ||
940 | struct radeon_cs_parser { | |
c8c15ff1 | 941 | struct device *dev; |
771fe6b9 JG |
942 | struct radeon_device *rdev; |
943 | struct drm_file *filp; | |
944 | /* chunks */ | |
945 | unsigned nchunks; | |
946 | struct radeon_cs_chunk *chunks; | |
947 | uint64_t *chunks_array; | |
948 | /* IB */ | |
949 | unsigned idx; | |
950 | /* relocations */ | |
951 | unsigned nrelocs; | |
952 | struct radeon_cs_reloc *relocs; | |
953 | struct radeon_cs_reloc **relocs_ptr; | |
954 | struct list_head validated; | |
cf4ccd01 | 955 | unsigned dma_reloc_idx; |
771fe6b9 JG |
956 | /* indices of various chunks */ |
957 | int chunk_ib_idx; | |
958 | int chunk_relocs_idx; | |
721604a1 | 959 | int chunk_flags_idx; |
dfcf5f36 | 960 | int chunk_const_ib_idx; |
f2e39221 JG |
961 | struct radeon_ib ib; |
962 | struct radeon_ib const_ib; | |
771fe6b9 | 963 | void *track; |
3ce0a23d | 964 | unsigned family; |
e70f224c | 965 | int parser_error; |
721604a1 JG |
966 | u32 cs_flags; |
967 | u32 ring; | |
968 | s32 priority; | |
771fe6b9 JG |
969 | }; |
970 | ||
513bcb46 | 971 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); |
ce580fab | 972 | extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); |
513bcb46 | 973 | |
771fe6b9 JG |
974 | struct radeon_cs_packet { |
975 | unsigned idx; | |
976 | unsigned type; | |
977 | unsigned reg; | |
978 | unsigned opcode; | |
979 | int count; | |
980 | unsigned one_reg_wr; | |
981 | }; | |
982 | ||
983 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, | |
984 | struct radeon_cs_packet *pkt, | |
985 | unsigned idx, unsigned reg); | |
986 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, | |
987 | struct radeon_cs_packet *pkt); | |
988 | ||
989 | ||
990 | /* | |
991 | * AGP | |
992 | */ | |
993 | int radeon_agp_init(struct radeon_device *rdev); | |
0ebf1717 | 994 | void radeon_agp_resume(struct radeon_device *rdev); |
10b06122 | 995 | void radeon_agp_suspend(struct radeon_device *rdev); |
771fe6b9 JG |
996 | void radeon_agp_fini(struct radeon_device *rdev); |
997 | ||
998 | ||
999 | /* | |
1000 | * Writeback | |
1001 | */ | |
1002 | struct radeon_wb { | |
4c788679 | 1003 | struct radeon_bo *wb_obj; |
771fe6b9 JG |
1004 | volatile uint32_t *wb; |
1005 | uint64_t gpu_addr; | |
724c80e1 | 1006 | bool enabled; |
d0f8a854 | 1007 | bool use_event; |
771fe6b9 JG |
1008 | }; |
1009 | ||
724c80e1 | 1010 | #define RADEON_WB_SCRATCH_OFFSET 0 |
89d35807 | 1011 | #define RADEON_WB_RING0_NEXT_RPTR 256 |
724c80e1 | 1012 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
0c88a02e AD |
1013 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
1014 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 | |
4d75658b | 1015 | #define R600_WB_DMA_RPTR_OFFSET 1792 |
724c80e1 | 1016 | #define R600_WB_IH_WPTR_OFFSET 2048 |
f60cbd11 | 1017 | #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 |
f2ba57b5 | 1018 | #define R600_WB_UVD_RPTR_OFFSET 2560 |
d0f8a854 | 1019 | #define R600_WB_EVENT_OFFSET 3072 |
963e81f9 AD |
1020 | #define CIK_WB_CP1_WPTR_OFFSET 3328 |
1021 | #define CIK_WB_CP2_WPTR_OFFSET 3584 | |
724c80e1 | 1022 | |
c93bb85b JG |
1023 | /** |
1024 | * struct radeon_pm - power management datas | |
1025 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) | |
1026 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) | |
1027 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) | |
1028 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) | |
1029 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) | |
1030 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) | |
1031 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) | |
1032 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) | |
1033 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) | |
25985edc | 1034 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
c93bb85b JG |
1035 | * @needed_bandwidth: current bandwidth needs |
1036 | * | |
1037 | * It keeps track of various data needed to take powermanagement decision. | |
25985edc | 1038 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
c93bb85b JG |
1039 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
1040 | * (type of memory, bus size, efficiency, ...) | |
1041 | */ | |
ce8f5370 AD |
1042 | |
1043 | enum radeon_pm_method { | |
1044 | PM_METHOD_PROFILE, | |
1045 | PM_METHOD_DYNPM, | |
1046 | }; | |
1047 | ||
1048 | enum radeon_dynpm_state { | |
1049 | DYNPM_STATE_DISABLED, | |
1050 | DYNPM_STATE_MINIMUM, | |
1051 | DYNPM_STATE_PAUSED, | |
3f53eb6f RW |
1052 | DYNPM_STATE_ACTIVE, |
1053 | DYNPM_STATE_SUSPENDED, | |
c913e23a | 1054 | }; |
ce8f5370 AD |
1055 | enum radeon_dynpm_action { |
1056 | DYNPM_ACTION_NONE, | |
1057 | DYNPM_ACTION_MINIMUM, | |
1058 | DYNPM_ACTION_DOWNCLOCK, | |
1059 | DYNPM_ACTION_UPCLOCK, | |
1060 | DYNPM_ACTION_DEFAULT | |
c913e23a | 1061 | }; |
56278a8e AD |
1062 | |
1063 | enum radeon_voltage_type { | |
1064 | VOLTAGE_NONE = 0, | |
1065 | VOLTAGE_GPIO, | |
1066 | VOLTAGE_VDDC, | |
1067 | VOLTAGE_SW | |
1068 | }; | |
1069 | ||
0ec0e74f AD |
1070 | enum radeon_pm_state_type { |
1071 | POWER_STATE_TYPE_DEFAULT, | |
1072 | POWER_STATE_TYPE_POWERSAVE, | |
1073 | POWER_STATE_TYPE_BATTERY, | |
1074 | POWER_STATE_TYPE_BALANCED, | |
1075 | POWER_STATE_TYPE_PERFORMANCE, | |
1076 | }; | |
1077 | ||
ce8f5370 AD |
1078 | enum radeon_pm_profile_type { |
1079 | PM_PROFILE_DEFAULT, | |
1080 | PM_PROFILE_AUTO, | |
1081 | PM_PROFILE_LOW, | |
c9e75b21 | 1082 | PM_PROFILE_MID, |
ce8f5370 AD |
1083 | PM_PROFILE_HIGH, |
1084 | }; | |
1085 | ||
1086 | #define PM_PROFILE_DEFAULT_IDX 0 | |
1087 | #define PM_PROFILE_LOW_SH_IDX 1 | |
c9e75b21 AD |
1088 | #define PM_PROFILE_MID_SH_IDX 2 |
1089 | #define PM_PROFILE_HIGH_SH_IDX 3 | |
1090 | #define PM_PROFILE_LOW_MH_IDX 4 | |
1091 | #define PM_PROFILE_MID_MH_IDX 5 | |
1092 | #define PM_PROFILE_HIGH_MH_IDX 6 | |
1093 | #define PM_PROFILE_MAX 7 | |
ce8f5370 AD |
1094 | |
1095 | struct radeon_pm_profile { | |
1096 | int dpms_off_ps_idx; | |
1097 | int dpms_on_ps_idx; | |
1098 | int dpms_off_cm_idx; | |
1099 | int dpms_on_cm_idx; | |
516d0e46 AD |
1100 | }; |
1101 | ||
21a8122a AD |
1102 | enum radeon_int_thermal_type { |
1103 | THERMAL_TYPE_NONE, | |
1104 | THERMAL_TYPE_RV6XX, | |
1105 | THERMAL_TYPE_RV770, | |
1106 | THERMAL_TYPE_EVERGREEN, | |
e33df25f | 1107 | THERMAL_TYPE_SUMO, |
4fddba1f | 1108 | THERMAL_TYPE_NI, |
14607d08 | 1109 | THERMAL_TYPE_SI, |
51150207 | 1110 | THERMAL_TYPE_CI, |
21a8122a AD |
1111 | }; |
1112 | ||
56278a8e AD |
1113 | struct radeon_voltage { |
1114 | enum radeon_voltage_type type; | |
1115 | /* gpio voltage */ | |
1116 | struct radeon_gpio_rec gpio; | |
1117 | u32 delay; /* delay in usec from voltage drop to sclk change */ | |
1118 | bool active_high; /* voltage drop is active when bit is high */ | |
1119 | /* VDDC voltage */ | |
1120 | u8 vddc_id; /* index into vddc voltage table */ | |
1121 | u8 vddci_id; /* index into vddci voltage table */ | |
1122 | bool vddci_enabled; | |
1123 | /* r6xx+ sw */ | |
2feea49a AD |
1124 | u16 voltage; |
1125 | /* evergreen+ vddci */ | |
1126 | u16 vddci; | |
56278a8e AD |
1127 | }; |
1128 | ||
d7311171 AD |
1129 | /* clock mode flags */ |
1130 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) | |
1131 | ||
56278a8e AD |
1132 | struct radeon_pm_clock_info { |
1133 | /* memory clock */ | |
1134 | u32 mclk; | |
1135 | /* engine clock */ | |
1136 | u32 sclk; | |
1137 | /* voltage info */ | |
1138 | struct radeon_voltage voltage; | |
d7311171 | 1139 | /* standardized clock flags */ |
56278a8e AD |
1140 | u32 flags; |
1141 | }; | |
1142 | ||
a48b9b4e | 1143 | /* state flags */ |
d7311171 | 1144 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
a48b9b4e | 1145 | |
56278a8e | 1146 | struct radeon_power_state { |
0ec0e74f | 1147 | enum radeon_pm_state_type type; |
8f3f1c9a | 1148 | struct radeon_pm_clock_info *clock_info; |
56278a8e AD |
1149 | /* number of valid clock modes in this power state */ |
1150 | int num_clock_modes; | |
56278a8e | 1151 | struct radeon_pm_clock_info *default_clock_mode; |
a48b9b4e AD |
1152 | /* standardized state flags */ |
1153 | u32 flags; | |
79daedc9 AD |
1154 | u32 misc; /* vbios specific flags */ |
1155 | u32 misc2; /* vbios specific flags */ | |
1156 | int pcie_lanes; /* pcie lanes */ | |
56278a8e AD |
1157 | }; |
1158 | ||
27459324 RM |
1159 | /* |
1160 | * Some modes are overclocked by very low value, accept them | |
1161 | */ | |
1162 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ | |
1163 | ||
c93bb85b | 1164 | struct radeon_pm { |
c913e23a | 1165 | struct mutex mutex; |
db7fce39 CK |
1166 | /* write locked while reprogramming mclk */ |
1167 | struct rw_semaphore mclk_lock; | |
a48b9b4e AD |
1168 | u32 active_crtcs; |
1169 | int active_crtc_count; | |
c913e23a | 1170 | int req_vblank; |
839461d3 | 1171 | bool vblank_sync; |
c93bb85b JG |
1172 | fixed20_12 max_bandwidth; |
1173 | fixed20_12 igp_sideport_mclk; | |
1174 | fixed20_12 igp_system_mclk; | |
1175 | fixed20_12 igp_ht_link_clk; | |
1176 | fixed20_12 igp_ht_link_width; | |
1177 | fixed20_12 k8_bandwidth; | |
1178 | fixed20_12 sideport_bandwidth; | |
1179 | fixed20_12 ht_bandwidth; | |
1180 | fixed20_12 core_bandwidth; | |
1181 | fixed20_12 sclk; | |
f47299c5 | 1182 | fixed20_12 mclk; |
c93bb85b | 1183 | fixed20_12 needed_bandwidth; |
0975b162 | 1184 | struct radeon_power_state *power_state; |
56278a8e AD |
1185 | /* number of valid power states */ |
1186 | int num_power_states; | |
a48b9b4e AD |
1187 | int current_power_state_index; |
1188 | int current_clock_mode_index; | |
1189 | int requested_power_state_index; | |
1190 | int requested_clock_mode_index; | |
1191 | int default_power_state_index; | |
1192 | u32 current_sclk; | |
1193 | u32 current_mclk; | |
2feea49a AD |
1194 | u16 current_vddc; |
1195 | u16 current_vddci; | |
9ace9f7b AD |
1196 | u32 default_sclk; |
1197 | u32 default_mclk; | |
2feea49a AD |
1198 | u16 default_vddc; |
1199 | u16 default_vddci; | |
29fb52ca | 1200 | struct radeon_i2c_chan *i2c_bus; |
ce8f5370 AD |
1201 | /* selected pm method */ |
1202 | enum radeon_pm_method pm_method; | |
1203 | /* dynpm power management */ | |
1204 | struct delayed_work dynpm_idle_work; | |
1205 | enum radeon_dynpm_state dynpm_state; | |
1206 | enum radeon_dynpm_action dynpm_planned_action; | |
1207 | unsigned long dynpm_action_timeout; | |
1208 | bool dynpm_can_upclock; | |
1209 | bool dynpm_can_downclock; | |
1210 | /* profile-based power management */ | |
1211 | enum radeon_pm_profile_type profile; | |
1212 | int profile_index; | |
1213 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; | |
21a8122a AD |
1214 | /* internal thermal controller on rv6xx+ */ |
1215 | enum radeon_int_thermal_type int_thermal_type; | |
1216 | struct device *int_hwmon_dev; | |
c93bb85b JG |
1217 | }; |
1218 | ||
a4c9e2ee AD |
1219 | int radeon_pm_get_type_index(struct radeon_device *rdev, |
1220 | enum radeon_pm_state_type ps_type, | |
1221 | int instance); | |
f2ba57b5 CK |
1222 | /* |
1223 | * UVD | |
1224 | */ | |
1225 | #define RADEON_MAX_UVD_HANDLES 10 | |
1226 | #define RADEON_UVD_STACK_SIZE (1024*1024) | |
1227 | #define RADEON_UVD_HEAP_SIZE (1024*1024) | |
1228 | ||
1229 | struct radeon_uvd { | |
1230 | struct radeon_bo *vcpu_bo; | |
1231 | void *cpu_addr; | |
1232 | uint64_t gpu_addr; | |
1233 | atomic_t handles[RADEON_MAX_UVD_HANDLES]; | |
1234 | struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; | |
55b51c88 | 1235 | struct delayed_work idle_work; |
f2ba57b5 CK |
1236 | }; |
1237 | ||
1238 | int radeon_uvd_init(struct radeon_device *rdev); | |
1239 | void radeon_uvd_fini(struct radeon_device *rdev); | |
1240 | int radeon_uvd_suspend(struct radeon_device *rdev); | |
1241 | int radeon_uvd_resume(struct radeon_device *rdev); | |
1242 | int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, | |
1243 | uint32_t handle, struct radeon_fence **fence); | |
1244 | int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, | |
1245 | uint32_t handle, struct radeon_fence **fence); | |
1246 | void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo); | |
1247 | void radeon_uvd_free_handles(struct radeon_device *rdev, | |
1248 | struct drm_file *filp); | |
1249 | int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); | |
55b51c88 | 1250 | void radeon_uvd_note_usage(struct radeon_device *rdev); |
facd112d CK |
1251 | int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, |
1252 | unsigned vclk, unsigned dclk, | |
1253 | unsigned vco_min, unsigned vco_max, | |
1254 | unsigned fb_factor, unsigned fb_mask, | |
1255 | unsigned pd_min, unsigned pd_max, | |
1256 | unsigned pd_even, | |
1257 | unsigned *optimal_fb_div, | |
1258 | unsigned *optimal_vclk_div, | |
1259 | unsigned *optimal_dclk_div); | |
1260 | int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, | |
1261 | unsigned cg_upll_func_cntl); | |
771fe6b9 | 1262 | |
a92553ab | 1263 | struct r600_audio { |
a92553ab RM |
1264 | int channels; |
1265 | int rate; | |
1266 | int bits_per_sample; | |
1267 | u8 status_bits; | |
1268 | u8 category_code; | |
1269 | }; | |
1270 | ||
771fe6b9 JG |
1271 | /* |
1272 | * Benchmarking | |
1273 | */ | |
638dd7db | 1274 | void radeon_benchmark(struct radeon_device *rdev, int test_number); |
771fe6b9 JG |
1275 | |
1276 | ||
ecc0b326 MD |
1277 | /* |
1278 | * Testing | |
1279 | */ | |
1280 | void radeon_test_moves(struct radeon_device *rdev); | |
60a7e396 | 1281 | void radeon_test_ring_sync(struct radeon_device *rdev, |
e32eb50d CK |
1282 | struct radeon_ring *cpA, |
1283 | struct radeon_ring *cpB); | |
60a7e396 | 1284 | void radeon_test_syncing(struct radeon_device *rdev); |
ecc0b326 MD |
1285 | |
1286 | ||
771fe6b9 JG |
1287 | /* |
1288 | * Debugfs | |
1289 | */ | |
4d8bf9ae CK |
1290 | struct radeon_debugfs { |
1291 | struct drm_info_list *files; | |
1292 | unsigned num_files; | |
1293 | }; | |
1294 | ||
771fe6b9 JG |
1295 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
1296 | struct drm_info_list *files, | |
1297 | unsigned nfiles); | |
1298 | int radeon_debugfs_fence_init(struct radeon_device *rdev); | |
771fe6b9 JG |
1299 | |
1300 | ||
1301 | /* | |
1302 | * ASIC specific functions. | |
1303 | */ | |
1304 | struct radeon_asic { | |
068a117c | 1305 | int (*init)(struct radeon_device *rdev); |
3ce0a23d JG |
1306 | void (*fini)(struct radeon_device *rdev); |
1307 | int (*resume)(struct radeon_device *rdev); | |
1308 | int (*suspend)(struct radeon_device *rdev); | |
28d52043 | 1309 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
a2d07b74 | 1310 | int (*asic_reset)(struct radeon_device *rdev); |
54e88e06 AD |
1311 | /* ioctl hw specific callback. Some hw might want to perform special |
1312 | * operation on specific ioctl. For instance on wait idle some hw | |
1313 | * might want to perform and HDP flush through MMIO as it seems that | |
1314 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed | |
1315 | * through ring. | |
1316 | */ | |
1317 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); | |
1318 | /* check if 3D engine is idle */ | |
1319 | bool (*gui_idle)(struct radeon_device *rdev); | |
1320 | /* wait for mc_idle */ | |
1321 | int (*mc_wait_for_idle)(struct radeon_device *rdev); | |
454d2e2a AD |
1322 | /* get the reference clock */ |
1323 | u32 (*get_xclk)(struct radeon_device *rdev); | |
d0418894 AD |
1324 | /* get the gpu clock counter */ |
1325 | uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); | |
54e88e06 | 1326 | /* gart */ |
c5b3b850 AD |
1327 | struct { |
1328 | void (*tlb_flush)(struct radeon_device *rdev); | |
1329 | int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); | |
1330 | } gart; | |
05b07147 CK |
1331 | struct { |
1332 | int (*init)(struct radeon_device *rdev); | |
1333 | void (*fini)(struct radeon_device *rdev); | |
2a6f1abb CK |
1334 | |
1335 | u32 pt_ring_index; | |
43f1214a AD |
1336 | void (*set_page)(struct radeon_device *rdev, |
1337 | struct radeon_ib *ib, | |
1338 | uint64_t pe, | |
dce34bfd CK |
1339 | uint64_t addr, unsigned count, |
1340 | uint32_t incr, uint32_t flags); | |
05b07147 | 1341 | } vm; |
54e88e06 | 1342 | /* ring specific callbacks */ |
4c87bc26 CK |
1343 | struct { |
1344 | void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); | |
721604a1 | 1345 | int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); |
4c87bc26 | 1346 | void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); |
e32eb50d | 1347 | void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, |
4c87bc26 | 1348 | struct radeon_semaphore *semaphore, bool emit_wait); |
eb0c19c5 | 1349 | int (*cs_parse)(struct radeon_cs_parser *p); |
f712812e AD |
1350 | void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); |
1351 | int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); | |
1352 | int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); | |
312c4a8c | 1353 | bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); |
498522b4 | 1354 | void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
f93bdefe AD |
1355 | |
1356 | u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); | |
1357 | u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); | |
1358 | void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); | |
4c87bc26 | 1359 | } ring[RADEON_NUM_RINGS]; |
54e88e06 | 1360 | /* irqs */ |
b35ea4ab AD |
1361 | struct { |
1362 | int (*set)(struct radeon_device *rdev); | |
1363 | int (*process)(struct radeon_device *rdev); | |
1364 | } irq; | |
54e88e06 | 1365 | /* displays */ |
c79a49ca AD |
1366 | struct { |
1367 | /* display watermarks */ | |
1368 | void (*bandwidth_update)(struct radeon_device *rdev); | |
1369 | /* get frame count */ | |
1370 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); | |
1371 | /* wait for vblank */ | |
1372 | void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); | |
37e9b6a6 AD |
1373 | /* set backlight level */ |
1374 | void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); | |
6d92f81d AD |
1375 | /* get backlight level */ |
1376 | u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); | |
a973bea1 AD |
1377 | /* audio callbacks */ |
1378 | void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); | |
1379 | void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); | |
c79a49ca | 1380 | } display; |
54e88e06 | 1381 | /* copy functions for bo handling */ |
27cd7769 AD |
1382 | struct { |
1383 | int (*blit)(struct radeon_device *rdev, | |
1384 | uint64_t src_offset, | |
1385 | uint64_t dst_offset, | |
1386 | unsigned num_gpu_pages, | |
876dc9f3 | 1387 | struct radeon_fence **fence); |
27cd7769 AD |
1388 | u32 blit_ring_index; |
1389 | int (*dma)(struct radeon_device *rdev, | |
1390 | uint64_t src_offset, | |
1391 | uint64_t dst_offset, | |
1392 | unsigned num_gpu_pages, | |
876dc9f3 | 1393 | struct radeon_fence **fence); |
27cd7769 AD |
1394 | u32 dma_ring_index; |
1395 | /* method used for bo copy */ | |
1396 | int (*copy)(struct radeon_device *rdev, | |
1397 | uint64_t src_offset, | |
1398 | uint64_t dst_offset, | |
1399 | unsigned num_gpu_pages, | |
876dc9f3 | 1400 | struct radeon_fence **fence); |
27cd7769 AD |
1401 | /* ring used for bo copies */ |
1402 | u32 copy_ring_index; | |
1403 | } copy; | |
54e88e06 | 1404 | /* surfaces */ |
9e6f3d02 AD |
1405 | struct { |
1406 | int (*set_reg)(struct radeon_device *rdev, int reg, | |
1407 | uint32_t tiling_flags, uint32_t pitch, | |
1408 | uint32_t offset, uint32_t obj_size); | |
1409 | void (*clear_reg)(struct radeon_device *rdev, int reg); | |
1410 | } surface; | |
54e88e06 | 1411 | /* hotplug detect */ |
901ea57d AD |
1412 | struct { |
1413 | void (*init)(struct radeon_device *rdev); | |
1414 | void (*fini)(struct radeon_device *rdev); | |
1415 | bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
1416 | void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); | |
1417 | } hpd; | |
ce8f5370 | 1418 | /* power management */ |
a02fa397 AD |
1419 | struct { |
1420 | void (*misc)(struct radeon_device *rdev); | |
1421 | void (*prepare)(struct radeon_device *rdev); | |
1422 | void (*finish)(struct radeon_device *rdev); | |
1423 | void (*init_profile)(struct radeon_device *rdev); | |
1424 | void (*get_dynpm_state)(struct radeon_device *rdev); | |
798bcf73 AD |
1425 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
1426 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); | |
1427 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); | |
1428 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); | |
1429 | int (*get_pcie_lanes)(struct radeon_device *rdev); | |
1430 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); | |
1431 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); | |
73afc70d | 1432 | int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); |
6bd1c385 | 1433 | int (*get_temperature)(struct radeon_device *rdev); |
a02fa397 | 1434 | } pm; |
6f34be50 | 1435 | /* pageflipping */ |
0f9e006c AD |
1436 | struct { |
1437 | void (*pre_page_flip)(struct radeon_device *rdev, int crtc); | |
1438 | u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); | |
1439 | void (*post_page_flip)(struct radeon_device *rdev, int crtc); | |
1440 | } pflip; | |
771fe6b9 JG |
1441 | }; |
1442 | ||
21f9a437 JG |
1443 | /* |
1444 | * Asic structures | |
1445 | */ | |
551ebd83 | 1446 | struct r100_asic { |
225758d8 JG |
1447 | const unsigned *reg_safe_bm; |
1448 | unsigned reg_safe_bm_size; | |
1449 | u32 hdp_cntl; | |
551ebd83 DA |
1450 | }; |
1451 | ||
21f9a437 | 1452 | struct r300_asic { |
225758d8 JG |
1453 | const unsigned *reg_safe_bm; |
1454 | unsigned reg_safe_bm_size; | |
1455 | u32 resync_scratch; | |
1456 | u32 hdp_cntl; | |
21f9a437 JG |
1457 | }; |
1458 | ||
1459 | struct r600_asic { | |
225758d8 JG |
1460 | unsigned max_pipes; |
1461 | unsigned max_tile_pipes; | |
1462 | unsigned max_simds; | |
1463 | unsigned max_backends; | |
1464 | unsigned max_gprs; | |
1465 | unsigned max_threads; | |
1466 | unsigned max_stack_entries; | |
1467 | unsigned max_hw_contexts; | |
1468 | unsigned max_gs_threads; | |
1469 | unsigned sx_max_export_size; | |
1470 | unsigned sx_max_export_pos_size; | |
1471 | unsigned sx_max_export_smx_size; | |
1472 | unsigned sq_num_cf_insts; | |
1473 | unsigned tiling_nbanks; | |
1474 | unsigned tiling_npipes; | |
1475 | unsigned tiling_group_size; | |
e7aeeba6 | 1476 | unsigned tile_config; |
e55b9422 | 1477 | unsigned backend_map; |
21f9a437 JG |
1478 | }; |
1479 | ||
1480 | struct rv770_asic { | |
225758d8 JG |
1481 | unsigned max_pipes; |
1482 | unsigned max_tile_pipes; | |
1483 | unsigned max_simds; | |
1484 | unsigned max_backends; | |
1485 | unsigned max_gprs; | |
1486 | unsigned max_threads; | |
1487 | unsigned max_stack_entries; | |
1488 | unsigned max_hw_contexts; | |
1489 | unsigned max_gs_threads; | |
1490 | unsigned sx_max_export_size; | |
1491 | unsigned sx_max_export_pos_size; | |
1492 | unsigned sx_max_export_smx_size; | |
1493 | unsigned sq_num_cf_insts; | |
1494 | unsigned sx_num_of_sets; | |
1495 | unsigned sc_prim_fifo_size; | |
1496 | unsigned sc_hiz_tile_fifo_size; | |
1497 | unsigned sc_earlyz_tile_fifo_fize; | |
1498 | unsigned tiling_nbanks; | |
1499 | unsigned tiling_npipes; | |
1500 | unsigned tiling_group_size; | |
e7aeeba6 | 1501 | unsigned tile_config; |
e55b9422 | 1502 | unsigned backend_map; |
21f9a437 JG |
1503 | }; |
1504 | ||
32fcdbf4 AD |
1505 | struct evergreen_asic { |
1506 | unsigned num_ses; | |
1507 | unsigned max_pipes; | |
1508 | unsigned max_tile_pipes; | |
1509 | unsigned max_simds; | |
1510 | unsigned max_backends; | |
1511 | unsigned max_gprs; | |
1512 | unsigned max_threads; | |
1513 | unsigned max_stack_entries; | |
1514 | unsigned max_hw_contexts; | |
1515 | unsigned max_gs_threads; | |
1516 | unsigned sx_max_export_size; | |
1517 | unsigned sx_max_export_pos_size; | |
1518 | unsigned sx_max_export_smx_size; | |
1519 | unsigned sq_num_cf_insts; | |
1520 | unsigned sx_num_of_sets; | |
1521 | unsigned sc_prim_fifo_size; | |
1522 | unsigned sc_hiz_tile_fifo_size; | |
1523 | unsigned sc_earlyz_tile_fifo_size; | |
1524 | unsigned tiling_nbanks; | |
1525 | unsigned tiling_npipes; | |
1526 | unsigned tiling_group_size; | |
e7aeeba6 | 1527 | unsigned tile_config; |
e55b9422 | 1528 | unsigned backend_map; |
32fcdbf4 AD |
1529 | }; |
1530 | ||
fecf1d07 AD |
1531 | struct cayman_asic { |
1532 | unsigned max_shader_engines; | |
1533 | unsigned max_pipes_per_simd; | |
1534 | unsigned max_tile_pipes; | |
1535 | unsigned max_simds_per_se; | |
1536 | unsigned max_backends_per_se; | |
1537 | unsigned max_texture_channel_caches; | |
1538 | unsigned max_gprs; | |
1539 | unsigned max_threads; | |
1540 | unsigned max_gs_threads; | |
1541 | unsigned max_stack_entries; | |
1542 | unsigned sx_num_of_sets; | |
1543 | unsigned sx_max_export_size; | |
1544 | unsigned sx_max_export_pos_size; | |
1545 | unsigned sx_max_export_smx_size; | |
1546 | unsigned max_hw_contexts; | |
1547 | unsigned sq_num_cf_insts; | |
1548 | unsigned sc_prim_fifo_size; | |
1549 | unsigned sc_hiz_tile_fifo_size; | |
1550 | unsigned sc_earlyz_tile_fifo_size; | |
1551 | ||
1552 | unsigned num_shader_engines; | |
1553 | unsigned num_shader_pipes_per_simd; | |
1554 | unsigned num_tile_pipes; | |
1555 | unsigned num_simds_per_se; | |
1556 | unsigned num_backends_per_se; | |
1557 | unsigned backend_disable_mask_per_asic; | |
1558 | unsigned backend_map; | |
1559 | unsigned num_texture_channel_caches; | |
1560 | unsigned mem_max_burst_length_bytes; | |
1561 | unsigned mem_row_size_in_kb; | |
1562 | unsigned shader_engine_tile_size; | |
1563 | unsigned num_gpus; | |
1564 | unsigned multi_gpu_tile_size; | |
1565 | ||
1566 | unsigned tile_config; | |
fecf1d07 AD |
1567 | }; |
1568 | ||
0a96d72b AD |
1569 | struct si_asic { |
1570 | unsigned max_shader_engines; | |
0a96d72b | 1571 | unsigned max_tile_pipes; |
1a8ca750 AD |
1572 | unsigned max_cu_per_sh; |
1573 | unsigned max_sh_per_se; | |
0a96d72b AD |
1574 | unsigned max_backends_per_se; |
1575 | unsigned max_texture_channel_caches; | |
1576 | unsigned max_gprs; | |
1577 | unsigned max_gs_threads; | |
1578 | unsigned max_hw_contexts; | |
1579 | unsigned sc_prim_fifo_size_frontend; | |
1580 | unsigned sc_prim_fifo_size_backend; | |
1581 | unsigned sc_hiz_tile_fifo_size; | |
1582 | unsigned sc_earlyz_tile_fifo_size; | |
1583 | ||
0a96d72b AD |
1584 | unsigned num_tile_pipes; |
1585 | unsigned num_backends_per_se; | |
1586 | unsigned backend_disable_mask_per_asic; | |
1587 | unsigned backend_map; | |
1588 | unsigned num_texture_channel_caches; | |
1589 | unsigned mem_max_burst_length_bytes; | |
1590 | unsigned mem_row_size_in_kb; | |
1591 | unsigned shader_engine_tile_size; | |
1592 | unsigned num_gpus; | |
1593 | unsigned multi_gpu_tile_size; | |
1594 | ||
1595 | unsigned tile_config; | |
64d7b8be | 1596 | uint32_t tile_mode_array[32]; |
0a96d72b AD |
1597 | }; |
1598 | ||
8cc1a532 AD |
1599 | struct cik_asic { |
1600 | unsigned max_shader_engines; | |
1601 | unsigned max_tile_pipes; | |
1602 | unsigned max_cu_per_sh; | |
1603 | unsigned max_sh_per_se; | |
1604 | unsigned max_backends_per_se; | |
1605 | unsigned max_texture_channel_caches; | |
1606 | unsigned max_gprs; | |
1607 | unsigned max_gs_threads; | |
1608 | unsigned max_hw_contexts; | |
1609 | unsigned sc_prim_fifo_size_frontend; | |
1610 | unsigned sc_prim_fifo_size_backend; | |
1611 | unsigned sc_hiz_tile_fifo_size; | |
1612 | unsigned sc_earlyz_tile_fifo_size; | |
1613 | ||
1614 | unsigned num_tile_pipes; | |
1615 | unsigned num_backends_per_se; | |
1616 | unsigned backend_disable_mask_per_asic; | |
1617 | unsigned backend_map; | |
1618 | unsigned num_texture_channel_caches; | |
1619 | unsigned mem_max_burst_length_bytes; | |
1620 | unsigned mem_row_size_in_kb; | |
1621 | unsigned shader_engine_tile_size; | |
1622 | unsigned num_gpus; | |
1623 | unsigned multi_gpu_tile_size; | |
1624 | ||
1625 | unsigned tile_config; | |
39aee490 | 1626 | uint32_t tile_mode_array[32]; |
8cc1a532 AD |
1627 | }; |
1628 | ||
068a117c JG |
1629 | union radeon_asic_config { |
1630 | struct r300_asic r300; | |
551ebd83 | 1631 | struct r100_asic r100; |
3ce0a23d JG |
1632 | struct r600_asic r600; |
1633 | struct rv770_asic rv770; | |
32fcdbf4 | 1634 | struct evergreen_asic evergreen; |
fecf1d07 | 1635 | struct cayman_asic cayman; |
0a96d72b | 1636 | struct si_asic si; |
8cc1a532 | 1637 | struct cik_asic cik; |
068a117c JG |
1638 | }; |
1639 | ||
0a10c851 DV |
1640 | /* |
1641 | * asic initizalization from radeon_asic.c | |
1642 | */ | |
1643 | void radeon_agp_disable(struct radeon_device *rdev); | |
1644 | int radeon_asic_init(struct radeon_device *rdev); | |
1645 | ||
771fe6b9 JG |
1646 | |
1647 | /* | |
1648 | * IOCTL. | |
1649 | */ | |
1650 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, | |
1651 | struct drm_file *filp); | |
1652 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, | |
1653 | struct drm_file *filp); | |
1654 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, | |
1655 | struct drm_file *file_priv); | |
1656 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1657 | struct drm_file *file_priv); | |
1658 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1659 | struct drm_file *file_priv); | |
1660 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1661 | struct drm_file *file_priv); | |
1662 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
1663 | struct drm_file *filp); | |
1664 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1665 | struct drm_file *filp); | |
1666 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1667 | struct drm_file *filp); | |
1668 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
1669 | struct drm_file *filp); | |
721604a1 JG |
1670 | int radeon_gem_va_ioctl(struct drm_device *dev, void *data, |
1671 | struct drm_file *filp); | |
771fe6b9 | 1672 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
e024e110 DA |
1673 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
1674 | struct drm_file *filp); | |
1675 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | |
1676 | struct drm_file *filp); | |
771fe6b9 | 1677 | |
16cdf04d AD |
1678 | /* VRAM scratch page for HDP bug, default vram page */ |
1679 | struct r600_vram_scratch { | |
87cbf8f2 AD |
1680 | struct radeon_bo *robj; |
1681 | volatile uint32_t *ptr; | |
16cdf04d | 1682 | u64 gpu_addr; |
87cbf8f2 | 1683 | }; |
771fe6b9 | 1684 | |
fd64ca8a LT |
1685 | /* |
1686 | * ACPI | |
1687 | */ | |
1688 | struct radeon_atif_notification_cfg { | |
1689 | bool enabled; | |
1690 | int command_code; | |
1691 | }; | |
1692 | ||
1693 | struct radeon_atif_notifications { | |
1694 | bool display_switch; | |
1695 | bool expansion_mode_change; | |
1696 | bool thermal_state; | |
1697 | bool forced_power_state; | |
1698 | bool system_power_state; | |
1699 | bool display_conf_change; | |
1700 | bool px_gfx_switch; | |
1701 | bool brightness_change; | |
1702 | bool dgpu_display_event; | |
1703 | }; | |
1704 | ||
1705 | struct radeon_atif_functions { | |
1706 | bool system_params; | |
1707 | bool sbios_requests; | |
1708 | bool select_active_disp; | |
1709 | bool lid_state; | |
1710 | bool get_tv_standard; | |
1711 | bool set_tv_standard; | |
1712 | bool get_panel_expansion_mode; | |
1713 | bool set_panel_expansion_mode; | |
1714 | bool temperature_change; | |
1715 | bool graphics_device_types; | |
1716 | }; | |
1717 | ||
1718 | struct radeon_atif { | |
1719 | struct radeon_atif_notifications notifications; | |
1720 | struct radeon_atif_functions functions; | |
1721 | struct radeon_atif_notification_cfg notification_cfg; | |
37e9b6a6 | 1722 | struct radeon_encoder *encoder_for_bl; |
fd64ca8a | 1723 | }; |
7a1619b9 | 1724 | |
e3a15920 AD |
1725 | struct radeon_atcs_functions { |
1726 | bool get_ext_state; | |
1727 | bool pcie_perf_req; | |
1728 | bool pcie_dev_rdy; | |
1729 | bool pcie_bus_width; | |
1730 | }; | |
1731 | ||
1732 | struct radeon_atcs { | |
1733 | struct radeon_atcs_functions functions; | |
1734 | }; | |
1735 | ||
771fe6b9 JG |
1736 | /* |
1737 | * Core structure, functions and helpers. | |
1738 | */ | |
1739 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); | |
1740 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); | |
1741 | ||
1742 | struct radeon_device { | |
9f022ddf | 1743 | struct device *dev; |
771fe6b9 JG |
1744 | struct drm_device *ddev; |
1745 | struct pci_dev *pdev; | |
dee53e7f | 1746 | struct rw_semaphore exclusive_lock; |
771fe6b9 | 1747 | /* ASIC */ |
068a117c | 1748 | union radeon_asic_config config; |
771fe6b9 JG |
1749 | enum radeon_family family; |
1750 | unsigned long flags; | |
1751 | int usec_timeout; | |
1752 | enum radeon_pll_errata pll_errata; | |
1753 | int num_gb_pipes; | |
f779b3e5 | 1754 | int num_z_pipes; |
771fe6b9 JG |
1755 | int disp_priority; |
1756 | /* BIOS */ | |
1757 | uint8_t *bios; | |
1758 | bool is_atom_bios; | |
1759 | uint16_t bios_header_start; | |
4c788679 | 1760 | struct radeon_bo *stollen_vga_memory; |
771fe6b9 | 1761 | /* Register mmio */ |
4c9bc75c DA |
1762 | resource_size_t rmmio_base; |
1763 | resource_size_t rmmio_size; | |
2c385151 DV |
1764 | /* protects concurrent MM_INDEX/DATA based register access */ |
1765 | spinlock_t mmio_idx_lock; | |
a0533fbf | 1766 | void __iomem *rmmio; |
771fe6b9 JG |
1767 | radeon_rreg_t mc_rreg; |
1768 | radeon_wreg_t mc_wreg; | |
1769 | radeon_rreg_t pll_rreg; | |
1770 | radeon_wreg_t pll_wreg; | |
de1b2898 | 1771 | uint32_t pcie_reg_mask; |
771fe6b9 JG |
1772 | radeon_rreg_t pciep_rreg; |
1773 | radeon_wreg_t pciep_wreg; | |
351a52a2 AD |
1774 | /* io port */ |
1775 | void __iomem *rio_mem; | |
1776 | resource_size_t rio_mem_size; | |
771fe6b9 JG |
1777 | struct radeon_clock clock; |
1778 | struct radeon_mc mc; | |
1779 | struct radeon_gart gart; | |
1780 | struct radeon_mode_info mode_info; | |
1781 | struct radeon_scratch scratch; | |
75efdee1 | 1782 | struct radeon_doorbell doorbell; |
771fe6b9 | 1783 | struct radeon_mman mman; |
7465280c | 1784 | struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; |
0085c950 | 1785 | wait_queue_head_t fence_queue; |
d6999bc7 | 1786 | struct mutex ring_lock; |
e32eb50d | 1787 | struct radeon_ring ring[RADEON_NUM_RINGS]; |
c507f7ef JG |
1788 | bool ib_pool_ready; |
1789 | struct radeon_sa_manager ring_tmp_bo; | |
771fe6b9 JG |
1790 | struct radeon_irq irq; |
1791 | struct radeon_asic *asic; | |
1792 | struct radeon_gem gem; | |
c93bb85b | 1793 | struct radeon_pm pm; |
f2ba57b5 | 1794 | struct radeon_uvd uvd; |
f657c2a7 | 1795 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
771fe6b9 | 1796 | struct radeon_wb wb; |
3ce0a23d | 1797 | struct radeon_dummy_page dummy_page; |
771fe6b9 JG |
1798 | bool shutdown; |
1799 | bool suspend; | |
ad49f501 | 1800 | bool need_dma32; |
733289c2 | 1801 | bool accel_working; |
a0a53aa8 | 1802 | bool fastfb_working; /* IGP feature*/ |
e024e110 | 1803 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
3ce0a23d JG |
1804 | const struct firmware *me_fw; /* all family ME firmware */ |
1805 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ | |
d8f60cfc | 1806 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
0af62b01 | 1807 | const struct firmware *mc_fw; /* NI MC firmware */ |
0f0de06c | 1808 | const struct firmware *ce_fw; /* SI CE firmware */ |
f2ba57b5 | 1809 | const struct firmware *uvd_fw; /* UVD firmware */ |
02c81327 | 1810 | const struct firmware *mec_fw; /* CIK MEC firmware */ |
21a93e13 | 1811 | const struct firmware *sdma_fw; /* CIK SDMA firmware */ |
3ce0a23d | 1812 | struct r600_blit r600_blit; |
16cdf04d | 1813 | struct r600_vram_scratch vram_scratch; |
3e5cb98d | 1814 | int msi_enabled; /* msi enabled */ |
d8f60cfc | 1815 | struct r600_ih ih; /* r6/700 interrupt ring */ |
2948f5e6 | 1816 | struct radeon_rlc rlc; |
963e81f9 | 1817 | struct radeon_mec mec; |
d4877cf2 | 1818 | struct work_struct hotplug_work; |
f122c610 | 1819 | struct work_struct audio_work; |
8f61b34c | 1820 | struct work_struct reset_work; |
18917b60 | 1821 | int num_crtc; /* number of crtcs */ |
40bacf16 | 1822 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
3299de95 | 1823 | bool audio_enabled; |
948bee3f | 1824 | bool has_uvd; |
3299de95 | 1825 | struct r600_audio audio_status; /* audio stuff */ |
ce8f5370 | 1826 | struct notifier_block acpi_nb; |
9eba4a93 | 1827 | /* only one userspace can use Hyperz features or CMASK at a time */ |
ab9e1f59 | 1828 | struct drm_file *hyperz_filp; |
9eba4a93 | 1829 | struct drm_file *cmask_filp; |
f376b94f AD |
1830 | /* i2c buses */ |
1831 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; | |
4d8bf9ae CK |
1832 | /* debugfs */ |
1833 | struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; | |
1834 | unsigned debugfs_count; | |
721604a1 JG |
1835 | /* virtual memory */ |
1836 | struct radeon_vm_manager vm_manager; | |
6759a0a7 | 1837 | struct mutex gpu_clock_mutex; |
fd64ca8a LT |
1838 | /* ACPI interface */ |
1839 | struct radeon_atif atif; | |
e3a15920 | 1840 | struct radeon_atcs atcs; |
771fe6b9 JG |
1841 | }; |
1842 | ||
1843 | int radeon_device_init(struct radeon_device *rdev, | |
1844 | struct drm_device *ddev, | |
1845 | struct pci_dev *pdev, | |
1846 | uint32_t flags); | |
1847 | void radeon_device_fini(struct radeon_device *rdev); | |
1848 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); | |
1849 | ||
2ef9bdfe DV |
1850 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, |
1851 | bool always_indirect); | |
1852 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, | |
1853 | bool always_indirect); | |
6fcbef7a AK |
1854 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); |
1855 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); | |
351a52a2 | 1856 | |
75efdee1 AD |
1857 | u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset); |
1858 | void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v); | |
1859 | ||
4c788679 JG |
1860 | /* |
1861 | * Cast helper | |
1862 | */ | |
1863 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) | |
771fe6b9 JG |
1864 | |
1865 | /* | |
1866 | * Registers read & write functions. | |
1867 | */ | |
a0533fbf BH |
1868 | #define RREG8(reg) readb((rdev->rmmio) + (reg)) |
1869 | #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) | |
1870 | #define RREG16(reg) readw((rdev->rmmio) + (reg)) | |
1871 | #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) | |
2ef9bdfe DV |
1872 | #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) |
1873 | #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) | |
1874 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) | |
1875 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) | |
1876 | #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) | |
771fe6b9 JG |
1877 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1878 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) | |
1879 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) | |
1880 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) | |
1881 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) | |
1882 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) | |
de1b2898 DA |
1883 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
1884 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) | |
492d2b61 AD |
1885 | #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) |
1886 | #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) | |
1d5d0c34 AD |
1887 | #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) |
1888 | #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) | |
ff82bbc4 AD |
1889 | #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) |
1890 | #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) | |
46f9564a AD |
1891 | #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) |
1892 | #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) | |
771fe6b9 JG |
1893 | #define WREG32_P(reg, val, mask) \ |
1894 | do { \ | |
1895 | uint32_t tmp_ = RREG32(reg); \ | |
1896 | tmp_ &= (mask); \ | |
1897 | tmp_ |= ((val) & ~(mask)); \ | |
1898 | WREG32(reg, tmp_); \ | |
1899 | } while (0) | |
d5169fc4 RM |
1900 | #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) |
1901 | #define WREG32_OR(reg, or) WREG32_P(reg, or, ~or) | |
771fe6b9 JG |
1902 | #define WREG32_PLL_P(reg, val, mask) \ |
1903 | do { \ | |
1904 | uint32_t tmp_ = RREG32_PLL(reg); \ | |
1905 | tmp_ &= (mask); \ | |
1906 | tmp_ |= ((val) & ~(mask)); \ | |
1907 | WREG32_PLL(reg, tmp_); \ | |
1908 | } while (0) | |
2ef9bdfe | 1909 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) |
351a52a2 AD |
1910 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
1911 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) | |
771fe6b9 | 1912 | |
75efdee1 AD |
1913 | #define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset)) |
1914 | #define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v)) | |
1915 | ||
de1b2898 DA |
1916 | /* |
1917 | * Indirect registers accessor | |
1918 | */ | |
1919 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) | |
1920 | { | |
1921 | uint32_t r; | |
1922 | ||
1923 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
1924 | r = RREG32(RADEON_PCIE_DATA); | |
1925 | return r; | |
1926 | } | |
1927 | ||
1928 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) | |
1929 | { | |
1930 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); | |
1931 | WREG32(RADEON_PCIE_DATA, (v)); | |
1932 | } | |
1933 | ||
1d5d0c34 AD |
1934 | static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) |
1935 | { | |
1936 | u32 r; | |
1937 | ||
1938 | WREG32(TN_SMC_IND_INDEX_0, (reg)); | |
1939 | r = RREG32(TN_SMC_IND_DATA_0); | |
1940 | return r; | |
1941 | } | |
1942 | ||
1943 | static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
1944 | { | |
1945 | WREG32(TN_SMC_IND_INDEX_0, (reg)); | |
1946 | WREG32(TN_SMC_IND_DATA_0, (v)); | |
1947 | } | |
1948 | ||
ff82bbc4 AD |
1949 | static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) |
1950 | { | |
1951 | u32 r; | |
1952 | ||
1953 | WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); | |
1954 | r = RREG32(R600_RCU_DATA); | |
1955 | return r; | |
1956 | } | |
1957 | ||
1958 | static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
1959 | { | |
1960 | WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); | |
1961 | WREG32(R600_RCU_DATA, (v)); | |
1962 | } | |
1963 | ||
46f9564a AD |
1964 | static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) |
1965 | { | |
1966 | u32 r; | |
1967 | ||
1968 | WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); | |
1969 | r = RREG32(EVERGREEN_CG_IND_DATA); | |
1970 | return r; | |
1971 | } | |
1972 | ||
1973 | static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) | |
1974 | { | |
1975 | WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); | |
1976 | WREG32(EVERGREEN_CG_IND_DATA, (v)); | |
1977 | } | |
1978 | ||
771fe6b9 JG |
1979 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
1980 | ||
1981 | ||
1982 | /* | |
1983 | * ASICs helpers. | |
1984 | */ | |
b995e433 DA |
1985 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
1986 | (rdev->pdev->device == 0x5969)) | |
771fe6b9 JG |
1987 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
1988 | (rdev->family == CHIP_RV200) || \ | |
1989 | (rdev->family == CHIP_RS100) || \ | |
1990 | (rdev->family == CHIP_RS200) || \ | |
1991 | (rdev->family == CHIP_RV250) || \ | |
1992 | (rdev->family == CHIP_RV280) || \ | |
1993 | (rdev->family == CHIP_RS300)) | |
1994 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ | |
1995 | (rdev->family == CHIP_RV350) || \ | |
1996 | (rdev->family == CHIP_R350) || \ | |
1997 | (rdev->family == CHIP_RV380) || \ | |
1998 | (rdev->family == CHIP_R420) || \ | |
1999 | (rdev->family == CHIP_R423) || \ | |
2000 | (rdev->family == CHIP_RV410) || \ | |
2001 | (rdev->family == CHIP_RS400) || \ | |
2002 | (rdev->family == CHIP_RS480)) | |
3313e3d4 AD |
2003 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
2004 | (rdev->ddev->pdev->device == 0x9443) || \ | |
2005 | (rdev->ddev->pdev->device == 0x944B) || \ | |
2006 | (rdev->ddev->pdev->device == 0x9506) || \ | |
2007 | (rdev->ddev->pdev->device == 0x9509) || \ | |
2008 | (rdev->ddev->pdev->device == 0x950F) || \ | |
2009 | (rdev->ddev->pdev->device == 0x689C) || \ | |
2010 | (rdev->ddev->pdev->device == 0x689D)) | |
771fe6b9 | 2011 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
99999aaa AD |
2012 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
2013 | (rdev->family == CHIP_RS690) || \ | |
2014 | (rdev->family == CHIP_RS740) || \ | |
2015 | (rdev->family >= CHIP_R600)) | |
771fe6b9 JG |
2016 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
2017 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) | |
bcc1c2a1 | 2018 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
633b9164 AD |
2019 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
2020 | (rdev->flags & RADEON_IS_IGP)) | |
1fe18305 | 2021 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
8848f759 AD |
2022 | #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) |
2023 | #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ | |
2024 | (rdev->flags & RADEON_IS_IGP)) | |
624d3524 | 2025 | #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) |
b5d9d726 | 2026 | #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) |
e282917c | 2027 | #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) |
771fe6b9 JG |
2028 | |
2029 | /* | |
2030 | * BIOS helpers. | |
2031 | */ | |
2032 | #define RBIOS8(i) (rdev->bios[i]) | |
2033 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) | |
2034 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) | |
2035 | ||
2036 | int radeon_combios_init(struct radeon_device *rdev); | |
2037 | void radeon_combios_fini(struct radeon_device *rdev); | |
2038 | int radeon_atombios_init(struct radeon_device *rdev); | |
2039 | void radeon_atombios_fini(struct radeon_device *rdev); | |
2040 | ||
2041 | ||
2042 | /* | |
2043 | * RING helpers. | |
2044 | */ | |
ce580fab | 2045 | #if DRM_DEBUG_CODE == 0 |
e32eb50d | 2046 | static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
771fe6b9 | 2047 | { |
e32eb50d CK |
2048 | ring->ring[ring->wptr++] = v; |
2049 | ring->wptr &= ring->ptr_mask; | |
2050 | ring->count_dw--; | |
2051 | ring->ring_free_dw--; | |
771fe6b9 | 2052 | } |
ce580fab AK |
2053 | #else |
2054 | /* With debugging this is just too big to inline */ | |
e32eb50d | 2055 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v); |
ce580fab | 2056 | #endif |
771fe6b9 JG |
2057 | |
2058 | /* | |
2059 | * ASICs macro. | |
2060 | */ | |
068a117c | 2061 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
3ce0a23d JG |
2062 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
2063 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) | |
2064 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) | |
eb0c19c5 | 2065 | #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p)) |
28d52043 | 2066 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
a2d07b74 | 2067 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
c5b3b850 AD |
2068 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) |
2069 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) | |
05b07147 CK |
2070 | #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) |
2071 | #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) | |
43f1214a | 2072 | #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags))) |
f712812e AD |
2073 | #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) |
2074 | #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) | |
2075 | #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) | |
4c87bc26 | 2076 | #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) |
721604a1 | 2077 | #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) |
312c4a8c | 2078 | #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) |
498522b4 | 2079 | #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm)) |
f93bdefe AD |
2080 | #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_rptr((rdev), (r)) |
2081 | #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].get_wptr((rdev), (r)) | |
2082 | #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx].set_wptr((rdev), (r)) | |
b35ea4ab AD |
2083 | #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) |
2084 | #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) | |
c79a49ca | 2085 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) |
37e9b6a6 | 2086 | #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) |
6d92f81d | 2087 | #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) |
a973bea1 AD |
2088 | #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) |
2089 | #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) | |
4c87bc26 CK |
2090 | #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) |
2091 | #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) | |
27cd7769 AD |
2092 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) |
2093 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) | |
2094 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) | |
2095 | #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index | |
2096 | #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index | |
2097 | #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index | |
798bcf73 AD |
2098 | #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) |
2099 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) | |
2100 | #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) | |
2101 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) | |
2102 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) | |
2103 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) | |
2104 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) | |
73afc70d | 2105 | #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) |
6bd1c385 | 2106 | #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) |
9e6f3d02 AD |
2107 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) |
2108 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) | |
c79a49ca | 2109 | #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) |
901ea57d AD |
2110 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) |
2111 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) | |
2112 | #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) | |
2113 | #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) | |
def9ba9c | 2114 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
a02fa397 AD |
2115 | #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) |
2116 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) | |
2117 | #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) | |
2118 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) | |
2119 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) | |
69b62ad8 AD |
2120 | #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc)) |
2121 | #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) | |
2122 | #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) | |
2123 | #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) | |
2124 | #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) | |
454d2e2a | 2125 | #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) |
d0418894 | 2126 | #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) |
771fe6b9 | 2127 | |
6cf8a3f5 | 2128 | /* Common functions */ |
700a0cc0 | 2129 | /* AGP */ |
90aca4d2 | 2130 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
410a3418 | 2131 | extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); |
700a0cc0 | 2132 | extern void radeon_agp_disable(struct radeon_device *rdev); |
21f9a437 JG |
2133 | extern int radeon_modeset_init(struct radeon_device *rdev); |
2134 | extern void radeon_modeset_fini(struct radeon_device *rdev); | |
9f022ddf | 2135 | extern bool radeon_card_posted(struct radeon_device *rdev); |
f47299c5 | 2136 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
f46c0120 | 2137 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
72542d77 | 2138 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
21f9a437 | 2139 | extern void radeon_scratch_init(struct radeon_device *rdev); |
724c80e1 AD |
2140 | extern void radeon_wb_fini(struct radeon_device *rdev); |
2141 | extern int radeon_wb_init(struct radeon_device *rdev); | |
2142 | extern void radeon_wb_disable(struct radeon_device *rdev); | |
21f9a437 JG |
2143 | extern void radeon_surface_init(struct radeon_device *rdev); |
2144 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); | |
ca6ffc64 | 2145 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
d39c3b89 | 2146 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
312ea8da | 2147 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
d03d8589 | 2148 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
d594e46a JG |
2149 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
2150 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); | |
6a9ee8af DA |
2151 | extern int radeon_resume_kms(struct drm_device *dev); |
2152 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); | |
53595338 | 2153 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
2e1b65f9 AD |
2154 | extern void radeon_program_register_sequence(struct radeon_device *rdev, |
2155 | const u32 *registers, | |
2156 | const u32 array_size); | |
6cf8a3f5 | 2157 | |
721604a1 JG |
2158 | /* |
2159 | * vm | |
2160 | */ | |
2161 | int radeon_vm_manager_init(struct radeon_device *rdev); | |
2162 | void radeon_vm_manager_fini(struct radeon_device *rdev); | |
d72d43cf | 2163 | void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); |
721604a1 | 2164 | void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); |
ddf03f5c | 2165 | int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm); |
13e55c38 | 2166 | void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm); |
ee60e29f CK |
2167 | struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, |
2168 | struct radeon_vm *vm, int ring); | |
2169 | void radeon_vm_fence(struct radeon_device *rdev, | |
2170 | struct radeon_vm *vm, | |
2171 | struct radeon_fence *fence); | |
dce34bfd | 2172 | uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); |
721604a1 JG |
2173 | int radeon_vm_bo_update_pte(struct radeon_device *rdev, |
2174 | struct radeon_vm *vm, | |
2175 | struct radeon_bo *bo, | |
2176 | struct ttm_mem_reg *mem); | |
2177 | void radeon_vm_bo_invalidate(struct radeon_device *rdev, | |
2178 | struct radeon_bo *bo); | |
421ca7ab CK |
2179 | struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, |
2180 | struct radeon_bo *bo); | |
e971bd5e CK |
2181 | struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, |
2182 | struct radeon_vm *vm, | |
2183 | struct radeon_bo *bo); | |
2184 | int radeon_vm_bo_set_addr(struct radeon_device *rdev, | |
2185 | struct radeon_bo_va *bo_va, | |
2186 | uint64_t offset, | |
2187 | uint32_t flags); | |
721604a1 | 2188 | int radeon_vm_bo_rmv(struct radeon_device *rdev, |
e971bd5e | 2189 | struct radeon_bo_va *bo_va); |
721604a1 | 2190 | |
f122c610 AD |
2191 | /* audio */ |
2192 | void r600_audio_update_hdmi(struct work_struct *work); | |
721604a1 | 2193 | |
16cdf04d AD |
2194 | /* |
2195 | * R600 vram scratch functions | |
2196 | */ | |
2197 | int r600_vram_scratch_init(struct radeon_device *rdev); | |
2198 | void r600_vram_scratch_fini(struct radeon_device *rdev); | |
2199 | ||
285484e2 JG |
2200 | /* |
2201 | * r600 cs checking helper | |
2202 | */ | |
2203 | unsigned r600_mip_minify(unsigned size, unsigned level); | |
2204 | bool r600_fmt_is_valid_color(u32 format); | |
2205 | bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); | |
2206 | int r600_fmt_get_blocksize(u32 format); | |
2207 | int r600_fmt_get_nblocksx(u32 format, u32 w); | |
2208 | int r600_fmt_get_nblocksy(u32 format, u32 h); | |
2209 | ||
3574dda4 DV |
2210 | /* |
2211 | * r600 functions used by radeon_encoder.c | |
2212 | */ | |
1b688d08 RM |
2213 | struct radeon_hdmi_acr { |
2214 | u32 clock; | |
2215 | ||
2216 | int n_32khz; | |
2217 | int cts_32khz; | |
2218 | ||
2219 | int n_44_1khz; | |
2220 | int cts_44_1khz; | |
2221 | ||
2222 | int n_48khz; | |
2223 | int cts_48khz; | |
2224 | ||
2225 | }; | |
2226 | ||
e55d3e6c RM |
2227 | extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); |
2228 | ||
416a2bd2 AD |
2229 | extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, |
2230 | u32 tiling_pipe_num, | |
2231 | u32 max_rb_num, | |
2232 | u32 total_max_rb_num, | |
2233 | u32 enabled_rb_mask); | |
fe251e2f | 2234 | |
e55d3e6c RM |
2235 | /* |
2236 | * evergreen functions used by radeon_encoder.c | |
2237 | */ | |
2238 | ||
0af62b01 | 2239 | extern int ni_init_microcode(struct radeon_device *rdev); |
755d819e | 2240 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
0af62b01 | 2241 | |
c4917074 AD |
2242 | /* radeon_acpi.c */ |
2243 | #if defined(CONFIG_ACPI) | |
2244 | extern int radeon_acpi_init(struct radeon_device *rdev); | |
2245 | extern void radeon_acpi_fini(struct radeon_device *rdev); | |
2246 | #else | |
2247 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } | |
2248 | static inline void radeon_acpi_fini(struct radeon_device *rdev) { } | |
2249 | #endif | |
d7a2952f | 2250 | |
c38f34b5 IH |
2251 | int radeon_cs_packet_parse(struct radeon_cs_parser *p, |
2252 | struct radeon_cs_packet *pkt, | |
2253 | unsigned idx); | |
9ffb7a6d | 2254 | bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); |
c3ad63af IH |
2255 | void radeon_cs_dump_packet(struct radeon_cs_parser *p, |
2256 | struct radeon_cs_packet *pkt); | |
e9716993 IH |
2257 | int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, |
2258 | struct radeon_cs_reloc **cs_reloc, | |
2259 | int nomm); | |
40592a17 IH |
2260 | int r600_cs_common_vline_parse(struct radeon_cs_parser *p, |
2261 | uint32_t *vline_start_end, | |
2262 | uint32_t *vline_status); | |
c38f34b5 | 2263 | |
4c788679 JG |
2264 | #include "radeon_object.h" |
2265 | ||
771fe6b9 | 2266 | #endif |