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drm/radeon: remove radeon_bo_clear_va
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
a18cee15 96extern int radeon_msi;
3368ff0c 97extern int radeon_lockup_timeout;
a0a53aa8 98extern int radeon_fastfb;
da321c8a 99extern int radeon_dpm;
1294d4a3 100extern int radeon_aspm;
10ebc0bc 101extern int radeon_runtime_pm;
363eb0b4 102extern int radeon_hard_reset;
c1c44132 103extern int radeon_vm_size;
4510fb98 104extern int radeon_vm_block_size;
a624f429 105extern int radeon_deep_color;
771fe6b9
JG		 106
107/*
108 * Copy from radeon_drv.h so we don't have to include both and have conflicting
109 * symbol;
110 */
bb635567
JG		 111#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
112#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 113/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 114#define RADEON_IB_POOL_SIZE 16
115#define RADEON_DEBUGFS_MAX_COMPONENTS 32
116#define RADEONFB_CONN_LIMIT 4
117#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 118
bb635567
JG		 119/* fence seq are set to this number when signaled */
120#define RADEON_FENCE_SIGNALED_SEQ 0LL
1b37078b
AD		 121
122/* internal ring indices */
123/* r1xx+ has gfx CP ring */
d93f7937 124#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 125
126/* cayman has 2 compute CP rings */
d93f7937
CK		 127#define CAYMAN_RING_TYPE_CP1_INDEX 1
128#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 129
4d75658b
AD		 130/* R600+ has an async dma ring */
131#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 132/* cayman add a second async dma ring */
133#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 134
f2ba57b5 135/* R600+ */
d93f7937
CK		 136#define R600_RING_TYPE_UVD_INDEX 5
137
138/* TN+ */
139#define TN_RING_TYPE_VCE1_INDEX 6
140#define TN_RING_TYPE_VCE2_INDEX 7
141
142/* max number of rings */
143#define RADEON_NUM_RINGS 8
f2ba57b5 144
1c61eae4
CK		 145/* number of hw syncs before falling back on blocking */
146#define RADEON_NUM_SYNCS 4
f2ba57b5 147
8f53492f
CK		 148/* number of hw syncs before falling back on blocking */
149#define RADEON_NUM_SYNCS 4
150
721604a1 151/* hardcode those limit for now */
ca19f21e 152#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 153#define RADEON_VA_RESERVED_SIZE (8 << 20)
154#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 155
1a0041b8
AD		 156/* hard reset data */
157#define RADEON_ASIC_RESET_DATA 0x39d5e86b
158
ec46c76d
AD		 159/* reset flags */
160#define RADEON_RESET_GFX (1 << 0)
161#define RADEON_RESET_COMPUTE (1 << 1)
162#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 163#define RADEON_RESET_CP (1 << 3)
164#define RADEON_RESET_GRBM (1 << 4)
165#define RADEON_RESET_DMA1 (1 << 5)
166#define RADEON_RESET_RLC (1 << 6)
167#define RADEON_RESET_SEM (1 << 7)
168#define RADEON_RESET_IH (1 << 8)
169#define RADEON_RESET_VMC (1 << 9)
170#define RADEON_RESET_MC (1 << 10)
171#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 172
22c775ce
AD		 173/* CG block flags */
174#define RADEON_CG_BLOCK_GFX (1 << 0)
175#define RADEON_CG_BLOCK_MC (1 << 1)
176#define RADEON_CG_BLOCK_SDMA (1 << 2)
177#define RADEON_CG_BLOCK_UVD (1 << 3)
178#define RADEON_CG_BLOCK_VCE (1 << 4)
179#define RADEON_CG_BLOCK_HDP (1 << 5)
e16866ec 180#define RADEON_CG_BLOCK_BIF (1 << 6)
22c775ce 181
64d8a728
AD		 182/* CG flags */
183#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
184#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
185#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
186#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
187#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
188#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
189#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
190#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
191#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
192#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
193#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
194#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
195#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
196#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
197#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
198#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
199#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
200
201/* PG flags */
2b19d17f 202#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
64d8a728
AD		 203#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
204#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
205#define RADEON_PG_SUPPORT_UVD (1 << 3)
206#define RADEON_PG_SUPPORT_VCE (1 << 4)
207#define RADEON_PG_SUPPORT_CP (1 << 5)
208#define RADEON_PG_SUPPORT_GDS (1 << 6)
209#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
210#define RADEON_PG_SUPPORT_SDMA (1 << 8)
211#define RADEON_PG_SUPPORT_ACP (1 << 9)
212#define RADEON_PG_SUPPORT_SAMU (1 << 10)
213
9e05fa1d
AD		 214/* max cursor sizes (in pixels) */
215#define CURSOR_WIDTH 64
216#define CURSOR_HEIGHT 64
217
218#define CIK_CURSOR_WIDTH 128
219#define CIK_CURSOR_HEIGHT 128
220
771fe6b9
JG		 221/*
222 * Errata workarounds.
223 */
224enum radeon_pll_errata {
225 CHIP_ERRATA_R300_CG = 0x00000001,
226 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
227 CHIP_ERRATA_PLL_DELAY = 0x00000004
228};
229
230
231struct radeon_device;
232
233
234/*
235 * BIOS.
236 */
237bool radeon_get_bios(struct radeon_device *rdev);
238
239/*
3ce0a23d 240 * Dummy page
771fe6b9 241 */
3ce0a23d
JG		 242struct radeon_dummy_page {
243 struct page *page;
244 dma_addr_t addr;
245};
246int radeon_dummy_page_init(struct radeon_device *rdev);
247void radeon_dummy_page_fini(struct radeon_device *rdev);
248
771fe6b9 249
3ce0a23d
JG		 250/*
251 * Clocks
252 */
771fe6b9
JG		 253struct radeon_clock {
254 struct radeon_pll p1pll;
255 struct radeon_pll p2pll;
bcc1c2a1 256 struct radeon_pll dcpll;
771fe6b9
JG		 257 struct radeon_pll spll;
258 struct radeon_pll mpll;
259 /* 10 Khz units */
260 uint32_t default_mclk;
261 uint32_t default_sclk;
bcc1c2a1 262 uint32_t default_dispclk;
4489cd62 263 uint32_t current_dispclk;
bcc1c2a1 264 uint32_t dp_extclk;
b20f9bef 265 uint32_t max_pixel_clock;
771fe6b9
JG		 266};
267
7433874e
RM		 268/*
269 * Power management
270 */
271int radeon_pm_init(struct radeon_device *rdev);
914a8987 272int radeon_pm_late_init(struct radeon_device *rdev);
29fb52ca 273void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 274void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 275void radeon_pm_suspend(struct radeon_device *rdev);
276void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 277void radeon_combios_get_power_modes(struct radeon_device *rdev);
278void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 279int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
280 u8 clock_type,
281 u32 clock,
282 bool strobe_mode,
283 struct atom_clock_dividers *dividers);
eaa778af
AD		 284int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
285 u32 clock,
286 bool strobe_mode,
287 struct atom_mpll_param *mpll_param);
8a83ec5e 288void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 289int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
290 u16 voltage_level, u8 voltage_type,
291 u32 *gpio_value, u32 *gpio_mask);
292void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
293 u32 eng_clock, u32 mem_clock);
294int radeon_atom_get_voltage_step(struct radeon_device *rdev,
295 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 296int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
297 u16 voltage_id, u16 *voltage);
beb79f40
AD		 298int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
299 u16 *voltage,
300 u16 leakage_idx);
cc8dbbb4
AD		 301int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
302 u16 *leakage_id);
303int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
304 u16 *vddc, u16 *vddci,
305 u16 virtual_voltage_id,
306 u16 vbios_voltage_id);
e9f274b2
AD		 307int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
308 u16 virtual_voltage_id,
309 u16 *voltage);
ae5b0abb
AD		 310int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
311 u8 voltage_type,
312 u16 nominal_voltage,
313 u16 *true_voltage);
314int radeon_atom_get_min_voltage(struct radeon_device *rdev,
315 u8 voltage_type, u16 *min_voltage);
316int radeon_atom_get_max_voltage(struct radeon_device *rdev,
317 u8 voltage_type, u16 *max_voltage);
318int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 319 u8 voltage_type, u8 voltage_mode,
ae5b0abb 320 struct atom_voltage_table *voltage_table);
58653abd
AD		 321bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
322 u8 voltage_type, u8 voltage_mode);
636e2582
AD		 323int radeon_atom_get_svi2_info(struct radeon_device *rdev,
324 u8 voltage_type,
325 u8 *svd_gpio_id, u8 *svc_gpio_id);
ae5b0abb
AD		 326void radeon_atom_update_memory_dll(struct radeon_device *rdev,
327 u32 mem_clock);
328void radeon_atom_set_ac_timing(struct radeon_device *rdev,
329 u32 mem_clock);
330int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
331 u8 module_index,
332 struct atom_mc_reg_table *reg_table);
333int radeon_atom_get_memory_info(struct radeon_device *rdev,
334 u8 module_index, struct atom_memory_info *mem_info);
335int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
336 bool gddr5, u8 module_index,
337 struct atom_memory_clock_range_table *mclk_range_table);
338int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
339 u16 voltage_id, u16 *voltage);
f892034a 340void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 341extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
342 unsigned *bankh, unsigned *mtaspect,
343 unsigned *tile_split);
3ce0a23d 344
771fe6b9
JG		 345/*
346 * Fences.
347 */
348struct radeon_fence_driver {
349 uint32_t scratch_reg;
30eb77f4
JG		 350 uint64_t gpu_addr;
351 volatile uint32_t *cpu_addr;
68e250b7
CK		 352 /* sync_seq is protected by ring emission lock */
353 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 354 atomic64_t last_seq;
0a0c7596 355 bool initialized;
771fe6b9
JG		 356};
357
358struct radeon_fence {
359 struct radeon_device *rdev;
360 struct kref kref;
771fe6b9 361 /* protected by radeon_fence.lock */
bb635567 362 uint64_t seq;
7465280c 363 /* RB, DMA, etc. */
bb635567 364 unsigned ring;
771fe6b9
JG		 365};
366
30eb77f4
JG		 367int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
368int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 369void radeon_fence_driver_fini(struct radeon_device *rdev);
76903b96 370void radeon_fence_driver_force_completion(struct radeon_device *rdev);
876dc9f3 371int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 372void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 373bool radeon_fence_signaled(struct radeon_fence *fence);
374int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
37615527
CK		 375int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
376int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
0085c950
JG		 377int radeon_fence_wait_any(struct radeon_device *rdev,
378 struct radeon_fence **fences,
379 bool intr);
771fe6b9
JG		 380struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
381void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 382unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 383bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
384void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
385static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
386 struct radeon_fence *b)
387{
388 if (!a) {
389 return b;
390 }
391
392 if (!b) {
393 return a;
394 }
395
396 BUG_ON(a->ring != b->ring);
397
398 if (a->seq > b->seq) {
399 return a;
400 } else {
401 return b;
402 }
403}
771fe6b9 404
ee60e29f
CK		 405static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
406 struct radeon_fence *b)
407{
408 if (!a) {
409 return false;
410 }
411
412 if (!b) {
413 return true;
414 }
415
416 BUG_ON(a->ring != b->ring);
417
418 return a->seq < b->seq;
419}
420
e024e110
DA		 421/*
422 * Tiling registers
423 */
424struct radeon_surface_reg {
4c788679 425 struct radeon_bo *bo;
e024e110
DA		 426};
427
428#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 429
430/*
4c788679 431 * TTM.
771fe6b9 432 */
4c788679
JG		 433struct radeon_mman {
434 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 435 struct drm_global_reference mem_global_ref;
4c788679 436 struct ttm_bo_device bdev;
0a0c7596
JG		 437 bool mem_global_referenced;
438 bool initialized;
2014b569
CK		 439
440#if defined(CONFIG_DEBUG_FS)
441 struct dentry *vram;
dd66d20e 442 struct dentry *gtt;
2014b569 443#endif
4c788679
JG		 444};
445
721604a1
JG		 446/* bo virtual address in a specific vm */
447struct radeon_bo_va {
e971bd5e 448 /* protected by bo being reserved */
721604a1 449 struct list_head bo_list;
721604a1
JG		 450 uint64_t soffset;
451 uint64_t eoffset;
452 uint32_t flags;
e31ad969 453 uint64_t addr;
e971bd5e
CK		 454 unsigned ref_count;
455
456 /* protected by vm mutex */
457 struct list_head vm_list;
036bf46a 458 struct list_head vm_status;
e971bd5e
CK		 459
460 /* constant after initialization */
461 struct radeon_vm *vm;
462 struct radeon_bo *bo;
721604a1
JG		 463};
464
4c788679
JG		 465struct radeon_bo {
466 /* Protected by gem.mutex */
467 struct list_head list;
468 /* Protected by tbo.reserved */
bda72d58 469 u32 initial_domain;
312ea8da
JG		 470 u32 placements[3];
471 struct ttm_placement placement;
4c788679
JG		 472 struct ttm_buffer_object tbo;
473 struct ttm_bo_kmap_obj kmap;
02376d82 474 u32 flags;
4c788679
JG		 475 unsigned pin_count;
476 void *kptr;
477 u32 tiling_flags;
478 u32 pitch;
479 int surface_reg;
721604a1
JG		 480 /* list of all virtual address to which this bo
481 * is associated to
482 */
483 struct list_head va;
4c788679
JG		 484 /* Constant after initialization */
485 struct radeon_device *rdev;
441921d5 486 struct drm_gem_object gem_base;
63bc620b 487
409851f4
JG		 488 struct ttm_bo_kmap_obj dma_buf_vmap;
489 pid_t pid;
4c788679 490};
7e4d15d9 491#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 492
409851f4
JG		 493int radeon_gem_debugfs_init(struct radeon_device *rdev);
494
b15ba512
JG		 495/* sub-allocation manager, it has to be protected by another lock.
496 * By conception this is an helper for other part of the driver
497 * like the indirect buffer or semaphore, which both have their
498 * locking.
499 *
500 * Principe is simple, we keep a list of sub allocation in offset
501 * order (first entry has offset == 0, last entry has the highest
502 * offset).
503 *
504 * When allocating new object we first check if there is room at
505 * the end total_size - (last_object_offset + last_object_size) >=
506 * alloc_size. If so we allocate new object there.
507 *
508 * When there is not enough room at the end, we start waiting for
509 * each sub object until we reach object_offset+object_size >=
510 * alloc_size, this object then become the sub object we return.
511 *
512 * Alignment can't be bigger than page size.
513 *
514 * Hole are not considered for allocation to keep things simple.
515 * Assumption is that there won't be hole (all object on same
516 * alignment).
517 */
518struct radeon_sa_manager {
bfb38d35 519 wait_queue_head_t wq;
b15ba512 520 struct radeon_bo *bo;
c3b7fe8b
CK		 521 struct list_head *hole;
522 struct list_head flist[RADEON_NUM_RINGS];
523 struct list_head olist;
b15ba512
JG		 524 unsigned size;
525 uint64_t gpu_addr;
526 void *cpu_ptr;
527 uint32_t domain;
6c4f978b 528 uint32_t align;
b15ba512
JG		 529};
530
531struct radeon_sa_bo;
532
533/* sub-allocation buffer */
534struct radeon_sa_bo {
c3b7fe8b
CK		 535 struct list_head olist;
536 struct list_head flist;
b15ba512 537 struct radeon_sa_manager *manager;
e6661a96
CK		 538 unsigned soffset;
539 unsigned eoffset;
557017a0 540 struct radeon_fence *fence;
b15ba512
JG		 541};
542
771fe6b9
JG		 543/*
544 * GEM objects.
545 */
546struct radeon_gem {
4c788679 547 struct mutex mutex;
771fe6b9
JG		 548 struct list_head objects;
549};
550
551int radeon_gem_init(struct radeon_device *rdev);
552void radeon_gem_fini(struct radeon_device *rdev);
391bfec3 553int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
4c788679 554 int alignment, int initial_domain,
ed5cb43f 555 u32 flags, bool kernel,
4c788679 556 struct drm_gem_object **obj);
771fe6b9 557
ff72145b
DA		 558int radeon_mode_dumb_create(struct drm_file *file_priv,
559 struct drm_device *dev,
560 struct drm_mode_create_dumb *args);
561int radeon_mode_dumb_mmap(struct drm_file *filp,
562 struct drm_device *dev,
563 uint32_t handle, uint64_t *offset_p);
771fe6b9 564
c1341e52
JG		 565/*
566 * Semaphores.
567 */
c1341e52 568struct radeon_semaphore {
a8c05940
JG		 569 struct radeon_sa_bo *sa_bo;
570 signed waiters;
c1341e52 571 uint64_t gpu_addr;
1654b817 572 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
c1341e52
JG		 573};
574
c1341e52
JG		 575int radeon_semaphore_create(struct radeon_device *rdev,
576 struct radeon_semaphore **semaphore);
1654b817 577bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
c1341e52 578 struct radeon_semaphore *semaphore);
1654b817 579bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
c1341e52 580 struct radeon_semaphore *semaphore);
1654b817
CK		 581void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
582 struct radeon_fence *fence);
8f676c4c
CK		 583int radeon_semaphore_sync_rings(struct radeon_device *rdev,
584 struct radeon_semaphore *semaphore,
1654b817 585 int waiting_ring);
c1341e52 586void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 587 struct radeon_semaphore **semaphore,
a8c05940 588 struct radeon_fence *fence);
c1341e52 589
771fe6b9
JG		 590/*
591 * GART structures, functions & helpers
592 */
593struct radeon_mc;
594
a77f1718 595#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 596#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 597#define RADEON_GPU_PAGE_SHIFT 12
721604a1 598#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 599
77497f27
MD		 600#define RADEON_GART_PAGE_DUMMY 0
601#define RADEON_GART_PAGE_VALID (1 << 0)
602#define RADEON_GART_PAGE_READ (1 << 1)
603#define RADEON_GART_PAGE_WRITE (1 << 2)
604#define RADEON_GART_PAGE_SNOOP (1 << 3)
605
771fe6b9
JG		 606struct radeon_gart {
607 dma_addr_t table_addr;
c9a1be96
JG		 608 struct radeon_bo *robj;
609 void *ptr;
771fe6b9
JG		 610 unsigned num_gpu_pages;
611 unsigned num_cpu_pages;
612 unsigned table_size;
771fe6b9
JG		 613 struct page **pages;
614 dma_addr_t *pages_addr;
615 bool ready;
616};
617
618int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
619void radeon_gart_table_ram_free(struct radeon_device *rdev);
620int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
621void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 622int radeon_gart_table_vram_pin(struct radeon_device *rdev);
623void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 624int radeon_gart_init(struct radeon_device *rdev);
625void radeon_gart_fini(struct radeon_device *rdev);
626void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
627 int pages);
628int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516 629 int pages, struct page **pagelist,
77497f27 630 dma_addr_t *dma_addr, uint32_t flags);
771fe6b9
JG		 631
632
633/*
634 * GPU MC structures, functions & helpers
635 */
636struct radeon_mc {
637 resource_size_t aper_size;
638 resource_size_t aper_base;
639 resource_size_t agp_base;
7a50f01a
DA		 640 /* for some chips with <= 32MB we need to lie
641 * about vram size near mc fb location */
3ce0a23d 642 u64 mc_vram_size;
d594e46a 643 u64 visible_vram_size;
3ce0a23d
JG		 644 u64 gtt_size;
645 u64 gtt_start;
646 u64 gtt_end;
3ce0a23d
JG		 647 u64 vram_start;
648 u64 vram_end;
771fe6b9 649 unsigned vram_width;
3ce0a23d 650 u64 real_vram_size;
771fe6b9
JG		 651 int vram_mtrr;
652 bool vram_is_ddr;
d594e46a 653 bool igp_sideport_enabled;
8d369bb1 654 u64 gtt_base_align;
9ed8b1f9 655 u64 mc_mask;
771fe6b9
JG		 656};
657
06b6476d
AD		 658bool radeon_combios_sideport_present(struct radeon_device *rdev);
659bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 660
661/*
662 * GPU scratch registers structures, functions & helpers
663 */
664struct radeon_scratch {
665 unsigned num_reg;
724c80e1 666 uint32_t reg_base;
771fe6b9
JG		 667 bool free[32];
668 uint32_t reg[32];
669};
670
671int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
672void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
673
75efdee1
AD		 674/*
675 * GPU doorbell structures, functions & helpers
676 */
d5754ab8
AL		 677#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
678
75efdee1 679struct radeon_doorbell {
75efdee1 680 /* doorbell mmio */
d5754ab8
AL		 681 resource_size_t base;
682 resource_size_t size;
683 u32 __iomem *ptr;
684 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
685 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
75efdee1
AD		 686};
687
688int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
689void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771fe6b9
JG		 690
691/*
692 * IRQS.
693 */
6f34be50 694
fa7f517c
CK		 695struct radeon_flip_work {
696 struct work_struct flip_work;
697 struct work_struct unpin_work;
698 struct radeon_device *rdev;
699 int crtc_id;
c60381bd 700 uint64_t base;
6f34be50 701 struct drm_pending_vblank_event *event;
fa7f517c 702 struct radeon_bo *old_rbo;
fa7f517c 703 struct radeon_fence *fence;
6f34be50
AD		 704};
705
706struct r500_irq_stat_regs {
707 u32 disp_int;
f122c610 708 u32 hdmi0_status;
6f34be50
AD		 709};
710
711struct r600_irq_stat_regs {
712 u32 disp_int;
713 u32 disp_int_cont;
714 u32 disp_int_cont2;
715 u32 d1grph_int;
716 u32 d2grph_int;
f122c610
AD		 717 u32 hdmi0_status;
718 u32 hdmi1_status;
6f34be50
AD		 719};
720
721struct evergreen_irq_stat_regs {
722 u32 disp_int;
723 u32 disp_int_cont;
724 u32 disp_int_cont2;
725 u32 disp_int_cont3;
726 u32 disp_int_cont4;
727 u32 disp_int_cont5;
728 u32 d1grph_int;
729 u32 d2grph_int;
730 u32 d3grph_int;
731 u32 d4grph_int;
732 u32 d5grph_int;
733 u32 d6grph_int;
f122c610
AD		 734 u32 afmt_status1;
735 u32 afmt_status2;
736 u32 afmt_status3;
737 u32 afmt_status4;
738 u32 afmt_status5;
739 u32 afmt_status6;
6f34be50
AD		 740};
741
a59781bb
AD		 742struct cik_irq_stat_regs {
743 u32 disp_int;
744 u32 disp_int_cont;
745 u32 disp_int_cont2;
746 u32 disp_int_cont3;
747 u32 disp_int_cont4;
748 u32 disp_int_cont5;
749 u32 disp_int_cont6;
f5d636d2
CK		 750 u32 d1grph_int;
751 u32 d2grph_int;
752 u32 d3grph_int;
753 u32 d4grph_int;
754 u32 d5grph_int;
755 u32 d6grph_int;
a59781bb
AD		 756};
757
6f34be50
AD		 758union radeon_irq_stat_regs {
759 struct r500_irq_stat_regs r500;
760 struct r600_irq_stat_regs r600;
761 struct evergreen_irq_stat_regs evergreen;
a59781bb 762 struct cik_irq_stat_regs cik;
6f34be50
AD		 763};
764
771fe6b9 765struct radeon_irq {
fb98257a
CK		 766 bool installed;
767 spinlock_t lock;
736fc37f 768 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 769 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 770 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 771 wait_queue_head_t vblank_queue;
772 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 773 bool afmt[RADEON_MAX_AFMT_BLOCKS];
774 union radeon_irq_stat_regs stat_regs;
4a6369e9 775 bool dpm_thermal;
771fe6b9
JG		 776};
777
778int radeon_irq_kms_init(struct radeon_device *rdev);
779void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b
AD		 780void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
781void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 782void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
783void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 784void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
785void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
786void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
787void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 788
789/*
e32eb50d 790 * CP & rings.
771fe6b9 791 */
7465280c 792
771fe6b9 793struct radeon_ib {
68470ae7
JG		 794 struct radeon_sa_bo *sa_bo;
795 uint32_t length_dw;
796 uint64_t gpu_addr;
797 uint32_t *ptr;
876dc9f3 798 int ring;
68470ae7 799 struct radeon_fence *fence;
4bf3dd92 800 struct radeon_vm *vm;
68470ae7
JG		 801 bool is_const_ib;
802 struct radeon_semaphore *semaphore;
771fe6b9
JG		 803};
804
e32eb50d 805struct radeon_ring {
4c788679 806 struct radeon_bo *ring_obj;
771fe6b9 807 volatile uint32_t *ring;
5596a9db 808 unsigned rptr_offs;
45df6803 809 unsigned rptr_save_reg;
89d35807
AD		 810 u64 next_rptr_gpu_addr;
811 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 812 unsigned wptr;
813 unsigned wptr_old;
814 unsigned ring_size;
815 unsigned ring_free_dw;
816 int count_dw;
aee4aa73
CK		 817 atomic_t last_rptr;
818 atomic64_t last_activity;
771fe6b9
JG		 819 uint64_t gpu_addr;
820 uint32_t align_mask;
821 uint32_t ptr_mask;
771fe6b9 822 bool ready;
78c5560a 823 u32 nop;
8b25ed34 824 u32 idx;
5f0839c1
JG		 825 u64 last_semaphore_signal_addr;
826 u64 last_semaphore_wait_addr;
963e81f9
AD		 827 /* for CIK queues */
828 u32 me;
829 u32 pipe;
830 u32 queue;
831 struct radeon_bo *mqd_obj;
d5754ab8 832 u32 doorbell_index;
963e81f9
AD		 833 unsigned wptr_offs;
834};
835
836struct radeon_mec {
837 struct radeon_bo *hpd_eop_obj;
838 u64 hpd_eop_gpu_addr;
839 u32 num_pipe;
840 u32 num_mec;
841 u32 num_queue;
771fe6b9
JG		 842};
843
721604a1
JG		 844/*
845 * VM
846 */
ee60e29f 847
fa87e62d 848/* maximum number of VMIDs */
ee60e29f
CK		 849#define RADEON_NUM_VM 16
850
fa87e62d 851/* number of entries in page table */
4510fb98 852#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
fa87e62d 853
1c01103c
AD		 854/* PTBs (Page Table Blocks) need to be aligned to 32K */
855#define RADEON_VM_PTB_ALIGN_SIZE 32768
856#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
857#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
858
24c16439
CK		 859#define R600_PTE_VALID (1 << 0)
860#define R600_PTE_SYSTEM (1 << 1)
861#define R600_PTE_SNOOPED (1 << 2)
862#define R600_PTE_READABLE (1 << 5)
863#define R600_PTE_WRITEABLE (1 << 6)
864
ec3dbbcb
CK		 865/* PTE (Page Table Entry) fragment field for different page sizes */
866#define R600_PTE_FRAG_4KB (0 << 7)
867#define R600_PTE_FRAG_64KB (4 << 7)
868#define R600_PTE_FRAG_256KB (6 << 7)
869
33fa9fe3
CK		 870/* flags needed to be set so we can copy directly from the GART table */
871#define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
872 R600_PTE_SYSTEM | R600_PTE_VALID )
0e97703c 873
6d2f2944
CK		 874struct radeon_vm_pt {
875 struct radeon_bo *bo;
876 uint64_t addr;
877};
878
721604a1 879struct radeon_vm {
721604a1 880 struct list_head va;
ee60e29f 881 unsigned id;
90a51a32 882
e31ad969
CK		 883 /* BOs moved, but not yet updated in the PT */
884 struct list_head invalidated;
885
036bf46a
CK		 886 /* BOs freed, but not yet updated in the PT */
887 struct list_head freed;
888
90a51a32 889 /* contains the page directory */
6d2f2944 890 struct radeon_bo *page_directory;
90a51a32 891 uint64_t pd_gpu_addr;
6d2f2944 892 unsigned max_pde_used;
90a51a32
CK		 893
894 /* array of page tables, one for each page directory entry */
6d2f2944 895 struct radeon_vm_pt *page_tables;
90a51a32 896
cc9e67e3
CK		 897 struct radeon_bo_va *ib_bo_va;
898
721604a1
JG		 899 struct mutex mutex;
900 /* last fence for cs using this vm */
901 struct radeon_fence *fence;
9b40e5d8
CK		 902 /* last flush or NULL if we still need to flush */
903 struct radeon_fence *last_flush;
593b2635
CK		 904 /* last use of vmid */
905 struct radeon_fence *last_id_use;
721604a1
JG		 906};
907
721604a1 908struct radeon_vm_manager {
ee60e29f 909 struct radeon_fence *active[RADEON_NUM_VM];
721604a1 910 uint32_t max_pfn;
721604a1
JG		 911 /* number of VMIDs */
912 unsigned nvm;
913 /* vram base address for page table entry */
914 u64 vram_base_offset;
67e915e4
AD		 915 /* is vm enabled? */
916 bool enabled;
721604a1
JG		 917};
918
919/*
920 * file private structure
921 */
922struct radeon_fpriv {
923 struct radeon_vm vm;
924};
925
d8f60cfc
AD		 926/*
927 * R6xx+ IH ring
928 */
929struct r600_ih {
4c788679 930 struct radeon_bo *ring_obj;
d8f60cfc
AD		 931 volatile uint32_t *ring;
932 unsigned rptr;
d8f60cfc
AD		 933 unsigned ring_size;
934 uint64_t gpu_addr;
d8f60cfc 935 uint32_t ptr_mask;
c20dc369 936 atomic_t lock;
d8f60cfc
AD		 937 bool enabled;
938};
939
347e7592 940/*
2948f5e6 941 * RLC stuff
347e7592 942 */
2948f5e6
AD		 943#include "clearstate_defs.h"
944
945struct radeon_rlc {
347e7592
AD		 946 /* for power gating */
947 struct radeon_bo *save_restore_obj;
948 uint64_t save_restore_gpu_addr;
2948f5e6 949 volatile uint32_t *sr_ptr;
1fd11777 950 const u32 *reg_list;
2948f5e6 951 u32 reg_list_size;
347e7592
AD		 952 /* for clear state */
953 struct radeon_bo *clear_state_obj;
954 uint64_t clear_state_gpu_addr;
2948f5e6 955 volatile uint32_t *cs_ptr;
1fd11777 956 const struct cs_section_def *cs_data;
22c775ce
AD		 957 u32 clear_state_size;
958 /* for cp tables */
959 struct radeon_bo *cp_table_obj;
960 uint64_t cp_table_gpu_addr;
961 volatile uint32_t *cp_table_ptr;
962 u32 cp_table_size;
347e7592
AD		 963};
964
69e130a6 965int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 966 struct radeon_ib *ib, struct radeon_vm *vm,
967 unsigned size);
f2e39221 968void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
4ef72566
CK		 969int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
970 struct radeon_ib *const_ib);
771fe6b9
JG		 971int radeon_ib_pool_init(struct radeon_device *rdev);
972void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 973int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 974/* Ring access between begin & end cannot sleep */
89d35807
AD		 975bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
976 struct radeon_ring *ring);
e32eb50d
CK		 977void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
978int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
979int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
980void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
981void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
d6999bc7 982void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 983void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
984int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
ff212f25
CK		 985void radeon_ring_lockup_update(struct radeon_device *rdev,
986 struct radeon_ring *ring);
069211e5 987bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 988unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
989 uint32_t **data);
990int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
991 unsigned size, uint32_t *data);
e32eb50d 992int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
ea31bf69 993 unsigned rptr_offs, u32 nop);
e32eb50d 994void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 995
996
4d75658b
AD		 997/* r600 async dma */
998void r600_dma_stop(struct radeon_device *rdev);
999int r600_dma_resume(struct radeon_device *rdev);
1000void r600_dma_fini(struct radeon_device *rdev);
1001
8c5fd7ef
AD		 1002void cayman_dma_stop(struct radeon_device *rdev);
1003int cayman_dma_resume(struct radeon_device *rdev);
1004void cayman_dma_fini(struct radeon_device *rdev);
1005
771fe6b9
JG		 1006/*
1007 * CS.
1008 */
1009struct radeon_cs_reloc {
1010 struct drm_gem_object *gobj;
4c788679 1011 struct radeon_bo *robj;
df0af440
CK		 1012 struct ttm_validate_buffer tv;
1013 uint64_t gpu_offset;
ce6758c8
CK		 1014 unsigned prefered_domains;
1015 unsigned allowed_domains;
df0af440 1016 uint32_t tiling_flags;
771fe6b9 1017 uint32_t handle;
771fe6b9
JG		 1018};
1019
1020struct radeon_cs_chunk {
1021 uint32_t chunk_id;
1022 uint32_t length_dw;
1023 uint32_t *kdata;
721604a1 1024 void __user *user_ptr;
771fe6b9
JG		 1025};
1026
1027struct radeon_cs_parser {
c8c15ff1 1028 struct device *dev;
771fe6b9
JG		 1029 struct radeon_device *rdev;
1030 struct drm_file *filp;
1031 /* chunks */
1032 unsigned nchunks;
1033 struct radeon_cs_chunk *chunks;
1034 uint64_t *chunks_array;
1035 /* IB */
1036 unsigned idx;
1037 /* relocations */
1038 unsigned nrelocs;
1039 struct radeon_cs_reloc *relocs;
1040 struct radeon_cs_reloc **relocs_ptr;
df0af440 1041 struct radeon_cs_reloc *vm_bos;
771fe6b9 1042 struct list_head validated;
cf4ccd01 1043 unsigned dma_reloc_idx;
771fe6b9
JG		 1044 /* indices of various chunks */
1045 int chunk_ib_idx;
1046 int chunk_relocs_idx;
721604a1 1047 int chunk_flags_idx;
dfcf5f36 1048 int chunk_const_ib_idx;
f2e39221
JG		 1049 struct radeon_ib ib;
1050 struct radeon_ib const_ib;
771fe6b9 1051 void *track;
3ce0a23d 1052 unsigned family;
e70f224c 1053 int parser_error;
721604a1
JG		 1054 u32 cs_flags;
1055 u32 ring;
1056 s32 priority;
ecff665f 1057 struct ww_acquire_ctx ticket;
771fe6b9
JG		 1058};
1059
28a326c5
ML		 1060static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1061{
1062 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1063
1064 if (ibc->kdata)
1065 return ibc->kdata[idx];
1066 return p->ib.ptr[idx];
1067}
1068
513bcb46 1069
771fe6b9
JG		 1070struct radeon_cs_packet {
1071 unsigned idx;
1072 unsigned type;
1073 unsigned reg;
1074 unsigned opcode;
1075 int count;
1076 unsigned one_reg_wr;
1077};
1078
1079typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1080 struct radeon_cs_packet *pkt,
1081 unsigned idx, unsigned reg);
1082typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1083 struct radeon_cs_packet *pkt);
1084
1085
1086/*
1087 * AGP
1088 */
1089int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1090void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1091void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1092void radeon_agp_fini(struct radeon_device *rdev);
1093
1094
1095/*
1096 * Writeback
1097 */
1098struct radeon_wb {
4c788679 1099 struct radeon_bo *wb_obj;
771fe6b9
JG		 1100 volatile uint32_t *wb;
1101 uint64_t gpu_addr;
724c80e1 1102 bool enabled;
d0f8a854 1103 bool use_event;
771fe6b9
JG		 1104};
1105
724c80e1 1106#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1107#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1108#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1109#define RADEON_WB_CP1_RPTR_OFFSET 1280
1110#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1111#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1112#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1113#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1114#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1115#define CIK_WB_CP1_WPTR_OFFSET 3328
1116#define CIK_WB_CP2_WPTR_OFFSET 3584
724c80e1 1117
c93bb85b
JG		 1118/**
1119 * struct radeon_pm - power management datas
1120 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1121 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1122 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1123 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1124 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1125 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1126 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1127 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1128 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1129 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1130 * @needed_bandwidth: current bandwidth needs
1131 *
1132 * It keeps track of various data needed to take powermanagement decision.
25985edc 1133 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1134 * Equation between gpu/memory clock and available bandwidth is hw dependent
1135 * (type of memory, bus size, efficiency, ...)
1136 */
ce8f5370
AD		 1137
1138enum radeon_pm_method {
1139 PM_METHOD_PROFILE,
1140 PM_METHOD_DYNPM,
da321c8a 1141 PM_METHOD_DPM,
ce8f5370
AD		 1142};
1143
1144enum radeon_dynpm_state {
1145 DYNPM_STATE_DISABLED,
1146 DYNPM_STATE_MINIMUM,
1147 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1148 DYNPM_STATE_ACTIVE,
1149 DYNPM_STATE_SUSPENDED,
c913e23a 1150};
ce8f5370
AD		 1151enum radeon_dynpm_action {
1152 DYNPM_ACTION_NONE,
1153 DYNPM_ACTION_MINIMUM,
1154 DYNPM_ACTION_DOWNCLOCK,
1155 DYNPM_ACTION_UPCLOCK,
1156 DYNPM_ACTION_DEFAULT
c913e23a 1157};
56278a8e
AD		 1158
1159enum radeon_voltage_type {
1160 VOLTAGE_NONE = 0,
1161 VOLTAGE_GPIO,
1162 VOLTAGE_VDDC,
1163 VOLTAGE_SW
1164};
1165
0ec0e74f 1166enum radeon_pm_state_type {
da321c8a 1167 /* not used for dpm */
0ec0e74f
AD		 1168 POWER_STATE_TYPE_DEFAULT,
1169 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1170 /* user selectable states */
0ec0e74f
AD		 1171 POWER_STATE_TYPE_BATTERY,
1172 POWER_STATE_TYPE_BALANCED,
1173 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1174 /* internal states */
1175 POWER_STATE_TYPE_INTERNAL_UVD,
1176 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1177 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1178 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1179 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1180 POWER_STATE_TYPE_INTERNAL_BOOT,
1181 POWER_STATE_TYPE_INTERNAL_THERMAL,
1182 POWER_STATE_TYPE_INTERNAL_ACPI,
1183 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1184 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1185};
1186
ce8f5370
AD		 1187enum radeon_pm_profile_type {
1188 PM_PROFILE_DEFAULT,
1189 PM_PROFILE_AUTO,
1190 PM_PROFILE_LOW,
c9e75b21 1191 PM_PROFILE_MID,
ce8f5370
AD		 1192 PM_PROFILE_HIGH,
1193};
1194
1195#define PM_PROFILE_DEFAULT_IDX 0
1196#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1197#define PM_PROFILE_MID_SH_IDX 2
1198#define PM_PROFILE_HIGH_SH_IDX 3
1199#define PM_PROFILE_LOW_MH_IDX 4
1200#define PM_PROFILE_MID_MH_IDX 5
1201#define PM_PROFILE_HIGH_MH_IDX 6
1202#define PM_PROFILE_MAX 7
ce8f5370
AD		 1203
1204struct radeon_pm_profile {
1205 int dpms_off_ps_idx;
1206 int dpms_on_ps_idx;
1207 int dpms_off_cm_idx;
1208 int dpms_on_cm_idx;
516d0e46
AD		 1209};
1210
21a8122a
AD		 1211enum radeon_int_thermal_type {
1212 THERMAL_TYPE_NONE,
da321c8a
AD		 1213 THERMAL_TYPE_EXTERNAL,
1214 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1215 THERMAL_TYPE_RV6XX,
1216 THERMAL_TYPE_RV770,
da321c8a 1217 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1218 THERMAL_TYPE_EVERGREEN,
e33df25f 1219 THERMAL_TYPE_SUMO,
4fddba1f 1220 THERMAL_TYPE_NI,
14607d08 1221 THERMAL_TYPE_SI,
da321c8a 1222 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1223 THERMAL_TYPE_CI,
16fbe00d 1224 THERMAL_TYPE_KV,
21a8122a
AD		 1225};
1226
56278a8e
AD		 1227struct radeon_voltage {
1228 enum radeon_voltage_type type;
1229 /* gpio voltage */
1230 struct radeon_gpio_rec gpio;
1231 u32 delay; /* delay in usec from voltage drop to sclk change */
1232 bool active_high; /* voltage drop is active when bit is high */
1233 /* VDDC voltage */
1234 u8 vddc_id; /* index into vddc voltage table */
1235 u8 vddci_id; /* index into vddci voltage table */
1236 bool vddci_enabled;
1237 /* r6xx+ sw */
2feea49a
AD		 1238 u16 voltage;
1239 /* evergreen+ vddci */
1240 u16 vddci;
56278a8e
AD		 1241};
1242
d7311171
AD		 1243/* clock mode flags */
1244#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1245
56278a8e
AD		 1246struct radeon_pm_clock_info {
1247 /* memory clock */
1248 u32 mclk;
1249 /* engine clock */
1250 u32 sclk;
1251 /* voltage info */
1252 struct radeon_voltage voltage;
d7311171 1253 /* standardized clock flags */
56278a8e
AD		 1254 u32 flags;
1255};
1256
a48b9b4e 1257/* state flags */
d7311171 1258#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1259
56278a8e 1260struct radeon_power_state {
0ec0e74f 1261 enum radeon_pm_state_type type;
8f3f1c9a 1262 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1263 /* number of valid clock modes in this power state */
1264 int num_clock_modes;
56278a8e 1265 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1266 /* standardized state flags */
1267 u32 flags;
79daedc9
AD		 1268 u32 misc; /* vbios specific flags */
1269 u32 misc2; /* vbios specific flags */
1270 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1271};
1272
27459324
RM		 1273/*
1274 * Some modes are overclocked by very low value, accept them
1275 */
1276#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1277
2e9d4c05
AD		 1278enum radeon_dpm_auto_throttle_src {
1279 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1280 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1281};
1282
1283enum radeon_dpm_event_src {
1284 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1285 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1286 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1287 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1288 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1289};
1290
58bd2a88
AD		 1291#define RADEON_MAX_VCE_LEVELS 6
1292
b62d628b
AD		 1293enum radeon_vce_level {
1294 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1295 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1296 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1297 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1298 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1299 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1300};
1301
da321c8a
AD		 1302struct radeon_ps {
1303 u32 caps; /* vbios flags */
1304 u32 class; /* vbios flags */
1305 u32 class2; /* vbios flags */
1306 /* UVD clocks */
1307 u32 vclk;
1308 u32 dclk;
c4453e66
AD		 1309 /* VCE clocks */
1310 u32 evclk;
1311 u32 ecclk;
b62d628b
AD		 1312 bool vce_active;
1313 enum radeon_vce_level vce_level;
da321c8a
AD		 1314 /* asic priv */
1315 void *ps_priv;
1316};
1317
1318struct radeon_dpm_thermal {
1319 /* thermal interrupt work */
1320 struct work_struct work;
1321 /* low temperature threshold */
1322 int min_temp;
1323 /* high temperature threshold */
1324 int max_temp;
1325 /* was interrupt low to high or high to low */
1326 bool high_to_low;
1327};
1328
d22b7e40
AD		 1329enum radeon_clk_action
1330{
1331 RADEON_SCLK_UP = 1,
1332 RADEON_SCLK_DOWN
1333};
1334
1335struct radeon_blacklist_clocks
1336{
1337 u32 sclk;
1338 u32 mclk;
1339 enum radeon_clk_action action;
1340};
1341
61b7d601
AD		 1342struct radeon_clock_and_voltage_limits {
1343 u32 sclk;
1344 u32 mclk;
cdf6e805
AD		 1345 u16 vddc;
1346 u16 vddci;
61b7d601
AD		 1347};
1348
1349struct radeon_clock_array {
1350 u32 count;
1351 u32 *values;
1352};
1353
1354struct radeon_clock_voltage_dependency_entry {
1355 u32 clk;
1356 u16 v;
1357};
1358
1359struct radeon_clock_voltage_dependency_table {
1360 u32 count;
1361 struct radeon_clock_voltage_dependency_entry *entries;
1362};
1363
ef976ec4
AD		 1364union radeon_cac_leakage_entry {
1365 struct {
1366 u16 vddc;
1367 u32 leakage;
1368 };
1369 struct {
1370 u16 vddc1;
1371 u16 vddc2;
1372 u16 vddc3;
1373 };
61b7d601
AD		 1374};
1375
1376struct radeon_cac_leakage_table {
1377 u32 count;
ef976ec4 1378 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1379};
1380
929ee7a8
AD		 1381struct radeon_phase_shedding_limits_entry {
1382 u16 voltage;
1383 u32 sclk;
1384 u32 mclk;
1385};
1386
1387struct radeon_phase_shedding_limits_table {
1388 u32 count;
1389 struct radeon_phase_shedding_limits_entry *entries;
1390};
1391
84a9d9ee
AD		 1392struct radeon_uvd_clock_voltage_dependency_entry {
1393 u32 vclk;
1394 u32 dclk;
1395 u16 v;
1396};
1397
1398struct radeon_uvd_clock_voltage_dependency_table {
1399 u8 count;
1400 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1401};
1402
d29f013b
AD		 1403struct radeon_vce_clock_voltage_dependency_entry {
1404 u32 ecclk;
1405 u32 evclk;
1406 u16 v;
1407};
1408
1409struct radeon_vce_clock_voltage_dependency_table {
1410 u8 count;
1411 struct radeon_vce_clock_voltage_dependency_entry *entries;
1412};
1413
a5cb318e
AD		 1414struct radeon_ppm_table {
1415 u8 ppm_design;
1416 u16 cpu_core_number;
1417 u32 platform_tdp;
1418 u32 small_ac_platform_tdp;
1419 u32 platform_tdc;
1420 u32 small_ac_platform_tdc;
1421 u32 apu_tdp;
1422 u32 dgpu_tdp;
1423 u32 dgpu_ulv_power;
1424 u32 tj_max;
1425};
1426
58cb7632
AD		 1427struct radeon_cac_tdp_table {
1428 u16 tdp;
1429 u16 configurable_tdp;
1430 u16 tdc;
1431 u16 battery_power_limit;
1432 u16 small_power_limit;
1433 u16 low_cac_leakage;
1434 u16 high_cac_leakage;
1435 u16 maximum_power_delivery_limit;
1436};
1437
61b7d601
AD		 1438struct radeon_dpm_dynamic_state {
1439 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1440 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1441 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1442 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1443 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1444 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1445 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1446 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1447 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1448 struct radeon_clock_array valid_sclk_values;
1449 struct radeon_clock_array valid_mclk_values;
1450 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1451 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1452 u32 mclk_sclk_ratio;
1453 u32 sclk_mclk_delta;
1454 u16 vddc_vddci_delta;
1455 u16 min_vddc_for_pcie_gen2;
1456 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1457 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1458 struct radeon_ppm_table *ppm_table;
58cb7632 1459 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1460};
1461
1462struct radeon_dpm_fan {
1463 u16 t_min;
1464 u16 t_med;
1465 u16 t_high;
1466 u16 pwm_min;
1467 u16 pwm_med;
1468 u16 pwm_high;
1469 u8 t_hyst;
1470 u32 cycle_delay;
1471 u16 t_max;
1472 bool ucode_fan_control;
1473};
1474
32ce4652
AD		 1475enum radeon_pcie_gen {
1476 RADEON_PCIE_GEN1 = 0,
1477 RADEON_PCIE_GEN2 = 1,
1478 RADEON_PCIE_GEN3 = 2,
1479 RADEON_PCIE_GEN_INVALID = 0xffff
1480};
1481
70d01a5e
AD		 1482enum radeon_dpm_forced_level {
1483 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1484 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1485 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1486};
1487
58bd2a88
AD		 1488struct radeon_vce_state {
1489 /* vce clocks */
1490 u32 evclk;
1491 u32 ecclk;
1492 /* gpu clocks */
1493 u32 sclk;
1494 u32 mclk;
1495 u8 clk_idx;
1496 u8 pstate;
1497};
1498
da321c8a
AD		 1499struct radeon_dpm {
1500 struct radeon_ps *ps;
1501 /* number of valid power states */
1502 int num_ps;
1503 /* current power state that is active */
1504 struct radeon_ps *current_ps;
1505 /* requested power state */
1506 struct radeon_ps *requested_ps;
1507 /* boot up power state */
1508 struct radeon_ps *boot_ps;
1509 /* default uvd power state */
1510 struct radeon_ps *uvd_ps;
58bd2a88
AD		 1511 /* vce requirements */
1512 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1513 enum radeon_vce_level vce_level;
da321c8a
AD		 1514 enum radeon_pm_state_type state;
1515 enum radeon_pm_state_type user_state;
1516 u32 platform_caps;
1517 u32 voltage_response_time;
1518 u32 backbias_response_time;
1519 void *priv;
1520 u32 new_active_crtcs;
1521 int new_active_crtc_count;
1522 u32 current_active_crtcs;
1523 int current_active_crtc_count;
61b7d601
AD		 1524 struct radeon_dpm_dynamic_state dyn_state;
1525 struct radeon_dpm_fan fan;
1526 u32 tdp_limit;
1527 u32 near_tdp_limit;
a9e61410 1528 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1529 u32 sq_ramping_threshold;
1530 u32 cac_leakage;
1531 u16 tdp_od_limit;
1532 u32 tdp_adjustment;
1533 u16 load_line_slope;
1534 bool power_control;
5ca302f7 1535 bool ac_power;
da321c8a
AD		 1536 /* special states active */
1537 bool thermal_active;
8a227555 1538 bool uvd_active;
b62d628b 1539 bool vce_active;
da321c8a
AD		 1540 /* thermal handling */
1541 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1542 /* forced levels */
1543 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1544 /* track UVD streams */
1545 unsigned sd;
1546 unsigned hd;
da321c8a
AD		 1547};
1548
ce3537d5 1549void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
03afe6f6 1550void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
da321c8a 1551
c93bb85b 1552struct radeon_pm {
c913e23a 1553 struct mutex mutex;
db7fce39
CK		 1554 /* write locked while reprogramming mclk */
1555 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1556 u32 active_crtcs;
1557 int active_crtc_count;
c913e23a 1558 int req_vblank;
839461d3 1559 bool vblank_sync;
c93bb85b
JG		 1560 fixed20_12 max_bandwidth;
1561 fixed20_12 igp_sideport_mclk;
1562 fixed20_12 igp_system_mclk;
1563 fixed20_12 igp_ht_link_clk;
1564 fixed20_12 igp_ht_link_width;
1565 fixed20_12 k8_bandwidth;
1566 fixed20_12 sideport_bandwidth;
1567 fixed20_12 ht_bandwidth;
1568 fixed20_12 core_bandwidth;
1569 fixed20_12 sclk;
f47299c5 1570 fixed20_12 mclk;
c93bb85b 1571 fixed20_12 needed_bandwidth;
0975b162 1572 struct radeon_power_state *power_state;
56278a8e
AD		 1573 /* number of valid power states */
1574 int num_power_states;
a48b9b4e
AD		 1575 int current_power_state_index;
1576 int current_clock_mode_index;
1577 int requested_power_state_index;
1578 int requested_clock_mode_index;
1579 int default_power_state_index;
1580 u32 current_sclk;
1581 u32 current_mclk;
2feea49a
AD		 1582 u16 current_vddc;
1583 u16 current_vddci;
9ace9f7b
AD		 1584 u32 default_sclk;
1585 u32 default_mclk;
2feea49a
AD		 1586 u16 default_vddc;
1587 u16 default_vddci;
29fb52ca 1588 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1589 /* selected pm method */
1590 enum radeon_pm_method pm_method;
1591 /* dynpm power management */
1592 struct delayed_work dynpm_idle_work;
1593 enum radeon_dynpm_state dynpm_state;
1594 enum radeon_dynpm_action dynpm_planned_action;
1595 unsigned long dynpm_action_timeout;
1596 bool dynpm_can_upclock;
1597 bool dynpm_can_downclock;
1598 /* profile-based power management */
1599 enum radeon_pm_profile_type profile;
1600 int profile_index;
1601 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1602 /* internal thermal controller on rv6xx+ */
1603 enum radeon_int_thermal_type int_thermal_type;
1604 struct device *int_hwmon_dev;
da321c8a
AD		 1605 /* dpm */
1606 bool dpm_enabled;
1607 struct radeon_dpm dpm;
c93bb85b
JG		 1608};
1609
a4c9e2ee
AD		 1610int radeon_pm_get_type_index(struct radeon_device *rdev,
1611 enum radeon_pm_state_type ps_type,
1612 int instance);
f2ba57b5
CK		 1613/*
1614 * UVD
1615 */
1616#define RADEON_MAX_UVD_HANDLES 10
1617#define RADEON_UVD_STACK_SIZE (1024*1024)
1618#define RADEON_UVD_HEAP_SIZE (1024*1024)
1619
1620struct radeon_uvd {
1621 struct radeon_bo *vcpu_bo;
1622 void *cpu_addr;
1623 uint64_t gpu_addr;
9cc2e0e9 1624 void *saved_bo;
f2ba57b5
CK		 1625 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1626 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1627 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1628 struct delayed_work idle_work;
f2ba57b5
CK		 1629};
1630
1631int radeon_uvd_init(struct radeon_device *rdev);
1632void radeon_uvd_fini(struct radeon_device *rdev);
1633int radeon_uvd_suspend(struct radeon_device *rdev);
1634int radeon_uvd_resume(struct radeon_device *rdev);
1635int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1636 uint32_t handle, struct radeon_fence **fence);
1637int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1638 uint32_t handle, struct radeon_fence **fence);
1639void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1640void radeon_uvd_free_handles(struct radeon_device *rdev,
1641 struct drm_file *filp);
1642int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1643void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1644int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1645 unsigned vclk, unsigned dclk,
1646 unsigned vco_min, unsigned vco_max,
1647 unsigned fb_factor, unsigned fb_mask,
1648 unsigned pd_min, unsigned pd_max,
1649 unsigned pd_even,
1650 unsigned *optimal_fb_div,
1651 unsigned *optimal_vclk_div,
1652 unsigned *optimal_dclk_div);
1653int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1654 unsigned cg_upll_func_cntl);
771fe6b9 1655
d93f7937
CK		 1656/*
1657 * VCE
1658 */
1659#define RADEON_MAX_VCE_HANDLES 16
1660#define RADEON_VCE_STACK_SIZE (1024*1024)
1661#define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1662
1663struct radeon_vce {
1664 struct radeon_bo *vcpu_bo;
d93f7937 1665 uint64_t gpu_addr;
98ccc291
CK		 1666 unsigned fw_version;
1667 unsigned fb_version;
d93f7937
CK		 1668 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1669 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
2fc5703a 1670 unsigned img_size[RADEON_MAX_VCE_HANDLES];
03afe6f6 1671 struct delayed_work idle_work;
d93f7937
CK		 1672};
1673
1674int radeon_vce_init(struct radeon_device *rdev);
1675void radeon_vce_fini(struct radeon_device *rdev);
1676int radeon_vce_suspend(struct radeon_device *rdev);
1677int radeon_vce_resume(struct radeon_device *rdev);
1678int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1679 uint32_t handle, struct radeon_fence **fence);
1680int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1681 uint32_t handle, struct radeon_fence **fence);
1682void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
03afe6f6 1683void radeon_vce_note_usage(struct radeon_device *rdev);
2fc5703a 1684int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
d93f7937
CK		 1685int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1686bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1687 struct radeon_ring *ring,
1688 struct radeon_semaphore *semaphore,
1689 bool emit_wait);
1690void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1691void radeon_vce_fence_emit(struct radeon_device *rdev,
1692 struct radeon_fence *fence);
1693int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1694int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1695
b530602f 1696struct r600_audio_pin {
a92553ab
RM		 1697 int channels;
1698 int rate;
1699 int bits_per_sample;
1700 u8 status_bits;
1701 u8 category_code;
b530602f
AD		 1702 u32 offset;
1703 bool connected;
1704 u32 id;
1705};
1706
1707struct r600_audio {
1708 bool enabled;
1709 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1710 int num_pins;
a92553ab
RM		 1711};
1712
771fe6b9
JG		 1713/*
1714 * Benchmarking
1715 */
638dd7db 1716void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1717
1718
ecc0b326
MD		 1719/*
1720 * Testing
1721 */
1722void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1723void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1724 struct radeon_ring *cpA,
1725 struct radeon_ring *cpB);
60a7e396 1726void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326
MD		 1727
1728
771fe6b9
JG		 1729/*
1730 * Debugfs
1731 */
4d8bf9ae
CK		 1732struct radeon_debugfs {
1733 struct drm_info_list *files;
1734 unsigned num_files;
1735};
1736
771fe6b9
JG		 1737int radeon_debugfs_add_files(struct radeon_device *rdev,
1738 struct drm_info_list *files,
1739 unsigned nfiles);
1740int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1741
76a0df85
CK		 1742/*
1743 * ASIC ring specific functions.
1744 */
1745struct radeon_asic_ring {
1746 /* ring read/write ptr handling */
1747 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1748 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1749 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1750
1751 /* validating and patching of IBs */
1752 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1753 int (*cs_parse)(struct radeon_cs_parser *p);
1754
1755 /* command emmit functions */
1756 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1757 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
72a9987e 1758 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1654b817 1759 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
76a0df85
CK		 1760 struct radeon_semaphore *semaphore, bool emit_wait);
1761 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1762
1763 /* testing functions */
1764 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1765 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1766 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1767
1768 /* deprecated */
1769 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1770};
771fe6b9
JG		 1771
1772/*
1773 * ASIC specific functions.
1774 */
1775struct radeon_asic {
068a117c 1776 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1777 void (*fini)(struct radeon_device *rdev);
1778 int (*resume)(struct radeon_device *rdev);
1779 int (*suspend)(struct radeon_device *rdev);
28d52043 1780 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1781 int (*asic_reset)(struct radeon_device *rdev);
124764f1
MD		 1782 /* Flush the HDP cache via MMIO */
1783 void (*mmio_hdp_flush)(struct radeon_device *rdev);
54e88e06
AD		 1784 /* check if 3D engine is idle */
1785 bool (*gui_idle)(struct radeon_device *rdev);
1786 /* wait for mc_idle */
1787 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1788 /* get the reference clock */
1789 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1790 /* get the gpu clock counter */
1791 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1792 /* gart */
c5b3b850
AD		 1793 struct {
1794 void (*tlb_flush)(struct radeon_device *rdev);
7f90fc96 1795 void (*set_page)(struct radeon_device *rdev, unsigned i,
77497f27 1796 uint64_t addr, uint32_t flags);
c5b3b850 1797 } gart;
05b07147
CK		 1798 struct {
1799 int (*init)(struct radeon_device *rdev);
1800 void (*fini)(struct radeon_device *rdev);
43f1214a
AD		 1801 void (*set_page)(struct radeon_device *rdev,
1802 struct radeon_ib *ib,
1803 uint64_t pe,
dce34bfd
CK		 1804 uint64_t addr, unsigned count,
1805 uint32_t incr, uint32_t flags);
05b07147 1806 } vm;
54e88e06 1807 /* ring specific callbacks */
76a0df85 1808 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1809 /* irqs */
b35ea4ab
AD		 1810 struct {
1811 int (*set)(struct radeon_device *rdev);
1812 int (*process)(struct radeon_device *rdev);
1813 } irq;
54e88e06 1814 /* displays */
c79a49ca
AD		 1815 struct {
1816 /* display watermarks */
1817 void (*bandwidth_update)(struct radeon_device *rdev);
1818 /* get frame count */
1819 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1820 /* wait for vblank */
1821 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1822 /* set backlight level */
1823 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1824 /* get backlight level */
1825 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1826 /* audio callbacks */
1827 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1828 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1829 } display;
54e88e06 1830 /* copy functions for bo handling */
27cd7769
AD		 1831 struct {
1832 int (*blit)(struct radeon_device *rdev,
1833 uint64_t src_offset,
1834 uint64_t dst_offset,
1835 unsigned num_gpu_pages,
876dc9f3 1836 struct radeon_fence **fence);
27cd7769
AD		 1837 u32 blit_ring_index;
1838 int (*dma)(struct radeon_device *rdev,
1839 uint64_t src_offset,
1840 uint64_t dst_offset,
1841 unsigned num_gpu_pages,
876dc9f3 1842 struct radeon_fence **fence);
27cd7769
AD		 1843 u32 dma_ring_index;
1844 /* method used for bo copy */
1845 int (*copy)(struct radeon_device *rdev,
1846 uint64_t src_offset,
1847 uint64_t dst_offset,
1848 unsigned num_gpu_pages,
876dc9f3 1849 struct radeon_fence **fence);
27cd7769
AD		 1850 /* ring used for bo copies */
1851 u32 copy_ring_index;
1852 } copy;
54e88e06 1853 /* surfaces */
9e6f3d02
AD		 1854 struct {
1855 int (*set_reg)(struct radeon_device *rdev, int reg,
1856 uint32_t tiling_flags, uint32_t pitch,
1857 uint32_t offset, uint32_t obj_size);
1858 void (*clear_reg)(struct radeon_device *rdev, int reg);
1859 } surface;
54e88e06 1860 /* hotplug detect */
901ea57d
AD		 1861 struct {
1862 void (*init)(struct radeon_device *rdev);
1863 void (*fini)(struct radeon_device *rdev);
1864 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1865 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1866 } hpd;
da321c8a 1867 /* static power management */
a02fa397
AD		 1868 struct {
1869 void (*misc)(struct radeon_device *rdev);
1870 void (*prepare)(struct radeon_device *rdev);
1871 void (*finish)(struct radeon_device *rdev);
1872 void (*init_profile)(struct radeon_device *rdev);
1873 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1874 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1875 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1876 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1877 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1878 int (*get_pcie_lanes)(struct radeon_device *rdev);
1879 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1880 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1881 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
b59b7333 1882 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
6bd1c385 1883 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1884 } pm;
da321c8a
AD		 1885 /* dynamic power management */
1886 struct {
1887 int (*init)(struct radeon_device *rdev);
1888 void (*setup_asic)(struct radeon_device *rdev);
1889 int (*enable)(struct radeon_device *rdev);
914a8987 1890 int (*late_enable)(struct radeon_device *rdev);
da321c8a 1891 void (*disable)(struct radeon_device *rdev);
84dd1928 1892 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1893 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1894 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1895 void (*display_configuration_changed)(struct radeon_device *rdev);
1896 void (*fini)(struct radeon_device *rdev);
1897 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1898 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1899 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1900 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1901 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1902 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1903 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1c71bda0 1904 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
da321c8a 1905 } dpm;
6f34be50 1906 /* pageflipping */
0f9e006c 1907 struct {
157fa14d
CK		 1908 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1909 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
0f9e006c 1910 } pflip;
771fe6b9
JG		 1911};
1912
21f9a437
JG		 1913/*
1914 * Asic structures
1915 */
551ebd83 1916struct r100_asic {
225758d8
JG		 1917 const unsigned *reg_safe_bm;
1918 unsigned reg_safe_bm_size;
1919 u32 hdp_cntl;
551ebd83
DA		 1920};
1921
21f9a437 1922struct r300_asic {
225758d8
JG		 1923 const unsigned *reg_safe_bm;
1924 unsigned reg_safe_bm_size;
1925 u32 resync_scratch;
1926 u32 hdp_cntl;
21f9a437
JG		 1927};
1928
1929struct r600_asic {
225758d8
JG		 1930 unsigned max_pipes;
1931 unsigned max_tile_pipes;
1932 unsigned max_simds;
1933 unsigned max_backends;
1934 unsigned max_gprs;
1935 unsigned max_threads;
1936 unsigned max_stack_entries;
1937 unsigned max_hw_contexts;
1938 unsigned max_gs_threads;
1939 unsigned sx_max_export_size;
1940 unsigned sx_max_export_pos_size;
1941 unsigned sx_max_export_smx_size;
1942 unsigned sq_num_cf_insts;
1943 unsigned tiling_nbanks;
1944 unsigned tiling_npipes;
1945 unsigned tiling_group_size;
e7aeeba6 1946 unsigned tile_config;
e55b9422 1947 unsigned backend_map;
65fcf668 1948 unsigned active_simds;
21f9a437
JG		 1949};
1950
1951struct rv770_asic {
225758d8
JG		 1952 unsigned max_pipes;
1953 unsigned max_tile_pipes;
1954 unsigned max_simds;
1955 unsigned max_backends;
1956 unsigned max_gprs;
1957 unsigned max_threads;
1958 unsigned max_stack_entries;
1959 unsigned max_hw_contexts;
1960 unsigned max_gs_threads;
1961 unsigned sx_max_export_size;
1962 unsigned sx_max_export_pos_size;
1963 unsigned sx_max_export_smx_size;
1964 unsigned sq_num_cf_insts;
1965 unsigned sx_num_of_sets;
1966 unsigned sc_prim_fifo_size;
1967 unsigned sc_hiz_tile_fifo_size;
1968 unsigned sc_earlyz_tile_fifo_fize;
1969 unsigned tiling_nbanks;
1970 unsigned tiling_npipes;
1971 unsigned tiling_group_size;
e7aeeba6 1972 unsigned tile_config;
e55b9422 1973 unsigned backend_map;
65fcf668 1974 unsigned active_simds;
21f9a437
JG		 1975};
1976
32fcdbf4
AD		 1977struct evergreen_asic {
1978 unsigned num_ses;
1979 unsigned max_pipes;
1980 unsigned max_tile_pipes;
1981 unsigned max_simds;
1982 unsigned max_backends;
1983 unsigned max_gprs;
1984 unsigned max_threads;
1985 unsigned max_stack_entries;
1986 unsigned max_hw_contexts;
1987 unsigned max_gs_threads;
1988 unsigned sx_max_export_size;
1989 unsigned sx_max_export_pos_size;
1990 unsigned sx_max_export_smx_size;
1991 unsigned sq_num_cf_insts;
1992 unsigned sx_num_of_sets;
1993 unsigned sc_prim_fifo_size;
1994 unsigned sc_hiz_tile_fifo_size;
1995 unsigned sc_earlyz_tile_fifo_size;
1996 unsigned tiling_nbanks;
1997 unsigned tiling_npipes;
1998 unsigned tiling_group_size;
e7aeeba6 1999 unsigned tile_config;
e55b9422 2000 unsigned backend_map;
65fcf668 2001 unsigned active_simds;
32fcdbf4
AD		 2002};
2003
fecf1d07
AD		 2004struct cayman_asic {
2005 unsigned max_shader_engines;
2006 unsigned max_pipes_per_simd;
2007 unsigned max_tile_pipes;
2008 unsigned max_simds_per_se;
2009 unsigned max_backends_per_se;
2010 unsigned max_texture_channel_caches;
2011 unsigned max_gprs;
2012 unsigned max_threads;
2013 unsigned max_gs_threads;
2014 unsigned max_stack_entries;
2015 unsigned sx_num_of_sets;
2016 unsigned sx_max_export_size;
2017 unsigned sx_max_export_pos_size;
2018 unsigned sx_max_export_smx_size;
2019 unsigned max_hw_contexts;
2020 unsigned sq_num_cf_insts;
2021 unsigned sc_prim_fifo_size;
2022 unsigned sc_hiz_tile_fifo_size;
2023 unsigned sc_earlyz_tile_fifo_size;
2024
2025 unsigned num_shader_engines;
2026 unsigned num_shader_pipes_per_simd;
2027 unsigned num_tile_pipes;
2028 unsigned num_simds_per_se;
2029 unsigned num_backends_per_se;
2030 unsigned backend_disable_mask_per_asic;
2031 unsigned backend_map;
2032 unsigned num_texture_channel_caches;
2033 unsigned mem_max_burst_length_bytes;
2034 unsigned mem_row_size_in_kb;
2035 unsigned shader_engine_tile_size;
2036 unsigned num_gpus;
2037 unsigned multi_gpu_tile_size;
2038
2039 unsigned tile_config;
65fcf668 2040 unsigned active_simds;
fecf1d07
AD		 2041};
2042
0a96d72b
AD		 2043struct si_asic {
2044 unsigned max_shader_engines;
0a96d72b 2045 unsigned max_tile_pipes;
1a8ca750
AD		 2046 unsigned max_cu_per_sh;
2047 unsigned max_sh_per_se;
0a96d72b
AD		 2048 unsigned max_backends_per_se;
2049 unsigned max_texture_channel_caches;
2050 unsigned max_gprs;
2051 unsigned max_gs_threads;
2052 unsigned max_hw_contexts;
2053 unsigned sc_prim_fifo_size_frontend;
2054 unsigned sc_prim_fifo_size_backend;
2055 unsigned sc_hiz_tile_fifo_size;
2056 unsigned sc_earlyz_tile_fifo_size;
2057
0a96d72b 2058 unsigned num_tile_pipes;
439a1cff 2059 unsigned backend_enable_mask;
0a96d72b
AD		 2060 unsigned backend_disable_mask_per_asic;
2061 unsigned backend_map;
2062 unsigned num_texture_channel_caches;
2063 unsigned mem_max_burst_length_bytes;
2064 unsigned mem_row_size_in_kb;
2065 unsigned shader_engine_tile_size;
2066 unsigned num_gpus;
2067 unsigned multi_gpu_tile_size;
2068
2069 unsigned tile_config;
64d7b8be 2070 uint32_t tile_mode_array[32];
65fcf668 2071 uint32_t active_cus;
0a96d72b
AD		 2072};
2073
8cc1a532
AD		 2074struct cik_asic {
2075 unsigned max_shader_engines;
2076 unsigned max_tile_pipes;
2077 unsigned max_cu_per_sh;
2078 unsigned max_sh_per_se;
2079 unsigned max_backends_per_se;
2080 unsigned max_texture_channel_caches;
2081 unsigned max_gprs;
2082 unsigned max_gs_threads;
2083 unsigned max_hw_contexts;
2084 unsigned sc_prim_fifo_size_frontend;
2085 unsigned sc_prim_fifo_size_backend;
2086 unsigned sc_hiz_tile_fifo_size;
2087 unsigned sc_earlyz_tile_fifo_size;
2088
2089 unsigned num_tile_pipes;
439a1cff 2090 unsigned backend_enable_mask;
8cc1a532
AD		 2091 unsigned backend_disable_mask_per_asic;
2092 unsigned backend_map;
2093 unsigned num_texture_channel_caches;
2094 unsigned mem_max_burst_length_bytes;
2095 unsigned mem_row_size_in_kb;
2096 unsigned shader_engine_tile_size;
2097 unsigned num_gpus;
2098 unsigned multi_gpu_tile_size;
2099
2100 unsigned tile_config;
39aee490 2101 uint32_t tile_mode_array[32];
32f79a8a 2102 uint32_t macrotile_mode_array[16];
65fcf668 2103 uint32_t active_cus;
8cc1a532
AD		 2104};
2105
068a117c
JG		 2106union radeon_asic_config {
2107 struct r300_asic r300;
551ebd83 2108 struct r100_asic r100;
3ce0a23d
JG		 2109 struct r600_asic r600;
2110 struct rv770_asic rv770;
32fcdbf4 2111 struct evergreen_asic evergreen;
fecf1d07 2112 struct cayman_asic cayman;
0a96d72b 2113 struct si_asic si;
8cc1a532 2114 struct cik_asic cik;
068a117c
JG		 2115};
2116
0a10c851
DV		 2117/*
2118 * asic initizalization from radeon_asic.c
2119 */
2120void radeon_agp_disable(struct radeon_device *rdev);
2121int radeon_asic_init(struct radeon_device *rdev);
2122
771fe6b9
JG		 2123
2124/*
2125 * IOCTL.
2126 */
2127int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2128 struct drm_file *filp);
2129int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2130 struct drm_file *filp);
2131int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2132 struct drm_file *file_priv);
2133int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2134 struct drm_file *file_priv);
2135int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2136 struct drm_file *file_priv);
2137int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2138 struct drm_file *file_priv);
2139int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2140 struct drm_file *filp);
2141int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2142 struct drm_file *filp);
2143int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2144 struct drm_file *filp);
2145int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2146 struct drm_file *filp);
721604a1
JG		 2147int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2148 struct drm_file *filp);
bda72d58
MO		 2149int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2150 struct drm_file *filp);
771fe6b9 2151int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 2152int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2153 struct drm_file *filp);
2154int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2155 struct drm_file *filp);
771fe6b9 2156
16cdf04d
AD		 2157/* VRAM scratch page for HDP bug, default vram page */
2158struct r600_vram_scratch {
87cbf8f2
AD		 2159 struct radeon_bo *robj;
2160 volatile uint32_t *ptr;
16cdf04d 2161 u64 gpu_addr;
87cbf8f2 2162};
771fe6b9 2163
fd64ca8a
LT		 2164/*
2165 * ACPI
2166 */
2167struct radeon_atif_notification_cfg {
2168 bool enabled;
2169 int command_code;
2170};
2171
2172struct radeon_atif_notifications {
2173 bool display_switch;
2174 bool expansion_mode_change;
2175 bool thermal_state;
2176 bool forced_power_state;
2177 bool system_power_state;
2178 bool display_conf_change;
2179 bool px_gfx_switch;
2180 bool brightness_change;
2181 bool dgpu_display_event;
2182};
2183
2184struct radeon_atif_functions {
2185 bool system_params;
2186 bool sbios_requests;
2187 bool select_active_disp;
2188 bool lid_state;
2189 bool get_tv_standard;
2190 bool set_tv_standard;
2191 bool get_panel_expansion_mode;
2192 bool set_panel_expansion_mode;
2193 bool temperature_change;
2194 bool graphics_device_types;
2195};
2196
2197struct radeon_atif {
2198 struct radeon_atif_notifications notifications;
2199 struct radeon_atif_functions functions;
2200 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2201 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2202};
7a1619b9 2203
e3a15920
AD		 2204struct radeon_atcs_functions {
2205 bool get_ext_state;
2206 bool pcie_perf_req;
2207 bool pcie_dev_rdy;
2208 bool pcie_bus_width;
2209};
2210
2211struct radeon_atcs {
2212 struct radeon_atcs_functions functions;
2213};
2214
771fe6b9
JG		 2215/*
2216 * Core structure, functions and helpers.
2217 */
2218typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2219typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2220
2221struct radeon_device {
9f022ddf 2222 struct device *dev;
771fe6b9
JG		 2223 struct drm_device *ddev;
2224 struct pci_dev *pdev;
dee53e7f 2225 struct rw_semaphore exclusive_lock;
771fe6b9 2226 /* ASIC */
068a117c 2227 union radeon_asic_config config;
771fe6b9
JG		 2228 enum radeon_family family;
2229 unsigned long flags;
2230 int usec_timeout;
2231 enum radeon_pll_errata pll_errata;
2232 int num_gb_pipes;
f779b3e5 2233 int num_z_pipes;
771fe6b9
JG		 2234 int disp_priority;
2235 /* BIOS */
2236 uint8_t *bios;
2237 bool is_atom_bios;
2238 uint16_t bios_header_start;
4c788679 2239 struct radeon_bo *stollen_vga_memory;
771fe6b9 2240 /* Register mmio */
4c9bc75c
DA		 2241 resource_size_t rmmio_base;
2242 resource_size_t rmmio_size;
2c385151
DV		 2243 /* protects concurrent MM_INDEX/DATA based register access */
2244 spinlock_t mmio_idx_lock;
fe78118c
AD		 2245 /* protects concurrent SMC based register access */
2246 spinlock_t smc_idx_lock;
0a5b7b0b
AD		 2247 /* protects concurrent PLL register access */
2248 spinlock_t pll_idx_lock;
2249 /* protects concurrent MC register access */
2250 spinlock_t mc_idx_lock;
2251 /* protects concurrent PCIE register access */
2252 spinlock_t pcie_idx_lock;
2253 /* protects concurrent PCIE_PORT register access */
2254 spinlock_t pciep_idx_lock;
2255 /* protects concurrent PIF register access */
2256 spinlock_t pif_idx_lock;
2257 /* protects concurrent CG register access */
2258 spinlock_t cg_idx_lock;
2259 /* protects concurrent UVD register access */
2260 spinlock_t uvd_idx_lock;
2261 /* protects concurrent RCU register access */
2262 spinlock_t rcu_idx_lock;
2263 /* protects concurrent DIDT register access */
2264 spinlock_t didt_idx_lock;
2265 /* protects concurrent ENDPOINT (audio) register access */
2266 spinlock_t end_idx_lock;
a0533fbf 2267 void __iomem *rmmio;
771fe6b9
JG		 2268 radeon_rreg_t mc_rreg;
2269 radeon_wreg_t mc_wreg;
2270 radeon_rreg_t pll_rreg;
2271 radeon_wreg_t pll_wreg;
de1b2898 2272 uint32_t pcie_reg_mask;
771fe6b9
JG		 2273 radeon_rreg_t pciep_rreg;
2274 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2275 /* io port */
2276 void __iomem *rio_mem;
2277 resource_size_t rio_mem_size;
771fe6b9
JG		 2278 struct radeon_clock clock;
2279 struct radeon_mc mc;
2280 struct radeon_gart gart;
2281 struct radeon_mode_info mode_info;
2282 struct radeon_scratch scratch;
75efdee1 2283 struct radeon_doorbell doorbell;
771fe6b9 2284 struct radeon_mman mman;
7465280c 2285 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2286 wait_queue_head_t fence_queue;
d6999bc7 2287 struct mutex ring_lock;
e32eb50d 2288 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2289 bool ib_pool_ready;
2290 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2291 struct radeon_irq irq;
2292 struct radeon_asic *asic;
2293 struct radeon_gem gem;
c93bb85b 2294 struct radeon_pm pm;
f2ba57b5 2295 struct radeon_uvd uvd;
d93f7937 2296 struct radeon_vce vce;
f657c2a7 2297 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2298 struct radeon_wb wb;
3ce0a23d 2299 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2300 bool shutdown;
2301 bool suspend;
ad49f501 2302 bool need_dma32;
733289c2 2303 bool accel_working;
a0a53aa8 2304 bool fastfb_working; /* IGP feature*/
f9eaf9ae 2305 bool needs_reset;
e024e110 2306 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2307 const struct firmware *me_fw; /* all family ME firmware */
2308 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2309 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2310 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2311 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2312 const struct firmware *mec_fw; /* CIK MEC firmware */
f2c6b0f4 2313 const struct firmware *mec2_fw; /* KV MEC2 firmware */
21a93e13 2314 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2315 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2316 const struct firmware *uvd_fw; /* UVD firmware */
d93f7937 2317 const struct firmware *vce_fw; /* VCE firmware */
629bd33c 2318 bool new_fw;
16cdf04d 2319 struct r600_vram_scratch vram_scratch;
3e5cb98d 2320 int msi_enabled; /* msi enabled */
d8f60cfc 2321 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2322 struct radeon_rlc rlc;
963e81f9 2323 struct radeon_mec mec;
d4877cf2 2324 struct work_struct hotplug_work;
f122c610 2325 struct work_struct audio_work;
8f61b34c 2326 struct work_struct reset_work;
18917b60 2327 int num_crtc; /* number of crtcs */
40bacf16 2328 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
948bee3f 2329 bool has_uvd;
b530602f 2330 struct r600_audio audio; /* audio stuff */
ce8f5370 2331 struct notifier_block acpi_nb;
9eba4a93 2332 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2333 struct drm_file *hyperz_filp;
9eba4a93 2334 struct drm_file *cmask_filp;
f376b94f
AD		 2335 /* i2c buses */
2336 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2337 /* debugfs */
2338 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2339 unsigned debugfs_count;
721604a1
JG		 2340 /* virtual memory */
2341 struct radeon_vm_manager vm_manager;
6759a0a7 2342 struct mutex gpu_clock_mutex;
67e8e3f9
MO		 2343 /* memory stats */
2344 atomic64_t vram_usage;
2345 atomic64_t gtt_usage;
2346 atomic64_t num_bytes_moved;
fd64ca8a
LT		 2347 /* ACPI interface */
2348 struct radeon_atif atif;
e3a15920 2349 struct radeon_atcs atcs;
f61d5b46
AD		 2350 /* srbm instance registers */
2351 struct mutex srbm_mutex;
64d8a728
AD		 2352 /* clock, powergating flags */
2353 u32 cg_flags;
2354 u32 pg_flags;
10ebc0bc
DA		 2355
2356 struct dev_pm_domain vga_pm_domain;
2357 bool have_disp_power_ref;
4807c5a8 2358 u32 px_quirk_flags;
71ecc97e
AD		 2359
2360 /* tracking pinned memory */
2361 u64 vram_pin_size;
2362 u64 gart_pin_size;
771fe6b9
JG		 2363};
2364
90c4cde9 2365bool radeon_is_px(struct drm_device *dev);
771fe6b9
JG		 2366int radeon_device_init(struct radeon_device *rdev,
2367 struct drm_device *ddev,
2368 struct pci_dev *pdev,
2369 uint32_t flags);
2370void radeon_device_fini(struct radeon_device *rdev);
2371int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2372
59bc1d89
LK		 2373#define RADEON_MIN_MMIO_SIZE 0x10000
2374
2375static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2376 bool always_indirect)
2377{
2378 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2379 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2380 return readl(((void __iomem *)rdev->rmmio) + reg);
2381 else {
2382 unsigned long flags;
2383 uint32_t ret;
2384
2385 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2386 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2387 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2388 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2389
2390 return ret;
2391 }
2392}
2393
2394static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2395 bool always_indirect)
2396{
2397 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2398 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2399 else {
2400 unsigned long flags;
2401
2402 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2403 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2404 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2405 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2406 }
2407}
2408
6fcbef7a
AK		 2409u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2410void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2411
d5754ab8
AL		 2412u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2413void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
75efdee1 2414
4c788679
JG		 2415/*
2416 * Cast helper
2417 */
2418#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 2419
2420/*
2421 * Registers read & write functions.
2422 */
a0533fbf
BH		 2423#define RREG8(reg) readb((rdev->rmmio) + (reg))
2424#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2425#define RREG16(reg) readw((rdev->rmmio) + (reg))
2426#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2427#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2428#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2429#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2430#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2431#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2432#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2433#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2434#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2435#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2436#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2437#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2438#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2439#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2440#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2441#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2442#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2443#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2444#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2445#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2446#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2447#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2448#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2449#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2450#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2451#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2452#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2453#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2454#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2455#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2456#define WREG32_P(reg, val, mask) \
2457 do { \
2458 uint32_t tmp_ = RREG32(reg); \
2459 tmp_ &= (mask); \
2460 tmp_ |= ((val) & ~(mask)); \
2461 WREG32(reg, tmp_); \
2462 } while (0)
d5169fc4 2463#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2464#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2465#define WREG32_PLL_P(reg, val, mask) \
2466 do { \
2467 uint32_t tmp_ = RREG32_PLL(reg); \
2468 tmp_ &= (mask); \
2469 tmp_ |= ((val) & ~(mask)); \
2470 WREG32_PLL(reg, tmp_); \
2471 } while (0)
2ef9bdfe 2472#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2473#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2474#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2475
d5754ab8
AL		 2476#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2477#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
75efdee1 2478
de1b2898
DA		 2479/*
2480 * Indirect registers accessor
2481 */
2482static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2483{
0a5b7b0b 2484 unsigned long flags;
de1b2898
DA		 2485 uint32_t r;
2486
0a5b7b0b 2487 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2488 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2489 r = RREG32(RADEON_PCIE_DATA);
0a5b7b0b 2490 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2491 return r;
2492}
2493
2494static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2495{
0a5b7b0b
AD		 2496 unsigned long flags;
2497
2498 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2499 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2500 WREG32(RADEON_PCIE_DATA, (v));
0a5b7b0b 2501 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2502}
2503
1d5d0c34
AD		 2504static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2505{
fe78118c 2506 unsigned long flags;
1d5d0c34
AD		 2507 u32 r;
2508
fe78118c 2509 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2510 WREG32(TN_SMC_IND_INDEX_0, (reg));
2511 r = RREG32(TN_SMC_IND_DATA_0);
fe78118c 2512 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2513 return r;
2514}
2515
2516static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2517{
fe78118c
AD		 2518 unsigned long flags;
2519
2520 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2521 WREG32(TN_SMC_IND_INDEX_0, (reg));
2522 WREG32(TN_SMC_IND_DATA_0, (v));
fe78118c 2523 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2524}
2525
ff82bbc4
AD		 2526static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2527{
0a5b7b0b 2528 unsigned long flags;
ff82bbc4
AD		 2529 u32 r;
2530
0a5b7b0b 2531 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2532 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2533 r = RREG32(R600_RCU_DATA);
0a5b7b0b 2534 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2535 return r;
2536}
2537
2538static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2539{
0a5b7b0b
AD		 2540 unsigned long flags;
2541
2542 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2543 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2544 WREG32(R600_RCU_DATA, (v));
0a5b7b0b 2545 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2546}
2547
46f9564a
AD		 2548static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2549{
0a5b7b0b 2550 unsigned long flags;
46f9564a
AD		 2551 u32 r;
2552
0a5b7b0b 2553 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2554 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2555 r = RREG32(EVERGREEN_CG_IND_DATA);
0a5b7b0b 2556 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2557 return r;
2558}
2559
2560static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2561{
0a5b7b0b
AD		 2562 unsigned long flags;
2563
2564 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2565 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2566 WREG32(EVERGREEN_CG_IND_DATA, (v));
0a5b7b0b 2567 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2568}
2569
792edd69
AD		 2570static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2571{
0a5b7b0b 2572 unsigned long flags;
792edd69
AD		 2573 u32 r;
2574
0a5b7b0b 2575 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2576 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2577 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
0a5b7b0b 2578 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2579 return r;
2580}
2581
2582static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2583{
0a5b7b0b
AD		 2584 unsigned long flags;
2585
2586 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2587 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2588 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
0a5b7b0b 2589 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2590}
2591
2592static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2593{
0a5b7b0b 2594 unsigned long flags;
792edd69
AD		 2595 u32 r;
2596
0a5b7b0b 2597 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2598 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2599 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
0a5b7b0b 2600 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2601 return r;
2602}
2603
2604static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2605{
0a5b7b0b
AD		 2606 unsigned long flags;
2607
2608 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2609 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2610 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
0a5b7b0b 2611 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2612}
2613
93656cdd
AD		 2614static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2615{
0a5b7b0b 2616 unsigned long flags;
93656cdd
AD		 2617 u32 r;
2618
0a5b7b0b 2619 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2620 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2621 r = RREG32(R600_UVD_CTX_DATA);
0a5b7b0b 2622 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2623 return r;
2624}
2625
2626static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2627{
0a5b7b0b
AD		 2628 unsigned long flags;
2629
2630 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2631 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2632 WREG32(R600_UVD_CTX_DATA, (v));
0a5b7b0b 2633 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2634}
2635
1d58234d
AD		 2636
2637static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2638{
0a5b7b0b 2639 unsigned long flags;
1d58234d
AD		 2640 u32 r;
2641
0a5b7b0b 2642 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2643 WREG32(CIK_DIDT_IND_INDEX, (reg));
2644 r = RREG32(CIK_DIDT_IND_DATA);
0a5b7b0b 2645 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2646 return r;
2647}
2648
2649static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2650{
0a5b7b0b
AD		 2651 unsigned long flags;
2652
2653 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2654 WREG32(CIK_DIDT_IND_INDEX, (reg));
2655 WREG32(CIK_DIDT_IND_DATA, (v));
0a5b7b0b 2656 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2657}
2658
771fe6b9
JG		 2659void r100_pll_errata_after_index(struct radeon_device *rdev);
2660
2661
2662/*
2663 * ASICs helpers.
2664 */
b995e433
DA		 2665#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2666 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2667#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2668 (rdev->family == CHIP_RV200) || \
2669 (rdev->family == CHIP_RS100) || \
2670 (rdev->family == CHIP_RS200) || \
2671 (rdev->family == CHIP_RV250) || \
2672 (rdev->family == CHIP_RV280) || \
2673 (rdev->family == CHIP_RS300))
2674#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2675 (rdev->family == CHIP_RV350) || \
2676 (rdev->family == CHIP_R350) || \
2677 (rdev->family == CHIP_RV380) || \
2678 (rdev->family == CHIP_R420) || \
2679 (rdev->family == CHIP_R423) || \
2680 (rdev->family == CHIP_RV410) || \
2681 (rdev->family == CHIP_RS400) || \
2682 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2683#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2684 (rdev->ddev->pdev->device == 0x9443) || \
2685 (rdev->ddev->pdev->device == 0x944B) || \
2686 (rdev->ddev->pdev->device == 0x9506) || \
2687 (rdev->ddev->pdev->device == 0x9509) || \
2688 (rdev->ddev->pdev->device == 0x950F) || \
2689 (rdev->ddev->pdev->device == 0x689C) || \
2690 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2691#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2692#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2693 (rdev->family == CHIP_RS690) || \
2694 (rdev->family == CHIP_RS740) || \
2695 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2696#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2697#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2698#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2699#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2700 (rdev->flags & RADEON_IS_IGP))
1fe18305 2701#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2702#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2703#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2704 (rdev->flags & RADEON_IS_IGP))
624d3524 2705#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2706#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2707#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
be0949f5
AD		 2708#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2709#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
89d2618d
AD		 2710#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2711 (rdev->family == CHIP_MULLINS))
771fe6b9 2712
dc50ba7f
AD		 2713#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2714 (rdev->ddev->pdev->device == 0x6850) || \
2715 (rdev->ddev->pdev->device == 0x6858) || \
2716 (rdev->ddev->pdev->device == 0x6859) || \
2717 (rdev->ddev->pdev->device == 0x6840) || \
2718 (rdev->ddev->pdev->device == 0x6841) || \
2719 (rdev->ddev->pdev->device == 0x6842) || \
2720 (rdev->ddev->pdev->device == 0x6843))
2721
771fe6b9
JG		 2722/*
2723 * BIOS helpers.
2724 */
2725#define RBIOS8(i) (rdev->bios[i])
2726#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2727#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2728
2729int radeon_combios_init(struct radeon_device *rdev);
2730void radeon_combios_fini(struct radeon_device *rdev);
2731int radeon_atombios_init(struct radeon_device *rdev);
2732void radeon_atombios_fini(struct radeon_device *rdev);
2733
2734
2735/*
2736 * RING helpers.
2737 */
ce580fab 2738#if DRM_DEBUG_CODE == 0
e32eb50d 2739static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2740{
e32eb50d
CK		 2741 ring->ring[ring->wptr++] = v;
2742 ring->wptr &= ring->ptr_mask;
2743 ring->count_dw--;
2744 ring->ring_free_dw--;
771fe6b9 2745}
ce580fab
AK		 2746#else
2747/* With debugging this is just too big to inline */
e32eb50d 2748void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
ce580fab 2749#endif
771fe6b9
JG		 2750
2751/*
2752 * ASICs macro.
2753 */
068a117c 2754#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2755#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2756#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2757#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2758#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2759#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2760#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850 2761#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
77497f27 2762#define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f))
05b07147
CK		 2763#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2764#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
43f1214a 2765#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
76a0df85
CK		 2766#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2767#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2768#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2769#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2770#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2771#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2772#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2773#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2774#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2775#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2776#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2777#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2778#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2779#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2780#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2781#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2782#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2783#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2784#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
27cd7769
AD		 2785#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2786#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2787#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2788#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2789#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2790#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2791#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2792#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2793#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2794#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2795#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2796#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2797#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2798#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
b59b7333 2799#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
6bd1c385 2800#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2801#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2802#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2803#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2804#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2805#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2806#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2807#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2808#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2809#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2810#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2811#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2812#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2813#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8 2814#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
157fa14d 2815#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
69b62ad8
AD		 2816#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2817#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2818#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2819#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2820#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2821#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2822#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
914a8987 2823#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
da321c8a 2824#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2825#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2826#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2827#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2828#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2829#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2830#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2831#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2832#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2833#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2834#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2835#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2836#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
1c71bda0 2837#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
771fe6b9 2838
6cf8a3f5 2839/* Common functions */
700a0cc0 2840/* AGP */
90aca4d2 2841extern int radeon_gpu_reset(struct radeon_device *rdev);
1a0041b8 2842extern void radeon_pci_config_reset(struct radeon_device *rdev);
410a3418 2843extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2844extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2845extern int radeon_modeset_init(struct radeon_device *rdev);
2846extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2847extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2848extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2849extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2850extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2851extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2852extern void radeon_wb_fini(struct radeon_device *rdev);
2853extern int radeon_wb_init(struct radeon_device *rdev);
2854extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2855extern void radeon_surface_init(struct radeon_device *rdev);
2856extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2857extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2858extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2859extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2860extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 2861extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2862extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
10ebc0bc
DA		 2863extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2864extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
53595338 2865extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2866extern void radeon_program_register_sequence(struct radeon_device *rdev,
2867 const u32 *registers,
2868 const u32 array_size);
6cf8a3f5 2869
721604a1
JG		 2870/*
2871 * vm
2872 */
2873int radeon_vm_manager_init(struct radeon_device *rdev);
2874void radeon_vm_manager_fini(struct radeon_device *rdev);
6d2f2944 2875int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2876void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
df0af440
CK		 2877struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2878 struct radeon_vm *vm,
2879 struct list_head *head);
ee60e29f
CK		 2880struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2881 struct radeon_vm *vm, int ring);
fa688343
CK		 2882void radeon_vm_flush(struct radeon_device *rdev,
2883 struct radeon_vm *vm,
2884 int ring);
ee60e29f
CK		 2885void radeon_vm_fence(struct radeon_device *rdev,
2886 struct radeon_vm *vm,
2887 struct radeon_fence *fence);
dce34bfd 2888uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
6d2f2944
CK		 2889int radeon_vm_update_page_directory(struct radeon_device *rdev,
2890 struct radeon_vm *vm);
036bf46a
CK		 2891int radeon_vm_clear_freed(struct radeon_device *rdev,
2892 struct radeon_vm *vm);
e31ad969
CK		 2893int radeon_vm_clear_invalids(struct radeon_device *rdev,
2894 struct radeon_vm *vm);
9c57a6bd 2895int radeon_vm_bo_update(struct radeon_device *rdev,
036bf46a 2896 struct radeon_bo_va *bo_va,
9c57a6bd 2897 struct ttm_mem_reg *mem);
721604a1
JG		 2898void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2899 struct radeon_bo *bo);
421ca7ab
CK		 2900struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2901 struct radeon_bo *bo);
e971bd5e
CK		 2902struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2903 struct radeon_vm *vm,
2904 struct radeon_bo *bo);
2905int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2906 struct radeon_bo_va *bo_va,
2907 uint64_t offset,
2908 uint32_t flags);
036bf46a
CK		 2909void radeon_vm_bo_rmv(struct radeon_device *rdev,
2910 struct radeon_bo_va *bo_va);
721604a1 2911
f122c610
AD		 2912/* audio */
2913void r600_audio_update_hdmi(struct work_struct *work);
b530602f
AD		 2914struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2915struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
832eafaf
AD		 2916void r600_audio_enable(struct radeon_device *rdev,
2917 struct r600_audio_pin *pin,
2918 bool enable);
2919void dce6_audio_enable(struct radeon_device *rdev,
2920 struct r600_audio_pin *pin,
2921 bool enable);
721604a1 2922
16cdf04d
AD		 2923/*
2924 * R600 vram scratch functions
2925 */
2926int r600_vram_scratch_init(struct radeon_device *rdev);
2927void r600_vram_scratch_fini(struct radeon_device *rdev);
2928
285484e2
JG		 2929/*
2930 * r600 cs checking helper
2931 */
2932unsigned r600_mip_minify(unsigned size, unsigned level);
2933bool r600_fmt_is_valid_color(u32 format);
2934bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2935int r600_fmt_get_blocksize(u32 format);
2936int r600_fmt_get_nblocksx(u32 format, u32 w);
2937int r600_fmt_get_nblocksy(u32 format, u32 h);
2938
3574dda4
DV		 2939/*
2940 * r600 functions used by radeon_encoder.c
2941 */
1b688d08
RM		 2942struct radeon_hdmi_acr {
2943 u32 clock;
2944
2945 int n_32khz;
2946 int cts_32khz;
2947
2948 int n_44_1khz;
2949 int cts_44_1khz;
2950
2951 int n_48khz;
2952 int cts_48khz;
2953
2954};
2955
e55d3e6c
RM		 2956extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2957
416a2bd2
AD		 2958extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2959 u32 tiling_pipe_num,
2960 u32 max_rb_num,
2961 u32 total_max_rb_num,
2962 u32 enabled_rb_mask);
fe251e2f 2963
e55d3e6c
RM		 2964/*
2965 * evergreen functions used by radeon_encoder.c
2966 */
2967
0af62b01 2968extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2969extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2970
c4917074
AD		 2971/* radeon_acpi.c */
2972#if defined(CONFIG_ACPI)
2973extern int radeon_acpi_init(struct radeon_device *rdev);
2974extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2975extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2976extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2977 u8 perf_req, bool advertise);
dc50ba7f 2978extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2979#else
2980static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2981static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2982#endif
d7a2952f 2983
c38f34b5
IH		 2984int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2985 struct radeon_cs_packet *pkt,
2986 unsigned idx);
9ffb7a6d 2987bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2988void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2989 struct radeon_cs_packet *pkt);
e9716993
IH		 2990int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2991 struct radeon_cs_reloc **cs_reloc,
2992 int nomm);
40592a17
IH		 2993int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2994 uint32_t *vline_start_end,
2995 uint32_t *vline_status);
c38f34b5 2996
4c788679
JG		 2997#include "radeon_object.h"
2998
771fe6b9 2999#endif
Linux kernel - Deliverables
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