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drm/radeon/kms: Add support for interrupts on r6xx/r7xx chips (v3)
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31#include "radeon_object.h"
32
33/* TODO: Here are things that needs to be done :
34 * - surface allocator & initializer : (bit like scratch reg) should
35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
36 * related to surface
37 * - WB : write back stuff (do it bit like scratch reg things)
38 * - Vblank : look at Jesse's rework and what we should do
39 * - r600/r700: gart & cp
40 * - cs : clean cs ioctl use bitmap & things like that.
41 * - power management stuff
42 * - Barrier in gart code
43 * - Unmappabled vram ?
44 * - TESTING, TESTING, TESTING
45 */
46
d39c3b89
JG		 47/* Initialization path:
48 * We expect that acceleration initialization might fail for various
49 * reasons even thought we work hard to make it works on most
50 * configurations. In order to still have a working userspace in such
51 * situation the init path must succeed up to the memory controller
52 * initialization point. Failure before this point are considered as
53 * fatal error. Here is the init callchain :
54 * radeon_device_init perform common structure, mutex initialization
55 * asic_init setup the GPU memory layout and perform all
56 * one time initialization (failure in this
57 * function are considered fatal)
58 * asic_startup setup the GPU acceleration, in order to
59 * follow guideline the first thing this
60 * function should do is setting the GPU
61 * memory controller (only MC setup failure
62 * are considered as fatal)
63 */
64
771fe6b9
JG		 65#include <asm/atomic.h>
66#include <linux/wait.h>
67#include <linux/list.h>
68#include <linux/kref.h>
69
c2142715 70#include "radeon_family.h"
771fe6b9
JG		 71#include "radeon_mode.h"
72#include "radeon_reg.h"
771fe6b9
JG		 73
74/*
75 * Modules parameters.
76 */
77extern int radeon_no_wb;
78extern int radeon_modeset;
79extern int radeon_dynclks;
80extern int radeon_r4xx_atom;
81extern int radeon_agpmode;
82extern int radeon_vram_limit;
83extern int radeon_gart_size;
84extern int radeon_benchmarking;
ecc0b326 85extern int radeon_testing;
771fe6b9 86extern int radeon_connector_table;
4ce001ab 87extern int radeon_tv;
771fe6b9
JG		 88
89/*
90 * Copy from radeon_drv.h so we don't have to include both and have conflicting
91 * symbol;
92 */
93#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
94#define RADEON_IB_POOL_SIZE 16
95#define RADEON_DEBUGFS_MAX_NUM_FILES 32
96#define RADEONFB_CONN_LIMIT 4
f657c2a7 97#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 98
771fe6b9
JG		 99/*
100 * Errata workarounds.
101 */
102enum radeon_pll_errata {
103 CHIP_ERRATA_R300_CG = 0x00000001,
104 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
105 CHIP_ERRATA_PLL_DELAY = 0x00000004
106};
107
108
109struct radeon_device;
110
111
112/*
113 * BIOS.
114 */
115bool radeon_get_bios(struct radeon_device *rdev);
116
3ce0a23d 117
771fe6b9 118/*
3ce0a23d 119 * Dummy page
771fe6b9 120 */
3ce0a23d
JG		 121struct radeon_dummy_page {
122 struct page *page;
123 dma_addr_t addr;
124};
125int radeon_dummy_page_init(struct radeon_device *rdev);
126void radeon_dummy_page_fini(struct radeon_device *rdev);
127
771fe6b9 128
3ce0a23d
JG		 129/*
130 * Clocks
131 */
771fe6b9
JG		 132struct radeon_clock {
133 struct radeon_pll p1pll;
134 struct radeon_pll p2pll;
135 struct radeon_pll spll;
136 struct radeon_pll mpll;
137 /* 10 Khz units */
138 uint32_t default_mclk;
139 uint32_t default_sclk;
140};
141
7433874e
RM		 142/*
143 * Power management
144 */
145int radeon_pm_init(struct radeon_device *rdev);
3ce0a23d 146
771fe6b9
JG		 147/*
148 * Fences.
149 */
150struct radeon_fence_driver {
151 uint32_t scratch_reg;
152 atomic_t seq;
153 uint32_t last_seq;
154 unsigned long count_timeout;
155 wait_queue_head_t queue;
156 rwlock_t lock;
157 struct list_head created;
158 struct list_head emited;
159 struct list_head signaled;
160};
161
162struct radeon_fence {
163 struct radeon_device *rdev;
164 struct kref kref;
165 struct list_head list;
166 /* protected by radeon_fence.lock */
167 uint32_t seq;
168 unsigned long timeout;
169 bool emited;
170 bool signaled;
171};
172
173int radeon_fence_driver_init(struct radeon_device *rdev);
174void radeon_fence_driver_fini(struct radeon_device *rdev);
175int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
176int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
177void radeon_fence_process(struct radeon_device *rdev);
178bool radeon_fence_signaled(struct radeon_fence *fence);
179int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
180int radeon_fence_wait_next(struct radeon_device *rdev);
181int radeon_fence_wait_last(struct radeon_device *rdev);
182struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
183void radeon_fence_unref(struct radeon_fence **fence);
184
e024e110
DA		 185/*
186 * Tiling registers
187 */
188struct radeon_surface_reg {
189 struct radeon_object *robj;
190};
191
192#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 193
194/*
195 * Radeon buffer.
196 */
197struct radeon_object;
198
199struct radeon_object_list {
200 struct list_head list;
201 struct radeon_object *robj;
202 uint64_t gpu_offset;
203 unsigned rdomain;
204 unsigned wdomain;
e024e110 205 uint32_t tiling_flags;
771fe6b9
JG		 206};
207
208int radeon_object_init(struct radeon_device *rdev);
209void radeon_object_fini(struct radeon_device *rdev);
210int radeon_object_create(struct radeon_device *rdev,
211 struct drm_gem_object *gobj,
212 unsigned long size,
213 bool kernel,
214 uint32_t domain,
215 bool interruptible,
216 struct radeon_object **robj_ptr);
217int radeon_object_kmap(struct radeon_object *robj, void **ptr);
218void radeon_object_kunmap(struct radeon_object *robj);
219void radeon_object_unref(struct radeon_object **robj);
220int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
221 uint64_t *gpu_addr);
222void radeon_object_unpin(struct radeon_object *robj);
223int radeon_object_wait(struct radeon_object *robj);
cefb87ef 224int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement);
771fe6b9
JG		 225int radeon_object_evict_vram(struct radeon_device *rdev);
226int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
227void radeon_object_force_delete(struct radeon_device *rdev);
228void radeon_object_list_add_object(struct radeon_object_list *lobj,
229 struct list_head *head);
230int radeon_object_list_validate(struct list_head *head, void *fence);
231void radeon_object_list_unvalidate(struct list_head *head);
232void radeon_object_list_clean(struct list_head *head);
233int radeon_object_fbdev_mmap(struct radeon_object *robj,
234 struct vm_area_struct *vma);
235unsigned long radeon_object_size(struct radeon_object *robj);
e024e110
DA		 236void radeon_object_clear_surface_reg(struct radeon_object *robj);
237int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
238 bool force_drop);
239void radeon_object_set_tiling_flags(struct radeon_object *robj,
240 uint32_t tiling_flags, uint32_t pitch);
241void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
242void radeon_bo_move_notify(struct ttm_buffer_object *bo,
243 struct ttm_mem_reg *mem);
244void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
771fe6b9
JG		 245/*
246 * GEM objects.
247 */
248struct radeon_gem {
249 struct list_head objects;
250};
251
252int radeon_gem_init(struct radeon_device *rdev);
253void radeon_gem_fini(struct radeon_device *rdev);
254int radeon_gem_object_create(struct radeon_device *rdev, int size,
255 int alignment, int initial_domain,
256 bool discardable, bool kernel,
257 bool interruptible,
258 struct drm_gem_object **obj);
259int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
260 uint64_t *gpu_addr);
261void radeon_gem_object_unpin(struct drm_gem_object *obj);
262
263
264/*
265 * GART structures, functions & helpers
266 */
267struct radeon_mc;
268
269struct radeon_gart_table_ram {
270 volatile uint32_t *ptr;
271};
272
273struct radeon_gart_table_vram {
274 struct radeon_object *robj;
275 volatile uint32_t *ptr;
276};
277
278union radeon_gart_table {
279 struct radeon_gart_table_ram ram;
280 struct radeon_gart_table_vram vram;
281};
282
a77f1718
MT		 283#define RADEON_GPU_PAGE_SIZE 4096
284
771fe6b9
JG		 285struct radeon_gart {
286 dma_addr_t table_addr;
287 unsigned num_gpu_pages;
288 unsigned num_cpu_pages;
289 unsigned table_size;
290 union radeon_gart_table table;
291 struct page **pages;
292 dma_addr_t *pages_addr;
293 bool ready;
294};
295
296int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
297void radeon_gart_table_ram_free(struct radeon_device *rdev);
298int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
299void radeon_gart_table_vram_free(struct radeon_device *rdev);
300int radeon_gart_init(struct radeon_device *rdev);
301void radeon_gart_fini(struct radeon_device *rdev);
302void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
303 int pages);
304int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
305 int pages, struct page **pagelist);
306
307
308/*
309 * GPU MC structures, functions & helpers
310 */
311struct radeon_mc {
312 resource_size_t aper_size;
313 resource_size_t aper_base;
314 resource_size_t agp_base;
7a50f01a
DA		 315 /* for some chips with <= 32MB we need to lie
316 * about vram size near mc fb location */
3ce0a23d
JG		 317 u64 mc_vram_size;
318 u64 gtt_location;
319 u64 gtt_size;
320 u64 gtt_start;
321 u64 gtt_end;
322 u64 vram_location;
323 u64 vram_start;
324 u64 vram_end;
771fe6b9 325 unsigned vram_width;
3ce0a23d 326 u64 real_vram_size;
771fe6b9
JG		 327 int vram_mtrr;
328 bool vram_is_ddr;
329};
330
331int radeon_mc_setup(struct radeon_device *rdev);
332
333
334/*
335 * GPU scratch registers structures, functions & helpers
336 */
337struct radeon_scratch {
338 unsigned num_reg;
339 bool free[32];
340 uint32_t reg[32];
341};
342
343int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
344void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
345
346
347/*
348 * IRQS.
349 */
350struct radeon_irq {
351 bool installed;
352 bool sw_int;
353 /* FIXME: use a define max crtc rather than hardcode it */
354 bool crtc_vblank_int[2];
355};
356
357int radeon_irq_kms_init(struct radeon_device *rdev);
358void radeon_irq_kms_fini(struct radeon_device *rdev);
359
360
361/*
362 * CP & ring.
363 */
364struct radeon_ib {
365 struct list_head list;
366 unsigned long idx;
367 uint64_t gpu_addr;
368 struct radeon_fence *fence;
513bcb46 369 uint32_t *ptr;
771fe6b9
JG		 370 uint32_t length_dw;
371};
372
ecb114a1
DA		 373/*
374 * locking -
375 * mutex protects scheduled_ibs, ready, alloc_bm
376 */
771fe6b9
JG		 377struct radeon_ib_pool {
378 struct mutex mutex;
379 struct radeon_object *robj;
380 struct list_head scheduled_ibs;
381 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
382 bool ready;
383 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
384};
385
386struct radeon_cp {
387 struct radeon_object *ring_obj;
388 volatile uint32_t *ring;
389 unsigned rptr;
390 unsigned wptr;
391 unsigned wptr_old;
392 unsigned ring_size;
393 unsigned ring_free_dw;
394 int count_dw;
395 uint64_t gpu_addr;
396 uint32_t align_mask;
397 uint32_t ptr_mask;
398 struct mutex mutex;
399 bool ready;
400};
401
d8f60cfc
AD		 402/*
403 * R6xx+ IH ring
404 */
405struct r600_ih {
406 struct radeon_object *ring_obj;
407 volatile uint32_t *ring;
408 unsigned rptr;
409 unsigned wptr;
410 unsigned wptr_old;
411 unsigned ring_size;
412 uint64_t gpu_addr;
413 uint32_t align_mask;
414 uint32_t ptr_mask;
415 spinlock_t lock;
416 bool enabled;
417};
418
3ce0a23d
JG		 419struct r600_blit {
420 struct radeon_object *shader_obj;
421 u64 shader_gpu_addr;
422 u32 vs_offset, ps_offset;
423 u32 state_offset;
424 u32 state_len;
425 u32 vb_used, vb_total;
426 struct radeon_ib *vb_ib;
427};
428
771fe6b9
JG		 429int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
430void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
431int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
432int radeon_ib_pool_init(struct radeon_device *rdev);
433void radeon_ib_pool_fini(struct radeon_device *rdev);
434int radeon_ib_test(struct radeon_device *rdev);
435/* Ring access between begin & end cannot sleep */
436void radeon_ring_free_size(struct radeon_device *rdev);
437int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
438void radeon_ring_unlock_commit(struct radeon_device *rdev);
439void radeon_ring_unlock_undo(struct radeon_device *rdev);
440int radeon_ring_test(struct radeon_device *rdev);
441int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
442void radeon_ring_fini(struct radeon_device *rdev);
443
444
445/*
446 * CS.
447 */
448struct radeon_cs_reloc {
449 struct drm_gem_object *gobj;
450 struct radeon_object *robj;
451 struct radeon_object_list lobj;
452 uint32_t handle;
453 uint32_t flags;
454};
455
456struct radeon_cs_chunk {
457 uint32_t chunk_id;
458 uint32_t length_dw;
513bcb46
DA		 459 int kpage_idx[2];
460 uint32_t *kpage[2];
771fe6b9 461 uint32_t *kdata;
513bcb46
DA		 462 void __user *user_ptr;
463 int last_copied_page;
464 int last_page_index;
771fe6b9
JG		 465};
466
467struct radeon_cs_parser {
468 struct radeon_device *rdev;
469 struct drm_file *filp;
470 /* chunks */
471 unsigned nchunks;
472 struct radeon_cs_chunk *chunks;
473 uint64_t *chunks_array;
474 /* IB */
475 unsigned idx;
476 /* relocations */
477 unsigned nrelocs;
478 struct radeon_cs_reloc *relocs;
479 struct radeon_cs_reloc **relocs_ptr;
480 struct list_head validated;
481 /* indices of various chunks */
482 int chunk_ib_idx;
483 int chunk_relocs_idx;
484 struct radeon_ib *ib;
485 void *track;
3ce0a23d 486 unsigned family;
513bcb46 487 int parser_error;
771fe6b9
JG		 488};
489
513bcb46
DA		 490extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
491extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
492
493
494static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
495{
496 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
497 u32 pg_idx, pg_offset;
498 u32 idx_value = 0;
499 int new_page;
500
501 pg_idx = (idx * 4) / PAGE_SIZE;
502 pg_offset = (idx * 4) % PAGE_SIZE;
503
504 if (ibc->kpage_idx[0] == pg_idx)
505 return ibc->kpage[0][pg_offset/4];
506 if (ibc->kpage_idx[1] == pg_idx)
507 return ibc->kpage[1][pg_offset/4];
508
509 new_page = radeon_cs_update_pages(p, pg_idx);
510 if (new_page < 0) {
511 p->parser_error = new_page;
512 return 0;
513 }
514
515 idx_value = ibc->kpage[new_page][pg_offset/4];
516 return idx_value;
517}
518
771fe6b9
JG		 519struct radeon_cs_packet {
520 unsigned idx;
521 unsigned type;
522 unsigned reg;
523 unsigned opcode;
524 int count;
525 unsigned one_reg_wr;
526};
527
528typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
529 struct radeon_cs_packet *pkt,
530 unsigned idx, unsigned reg);
531typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
532 struct radeon_cs_packet *pkt);
533
534
535/*
536 * AGP
537 */
538int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 539void radeon_agp_resume(struct radeon_device *rdev);
771fe6b9
JG		 540void radeon_agp_fini(struct radeon_device *rdev);
541
542
543/*
544 * Writeback
545 */
546struct radeon_wb {
547 struct radeon_object *wb_obj;
548 volatile uint32_t *wb;
549 uint64_t gpu_addr;
550};
551
c93bb85b
JG		 552/**
553 * struct radeon_pm - power management datas
554 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
555 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
556 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
557 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
558 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
559 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
560 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
561 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
562 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
563 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
564 * @needed_bandwidth: current bandwidth needs
565 *
566 * It keeps track of various data needed to take powermanagement decision.
567 * Bandwith need is used to determine minimun clock of the GPU and memory.
568 * Equation between gpu/memory clock and available bandwidth is hw dependent
569 * (type of memory, bus size, efficiency, ...)
570 */
571struct radeon_pm {
572 fixed20_12 max_bandwidth;
573 fixed20_12 igp_sideport_mclk;
574 fixed20_12 igp_system_mclk;
575 fixed20_12 igp_ht_link_clk;
576 fixed20_12 igp_ht_link_width;
577 fixed20_12 k8_bandwidth;
578 fixed20_12 sideport_bandwidth;
579 fixed20_12 ht_bandwidth;
580 fixed20_12 core_bandwidth;
581 fixed20_12 sclk;
582 fixed20_12 needed_bandwidth;
583};
584
771fe6b9
JG		 585
586/*
587 * Benchmarking
588 */
589void radeon_benchmark(struct radeon_device *rdev);
590
591
ecc0b326
MD		 592/*
593 * Testing
594 */
595void radeon_test_moves(struct radeon_device *rdev);
596
597
771fe6b9
JG		 598/*
599 * Debugfs
600 */
601int radeon_debugfs_add_files(struct radeon_device *rdev,
602 struct drm_info_list *files,
603 unsigned nfiles);
604int radeon_debugfs_fence_init(struct radeon_device *rdev);
605int r100_debugfs_rbbm_init(struct radeon_device *rdev);
606int r100_debugfs_cp_init(struct radeon_device *rdev);
607
608
609/*
610 * ASIC specific functions.
611 */
612struct radeon_asic {
068a117c 613 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 614 void (*fini)(struct radeon_device *rdev);
615 int (*resume)(struct radeon_device *rdev);
616 int (*suspend)(struct radeon_device *rdev);
28d52043 617 void (*vga_set_state)(struct radeon_device *rdev, bool state);
771fe6b9 618 int (*gpu_reset)(struct radeon_device *rdev);
771fe6b9
JG		 619 void (*gart_tlb_flush)(struct radeon_device *rdev);
620 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
621 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
622 void (*cp_fini)(struct radeon_device *rdev);
623 void (*cp_disable)(struct radeon_device *rdev);
3ce0a23d 624 void (*cp_commit)(struct radeon_device *rdev);
771fe6b9 625 void (*ring_start)(struct radeon_device *rdev);
3ce0a23d
JG		 626 int (*ring_test)(struct radeon_device *rdev);
627 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
771fe6b9
JG		 628 int (*irq_set)(struct radeon_device *rdev);
629 int (*irq_process)(struct radeon_device *rdev);
7ed220d7 630 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 631 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
632 int (*cs_parse)(struct radeon_cs_parser *p);
633 int (*copy_blit)(struct radeon_device *rdev,
634 uint64_t src_offset,
635 uint64_t dst_offset,
636 unsigned num_pages,
637 struct radeon_fence *fence);
638 int (*copy_dma)(struct radeon_device *rdev,
639 uint64_t src_offset,
640 uint64_t dst_offset,
641 unsigned num_pages,
642 struct radeon_fence *fence);
643 int (*copy)(struct radeon_device *rdev,
644 uint64_t src_offset,
645 uint64_t dst_offset,
646 unsigned num_pages,
647 struct radeon_fence *fence);
7433874e 648 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
771fe6b9 649 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
7433874e 650 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
771fe6b9
JG		 651 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
652 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
653 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
e024e110
DA		 654 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
655 uint32_t tiling_flags, uint32_t pitch,
656 uint32_t offset, uint32_t obj_size);
657 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
c93bb85b 658 void (*bandwidth_update)(struct radeon_device *rdev);
23956dfa 659 void (*hdp_flush)(struct radeon_device *rdev);
771fe6b9
JG		 660};
661
21f9a437
JG		 662/*
663 * Asic structures
664 */
551ebd83
DA		 665struct r100_asic {
666 const unsigned *reg_safe_bm;
667 unsigned reg_safe_bm_size;
668};
669
21f9a437
JG		 670struct r300_asic {
671 const unsigned *reg_safe_bm;
672 unsigned reg_safe_bm_size;
673};
674
675struct r600_asic {
676 unsigned max_pipes;
677 unsigned max_tile_pipes;
678 unsigned max_simds;
679 unsigned max_backends;
680 unsigned max_gprs;
681 unsigned max_threads;
682 unsigned max_stack_entries;
683 unsigned max_hw_contexts;
684 unsigned max_gs_threads;
685 unsigned sx_max_export_size;
686 unsigned sx_max_export_pos_size;
687 unsigned sx_max_export_smx_size;
688 unsigned sq_num_cf_insts;
689};
690
691struct rv770_asic {
692 unsigned max_pipes;
693 unsigned max_tile_pipes;
694 unsigned max_simds;
695 unsigned max_backends;
696 unsigned max_gprs;
697 unsigned max_threads;
698 unsigned max_stack_entries;
699 unsigned max_hw_contexts;
700 unsigned max_gs_threads;
701 unsigned sx_max_export_size;
702 unsigned sx_max_export_pos_size;
703 unsigned sx_max_export_smx_size;
704 unsigned sq_num_cf_insts;
705 unsigned sx_num_of_sets;
706 unsigned sc_prim_fifo_size;
707 unsigned sc_hiz_tile_fifo_size;
708 unsigned sc_earlyz_tile_fifo_fize;
709};
710
068a117c
JG		 711union radeon_asic_config {
712 struct r300_asic r300;
551ebd83 713 struct r100_asic r100;
3ce0a23d
JG		 714 struct r600_asic r600;
715 struct rv770_asic rv770;
068a117c
JG		 716};
717
771fe6b9
JG		 718
719/*
720 * IOCTL.
721 */
722int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
723 struct drm_file *filp);
724int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
725 struct drm_file *filp);
726int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
727 struct drm_file *file_priv);
728int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
729 struct drm_file *file_priv);
730int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
731 struct drm_file *file_priv);
732int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
733 struct drm_file *file_priv);
734int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
735 struct drm_file *filp);
736int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
737 struct drm_file *filp);
738int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
739 struct drm_file *filp);
740int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
741 struct drm_file *filp);
742int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 743int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
744 struct drm_file *filp);
745int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
746 struct drm_file *filp);
771fe6b9
JG		 747
748
749/*
750 * Core structure, functions and helpers.
751 */
752typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
753typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
754
755struct radeon_device {
9f022ddf 756 struct device *dev;
771fe6b9
JG		 757 struct drm_device *ddev;
758 struct pci_dev *pdev;
759 /* ASIC */
068a117c 760 union radeon_asic_config config;
771fe6b9
JG		 761 enum radeon_family family;
762 unsigned long flags;
763 int usec_timeout;
764 enum radeon_pll_errata pll_errata;
765 int num_gb_pipes;
f779b3e5 766 int num_z_pipes;
771fe6b9
JG		 767 int disp_priority;
768 /* BIOS */
769 uint8_t *bios;
770 bool is_atom_bios;
771 uint16_t bios_header_start;
772 struct radeon_object *stollen_vga_memory;
773 struct fb_info *fbdev_info;
774 struct radeon_object *fbdev_robj;
775 struct radeon_framebuffer *fbdev_rfb;
776 /* Register mmio */
4c9bc75c
DA		 777 resource_size_t rmmio_base;
778 resource_size_t rmmio_size;
771fe6b9 779 void *rmmio;
771fe6b9
JG		 780 radeon_rreg_t mc_rreg;
781 radeon_wreg_t mc_wreg;
782 radeon_rreg_t pll_rreg;
783 radeon_wreg_t pll_wreg;
de1b2898 784 uint32_t pcie_reg_mask;
771fe6b9
JG		 785 radeon_rreg_t pciep_rreg;
786 radeon_wreg_t pciep_wreg;
787 struct radeon_clock clock;
788 struct radeon_mc mc;
789 struct radeon_gart gart;
790 struct radeon_mode_info mode_info;
791 struct radeon_scratch scratch;
792 struct radeon_mman mman;
793 struct radeon_fence_driver fence_drv;
794 struct radeon_cp cp;
795 struct radeon_ib_pool ib_pool;
796 struct radeon_irq irq;
797 struct radeon_asic *asic;
798 struct radeon_gem gem;
c93bb85b 799 struct radeon_pm pm;
f657c2a7 800 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9
JG		 801 struct mutex cs_mutex;
802 struct radeon_wb wb;
3ce0a23d 803 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 804 bool gpu_lockup;
805 bool shutdown;
806 bool suspend;
ad49f501 807 bool need_dma32;
733289c2 808 bool accel_working;
e024e110 809 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 810 const struct firmware *me_fw; /* all family ME firmware */
811 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 812 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
3ce0a23d 813 struct r600_blit r600_blit;
3e5cb98d 814 int msi_enabled; /* msi enabled */
d8f60cfc 815 struct r600_ih ih; /* r6/700 interrupt ring */
771fe6b9
JG		 816};
817
818int radeon_device_init(struct radeon_device *rdev,
819 struct drm_device *ddev,
820 struct pci_dev *pdev,
821 uint32_t flags);
822void radeon_device_fini(struct radeon_device *rdev);
823int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
824
3ce0a23d
JG		 825/* r600 blit */
826int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
827void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
828void r600_kms_blit_copy(struct radeon_device *rdev,
829 u64 src_gpu_addr, u64 dst_gpu_addr,
830 int size_bytes);
831
de1b2898
DA		 832static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
833{
834 if (reg < 0x10000)
835 return readl(((void __iomem *)rdev->rmmio) + reg);
836 else {
837 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
838 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
839 }
840}
841
842static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
843{
844 if (reg < 0x10000)
845 writel(v, ((void __iomem *)rdev->rmmio) + reg);
846 else {
847 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
848 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
849 }
850}
851
771fe6b9
JG		 852
853/*
854 * Registers read & write functions.
855 */
856#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
857#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
de1b2898 858#define RREG32(reg) r100_mm_rreg(rdev, (reg))
3ce0a23d 859#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
de1b2898 860#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
771fe6b9
JG		 861#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
862#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
863#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
864#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
865#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
866#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 867#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
868#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
771fe6b9
JG		 869#define WREG32_P(reg, val, mask) \
870 do { \
871 uint32_t tmp_ = RREG32(reg); \
872 tmp_ &= (mask); \
873 tmp_ |= ((val) & ~(mask)); \
874 WREG32(reg, tmp_); \
875 } while (0)
876#define WREG32_PLL_P(reg, val, mask) \
877 do { \
878 uint32_t tmp_ = RREG32_PLL(reg); \
879 tmp_ &= (mask); \
880 tmp_ |= ((val) & ~(mask)); \
881 WREG32_PLL(reg, tmp_); \
882 } while (0)
3ce0a23d 883#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
771fe6b9 884
de1b2898
DA		 885/*
886 * Indirect registers accessor
887 */
888static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
889{
890 uint32_t r;
891
892 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
893 r = RREG32(RADEON_PCIE_DATA);
894 return r;
895}
896
897static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
898{
899 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
900 WREG32(RADEON_PCIE_DATA, (v));
901}
902
771fe6b9
JG		 903void r100_pll_errata_after_index(struct radeon_device *rdev);
904
905
906/*
907 * ASICs helpers.
908 */
b995e433
DA		 909#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
910 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 911#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
912 (rdev->family == CHIP_RV200) || \
913 (rdev->family == CHIP_RS100) || \
914 (rdev->family == CHIP_RS200) || \
915 (rdev->family == CHIP_RV250) || \
916 (rdev->family == CHIP_RV280) || \
917 (rdev->family == CHIP_RS300))
918#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
919 (rdev->family == CHIP_RV350) || \
920 (rdev->family == CHIP_R350) || \
921 (rdev->family == CHIP_RV380) || \
922 (rdev->family == CHIP_R420) || \
923 (rdev->family == CHIP_R423) || \
924 (rdev->family == CHIP_RV410) || \
925 (rdev->family == CHIP_RS400) || \
926 (rdev->family == CHIP_RS480))
927#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
928#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
929#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
930
931
932/*
933 * BIOS helpers.
934 */
935#define RBIOS8(i) (rdev->bios[i])
936#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
937#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
938
939int radeon_combios_init(struct radeon_device *rdev);
940void radeon_combios_fini(struct radeon_device *rdev);
941int radeon_atombios_init(struct radeon_device *rdev);
942void radeon_atombios_fini(struct radeon_device *rdev);
943
944
945/*
946 * RING helpers.
947 */
771fe6b9
JG		 948static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
949{
950#if DRM_DEBUG_CODE
951 if (rdev->cp.count_dw <= 0) {
952 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
953 }
954#endif
955 rdev->cp.ring[rdev->cp.wptr++] = v;
956 rdev->cp.wptr &= rdev->cp.ptr_mask;
957 rdev->cp.count_dw--;
958 rdev->cp.ring_free_dw--;
959}
960
961
962/*
963 * ASICs macro.
964 */
068a117c 965#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 966#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
967#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
968#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
771fe6b9 969#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
28d52043 970#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
771fe6b9 971#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
771fe6b9
JG		 972#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
973#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
3ce0a23d 974#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
771fe6b9 975#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
3ce0a23d
JG		 976#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
977#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
771fe6b9
JG		 978#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
979#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
7ed220d7 980#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
771fe6b9
JG		 981#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
982#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
983#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
984#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
7433874e 985#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
771fe6b9 986#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
7433874e 987#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
771fe6b9
JG		 988#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
989#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
990#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
e024e110
DA		 991#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
992#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
c93bb85b 993#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
23956dfa 994#define radeon_hdp_flush(rdev) (rdev)->asic->hdp_flush((rdev))
771fe6b9 995
6cf8a3f5 996/* Common functions */
4aac0473 997extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
21f9a437
JG		 998extern int radeon_modeset_init(struct radeon_device *rdev);
999extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 1000extern bool radeon_card_posted(struct radeon_device *rdev);
72542d77 1001extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437
JG		 1002extern int radeon_clocks_init(struct radeon_device *rdev);
1003extern void radeon_clocks_fini(struct radeon_device *rdev);
1004extern void radeon_scratch_init(struct radeon_device *rdev);
1005extern void radeon_surface_init(struct radeon_device *rdev);
1006extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 1007extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 1008extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
6cf8a3f5 1009
a18d7ea1 1010/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
9f022ddf
JG		 1011struct r100_mc_save {
1012 u32 GENMO_WT;
1013 u32 CRTC_EXT_CNTL;
1014 u32 CRTC_GEN_CNTL;
1015 u32 CRTC2_GEN_CNTL;
1016 u32 CUR_OFFSET;
1017 u32 CUR2_OFFSET;
1018};
1019extern void r100_cp_disable(struct radeon_device *rdev);
1020extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
1021extern void r100_cp_fini(struct radeon_device *rdev);
21f9a437 1022extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
4aac0473
JG		 1023extern int r100_pci_gart_init(struct radeon_device *rdev);
1024extern void r100_pci_gart_fini(struct radeon_device *rdev);
21f9a437
JG		 1025extern int r100_pci_gart_enable(struct radeon_device *rdev);
1026extern void r100_pci_gart_disable(struct radeon_device *rdev);
1027extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
9f022ddf
JG		 1028extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
1029extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
1030extern void r100_ib_fini(struct radeon_device *rdev);
1031extern int r100_ib_init(struct radeon_device *rdev);
1032extern void r100_irq_disable(struct radeon_device *rdev);
1033extern int r100_irq_set(struct radeon_device *rdev);
1034extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1035extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
21f9a437 1036extern void r100_vram_init_sizes(struct radeon_device *rdev);
9f022ddf
JG		 1037extern void r100_wb_disable(struct radeon_device *rdev);
1038extern void r100_wb_fini(struct radeon_device *rdev);
1039extern int r100_wb_init(struct radeon_device *rdev);
d39c3b89
JG		 1040extern void r100_hdp_reset(struct radeon_device *rdev);
1041extern int r100_rb2d_reset(struct radeon_device *rdev);
1042extern int r100_cp_reset(struct radeon_device *rdev);
ca6ffc64 1043extern void r100_vga_render_disable(struct radeon_device *rdev);
207bf9e9
JG		 1044extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1045 struct radeon_cs_packet *pkt,
1046 struct radeon_object *robj);
1047extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1048 struct radeon_cs_packet *pkt,
1049 const unsigned *auth, unsigned n,
1050 radeon_packet0_check_t check);
1051extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
1052 struct radeon_cs_packet *pkt,
1053 unsigned idx);
17e15b0c 1054extern void r100_enable_bm(struct radeon_device *rdev);
9f022ddf 1055
d4550907
JG		 1056/* rv200,rv250,rv280 */
1057extern void r200_set_safe_registers(struct radeon_device *rdev);
9f022ddf
JG		 1058
1059/* r300,r350,rv350,rv370,rv380 */
1060extern void r300_set_reg_safe(struct radeon_device *rdev);
1061extern void r300_mc_program(struct radeon_device *rdev);
1062extern void r300_vram_info(struct radeon_device *rdev);
ca6ffc64
JG		 1063extern void r300_clock_startup(struct radeon_device *rdev);
1064extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
4aac0473
JG		 1065extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1066extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1067extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
9f022ddf 1068extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
a18d7ea1 1069
905b6822 1070/* r420,r423,rv410 */
d39c3b89 1071extern int r420_mc_init(struct radeon_device *rdev);
21f9a437
JG		 1072extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1073extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
9f022ddf 1074extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
d39c3b89 1075extern void r420_pipes_init(struct radeon_device *rdev);
905b6822 1076
21f9a437 1077/* rv515 */
d39c3b89
JG		 1078struct rv515_mc_save {
1079 u32 d1vga_control;
1080 u32 d2vga_control;
1081 u32 vga_render_control;
1082 u32 vga_hdp_control;
1083 u32 d1crtc_control;
1084 u32 d2crtc_control;
1085};
21f9a437 1086extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
d39c3b89
JG		 1087extern void rv515_vga_render_disable(struct radeon_device *rdev);
1088extern void rv515_set_safe_registers(struct radeon_device *rdev);
f0ed1f65
JG		 1089extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1090extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1091extern void rv515_clock_startup(struct radeon_device *rdev);
1092extern void rv515_debugfs(struct radeon_device *rdev);
1093extern int rv515_suspend(struct radeon_device *rdev);
21f9a437 1094
3bc68535
JG		 1095/* rs400 */
1096extern int rs400_gart_init(struct radeon_device *rdev);
1097extern int rs400_gart_enable(struct radeon_device *rdev);
1098extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1099extern void rs400_gart_disable(struct radeon_device *rdev);
1100extern void rs400_gart_fini(struct radeon_device *rdev);
1101
1102/* rs600 */
1103extern void rs600_set_safe_registers(struct radeon_device *rdev);
ac447df4
JG		 1104extern int rs600_irq_set(struct radeon_device *rdev);
1105extern void rs600_irq_disable(struct radeon_device *rdev);
3bc68535 1106
21f9a437
JG		 1107/* rs690, rs740 */
1108extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1109 struct drm_display_mode *mode1,
1110 struct drm_display_mode *mode2);
1111
1112/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1113extern bool r600_card_posted(struct radeon_device *rdev);
1114extern void r600_cp_stop(struct radeon_device *rdev);
1115extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1116extern int r600_cp_resume(struct radeon_device *rdev);
1117extern int r600_count_pipe_bits(uint32_t val);
1118extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1119extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
4aac0473 1120extern int r600_pcie_gart_init(struct radeon_device *rdev);
21f9a437
JG		 1121extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1122extern int r600_ib_test(struct radeon_device *rdev);
1123extern int r600_ring_test(struct radeon_device *rdev);
21f9a437 1124extern void r600_wb_fini(struct radeon_device *rdev);
81cc35bf
JG		 1125extern int r600_wb_enable(struct radeon_device *rdev);
1126extern void r600_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 1127extern void r600_scratch_init(struct radeon_device *rdev);
1128extern int r600_blit_init(struct radeon_device *rdev);
1129extern void r600_blit_fini(struct radeon_device *rdev);
d8f60cfc 1130extern int r600_init_microcode(struct radeon_device *rdev);
fe62e1a4 1131extern int r600_gpu_reset(struct radeon_device *rdev);
d8f60cfc
AD		 1132/* r600 irq */
1133extern int r600_irq_init(struct radeon_device *rdev);
1134extern void r600_irq_fini(struct radeon_device *rdev);
1135extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1136extern int r600_irq_set(struct radeon_device *rdev);
21f9a437 1137
771fe6b9 1138#endif
Linux kernel - Deliverables
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