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drm/radeon/kms: limit default tv modes to <= 1024x768
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31#include "radeon_object.h"
32
33/* TODO: Here are things that needs to be done :
34 * - surface allocator & initializer : (bit like scratch reg) should
35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
36 * related to surface
37 * - WB : write back stuff (do it bit like scratch reg things)
38 * - Vblank : look at Jesse's rework and what we should do
39 * - r600/r700: gart & cp
40 * - cs : clean cs ioctl use bitmap & things like that.
41 * - power management stuff
42 * - Barrier in gart code
43 * - Unmappabled vram ?
44 * - TESTING, TESTING, TESTING
45 */
46
d39c3b89
JG		 47/* Initialization path:
48 * We expect that acceleration initialization might fail for various
49 * reasons even thought we work hard to make it works on most
50 * configurations. In order to still have a working userspace in such
51 * situation the init path must succeed up to the memory controller
52 * initialization point. Failure before this point are considered as
53 * fatal error. Here is the init callchain :
54 * radeon_device_init perform common structure, mutex initialization
55 * asic_init setup the GPU memory layout and perform all
56 * one time initialization (failure in this
57 * function are considered fatal)
58 * asic_startup setup the GPU acceleration, in order to
59 * follow guideline the first thing this
60 * function should do is setting the GPU
61 * memory controller (only MC setup failure
62 * are considered as fatal)
63 */
64
771fe6b9
JG		 65#include <asm/atomic.h>
66#include <linux/wait.h>
67#include <linux/list.h>
68#include <linux/kref.h>
69
c2142715 70#include "radeon_family.h"
771fe6b9
JG		 71#include "radeon_mode.h"
72#include "radeon_reg.h"
771fe6b9
JG		 73
74/*
75 * Modules parameters.
76 */
77extern int radeon_no_wb;
78extern int radeon_modeset;
79extern int radeon_dynclks;
80extern int radeon_r4xx_atom;
81extern int radeon_agpmode;
82extern int radeon_vram_limit;
83extern int radeon_gart_size;
84extern int radeon_benchmarking;
ecc0b326 85extern int radeon_testing;
771fe6b9 86extern int radeon_connector_table;
4ce001ab 87extern int radeon_tv;
771fe6b9
JG		 88
89/*
90 * Copy from radeon_drv.h so we don't have to include both and have conflicting
91 * symbol;
92 */
93#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
94#define RADEON_IB_POOL_SIZE 16
95#define RADEON_DEBUGFS_MAX_NUM_FILES 32
96#define RADEONFB_CONN_LIMIT 4
f657c2a7 97#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 98
771fe6b9
JG		 99/*
100 * Errata workarounds.
101 */
102enum radeon_pll_errata {
103 CHIP_ERRATA_R300_CG = 0x00000001,
104 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
105 CHIP_ERRATA_PLL_DELAY = 0x00000004
106};
107
108
109struct radeon_device;
110
111
112/*
113 * BIOS.
114 */
115bool radeon_get_bios(struct radeon_device *rdev);
116
3ce0a23d 117
771fe6b9 118/*
3ce0a23d 119 * Dummy page
771fe6b9 120 */
3ce0a23d
JG		 121struct radeon_dummy_page {
122 struct page *page;
123 dma_addr_t addr;
124};
125int radeon_dummy_page_init(struct radeon_device *rdev);
126void radeon_dummy_page_fini(struct radeon_device *rdev);
127
771fe6b9 128
3ce0a23d
JG		 129/*
130 * Clocks
131 */
771fe6b9
JG		 132struct radeon_clock {
133 struct radeon_pll p1pll;
134 struct radeon_pll p2pll;
135 struct radeon_pll spll;
136 struct radeon_pll mpll;
137 /* 10 Khz units */
138 uint32_t default_mclk;
139 uint32_t default_sclk;
140};
141
3ce0a23d 142
771fe6b9
JG		 143/*
144 * Fences.
145 */
146struct radeon_fence_driver {
147 uint32_t scratch_reg;
148 atomic_t seq;
149 uint32_t last_seq;
150 unsigned long count_timeout;
151 wait_queue_head_t queue;
152 rwlock_t lock;
153 struct list_head created;
154 struct list_head emited;
155 struct list_head signaled;
156};
157
158struct radeon_fence {
159 struct radeon_device *rdev;
160 struct kref kref;
161 struct list_head list;
162 /* protected by radeon_fence.lock */
163 uint32_t seq;
164 unsigned long timeout;
165 bool emited;
166 bool signaled;
167};
168
169int radeon_fence_driver_init(struct radeon_device *rdev);
170void radeon_fence_driver_fini(struct radeon_device *rdev);
171int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
172int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
173void radeon_fence_process(struct radeon_device *rdev);
174bool radeon_fence_signaled(struct radeon_fence *fence);
175int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
176int radeon_fence_wait_next(struct radeon_device *rdev);
177int radeon_fence_wait_last(struct radeon_device *rdev);
178struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
179void radeon_fence_unref(struct radeon_fence **fence);
180
e024e110
DA		 181/*
182 * Tiling registers
183 */
184struct radeon_surface_reg {
185 struct radeon_object *robj;
186};
187
188#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 189
190/*
191 * Radeon buffer.
192 */
193struct radeon_object;
194
195struct radeon_object_list {
196 struct list_head list;
197 struct radeon_object *robj;
198 uint64_t gpu_offset;
199 unsigned rdomain;
200 unsigned wdomain;
e024e110 201 uint32_t tiling_flags;
771fe6b9
JG		 202};
203
204int radeon_object_init(struct radeon_device *rdev);
205void radeon_object_fini(struct radeon_device *rdev);
206int radeon_object_create(struct radeon_device *rdev,
207 struct drm_gem_object *gobj,
208 unsigned long size,
209 bool kernel,
210 uint32_t domain,
211 bool interruptible,
212 struct radeon_object **robj_ptr);
213int radeon_object_kmap(struct radeon_object *robj, void **ptr);
214void radeon_object_kunmap(struct radeon_object *robj);
215void radeon_object_unref(struct radeon_object **robj);
216int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
217 uint64_t *gpu_addr);
218void radeon_object_unpin(struct radeon_object *robj);
219int radeon_object_wait(struct radeon_object *robj);
cefb87ef 220int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement);
771fe6b9
JG		 221int radeon_object_evict_vram(struct radeon_device *rdev);
222int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
223void radeon_object_force_delete(struct radeon_device *rdev);
224void radeon_object_list_add_object(struct radeon_object_list *lobj,
225 struct list_head *head);
226int radeon_object_list_validate(struct list_head *head, void *fence);
227void radeon_object_list_unvalidate(struct list_head *head);
228void radeon_object_list_clean(struct list_head *head);
229int radeon_object_fbdev_mmap(struct radeon_object *robj,
230 struct vm_area_struct *vma);
231unsigned long radeon_object_size(struct radeon_object *robj);
e024e110
DA		 232void radeon_object_clear_surface_reg(struct radeon_object *robj);
233int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
234 bool force_drop);
235void radeon_object_set_tiling_flags(struct radeon_object *robj,
236 uint32_t tiling_flags, uint32_t pitch);
237void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
238void radeon_bo_move_notify(struct ttm_buffer_object *bo,
239 struct ttm_mem_reg *mem);
240void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
771fe6b9
JG		 241/*
242 * GEM objects.
243 */
244struct radeon_gem {
245 struct list_head objects;
246};
247
248int radeon_gem_init(struct radeon_device *rdev);
249void radeon_gem_fini(struct radeon_device *rdev);
250int radeon_gem_object_create(struct radeon_device *rdev, int size,
251 int alignment, int initial_domain,
252 bool discardable, bool kernel,
253 bool interruptible,
254 struct drm_gem_object **obj);
255int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
256 uint64_t *gpu_addr);
257void radeon_gem_object_unpin(struct drm_gem_object *obj);
258
259
260/*
261 * GART structures, functions & helpers
262 */
263struct radeon_mc;
264
265struct radeon_gart_table_ram {
266 volatile uint32_t *ptr;
267};
268
269struct radeon_gart_table_vram {
270 struct radeon_object *robj;
271 volatile uint32_t *ptr;
272};
273
274union radeon_gart_table {
275 struct radeon_gart_table_ram ram;
276 struct radeon_gart_table_vram vram;
277};
278
279struct radeon_gart {
280 dma_addr_t table_addr;
281 unsigned num_gpu_pages;
282 unsigned num_cpu_pages;
283 unsigned table_size;
284 union radeon_gart_table table;
285 struct page **pages;
286 dma_addr_t *pages_addr;
287 bool ready;
288};
289
290int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
291void radeon_gart_table_ram_free(struct radeon_device *rdev);
292int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
293void radeon_gart_table_vram_free(struct radeon_device *rdev);
294int radeon_gart_init(struct radeon_device *rdev);
295void radeon_gart_fini(struct radeon_device *rdev);
296void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
297 int pages);
298int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
299 int pages, struct page **pagelist);
300
301
302/*
303 * GPU MC structures, functions & helpers
304 */
305struct radeon_mc {
306 resource_size_t aper_size;
307 resource_size_t aper_base;
308 resource_size_t agp_base;
7a50f01a
DA		 309 /* for some chips with <= 32MB we need to lie
310 * about vram size near mc fb location */
3ce0a23d
JG		 311 u64 mc_vram_size;
312 u64 gtt_location;
313 u64 gtt_size;
314 u64 gtt_start;
315 u64 gtt_end;
316 u64 vram_location;
317 u64 vram_start;
318 u64 vram_end;
771fe6b9 319 unsigned vram_width;
3ce0a23d 320 u64 real_vram_size;
771fe6b9
JG		 321 int vram_mtrr;
322 bool vram_is_ddr;
323};
324
325int radeon_mc_setup(struct radeon_device *rdev);
326
327
328/*
329 * GPU scratch registers structures, functions & helpers
330 */
331struct radeon_scratch {
332 unsigned num_reg;
333 bool free[32];
334 uint32_t reg[32];
335};
336
337int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
338void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
339
340
341/*
342 * IRQS.
343 */
344struct radeon_irq {
345 bool installed;
346 bool sw_int;
347 /* FIXME: use a define max crtc rather than hardcode it */
348 bool crtc_vblank_int[2];
349};
350
351int radeon_irq_kms_init(struct radeon_device *rdev);
352void radeon_irq_kms_fini(struct radeon_device *rdev);
353
354
355/*
356 * CP & ring.
357 */
358struct radeon_ib {
359 struct list_head list;
360 unsigned long idx;
361 uint64_t gpu_addr;
362 struct radeon_fence *fence;
513bcb46 363 uint32_t *ptr;
771fe6b9
JG		 364 uint32_t length_dw;
365};
366
ecb114a1
DA		 367/*
368 * locking -
369 * mutex protects scheduled_ibs, ready, alloc_bm
370 */
771fe6b9
JG		 371struct radeon_ib_pool {
372 struct mutex mutex;
373 struct radeon_object *robj;
374 struct list_head scheduled_ibs;
375 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
376 bool ready;
377 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
378};
379
380struct radeon_cp {
381 struct radeon_object *ring_obj;
382 volatile uint32_t *ring;
383 unsigned rptr;
384 unsigned wptr;
385 unsigned wptr_old;
386 unsigned ring_size;
387 unsigned ring_free_dw;
388 int count_dw;
389 uint64_t gpu_addr;
390 uint32_t align_mask;
391 uint32_t ptr_mask;
392 struct mutex mutex;
393 bool ready;
394};
395
3ce0a23d
JG		 396struct r600_blit {
397 struct radeon_object *shader_obj;
398 u64 shader_gpu_addr;
399 u32 vs_offset, ps_offset;
400 u32 state_offset;
401 u32 state_len;
402 u32 vb_used, vb_total;
403 struct radeon_ib *vb_ib;
404};
405
771fe6b9
JG		 406int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
407void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
408int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
409int radeon_ib_pool_init(struct radeon_device *rdev);
410void radeon_ib_pool_fini(struct radeon_device *rdev);
411int radeon_ib_test(struct radeon_device *rdev);
412/* Ring access between begin & end cannot sleep */
413void radeon_ring_free_size(struct radeon_device *rdev);
414int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
415void radeon_ring_unlock_commit(struct radeon_device *rdev);
416void radeon_ring_unlock_undo(struct radeon_device *rdev);
417int radeon_ring_test(struct radeon_device *rdev);
418int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
419void radeon_ring_fini(struct radeon_device *rdev);
420
421
422/*
423 * CS.
424 */
425struct radeon_cs_reloc {
426 struct drm_gem_object *gobj;
427 struct radeon_object *robj;
428 struct radeon_object_list lobj;
429 uint32_t handle;
430 uint32_t flags;
431};
432
433struct radeon_cs_chunk {
434 uint32_t chunk_id;
435 uint32_t length_dw;
513bcb46
DA		 436 int kpage_idx[2];
437 uint32_t *kpage[2];
771fe6b9 438 uint32_t *kdata;
513bcb46
DA		 439 void __user *user_ptr;
440 int last_copied_page;
441 int last_page_index;
771fe6b9
JG		 442};
443
444struct radeon_cs_parser {
445 struct radeon_device *rdev;
446 struct drm_file *filp;
447 /* chunks */
448 unsigned nchunks;
449 struct radeon_cs_chunk *chunks;
450 uint64_t *chunks_array;
451 /* IB */
452 unsigned idx;
453 /* relocations */
454 unsigned nrelocs;
455 struct radeon_cs_reloc *relocs;
456 struct radeon_cs_reloc **relocs_ptr;
457 struct list_head validated;
458 /* indices of various chunks */
459 int chunk_ib_idx;
460 int chunk_relocs_idx;
461 struct radeon_ib *ib;
462 void *track;
3ce0a23d 463 unsigned family;
513bcb46 464 int parser_error;
771fe6b9
JG		 465};
466
513bcb46
DA		 467extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
468extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
469
470
471static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
472{
473 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
474 u32 pg_idx, pg_offset;
475 u32 idx_value = 0;
476 int new_page;
477
478 pg_idx = (idx * 4) / PAGE_SIZE;
479 pg_offset = (idx * 4) % PAGE_SIZE;
480
481 if (ibc->kpage_idx[0] == pg_idx)
482 return ibc->kpage[0][pg_offset/4];
483 if (ibc->kpage_idx[1] == pg_idx)
484 return ibc->kpage[1][pg_offset/4];
485
486 new_page = radeon_cs_update_pages(p, pg_idx);
487 if (new_page < 0) {
488 p->parser_error = new_page;
489 return 0;
490 }
491
492 idx_value = ibc->kpage[new_page][pg_offset/4];
493 return idx_value;
494}
495
771fe6b9
JG		 496struct radeon_cs_packet {
497 unsigned idx;
498 unsigned type;
499 unsigned reg;
500 unsigned opcode;
501 int count;
502 unsigned one_reg_wr;
503};
504
505typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
506 struct radeon_cs_packet *pkt,
507 unsigned idx, unsigned reg);
508typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
509 struct radeon_cs_packet *pkt);
510
511
512/*
513 * AGP
514 */
515int radeon_agp_init(struct radeon_device *rdev);
516void radeon_agp_fini(struct radeon_device *rdev);
517
518
519/*
520 * Writeback
521 */
522struct radeon_wb {
523 struct radeon_object *wb_obj;
524 volatile uint32_t *wb;
525 uint64_t gpu_addr;
526};
527
c93bb85b
JG		 528/**
529 * struct radeon_pm - power management datas
530 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
531 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
532 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
533 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
534 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
535 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
536 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
537 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
538 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
539 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
540 * @needed_bandwidth: current bandwidth needs
541 *
542 * It keeps track of various data needed to take powermanagement decision.
543 * Bandwith need is used to determine minimun clock of the GPU and memory.
544 * Equation between gpu/memory clock and available bandwidth is hw dependent
545 * (type of memory, bus size, efficiency, ...)
546 */
547struct radeon_pm {
548 fixed20_12 max_bandwidth;
549 fixed20_12 igp_sideport_mclk;
550 fixed20_12 igp_system_mclk;
551 fixed20_12 igp_ht_link_clk;
552 fixed20_12 igp_ht_link_width;
553 fixed20_12 k8_bandwidth;
554 fixed20_12 sideport_bandwidth;
555 fixed20_12 ht_bandwidth;
556 fixed20_12 core_bandwidth;
557 fixed20_12 sclk;
558 fixed20_12 needed_bandwidth;
559};
560
771fe6b9
JG		 561
562/*
563 * Benchmarking
564 */
565void radeon_benchmark(struct radeon_device *rdev);
566
567
ecc0b326
MD		 568/*
569 * Testing
570 */
571void radeon_test_moves(struct radeon_device *rdev);
572
573
771fe6b9
JG		 574/*
575 * Debugfs
576 */
577int radeon_debugfs_add_files(struct radeon_device *rdev,
578 struct drm_info_list *files,
579 unsigned nfiles);
580int radeon_debugfs_fence_init(struct radeon_device *rdev);
581int r100_debugfs_rbbm_init(struct radeon_device *rdev);
582int r100_debugfs_cp_init(struct radeon_device *rdev);
583
584
585/*
586 * ASIC specific functions.
587 */
588struct radeon_asic {
068a117c 589 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 590 void (*fini)(struct radeon_device *rdev);
591 int (*resume)(struct radeon_device *rdev);
592 int (*suspend)(struct radeon_device *rdev);
771fe6b9 593 int (*gpu_reset)(struct radeon_device *rdev);
771fe6b9
JG		 594 void (*gart_tlb_flush)(struct radeon_device *rdev);
595 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
596 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
597 void (*cp_fini)(struct radeon_device *rdev);
598 void (*cp_disable)(struct radeon_device *rdev);
3ce0a23d 599 void (*cp_commit)(struct radeon_device *rdev);
771fe6b9 600 void (*ring_start)(struct radeon_device *rdev);
3ce0a23d
JG		 601 int (*ring_test)(struct radeon_device *rdev);
602 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
771fe6b9
JG		 603 int (*irq_set)(struct radeon_device *rdev);
604 int (*irq_process)(struct radeon_device *rdev);
7ed220d7 605 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 606 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
607 int (*cs_parse)(struct radeon_cs_parser *p);
608 int (*copy_blit)(struct radeon_device *rdev,
609 uint64_t src_offset,
610 uint64_t dst_offset,
611 unsigned num_pages,
612 struct radeon_fence *fence);
613 int (*copy_dma)(struct radeon_device *rdev,
614 uint64_t src_offset,
615 uint64_t dst_offset,
616 unsigned num_pages,
617 struct radeon_fence *fence);
618 int (*copy)(struct radeon_device *rdev,
619 uint64_t src_offset,
620 uint64_t dst_offset,
621 unsigned num_pages,
622 struct radeon_fence *fence);
623 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
624 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
625 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
626 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
e024e110
DA		 627 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
628 uint32_t tiling_flags, uint32_t pitch,
629 uint32_t offset, uint32_t obj_size);
630 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
c93bb85b 631 void (*bandwidth_update)(struct radeon_device *rdev);
771fe6b9
JG		 632};
633
21f9a437
JG		 634/*
635 * Asic structures
636 */
551ebd83
DA		 637struct r100_asic {
638 const unsigned *reg_safe_bm;
639 unsigned reg_safe_bm_size;
640};
641
21f9a437
JG		 642struct r300_asic {
643 const unsigned *reg_safe_bm;
644 unsigned reg_safe_bm_size;
645};
646
647struct r600_asic {
648 unsigned max_pipes;
649 unsigned max_tile_pipes;
650 unsigned max_simds;
651 unsigned max_backends;
652 unsigned max_gprs;
653 unsigned max_threads;
654 unsigned max_stack_entries;
655 unsigned max_hw_contexts;
656 unsigned max_gs_threads;
657 unsigned sx_max_export_size;
658 unsigned sx_max_export_pos_size;
659 unsigned sx_max_export_smx_size;
660 unsigned sq_num_cf_insts;
661};
662
663struct rv770_asic {
664 unsigned max_pipes;
665 unsigned max_tile_pipes;
666 unsigned max_simds;
667 unsigned max_backends;
668 unsigned max_gprs;
669 unsigned max_threads;
670 unsigned max_stack_entries;
671 unsigned max_hw_contexts;
672 unsigned max_gs_threads;
673 unsigned sx_max_export_size;
674 unsigned sx_max_export_pos_size;
675 unsigned sx_max_export_smx_size;
676 unsigned sq_num_cf_insts;
677 unsigned sx_num_of_sets;
678 unsigned sc_prim_fifo_size;
679 unsigned sc_hiz_tile_fifo_size;
680 unsigned sc_earlyz_tile_fifo_fize;
681};
682
068a117c
JG		 683union radeon_asic_config {
684 struct r300_asic r300;
551ebd83 685 struct r100_asic r100;
3ce0a23d
JG		 686 struct r600_asic r600;
687 struct rv770_asic rv770;
068a117c
JG		 688};
689
771fe6b9
JG		 690
691/*
692 * IOCTL.
693 */
694int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
695 struct drm_file *filp);
696int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
697 struct drm_file *filp);
698int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
699 struct drm_file *file_priv);
700int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
701 struct drm_file *file_priv);
702int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
703 struct drm_file *file_priv);
704int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
705 struct drm_file *file_priv);
706int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
707 struct drm_file *filp);
708int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
709 struct drm_file *filp);
710int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
711 struct drm_file *filp);
712int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
713 struct drm_file *filp);
714int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 715int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
716 struct drm_file *filp);
717int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
718 struct drm_file *filp);
771fe6b9
JG		 719
720
721/*
722 * Core structure, functions and helpers.
723 */
724typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
725typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
726
727struct radeon_device {
9f022ddf 728 struct device *dev;
771fe6b9
JG		 729 struct drm_device *ddev;
730 struct pci_dev *pdev;
731 /* ASIC */
068a117c 732 union radeon_asic_config config;
771fe6b9
JG		 733 enum radeon_family family;
734 unsigned long flags;
735 int usec_timeout;
736 enum radeon_pll_errata pll_errata;
737 int num_gb_pipes;
f779b3e5 738 int num_z_pipes;
771fe6b9
JG		 739 int disp_priority;
740 /* BIOS */
741 uint8_t *bios;
742 bool is_atom_bios;
743 uint16_t bios_header_start;
744 struct radeon_object *stollen_vga_memory;
745 struct fb_info *fbdev_info;
746 struct radeon_object *fbdev_robj;
747 struct radeon_framebuffer *fbdev_rfb;
748 /* Register mmio */
4c9bc75c
DA		 749 resource_size_t rmmio_base;
750 resource_size_t rmmio_size;
771fe6b9 751 void *rmmio;
771fe6b9
JG		 752 radeon_rreg_t mc_rreg;
753 radeon_wreg_t mc_wreg;
754 radeon_rreg_t pll_rreg;
755 radeon_wreg_t pll_wreg;
de1b2898 756 uint32_t pcie_reg_mask;
771fe6b9
JG		 757 radeon_rreg_t pciep_rreg;
758 radeon_wreg_t pciep_wreg;
759 struct radeon_clock clock;
760 struct radeon_mc mc;
761 struct radeon_gart gart;
762 struct radeon_mode_info mode_info;
763 struct radeon_scratch scratch;
764 struct radeon_mman mman;
765 struct radeon_fence_driver fence_drv;
766 struct radeon_cp cp;
767 struct radeon_ib_pool ib_pool;
768 struct radeon_irq irq;
769 struct radeon_asic *asic;
770 struct radeon_gem gem;
c93bb85b 771 struct radeon_pm pm;
f657c2a7 772 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9
JG		 773 struct mutex cs_mutex;
774 struct radeon_wb wb;
3ce0a23d 775 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 776 bool gpu_lockup;
777 bool shutdown;
778 bool suspend;
ad49f501 779 bool need_dma32;
733289c2 780 bool accel_working;
e024e110 781 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 782 const struct firmware *me_fw; /* all family ME firmware */
783 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
784 struct r600_blit r600_blit;
771fe6b9
JG		 785};
786
787int radeon_device_init(struct radeon_device *rdev,
788 struct drm_device *ddev,
789 struct pci_dev *pdev,
790 uint32_t flags);
791void radeon_device_fini(struct radeon_device *rdev);
792int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
793
3ce0a23d
JG		 794/* r600 blit */
795int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
796void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
797void r600_kms_blit_copy(struct radeon_device *rdev,
798 u64 src_gpu_addr, u64 dst_gpu_addr,
799 int size_bytes);
800
de1b2898
DA		 801static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
802{
803 if (reg < 0x10000)
804 return readl(((void __iomem *)rdev->rmmio) + reg);
805 else {
806 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
807 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
808 }
809}
810
811static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
812{
813 if (reg < 0x10000)
814 writel(v, ((void __iomem *)rdev->rmmio) + reg);
815 else {
816 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
817 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
818 }
819}
820
771fe6b9
JG		 821
822/*
823 * Registers read & write functions.
824 */
825#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
826#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
de1b2898 827#define RREG32(reg) r100_mm_rreg(rdev, (reg))
3ce0a23d 828#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
de1b2898 829#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
771fe6b9
JG		 830#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
831#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
832#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
833#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
834#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
835#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 836#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
837#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
771fe6b9
JG		 838#define WREG32_P(reg, val, mask) \
839 do { \
840 uint32_t tmp_ = RREG32(reg); \
841 tmp_ &= (mask); \
842 tmp_ |= ((val) & ~(mask)); \
843 WREG32(reg, tmp_); \
844 } while (0)
845#define WREG32_PLL_P(reg, val, mask) \
846 do { \
847 uint32_t tmp_ = RREG32_PLL(reg); \
848 tmp_ &= (mask); \
849 tmp_ |= ((val) & ~(mask)); \
850 WREG32_PLL(reg, tmp_); \
851 } while (0)
3ce0a23d 852#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
771fe6b9 853
de1b2898
DA		 854/*
855 * Indirect registers accessor
856 */
857static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
858{
859 uint32_t r;
860
861 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
862 r = RREG32(RADEON_PCIE_DATA);
863 return r;
864}
865
866static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
867{
868 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
869 WREG32(RADEON_PCIE_DATA, (v));
870}
871
771fe6b9
JG		 872void r100_pll_errata_after_index(struct radeon_device *rdev);
873
874
875/*
876 * ASICs helpers.
877 */
b995e433
DA		 878#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
879 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 880#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
881 (rdev->family == CHIP_RV200) || \
882 (rdev->family == CHIP_RS100) || \
883 (rdev->family == CHIP_RS200) || \
884 (rdev->family == CHIP_RV250) || \
885 (rdev->family == CHIP_RV280) || \
886 (rdev->family == CHIP_RS300))
887#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
888 (rdev->family == CHIP_RV350) || \
889 (rdev->family == CHIP_R350) || \
890 (rdev->family == CHIP_RV380) || \
891 (rdev->family == CHIP_R420) || \
892 (rdev->family == CHIP_R423) || \
893 (rdev->family == CHIP_RV410) || \
894 (rdev->family == CHIP_RS400) || \
895 (rdev->family == CHIP_RS480))
896#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
897#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
898#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
899
900
901/*
902 * BIOS helpers.
903 */
904#define RBIOS8(i) (rdev->bios[i])
905#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
906#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
907
908int radeon_combios_init(struct radeon_device *rdev);
909void radeon_combios_fini(struct radeon_device *rdev);
910int radeon_atombios_init(struct radeon_device *rdev);
911void radeon_atombios_fini(struct radeon_device *rdev);
912
913
914/*
915 * RING helpers.
916 */
771fe6b9
JG		 917static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
918{
919#if DRM_DEBUG_CODE
920 if (rdev->cp.count_dw <= 0) {
921 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
922 }
923#endif
924 rdev->cp.ring[rdev->cp.wptr++] = v;
925 rdev->cp.wptr &= rdev->cp.ptr_mask;
926 rdev->cp.count_dw--;
927 rdev->cp.ring_free_dw--;
928}
929
930
931/*
932 * ASICs macro.
933 */
068a117c 934#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 935#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
936#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
937#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
771fe6b9 938#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
771fe6b9 939#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
771fe6b9
JG		 940#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
941#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
3ce0a23d 942#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
771fe6b9 943#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
3ce0a23d
JG		 944#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
945#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
771fe6b9
JG		 946#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
947#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
7ed220d7 948#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
771fe6b9
JG		 949#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
950#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
951#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
952#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
953#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
954#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
955#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
956#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
e024e110
DA		 957#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
958#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
c93bb85b 959#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
771fe6b9 960
6cf8a3f5 961/* Common functions */
4aac0473 962extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
21f9a437
JG		 963extern int radeon_modeset_init(struct radeon_device *rdev);
964extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 965extern bool radeon_card_posted(struct radeon_device *rdev);
21f9a437
JG		 966extern int radeon_clocks_init(struct radeon_device *rdev);
967extern void radeon_clocks_fini(struct radeon_device *rdev);
968extern void radeon_scratch_init(struct radeon_device *rdev);
969extern void radeon_surface_init(struct radeon_device *rdev);
970extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 971extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 972extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
6cf8a3f5 973
a18d7ea1 974/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
9f022ddf
JG		 975struct r100_mc_save {
976 u32 GENMO_WT;
977 u32 CRTC_EXT_CNTL;
978 u32 CRTC_GEN_CNTL;
979 u32 CRTC2_GEN_CNTL;
980 u32 CUR_OFFSET;
981 u32 CUR2_OFFSET;
982};
983extern void r100_cp_disable(struct radeon_device *rdev);
984extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
985extern void r100_cp_fini(struct radeon_device *rdev);
21f9a437 986extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
4aac0473
JG		 987extern int r100_pci_gart_init(struct radeon_device *rdev);
988extern void r100_pci_gart_fini(struct radeon_device *rdev);
21f9a437
JG		 989extern int r100_pci_gart_enable(struct radeon_device *rdev);
990extern void r100_pci_gart_disable(struct radeon_device *rdev);
991extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
9f022ddf
JG		 992extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
993extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
994extern void r100_ib_fini(struct radeon_device *rdev);
995extern int r100_ib_init(struct radeon_device *rdev);
996extern void r100_irq_disable(struct radeon_device *rdev);
997extern int r100_irq_set(struct radeon_device *rdev);
998extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
999extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
21f9a437 1000extern void r100_vram_init_sizes(struct radeon_device *rdev);
9f022ddf
JG		 1001extern void r100_wb_disable(struct radeon_device *rdev);
1002extern void r100_wb_fini(struct radeon_device *rdev);
1003extern int r100_wb_init(struct radeon_device *rdev);
d39c3b89
JG		 1004extern void r100_hdp_reset(struct radeon_device *rdev);
1005extern int r100_rb2d_reset(struct radeon_device *rdev);
1006extern int r100_cp_reset(struct radeon_device *rdev);
ca6ffc64 1007extern void r100_vga_render_disable(struct radeon_device *rdev);
207bf9e9
JG		 1008extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1009 struct radeon_cs_packet *pkt,
1010 struct radeon_object *robj);
1011extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1012 struct radeon_cs_packet *pkt,
1013 const unsigned *auth, unsigned n,
1014 radeon_packet0_check_t check);
1015extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
1016 struct radeon_cs_packet *pkt,
1017 unsigned idx);
9f022ddf 1018
d4550907
JG		 1019/* rv200,rv250,rv280 */
1020extern void r200_set_safe_registers(struct radeon_device *rdev);
1021
9f022ddf
JG		 1022/* r300,r350,rv350,rv370,rv380 */
1023extern void r300_set_reg_safe(struct radeon_device *rdev);
1024extern void r300_mc_program(struct radeon_device *rdev);
1025extern void r300_vram_info(struct radeon_device *rdev);
ca6ffc64
JG		 1026extern void r300_clock_startup(struct radeon_device *rdev);
1027extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
4aac0473
JG		 1028extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1029extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1030extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
9f022ddf 1031extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
a18d7ea1 1032
905b6822 1033/* r420,r423,rv410 */
d39c3b89 1034extern int r420_mc_init(struct radeon_device *rdev);
21f9a437
JG		 1035extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1036extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
9f022ddf 1037extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
d39c3b89 1038extern void r420_pipes_init(struct radeon_device *rdev);
905b6822 1039
21f9a437 1040/* rv515 */
d39c3b89
JG		 1041struct rv515_mc_save {
1042 u32 d1vga_control;
1043 u32 d2vga_control;
1044 u32 vga_render_control;
1045 u32 vga_hdp_control;
1046 u32 d1crtc_control;
1047 u32 d2crtc_control;
1048};
21f9a437 1049extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
d39c3b89
JG		 1050extern void rv515_vga_render_disable(struct radeon_device *rdev);
1051extern void rv515_set_safe_registers(struct radeon_device *rdev);
f0ed1f65
JG		 1052extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1053extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1054extern void rv515_clock_startup(struct radeon_device *rdev);
1055extern void rv515_debugfs(struct radeon_device *rdev);
1056extern int rv515_suspend(struct radeon_device *rdev);
21f9a437 1057
3bc68535
JG		 1058/* rs400 */
1059extern int rs400_gart_init(struct radeon_device *rdev);
1060extern int rs400_gart_enable(struct radeon_device *rdev);
1061extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1062extern void rs400_gart_disable(struct radeon_device *rdev);
1063extern void rs400_gart_fini(struct radeon_device *rdev);
1064
1065/* rs600 */
1066extern void rs600_set_safe_registers(struct radeon_device *rdev);
ac447df4
JG		 1067extern int rs600_irq_set(struct radeon_device *rdev);
1068extern void rs600_irq_disable(struct radeon_device *rdev);
3bc68535 1069
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JG		 1070/* rs690, rs740 */
1071extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1072 struct drm_display_mode *mode1,
1073 struct drm_display_mode *mode2);
1074
1075/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1076extern bool r600_card_posted(struct radeon_device *rdev);
1077extern void r600_cp_stop(struct radeon_device *rdev);
1078extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1079extern int r600_cp_resume(struct radeon_device *rdev);
1080extern int r600_count_pipe_bits(uint32_t val);
1081extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1082extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
4aac0473 1083extern int r600_pcie_gart_init(struct radeon_device *rdev);
21f9a437
JG		 1084extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1085extern int r600_ib_test(struct radeon_device *rdev);
1086extern int r600_ring_test(struct radeon_device *rdev);
21f9a437 1087extern void r600_wb_fini(struct radeon_device *rdev);
81cc35bf
JG		 1088extern int r600_wb_enable(struct radeon_device *rdev);
1089extern void r600_wb_disable(struct radeon_device *rdev);
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JG		 1090extern void r600_scratch_init(struct radeon_device *rdev);
1091extern int r600_blit_init(struct radeon_device *rdev);
1092extern void r600_blit_fini(struct radeon_device *rdev);
1093extern int r600_cp_init_microcode(struct radeon_device *rdev);
fe62e1a4 1094extern int r600_gpu_reset(struct radeon_device *rdev);
21f9a437 1095
771fe6b9 1096#endif
Linux kernel - Deliverables
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