projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/radeon: enable dpm by default on CI APUs
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
147666fb 72#include <ttm/ttm_execbuf_util.h>
4c788679 73
c2142715 74#include "radeon_family.h"
771fe6b9
JG		 75#include "radeon_mode.h"
76#include "radeon_reg.h"
771fe6b9
JG		 77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
ecc0b326 89extern int radeon_testing;
771fe6b9 90extern int radeon_connector_table;
4ce001ab 91extern int radeon_tv;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
d42dd579 95extern int radeon_pcie_gen2;
a18cee15 96extern int radeon_msi;
3368ff0c 97extern int radeon_lockup_timeout;
a0a53aa8 98extern int radeon_fastfb;
da321c8a 99extern int radeon_dpm;
1294d4a3 100extern int radeon_aspm;
10ebc0bc 101extern int radeon_runtime_pm;
771fe6b9
JG		 102
103/*
104 * Copy from radeon_drv.h so we don't have to include both and have conflicting
105 * symbol;
106 */
bb635567
JG		 107#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
108#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 109/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 110#define RADEON_IB_POOL_SIZE 16
111#define RADEON_DEBUGFS_MAX_COMPONENTS 32
112#define RADEONFB_CONN_LIMIT 4
113#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 114
1b37078b 115/* max number of rings */
f2ba57b5 116#define RADEON_NUM_RINGS 6
bb635567
JG		 117
118/* fence seq are set to this number when signaled */
119#define RADEON_FENCE_SIGNALED_SEQ 0LL
1b37078b
AD		 120
121/* internal ring indices */
122/* r1xx+ has gfx CP ring */
f2ba57b5 123#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 124
125/* cayman has 2 compute CP rings */
f2ba57b5
CK		 126#define CAYMAN_RING_TYPE_CP1_INDEX 1
127#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 128
4d75658b
AD		 129/* R600+ has an async dma ring */
130#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 131/* cayman add a second async dma ring */
132#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 133
f2ba57b5
CK		 134/* R600+ */
135#define R600_RING_TYPE_UVD_INDEX 5
136
721604a1 137/* hardcode those limit for now */
ca19f21e 138#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 139#define RADEON_VA_RESERVED_SIZE (8 << 20)
140#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 141
ec46c76d
AD		 142/* reset flags */
143#define RADEON_RESET_GFX (1 << 0)
144#define RADEON_RESET_COMPUTE (1 << 1)
145#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 146#define RADEON_RESET_CP (1 << 3)
147#define RADEON_RESET_GRBM (1 << 4)
148#define RADEON_RESET_DMA1 (1 << 5)
149#define RADEON_RESET_RLC (1 << 6)
150#define RADEON_RESET_SEM (1 << 7)
151#define RADEON_RESET_IH (1 << 8)
152#define RADEON_RESET_VMC (1 << 9)
153#define RADEON_RESET_MC (1 << 10)
154#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 155
22c775ce
AD		 156/* CG block flags */
157#define RADEON_CG_BLOCK_GFX (1 << 0)
158#define RADEON_CG_BLOCK_MC (1 << 1)
159#define RADEON_CG_BLOCK_SDMA (1 << 2)
160#define RADEON_CG_BLOCK_UVD (1 << 3)
161#define RADEON_CG_BLOCK_VCE (1 << 4)
162#define RADEON_CG_BLOCK_HDP (1 << 5)
e16866ec 163#define RADEON_CG_BLOCK_BIF (1 << 6)
22c775ce 164
64d8a728
AD		 165/* CG flags */
166#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
167#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
168#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
169#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
170#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
171#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
172#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
173#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
174#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
175#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
176#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
177#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
178#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
179#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
180#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
181#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
182#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
183
184/* PG flags */
2b19d17f 185#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
64d8a728
AD		 186#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
187#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
188#define RADEON_PG_SUPPORT_UVD (1 << 3)
189#define RADEON_PG_SUPPORT_VCE (1 << 4)
190#define RADEON_PG_SUPPORT_CP (1 << 5)
191#define RADEON_PG_SUPPORT_GDS (1 << 6)
192#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
193#define RADEON_PG_SUPPORT_SDMA (1 << 8)
194#define RADEON_PG_SUPPORT_ACP (1 << 9)
195#define RADEON_PG_SUPPORT_SAMU (1 << 10)
196
9e05fa1d
AD		 197/* max cursor sizes (in pixels) */
198#define CURSOR_WIDTH 64
199#define CURSOR_HEIGHT 64
200
201#define CIK_CURSOR_WIDTH 128
202#define CIK_CURSOR_HEIGHT 128
203
771fe6b9
JG		 204/*
205 * Errata workarounds.
206 */
207enum radeon_pll_errata {
208 CHIP_ERRATA_R300_CG = 0x00000001,
209 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
210 CHIP_ERRATA_PLL_DELAY = 0x00000004
211};
212
213
214struct radeon_device;
215
216
217/*
218 * BIOS.
219 */
220bool radeon_get_bios(struct radeon_device *rdev);
221
222/*
3ce0a23d 223 * Dummy page
771fe6b9 224 */
3ce0a23d
JG		 225struct radeon_dummy_page {
226 struct page *page;
227 dma_addr_t addr;
228};
229int radeon_dummy_page_init(struct radeon_device *rdev);
230void radeon_dummy_page_fini(struct radeon_device *rdev);
231
771fe6b9 232
3ce0a23d
JG		 233/*
234 * Clocks
235 */
771fe6b9
JG		 236struct radeon_clock {
237 struct radeon_pll p1pll;
238 struct radeon_pll p2pll;
bcc1c2a1 239 struct radeon_pll dcpll;
771fe6b9
JG		 240 struct radeon_pll spll;
241 struct radeon_pll mpll;
242 /* 10 Khz units */
243 uint32_t default_mclk;
244 uint32_t default_sclk;
bcc1c2a1 245 uint32_t default_dispclk;
4489cd62 246 uint32_t current_dispclk;
bcc1c2a1 247 uint32_t dp_extclk;
b20f9bef 248 uint32_t max_pixel_clock;
771fe6b9
JG		 249};
250
7433874e
RM		 251/*
252 * Power management
253 */
254int radeon_pm_init(struct radeon_device *rdev);
914a8987 255int radeon_pm_late_init(struct radeon_device *rdev);
29fb52ca 256void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 257void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 258void radeon_pm_suspend(struct radeon_device *rdev);
259void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 260void radeon_combios_get_power_modes(struct radeon_device *rdev);
261void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 262int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
263 u8 clock_type,
264 u32 clock,
265 bool strobe_mode,
266 struct atom_clock_dividers *dividers);
eaa778af
AD		 267int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
268 u32 clock,
269 bool strobe_mode,
270 struct atom_mpll_param *mpll_param);
8a83ec5e 271void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 272int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
273 u16 voltage_level, u8 voltage_type,
274 u32 *gpio_value, u32 *gpio_mask);
275void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
276 u32 eng_clock, u32 mem_clock);
277int radeon_atom_get_voltage_step(struct radeon_device *rdev,
278 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 279int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
280 u16 voltage_id, u16 *voltage);
beb79f40
AD		 281int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
282 u16 *voltage,
283 u16 leakage_idx);
cc8dbbb4
AD		 284int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
285 u16 *leakage_id);
286int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
287 u16 *vddc, u16 *vddci,
288 u16 virtual_voltage_id,
289 u16 vbios_voltage_id);
ae5b0abb
AD		 290int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
291 u8 voltage_type,
292 u16 nominal_voltage,
293 u16 *true_voltage);
294int radeon_atom_get_min_voltage(struct radeon_device *rdev,
295 u8 voltage_type, u16 *min_voltage);
296int radeon_atom_get_max_voltage(struct radeon_device *rdev,
297 u8 voltage_type, u16 *max_voltage);
298int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 299 u8 voltage_type, u8 voltage_mode,
ae5b0abb 300 struct atom_voltage_table *voltage_table);
58653abd
AD		 301bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
302 u8 voltage_type, u8 voltage_mode);
ae5b0abb
AD		 303void radeon_atom_update_memory_dll(struct radeon_device *rdev,
304 u32 mem_clock);
305void radeon_atom_set_ac_timing(struct radeon_device *rdev,
306 u32 mem_clock);
307int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
308 u8 module_index,
309 struct atom_mc_reg_table *reg_table);
310int radeon_atom_get_memory_info(struct radeon_device *rdev,
311 u8 module_index, struct atom_memory_info *mem_info);
312int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
313 bool gddr5, u8 module_index,
314 struct atom_memory_clock_range_table *mclk_range_table);
315int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
316 u16 voltage_id, u16 *voltage);
f892034a 317void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 318extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
319 unsigned *bankh, unsigned *mtaspect,
320 unsigned *tile_split);
3ce0a23d 321
771fe6b9
JG		 322/*
323 * Fences.
324 */
325struct radeon_fence_driver {
326 uint32_t scratch_reg;
30eb77f4
JG		 327 uint64_t gpu_addr;
328 volatile uint32_t *cpu_addr;
68e250b7
CK		 329 /* sync_seq is protected by ring emission lock */
330 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 331 atomic64_t last_seq;
0a0c7596 332 bool initialized;
771fe6b9
JG		 333};
334
335struct radeon_fence {
336 struct radeon_device *rdev;
337 struct kref kref;
771fe6b9 338 /* protected by radeon_fence.lock */
bb635567 339 uint64_t seq;
7465280c 340 /* RB, DMA, etc. */
bb635567 341 unsigned ring;
771fe6b9
JG		 342};
343
30eb77f4
JG		 344int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
345int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 346void radeon_fence_driver_fini(struct radeon_device *rdev);
76903b96 347void radeon_fence_driver_force_completion(struct radeon_device *rdev);
876dc9f3 348int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 349void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 350bool radeon_fence_signaled(struct radeon_fence *fence);
351int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
1654b817 352int radeon_fence_wait_locked(struct radeon_fence *fence);
8a47cc9e 353int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
5f8f635e 354int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
0085c950
JG		 355int radeon_fence_wait_any(struct radeon_device *rdev,
356 struct radeon_fence **fences,
357 bool intr);
771fe6b9
JG		 358struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
359void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 360unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 361bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
362void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
363static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
364 struct radeon_fence *b)
365{
366 if (!a) {
367 return b;
368 }
369
370 if (!b) {
371 return a;
372 }
373
374 BUG_ON(a->ring != b->ring);
375
376 if (a->seq > b->seq) {
377 return a;
378 } else {
379 return b;
380 }
381}
771fe6b9 382
ee60e29f
CK		 383static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
384 struct radeon_fence *b)
385{
386 if (!a) {
387 return false;
388 }
389
390 if (!b) {
391 return true;
392 }
393
394 BUG_ON(a->ring != b->ring);
395
396 return a->seq < b->seq;
397}
398
e024e110
DA		 399/*
400 * Tiling registers
401 */
402struct radeon_surface_reg {
4c788679 403 struct radeon_bo *bo;
e024e110
DA		 404};
405
406#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 407
408/*
4c788679 409 * TTM.
771fe6b9 410 */
4c788679
JG		 411struct radeon_mman {
412 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 413 struct drm_global_reference mem_global_ref;
4c788679 414 struct ttm_bo_device bdev;
0a0c7596
JG		 415 bool mem_global_referenced;
416 bool initialized;
2014b569
CK		 417
418#if defined(CONFIG_DEBUG_FS)
419 struct dentry *vram;
dd66d20e 420 struct dentry *gtt;
2014b569 421#endif
4c788679
JG		 422};
423
721604a1
JG		 424/* bo virtual address in a specific vm */
425struct radeon_bo_va {
e971bd5e 426 /* protected by bo being reserved */
721604a1 427 struct list_head bo_list;
721604a1
JG		 428 uint64_t soffset;
429 uint64_t eoffset;
430 uint32_t flags;
431 bool valid;
e971bd5e
CK		 432 unsigned ref_count;
433
434 /* protected by vm mutex */
435 struct list_head vm_list;
436
437 /* constant after initialization */
438 struct radeon_vm *vm;
439 struct radeon_bo *bo;
721604a1
JG		 440};
441
4c788679
JG		 442struct radeon_bo {
443 /* Protected by gem.mutex */
444 struct list_head list;
445 /* Protected by tbo.reserved */
312ea8da
JG		 446 u32 placements[3];
447 struct ttm_placement placement;
4c788679
JG		 448 struct ttm_buffer_object tbo;
449 struct ttm_bo_kmap_obj kmap;
450 unsigned pin_count;
451 void *kptr;
452 u32 tiling_flags;
453 u32 pitch;
454 int surface_reg;
721604a1
JG		 455 /* list of all virtual address to which this bo
456 * is associated to
457 */
458 struct list_head va;
4c788679
JG		 459 /* Constant after initialization */
460 struct radeon_device *rdev;
441921d5 461 struct drm_gem_object gem_base;
63bc620b 462
409851f4
JG		 463 struct ttm_bo_kmap_obj dma_buf_vmap;
464 pid_t pid;
4c788679 465};
7e4d15d9 466#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 467
4c788679 468struct radeon_bo_list {
147666fb 469 struct ttm_validate_buffer tv;
4c788679 470 struct radeon_bo *bo;
771fe6b9 471 uint64_t gpu_offset;
4474f3a9
CK		 472 bool written;
473 unsigned domain;
474 unsigned alt_domain;
4c788679 475 u32 tiling_flags;
771fe6b9
JG		 476};
477
409851f4
JG		 478int radeon_gem_debugfs_init(struct radeon_device *rdev);
479
b15ba512
JG		 480/* sub-allocation manager, it has to be protected by another lock.
481 * By conception this is an helper for other part of the driver
482 * like the indirect buffer or semaphore, which both have their
483 * locking.
484 *
485 * Principe is simple, we keep a list of sub allocation in offset
486 * order (first entry has offset == 0, last entry has the highest
487 * offset).
488 *
489 * When allocating new object we first check if there is room at
490 * the end total_size - (last_object_offset + last_object_size) >=
491 * alloc_size. If so we allocate new object there.
492 *
493 * When there is not enough room at the end, we start waiting for
494 * each sub object until we reach object_offset+object_size >=
495 * alloc_size, this object then become the sub object we return.
496 *
497 * Alignment can't be bigger than page size.
498 *
499 * Hole are not considered for allocation to keep things simple.
500 * Assumption is that there won't be hole (all object on same
501 * alignment).
502 */
503struct radeon_sa_manager {
bfb38d35 504 wait_queue_head_t wq;
b15ba512 505 struct radeon_bo *bo;
c3b7fe8b
CK		 506 struct list_head *hole;
507 struct list_head flist[RADEON_NUM_RINGS];
508 struct list_head olist;
b15ba512
JG		 509 unsigned size;
510 uint64_t gpu_addr;
511 void *cpu_ptr;
512 uint32_t domain;
6c4f978b 513 uint32_t align;
b15ba512
JG		 514};
515
516struct radeon_sa_bo;
517
518/* sub-allocation buffer */
519struct radeon_sa_bo {
c3b7fe8b
CK		 520 struct list_head olist;
521 struct list_head flist;
b15ba512 522 struct radeon_sa_manager *manager;
e6661a96
CK		 523 unsigned soffset;
524 unsigned eoffset;
557017a0 525 struct radeon_fence *fence;
b15ba512
JG		 526};
527
771fe6b9
JG		 528/*
529 * GEM objects.
530 */
531struct radeon_gem {
4c788679 532 struct mutex mutex;
771fe6b9
JG		 533 struct list_head objects;
534};
535
536int radeon_gem_init(struct radeon_device *rdev);
537void radeon_gem_fini(struct radeon_device *rdev);
538int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 539 int alignment, int initial_domain,
540 bool discardable, bool kernel,
541 struct drm_gem_object **obj);
771fe6b9 542
ff72145b
DA		 543int radeon_mode_dumb_create(struct drm_file *file_priv,
544 struct drm_device *dev,
545 struct drm_mode_create_dumb *args);
546int radeon_mode_dumb_mmap(struct drm_file *filp,
547 struct drm_device *dev,
548 uint32_t handle, uint64_t *offset_p);
771fe6b9 549
c1341e52
JG		 550/*
551 * Semaphores.
552 */
c1341e52
JG		 553/* everything here is constant */
554struct radeon_semaphore {
a8c05940
JG		 555 struct radeon_sa_bo *sa_bo;
556 signed waiters;
c1341e52 557 uint64_t gpu_addr;
1654b817 558 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
c1341e52
JG		 559};
560
c1341e52
JG		 561int radeon_semaphore_create(struct radeon_device *rdev,
562 struct radeon_semaphore **semaphore);
1654b817 563bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
c1341e52 564 struct radeon_semaphore *semaphore);
1654b817 565bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
c1341e52 566 struct radeon_semaphore *semaphore);
1654b817
CK		 567void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
568 struct radeon_fence *fence);
8f676c4c
CK		 569int radeon_semaphore_sync_rings(struct radeon_device *rdev,
570 struct radeon_semaphore *semaphore,
1654b817 571 int waiting_ring);
c1341e52 572void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 573 struct radeon_semaphore **semaphore,
a8c05940 574 struct radeon_fence *fence);
c1341e52 575
771fe6b9
JG		 576/*
577 * GART structures, functions & helpers
578 */
579struct radeon_mc;
580
a77f1718 581#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 582#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 583#define RADEON_GPU_PAGE_SHIFT 12
721604a1 584#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 585
771fe6b9
JG		 586struct radeon_gart {
587 dma_addr_t table_addr;
c9a1be96
JG		 588 struct radeon_bo *robj;
589 void *ptr;
771fe6b9
JG		 590 unsigned num_gpu_pages;
591 unsigned num_cpu_pages;
592 unsigned table_size;
771fe6b9
JG		 593 struct page **pages;
594 dma_addr_t *pages_addr;
595 bool ready;
596};
597
598int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
599void radeon_gart_table_ram_free(struct radeon_device *rdev);
600int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
601void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 602int radeon_gart_table_vram_pin(struct radeon_device *rdev);
603void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 604int radeon_gart_init(struct radeon_device *rdev);
605void radeon_gart_fini(struct radeon_device *rdev);
606void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
607 int pages);
608int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516
KRW		 609 int pages, struct page **pagelist,
610 dma_addr_t *dma_addr);
c9a1be96 611void radeon_gart_restore(struct radeon_device *rdev);
771fe6b9
JG		 612
613
614/*
615 * GPU MC structures, functions & helpers
616 */
617struct radeon_mc {
618 resource_size_t aper_size;
619 resource_size_t aper_base;
620 resource_size_t agp_base;
7a50f01a
DA		 621 /* for some chips with <= 32MB we need to lie
622 * about vram size near mc fb location */
3ce0a23d 623 u64 mc_vram_size;
d594e46a 624 u64 visible_vram_size;
3ce0a23d
JG		 625 u64 gtt_size;
626 u64 gtt_start;
627 u64 gtt_end;
3ce0a23d
JG		 628 u64 vram_start;
629 u64 vram_end;
771fe6b9 630 unsigned vram_width;
3ce0a23d 631 u64 real_vram_size;
771fe6b9
JG		 632 int vram_mtrr;
633 bool vram_is_ddr;
d594e46a 634 bool igp_sideport_enabled;
8d369bb1 635 u64 gtt_base_align;
9ed8b1f9 636 u64 mc_mask;
771fe6b9
JG		 637};
638
06b6476d
AD		 639bool radeon_combios_sideport_present(struct radeon_device *rdev);
640bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 641
642/*
643 * GPU scratch registers structures, functions & helpers
644 */
645struct radeon_scratch {
646 unsigned num_reg;
724c80e1 647 uint32_t reg_base;
771fe6b9
JG		 648 bool free[32];
649 uint32_t reg[32];
650};
651
652int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
653void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
654
75efdee1
AD		 655/*
656 * GPU doorbell structures, functions & helpers
657 */
d5754ab8
AL		 658#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
659
75efdee1 660struct radeon_doorbell {
75efdee1 661 /* doorbell mmio */
d5754ab8
AL		 662 resource_size_t base;
663 resource_size_t size;
664 u32 __iomem *ptr;
665 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
666 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
75efdee1
AD		 667};
668
669int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
670void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771fe6b9
JG		 671
672/*
673 * IRQS.
674 */
6f34be50
AD		 675
676struct radeon_unpin_work {
677 struct work_struct work;
678 struct radeon_device *rdev;
679 int crtc_id;
680 struct radeon_fence *fence;
681 struct drm_pending_vblank_event *event;
682 struct radeon_bo *old_rbo;
683 u64 new_crtc_base;
684};
685
686struct r500_irq_stat_regs {
687 u32 disp_int;
f122c610 688 u32 hdmi0_status;
6f34be50
AD		 689};
690
691struct r600_irq_stat_regs {
692 u32 disp_int;
693 u32 disp_int_cont;
694 u32 disp_int_cont2;
695 u32 d1grph_int;
696 u32 d2grph_int;
f122c610
AD		 697 u32 hdmi0_status;
698 u32 hdmi1_status;
6f34be50
AD		 699};
700
701struct evergreen_irq_stat_regs {
702 u32 disp_int;
703 u32 disp_int_cont;
704 u32 disp_int_cont2;
705 u32 disp_int_cont3;
706 u32 disp_int_cont4;
707 u32 disp_int_cont5;
708 u32 d1grph_int;
709 u32 d2grph_int;
710 u32 d3grph_int;
711 u32 d4grph_int;
712 u32 d5grph_int;
713 u32 d6grph_int;
f122c610
AD		 714 u32 afmt_status1;
715 u32 afmt_status2;
716 u32 afmt_status3;
717 u32 afmt_status4;
718 u32 afmt_status5;
719 u32 afmt_status6;
6f34be50
AD		 720};
721
a59781bb
AD		 722struct cik_irq_stat_regs {
723 u32 disp_int;
724 u32 disp_int_cont;
725 u32 disp_int_cont2;
726 u32 disp_int_cont3;
727 u32 disp_int_cont4;
728 u32 disp_int_cont5;
729 u32 disp_int_cont6;
730};
731
6f34be50
AD		 732union radeon_irq_stat_regs {
733 struct r500_irq_stat_regs r500;
734 struct r600_irq_stat_regs r600;
735 struct evergreen_irq_stat_regs evergreen;
a59781bb 736 struct cik_irq_stat_regs cik;
6f34be50
AD		 737};
738
54bd5206
IH		 739#define RADEON_MAX_HPD_PINS 6
740#define RADEON_MAX_CRTCS 6
b530602f 741#define RADEON_MAX_AFMT_BLOCKS 7
54bd5206 742
771fe6b9 743struct radeon_irq {
fb98257a
CK		 744 bool installed;
745 spinlock_t lock;
736fc37f 746 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 747 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 748 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 749 wait_queue_head_t vblank_queue;
750 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 751 bool afmt[RADEON_MAX_AFMT_BLOCKS];
752 union radeon_irq_stat_regs stat_regs;
4a6369e9 753 bool dpm_thermal;
771fe6b9
JG		 754};
755
756int radeon_irq_kms_init(struct radeon_device *rdev);
757void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b
AD		 758void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
759void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 760void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
761void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 762void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
763void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
764void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
765void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 766
767/*
e32eb50d 768 * CP & rings.
771fe6b9 769 */
7465280c 770
771fe6b9 771struct radeon_ib {
68470ae7
JG		 772 struct radeon_sa_bo *sa_bo;
773 uint32_t length_dw;
774 uint64_t gpu_addr;
775 uint32_t *ptr;
876dc9f3 776 int ring;
68470ae7 777 struct radeon_fence *fence;
4bf3dd92 778 struct radeon_vm *vm;
68470ae7
JG		 779 bool is_const_ib;
780 struct radeon_semaphore *semaphore;
771fe6b9
JG		 781};
782
e32eb50d 783struct radeon_ring {
4c788679 784 struct radeon_bo *ring_obj;
771fe6b9
JG		 785 volatile uint32_t *ring;
786 unsigned rptr;
5596a9db
CK		 787 unsigned rptr_offs;
788 unsigned rptr_reg;
45df6803 789 unsigned rptr_save_reg;
89d35807
AD		 790 u64 next_rptr_gpu_addr;
791 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 792 unsigned wptr;
793 unsigned wptr_old;
5596a9db 794 unsigned wptr_reg;
771fe6b9
JG		 795 unsigned ring_size;
796 unsigned ring_free_dw;
797 int count_dw;
069211e5
CK		 798 unsigned long last_activity;
799 unsigned last_rptr;
771fe6b9
JG		 800 uint64_t gpu_addr;
801 uint32_t align_mask;
802 uint32_t ptr_mask;
771fe6b9 803 bool ready;
78c5560a 804 u32 nop;
8b25ed34 805 u32 idx;
5f0839c1
JG		 806 u64 last_semaphore_signal_addr;
807 u64 last_semaphore_wait_addr;
963e81f9
AD		 808 /* for CIK queues */
809 u32 me;
810 u32 pipe;
811 u32 queue;
812 struct radeon_bo *mqd_obj;
d5754ab8 813 u32 doorbell_index;
963e81f9
AD		 814 unsigned wptr_offs;
815};
816
817struct radeon_mec {
818 struct radeon_bo *hpd_eop_obj;
819 u64 hpd_eop_gpu_addr;
820 u32 num_pipe;
821 u32 num_mec;
822 u32 num_queue;
771fe6b9
JG		 823};
824
721604a1
JG		 825/*
826 * VM
827 */
ee60e29f 828
fa87e62d 829/* maximum number of VMIDs */
ee60e29f
CK		 830#define RADEON_NUM_VM 16
831
fa87e62d
DC		 832/* defines number of bits in page table versus page directory,
833 * a page is 4KB so we have 12 bits offset, 9 bits in the page
834 * table and the remaining 19 bits are in the page directory */
835#define RADEON_VM_BLOCK_SIZE 9
836
837/* number of entries in page table */
838#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
839
1c01103c
AD		 840/* PTBs (Page Table Blocks) need to be aligned to 32K */
841#define RADEON_VM_PTB_ALIGN_SIZE 32768
842#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
843#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
844
24c16439
CK		 845#define R600_PTE_VALID (1 << 0)
846#define R600_PTE_SYSTEM (1 << 1)
847#define R600_PTE_SNOOPED (1 << 2)
848#define R600_PTE_READABLE (1 << 5)
849#define R600_PTE_WRITEABLE (1 << 6)
850
721604a1
JG		 851struct radeon_vm {
852 struct list_head list;
853 struct list_head va;
ee60e29f 854 unsigned id;
90a51a32
CK		 855
856 /* contains the page directory */
857 struct radeon_sa_bo *page_directory;
858 uint64_t pd_gpu_addr;
859
860 /* array of page tables, one for each page directory entry */
861 struct radeon_sa_bo **page_tables;
862
721604a1
JG		 863 struct mutex mutex;
864 /* last fence for cs using this vm */
865 struct radeon_fence *fence;
9b40e5d8
CK		 866 /* last flush or NULL if we still need to flush */
867 struct radeon_fence *last_flush;
721604a1
JG		 868};
869
721604a1 870struct radeon_vm_manager {
36ff39c4 871 struct mutex lock;
721604a1 872 struct list_head lru_vm;
ee60e29f 873 struct radeon_fence *active[RADEON_NUM_VM];
721604a1
JG		 874 struct radeon_sa_manager sa_manager;
875 uint32_t max_pfn;
721604a1
JG		 876 /* number of VMIDs */
877 unsigned nvm;
878 /* vram base address for page table entry */
879 u64 vram_base_offset;
67e915e4
AD		 880 /* is vm enabled? */
881 bool enabled;
721604a1
JG		 882};
883
884/*
885 * file private structure
886 */
887struct radeon_fpriv {
888 struct radeon_vm vm;
889};
890
d8f60cfc
AD		 891/*
892 * R6xx+ IH ring
893 */
894struct r600_ih {
4c788679 895 struct radeon_bo *ring_obj;
d8f60cfc
AD		 896 volatile uint32_t *ring;
897 unsigned rptr;
d8f60cfc
AD		 898 unsigned ring_size;
899 uint64_t gpu_addr;
d8f60cfc 900 uint32_t ptr_mask;
c20dc369 901 atomic_t lock;
d8f60cfc
AD		 902 bool enabled;
903};
904
347e7592 905/*
2948f5e6 906 * RLC stuff
347e7592 907 */
2948f5e6
AD		 908#include "clearstate_defs.h"
909
910struct radeon_rlc {
347e7592
AD		 911 /* for power gating */
912 struct radeon_bo *save_restore_obj;
913 uint64_t save_restore_gpu_addr;
2948f5e6 914 volatile uint32_t *sr_ptr;
1fd11777 915 const u32 *reg_list;
2948f5e6 916 u32 reg_list_size;
347e7592
AD		 917 /* for clear state */
918 struct radeon_bo *clear_state_obj;
919 uint64_t clear_state_gpu_addr;
2948f5e6 920 volatile uint32_t *cs_ptr;
1fd11777 921 const struct cs_section_def *cs_data;
22c775ce
AD		 922 u32 clear_state_size;
923 /* for cp tables */
924 struct radeon_bo *cp_table_obj;
925 uint64_t cp_table_gpu_addr;
926 volatile uint32_t *cp_table_ptr;
927 u32 cp_table_size;
347e7592
AD		 928};
929
69e130a6 930int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 931 struct radeon_ib *ib, struct radeon_vm *vm,
932 unsigned size);
f2e39221 933void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
4ef72566
CK		 934int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
935 struct radeon_ib *const_ib);
771fe6b9
JG		 936int radeon_ib_pool_init(struct radeon_device *rdev);
937void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 938int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 939/* Ring access between begin & end cannot sleep */
89d35807
AD		 940bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
941 struct radeon_ring *ring);
e32eb50d
CK		 942void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
943int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
944int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
945void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
946void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
d6999bc7 947void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 948void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
949int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
7b9ef16b 950void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
069211e5
CK		 951void radeon_ring_lockup_update(struct radeon_ring *ring);
952bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 953unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
954 uint32_t **data);
955int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
956 unsigned size, uint32_t *data);
e32eb50d 957int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
2e1e6dad 958 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, u32 nop);
e32eb50d 959void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 960
961
4d75658b
AD		 962/* r600 async dma */
963void r600_dma_stop(struct radeon_device *rdev);
964int r600_dma_resume(struct radeon_device *rdev);
965void r600_dma_fini(struct radeon_device *rdev);
966
8c5fd7ef
AD		 967void cayman_dma_stop(struct radeon_device *rdev);
968int cayman_dma_resume(struct radeon_device *rdev);
969void cayman_dma_fini(struct radeon_device *rdev);
970
771fe6b9
JG		 971/*
972 * CS.
973 */
974struct radeon_cs_reloc {
975 struct drm_gem_object *gobj;
4c788679
JG		 976 struct radeon_bo *robj;
977 struct radeon_bo_list lobj;
771fe6b9
JG		 978 uint32_t handle;
979 uint32_t flags;
980};
981
982struct radeon_cs_chunk {
983 uint32_t chunk_id;
984 uint32_t length_dw;
985 uint32_t *kdata;
721604a1 986 void __user *user_ptr;
771fe6b9
JG		 987};
988
989struct radeon_cs_parser {
c8c15ff1 990 struct device *dev;
771fe6b9
JG		 991 struct radeon_device *rdev;
992 struct drm_file *filp;
993 /* chunks */
994 unsigned nchunks;
995 struct radeon_cs_chunk *chunks;
996 uint64_t *chunks_array;
997 /* IB */
998 unsigned idx;
999 /* relocations */
1000 unsigned nrelocs;
1001 struct radeon_cs_reloc *relocs;
1002 struct radeon_cs_reloc **relocs_ptr;
1003 struct list_head validated;
cf4ccd01 1004 unsigned dma_reloc_idx;
771fe6b9
JG		 1005 /* indices of various chunks */
1006 int chunk_ib_idx;
1007 int chunk_relocs_idx;
721604a1 1008 int chunk_flags_idx;
dfcf5f36 1009 int chunk_const_ib_idx;
f2e39221
JG		 1010 struct radeon_ib ib;
1011 struct radeon_ib const_ib;
771fe6b9 1012 void *track;
3ce0a23d 1013 unsigned family;
e70f224c 1014 int parser_error;
721604a1
JG		 1015 u32 cs_flags;
1016 u32 ring;
1017 s32 priority;
ecff665f 1018 struct ww_acquire_ctx ticket;
771fe6b9
JG		 1019};
1020
28a326c5
ML		 1021static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1022{
1023 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1024
1025 if (ibc->kdata)
1026 return ibc->kdata[idx];
1027 return p->ib.ptr[idx];
1028}
1029
513bcb46 1030
771fe6b9
JG		 1031struct radeon_cs_packet {
1032 unsigned idx;
1033 unsigned type;
1034 unsigned reg;
1035 unsigned opcode;
1036 int count;
1037 unsigned one_reg_wr;
1038};
1039
1040typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1041 struct radeon_cs_packet *pkt,
1042 unsigned idx, unsigned reg);
1043typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1044 struct radeon_cs_packet *pkt);
1045
1046
1047/*
1048 * AGP
1049 */
1050int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1051void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1052void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1053void radeon_agp_fini(struct radeon_device *rdev);
1054
1055
1056/*
1057 * Writeback
1058 */
1059struct radeon_wb {
4c788679 1060 struct radeon_bo *wb_obj;
771fe6b9
JG		 1061 volatile uint32_t *wb;
1062 uint64_t gpu_addr;
724c80e1 1063 bool enabled;
d0f8a854 1064 bool use_event;
771fe6b9
JG		 1065};
1066
724c80e1 1067#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1068#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1069#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1070#define RADEON_WB_CP1_RPTR_OFFSET 1280
1071#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1072#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1073#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1074#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1075#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1076#define CIK_WB_CP1_WPTR_OFFSET 3328
1077#define CIK_WB_CP2_WPTR_OFFSET 3584
724c80e1 1078
c93bb85b
JG		 1079/**
1080 * struct radeon_pm - power management datas
1081 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1082 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1083 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1084 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1085 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1086 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1087 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1088 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1089 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1090 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1091 * @needed_bandwidth: current bandwidth needs
1092 *
1093 * It keeps track of various data needed to take powermanagement decision.
25985edc 1094 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1095 * Equation between gpu/memory clock and available bandwidth is hw dependent
1096 * (type of memory, bus size, efficiency, ...)
1097 */
ce8f5370
AD		 1098
1099enum radeon_pm_method {
1100 PM_METHOD_PROFILE,
1101 PM_METHOD_DYNPM,
da321c8a 1102 PM_METHOD_DPM,
ce8f5370
AD		 1103};
1104
1105enum radeon_dynpm_state {
1106 DYNPM_STATE_DISABLED,
1107 DYNPM_STATE_MINIMUM,
1108 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1109 DYNPM_STATE_ACTIVE,
1110 DYNPM_STATE_SUSPENDED,
c913e23a 1111};
ce8f5370
AD		 1112enum radeon_dynpm_action {
1113 DYNPM_ACTION_NONE,
1114 DYNPM_ACTION_MINIMUM,
1115 DYNPM_ACTION_DOWNCLOCK,
1116 DYNPM_ACTION_UPCLOCK,
1117 DYNPM_ACTION_DEFAULT
c913e23a 1118};
56278a8e
AD		 1119
1120enum radeon_voltage_type {
1121 VOLTAGE_NONE = 0,
1122 VOLTAGE_GPIO,
1123 VOLTAGE_VDDC,
1124 VOLTAGE_SW
1125};
1126
0ec0e74f 1127enum radeon_pm_state_type {
da321c8a 1128 /* not used for dpm */
0ec0e74f
AD		 1129 POWER_STATE_TYPE_DEFAULT,
1130 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1131 /* user selectable states */
0ec0e74f
AD		 1132 POWER_STATE_TYPE_BATTERY,
1133 POWER_STATE_TYPE_BALANCED,
1134 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1135 /* internal states */
1136 POWER_STATE_TYPE_INTERNAL_UVD,
1137 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1138 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1139 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1140 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1141 POWER_STATE_TYPE_INTERNAL_BOOT,
1142 POWER_STATE_TYPE_INTERNAL_THERMAL,
1143 POWER_STATE_TYPE_INTERNAL_ACPI,
1144 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1145 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1146};
1147
ce8f5370
AD		 1148enum radeon_pm_profile_type {
1149 PM_PROFILE_DEFAULT,
1150 PM_PROFILE_AUTO,
1151 PM_PROFILE_LOW,
c9e75b21 1152 PM_PROFILE_MID,
ce8f5370
AD		 1153 PM_PROFILE_HIGH,
1154};
1155
1156#define PM_PROFILE_DEFAULT_IDX 0
1157#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1158#define PM_PROFILE_MID_SH_IDX 2
1159#define PM_PROFILE_HIGH_SH_IDX 3
1160#define PM_PROFILE_LOW_MH_IDX 4
1161#define PM_PROFILE_MID_MH_IDX 5
1162#define PM_PROFILE_HIGH_MH_IDX 6
1163#define PM_PROFILE_MAX 7
ce8f5370
AD		 1164
1165struct radeon_pm_profile {
1166 int dpms_off_ps_idx;
1167 int dpms_on_ps_idx;
1168 int dpms_off_cm_idx;
1169 int dpms_on_cm_idx;
516d0e46
AD		 1170};
1171
21a8122a
AD		 1172enum radeon_int_thermal_type {
1173 THERMAL_TYPE_NONE,
da321c8a
AD		 1174 THERMAL_TYPE_EXTERNAL,
1175 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1176 THERMAL_TYPE_RV6XX,
1177 THERMAL_TYPE_RV770,
da321c8a 1178 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1179 THERMAL_TYPE_EVERGREEN,
e33df25f 1180 THERMAL_TYPE_SUMO,
4fddba1f 1181 THERMAL_TYPE_NI,
14607d08 1182 THERMAL_TYPE_SI,
da321c8a 1183 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1184 THERMAL_TYPE_CI,
16fbe00d 1185 THERMAL_TYPE_KV,
21a8122a
AD		 1186};
1187
56278a8e
AD		 1188struct radeon_voltage {
1189 enum radeon_voltage_type type;
1190 /* gpio voltage */
1191 struct radeon_gpio_rec gpio;
1192 u32 delay; /* delay in usec from voltage drop to sclk change */
1193 bool active_high; /* voltage drop is active when bit is high */
1194 /* VDDC voltage */
1195 u8 vddc_id; /* index into vddc voltage table */
1196 u8 vddci_id; /* index into vddci voltage table */
1197 bool vddci_enabled;
1198 /* r6xx+ sw */
2feea49a
AD		 1199 u16 voltage;
1200 /* evergreen+ vddci */
1201 u16 vddci;
56278a8e
AD		 1202};
1203
d7311171
AD		 1204/* clock mode flags */
1205#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1206
56278a8e
AD		 1207struct radeon_pm_clock_info {
1208 /* memory clock */
1209 u32 mclk;
1210 /* engine clock */
1211 u32 sclk;
1212 /* voltage info */
1213 struct radeon_voltage voltage;
d7311171 1214 /* standardized clock flags */
56278a8e
AD		 1215 u32 flags;
1216};
1217
a48b9b4e 1218/* state flags */
d7311171 1219#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1220
56278a8e 1221struct radeon_power_state {
0ec0e74f 1222 enum radeon_pm_state_type type;
8f3f1c9a 1223 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1224 /* number of valid clock modes in this power state */
1225 int num_clock_modes;
56278a8e 1226 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1227 /* standardized state flags */
1228 u32 flags;
79daedc9
AD		 1229 u32 misc; /* vbios specific flags */
1230 u32 misc2; /* vbios specific flags */
1231 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1232};
1233
27459324
RM		 1234/*
1235 * Some modes are overclocked by very low value, accept them
1236 */
1237#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1238
2e9d4c05
AD		 1239enum radeon_dpm_auto_throttle_src {
1240 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1241 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1242};
1243
1244enum radeon_dpm_event_src {
1245 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1246 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1247 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1248 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1249 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1250};
1251
da321c8a
AD		 1252struct radeon_ps {
1253 u32 caps; /* vbios flags */
1254 u32 class; /* vbios flags */
1255 u32 class2; /* vbios flags */
1256 /* UVD clocks */
1257 u32 vclk;
1258 u32 dclk;
c4453e66
AD		 1259 /* VCE clocks */
1260 u32 evclk;
1261 u32 ecclk;
da321c8a
AD		 1262 /* asic priv */
1263 void *ps_priv;
1264};
1265
1266struct radeon_dpm_thermal {
1267 /* thermal interrupt work */
1268 struct work_struct work;
1269 /* low temperature threshold */
1270 int min_temp;
1271 /* high temperature threshold */
1272 int max_temp;
1273 /* was interrupt low to high or high to low */
1274 bool high_to_low;
1275};
1276
d22b7e40
AD		 1277enum radeon_clk_action
1278{
1279 RADEON_SCLK_UP = 1,
1280 RADEON_SCLK_DOWN
1281};
1282
1283struct radeon_blacklist_clocks
1284{
1285 u32 sclk;
1286 u32 mclk;
1287 enum radeon_clk_action action;
1288};
1289
61b7d601
AD		 1290struct radeon_clock_and_voltage_limits {
1291 u32 sclk;
1292 u32 mclk;
cdf6e805
AD		 1293 u16 vddc;
1294 u16 vddci;
61b7d601
AD		 1295};
1296
1297struct radeon_clock_array {
1298 u32 count;
1299 u32 *values;
1300};
1301
1302struct radeon_clock_voltage_dependency_entry {
1303 u32 clk;
1304 u16 v;
1305};
1306
1307struct radeon_clock_voltage_dependency_table {
1308 u32 count;
1309 struct radeon_clock_voltage_dependency_entry *entries;
1310};
1311
ef976ec4
AD		 1312union radeon_cac_leakage_entry {
1313 struct {
1314 u16 vddc;
1315 u32 leakage;
1316 };
1317 struct {
1318 u16 vddc1;
1319 u16 vddc2;
1320 u16 vddc3;
1321 };
61b7d601
AD		 1322};
1323
1324struct radeon_cac_leakage_table {
1325 u32 count;
ef976ec4 1326 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1327};
1328
929ee7a8
AD		 1329struct radeon_phase_shedding_limits_entry {
1330 u16 voltage;
1331 u32 sclk;
1332 u32 mclk;
1333};
1334
1335struct radeon_phase_shedding_limits_table {
1336 u32 count;
1337 struct radeon_phase_shedding_limits_entry *entries;
1338};
1339
84a9d9ee
AD		 1340struct radeon_uvd_clock_voltage_dependency_entry {
1341 u32 vclk;
1342 u32 dclk;
1343 u16 v;
1344};
1345
1346struct radeon_uvd_clock_voltage_dependency_table {
1347 u8 count;
1348 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1349};
1350
d29f013b
AD		 1351struct radeon_vce_clock_voltage_dependency_entry {
1352 u32 ecclk;
1353 u32 evclk;
1354 u16 v;
1355};
1356
1357struct radeon_vce_clock_voltage_dependency_table {
1358 u8 count;
1359 struct radeon_vce_clock_voltage_dependency_entry *entries;
1360};
1361
a5cb318e
AD		 1362struct radeon_ppm_table {
1363 u8 ppm_design;
1364 u16 cpu_core_number;
1365 u32 platform_tdp;
1366 u32 small_ac_platform_tdp;
1367 u32 platform_tdc;
1368 u32 small_ac_platform_tdc;
1369 u32 apu_tdp;
1370 u32 dgpu_tdp;
1371 u32 dgpu_ulv_power;
1372 u32 tj_max;
1373};
1374
58cb7632
AD		 1375struct radeon_cac_tdp_table {
1376 u16 tdp;
1377 u16 configurable_tdp;
1378 u16 tdc;
1379 u16 battery_power_limit;
1380 u16 small_power_limit;
1381 u16 low_cac_leakage;
1382 u16 high_cac_leakage;
1383 u16 maximum_power_delivery_limit;
1384};
1385
61b7d601
AD		 1386struct radeon_dpm_dynamic_state {
1387 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1388 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1389 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1390 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1391 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1392 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1393 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1394 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1395 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1396 struct radeon_clock_array valid_sclk_values;
1397 struct radeon_clock_array valid_mclk_values;
1398 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1399 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1400 u32 mclk_sclk_ratio;
1401 u32 sclk_mclk_delta;
1402 u16 vddc_vddci_delta;
1403 u16 min_vddc_for_pcie_gen2;
1404 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1405 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1406 struct radeon_ppm_table *ppm_table;
58cb7632 1407 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1408};
1409
1410struct radeon_dpm_fan {
1411 u16 t_min;
1412 u16 t_med;
1413 u16 t_high;
1414 u16 pwm_min;
1415 u16 pwm_med;
1416 u16 pwm_high;
1417 u8 t_hyst;
1418 u32 cycle_delay;
1419 u16 t_max;
1420 bool ucode_fan_control;
1421};
1422
32ce4652
AD		 1423enum radeon_pcie_gen {
1424 RADEON_PCIE_GEN1 = 0,
1425 RADEON_PCIE_GEN2 = 1,
1426 RADEON_PCIE_GEN3 = 2,
1427 RADEON_PCIE_GEN_INVALID = 0xffff
1428};
1429
70d01a5e
AD		 1430enum radeon_dpm_forced_level {
1431 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1432 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1433 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1434};
1435
da321c8a
AD		 1436struct radeon_dpm {
1437 struct radeon_ps *ps;
1438 /* number of valid power states */
1439 int num_ps;
1440 /* current power state that is active */
1441 struct radeon_ps *current_ps;
1442 /* requested power state */
1443 struct radeon_ps *requested_ps;
1444 /* boot up power state */
1445 struct radeon_ps *boot_ps;
1446 /* default uvd power state */
1447 struct radeon_ps *uvd_ps;
1448 enum radeon_pm_state_type state;
1449 enum radeon_pm_state_type user_state;
1450 u32 platform_caps;
1451 u32 voltage_response_time;
1452 u32 backbias_response_time;
1453 void *priv;
1454 u32 new_active_crtcs;
1455 int new_active_crtc_count;
1456 u32 current_active_crtcs;
1457 int current_active_crtc_count;
61b7d601
AD		 1458 struct radeon_dpm_dynamic_state dyn_state;
1459 struct radeon_dpm_fan fan;
1460 u32 tdp_limit;
1461 u32 near_tdp_limit;
a9e61410 1462 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1463 u32 sq_ramping_threshold;
1464 u32 cac_leakage;
1465 u16 tdp_od_limit;
1466 u32 tdp_adjustment;
1467 u16 load_line_slope;
1468 bool power_control;
5ca302f7 1469 bool ac_power;
da321c8a
AD		 1470 /* special states active */
1471 bool thermal_active;
8a227555 1472 bool uvd_active;
da321c8a
AD		 1473 /* thermal handling */
1474 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1475 /* forced levels */
1476 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1477 /* track UVD streams */
1478 unsigned sd;
1479 unsigned hd;
da321c8a
AD		 1480};
1481
ce3537d5 1482void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
da321c8a 1483
c93bb85b 1484struct radeon_pm {
c913e23a 1485 struct mutex mutex;
db7fce39
CK		 1486 /* write locked while reprogramming mclk */
1487 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1488 u32 active_crtcs;
1489 int active_crtc_count;
c913e23a 1490 int req_vblank;
839461d3 1491 bool vblank_sync;
c93bb85b
JG		 1492 fixed20_12 max_bandwidth;
1493 fixed20_12 igp_sideport_mclk;
1494 fixed20_12 igp_system_mclk;
1495 fixed20_12 igp_ht_link_clk;
1496 fixed20_12 igp_ht_link_width;
1497 fixed20_12 k8_bandwidth;
1498 fixed20_12 sideport_bandwidth;
1499 fixed20_12 ht_bandwidth;
1500 fixed20_12 core_bandwidth;
1501 fixed20_12 sclk;
f47299c5 1502 fixed20_12 mclk;
c93bb85b 1503 fixed20_12 needed_bandwidth;
0975b162 1504 struct radeon_power_state *power_state;
56278a8e
AD		 1505 /* number of valid power states */
1506 int num_power_states;
a48b9b4e
AD		 1507 int current_power_state_index;
1508 int current_clock_mode_index;
1509 int requested_power_state_index;
1510 int requested_clock_mode_index;
1511 int default_power_state_index;
1512 u32 current_sclk;
1513 u32 current_mclk;
2feea49a
AD		 1514 u16 current_vddc;
1515 u16 current_vddci;
9ace9f7b
AD		 1516 u32 default_sclk;
1517 u32 default_mclk;
2feea49a
AD		 1518 u16 default_vddc;
1519 u16 default_vddci;
29fb52ca 1520 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1521 /* selected pm method */
1522 enum radeon_pm_method pm_method;
1523 /* dynpm power management */
1524 struct delayed_work dynpm_idle_work;
1525 enum radeon_dynpm_state dynpm_state;
1526 enum radeon_dynpm_action dynpm_planned_action;
1527 unsigned long dynpm_action_timeout;
1528 bool dynpm_can_upclock;
1529 bool dynpm_can_downclock;
1530 /* profile-based power management */
1531 enum radeon_pm_profile_type profile;
1532 int profile_index;
1533 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1534 /* internal thermal controller on rv6xx+ */
1535 enum radeon_int_thermal_type int_thermal_type;
1536 struct device *int_hwmon_dev;
da321c8a
AD		 1537 /* dpm */
1538 bool dpm_enabled;
1539 struct radeon_dpm dpm;
c93bb85b
JG		 1540};
1541
a4c9e2ee
AD		 1542int radeon_pm_get_type_index(struct radeon_device *rdev,
1543 enum radeon_pm_state_type ps_type,
1544 int instance);
f2ba57b5
CK		 1545/*
1546 * UVD
1547 */
1548#define RADEON_MAX_UVD_HANDLES 10
1549#define RADEON_UVD_STACK_SIZE (1024*1024)
1550#define RADEON_UVD_HEAP_SIZE (1024*1024)
1551
1552struct radeon_uvd {
1553 struct radeon_bo *vcpu_bo;
1554 void *cpu_addr;
1555 uint64_t gpu_addr;
9cc2e0e9 1556 void *saved_bo;
f2ba57b5
CK		 1557 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1558 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1559 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1560 struct delayed_work idle_work;
f2ba57b5
CK		 1561};
1562
1563int radeon_uvd_init(struct radeon_device *rdev);
1564void radeon_uvd_fini(struct radeon_device *rdev);
1565int radeon_uvd_suspend(struct radeon_device *rdev);
1566int radeon_uvd_resume(struct radeon_device *rdev);
1567int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1568 uint32_t handle, struct radeon_fence **fence);
1569int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1570 uint32_t handle, struct radeon_fence **fence);
1571void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1572void radeon_uvd_free_handles(struct radeon_device *rdev,
1573 struct drm_file *filp);
1574int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1575void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1576int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1577 unsigned vclk, unsigned dclk,
1578 unsigned vco_min, unsigned vco_max,
1579 unsigned fb_factor, unsigned fb_mask,
1580 unsigned pd_min, unsigned pd_max,
1581 unsigned pd_even,
1582 unsigned *optimal_fb_div,
1583 unsigned *optimal_vclk_div,
1584 unsigned *optimal_dclk_div);
1585int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1586 unsigned cg_upll_func_cntl);
771fe6b9 1587
b530602f 1588struct r600_audio_pin {
a92553ab
RM		 1589 int channels;
1590 int rate;
1591 int bits_per_sample;
1592 u8 status_bits;
1593 u8 category_code;
b530602f
AD		 1594 u32 offset;
1595 bool connected;
1596 u32 id;
1597};
1598
1599struct r600_audio {
1600 bool enabled;
1601 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1602 int num_pins;
a92553ab
RM		 1603};
1604
771fe6b9
JG		 1605/*
1606 * Benchmarking
1607 */
638dd7db 1608void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1609
1610
ecc0b326
MD		 1611/*
1612 * Testing
1613 */
1614void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1615void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1616 struct radeon_ring *cpA,
1617 struct radeon_ring *cpB);
60a7e396 1618void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326
MD		 1619
1620
771fe6b9
JG		 1621/*
1622 * Debugfs
1623 */
4d8bf9ae
CK		 1624struct radeon_debugfs {
1625 struct drm_info_list *files;
1626 unsigned num_files;
1627};
1628
771fe6b9
JG		 1629int radeon_debugfs_add_files(struct radeon_device *rdev,
1630 struct drm_info_list *files,
1631 unsigned nfiles);
1632int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1633
76a0df85
CK		 1634/*
1635 * ASIC ring specific functions.
1636 */
1637struct radeon_asic_ring {
1638 /* ring read/write ptr handling */
1639 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1640 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1641 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1642
1643 /* validating and patching of IBs */
1644 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1645 int (*cs_parse)(struct radeon_cs_parser *p);
1646
1647 /* command emmit functions */
1648 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1649 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1654b817 1650 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
76a0df85
CK		 1651 struct radeon_semaphore *semaphore, bool emit_wait);
1652 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1653
1654 /* testing functions */
1655 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1656 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1657 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1658
1659 /* deprecated */
1660 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1661};
771fe6b9
JG		 1662
1663/*
1664 * ASIC specific functions.
1665 */
1666struct radeon_asic {
068a117c 1667 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1668 void (*fini)(struct radeon_device *rdev);
1669 int (*resume)(struct radeon_device *rdev);
1670 int (*suspend)(struct radeon_device *rdev);
28d52043 1671 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1672 int (*asic_reset)(struct radeon_device *rdev);
54e88e06
AD		 1673 /* ioctl hw specific callback. Some hw might want to perform special
1674 * operation on specific ioctl. For instance on wait idle some hw
1675 * might want to perform and HDP flush through MMIO as it seems that
1676 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1677 * through ring.
1678 */
1679 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1680 /* check if 3D engine is idle */
1681 bool (*gui_idle)(struct radeon_device *rdev);
1682 /* wait for mc_idle */
1683 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1684 /* get the reference clock */
1685 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1686 /* get the gpu clock counter */
1687 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1688 /* gart */
c5b3b850
AD		 1689 struct {
1690 void (*tlb_flush)(struct radeon_device *rdev);
1691 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1692 } gart;
05b07147
CK		 1693 struct {
1694 int (*init)(struct radeon_device *rdev);
1695 void (*fini)(struct radeon_device *rdev);
43f1214a
AD		 1696 void (*set_page)(struct radeon_device *rdev,
1697 struct radeon_ib *ib,
1698 uint64_t pe,
dce34bfd
CK		 1699 uint64_t addr, unsigned count,
1700 uint32_t incr, uint32_t flags);
05b07147 1701 } vm;
54e88e06 1702 /* ring specific callbacks */
76a0df85 1703 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1704 /* irqs */
b35ea4ab
AD		 1705 struct {
1706 int (*set)(struct radeon_device *rdev);
1707 int (*process)(struct radeon_device *rdev);
1708 } irq;
54e88e06 1709 /* displays */
c79a49ca
AD		 1710 struct {
1711 /* display watermarks */
1712 void (*bandwidth_update)(struct radeon_device *rdev);
1713 /* get frame count */
1714 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1715 /* wait for vblank */
1716 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1717 /* set backlight level */
1718 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1719 /* get backlight level */
1720 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1721 /* audio callbacks */
1722 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1723 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1724 } display;
54e88e06 1725 /* copy functions for bo handling */
27cd7769
AD		 1726 struct {
1727 int (*blit)(struct radeon_device *rdev,
1728 uint64_t src_offset,
1729 uint64_t dst_offset,
1730 unsigned num_gpu_pages,
876dc9f3 1731 struct radeon_fence **fence);
27cd7769
AD		 1732 u32 blit_ring_index;
1733 int (*dma)(struct radeon_device *rdev,
1734 uint64_t src_offset,
1735 uint64_t dst_offset,
1736 unsigned num_gpu_pages,
876dc9f3 1737 struct radeon_fence **fence);
27cd7769
AD		 1738 u32 dma_ring_index;
1739 /* method used for bo copy */
1740 int (*copy)(struct radeon_device *rdev,
1741 uint64_t src_offset,
1742 uint64_t dst_offset,
1743 unsigned num_gpu_pages,
876dc9f3 1744 struct radeon_fence **fence);
27cd7769
AD		 1745 /* ring used for bo copies */
1746 u32 copy_ring_index;
1747 } copy;
54e88e06 1748 /* surfaces */
9e6f3d02
AD		 1749 struct {
1750 int (*set_reg)(struct radeon_device *rdev, int reg,
1751 uint32_t tiling_flags, uint32_t pitch,
1752 uint32_t offset, uint32_t obj_size);
1753 void (*clear_reg)(struct radeon_device *rdev, int reg);
1754 } surface;
54e88e06 1755 /* hotplug detect */
901ea57d
AD		 1756 struct {
1757 void (*init)(struct radeon_device *rdev);
1758 void (*fini)(struct radeon_device *rdev);
1759 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1760 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1761 } hpd;
da321c8a 1762 /* static power management */
a02fa397
AD		 1763 struct {
1764 void (*misc)(struct radeon_device *rdev);
1765 void (*prepare)(struct radeon_device *rdev);
1766 void (*finish)(struct radeon_device *rdev);
1767 void (*init_profile)(struct radeon_device *rdev);
1768 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1769 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1770 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1771 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1772 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1773 int (*get_pcie_lanes)(struct radeon_device *rdev);
1774 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1775 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1776 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
6bd1c385 1777 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1778 } pm;
da321c8a
AD		 1779 /* dynamic power management */
1780 struct {
1781 int (*init)(struct radeon_device *rdev);
1782 void (*setup_asic)(struct radeon_device *rdev);
1783 int (*enable)(struct radeon_device *rdev);
914a8987 1784 int (*late_enable)(struct radeon_device *rdev);
da321c8a 1785 void (*disable)(struct radeon_device *rdev);
84dd1928 1786 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1787 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1788 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1789 void (*display_configuration_changed)(struct radeon_device *rdev);
1790 void (*fini)(struct radeon_device *rdev);
1791 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1792 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1793 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1794 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1795 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1796 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1797 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1c71bda0 1798 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
da321c8a 1799 } dpm;
6f34be50 1800 /* pageflipping */
0f9e006c
AD		 1801 struct {
1802 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1803 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1804 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1805 } pflip;
771fe6b9
JG		 1806};
1807
21f9a437
JG		 1808/*
1809 * Asic structures
1810 */
551ebd83 1811struct r100_asic {
225758d8
JG		 1812 const unsigned *reg_safe_bm;
1813 unsigned reg_safe_bm_size;
1814 u32 hdp_cntl;
551ebd83
DA		 1815};
1816
21f9a437 1817struct r300_asic {
225758d8
JG		 1818 const unsigned *reg_safe_bm;
1819 unsigned reg_safe_bm_size;
1820 u32 resync_scratch;
1821 u32 hdp_cntl;
21f9a437
JG		 1822};
1823
1824struct r600_asic {
225758d8
JG		 1825 unsigned max_pipes;
1826 unsigned max_tile_pipes;
1827 unsigned max_simds;
1828 unsigned max_backends;
1829 unsigned max_gprs;
1830 unsigned max_threads;
1831 unsigned max_stack_entries;
1832 unsigned max_hw_contexts;
1833 unsigned max_gs_threads;
1834 unsigned sx_max_export_size;
1835 unsigned sx_max_export_pos_size;
1836 unsigned sx_max_export_smx_size;
1837 unsigned sq_num_cf_insts;
1838 unsigned tiling_nbanks;
1839 unsigned tiling_npipes;
1840 unsigned tiling_group_size;
e7aeeba6 1841 unsigned tile_config;
e55b9422 1842 unsigned backend_map;
21f9a437
JG		 1843};
1844
1845struct rv770_asic {
225758d8
JG		 1846 unsigned max_pipes;
1847 unsigned max_tile_pipes;
1848 unsigned max_simds;
1849 unsigned max_backends;
1850 unsigned max_gprs;
1851 unsigned max_threads;
1852 unsigned max_stack_entries;
1853 unsigned max_hw_contexts;
1854 unsigned max_gs_threads;
1855 unsigned sx_max_export_size;
1856 unsigned sx_max_export_pos_size;
1857 unsigned sx_max_export_smx_size;
1858 unsigned sq_num_cf_insts;
1859 unsigned sx_num_of_sets;
1860 unsigned sc_prim_fifo_size;
1861 unsigned sc_hiz_tile_fifo_size;
1862 unsigned sc_earlyz_tile_fifo_fize;
1863 unsigned tiling_nbanks;
1864 unsigned tiling_npipes;
1865 unsigned tiling_group_size;
e7aeeba6 1866 unsigned tile_config;
e55b9422 1867 unsigned backend_map;
21f9a437
JG		 1868};
1869
32fcdbf4
AD		 1870struct evergreen_asic {
1871 unsigned num_ses;
1872 unsigned max_pipes;
1873 unsigned max_tile_pipes;
1874 unsigned max_simds;
1875 unsigned max_backends;
1876 unsigned max_gprs;
1877 unsigned max_threads;
1878 unsigned max_stack_entries;
1879 unsigned max_hw_contexts;
1880 unsigned max_gs_threads;
1881 unsigned sx_max_export_size;
1882 unsigned sx_max_export_pos_size;
1883 unsigned sx_max_export_smx_size;
1884 unsigned sq_num_cf_insts;
1885 unsigned sx_num_of_sets;
1886 unsigned sc_prim_fifo_size;
1887 unsigned sc_hiz_tile_fifo_size;
1888 unsigned sc_earlyz_tile_fifo_size;
1889 unsigned tiling_nbanks;
1890 unsigned tiling_npipes;
1891 unsigned tiling_group_size;
e7aeeba6 1892 unsigned tile_config;
e55b9422 1893 unsigned backend_map;
32fcdbf4
AD		 1894};
1895
fecf1d07
AD		 1896struct cayman_asic {
1897 unsigned max_shader_engines;
1898 unsigned max_pipes_per_simd;
1899 unsigned max_tile_pipes;
1900 unsigned max_simds_per_se;
1901 unsigned max_backends_per_se;
1902 unsigned max_texture_channel_caches;
1903 unsigned max_gprs;
1904 unsigned max_threads;
1905 unsigned max_gs_threads;
1906 unsigned max_stack_entries;
1907 unsigned sx_num_of_sets;
1908 unsigned sx_max_export_size;
1909 unsigned sx_max_export_pos_size;
1910 unsigned sx_max_export_smx_size;
1911 unsigned max_hw_contexts;
1912 unsigned sq_num_cf_insts;
1913 unsigned sc_prim_fifo_size;
1914 unsigned sc_hiz_tile_fifo_size;
1915 unsigned sc_earlyz_tile_fifo_size;
1916
1917 unsigned num_shader_engines;
1918 unsigned num_shader_pipes_per_simd;
1919 unsigned num_tile_pipes;
1920 unsigned num_simds_per_se;
1921 unsigned num_backends_per_se;
1922 unsigned backend_disable_mask_per_asic;
1923 unsigned backend_map;
1924 unsigned num_texture_channel_caches;
1925 unsigned mem_max_burst_length_bytes;
1926 unsigned mem_row_size_in_kb;
1927 unsigned shader_engine_tile_size;
1928 unsigned num_gpus;
1929 unsigned multi_gpu_tile_size;
1930
1931 unsigned tile_config;
fecf1d07
AD		 1932};
1933
0a96d72b
AD		 1934struct si_asic {
1935 unsigned max_shader_engines;
0a96d72b 1936 unsigned max_tile_pipes;
1a8ca750
AD		 1937 unsigned max_cu_per_sh;
1938 unsigned max_sh_per_se;
0a96d72b
AD		 1939 unsigned max_backends_per_se;
1940 unsigned max_texture_channel_caches;
1941 unsigned max_gprs;
1942 unsigned max_gs_threads;
1943 unsigned max_hw_contexts;
1944 unsigned sc_prim_fifo_size_frontend;
1945 unsigned sc_prim_fifo_size_backend;
1946 unsigned sc_hiz_tile_fifo_size;
1947 unsigned sc_earlyz_tile_fifo_size;
1948
0a96d72b
AD		 1949 unsigned num_tile_pipes;
1950 unsigned num_backends_per_se;
1951 unsigned backend_disable_mask_per_asic;
1952 unsigned backend_map;
1953 unsigned num_texture_channel_caches;
1954 unsigned mem_max_burst_length_bytes;
1955 unsigned mem_row_size_in_kb;
1956 unsigned shader_engine_tile_size;
1957 unsigned num_gpus;
1958 unsigned multi_gpu_tile_size;
1959
1960 unsigned tile_config;
64d7b8be 1961 uint32_t tile_mode_array[32];
0a96d72b
AD		 1962};
1963
8cc1a532
AD		 1964struct cik_asic {
1965 unsigned max_shader_engines;
1966 unsigned max_tile_pipes;
1967 unsigned max_cu_per_sh;
1968 unsigned max_sh_per_se;
1969 unsigned max_backends_per_se;
1970 unsigned max_texture_channel_caches;
1971 unsigned max_gprs;
1972 unsigned max_gs_threads;
1973 unsigned max_hw_contexts;
1974 unsigned sc_prim_fifo_size_frontend;
1975 unsigned sc_prim_fifo_size_backend;
1976 unsigned sc_hiz_tile_fifo_size;
1977 unsigned sc_earlyz_tile_fifo_size;
1978
1979 unsigned num_tile_pipes;
1980 unsigned num_backends_per_se;
1981 unsigned backend_disable_mask_per_asic;
1982 unsigned backend_map;
1983 unsigned num_texture_channel_caches;
1984 unsigned mem_max_burst_length_bytes;
1985 unsigned mem_row_size_in_kb;
1986 unsigned shader_engine_tile_size;
1987 unsigned num_gpus;
1988 unsigned multi_gpu_tile_size;
1989
1990 unsigned tile_config;
39aee490 1991 uint32_t tile_mode_array[32];
32f79a8a 1992 uint32_t macrotile_mode_array[16];
8cc1a532
AD		 1993};
1994
068a117c
JG		 1995union radeon_asic_config {
1996 struct r300_asic r300;
551ebd83 1997 struct r100_asic r100;
3ce0a23d
JG		 1998 struct r600_asic r600;
1999 struct rv770_asic rv770;
32fcdbf4 2000 struct evergreen_asic evergreen;
fecf1d07 2001 struct cayman_asic cayman;
0a96d72b 2002 struct si_asic si;
8cc1a532 2003 struct cik_asic cik;
068a117c
JG		 2004};
2005
0a10c851
DV		 2006/*
2007 * asic initizalization from radeon_asic.c
2008 */
2009void radeon_agp_disable(struct radeon_device *rdev);
2010int radeon_asic_init(struct radeon_device *rdev);
2011
771fe6b9
JG		 2012
2013/*
2014 * IOCTL.
2015 */
2016int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2017 struct drm_file *filp);
2018int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2019 struct drm_file *filp);
2020int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2021 struct drm_file *file_priv);
2022int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2023 struct drm_file *file_priv);
2024int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2025 struct drm_file *file_priv);
2026int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2027 struct drm_file *file_priv);
2028int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2029 struct drm_file *filp);
2030int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2031 struct drm_file *filp);
2032int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2033 struct drm_file *filp);
2034int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2035 struct drm_file *filp);
721604a1
JG		 2036int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2037 struct drm_file *filp);
771fe6b9 2038int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 2039int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2040 struct drm_file *filp);
2041int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2042 struct drm_file *filp);
771fe6b9 2043
16cdf04d
AD		 2044/* VRAM scratch page for HDP bug, default vram page */
2045struct r600_vram_scratch {
87cbf8f2
AD		 2046 struct radeon_bo *robj;
2047 volatile uint32_t *ptr;
16cdf04d 2048 u64 gpu_addr;
87cbf8f2 2049};
771fe6b9 2050
fd64ca8a
LT		 2051/*
2052 * ACPI
2053 */
2054struct radeon_atif_notification_cfg {
2055 bool enabled;
2056 int command_code;
2057};
2058
2059struct radeon_atif_notifications {
2060 bool display_switch;
2061 bool expansion_mode_change;
2062 bool thermal_state;
2063 bool forced_power_state;
2064 bool system_power_state;
2065 bool display_conf_change;
2066 bool px_gfx_switch;
2067 bool brightness_change;
2068 bool dgpu_display_event;
2069};
2070
2071struct radeon_atif_functions {
2072 bool system_params;
2073 bool sbios_requests;
2074 bool select_active_disp;
2075 bool lid_state;
2076 bool get_tv_standard;
2077 bool set_tv_standard;
2078 bool get_panel_expansion_mode;
2079 bool set_panel_expansion_mode;
2080 bool temperature_change;
2081 bool graphics_device_types;
2082};
2083
2084struct radeon_atif {
2085 struct radeon_atif_notifications notifications;
2086 struct radeon_atif_functions functions;
2087 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2088 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2089};
7a1619b9 2090
e3a15920
AD		 2091struct radeon_atcs_functions {
2092 bool get_ext_state;
2093 bool pcie_perf_req;
2094 bool pcie_dev_rdy;
2095 bool pcie_bus_width;
2096};
2097
2098struct radeon_atcs {
2099 struct radeon_atcs_functions functions;
2100};
2101
771fe6b9
JG		 2102/*
2103 * Core structure, functions and helpers.
2104 */
2105typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2106typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2107
2108struct radeon_device {
9f022ddf 2109 struct device *dev;
771fe6b9
JG		 2110 struct drm_device *ddev;
2111 struct pci_dev *pdev;
dee53e7f 2112 struct rw_semaphore exclusive_lock;
771fe6b9 2113 /* ASIC */
068a117c 2114 union radeon_asic_config config;
771fe6b9
JG		 2115 enum radeon_family family;
2116 unsigned long flags;
2117 int usec_timeout;
2118 enum radeon_pll_errata pll_errata;
2119 int num_gb_pipes;
f779b3e5 2120 int num_z_pipes;
771fe6b9
JG		 2121 int disp_priority;
2122 /* BIOS */
2123 uint8_t *bios;
2124 bool is_atom_bios;
2125 uint16_t bios_header_start;
4c788679 2126 struct radeon_bo *stollen_vga_memory;
771fe6b9 2127 /* Register mmio */
4c9bc75c
DA		 2128 resource_size_t rmmio_base;
2129 resource_size_t rmmio_size;
2c385151
DV		 2130 /* protects concurrent MM_INDEX/DATA based register access */
2131 spinlock_t mmio_idx_lock;
fe78118c
AD		 2132 /* protects concurrent SMC based register access */
2133 spinlock_t smc_idx_lock;
0a5b7b0b
AD		 2134 /* protects concurrent PLL register access */
2135 spinlock_t pll_idx_lock;
2136 /* protects concurrent MC register access */
2137 spinlock_t mc_idx_lock;
2138 /* protects concurrent PCIE register access */
2139 spinlock_t pcie_idx_lock;
2140 /* protects concurrent PCIE_PORT register access */
2141 spinlock_t pciep_idx_lock;
2142 /* protects concurrent PIF register access */
2143 spinlock_t pif_idx_lock;
2144 /* protects concurrent CG register access */
2145 spinlock_t cg_idx_lock;
2146 /* protects concurrent UVD register access */
2147 spinlock_t uvd_idx_lock;
2148 /* protects concurrent RCU register access */
2149 spinlock_t rcu_idx_lock;
2150 /* protects concurrent DIDT register access */
2151 spinlock_t didt_idx_lock;
2152 /* protects concurrent ENDPOINT (audio) register access */
2153 spinlock_t end_idx_lock;
a0533fbf 2154 void __iomem *rmmio;
771fe6b9
JG		 2155 radeon_rreg_t mc_rreg;
2156 radeon_wreg_t mc_wreg;
2157 radeon_rreg_t pll_rreg;
2158 radeon_wreg_t pll_wreg;
de1b2898 2159 uint32_t pcie_reg_mask;
771fe6b9
JG		 2160 radeon_rreg_t pciep_rreg;
2161 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2162 /* io port */
2163 void __iomem *rio_mem;
2164 resource_size_t rio_mem_size;
771fe6b9
JG		 2165 struct radeon_clock clock;
2166 struct radeon_mc mc;
2167 struct radeon_gart gart;
2168 struct radeon_mode_info mode_info;
2169 struct radeon_scratch scratch;
75efdee1 2170 struct radeon_doorbell doorbell;
771fe6b9 2171 struct radeon_mman mman;
7465280c 2172 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2173 wait_queue_head_t fence_queue;
d6999bc7 2174 struct mutex ring_lock;
e32eb50d 2175 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2176 bool ib_pool_ready;
2177 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2178 struct radeon_irq irq;
2179 struct radeon_asic *asic;
2180 struct radeon_gem gem;
c93bb85b 2181 struct radeon_pm pm;
f2ba57b5 2182 struct radeon_uvd uvd;
f657c2a7 2183 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2184 struct radeon_wb wb;
3ce0a23d 2185 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2186 bool shutdown;
2187 bool suspend;
ad49f501 2188 bool need_dma32;
733289c2 2189 bool accel_working;
a0a53aa8 2190 bool fastfb_working; /* IGP feature*/
f9eaf9ae 2191 bool needs_reset;
e024e110 2192 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2193 const struct firmware *me_fw; /* all family ME firmware */
2194 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2195 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2196 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2197 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2198 const struct firmware *mec_fw; /* CIK MEC firmware */
21a93e13 2199 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2200 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2201 const struct firmware *uvd_fw; /* UVD firmware */
16cdf04d 2202 struct r600_vram_scratch vram_scratch;
3e5cb98d 2203 int msi_enabled; /* msi enabled */
d8f60cfc 2204 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2205 struct radeon_rlc rlc;
963e81f9 2206 struct radeon_mec mec;
d4877cf2 2207 struct work_struct hotplug_work;
f122c610 2208 struct work_struct audio_work;
8f61b34c 2209 struct work_struct reset_work;
18917b60 2210 int num_crtc; /* number of crtcs */
40bacf16 2211 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
948bee3f 2212 bool has_uvd;
b530602f 2213 struct r600_audio audio; /* audio stuff */
ce8f5370 2214 struct notifier_block acpi_nb;
9eba4a93 2215 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2216 struct drm_file *hyperz_filp;
9eba4a93 2217 struct drm_file *cmask_filp;
f376b94f
AD		 2218 /* i2c buses */
2219 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2220 /* debugfs */
2221 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2222 unsigned debugfs_count;
721604a1
JG		 2223 /* virtual memory */
2224 struct radeon_vm_manager vm_manager;
6759a0a7 2225 struct mutex gpu_clock_mutex;
fd64ca8a
LT		 2226 /* ACPI interface */
2227 struct radeon_atif atif;
e3a15920 2228 struct radeon_atcs atcs;
f61d5b46
AD		 2229 /* srbm instance registers */
2230 struct mutex srbm_mutex;
64d8a728
AD		 2231 /* clock, powergating flags */
2232 u32 cg_flags;
2233 u32 pg_flags;
10ebc0bc
DA		 2234
2235 struct dev_pm_domain vga_pm_domain;
2236 bool have_disp_power_ref;
771fe6b9
JG		 2237};
2238
2239int radeon_device_init(struct radeon_device *rdev,
2240 struct drm_device *ddev,
2241 struct pci_dev *pdev,
2242 uint32_t flags);
2243void radeon_device_fini(struct radeon_device *rdev);
2244int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2245
2ef9bdfe
DV		 2246uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2247 bool always_indirect);
2248void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2249 bool always_indirect);
6fcbef7a
AK		 2250u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2251void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2252
d5754ab8
AL		 2253u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2254void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
75efdee1 2255
4c788679
JG		 2256/*
2257 * Cast helper
2258 */
2259#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 2260
2261/*
2262 * Registers read & write functions.
2263 */
a0533fbf
BH		 2264#define RREG8(reg) readb((rdev->rmmio) + (reg))
2265#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2266#define RREG16(reg) readw((rdev->rmmio) + (reg))
2267#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2268#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2269#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2270#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2271#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2272#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2273#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2274#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2275#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2276#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2277#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2278#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2279#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2280#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2281#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2282#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2283#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2284#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2285#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2286#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2287#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2288#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2289#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2290#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2291#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2292#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2293#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2294#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2295#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2296#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2297#define WREG32_P(reg, val, mask) \
2298 do { \
2299 uint32_t tmp_ = RREG32(reg); \
2300 tmp_ &= (mask); \
2301 tmp_ |= ((val) & ~(mask)); \
2302 WREG32(reg, tmp_); \
2303 } while (0)
d5169fc4 2304#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2305#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2306#define WREG32_PLL_P(reg, val, mask) \
2307 do { \
2308 uint32_t tmp_ = RREG32_PLL(reg); \
2309 tmp_ &= (mask); \
2310 tmp_ |= ((val) & ~(mask)); \
2311 WREG32_PLL(reg, tmp_); \
2312 } while (0)
2ef9bdfe 2313#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2314#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2315#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2316
d5754ab8
AL		 2317#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2318#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
75efdee1 2319
de1b2898
DA		 2320/*
2321 * Indirect registers accessor
2322 */
2323static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2324{
0a5b7b0b 2325 unsigned long flags;
de1b2898
DA		 2326 uint32_t r;
2327
0a5b7b0b 2328 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2329 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2330 r = RREG32(RADEON_PCIE_DATA);
0a5b7b0b 2331 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2332 return r;
2333}
2334
2335static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2336{
0a5b7b0b
AD		 2337 unsigned long flags;
2338
2339 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2340 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2341 WREG32(RADEON_PCIE_DATA, (v));
0a5b7b0b 2342 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2343}
2344
1d5d0c34
AD		 2345static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2346{
fe78118c 2347 unsigned long flags;
1d5d0c34
AD		 2348 u32 r;
2349
fe78118c 2350 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2351 WREG32(TN_SMC_IND_INDEX_0, (reg));
2352 r = RREG32(TN_SMC_IND_DATA_0);
fe78118c 2353 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2354 return r;
2355}
2356
2357static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2358{
fe78118c
AD		 2359 unsigned long flags;
2360
2361 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2362 WREG32(TN_SMC_IND_INDEX_0, (reg));
2363 WREG32(TN_SMC_IND_DATA_0, (v));
fe78118c 2364 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2365}
2366
ff82bbc4
AD		 2367static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2368{
0a5b7b0b 2369 unsigned long flags;
ff82bbc4
AD		 2370 u32 r;
2371
0a5b7b0b 2372 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2373 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2374 r = RREG32(R600_RCU_DATA);
0a5b7b0b 2375 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2376 return r;
2377}
2378
2379static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2380{
0a5b7b0b
AD		 2381 unsigned long flags;
2382
2383 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2384 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2385 WREG32(R600_RCU_DATA, (v));
0a5b7b0b 2386 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2387}
2388
46f9564a
AD		 2389static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2390{
0a5b7b0b 2391 unsigned long flags;
46f9564a
AD		 2392 u32 r;
2393
0a5b7b0b 2394 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2395 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2396 r = RREG32(EVERGREEN_CG_IND_DATA);
0a5b7b0b 2397 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2398 return r;
2399}
2400
2401static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2402{
0a5b7b0b
AD		 2403 unsigned long flags;
2404
2405 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2406 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2407 WREG32(EVERGREEN_CG_IND_DATA, (v));
0a5b7b0b 2408 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2409}
2410
792edd69
AD		 2411static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2412{
0a5b7b0b 2413 unsigned long flags;
792edd69
AD		 2414 u32 r;
2415
0a5b7b0b 2416 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2417 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2418 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
0a5b7b0b 2419 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2420 return r;
2421}
2422
2423static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2424{
0a5b7b0b
AD		 2425 unsigned long flags;
2426
2427 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2428 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2429 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
0a5b7b0b 2430 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2431}
2432
2433static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2434{
0a5b7b0b 2435 unsigned long flags;
792edd69
AD		 2436 u32 r;
2437
0a5b7b0b 2438 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2439 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2440 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
0a5b7b0b 2441 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2442 return r;
2443}
2444
2445static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2446{
0a5b7b0b
AD		 2447 unsigned long flags;
2448
2449 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2450 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2451 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
0a5b7b0b 2452 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2453}
2454
93656cdd
AD		 2455static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2456{
0a5b7b0b 2457 unsigned long flags;
93656cdd
AD		 2458 u32 r;
2459
0a5b7b0b 2460 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2461 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2462 r = RREG32(R600_UVD_CTX_DATA);
0a5b7b0b 2463 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2464 return r;
2465}
2466
2467static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2468{
0a5b7b0b
AD		 2469 unsigned long flags;
2470
2471 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2472 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2473 WREG32(R600_UVD_CTX_DATA, (v));
0a5b7b0b 2474 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2475}
2476
1d58234d
AD		 2477
2478static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2479{
0a5b7b0b 2480 unsigned long flags;
1d58234d
AD		 2481 u32 r;
2482
0a5b7b0b 2483 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2484 WREG32(CIK_DIDT_IND_INDEX, (reg));
2485 r = RREG32(CIK_DIDT_IND_DATA);
0a5b7b0b 2486 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2487 return r;
2488}
2489
2490static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2491{
0a5b7b0b
AD		 2492 unsigned long flags;
2493
2494 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2495 WREG32(CIK_DIDT_IND_INDEX, (reg));
2496 WREG32(CIK_DIDT_IND_DATA, (v));
0a5b7b0b 2497 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2498}
2499
771fe6b9
JG		 2500void r100_pll_errata_after_index(struct radeon_device *rdev);
2501
2502
2503/*
2504 * ASICs helpers.
2505 */
b995e433
DA		 2506#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2507 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2508#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2509 (rdev->family == CHIP_RV200) || \
2510 (rdev->family == CHIP_RS100) || \
2511 (rdev->family == CHIP_RS200) || \
2512 (rdev->family == CHIP_RV250) || \
2513 (rdev->family == CHIP_RV280) || \
2514 (rdev->family == CHIP_RS300))
2515#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2516 (rdev->family == CHIP_RV350) || \
2517 (rdev->family == CHIP_R350) || \
2518 (rdev->family == CHIP_RV380) || \
2519 (rdev->family == CHIP_R420) || \
2520 (rdev->family == CHIP_R423) || \
2521 (rdev->family == CHIP_RV410) || \
2522 (rdev->family == CHIP_RS400) || \
2523 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2524#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2525 (rdev->ddev->pdev->device == 0x9443) || \
2526 (rdev->ddev->pdev->device == 0x944B) || \
2527 (rdev->ddev->pdev->device == 0x9506) || \
2528 (rdev->ddev->pdev->device == 0x9509) || \
2529 (rdev->ddev->pdev->device == 0x950F) || \
2530 (rdev->ddev->pdev->device == 0x689C) || \
2531 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2532#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2533#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2534 (rdev->family == CHIP_RS690) || \
2535 (rdev->family == CHIP_RS740) || \
2536 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2537#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2538#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2539#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2540#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2541 (rdev->flags & RADEON_IS_IGP))
1fe18305 2542#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2543#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2544#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2545 (rdev->flags & RADEON_IS_IGP))
624d3524 2546#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2547#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2548#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
771fe6b9 2549
dc50ba7f
AD		 2550#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2551 (rdev->ddev->pdev->device == 0x6850) || \
2552 (rdev->ddev->pdev->device == 0x6858) || \
2553 (rdev->ddev->pdev->device == 0x6859) || \
2554 (rdev->ddev->pdev->device == 0x6840) || \
2555 (rdev->ddev->pdev->device == 0x6841) || \
2556 (rdev->ddev->pdev->device == 0x6842) || \
2557 (rdev->ddev->pdev->device == 0x6843))
2558
771fe6b9
JG		 2559/*
2560 * BIOS helpers.
2561 */
2562#define RBIOS8(i) (rdev->bios[i])
2563#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2564#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2565
2566int radeon_combios_init(struct radeon_device *rdev);
2567void radeon_combios_fini(struct radeon_device *rdev);
2568int radeon_atombios_init(struct radeon_device *rdev);
2569void radeon_atombios_fini(struct radeon_device *rdev);
2570
2571
2572/*
2573 * RING helpers.
2574 */
ce580fab 2575#if DRM_DEBUG_CODE == 0
e32eb50d 2576static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2577{
e32eb50d
CK		 2578 ring->ring[ring->wptr++] = v;
2579 ring->wptr &= ring->ptr_mask;
2580 ring->count_dw--;
2581 ring->ring_free_dw--;
771fe6b9 2582}
ce580fab
AK		 2583#else
2584/* With debugging this is just too big to inline */
e32eb50d 2585void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
ce580fab 2586#endif
771fe6b9
JG		 2587
2588/*
2589 * ASICs macro.
2590 */
068a117c 2591#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2592#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2593#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2594#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2595#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2596#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2597#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850
AD		 2598#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2599#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
05b07147
CK		 2600#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2601#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
43f1214a 2602#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
76a0df85
CK		 2603#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2604#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2605#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2606#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2607#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2608#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2609#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2610#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2611#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2612#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2613#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2614#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2615#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2616#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2617#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2618#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2619#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2620#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2621#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
27cd7769
AD		 2622#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2623#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2624#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2625#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2626#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2627#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2628#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2629#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2630#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2631#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2632#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2633#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2634#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2635#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
6bd1c385 2636#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2637#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2638#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2639#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2640#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2641#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2642#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2643#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2644#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2645#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2646#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2647#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2648#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2649#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8
AD		 2650#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2651#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2652#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2653#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2654#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2655#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2656#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2657#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2658#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2659#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
914a8987 2660#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
da321c8a 2661#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2662#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2663#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2664#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2665#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2666#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2667#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2668#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2669#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2670#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2671#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2672#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2673#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
1c71bda0 2674#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
771fe6b9 2675
6cf8a3f5 2676/* Common functions */
700a0cc0 2677/* AGP */
90aca4d2 2678extern int radeon_gpu_reset(struct radeon_device *rdev);
410a3418 2679extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2680extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2681extern int radeon_modeset_init(struct radeon_device *rdev);
2682extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2683extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2684extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2685extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2686extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2687extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2688extern void radeon_wb_fini(struct radeon_device *rdev);
2689extern int radeon_wb_init(struct radeon_device *rdev);
2690extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2691extern void radeon_surface_init(struct radeon_device *rdev);
2692extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2693extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2694extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2695extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2696extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 2697extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2698extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
10ebc0bc
DA		 2699extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2700extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
53595338 2701extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2702extern void radeon_program_register_sequence(struct radeon_device *rdev,
2703 const u32 *registers,
2704 const u32 array_size);
6cf8a3f5 2705
721604a1
JG		 2706/*
2707 * vm
2708 */
2709int radeon_vm_manager_init(struct radeon_device *rdev);
2710void radeon_vm_manager_fini(struct radeon_device *rdev);
d72d43cf 2711void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2712void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
ddf03f5c 2713int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
13e55c38 2714void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
ee60e29f
CK		 2715struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2716 struct radeon_vm *vm, int ring);
2717void radeon_vm_fence(struct radeon_device *rdev,
2718 struct radeon_vm *vm,
2719 struct radeon_fence *fence);
dce34bfd 2720uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
9c57a6bd
CK		 2721int radeon_vm_bo_update(struct radeon_device *rdev,
2722 struct radeon_vm *vm,
2723 struct radeon_bo *bo,
2724 struct ttm_mem_reg *mem);
721604a1
JG		 2725void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2726 struct radeon_bo *bo);
421ca7ab
CK		 2727struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2728 struct radeon_bo *bo);
e971bd5e
CK		 2729struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2730 struct radeon_vm *vm,
2731 struct radeon_bo *bo);
2732int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2733 struct radeon_bo_va *bo_va,
2734 uint64_t offset,
2735 uint32_t flags);
721604a1 2736int radeon_vm_bo_rmv(struct radeon_device *rdev,
e971bd5e 2737 struct radeon_bo_va *bo_va);
721604a1 2738
f122c610
AD		 2739/* audio */
2740void r600_audio_update_hdmi(struct work_struct *work);
b530602f
AD		 2741struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2742struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
721604a1 2743
16cdf04d
AD		 2744/*
2745 * R600 vram scratch functions
2746 */
2747int r600_vram_scratch_init(struct radeon_device *rdev);
2748void r600_vram_scratch_fini(struct radeon_device *rdev);
2749
285484e2
JG		 2750/*
2751 * r600 cs checking helper
2752 */
2753unsigned r600_mip_minify(unsigned size, unsigned level);
2754bool r600_fmt_is_valid_color(u32 format);
2755bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2756int r600_fmt_get_blocksize(u32 format);
2757int r600_fmt_get_nblocksx(u32 format, u32 w);
2758int r600_fmt_get_nblocksy(u32 format, u32 h);
2759
3574dda4
DV		 2760/*
2761 * r600 functions used by radeon_encoder.c
2762 */
1b688d08
RM		 2763struct radeon_hdmi_acr {
2764 u32 clock;
2765
2766 int n_32khz;
2767 int cts_32khz;
2768
2769 int n_44_1khz;
2770 int cts_44_1khz;
2771
2772 int n_48khz;
2773 int cts_48khz;
2774
2775};
2776
e55d3e6c
RM		 2777extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2778
416a2bd2
AD		 2779extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2780 u32 tiling_pipe_num,
2781 u32 max_rb_num,
2782 u32 total_max_rb_num,
2783 u32 enabled_rb_mask);
fe251e2f 2784
e55d3e6c
RM		 2785/*
2786 * evergreen functions used by radeon_encoder.c
2787 */
2788
0af62b01 2789extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2790extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2791
c4917074
AD		 2792/* radeon_acpi.c */
2793#if defined(CONFIG_ACPI)
2794extern int radeon_acpi_init(struct radeon_device *rdev);
2795extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2796extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2797extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2798 u8 perf_req, bool advertise);
dc50ba7f 2799extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2800#else
2801static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2802static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2803#endif
d7a2952f 2804
c38f34b5
IH		 2805int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2806 struct radeon_cs_packet *pkt,
2807 unsigned idx);
9ffb7a6d 2808bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2809void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2810 struct radeon_cs_packet *pkt);
e9716993
IH		 2811int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2812 struct radeon_cs_reloc **cs_reloc,
2813 int nomm);
40592a17
IH		 2814int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2815 uint32_t *vline_start_end,
2816 uint32_t *vline_status);
c38f34b5 2817
4c788679
JG		 2818#include "radeon_object.h"
2819
771fe6b9 2820#endif
Linux kernel - Deliverables
This page took 0.547551 seconds and 5 git commands to generate.