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drm/radeon/kms/r6xx+: add query for tile config (v2)
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
771fe6b9
JG		 63#include <asm/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
4c788679
JG		 68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
72
c2142715 73#include "radeon_family.h"
771fe6b9
JG		 74#include "radeon_mode.h"
75#include "radeon_reg.h"
771fe6b9
JG		 76
77/*
78 * Modules parameters.
79 */
80extern int radeon_no_wb;
81extern int radeon_modeset;
82extern int radeon_dynclks;
83extern int radeon_r4xx_atom;
84extern int radeon_agpmode;
85extern int radeon_vram_limit;
86extern int radeon_gart_size;
87extern int radeon_benchmarking;
ecc0b326 88extern int radeon_testing;
771fe6b9 89extern int radeon_connector_table;
4ce001ab 90extern int radeon_tv;
b27b6375 91extern int radeon_new_pll;
dafc3bd5 92extern int radeon_audio;
f46c0120 93extern int radeon_disp_priority;
e2b0a8e1 94extern int radeon_hw_i2c;
771fe6b9
JG		 95
96/*
97 * Copy from radeon_drv.h so we don't have to include both and have conflicting
98 * symbol;
99 */
100#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
225758d8 101#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 102/* RADEON_IB_POOL_SIZE must be a power of 2 */
771fe6b9
JG		 103#define RADEON_IB_POOL_SIZE 16
104#define RADEON_DEBUGFS_MAX_NUM_FILES 32
105#define RADEONFB_CONN_LIMIT 4
f657c2a7 106#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 107
771fe6b9
JG		 108/*
109 * Errata workarounds.
110 */
111enum radeon_pll_errata {
112 CHIP_ERRATA_R300_CG = 0x00000001,
113 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
114 CHIP_ERRATA_PLL_DELAY = 0x00000004
115};
116
117
118struct radeon_device;
119
120
121/*
122 * BIOS.
123 */
6a9ee8af
DA		 124#define ATRM_BIOS_PAGE 4096
125
8edb381d 126#if defined(CONFIG_VGA_SWITCHEROO)
6a9ee8af
DA		 127bool radeon_atrm_supported(struct pci_dev *pdev);
128int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
8edb381d
DA		 129#else
130static inline bool radeon_atrm_supported(struct pci_dev *pdev)
131{
132 return false;
133}
134
135static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
136 return -EINVAL;
137}
138#endif
771fe6b9
JG		 139bool radeon_get_bios(struct radeon_device *rdev);
140
3ce0a23d 141
771fe6b9 142/*
3ce0a23d 143 * Dummy page
771fe6b9 144 */
3ce0a23d
JG		 145struct radeon_dummy_page {
146 struct page *page;
147 dma_addr_t addr;
148};
149int radeon_dummy_page_init(struct radeon_device *rdev);
150void radeon_dummy_page_fini(struct radeon_device *rdev);
151
771fe6b9 152
3ce0a23d
JG		 153/*
154 * Clocks
155 */
771fe6b9
JG		 156struct radeon_clock {
157 struct radeon_pll p1pll;
158 struct radeon_pll p2pll;
bcc1c2a1 159 struct radeon_pll dcpll;
771fe6b9
JG		 160 struct radeon_pll spll;
161 struct radeon_pll mpll;
162 /* 10 Khz units */
163 uint32_t default_mclk;
164 uint32_t default_sclk;
bcc1c2a1
AD		 165 uint32_t default_dispclk;
166 uint32_t dp_extclk;
771fe6b9
JG		 167};
168
7433874e
RM		 169/*
170 * Power management
171 */
172int radeon_pm_init(struct radeon_device *rdev);
29fb52ca 173void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 174void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 175void radeon_pm_suspend(struct radeon_device *rdev);
176void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 177void radeon_combios_get_power_modes(struct radeon_device *rdev);
178void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7ac9aa5a 179void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level);
f892034a 180void rs690_pm_info(struct radeon_device *rdev);
21a8122a
AD		 181extern u32 rv6xx_get_temp(struct radeon_device *rdev);
182extern u32 rv770_get_temp(struct radeon_device *rdev);
183extern u32 evergreen_get_temp(struct radeon_device *rdev);
3ce0a23d 184
771fe6b9
JG		 185/*
186 * Fences.
187 */
188struct radeon_fence_driver {
189 uint32_t scratch_reg;
190 atomic_t seq;
191 uint32_t last_seq;
225758d8
JG		 192 unsigned long last_jiffies;
193 unsigned long last_timeout;
771fe6b9
JG		 194 wait_queue_head_t queue;
195 rwlock_t lock;
196 struct list_head created;
197 struct list_head emited;
198 struct list_head signaled;
0a0c7596 199 bool initialized;
771fe6b9
JG		 200};
201
202struct radeon_fence {
203 struct radeon_device *rdev;
204 struct kref kref;
205 struct list_head list;
206 /* protected by radeon_fence.lock */
207 uint32_t seq;
771fe6b9
JG		 208 bool emited;
209 bool signaled;
210};
211
212int radeon_fence_driver_init(struct radeon_device *rdev);
213void radeon_fence_driver_fini(struct radeon_device *rdev);
214int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
215int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
216void radeon_fence_process(struct radeon_device *rdev);
217bool radeon_fence_signaled(struct radeon_fence *fence);
218int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
219int radeon_fence_wait_next(struct radeon_device *rdev);
220int radeon_fence_wait_last(struct radeon_device *rdev);
221struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
222void radeon_fence_unref(struct radeon_fence **fence);
223
e024e110
DA		 224/*
225 * Tiling registers
226 */
227struct radeon_surface_reg {
4c788679 228 struct radeon_bo *bo;
e024e110
DA		 229};
230
231#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 232
233/*
4c788679 234 * TTM.
771fe6b9 235 */
4c788679
JG		 236struct radeon_mman {
237 struct ttm_bo_global_ref bo_global_ref;
238 struct ttm_global_reference mem_global_ref;
4c788679 239 struct ttm_bo_device bdev;
0a0c7596
JG		 240 bool mem_global_referenced;
241 bool initialized;
4c788679
JG		 242};
243
244struct radeon_bo {
245 /* Protected by gem.mutex */
246 struct list_head list;
247 /* Protected by tbo.reserved */
312ea8da
JG		 248 u32 placements[3];
249 struct ttm_placement placement;
4c788679
JG		 250 struct ttm_buffer_object tbo;
251 struct ttm_bo_kmap_obj kmap;
252 unsigned pin_count;
253 void *kptr;
254 u32 tiling_flags;
255 u32 pitch;
256 int surface_reg;
257 /* Constant after initialization */
258 struct radeon_device *rdev;
259 struct drm_gem_object *gobj;
260};
771fe6b9 261
4c788679 262struct radeon_bo_list {
771fe6b9 263 struct list_head list;
4c788679 264 struct radeon_bo *bo;
771fe6b9
JG		 265 uint64_t gpu_offset;
266 unsigned rdomain;
267 unsigned wdomain;
4c788679 268 u32 tiling_flags;
e8652753 269 bool reserved;
771fe6b9
JG		 270};
271
771fe6b9
JG		 272/*
273 * GEM objects.
274 */
275struct radeon_gem {
4c788679 276 struct mutex mutex;
771fe6b9
JG		 277 struct list_head objects;
278};
279
280int radeon_gem_init(struct radeon_device *rdev);
281void radeon_gem_fini(struct radeon_device *rdev);
282int radeon_gem_object_create(struct radeon_device *rdev, int size,
4c788679
JG		 283 int alignment, int initial_domain,
284 bool discardable, bool kernel,
285 struct drm_gem_object **obj);
771fe6b9
JG		 286int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
287 uint64_t *gpu_addr);
288void radeon_gem_object_unpin(struct drm_gem_object *obj);
289
290
291/*
292 * GART structures, functions & helpers
293 */
294struct radeon_mc;
295
296struct radeon_gart_table_ram {
297 volatile uint32_t *ptr;
298};
299
300struct radeon_gart_table_vram {
4c788679 301 struct radeon_bo *robj;
771fe6b9
JG		 302 volatile uint32_t *ptr;
303};
304
305union radeon_gart_table {
306 struct radeon_gart_table_ram ram;
307 struct radeon_gart_table_vram vram;
308};
309
a77f1718 310#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 311#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
a77f1718 312
771fe6b9
JG		 313struct radeon_gart {
314 dma_addr_t table_addr;
315 unsigned num_gpu_pages;
316 unsigned num_cpu_pages;
317 unsigned table_size;
318 union radeon_gart_table table;
319 struct page **pages;
320 dma_addr_t *pages_addr;
321 bool ready;
322};
323
324int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
325void radeon_gart_table_ram_free(struct radeon_device *rdev);
326int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
327void radeon_gart_table_vram_free(struct radeon_device *rdev);
328int radeon_gart_init(struct radeon_device *rdev);
329void radeon_gart_fini(struct radeon_device *rdev);
330void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
331 int pages);
332int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
333 int pages, struct page **pagelist);
334
335
336/*
337 * GPU MC structures, functions & helpers
338 */
339struct radeon_mc {
340 resource_size_t aper_size;
341 resource_size_t aper_base;
342 resource_size_t agp_base;
7a50f01a
DA		 343 /* for some chips with <= 32MB we need to lie
344 * about vram size near mc fb location */
3ce0a23d 345 u64 mc_vram_size;
d594e46a 346 u64 visible_vram_size;
3ce0a23d
JG		 347 u64 gtt_size;
348 u64 gtt_start;
349 u64 gtt_end;
3ce0a23d
JG		 350 u64 vram_start;
351 u64 vram_end;
771fe6b9 352 unsigned vram_width;
3ce0a23d 353 u64 real_vram_size;
771fe6b9
JG		 354 int vram_mtrr;
355 bool vram_is_ddr;
d594e46a 356 bool igp_sideport_enabled;
771fe6b9
JG		 357};
358
06b6476d
AD		 359bool radeon_combios_sideport_present(struct radeon_device *rdev);
360bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 361
362/*
363 * GPU scratch registers structures, functions & helpers
364 */
365struct radeon_scratch {
366 unsigned num_reg;
367 bool free[32];
368 uint32_t reg[32];
369};
370
371int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
372void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
373
374
375/*
376 * IRQS.
377 */
378struct radeon_irq {
379 bool installed;
380 bool sw_int;
381 /* FIXME: use a define max crtc rather than hardcode it */
45f9a39b 382 bool crtc_vblank_int[6];
73a6d3fc 383 wait_queue_head_t vblank_queue;
b500f680
AD		 384 /* FIXME: use defines for max hpd/dacs */
385 bool hpd[6];
2031f77c
AD		 386 bool gui_idle;
387 bool gui_idle_acked;
388 wait_queue_head_t idle_queue;
f2594933
CK		 389 /* FIXME: use defines for max HDMI blocks */
390 bool hdmi[2];
1614f8b1
DA		 391 spinlock_t sw_lock;
392 int sw_refcount;
771fe6b9
JG		 393};
394
395int radeon_irq_kms_init(struct radeon_device *rdev);
396void radeon_irq_kms_fini(struct radeon_device *rdev);
1614f8b1
DA		 397void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
398void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
771fe6b9
JG		 399
400/*
401 * CP & ring.
402 */
403struct radeon_ib {
404 struct list_head list;
e821767b 405 unsigned idx;
771fe6b9
JG		 406 uint64_t gpu_addr;
407 struct radeon_fence *fence;
e821767b 408 uint32_t *ptr;
771fe6b9 409 uint32_t length_dw;
e821767b 410 bool free;
771fe6b9
JG		 411};
412
ecb114a1
DA		 413/*
414 * locking -
415 * mutex protects scheduled_ibs, ready, alloc_bm
416 */
771fe6b9
JG		 417struct radeon_ib_pool {
418 struct mutex mutex;
4c788679 419 struct radeon_bo *robj;
9f93ed39 420 struct list_head bogus_ib;
771fe6b9
JG		 421 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
422 bool ready;
e821767b 423 unsigned head_id;
771fe6b9
JG		 424};
425
426struct radeon_cp {
4c788679 427 struct radeon_bo *ring_obj;
771fe6b9
JG		 428 volatile uint32_t *ring;
429 unsigned rptr;
430 unsigned wptr;
431 unsigned wptr_old;
432 unsigned ring_size;
433 unsigned ring_free_dw;
434 int count_dw;
435 uint64_t gpu_addr;
436 uint32_t align_mask;
437 uint32_t ptr_mask;
438 struct mutex mutex;
439 bool ready;
440};
441
d8f60cfc
AD		 442/*
443 * R6xx+ IH ring
444 */
445struct r600_ih {
4c788679 446 struct radeon_bo *ring_obj;
d8f60cfc
AD		 447 volatile uint32_t *ring;
448 unsigned rptr;
449 unsigned wptr;
450 unsigned wptr_old;
451 unsigned ring_size;
452 uint64_t gpu_addr;
d8f60cfc
AD		 453 uint32_t ptr_mask;
454 spinlock_t lock;
455 bool enabled;
456};
457
3ce0a23d 458struct r600_blit {
ff82f052 459 struct mutex mutex;
4c788679 460 struct radeon_bo *shader_obj;
3ce0a23d
JG		 461 u64 shader_gpu_addr;
462 u32 vs_offset, ps_offset;
463 u32 state_offset;
464 u32 state_len;
465 u32 vb_used, vb_total;
466 struct radeon_ib *vb_ib;
467};
468
771fe6b9
JG		 469int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
470void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
471int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
472int radeon_ib_pool_init(struct radeon_device *rdev);
473void radeon_ib_pool_fini(struct radeon_device *rdev);
474int radeon_ib_test(struct radeon_device *rdev);
9f93ed39 475extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
771fe6b9
JG		 476/* Ring access between begin & end cannot sleep */
477void radeon_ring_free_size(struct radeon_device *rdev);
91700f3c 478int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
771fe6b9 479int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
91700f3c 480void radeon_ring_commit(struct radeon_device *rdev);
771fe6b9
JG		 481void radeon_ring_unlock_commit(struct radeon_device *rdev);
482void radeon_ring_unlock_undo(struct radeon_device *rdev);
483int radeon_ring_test(struct radeon_device *rdev);
484int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
485void radeon_ring_fini(struct radeon_device *rdev);
486
487
488/*
489 * CS.
490 */
491struct radeon_cs_reloc {
492 struct drm_gem_object *gobj;
4c788679
JG		 493 struct radeon_bo *robj;
494 struct radeon_bo_list lobj;
771fe6b9
JG		 495 uint32_t handle;
496 uint32_t flags;
497};
498
499struct radeon_cs_chunk {
500 uint32_t chunk_id;
501 uint32_t length_dw;
513bcb46
DA		 502 int kpage_idx[2];
503 uint32_t *kpage[2];
771fe6b9 504 uint32_t *kdata;
513bcb46
DA		 505 void __user *user_ptr;
506 int last_copied_page;
507 int last_page_index;
771fe6b9
JG		 508};
509
510struct radeon_cs_parser {
c8c15ff1 511 struct device *dev;
771fe6b9
JG		 512 struct radeon_device *rdev;
513 struct drm_file *filp;
514 /* chunks */
515 unsigned nchunks;
516 struct radeon_cs_chunk *chunks;
517 uint64_t *chunks_array;
518 /* IB */
519 unsigned idx;
520 /* relocations */
521 unsigned nrelocs;
522 struct radeon_cs_reloc *relocs;
523 struct radeon_cs_reloc **relocs_ptr;
524 struct list_head validated;
525 /* indices of various chunks */
526 int chunk_ib_idx;
527 int chunk_relocs_idx;
528 struct radeon_ib *ib;
529 void *track;
3ce0a23d 530 unsigned family;
513bcb46 531 int parser_error;
771fe6b9
JG		 532};
533
513bcb46
DA		 534extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
535extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
536
537
538static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
539{
540 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
541 u32 pg_idx, pg_offset;
542 u32 idx_value = 0;
543 int new_page;
544
545 pg_idx = (idx * 4) / PAGE_SIZE;
546 pg_offset = (idx * 4) % PAGE_SIZE;
547
548 if (ibc->kpage_idx[0] == pg_idx)
549 return ibc->kpage[0][pg_offset/4];
550 if (ibc->kpage_idx[1] == pg_idx)
551 return ibc->kpage[1][pg_offset/4];
552
553 new_page = radeon_cs_update_pages(p, pg_idx);
554 if (new_page < 0) {
555 p->parser_error = new_page;
556 return 0;
557 }
558
559 idx_value = ibc->kpage[new_page][pg_offset/4];
560 return idx_value;
561}
562
771fe6b9
JG		 563struct radeon_cs_packet {
564 unsigned idx;
565 unsigned type;
566 unsigned reg;
567 unsigned opcode;
568 int count;
569 unsigned one_reg_wr;
570};
571
572typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
573 struct radeon_cs_packet *pkt,
574 unsigned idx, unsigned reg);
575typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
576 struct radeon_cs_packet *pkt);
577
578
579/*
580 * AGP
581 */
582int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 583void radeon_agp_resume(struct radeon_device *rdev);
10b06122 584void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 585void radeon_agp_fini(struct radeon_device *rdev);
586
587
588/*
589 * Writeback
590 */
591struct radeon_wb {
4c788679 592 struct radeon_bo *wb_obj;
771fe6b9
JG		 593 volatile uint32_t *wb;
594 uint64_t gpu_addr;
595};
596
c93bb85b
JG		 597/**
598 * struct radeon_pm - power management datas
599 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
600 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
601 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
602 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
603 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
604 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
605 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
606 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
607 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
608 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
609 * @needed_bandwidth: current bandwidth needs
610 *
611 * It keeps track of various data needed to take powermanagement decision.
612 * Bandwith need is used to determine minimun clock of the GPU and memory.
613 * Equation between gpu/memory clock and available bandwidth is hw dependent
614 * (type of memory, bus size, efficiency, ...)
615 */
ce8f5370
AD		 616
617enum radeon_pm_method {
618 PM_METHOD_PROFILE,
619 PM_METHOD_DYNPM,
620};
621
622enum radeon_dynpm_state {
623 DYNPM_STATE_DISABLED,
624 DYNPM_STATE_MINIMUM,
625 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 626 DYNPM_STATE_ACTIVE,
627 DYNPM_STATE_SUSPENDED,
c913e23a 628};
ce8f5370
AD		 629enum radeon_dynpm_action {
630 DYNPM_ACTION_NONE,
631 DYNPM_ACTION_MINIMUM,
632 DYNPM_ACTION_DOWNCLOCK,
633 DYNPM_ACTION_UPCLOCK,
634 DYNPM_ACTION_DEFAULT
c913e23a 635};
56278a8e
AD		 636
637enum radeon_voltage_type {
638 VOLTAGE_NONE = 0,
639 VOLTAGE_GPIO,
640 VOLTAGE_VDDC,
641 VOLTAGE_SW
642};
643
0ec0e74f
AD		 644enum radeon_pm_state_type {
645 POWER_STATE_TYPE_DEFAULT,
646 POWER_STATE_TYPE_POWERSAVE,
647 POWER_STATE_TYPE_BATTERY,
648 POWER_STATE_TYPE_BALANCED,
649 POWER_STATE_TYPE_PERFORMANCE,
650};
651
ce8f5370
AD		 652enum radeon_pm_profile_type {
653 PM_PROFILE_DEFAULT,
654 PM_PROFILE_AUTO,
655 PM_PROFILE_LOW,
c9e75b21 656 PM_PROFILE_MID,
ce8f5370
AD		 657 PM_PROFILE_HIGH,
658};
659
660#define PM_PROFILE_DEFAULT_IDX 0
661#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 662#define PM_PROFILE_MID_SH_IDX 2
663#define PM_PROFILE_HIGH_SH_IDX 3
664#define PM_PROFILE_LOW_MH_IDX 4
665#define PM_PROFILE_MID_MH_IDX 5
666#define PM_PROFILE_HIGH_MH_IDX 6
667#define PM_PROFILE_MAX 7
ce8f5370
AD		 668
669struct radeon_pm_profile {
670 int dpms_off_ps_idx;
671 int dpms_on_ps_idx;
672 int dpms_off_cm_idx;
673 int dpms_on_cm_idx;
516d0e46
AD		 674};
675
21a8122a
AD		 676enum radeon_int_thermal_type {
677 THERMAL_TYPE_NONE,
678 THERMAL_TYPE_RV6XX,
679 THERMAL_TYPE_RV770,
680 THERMAL_TYPE_EVERGREEN,
681};
682
56278a8e
AD		 683struct radeon_voltage {
684 enum radeon_voltage_type type;
685 /* gpio voltage */
686 struct radeon_gpio_rec gpio;
687 u32 delay; /* delay in usec from voltage drop to sclk change */
688 bool active_high; /* voltage drop is active when bit is high */
689 /* VDDC voltage */
690 u8 vddc_id; /* index into vddc voltage table */
691 u8 vddci_id; /* index into vddci voltage table */
692 bool vddci_enabled;
693 /* r6xx+ sw */
694 u32 voltage;
695};
696
d7311171
AD		 697/* clock mode flags */
698#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
699
56278a8e
AD		 700struct radeon_pm_clock_info {
701 /* memory clock */
702 u32 mclk;
703 /* engine clock */
704 u32 sclk;
705 /* voltage info */
706 struct radeon_voltage voltage;
d7311171 707 /* standardized clock flags */
56278a8e
AD		 708 u32 flags;
709};
710
a48b9b4e 711/* state flags */
d7311171 712#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 713
56278a8e 714struct radeon_power_state {
0ec0e74f 715 enum radeon_pm_state_type type;
56278a8e
AD		 716 /* XXX: use a define for num clock modes */
717 struct radeon_pm_clock_info clock_info[8];
718 /* number of valid clock modes in this power state */
719 int num_clock_modes;
56278a8e 720 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 721 /* standardized state flags */
722 u32 flags;
79daedc9
AD		 723 u32 misc; /* vbios specific flags */
724 u32 misc2; /* vbios specific flags */
725 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 726};
727
27459324
RM		 728/*
729 * Some modes are overclocked by very low value, accept them
730 */
731#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
732
c93bb85b 733struct radeon_pm {
c913e23a 734 struct mutex mutex;
a48b9b4e
AD		 735 u32 active_crtcs;
736 int active_crtc_count;
c913e23a 737 int req_vblank;
839461d3 738 bool vblank_sync;
2031f77c 739 bool gui_idle;
c93bb85b
JG		 740 fixed20_12 max_bandwidth;
741 fixed20_12 igp_sideport_mclk;
742 fixed20_12 igp_system_mclk;
743 fixed20_12 igp_ht_link_clk;
744 fixed20_12 igp_ht_link_width;
745 fixed20_12 k8_bandwidth;
746 fixed20_12 sideport_bandwidth;
747 fixed20_12 ht_bandwidth;
748 fixed20_12 core_bandwidth;
749 fixed20_12 sclk;
f47299c5 750 fixed20_12 mclk;
c93bb85b 751 fixed20_12 needed_bandwidth;
56278a8e
AD		 752 /* XXX: use a define for num power modes */
753 struct radeon_power_state power_state[8];
754 /* number of valid power states */
755 int num_power_states;
a48b9b4e
AD		 756 int current_power_state_index;
757 int current_clock_mode_index;
758 int requested_power_state_index;
759 int requested_clock_mode_index;
760 int default_power_state_index;
761 u32 current_sclk;
762 u32 current_mclk;
4d60173f 763 u32 current_vddc;
29fb52ca 764 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 765 /* selected pm method */
766 enum radeon_pm_method pm_method;
767 /* dynpm power management */
768 struct delayed_work dynpm_idle_work;
769 enum radeon_dynpm_state dynpm_state;
770 enum radeon_dynpm_action dynpm_planned_action;
771 unsigned long dynpm_action_timeout;
772 bool dynpm_can_upclock;
773 bool dynpm_can_downclock;
774 /* profile-based power management */
775 enum radeon_pm_profile_type profile;
776 int profile_index;
777 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 778 /* internal thermal controller on rv6xx+ */
779 enum radeon_int_thermal_type int_thermal_type;
780 struct device *int_hwmon_dev;
c93bb85b
JG		 781};
782
771fe6b9
JG		 783
784/*
785 * Benchmarking
786 */
787void radeon_benchmark(struct radeon_device *rdev);
788
789
ecc0b326
MD		 790/*
791 * Testing
792 */
793void radeon_test_moves(struct radeon_device *rdev);
794
795
771fe6b9
JG		 796/*
797 * Debugfs
798 */
799int radeon_debugfs_add_files(struct radeon_device *rdev,
800 struct drm_info_list *files,
801 unsigned nfiles);
802int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9
JG		 803
804
805/*
806 * ASIC specific functions.
807 */
808struct radeon_asic {
068a117c 809 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 810 void (*fini)(struct radeon_device *rdev);
811 int (*resume)(struct radeon_device *rdev);
812 int (*suspend)(struct radeon_device *rdev);
28d52043 813 void (*vga_set_state)(struct radeon_device *rdev, bool state);
225758d8 814 bool (*gpu_is_lockup)(struct radeon_device *rdev);
a2d07b74 815 int (*asic_reset)(struct radeon_device *rdev);
771fe6b9
JG		 816 void (*gart_tlb_flush)(struct radeon_device *rdev);
817 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
818 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
819 void (*cp_fini)(struct radeon_device *rdev);
820 void (*cp_disable)(struct radeon_device *rdev);
3ce0a23d 821 void (*cp_commit)(struct radeon_device *rdev);
771fe6b9 822 void (*ring_start)(struct radeon_device *rdev);
3ce0a23d
JG		 823 int (*ring_test)(struct radeon_device *rdev);
824 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
771fe6b9
JG		 825 int (*irq_set)(struct radeon_device *rdev);
826 int (*irq_process)(struct radeon_device *rdev);
7ed220d7 827 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 828 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
829 int (*cs_parse)(struct radeon_cs_parser *p);
830 int (*copy_blit)(struct radeon_device *rdev,
831 uint64_t src_offset,
832 uint64_t dst_offset,
833 unsigned num_pages,
834 struct radeon_fence *fence);
835 int (*copy_dma)(struct radeon_device *rdev,
836 uint64_t src_offset,
837 uint64_t dst_offset,
838 unsigned num_pages,
839 struct radeon_fence *fence);
840 int (*copy)(struct radeon_device *rdev,
841 uint64_t src_offset,
842 uint64_t dst_offset,
843 unsigned num_pages,
844 struct radeon_fence *fence);
7433874e 845 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
771fe6b9 846 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
7433874e 847 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
771fe6b9 848 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
c836a412 849 int (*get_pcie_lanes)(struct radeon_device *rdev);
771fe6b9
JG		 850 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
851 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
e024e110
DA		 852 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
853 uint32_t tiling_flags, uint32_t pitch,
854 uint32_t offset, uint32_t obj_size);
9479c54f 855 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
c93bb85b 856 void (*bandwidth_update)(struct radeon_device *rdev);
429770b3
AD		 857 void (*hpd_init)(struct radeon_device *rdev);
858 void (*hpd_fini)(struct radeon_device *rdev);
859 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
860 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
062b389c
JG		 861 /* ioctl hw specific callback. Some hw might want to perform special
862 * operation on specific ioctl. For instance on wait idle some hw
863 * might want to perform and HDP flush through MMIO as it seems that
864 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
865 * through ring.
866 */
867 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
def9ba9c 868 bool (*gui_idle)(struct radeon_device *rdev);
ce8f5370 869 /* power management */
49e02b73
AD		 870 void (*pm_misc)(struct radeon_device *rdev);
871 void (*pm_prepare)(struct radeon_device *rdev);
872 void (*pm_finish)(struct radeon_device *rdev);
ce8f5370
AD		 873 void (*pm_init_profile)(struct radeon_device *rdev);
874 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
771fe6b9
JG		 875};
876
21f9a437
JG		 877/*
878 * Asic structures
879 */
225758d8
JG		 880struct r100_gpu_lockup {
881 unsigned long last_jiffies;
882 u32 last_cp_rptr;
883};
884
551ebd83 885struct r100_asic {
225758d8
JG		 886 const unsigned *reg_safe_bm;
887 unsigned reg_safe_bm_size;
888 u32 hdp_cntl;
889 struct r100_gpu_lockup lockup;
551ebd83
DA		 890};
891
21f9a437 892struct r300_asic {
225758d8
JG		 893 const unsigned *reg_safe_bm;
894 unsigned reg_safe_bm_size;
895 u32 resync_scratch;
896 u32 hdp_cntl;
897 struct r100_gpu_lockup lockup;
21f9a437
JG		 898};
899
900struct r600_asic {
225758d8
JG		 901 unsigned max_pipes;
902 unsigned max_tile_pipes;
903 unsigned max_simds;
904 unsigned max_backends;
905 unsigned max_gprs;
906 unsigned max_threads;
907 unsigned max_stack_entries;
908 unsigned max_hw_contexts;
909 unsigned max_gs_threads;
910 unsigned sx_max_export_size;
911 unsigned sx_max_export_pos_size;
912 unsigned sx_max_export_smx_size;
913 unsigned sq_num_cf_insts;
914 unsigned tiling_nbanks;
915 unsigned tiling_npipes;
916 unsigned tiling_group_size;
e7aeeba6 917 unsigned tile_config;
225758d8 918 struct r100_gpu_lockup lockup;
21f9a437
JG		 919};
920
921struct rv770_asic {
225758d8
JG		 922 unsigned max_pipes;
923 unsigned max_tile_pipes;
924 unsigned max_simds;
925 unsigned max_backends;
926 unsigned max_gprs;
927 unsigned max_threads;
928 unsigned max_stack_entries;
929 unsigned max_hw_contexts;
930 unsigned max_gs_threads;
931 unsigned sx_max_export_size;
932 unsigned sx_max_export_pos_size;
933 unsigned sx_max_export_smx_size;
934 unsigned sq_num_cf_insts;
935 unsigned sx_num_of_sets;
936 unsigned sc_prim_fifo_size;
937 unsigned sc_hiz_tile_fifo_size;
938 unsigned sc_earlyz_tile_fifo_fize;
939 unsigned tiling_nbanks;
940 unsigned tiling_npipes;
941 unsigned tiling_group_size;
e7aeeba6 942 unsigned tile_config;
225758d8 943 struct r100_gpu_lockup lockup;
21f9a437
JG		 944};
945
32fcdbf4
AD		 946struct evergreen_asic {
947 unsigned num_ses;
948 unsigned max_pipes;
949 unsigned max_tile_pipes;
950 unsigned max_simds;
951 unsigned max_backends;
952 unsigned max_gprs;
953 unsigned max_threads;
954 unsigned max_stack_entries;
955 unsigned max_hw_contexts;
956 unsigned max_gs_threads;
957 unsigned sx_max_export_size;
958 unsigned sx_max_export_pos_size;
959 unsigned sx_max_export_smx_size;
960 unsigned sq_num_cf_insts;
961 unsigned sx_num_of_sets;
962 unsigned sc_prim_fifo_size;
963 unsigned sc_hiz_tile_fifo_size;
964 unsigned sc_earlyz_tile_fifo_size;
965 unsigned tiling_nbanks;
966 unsigned tiling_npipes;
967 unsigned tiling_group_size;
e7aeeba6 968 unsigned tile_config;
32fcdbf4
AD		 969};
970
068a117c
JG		 971union radeon_asic_config {
972 struct r300_asic r300;
551ebd83 973 struct r100_asic r100;
3ce0a23d
JG		 974 struct r600_asic r600;
975 struct rv770_asic rv770;
32fcdbf4 976 struct evergreen_asic evergreen;
068a117c
JG		 977};
978
0a10c851
DV		 979/*
980 * asic initizalization from radeon_asic.c
981 */
982void radeon_agp_disable(struct radeon_device *rdev);
983int radeon_asic_init(struct radeon_device *rdev);
984
771fe6b9
JG		 985
986/*
987 * IOCTL.
988 */
989int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
990 struct drm_file *filp);
991int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
992 struct drm_file *filp);
993int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
994 struct drm_file *file_priv);
995int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
996 struct drm_file *file_priv);
997int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
998 struct drm_file *file_priv);
999int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1000 struct drm_file *file_priv);
1001int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1002 struct drm_file *filp);
1003int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1004 struct drm_file *filp);
1005int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1006 struct drm_file *filp);
1007int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1008 struct drm_file *filp);
1009int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 1010int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1011 struct drm_file *filp);
1012int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1013 struct drm_file *filp);
771fe6b9
JG		 1014
1015
1016/*
1017 * Core structure, functions and helpers.
1018 */
1019typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1020typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1021
1022struct radeon_device {
9f022ddf 1023 struct device *dev;
771fe6b9
JG		 1024 struct drm_device *ddev;
1025 struct pci_dev *pdev;
1026 /* ASIC */
068a117c 1027 union radeon_asic_config config;
771fe6b9
JG		 1028 enum radeon_family family;
1029 unsigned long flags;
1030 int usec_timeout;
1031 enum radeon_pll_errata pll_errata;
1032 int num_gb_pipes;
f779b3e5 1033 int num_z_pipes;
771fe6b9
JG		 1034 int disp_priority;
1035 /* BIOS */
1036 uint8_t *bios;
1037 bool is_atom_bios;
1038 uint16_t bios_header_start;
4c788679 1039 struct radeon_bo *stollen_vga_memory;
771fe6b9 1040 /* Register mmio */
4c9bc75c
DA		 1041 resource_size_t rmmio_base;
1042 resource_size_t rmmio_size;
771fe6b9 1043 void *rmmio;
771fe6b9
JG		 1044 radeon_rreg_t mc_rreg;
1045 radeon_wreg_t mc_wreg;
1046 radeon_rreg_t pll_rreg;
1047 radeon_wreg_t pll_wreg;
de1b2898 1048 uint32_t pcie_reg_mask;
771fe6b9
JG		 1049 radeon_rreg_t pciep_rreg;
1050 radeon_wreg_t pciep_wreg;
1051 struct radeon_clock clock;
1052 struct radeon_mc mc;
1053 struct radeon_gart gart;
1054 struct radeon_mode_info mode_info;
1055 struct radeon_scratch scratch;
1056 struct radeon_mman mman;
1057 struct radeon_fence_driver fence_drv;
1058 struct radeon_cp cp;
1059 struct radeon_ib_pool ib_pool;
1060 struct radeon_irq irq;
1061 struct radeon_asic *asic;
1062 struct radeon_gem gem;
c93bb85b 1063 struct radeon_pm pm;
f657c2a7 1064 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9
JG		 1065 struct mutex cs_mutex;
1066 struct radeon_wb wb;
3ce0a23d 1067 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 1068 bool gpu_lockup;
1069 bool shutdown;
1070 bool suspend;
ad49f501 1071 bool need_dma32;
733289c2 1072 bool accel_working;
e024e110 1073 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 1074 const struct firmware *me_fw; /* all family ME firmware */
1075 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 1076 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
3ce0a23d 1077 struct r600_blit r600_blit;
3e5cb98d 1078 int msi_enabled; /* msi enabled */
d8f60cfc 1079 struct r600_ih ih; /* r6/700 interrupt ring */
d4877cf2
AD		 1080 struct workqueue_struct *wq;
1081 struct work_struct hotplug_work;
18917b60 1082 int num_crtc; /* number of crtcs */
40bacf16 1083 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
5876dd24 1084 struct mutex vram_mutex;
dafc3bd5
CK		 1085
1086 /* audio stuff */
1087 struct timer_list audio_timer;
1088 int audio_channels;
1089 int audio_rate;
1090 int audio_bits_per_sample;
1091 uint8_t audio_status_bits;
1092 uint8_t audio_category_code;
6a9ee8af
DA		 1093
1094 bool powered_down;
ce8f5370 1095 struct notifier_block acpi_nb;
771fe6b9
JG		 1096};
1097
1098int radeon_device_init(struct radeon_device *rdev,
1099 struct drm_device *ddev,
1100 struct pci_dev *pdev,
1101 uint32_t flags);
1102void radeon_device_fini(struct radeon_device *rdev);
1103int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1104
3ce0a23d
JG		 1105/* r600 blit */
1106int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
1107void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
1108void r600_kms_blit_copy(struct radeon_device *rdev,
1109 u64 src_gpu_addr, u64 dst_gpu_addr,
1110 int size_bytes);
1111
de1b2898
DA		 1112static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1113{
07bec2df 1114 if (reg < rdev->rmmio_size)
de1b2898
DA		 1115 return readl(((void __iomem *)rdev->rmmio) + reg);
1116 else {
1117 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1118 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1119 }
1120}
1121
1122static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1123{
07bec2df 1124 if (reg < rdev->rmmio_size)
de1b2898
DA		 1125 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1126 else {
1127 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1128 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1129 }
1130}
1131
4c788679
JG		 1132/*
1133 * Cast helper
1134 */
1135#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 1136
1137/*
1138 * Registers read & write functions.
1139 */
1140#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
1141#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
de1b2898 1142#define RREG32(reg) r100_mm_rreg(rdev, (reg))
3ce0a23d 1143#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
de1b2898 1144#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
771fe6b9
JG		 1145#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1146#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1147#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1148#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1149#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1150#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 1151#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1152#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
aa5120d2
RM		 1153#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1154#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
771fe6b9
JG		 1155#define WREG32_P(reg, val, mask) \
1156 do { \
1157 uint32_t tmp_ = RREG32(reg); \
1158 tmp_ &= (mask); \
1159 tmp_ |= ((val) & ~(mask)); \
1160 WREG32(reg, tmp_); \
1161 } while (0)
1162#define WREG32_PLL_P(reg, val, mask) \
1163 do { \
1164 uint32_t tmp_ = RREG32_PLL(reg); \
1165 tmp_ &= (mask); \
1166 tmp_ |= ((val) & ~(mask)); \
1167 WREG32_PLL(reg, tmp_); \
1168 } while (0)
3ce0a23d 1169#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
771fe6b9 1170
de1b2898
DA		 1171/*
1172 * Indirect registers accessor
1173 */
1174static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1175{
1176 uint32_t r;
1177
1178 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1179 r = RREG32(RADEON_PCIE_DATA);
1180 return r;
1181}
1182
1183static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1184{
1185 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1186 WREG32(RADEON_PCIE_DATA, (v));
1187}
1188
771fe6b9
JG		 1189void r100_pll_errata_after_index(struct radeon_device *rdev);
1190
1191
1192/*
1193 * ASICs helpers.
1194 */
b995e433
DA		 1195#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1196 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 1197#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1198 (rdev->family == CHIP_RV200) || \
1199 (rdev->family == CHIP_RS100) || \
1200 (rdev->family == CHIP_RS200) || \
1201 (rdev->family == CHIP_RV250) || \
1202 (rdev->family == CHIP_RV280) || \
1203 (rdev->family == CHIP_RS300))
1204#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1205 (rdev->family == CHIP_RV350) || \
1206 (rdev->family == CHIP_R350) || \
1207 (rdev->family == CHIP_RV380) || \
1208 (rdev->family == CHIP_R420) || \
1209 (rdev->family == CHIP_R423) || \
1210 (rdev->family == CHIP_RV410) || \
1211 (rdev->family == CHIP_RS400) || \
1212 (rdev->family == CHIP_RS480))
1213#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1214#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1215#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 1216#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
771fe6b9
JG		 1217
1218/*
1219 * BIOS helpers.
1220 */
1221#define RBIOS8(i) (rdev->bios[i])
1222#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1223#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1224
1225int radeon_combios_init(struct radeon_device *rdev);
1226void radeon_combios_fini(struct radeon_device *rdev);
1227int radeon_atombios_init(struct radeon_device *rdev);
1228void radeon_atombios_fini(struct radeon_device *rdev);
1229
1230
1231/*
1232 * RING helpers.
1233 */
771fe6b9
JG		 1234static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1235{
1236#if DRM_DEBUG_CODE
1237 if (rdev->cp.count_dw <= 0) {
1238 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1239 }
1240#endif
1241 rdev->cp.ring[rdev->cp.wptr++] = v;
1242 rdev->cp.wptr &= rdev->cp.ptr_mask;
1243 rdev->cp.count_dw--;
1244 rdev->cp.ring_free_dw--;
1245}
1246
1247
1248/*
1249 * ASICs macro.
1250 */
068a117c 1251#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 1252#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1253#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1254#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
771fe6b9 1255#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
28d52043 1256#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
225758d8 1257#define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
a2d07b74 1258#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
771fe6b9
JG		 1259#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1260#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
3ce0a23d 1261#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
771fe6b9 1262#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
3ce0a23d
JG		 1263#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1264#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
771fe6b9
JG		 1265#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1266#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
7ed220d7 1267#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
771fe6b9
JG		 1268#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1269#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1270#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1271#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
7433874e 1272#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
771fe6b9 1273#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
7433874e 1274#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
93e7de7b 1275#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
c836a412 1276#define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
771fe6b9
JG		 1277#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1278#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
e024e110
DA		 1279#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1280#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
c93bb85b 1281#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
429770b3
AD		 1282#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1283#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1284#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1285#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
def9ba9c 1286#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a424816f
AD		 1287#define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1288#define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1289#define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
ce8f5370
AD		 1290#define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1291#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
771fe6b9 1292
6cf8a3f5 1293/* Common functions */
700a0cc0 1294/* AGP */
90aca4d2 1295extern int radeon_gpu_reset(struct radeon_device *rdev);
700a0cc0 1296extern void radeon_agp_disable(struct radeon_device *rdev);
4aac0473 1297extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
82568565 1298extern void radeon_gart_restore(struct radeon_device *rdev);
21f9a437
JG		 1299extern int radeon_modeset_init(struct radeon_device *rdev);
1300extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 1301extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 1302extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 1303extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 1304extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437
JG		 1305extern int radeon_clocks_init(struct radeon_device *rdev);
1306extern void radeon_clocks_fini(struct radeon_device *rdev);
1307extern void radeon_scratch_init(struct radeon_device *rdev);
1308extern void radeon_surface_init(struct radeon_device *rdev);
1309extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 1310extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 1311extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 1312extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 1313extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
d594e46a
JG		 1314extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1315extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
6a9ee8af
DA		 1316extern int radeon_resume_kms(struct drm_device *dev);
1317extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
6cf8a3f5 1318
a18d7ea1 1319/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
225758d8
JG		 1320extern void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
1321extern bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
9f022ddf 1322
d4550907
JG		 1323/* rv200,rv250,rv280 */
1324extern void r200_set_safe_registers(struct radeon_device *rdev);
9f022ddf
JG		 1325
1326/* r300,r350,rv350,rv370,rv380 */
1327extern void r300_set_reg_safe(struct radeon_device *rdev);
1328extern void r300_mc_program(struct radeon_device *rdev);
d594e46a 1329extern void r300_mc_init(struct radeon_device *rdev);
ca6ffc64
JG		 1330extern void r300_clock_startup(struct radeon_device *rdev);
1331extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
4aac0473
JG		 1332extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1333extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1334extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
9f022ddf 1335extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
a18d7ea1 1336
905b6822 1337/* r420,r423,rv410 */
21f9a437
JG		 1338extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1339extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
9f022ddf 1340extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
d39c3b89 1341extern void r420_pipes_init(struct radeon_device *rdev);
905b6822 1342
21f9a437 1343/* rv515 */
d39c3b89
JG		 1344struct rv515_mc_save {
1345 u32 d1vga_control;
1346 u32 d2vga_control;
1347 u32 vga_render_control;
1348 u32 vga_hdp_control;
1349 u32 d1crtc_control;
1350 u32 d2crtc_control;
1351};
21f9a437 1352extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
d39c3b89
JG		 1353extern void rv515_vga_render_disable(struct radeon_device *rdev);
1354extern void rv515_set_safe_registers(struct radeon_device *rdev);
f0ed1f65
JG		 1355extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1356extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1357extern void rv515_clock_startup(struct radeon_device *rdev);
1358extern void rv515_debugfs(struct radeon_device *rdev);
1359extern int rv515_suspend(struct radeon_device *rdev);
21f9a437 1360
3bc68535
JG		 1361/* rs400 */
1362extern int rs400_gart_init(struct radeon_device *rdev);
1363extern int rs400_gart_enable(struct radeon_device *rdev);
1364extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1365extern void rs400_gart_disable(struct radeon_device *rdev);
1366extern void rs400_gart_fini(struct radeon_device *rdev);
1367
1368/* rs600 */
1369extern void rs600_set_safe_registers(struct radeon_device *rdev);
ac447df4
JG		 1370extern int rs600_irq_set(struct radeon_device *rdev);
1371extern void rs600_irq_disable(struct radeon_device *rdev);
3bc68535 1372
21f9a437
JG		 1373/* rs690, rs740 */
1374extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1375 struct drm_display_mode *mode1,
1376 struct drm_display_mode *mode2);
1377
1378/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
d594e46a 1379extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
21f9a437
JG		 1380extern bool r600_card_posted(struct radeon_device *rdev);
1381extern void r600_cp_stop(struct radeon_device *rdev);
fe251e2f 1382extern int r600_cp_start(struct radeon_device *rdev);
21f9a437
JG		 1383extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1384extern int r600_cp_resume(struct radeon_device *rdev);
655efd3d 1385extern void r600_cp_fini(struct radeon_device *rdev);
21f9a437 1386extern int r600_count_pipe_bits(uint32_t val);
21f9a437 1387extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
4aac0473 1388extern int r600_pcie_gart_init(struct radeon_device *rdev);
21f9a437
JG		 1389extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1390extern int r600_ib_test(struct radeon_device *rdev);
1391extern int r600_ring_test(struct radeon_device *rdev);
21f9a437 1392extern void r600_wb_fini(struct radeon_device *rdev);
81cc35bf
JG		 1393extern int r600_wb_enable(struct radeon_device *rdev);
1394extern void r600_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 1395extern void r600_scratch_init(struct radeon_device *rdev);
1396extern int r600_blit_init(struct radeon_device *rdev);
1397extern void r600_blit_fini(struct radeon_device *rdev);
d8f60cfc 1398extern int r600_init_microcode(struct radeon_device *rdev);
a2d07b74 1399extern int r600_asic_reset(struct radeon_device *rdev);
d8f60cfc
AD		 1400/* r600 irq */
1401extern int r600_irq_init(struct radeon_device *rdev);
1402extern void r600_irq_fini(struct radeon_device *rdev);
1403extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1404extern int r600_irq_set(struct radeon_device *rdev);
0c45249f 1405extern void r600_irq_suspend(struct radeon_device *rdev);
45f9a39b
AD		 1406extern void r600_disable_interrupts(struct radeon_device *rdev);
1407extern void r600_rlc_stop(struct radeon_device *rdev);
0c45249f 1408/* r600 audio */
dafc3bd5
CK		 1409extern int r600_audio_init(struct radeon_device *rdev);
1410extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1411extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
58bd0863
CK		 1412extern int r600_audio_channels(struct radeon_device *rdev);
1413extern int r600_audio_bits_per_sample(struct radeon_device *rdev);
1414extern int r600_audio_rate(struct radeon_device *rdev);
1415extern uint8_t r600_audio_status_bits(struct radeon_device *rdev);
1416extern uint8_t r600_audio_category_code(struct radeon_device *rdev);
f2594933 1417extern void r600_audio_schedule_polling(struct radeon_device *rdev);
58bd0863
CK		 1418extern void r600_audio_enable_polling(struct drm_encoder *encoder);
1419extern void r600_audio_disable_polling(struct drm_encoder *encoder);
dafc3bd5
CK		 1420extern void r600_audio_fini(struct radeon_device *rdev);
1421extern void r600_hdmi_init(struct drm_encoder *encoder);
2cd6218c
RM		 1422extern void r600_hdmi_enable(struct drm_encoder *encoder);
1423extern void r600_hdmi_disable(struct drm_encoder *encoder);
dafc3bd5
CK		 1424extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1425extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
58bd0863 1426extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
dafc3bd5 1427
fe251e2f
AD		 1428extern void r700_cp_stop(struct radeon_device *rdev);
1429extern void r700_cp_fini(struct radeon_device *rdev);
0ca2ab52
AD		 1430extern void evergreen_disable_interrupt_state(struct radeon_device *rdev);
1431extern int evergreen_irq_set(struct radeon_device *rdev);
fe251e2f 1432
d7a2952f
AM		 1433/* radeon_acpi.c */
1434#if defined(CONFIG_ACPI)
1435extern int radeon_acpi_init(struct radeon_device *rdev);
1436#else
1437static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1438#endif
1439
bcc1c2a1
AD		 1440/* evergreen */
1441struct evergreen_mc_save {
1442 u32 vga_control[6];
1443 u32 vga_render_control;
1444 u32 vga_hdp_control;
1445 u32 crtc_control[6];
1446};
1447
4c788679
JG		 1448#include "radeon_object.h"
1449
771fe6b9 1450#endif
Linux kernel - Deliverables
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