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drm/radeon: wake up all fences on manual reset
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
0aea5e4a 67#include <linux/interval_tree.h>
341cb9e4 68#include <linux/hashtable.h>
771fe6b9 69
4c788679
JG		 70#include <ttm/ttm_bo_api.h>
71#include <ttm/ttm_bo_driver.h>
72#include <ttm/ttm_placement.h>
73#include <ttm/ttm_module.h>
147666fb 74#include <ttm/ttm_execbuf_util.h>
4c788679 75
c2142715 76#include "radeon_family.h"
771fe6b9
JG		 77#include "radeon_mode.h"
78#include "radeon_reg.h"
771fe6b9
JG		 79
80/*
81 * Modules parameters.
82 */
83extern int radeon_no_wb;
84extern int radeon_modeset;
85extern int radeon_dynclks;
86extern int radeon_r4xx_atom;
87extern int radeon_agpmode;
88extern int radeon_vram_limit;
89extern int radeon_gart_size;
90extern int radeon_benchmarking;
ecc0b326 91extern int radeon_testing;
771fe6b9 92extern int radeon_connector_table;
4ce001ab 93extern int radeon_tv;
dafc3bd5 94extern int radeon_audio;
f46c0120 95extern int radeon_disp_priority;
e2b0a8e1 96extern int radeon_hw_i2c;
d42dd579 97extern int radeon_pcie_gen2;
a18cee15 98extern int radeon_msi;
3368ff0c 99extern int radeon_lockup_timeout;
a0a53aa8 100extern int radeon_fastfb;
da321c8a 101extern int radeon_dpm;
1294d4a3 102extern int radeon_aspm;
10ebc0bc 103extern int radeon_runtime_pm;
363eb0b4 104extern int radeon_hard_reset;
c1c44132 105extern int radeon_vm_size;
4510fb98 106extern int radeon_vm_block_size;
a624f429 107extern int radeon_deep_color;
39dc5454 108extern int radeon_use_pflipirq;
6e909f74 109extern int radeon_bapm;
771fe6b9
JG		 110
111/*
112 * Copy from radeon_drv.h so we don't have to include both and have conflicting
113 * symbol;
114 */
bb635567
JG		 115#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
116#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
e821767b 117/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 118#define RADEON_IB_POOL_SIZE 16
119#define RADEON_DEBUGFS_MAX_COMPONENTS 32
120#define RADEONFB_CONN_LIMIT 4
121#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 122
bb635567
JG		 123/* fence seq are set to this number when signaled */
124#define RADEON_FENCE_SIGNALED_SEQ 0LL
1b37078b
AD		 125
126/* internal ring indices */
127/* r1xx+ has gfx CP ring */
d93f7937 128#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 129
130/* cayman has 2 compute CP rings */
d93f7937
CK		 131#define CAYMAN_RING_TYPE_CP1_INDEX 1
132#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 133
4d75658b
AD		 134/* R600+ has an async dma ring */
135#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 136/* cayman add a second async dma ring */
137#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 138
f2ba57b5 139/* R600+ */
d93f7937
CK		 140#define R600_RING_TYPE_UVD_INDEX 5
141
142/* TN+ */
143#define TN_RING_TYPE_VCE1_INDEX 6
144#define TN_RING_TYPE_VCE2_INDEX 7
145
146/* max number of rings */
147#define RADEON_NUM_RINGS 8
f2ba57b5 148
1c61eae4
CK		 149/* number of hw syncs before falling back on blocking */
150#define RADEON_NUM_SYNCS 4
f2ba57b5 151
8f53492f
CK		 152/* number of hw syncs before falling back on blocking */
153#define RADEON_NUM_SYNCS 4
154
721604a1 155/* hardcode those limit for now */
ca19f21e 156#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 157#define RADEON_VA_RESERVED_SIZE (8 << 20)
158#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 159
1a0041b8
AD		 160/* hard reset data */
161#define RADEON_ASIC_RESET_DATA 0x39d5e86b
162
ec46c76d
AD		 163/* reset flags */
164#define RADEON_RESET_GFX (1 << 0)
165#define RADEON_RESET_COMPUTE (1 << 1)
166#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 167#define RADEON_RESET_CP (1 << 3)
168#define RADEON_RESET_GRBM (1 << 4)
169#define RADEON_RESET_DMA1 (1 << 5)
170#define RADEON_RESET_RLC (1 << 6)
171#define RADEON_RESET_SEM (1 << 7)
172#define RADEON_RESET_IH (1 << 8)
173#define RADEON_RESET_VMC (1 << 9)
174#define RADEON_RESET_MC (1 << 10)
175#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 176
22c775ce
AD		 177/* CG block flags */
178#define RADEON_CG_BLOCK_GFX (1 << 0)
179#define RADEON_CG_BLOCK_MC (1 << 1)
180#define RADEON_CG_BLOCK_SDMA (1 << 2)
181#define RADEON_CG_BLOCK_UVD (1 << 3)
182#define RADEON_CG_BLOCK_VCE (1 << 4)
183#define RADEON_CG_BLOCK_HDP (1 << 5)
e16866ec 184#define RADEON_CG_BLOCK_BIF (1 << 6)
22c775ce 185
64d8a728
AD		 186/* CG flags */
187#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
188#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
189#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
190#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
191#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
192#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
193#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
194#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
195#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
196#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
197#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
198#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
199#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
200#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
201#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
202#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
203#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
204
205/* PG flags */
2b19d17f 206#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
64d8a728
AD		 207#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
208#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
209#define RADEON_PG_SUPPORT_UVD (1 << 3)
210#define RADEON_PG_SUPPORT_VCE (1 << 4)
211#define RADEON_PG_SUPPORT_CP (1 << 5)
212#define RADEON_PG_SUPPORT_GDS (1 << 6)
213#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
214#define RADEON_PG_SUPPORT_SDMA (1 << 8)
215#define RADEON_PG_SUPPORT_ACP (1 << 9)
216#define RADEON_PG_SUPPORT_SAMU (1 << 10)
217
9e05fa1d
AD		 218/* max cursor sizes (in pixels) */
219#define CURSOR_WIDTH 64
220#define CURSOR_HEIGHT 64
221
222#define CIK_CURSOR_WIDTH 128
223#define CIK_CURSOR_HEIGHT 128
224
771fe6b9
JG		 225/*
226 * Errata workarounds.
227 */
228enum radeon_pll_errata {
229 CHIP_ERRATA_R300_CG = 0x00000001,
230 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
231 CHIP_ERRATA_PLL_DELAY = 0x00000004
232};
233
234
235struct radeon_device;
236
237
238/*
239 * BIOS.
240 */
241bool radeon_get_bios(struct radeon_device *rdev);
242
243/*
3ce0a23d 244 * Dummy page
771fe6b9 245 */
3ce0a23d
JG		 246struct radeon_dummy_page {
247 struct page *page;
248 dma_addr_t addr;
249};
250int radeon_dummy_page_init(struct radeon_device *rdev);
251void radeon_dummy_page_fini(struct radeon_device *rdev);
252
771fe6b9 253
3ce0a23d
JG		 254/*
255 * Clocks
256 */
771fe6b9
JG		 257struct radeon_clock {
258 struct radeon_pll p1pll;
259 struct radeon_pll p2pll;
bcc1c2a1 260 struct radeon_pll dcpll;
771fe6b9
JG		 261 struct radeon_pll spll;
262 struct radeon_pll mpll;
263 /* 10 Khz units */
264 uint32_t default_mclk;
265 uint32_t default_sclk;
bcc1c2a1 266 uint32_t default_dispclk;
4489cd62 267 uint32_t current_dispclk;
bcc1c2a1 268 uint32_t dp_extclk;
b20f9bef 269 uint32_t max_pixel_clock;
771fe6b9
JG		 270};
271
7433874e
RM		 272/*
273 * Power management
274 */
275int radeon_pm_init(struct radeon_device *rdev);
914a8987 276int radeon_pm_late_init(struct radeon_device *rdev);
29fb52ca 277void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 278void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 279void radeon_pm_suspend(struct radeon_device *rdev);
280void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 281void radeon_combios_get_power_modes(struct radeon_device *rdev);
282void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 283int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
284 u8 clock_type,
285 u32 clock,
286 bool strobe_mode,
287 struct atom_clock_dividers *dividers);
eaa778af
AD		 288int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
289 u32 clock,
290 bool strobe_mode,
291 struct atom_mpll_param *mpll_param);
8a83ec5e 292void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 293int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
294 u16 voltage_level, u8 voltage_type,
295 u32 *gpio_value, u32 *gpio_mask);
296void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
297 u32 eng_clock, u32 mem_clock);
298int radeon_atom_get_voltage_step(struct radeon_device *rdev,
299 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 300int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
301 u16 voltage_id, u16 *voltage);
beb79f40
AD		 302int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
303 u16 *voltage,
304 u16 leakage_idx);
cc8dbbb4
AD		 305int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
306 u16 *leakage_id);
307int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
308 u16 *vddc, u16 *vddci,
309 u16 virtual_voltage_id,
310 u16 vbios_voltage_id);
e9f274b2
AD		 311int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
312 u16 virtual_voltage_id,
313 u16 *voltage);
ae5b0abb
AD		 314int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
315 u8 voltage_type,
316 u16 nominal_voltage,
317 u16 *true_voltage);
318int radeon_atom_get_min_voltage(struct radeon_device *rdev,
319 u8 voltage_type, u16 *min_voltage);
320int radeon_atom_get_max_voltage(struct radeon_device *rdev,
321 u8 voltage_type, u16 *max_voltage);
322int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 323 u8 voltage_type, u8 voltage_mode,
ae5b0abb 324 struct atom_voltage_table *voltage_table);
58653abd
AD		 325bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
326 u8 voltage_type, u8 voltage_mode);
636e2582
AD		 327int radeon_atom_get_svi2_info(struct radeon_device *rdev,
328 u8 voltage_type,
329 u8 *svd_gpio_id, u8 *svc_gpio_id);
ae5b0abb
AD		 330void radeon_atom_update_memory_dll(struct radeon_device *rdev,
331 u32 mem_clock);
332void radeon_atom_set_ac_timing(struct radeon_device *rdev,
333 u32 mem_clock);
334int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
335 u8 module_index,
336 struct atom_mc_reg_table *reg_table);
337int radeon_atom_get_memory_info(struct radeon_device *rdev,
338 u8 module_index, struct atom_memory_info *mem_info);
339int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
340 bool gddr5, u8 module_index,
341 struct atom_memory_clock_range_table *mclk_range_table);
342int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
343 u16 voltage_id, u16 *voltage);
f892034a 344void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 345extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
346 unsigned *bankh, unsigned *mtaspect,
347 unsigned *tile_split);
3ce0a23d 348
771fe6b9
JG		 349/*
350 * Fences.
351 */
352struct radeon_fence_driver {
353 uint32_t scratch_reg;
30eb77f4
JG		 354 uint64_t gpu_addr;
355 volatile uint32_t *cpu_addr;
68e250b7
CK		 356 /* sync_seq is protected by ring emission lock */
357 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 358 atomic64_t last_seq;
0a0c7596 359 bool initialized;
771fe6b9
JG		 360};
361
362struct radeon_fence {
363 struct radeon_device *rdev;
364 struct kref kref;
771fe6b9 365 /* protected by radeon_fence.lock */
bb635567 366 uint64_t seq;
7465280c 367 /* RB, DMA, etc. */
bb635567 368 unsigned ring;
771fe6b9
JG		 369};
370
30eb77f4
JG		 371int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
372int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 373void radeon_fence_driver_fini(struct radeon_device *rdev);
76903b96 374void radeon_fence_driver_force_completion(struct radeon_device *rdev);
876dc9f3 375int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 376void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9
JG		 377bool radeon_fence_signaled(struct radeon_fence *fence);
378int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
37615527
CK		 379int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
380int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
0085c950
JG		 381int radeon_fence_wait_any(struct radeon_device *rdev,
382 struct radeon_fence **fences,
383 bool intr);
771fe6b9
JG		 384struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
385void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 386unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 387bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
388void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
389static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
390 struct radeon_fence *b)
391{
392 if (!a) {
393 return b;
394 }
395
396 if (!b) {
397 return a;
398 }
399
400 BUG_ON(a->ring != b->ring);
401
402 if (a->seq > b->seq) {
403 return a;
404 } else {
405 return b;
406 }
407}
771fe6b9 408
ee60e29f
CK		 409static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
410 struct radeon_fence *b)
411{
412 if (!a) {
413 return false;
414 }
415
416 if (!b) {
417 return true;
418 }
419
420 BUG_ON(a->ring != b->ring);
421
422 return a->seq < b->seq;
423}
424
e024e110
DA		 425/*
426 * Tiling registers
427 */
428struct radeon_surface_reg {
4c788679 429 struct radeon_bo *bo;
e024e110
DA		 430};
431
432#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 433
434/*
4c788679 435 * TTM.
771fe6b9 436 */
4c788679
JG		 437struct radeon_mman {
438 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 439 struct drm_global_reference mem_global_ref;
4c788679 440 struct ttm_bo_device bdev;
0a0c7596
JG		 441 bool mem_global_referenced;
442 bool initialized;
2014b569
CK		 443
444#if defined(CONFIG_DEBUG_FS)
445 struct dentry *vram;
dd66d20e 446 struct dentry *gtt;
2014b569 447#endif
4c788679
JG		 448};
449
721604a1
JG		 450/* bo virtual address in a specific vm */
451struct radeon_bo_va {
e971bd5e 452 /* protected by bo being reserved */
721604a1 453 struct list_head bo_list;
721604a1 454 uint32_t flags;
e31ad969 455 uint64_t addr;
e971bd5e
CK		 456 unsigned ref_count;
457
458 /* protected by vm mutex */
0aea5e4a 459 struct interval_tree_node it;
036bf46a 460 struct list_head vm_status;
e971bd5e
CK		 461
462 /* constant after initialization */
463 struct radeon_vm *vm;
464 struct radeon_bo *bo;
721604a1
JG		 465};
466
4c788679
JG		 467struct radeon_bo {
468 /* Protected by gem.mutex */
469 struct list_head list;
470 /* Protected by tbo.reserved */
bda72d58 471 u32 initial_domain;
312ea8da
JG		 472 u32 placements[3];
473 struct ttm_placement placement;
4c788679
JG		 474 struct ttm_buffer_object tbo;
475 struct ttm_bo_kmap_obj kmap;
02376d82 476 u32 flags;
4c788679
JG		 477 unsigned pin_count;
478 void *kptr;
479 u32 tiling_flags;
480 u32 pitch;
481 int surface_reg;
721604a1
JG		 482 /* list of all virtual address to which this bo
483 * is associated to
484 */
485 struct list_head va;
4c788679
JG		 486 /* Constant after initialization */
487 struct radeon_device *rdev;
441921d5 488 struct drm_gem_object gem_base;
63bc620b 489
409851f4
JG		 490 struct ttm_bo_kmap_obj dma_buf_vmap;
491 pid_t pid;
341cb9e4
CK		 492
493 struct radeon_mn *mn;
494 struct interval_tree_node mn_it;
4c788679 495};
7e4d15d9 496#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 497
409851f4
JG		 498int radeon_gem_debugfs_init(struct radeon_device *rdev);
499
b15ba512
JG		 500/* sub-allocation manager, it has to be protected by another lock.
501 * By conception this is an helper for other part of the driver
502 * like the indirect buffer or semaphore, which both have their
503 * locking.
504 *
505 * Principe is simple, we keep a list of sub allocation in offset
506 * order (first entry has offset == 0, last entry has the highest
507 * offset).
508 *
509 * When allocating new object we first check if there is room at
510 * the end total_size - (last_object_offset + last_object_size) >=
511 * alloc_size. If so we allocate new object there.
512 *
513 * When there is not enough room at the end, we start waiting for
514 * each sub object until we reach object_offset+object_size >=
515 * alloc_size, this object then become the sub object we return.
516 *
517 * Alignment can't be bigger than page size.
518 *
519 * Hole are not considered for allocation to keep things simple.
520 * Assumption is that there won't be hole (all object on same
521 * alignment).
522 */
523struct radeon_sa_manager {
bfb38d35 524 wait_queue_head_t wq;
b15ba512 525 struct radeon_bo *bo;
c3b7fe8b
CK		 526 struct list_head *hole;
527 struct list_head flist[RADEON_NUM_RINGS];
528 struct list_head olist;
b15ba512
JG		 529 unsigned size;
530 uint64_t gpu_addr;
531 void *cpu_ptr;
532 uint32_t domain;
6c4f978b 533 uint32_t align;
b15ba512
JG		 534};
535
536struct radeon_sa_bo;
537
538/* sub-allocation buffer */
539struct radeon_sa_bo {
c3b7fe8b
CK		 540 struct list_head olist;
541 struct list_head flist;
b15ba512 542 struct radeon_sa_manager *manager;
e6661a96
CK		 543 unsigned soffset;
544 unsigned eoffset;
557017a0 545 struct radeon_fence *fence;
b15ba512
JG		 546};
547
771fe6b9
JG		 548/*
549 * GEM objects.
550 */
551struct radeon_gem {
4c788679 552 struct mutex mutex;
771fe6b9
JG		 553 struct list_head objects;
554};
555
556int radeon_gem_init(struct radeon_device *rdev);
557void radeon_gem_fini(struct radeon_device *rdev);
391bfec3 558int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
4c788679 559 int alignment, int initial_domain,
ed5cb43f 560 u32 flags, bool kernel,
4c788679 561 struct drm_gem_object **obj);
771fe6b9 562
ff72145b
DA		 563int radeon_mode_dumb_create(struct drm_file *file_priv,
564 struct drm_device *dev,
565 struct drm_mode_create_dumb *args);
566int radeon_mode_dumb_mmap(struct drm_file *filp,
567 struct drm_device *dev,
568 uint32_t handle, uint64_t *offset_p);
771fe6b9 569
c1341e52
JG		 570/*
571 * Semaphores.
572 */
c1341e52 573struct radeon_semaphore {
a8c05940
JG		 574 struct radeon_sa_bo *sa_bo;
575 signed waiters;
c1341e52 576 uint64_t gpu_addr;
1654b817 577 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
c1341e52
JG		 578};
579
c1341e52
JG		 580int radeon_semaphore_create(struct radeon_device *rdev,
581 struct radeon_semaphore **semaphore);
1654b817 582bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
c1341e52 583 struct radeon_semaphore *semaphore);
1654b817 584bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
c1341e52 585 struct radeon_semaphore *semaphore);
1654b817
CK		 586void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
587 struct radeon_fence *fence);
8f676c4c
CK		 588int radeon_semaphore_sync_rings(struct radeon_device *rdev,
589 struct radeon_semaphore *semaphore,
1654b817 590 int waiting_ring);
c1341e52 591void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 592 struct radeon_semaphore **semaphore,
a8c05940 593 struct radeon_fence *fence);
c1341e52 594
771fe6b9
JG		 595/*
596 * GART structures, functions & helpers
597 */
598struct radeon_mc;
599
a77f1718 600#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 601#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 602#define RADEON_GPU_PAGE_SHIFT 12
721604a1 603#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 604
77497f27
MD		 605#define RADEON_GART_PAGE_DUMMY 0
606#define RADEON_GART_PAGE_VALID (1 << 0)
607#define RADEON_GART_PAGE_READ (1 << 1)
608#define RADEON_GART_PAGE_WRITE (1 << 2)
609#define RADEON_GART_PAGE_SNOOP (1 << 3)
610
771fe6b9
JG		 611struct radeon_gart {
612 dma_addr_t table_addr;
c9a1be96
JG		 613 struct radeon_bo *robj;
614 void *ptr;
771fe6b9
JG		 615 unsigned num_gpu_pages;
616 unsigned num_cpu_pages;
617 unsigned table_size;
771fe6b9
JG		 618 struct page **pages;
619 dma_addr_t *pages_addr;
620 bool ready;
621};
622
623int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
624void radeon_gart_table_ram_free(struct radeon_device *rdev);
625int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
626void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 627int radeon_gart_table_vram_pin(struct radeon_device *rdev);
628void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 629int radeon_gart_init(struct radeon_device *rdev);
630void radeon_gart_fini(struct radeon_device *rdev);
631void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
632 int pages);
633int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516 634 int pages, struct page **pagelist,
77497f27 635 dma_addr_t *dma_addr, uint32_t flags);
771fe6b9
JG		 636
637
638/*
639 * GPU MC structures, functions & helpers
640 */
641struct radeon_mc {
642 resource_size_t aper_size;
643 resource_size_t aper_base;
644 resource_size_t agp_base;
7a50f01a
DA		 645 /* for some chips with <= 32MB we need to lie
646 * about vram size near mc fb location */
3ce0a23d 647 u64 mc_vram_size;
d594e46a 648 u64 visible_vram_size;
3ce0a23d
JG		 649 u64 gtt_size;
650 u64 gtt_start;
651 u64 gtt_end;
3ce0a23d
JG		 652 u64 vram_start;
653 u64 vram_end;
771fe6b9 654 unsigned vram_width;
3ce0a23d 655 u64 real_vram_size;
771fe6b9
JG		 656 int vram_mtrr;
657 bool vram_is_ddr;
d594e46a 658 bool igp_sideport_enabled;
8d369bb1 659 u64 gtt_base_align;
9ed8b1f9 660 u64 mc_mask;
771fe6b9
JG		 661};
662
06b6476d
AD		 663bool radeon_combios_sideport_present(struct radeon_device *rdev);
664bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 665
666/*
667 * GPU scratch registers structures, functions & helpers
668 */
669struct radeon_scratch {
670 unsigned num_reg;
724c80e1 671 uint32_t reg_base;
771fe6b9
JG		 672 bool free[32];
673 uint32_t reg[32];
674};
675
676int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
677void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
678
75efdee1
AD		 679/*
680 * GPU doorbell structures, functions & helpers
681 */
d5754ab8
AL		 682#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
683
75efdee1 684struct radeon_doorbell {
75efdee1 685 /* doorbell mmio */
d5754ab8
AL		 686 resource_size_t base;
687 resource_size_t size;
688 u32 __iomem *ptr;
689 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
690 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
75efdee1
AD		 691};
692
693int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
694void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
771fe6b9
JG		 695
696/*
697 * IRQS.
698 */
6f34be50 699
fa7f517c
CK		 700struct radeon_flip_work {
701 struct work_struct flip_work;
702 struct work_struct unpin_work;
703 struct radeon_device *rdev;
704 int crtc_id;
c60381bd 705 uint64_t base;
6f34be50 706 struct drm_pending_vblank_event *event;
fa7f517c 707 struct radeon_bo *old_rbo;
fa7f517c 708 struct radeon_fence *fence;
6f34be50
AD		 709};
710
711struct r500_irq_stat_regs {
712 u32 disp_int;
f122c610 713 u32 hdmi0_status;
6f34be50
AD		 714};
715
716struct r600_irq_stat_regs {
717 u32 disp_int;
718 u32 disp_int_cont;
719 u32 disp_int_cont2;
720 u32 d1grph_int;
721 u32 d2grph_int;
f122c610
AD		 722 u32 hdmi0_status;
723 u32 hdmi1_status;
6f34be50
AD		 724};
725
726struct evergreen_irq_stat_regs {
727 u32 disp_int;
728 u32 disp_int_cont;
729 u32 disp_int_cont2;
730 u32 disp_int_cont3;
731 u32 disp_int_cont4;
732 u32 disp_int_cont5;
733 u32 d1grph_int;
734 u32 d2grph_int;
735 u32 d3grph_int;
736 u32 d4grph_int;
737 u32 d5grph_int;
738 u32 d6grph_int;
f122c610
AD		 739 u32 afmt_status1;
740 u32 afmt_status2;
741 u32 afmt_status3;
742 u32 afmt_status4;
743 u32 afmt_status5;
744 u32 afmt_status6;
6f34be50
AD		 745};
746
a59781bb
AD		 747struct cik_irq_stat_regs {
748 u32 disp_int;
749 u32 disp_int_cont;
750 u32 disp_int_cont2;
751 u32 disp_int_cont3;
752 u32 disp_int_cont4;
753 u32 disp_int_cont5;
754 u32 disp_int_cont6;
f5d636d2
CK		 755 u32 d1grph_int;
756 u32 d2grph_int;
757 u32 d3grph_int;
758 u32 d4grph_int;
759 u32 d5grph_int;
760 u32 d6grph_int;
a59781bb
AD		 761};
762
6f34be50
AD		 763union radeon_irq_stat_regs {
764 struct r500_irq_stat_regs r500;
765 struct r600_irq_stat_regs r600;
766 struct evergreen_irq_stat_regs evergreen;
a59781bb 767 struct cik_irq_stat_regs cik;
6f34be50
AD		 768};
769
771fe6b9 770struct radeon_irq {
fb98257a
CK		 771 bool installed;
772 spinlock_t lock;
736fc37f 773 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 774 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 775 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 776 wait_queue_head_t vblank_queue;
777 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 778 bool afmt[RADEON_MAX_AFMT_BLOCKS];
779 union radeon_irq_stat_regs stat_regs;
4a6369e9 780 bool dpm_thermal;
771fe6b9
JG		 781};
782
783int radeon_irq_kms_init(struct radeon_device *rdev);
784void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b
AD		 785void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
786void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 787void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
788void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 789void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
790void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
791void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
792void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 793
794/*
e32eb50d 795 * CP & rings.
771fe6b9 796 */
7465280c 797
771fe6b9 798struct radeon_ib {
68470ae7
JG		 799 struct radeon_sa_bo *sa_bo;
800 uint32_t length_dw;
801 uint64_t gpu_addr;
802 uint32_t *ptr;
876dc9f3 803 int ring;
68470ae7 804 struct radeon_fence *fence;
4bf3dd92 805 struct radeon_vm *vm;
68470ae7
JG		 806 bool is_const_ib;
807 struct radeon_semaphore *semaphore;
771fe6b9
JG		 808};
809
e32eb50d 810struct radeon_ring {
4c788679 811 struct radeon_bo *ring_obj;
771fe6b9 812 volatile uint32_t *ring;
5596a9db 813 unsigned rptr_offs;
45df6803 814 unsigned rptr_save_reg;
89d35807
AD		 815 u64 next_rptr_gpu_addr;
816 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 817 unsigned wptr;
818 unsigned wptr_old;
819 unsigned ring_size;
820 unsigned ring_free_dw;
821 int count_dw;
aee4aa73
CK		 822 atomic_t last_rptr;
823 atomic64_t last_activity;
771fe6b9
JG		 824 uint64_t gpu_addr;
825 uint32_t align_mask;
826 uint32_t ptr_mask;
771fe6b9 827 bool ready;
78c5560a 828 u32 nop;
8b25ed34 829 u32 idx;
5f0839c1
JG		 830 u64 last_semaphore_signal_addr;
831 u64 last_semaphore_wait_addr;
963e81f9
AD		 832 /* for CIK queues */
833 u32 me;
834 u32 pipe;
835 u32 queue;
836 struct radeon_bo *mqd_obj;
d5754ab8 837 u32 doorbell_index;
963e81f9
AD		 838 unsigned wptr_offs;
839};
840
841struct radeon_mec {
842 struct radeon_bo *hpd_eop_obj;
843 u64 hpd_eop_gpu_addr;
844 u32 num_pipe;
845 u32 num_mec;
846 u32 num_queue;
771fe6b9
JG		 847};
848
721604a1
JG		 849/*
850 * VM
851 */
ee60e29f 852
fa87e62d 853/* maximum number of VMIDs */
ee60e29f
CK		 854#define RADEON_NUM_VM 16
855
fa87e62d 856/* number of entries in page table */
4510fb98 857#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
fa87e62d 858
1c01103c
AD		 859/* PTBs (Page Table Blocks) need to be aligned to 32K */
860#define RADEON_VM_PTB_ALIGN_SIZE 32768
861#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
862#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
863
24c16439
CK		 864#define R600_PTE_VALID (1 << 0)
865#define R600_PTE_SYSTEM (1 << 1)
866#define R600_PTE_SNOOPED (1 << 2)
867#define R600_PTE_READABLE (1 << 5)
868#define R600_PTE_WRITEABLE (1 << 6)
869
ec3dbbcb
CK		 870/* PTE (Page Table Entry) fragment field for different page sizes */
871#define R600_PTE_FRAG_4KB (0 << 7)
872#define R600_PTE_FRAG_64KB (4 << 7)
873#define R600_PTE_FRAG_256KB (6 << 7)
874
33fa9fe3
CK		 875/* flags needed to be set so we can copy directly from the GART table */
876#define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
877 R600_PTE_SYSTEM | R600_PTE_VALID )
0e97703c 878
6d2f2944
CK		 879struct radeon_vm_pt {
880 struct radeon_bo *bo;
881 uint64_t addr;
882};
883
721604a1 884struct radeon_vm {
0aea5e4a 885 struct rb_root va;
ee60e29f 886 unsigned id;
90a51a32 887
e31ad969
CK		 888 /* BOs moved, but not yet updated in the PT */
889 struct list_head invalidated;
890
036bf46a
CK		 891 /* BOs freed, but not yet updated in the PT */
892 struct list_head freed;
893
90a51a32 894 /* contains the page directory */
6d2f2944 895 struct radeon_bo *page_directory;
90a51a32 896 uint64_t pd_gpu_addr;
6d2f2944 897 unsigned max_pde_used;
90a51a32
CK		 898
899 /* array of page tables, one for each page directory entry */
6d2f2944 900 struct radeon_vm_pt *page_tables;
90a51a32 901
cc9e67e3
CK		 902 struct radeon_bo_va *ib_bo_va;
903
721604a1
JG		 904 struct mutex mutex;
905 /* last fence for cs using this vm */
906 struct radeon_fence *fence;
9b40e5d8
CK		 907 /* last flush or NULL if we still need to flush */
908 struct radeon_fence *last_flush;
593b2635
CK		 909 /* last use of vmid */
910 struct radeon_fence *last_id_use;
721604a1
JG		 911};
912
721604a1 913struct radeon_vm_manager {
ee60e29f 914 struct radeon_fence *active[RADEON_NUM_VM];
721604a1 915 uint32_t max_pfn;
721604a1
JG		 916 /* number of VMIDs */
917 unsigned nvm;
918 /* vram base address for page table entry */
919 u64 vram_base_offset;
67e915e4
AD		 920 /* is vm enabled? */
921 bool enabled;
721604a1
JG		 922};
923
924/*
925 * file private structure
926 */
927struct radeon_fpriv {
928 struct radeon_vm vm;
929};
930
d8f60cfc
AD		 931/*
932 * R6xx+ IH ring
933 */
934struct r600_ih {
4c788679 935 struct radeon_bo *ring_obj;
d8f60cfc
AD		 936 volatile uint32_t *ring;
937 unsigned rptr;
d8f60cfc
AD		 938 unsigned ring_size;
939 uint64_t gpu_addr;
d8f60cfc 940 uint32_t ptr_mask;
c20dc369 941 atomic_t lock;
d8f60cfc
AD		 942 bool enabled;
943};
944
347e7592 945/*
2948f5e6 946 * RLC stuff
347e7592 947 */
2948f5e6
AD		 948#include "clearstate_defs.h"
949
950struct radeon_rlc {
347e7592
AD		 951 /* for power gating */
952 struct radeon_bo *save_restore_obj;
953 uint64_t save_restore_gpu_addr;
2948f5e6 954 volatile uint32_t *sr_ptr;
1fd11777 955 const u32 *reg_list;
2948f5e6 956 u32 reg_list_size;
347e7592
AD		 957 /* for clear state */
958 struct radeon_bo *clear_state_obj;
959 uint64_t clear_state_gpu_addr;
2948f5e6 960 volatile uint32_t *cs_ptr;
1fd11777 961 const struct cs_section_def *cs_data;
22c775ce
AD		 962 u32 clear_state_size;
963 /* for cp tables */
964 struct radeon_bo *cp_table_obj;
965 uint64_t cp_table_gpu_addr;
966 volatile uint32_t *cp_table_ptr;
967 u32 cp_table_size;
347e7592
AD		 968};
969
69e130a6 970int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 971 struct radeon_ib *ib, struct radeon_vm *vm,
972 unsigned size);
f2e39221 973void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
4ef72566 974int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1538a9e0 975 struct radeon_ib *const_ib, bool hdp_flush);
771fe6b9
JG		 976int radeon_ib_pool_init(struct radeon_device *rdev);
977void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 978int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 979/* Ring access between begin & end cannot sleep */
89d35807
AD		 980bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
981 struct radeon_ring *ring);
e32eb50d
CK		 982void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
983int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
984int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1538a9e0
MD		 985void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
986 bool hdp_flush);
987void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
988 bool hdp_flush);
d6999bc7 989void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 990void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
991int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
ff212f25
CK		 992void radeon_ring_lockup_update(struct radeon_device *rdev,
993 struct radeon_ring *ring);
069211e5 994bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 995unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
996 uint32_t **data);
997int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
998 unsigned size, uint32_t *data);
e32eb50d 999int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
ea31bf69 1000 unsigned rptr_offs, u32 nop);
e32eb50d 1001void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 1002
1003
4d75658b
AD		 1004/* r600 async dma */
1005void r600_dma_stop(struct radeon_device *rdev);
1006int r600_dma_resume(struct radeon_device *rdev);
1007void r600_dma_fini(struct radeon_device *rdev);
1008
8c5fd7ef
AD		 1009void cayman_dma_stop(struct radeon_device *rdev);
1010int cayman_dma_resume(struct radeon_device *rdev);
1011void cayman_dma_fini(struct radeon_device *rdev);
1012
771fe6b9
JG		 1013/*
1014 * CS.
1015 */
1016struct radeon_cs_reloc {
1017 struct drm_gem_object *gobj;
4c788679 1018 struct radeon_bo *robj;
df0af440
CK		 1019 struct ttm_validate_buffer tv;
1020 uint64_t gpu_offset;
ce6758c8
CK		 1021 unsigned prefered_domains;
1022 unsigned allowed_domains;
df0af440 1023 uint32_t tiling_flags;
771fe6b9 1024 uint32_t handle;
771fe6b9
JG		 1025};
1026
1027struct radeon_cs_chunk {
1028 uint32_t chunk_id;
1029 uint32_t length_dw;
1030 uint32_t *kdata;
721604a1 1031 void __user *user_ptr;
771fe6b9
JG		 1032};
1033
1034struct radeon_cs_parser {
c8c15ff1 1035 struct device *dev;
771fe6b9
JG		 1036 struct radeon_device *rdev;
1037 struct drm_file *filp;
1038 /* chunks */
1039 unsigned nchunks;
1040 struct radeon_cs_chunk *chunks;
1041 uint64_t *chunks_array;
1042 /* IB */
1043 unsigned idx;
1044 /* relocations */
1045 unsigned nrelocs;
1046 struct radeon_cs_reloc *relocs;
1047 struct radeon_cs_reloc **relocs_ptr;
df0af440 1048 struct radeon_cs_reloc *vm_bos;
771fe6b9 1049 struct list_head validated;
cf4ccd01 1050 unsigned dma_reloc_idx;
771fe6b9
JG		 1051 /* indices of various chunks */
1052 int chunk_ib_idx;
1053 int chunk_relocs_idx;
721604a1 1054 int chunk_flags_idx;
dfcf5f36 1055 int chunk_const_ib_idx;
f2e39221
JG		 1056 struct radeon_ib ib;
1057 struct radeon_ib const_ib;
771fe6b9 1058 void *track;
3ce0a23d 1059 unsigned family;
e70f224c 1060 int parser_error;
721604a1
JG		 1061 u32 cs_flags;
1062 u32 ring;
1063 s32 priority;
ecff665f 1064 struct ww_acquire_ctx ticket;
771fe6b9
JG		 1065};
1066
28a326c5
ML		 1067static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1068{
1069 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1070
1071 if (ibc->kdata)
1072 return ibc->kdata[idx];
1073 return p->ib.ptr[idx];
1074}
1075
513bcb46 1076
771fe6b9
JG		 1077struct radeon_cs_packet {
1078 unsigned idx;
1079 unsigned type;
1080 unsigned reg;
1081 unsigned opcode;
1082 int count;
1083 unsigned one_reg_wr;
1084};
1085
1086typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1087 struct radeon_cs_packet *pkt,
1088 unsigned idx, unsigned reg);
1089typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1090 struct radeon_cs_packet *pkt);
1091
1092
1093/*
1094 * AGP
1095 */
1096int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1097void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1098void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1099void radeon_agp_fini(struct radeon_device *rdev);
1100
1101
1102/*
1103 * Writeback
1104 */
1105struct radeon_wb {
4c788679 1106 struct radeon_bo *wb_obj;
771fe6b9
JG		 1107 volatile uint32_t *wb;
1108 uint64_t gpu_addr;
724c80e1 1109 bool enabled;
d0f8a854 1110 bool use_event;
771fe6b9
JG		 1111};
1112
724c80e1 1113#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1114#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1115#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1116#define RADEON_WB_CP1_RPTR_OFFSET 1280
1117#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1118#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1119#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1120#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1121#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1122#define CIK_WB_CP1_WPTR_OFFSET 3328
1123#define CIK_WB_CP2_WPTR_OFFSET 3584
724c80e1 1124
c93bb85b
JG		 1125/**
1126 * struct radeon_pm - power management datas
1127 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1128 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1129 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1130 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1131 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1132 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1133 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1134 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1135 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1136 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1137 * @needed_bandwidth: current bandwidth needs
1138 *
1139 * It keeps track of various data needed to take powermanagement decision.
25985edc 1140 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1141 * Equation between gpu/memory clock and available bandwidth is hw dependent
1142 * (type of memory, bus size, efficiency, ...)
1143 */
ce8f5370
AD		 1144
1145enum radeon_pm_method {
1146 PM_METHOD_PROFILE,
1147 PM_METHOD_DYNPM,
da321c8a 1148 PM_METHOD_DPM,
ce8f5370
AD		 1149};
1150
1151enum radeon_dynpm_state {
1152 DYNPM_STATE_DISABLED,
1153 DYNPM_STATE_MINIMUM,
1154 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1155 DYNPM_STATE_ACTIVE,
1156 DYNPM_STATE_SUSPENDED,
c913e23a 1157};
ce8f5370
AD		 1158enum radeon_dynpm_action {
1159 DYNPM_ACTION_NONE,
1160 DYNPM_ACTION_MINIMUM,
1161 DYNPM_ACTION_DOWNCLOCK,
1162 DYNPM_ACTION_UPCLOCK,
1163 DYNPM_ACTION_DEFAULT
c913e23a 1164};
56278a8e
AD		 1165
1166enum radeon_voltage_type {
1167 VOLTAGE_NONE = 0,
1168 VOLTAGE_GPIO,
1169 VOLTAGE_VDDC,
1170 VOLTAGE_SW
1171};
1172
0ec0e74f 1173enum radeon_pm_state_type {
da321c8a 1174 /* not used for dpm */
0ec0e74f
AD		 1175 POWER_STATE_TYPE_DEFAULT,
1176 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1177 /* user selectable states */
0ec0e74f
AD		 1178 POWER_STATE_TYPE_BATTERY,
1179 POWER_STATE_TYPE_BALANCED,
1180 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1181 /* internal states */
1182 POWER_STATE_TYPE_INTERNAL_UVD,
1183 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1184 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1185 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1186 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1187 POWER_STATE_TYPE_INTERNAL_BOOT,
1188 POWER_STATE_TYPE_INTERNAL_THERMAL,
1189 POWER_STATE_TYPE_INTERNAL_ACPI,
1190 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1191 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1192};
1193
ce8f5370
AD		 1194enum radeon_pm_profile_type {
1195 PM_PROFILE_DEFAULT,
1196 PM_PROFILE_AUTO,
1197 PM_PROFILE_LOW,
c9e75b21 1198 PM_PROFILE_MID,
ce8f5370
AD		 1199 PM_PROFILE_HIGH,
1200};
1201
1202#define PM_PROFILE_DEFAULT_IDX 0
1203#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1204#define PM_PROFILE_MID_SH_IDX 2
1205#define PM_PROFILE_HIGH_SH_IDX 3
1206#define PM_PROFILE_LOW_MH_IDX 4
1207#define PM_PROFILE_MID_MH_IDX 5
1208#define PM_PROFILE_HIGH_MH_IDX 6
1209#define PM_PROFILE_MAX 7
ce8f5370
AD		 1210
1211struct radeon_pm_profile {
1212 int dpms_off_ps_idx;
1213 int dpms_on_ps_idx;
1214 int dpms_off_cm_idx;
1215 int dpms_on_cm_idx;
516d0e46
AD		 1216};
1217
21a8122a
AD		 1218enum radeon_int_thermal_type {
1219 THERMAL_TYPE_NONE,
da321c8a
AD		 1220 THERMAL_TYPE_EXTERNAL,
1221 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1222 THERMAL_TYPE_RV6XX,
1223 THERMAL_TYPE_RV770,
da321c8a 1224 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1225 THERMAL_TYPE_EVERGREEN,
e33df25f 1226 THERMAL_TYPE_SUMO,
4fddba1f 1227 THERMAL_TYPE_NI,
14607d08 1228 THERMAL_TYPE_SI,
da321c8a 1229 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1230 THERMAL_TYPE_CI,
16fbe00d 1231 THERMAL_TYPE_KV,
21a8122a
AD		 1232};
1233
56278a8e
AD		 1234struct radeon_voltage {
1235 enum radeon_voltage_type type;
1236 /* gpio voltage */
1237 struct radeon_gpio_rec gpio;
1238 u32 delay; /* delay in usec from voltage drop to sclk change */
1239 bool active_high; /* voltage drop is active when bit is high */
1240 /* VDDC voltage */
1241 u8 vddc_id; /* index into vddc voltage table */
1242 u8 vddci_id; /* index into vddci voltage table */
1243 bool vddci_enabled;
1244 /* r6xx+ sw */
2feea49a
AD		 1245 u16 voltage;
1246 /* evergreen+ vddci */
1247 u16 vddci;
56278a8e
AD		 1248};
1249
d7311171
AD		 1250/* clock mode flags */
1251#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1252
56278a8e
AD		 1253struct radeon_pm_clock_info {
1254 /* memory clock */
1255 u32 mclk;
1256 /* engine clock */
1257 u32 sclk;
1258 /* voltage info */
1259 struct radeon_voltage voltage;
d7311171 1260 /* standardized clock flags */
56278a8e
AD		 1261 u32 flags;
1262};
1263
a48b9b4e 1264/* state flags */
d7311171 1265#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1266
56278a8e 1267struct radeon_power_state {
0ec0e74f 1268 enum radeon_pm_state_type type;
8f3f1c9a 1269 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1270 /* number of valid clock modes in this power state */
1271 int num_clock_modes;
56278a8e 1272 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1273 /* standardized state flags */
1274 u32 flags;
79daedc9
AD		 1275 u32 misc; /* vbios specific flags */
1276 u32 misc2; /* vbios specific flags */
1277 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1278};
1279
27459324
RM		 1280/*
1281 * Some modes are overclocked by very low value, accept them
1282 */
1283#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1284
2e9d4c05
AD		 1285enum radeon_dpm_auto_throttle_src {
1286 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1287 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1288};
1289
1290enum radeon_dpm_event_src {
1291 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1292 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1293 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1294 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1295 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1296};
1297
58bd2a88
AD		 1298#define RADEON_MAX_VCE_LEVELS 6
1299
b62d628b
AD		 1300enum radeon_vce_level {
1301 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1302 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1303 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1304 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1305 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1306 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1307};
1308
da321c8a
AD		 1309struct radeon_ps {
1310 u32 caps; /* vbios flags */
1311 u32 class; /* vbios flags */
1312 u32 class2; /* vbios flags */
1313 /* UVD clocks */
1314 u32 vclk;
1315 u32 dclk;
c4453e66
AD		 1316 /* VCE clocks */
1317 u32 evclk;
1318 u32 ecclk;
b62d628b
AD		 1319 bool vce_active;
1320 enum radeon_vce_level vce_level;
da321c8a
AD		 1321 /* asic priv */
1322 void *ps_priv;
1323};
1324
1325struct radeon_dpm_thermal {
1326 /* thermal interrupt work */
1327 struct work_struct work;
1328 /* low temperature threshold */
1329 int min_temp;
1330 /* high temperature threshold */
1331 int max_temp;
1332 /* was interrupt low to high or high to low */
1333 bool high_to_low;
1334};
1335
d22b7e40
AD		 1336enum radeon_clk_action
1337{
1338 RADEON_SCLK_UP = 1,
1339 RADEON_SCLK_DOWN
1340};
1341
1342struct radeon_blacklist_clocks
1343{
1344 u32 sclk;
1345 u32 mclk;
1346 enum radeon_clk_action action;
1347};
1348
61b7d601
AD		 1349struct radeon_clock_and_voltage_limits {
1350 u32 sclk;
1351 u32 mclk;
cdf6e805
AD		 1352 u16 vddc;
1353 u16 vddci;
61b7d601
AD		 1354};
1355
1356struct radeon_clock_array {
1357 u32 count;
1358 u32 *values;
1359};
1360
1361struct radeon_clock_voltage_dependency_entry {
1362 u32 clk;
1363 u16 v;
1364};
1365
1366struct radeon_clock_voltage_dependency_table {
1367 u32 count;
1368 struct radeon_clock_voltage_dependency_entry *entries;
1369};
1370
ef976ec4
AD		 1371union radeon_cac_leakage_entry {
1372 struct {
1373 u16 vddc;
1374 u32 leakage;
1375 };
1376 struct {
1377 u16 vddc1;
1378 u16 vddc2;
1379 u16 vddc3;
1380 };
61b7d601
AD		 1381};
1382
1383struct radeon_cac_leakage_table {
1384 u32 count;
ef976ec4 1385 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1386};
1387
929ee7a8
AD		 1388struct radeon_phase_shedding_limits_entry {
1389 u16 voltage;
1390 u32 sclk;
1391 u32 mclk;
1392};
1393
1394struct radeon_phase_shedding_limits_table {
1395 u32 count;
1396 struct radeon_phase_shedding_limits_entry *entries;
1397};
1398
84a9d9ee
AD		 1399struct radeon_uvd_clock_voltage_dependency_entry {
1400 u32 vclk;
1401 u32 dclk;
1402 u16 v;
1403};
1404
1405struct radeon_uvd_clock_voltage_dependency_table {
1406 u8 count;
1407 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1408};
1409
d29f013b
AD		 1410struct radeon_vce_clock_voltage_dependency_entry {
1411 u32 ecclk;
1412 u32 evclk;
1413 u16 v;
1414};
1415
1416struct radeon_vce_clock_voltage_dependency_table {
1417 u8 count;
1418 struct radeon_vce_clock_voltage_dependency_entry *entries;
1419};
1420
a5cb318e
AD		 1421struct radeon_ppm_table {
1422 u8 ppm_design;
1423 u16 cpu_core_number;
1424 u32 platform_tdp;
1425 u32 small_ac_platform_tdp;
1426 u32 platform_tdc;
1427 u32 small_ac_platform_tdc;
1428 u32 apu_tdp;
1429 u32 dgpu_tdp;
1430 u32 dgpu_ulv_power;
1431 u32 tj_max;
1432};
1433
58cb7632
AD		 1434struct radeon_cac_tdp_table {
1435 u16 tdp;
1436 u16 configurable_tdp;
1437 u16 tdc;
1438 u16 battery_power_limit;
1439 u16 small_power_limit;
1440 u16 low_cac_leakage;
1441 u16 high_cac_leakage;
1442 u16 maximum_power_delivery_limit;
1443};
1444
61b7d601
AD		 1445struct radeon_dpm_dynamic_state {
1446 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1447 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1448 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1449 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1450 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1451 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1452 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1453 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1454 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1455 struct radeon_clock_array valid_sclk_values;
1456 struct radeon_clock_array valid_mclk_values;
1457 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1458 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1459 u32 mclk_sclk_ratio;
1460 u32 sclk_mclk_delta;
1461 u16 vddc_vddci_delta;
1462 u16 min_vddc_for_pcie_gen2;
1463 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1464 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1465 struct radeon_ppm_table *ppm_table;
58cb7632 1466 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1467};
1468
1469struct radeon_dpm_fan {
1470 u16 t_min;
1471 u16 t_med;
1472 u16 t_high;
1473 u16 pwm_min;
1474 u16 pwm_med;
1475 u16 pwm_high;
1476 u8 t_hyst;
1477 u32 cycle_delay;
1478 u16 t_max;
1479 bool ucode_fan_control;
1480};
1481
32ce4652
AD		 1482enum radeon_pcie_gen {
1483 RADEON_PCIE_GEN1 = 0,
1484 RADEON_PCIE_GEN2 = 1,
1485 RADEON_PCIE_GEN3 = 2,
1486 RADEON_PCIE_GEN_INVALID = 0xffff
1487};
1488
70d01a5e
AD		 1489enum radeon_dpm_forced_level {
1490 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1491 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1492 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1493};
1494
58bd2a88
AD		 1495struct radeon_vce_state {
1496 /* vce clocks */
1497 u32 evclk;
1498 u32 ecclk;
1499 /* gpu clocks */
1500 u32 sclk;
1501 u32 mclk;
1502 u8 clk_idx;
1503 u8 pstate;
1504};
1505
da321c8a
AD		 1506struct radeon_dpm {
1507 struct radeon_ps *ps;
1508 /* number of valid power states */
1509 int num_ps;
1510 /* current power state that is active */
1511 struct radeon_ps *current_ps;
1512 /* requested power state */
1513 struct radeon_ps *requested_ps;
1514 /* boot up power state */
1515 struct radeon_ps *boot_ps;
1516 /* default uvd power state */
1517 struct radeon_ps *uvd_ps;
58bd2a88
AD		 1518 /* vce requirements */
1519 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1520 enum radeon_vce_level vce_level;
da321c8a
AD		 1521 enum radeon_pm_state_type state;
1522 enum radeon_pm_state_type user_state;
1523 u32 platform_caps;
1524 u32 voltage_response_time;
1525 u32 backbias_response_time;
1526 void *priv;
1527 u32 new_active_crtcs;
1528 int new_active_crtc_count;
1529 u32 current_active_crtcs;
1530 int current_active_crtc_count;
61b7d601
AD		 1531 struct radeon_dpm_dynamic_state dyn_state;
1532 struct radeon_dpm_fan fan;
1533 u32 tdp_limit;
1534 u32 near_tdp_limit;
a9e61410 1535 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1536 u32 sq_ramping_threshold;
1537 u32 cac_leakage;
1538 u16 tdp_od_limit;
1539 u32 tdp_adjustment;
1540 u16 load_line_slope;
1541 bool power_control;
5ca302f7 1542 bool ac_power;
da321c8a
AD		 1543 /* special states active */
1544 bool thermal_active;
8a227555 1545 bool uvd_active;
b62d628b 1546 bool vce_active;
da321c8a
AD		 1547 /* thermal handling */
1548 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1549 /* forced levels */
1550 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1551 /* track UVD streams */
1552 unsigned sd;
1553 unsigned hd;
da321c8a
AD		 1554};
1555
ce3537d5 1556void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
03afe6f6 1557void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
da321c8a 1558
c93bb85b 1559struct radeon_pm {
c913e23a 1560 struct mutex mutex;
db7fce39
CK		 1561 /* write locked while reprogramming mclk */
1562 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1563 u32 active_crtcs;
1564 int active_crtc_count;
c913e23a 1565 int req_vblank;
839461d3 1566 bool vblank_sync;
c93bb85b
JG		 1567 fixed20_12 max_bandwidth;
1568 fixed20_12 igp_sideport_mclk;
1569 fixed20_12 igp_system_mclk;
1570 fixed20_12 igp_ht_link_clk;
1571 fixed20_12 igp_ht_link_width;
1572 fixed20_12 k8_bandwidth;
1573 fixed20_12 sideport_bandwidth;
1574 fixed20_12 ht_bandwidth;
1575 fixed20_12 core_bandwidth;
1576 fixed20_12 sclk;
f47299c5 1577 fixed20_12 mclk;
c93bb85b 1578 fixed20_12 needed_bandwidth;
0975b162 1579 struct radeon_power_state *power_state;
56278a8e
AD		 1580 /* number of valid power states */
1581 int num_power_states;
a48b9b4e
AD		 1582 int current_power_state_index;
1583 int current_clock_mode_index;
1584 int requested_power_state_index;
1585 int requested_clock_mode_index;
1586 int default_power_state_index;
1587 u32 current_sclk;
1588 u32 current_mclk;
2feea49a
AD		 1589 u16 current_vddc;
1590 u16 current_vddci;
9ace9f7b
AD		 1591 u32 default_sclk;
1592 u32 default_mclk;
2feea49a
AD		 1593 u16 default_vddc;
1594 u16 default_vddci;
29fb52ca 1595 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1596 /* selected pm method */
1597 enum radeon_pm_method pm_method;
1598 /* dynpm power management */
1599 struct delayed_work dynpm_idle_work;
1600 enum radeon_dynpm_state dynpm_state;
1601 enum radeon_dynpm_action dynpm_planned_action;
1602 unsigned long dynpm_action_timeout;
1603 bool dynpm_can_upclock;
1604 bool dynpm_can_downclock;
1605 /* profile-based power management */
1606 enum radeon_pm_profile_type profile;
1607 int profile_index;
1608 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1609 /* internal thermal controller on rv6xx+ */
1610 enum radeon_int_thermal_type int_thermal_type;
1611 struct device *int_hwmon_dev;
da321c8a
AD		 1612 /* dpm */
1613 bool dpm_enabled;
1614 struct radeon_dpm dpm;
c93bb85b
JG		 1615};
1616
a4c9e2ee
AD		 1617int radeon_pm_get_type_index(struct radeon_device *rdev,
1618 enum radeon_pm_state_type ps_type,
1619 int instance);
f2ba57b5
CK		 1620/*
1621 * UVD
1622 */
1623#define RADEON_MAX_UVD_HANDLES 10
1624#define RADEON_UVD_STACK_SIZE (1024*1024)
1625#define RADEON_UVD_HEAP_SIZE (1024*1024)
1626
1627struct radeon_uvd {
1628 struct radeon_bo *vcpu_bo;
1629 void *cpu_addr;
1630 uint64_t gpu_addr;
9cc2e0e9 1631 void *saved_bo;
f2ba57b5
CK		 1632 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1633 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1634 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1635 struct delayed_work idle_work;
f2ba57b5
CK		 1636};
1637
1638int radeon_uvd_init(struct radeon_device *rdev);
1639void radeon_uvd_fini(struct radeon_device *rdev);
1640int radeon_uvd_suspend(struct radeon_device *rdev);
1641int radeon_uvd_resume(struct radeon_device *rdev);
1642int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1643 uint32_t handle, struct radeon_fence **fence);
1644int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1645 uint32_t handle, struct radeon_fence **fence);
1646void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1647void radeon_uvd_free_handles(struct radeon_device *rdev,
1648 struct drm_file *filp);
1649int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1650void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1651int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1652 unsigned vclk, unsigned dclk,
1653 unsigned vco_min, unsigned vco_max,
1654 unsigned fb_factor, unsigned fb_mask,
1655 unsigned pd_min, unsigned pd_max,
1656 unsigned pd_even,
1657 unsigned *optimal_fb_div,
1658 unsigned *optimal_vclk_div,
1659 unsigned *optimal_dclk_div);
1660int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1661 unsigned cg_upll_func_cntl);
771fe6b9 1662
d93f7937
CK		 1663/*
1664 * VCE
1665 */
1666#define RADEON_MAX_VCE_HANDLES 16
1667#define RADEON_VCE_STACK_SIZE (1024*1024)
1668#define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1669
1670struct radeon_vce {
1671 struct radeon_bo *vcpu_bo;
d93f7937 1672 uint64_t gpu_addr;
98ccc291
CK		 1673 unsigned fw_version;
1674 unsigned fb_version;
d93f7937
CK		 1675 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1676 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
2fc5703a 1677 unsigned img_size[RADEON_MAX_VCE_HANDLES];
03afe6f6 1678 struct delayed_work idle_work;
d93f7937
CK		 1679};
1680
1681int radeon_vce_init(struct radeon_device *rdev);
1682void radeon_vce_fini(struct radeon_device *rdev);
1683int radeon_vce_suspend(struct radeon_device *rdev);
1684int radeon_vce_resume(struct radeon_device *rdev);
1685int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1686 uint32_t handle, struct radeon_fence **fence);
1687int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1688 uint32_t handle, struct radeon_fence **fence);
1689void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
03afe6f6 1690void radeon_vce_note_usage(struct radeon_device *rdev);
2fc5703a 1691int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
d93f7937
CK		 1692int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1693bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1694 struct radeon_ring *ring,
1695 struct radeon_semaphore *semaphore,
1696 bool emit_wait);
1697void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1698void radeon_vce_fence_emit(struct radeon_device *rdev,
1699 struct radeon_fence *fence);
1700int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1701int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1702
b530602f 1703struct r600_audio_pin {
a92553ab
RM		 1704 int channels;
1705 int rate;
1706 int bits_per_sample;
1707 u8 status_bits;
1708 u8 category_code;
b530602f
AD		 1709 u32 offset;
1710 bool connected;
1711 u32 id;
1712};
1713
1714struct r600_audio {
1715 bool enabled;
1716 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1717 int num_pins;
a92553ab
RM		 1718};
1719
771fe6b9
JG		 1720/*
1721 * Benchmarking
1722 */
638dd7db 1723void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1724
1725
ecc0b326
MD		 1726/*
1727 * Testing
1728 */
1729void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1730void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1731 struct radeon_ring *cpA,
1732 struct radeon_ring *cpB);
60a7e396 1733void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326 1734
341cb9e4
CK		 1735/*
1736 * MMU Notifier
1737 */
1738int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1739void radeon_mn_unregister(struct radeon_bo *bo);
ecc0b326 1740
771fe6b9
JG		 1741/*
1742 * Debugfs
1743 */
4d8bf9ae
CK		 1744struct radeon_debugfs {
1745 struct drm_info_list *files;
1746 unsigned num_files;
1747};
1748
771fe6b9
JG		 1749int radeon_debugfs_add_files(struct radeon_device *rdev,
1750 struct drm_info_list *files,
1751 unsigned nfiles);
1752int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1753
76a0df85
CK		 1754/*
1755 * ASIC ring specific functions.
1756 */
1757struct radeon_asic_ring {
1758 /* ring read/write ptr handling */
1759 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1760 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1761 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1762
1763 /* validating and patching of IBs */
1764 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1765 int (*cs_parse)(struct radeon_cs_parser *p);
1766
1767 /* command emmit functions */
1768 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1769 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
72a9987e 1770 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1654b817 1771 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
76a0df85
CK		 1772 struct radeon_semaphore *semaphore, bool emit_wait);
1773 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1774
1775 /* testing functions */
1776 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1777 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1778 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1779
1780 /* deprecated */
1781 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1782};
771fe6b9
JG		 1783
1784/*
1785 * ASIC specific functions.
1786 */
1787struct radeon_asic {
068a117c 1788 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1789 void (*fini)(struct radeon_device *rdev);
1790 int (*resume)(struct radeon_device *rdev);
1791 int (*suspend)(struct radeon_device *rdev);
28d52043 1792 void (*vga_set_state)(struct radeon_device *rdev, bool state);
a2d07b74 1793 int (*asic_reset)(struct radeon_device *rdev);
124764f1
MD		 1794 /* Flush the HDP cache via MMIO */
1795 void (*mmio_hdp_flush)(struct radeon_device *rdev);
54e88e06
AD		 1796 /* check if 3D engine is idle */
1797 bool (*gui_idle)(struct radeon_device *rdev);
1798 /* wait for mc_idle */
1799 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1800 /* get the reference clock */
1801 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1802 /* get the gpu clock counter */
1803 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
54e88e06 1804 /* gart */
c5b3b850
AD		 1805 struct {
1806 void (*tlb_flush)(struct radeon_device *rdev);
7f90fc96 1807 void (*set_page)(struct radeon_device *rdev, unsigned i,
77497f27 1808 uint64_t addr, uint32_t flags);
c5b3b850 1809 } gart;
05b07147
CK		 1810 struct {
1811 int (*init)(struct radeon_device *rdev);
1812 void (*fini)(struct radeon_device *rdev);
03f62abd
CK		 1813 void (*copy_pages)(struct radeon_device *rdev,
1814 struct radeon_ib *ib,
1815 uint64_t pe, uint64_t src,
1816 unsigned count);
1817 void (*write_pages)(struct radeon_device *rdev,
1818 struct radeon_ib *ib,
1819 uint64_t pe,
1820 uint64_t addr, unsigned count,
1821 uint32_t incr, uint32_t flags);
1822 void (*set_pages)(struct radeon_device *rdev,
1823 struct radeon_ib *ib,
1824 uint64_t pe,
1825 uint64_t addr, unsigned count,
1826 uint32_t incr, uint32_t flags);
1827 void (*pad_ib)(struct radeon_ib *ib);
05b07147 1828 } vm;
54e88e06 1829 /* ring specific callbacks */
76a0df85 1830 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1831 /* irqs */
b35ea4ab
AD		 1832 struct {
1833 int (*set)(struct radeon_device *rdev);
1834 int (*process)(struct radeon_device *rdev);
1835 } irq;
54e88e06 1836 /* displays */
c79a49ca
AD		 1837 struct {
1838 /* display watermarks */
1839 void (*bandwidth_update)(struct radeon_device *rdev);
1840 /* get frame count */
1841 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1842 /* wait for vblank */
1843 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1844 /* set backlight level */
1845 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1846 /* get backlight level */
1847 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1848 /* audio callbacks */
1849 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1850 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1851 } display;
54e88e06 1852 /* copy functions for bo handling */
27cd7769
AD		 1853 struct {
1854 int (*blit)(struct radeon_device *rdev,
1855 uint64_t src_offset,
1856 uint64_t dst_offset,
1857 unsigned num_gpu_pages,
876dc9f3 1858 struct radeon_fence **fence);
27cd7769
AD		 1859 u32 blit_ring_index;
1860 int (*dma)(struct radeon_device *rdev,
1861 uint64_t src_offset,
1862 uint64_t dst_offset,
1863 unsigned num_gpu_pages,
876dc9f3 1864 struct radeon_fence **fence);
27cd7769
AD		 1865 u32 dma_ring_index;
1866 /* method used for bo copy */
1867 int (*copy)(struct radeon_device *rdev,
1868 uint64_t src_offset,
1869 uint64_t dst_offset,
1870 unsigned num_gpu_pages,
876dc9f3 1871 struct radeon_fence **fence);
27cd7769
AD		 1872 /* ring used for bo copies */
1873 u32 copy_ring_index;
1874 } copy;
54e88e06 1875 /* surfaces */
9e6f3d02
AD		 1876 struct {
1877 int (*set_reg)(struct radeon_device *rdev, int reg,
1878 uint32_t tiling_flags, uint32_t pitch,
1879 uint32_t offset, uint32_t obj_size);
1880 void (*clear_reg)(struct radeon_device *rdev, int reg);
1881 } surface;
54e88e06 1882 /* hotplug detect */
901ea57d
AD		 1883 struct {
1884 void (*init)(struct radeon_device *rdev);
1885 void (*fini)(struct radeon_device *rdev);
1886 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1887 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1888 } hpd;
da321c8a 1889 /* static power management */
a02fa397
AD		 1890 struct {
1891 void (*misc)(struct radeon_device *rdev);
1892 void (*prepare)(struct radeon_device *rdev);
1893 void (*finish)(struct radeon_device *rdev);
1894 void (*init_profile)(struct radeon_device *rdev);
1895 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1896 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1897 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1898 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1899 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1900 int (*get_pcie_lanes)(struct radeon_device *rdev);
1901 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1902 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1903 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
b59b7333 1904 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
6bd1c385 1905 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1906 } pm;
da321c8a
AD		 1907 /* dynamic power management */
1908 struct {
1909 int (*init)(struct radeon_device *rdev);
1910 void (*setup_asic)(struct radeon_device *rdev);
1911 int (*enable)(struct radeon_device *rdev);
914a8987 1912 int (*late_enable)(struct radeon_device *rdev);
da321c8a 1913 void (*disable)(struct radeon_device *rdev);
84dd1928 1914 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1915 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1916 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1917 void (*display_configuration_changed)(struct radeon_device *rdev);
1918 void (*fini)(struct radeon_device *rdev);
1919 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1920 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1921 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1922 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1923 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1924 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1925 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1c71bda0 1926 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
da321c8a 1927 } dpm;
6f34be50 1928 /* pageflipping */
0f9e006c 1929 struct {
157fa14d
CK		 1930 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1931 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
0f9e006c 1932 } pflip;
771fe6b9
JG		 1933};
1934
21f9a437
JG		 1935/*
1936 * Asic structures
1937 */
551ebd83 1938struct r100_asic {
225758d8
JG		 1939 const unsigned *reg_safe_bm;
1940 unsigned reg_safe_bm_size;
1941 u32 hdp_cntl;
551ebd83
DA		 1942};
1943
21f9a437 1944struct r300_asic {
225758d8
JG		 1945 const unsigned *reg_safe_bm;
1946 unsigned reg_safe_bm_size;
1947 u32 resync_scratch;
1948 u32 hdp_cntl;
21f9a437
JG		 1949};
1950
1951struct r600_asic {
225758d8
JG		 1952 unsigned max_pipes;
1953 unsigned max_tile_pipes;
1954 unsigned max_simds;
1955 unsigned max_backends;
1956 unsigned max_gprs;
1957 unsigned max_threads;
1958 unsigned max_stack_entries;
1959 unsigned max_hw_contexts;
1960 unsigned max_gs_threads;
1961 unsigned sx_max_export_size;
1962 unsigned sx_max_export_pos_size;
1963 unsigned sx_max_export_smx_size;
1964 unsigned sq_num_cf_insts;
1965 unsigned tiling_nbanks;
1966 unsigned tiling_npipes;
1967 unsigned tiling_group_size;
e7aeeba6 1968 unsigned tile_config;
e55b9422 1969 unsigned backend_map;
65fcf668 1970 unsigned active_simds;
21f9a437
JG		 1971};
1972
1973struct rv770_asic {
225758d8
JG		 1974 unsigned max_pipes;
1975 unsigned max_tile_pipes;
1976 unsigned max_simds;
1977 unsigned max_backends;
1978 unsigned max_gprs;
1979 unsigned max_threads;
1980 unsigned max_stack_entries;
1981 unsigned max_hw_contexts;
1982 unsigned max_gs_threads;
1983 unsigned sx_max_export_size;
1984 unsigned sx_max_export_pos_size;
1985 unsigned sx_max_export_smx_size;
1986 unsigned sq_num_cf_insts;
1987 unsigned sx_num_of_sets;
1988 unsigned sc_prim_fifo_size;
1989 unsigned sc_hiz_tile_fifo_size;
1990 unsigned sc_earlyz_tile_fifo_fize;
1991 unsigned tiling_nbanks;
1992 unsigned tiling_npipes;
1993 unsigned tiling_group_size;
e7aeeba6 1994 unsigned tile_config;
e55b9422 1995 unsigned backend_map;
65fcf668 1996 unsigned active_simds;
21f9a437
JG		 1997};
1998
32fcdbf4
AD		 1999struct evergreen_asic {
2000 unsigned num_ses;
2001 unsigned max_pipes;
2002 unsigned max_tile_pipes;
2003 unsigned max_simds;
2004 unsigned max_backends;
2005 unsigned max_gprs;
2006 unsigned max_threads;
2007 unsigned max_stack_entries;
2008 unsigned max_hw_contexts;
2009 unsigned max_gs_threads;
2010 unsigned sx_max_export_size;
2011 unsigned sx_max_export_pos_size;
2012 unsigned sx_max_export_smx_size;
2013 unsigned sq_num_cf_insts;
2014 unsigned sx_num_of_sets;
2015 unsigned sc_prim_fifo_size;
2016 unsigned sc_hiz_tile_fifo_size;
2017 unsigned sc_earlyz_tile_fifo_size;
2018 unsigned tiling_nbanks;
2019 unsigned tiling_npipes;
2020 unsigned tiling_group_size;
e7aeeba6 2021 unsigned tile_config;
e55b9422 2022 unsigned backend_map;
65fcf668 2023 unsigned active_simds;
32fcdbf4
AD		 2024};
2025
fecf1d07
AD		 2026struct cayman_asic {
2027 unsigned max_shader_engines;
2028 unsigned max_pipes_per_simd;
2029 unsigned max_tile_pipes;
2030 unsigned max_simds_per_se;
2031 unsigned max_backends_per_se;
2032 unsigned max_texture_channel_caches;
2033 unsigned max_gprs;
2034 unsigned max_threads;
2035 unsigned max_gs_threads;
2036 unsigned max_stack_entries;
2037 unsigned sx_num_of_sets;
2038 unsigned sx_max_export_size;
2039 unsigned sx_max_export_pos_size;
2040 unsigned sx_max_export_smx_size;
2041 unsigned max_hw_contexts;
2042 unsigned sq_num_cf_insts;
2043 unsigned sc_prim_fifo_size;
2044 unsigned sc_hiz_tile_fifo_size;
2045 unsigned sc_earlyz_tile_fifo_size;
2046
2047 unsigned num_shader_engines;
2048 unsigned num_shader_pipes_per_simd;
2049 unsigned num_tile_pipes;
2050 unsigned num_simds_per_se;
2051 unsigned num_backends_per_se;
2052 unsigned backend_disable_mask_per_asic;
2053 unsigned backend_map;
2054 unsigned num_texture_channel_caches;
2055 unsigned mem_max_burst_length_bytes;
2056 unsigned mem_row_size_in_kb;
2057 unsigned shader_engine_tile_size;
2058 unsigned num_gpus;
2059 unsigned multi_gpu_tile_size;
2060
2061 unsigned tile_config;
65fcf668 2062 unsigned active_simds;
fecf1d07
AD		 2063};
2064
0a96d72b
AD		 2065struct si_asic {
2066 unsigned max_shader_engines;
0a96d72b 2067 unsigned max_tile_pipes;
1a8ca750
AD		 2068 unsigned max_cu_per_sh;
2069 unsigned max_sh_per_se;
0a96d72b
AD		 2070 unsigned max_backends_per_se;
2071 unsigned max_texture_channel_caches;
2072 unsigned max_gprs;
2073 unsigned max_gs_threads;
2074 unsigned max_hw_contexts;
2075 unsigned sc_prim_fifo_size_frontend;
2076 unsigned sc_prim_fifo_size_backend;
2077 unsigned sc_hiz_tile_fifo_size;
2078 unsigned sc_earlyz_tile_fifo_size;
2079
0a96d72b 2080 unsigned num_tile_pipes;
439a1cff 2081 unsigned backend_enable_mask;
0a96d72b
AD		 2082 unsigned backend_disable_mask_per_asic;
2083 unsigned backend_map;
2084 unsigned num_texture_channel_caches;
2085 unsigned mem_max_burst_length_bytes;
2086 unsigned mem_row_size_in_kb;
2087 unsigned shader_engine_tile_size;
2088 unsigned num_gpus;
2089 unsigned multi_gpu_tile_size;
2090
2091 unsigned tile_config;
64d7b8be 2092 uint32_t tile_mode_array[32];
65fcf668 2093 uint32_t active_cus;
0a96d72b
AD		 2094};
2095
8cc1a532
AD		 2096struct cik_asic {
2097 unsigned max_shader_engines;
2098 unsigned max_tile_pipes;
2099 unsigned max_cu_per_sh;
2100 unsigned max_sh_per_se;
2101 unsigned max_backends_per_se;
2102 unsigned max_texture_channel_caches;
2103 unsigned max_gprs;
2104 unsigned max_gs_threads;
2105 unsigned max_hw_contexts;
2106 unsigned sc_prim_fifo_size_frontend;
2107 unsigned sc_prim_fifo_size_backend;
2108 unsigned sc_hiz_tile_fifo_size;
2109 unsigned sc_earlyz_tile_fifo_size;
2110
2111 unsigned num_tile_pipes;
439a1cff 2112 unsigned backend_enable_mask;
8cc1a532
AD		 2113 unsigned backend_disable_mask_per_asic;
2114 unsigned backend_map;
2115 unsigned num_texture_channel_caches;
2116 unsigned mem_max_burst_length_bytes;
2117 unsigned mem_row_size_in_kb;
2118 unsigned shader_engine_tile_size;
2119 unsigned num_gpus;
2120 unsigned multi_gpu_tile_size;
2121
2122 unsigned tile_config;
39aee490 2123 uint32_t tile_mode_array[32];
32f79a8a 2124 uint32_t macrotile_mode_array[16];
65fcf668 2125 uint32_t active_cus;
8cc1a532
AD		 2126};
2127
068a117c
JG		 2128union radeon_asic_config {
2129 struct r300_asic r300;
551ebd83 2130 struct r100_asic r100;
3ce0a23d
JG		 2131 struct r600_asic r600;
2132 struct rv770_asic rv770;
32fcdbf4 2133 struct evergreen_asic evergreen;
fecf1d07 2134 struct cayman_asic cayman;
0a96d72b 2135 struct si_asic si;
8cc1a532 2136 struct cik_asic cik;
068a117c
JG		 2137};
2138
0a10c851
DV		 2139/*
2140 * asic initizalization from radeon_asic.c
2141 */
2142void radeon_agp_disable(struct radeon_device *rdev);
2143int radeon_asic_init(struct radeon_device *rdev);
2144
771fe6b9
JG		 2145
2146/*
2147 * IOCTL.
2148 */
2149int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2150 struct drm_file *filp);
2151int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2152 struct drm_file *filp);
f72a113a
CK		 2153int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2154 struct drm_file *filp);
771fe6b9
JG		 2155int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2156 struct drm_file *file_priv);
2157int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2158 struct drm_file *file_priv);
2159int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2160 struct drm_file *file_priv);
2161int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2162 struct drm_file *file_priv);
2163int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2164 struct drm_file *filp);
2165int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2166 struct drm_file *filp);
2167int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2168 struct drm_file *filp);
2169int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2170 struct drm_file *filp);
721604a1
JG		 2171int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2172 struct drm_file *filp);
bda72d58
MO		 2173int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2174 struct drm_file *filp);
771fe6b9 2175int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 2176int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2177 struct drm_file *filp);
2178int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2179 struct drm_file *filp);
771fe6b9 2180
16cdf04d
AD		 2181/* VRAM scratch page for HDP bug, default vram page */
2182struct r600_vram_scratch {
87cbf8f2
AD		 2183 struct radeon_bo *robj;
2184 volatile uint32_t *ptr;
16cdf04d 2185 u64 gpu_addr;
87cbf8f2 2186};
771fe6b9 2187
fd64ca8a
LT		 2188/*
2189 * ACPI
2190 */
2191struct radeon_atif_notification_cfg {
2192 bool enabled;
2193 int command_code;
2194};
2195
2196struct radeon_atif_notifications {
2197 bool display_switch;
2198 bool expansion_mode_change;
2199 bool thermal_state;
2200 bool forced_power_state;
2201 bool system_power_state;
2202 bool display_conf_change;
2203 bool px_gfx_switch;
2204 bool brightness_change;
2205 bool dgpu_display_event;
2206};
2207
2208struct radeon_atif_functions {
2209 bool system_params;
2210 bool sbios_requests;
2211 bool select_active_disp;
2212 bool lid_state;
2213 bool get_tv_standard;
2214 bool set_tv_standard;
2215 bool get_panel_expansion_mode;
2216 bool set_panel_expansion_mode;
2217 bool temperature_change;
2218 bool graphics_device_types;
2219};
2220
2221struct radeon_atif {
2222 struct radeon_atif_notifications notifications;
2223 struct radeon_atif_functions functions;
2224 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2225 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2226};
7a1619b9 2227
e3a15920
AD		 2228struct radeon_atcs_functions {
2229 bool get_ext_state;
2230 bool pcie_perf_req;
2231 bool pcie_dev_rdy;
2232 bool pcie_bus_width;
2233};
2234
2235struct radeon_atcs {
2236 struct radeon_atcs_functions functions;
2237};
2238
771fe6b9
JG		 2239/*
2240 * Core structure, functions and helpers.
2241 */
2242typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2243typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2244
2245struct radeon_device {
9f022ddf 2246 struct device *dev;
771fe6b9
JG		 2247 struct drm_device *ddev;
2248 struct pci_dev *pdev;
dee53e7f 2249 struct rw_semaphore exclusive_lock;
771fe6b9 2250 /* ASIC */
068a117c 2251 union radeon_asic_config config;
771fe6b9
JG		 2252 enum radeon_family family;
2253 unsigned long flags;
2254 int usec_timeout;
2255 enum radeon_pll_errata pll_errata;
2256 int num_gb_pipes;
f779b3e5 2257 int num_z_pipes;
771fe6b9
JG		 2258 int disp_priority;
2259 /* BIOS */
2260 uint8_t *bios;
2261 bool is_atom_bios;
2262 uint16_t bios_header_start;
4c788679 2263 struct radeon_bo *stollen_vga_memory;
771fe6b9 2264 /* Register mmio */
4c9bc75c
DA		 2265 resource_size_t rmmio_base;
2266 resource_size_t rmmio_size;
2c385151
DV		 2267 /* protects concurrent MM_INDEX/DATA based register access */
2268 spinlock_t mmio_idx_lock;
fe78118c
AD		 2269 /* protects concurrent SMC based register access */
2270 spinlock_t smc_idx_lock;
0a5b7b0b
AD		 2271 /* protects concurrent PLL register access */
2272 spinlock_t pll_idx_lock;
2273 /* protects concurrent MC register access */
2274 spinlock_t mc_idx_lock;
2275 /* protects concurrent PCIE register access */
2276 spinlock_t pcie_idx_lock;
2277 /* protects concurrent PCIE_PORT register access */
2278 spinlock_t pciep_idx_lock;
2279 /* protects concurrent PIF register access */
2280 spinlock_t pif_idx_lock;
2281 /* protects concurrent CG register access */
2282 spinlock_t cg_idx_lock;
2283 /* protects concurrent UVD register access */
2284 spinlock_t uvd_idx_lock;
2285 /* protects concurrent RCU register access */
2286 spinlock_t rcu_idx_lock;
2287 /* protects concurrent DIDT register access */
2288 spinlock_t didt_idx_lock;
2289 /* protects concurrent ENDPOINT (audio) register access */
2290 spinlock_t end_idx_lock;
a0533fbf 2291 void __iomem *rmmio;
771fe6b9
JG		 2292 radeon_rreg_t mc_rreg;
2293 radeon_wreg_t mc_wreg;
2294 radeon_rreg_t pll_rreg;
2295 radeon_wreg_t pll_wreg;
de1b2898 2296 uint32_t pcie_reg_mask;
771fe6b9
JG		 2297 radeon_rreg_t pciep_rreg;
2298 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2299 /* io port */
2300 void __iomem *rio_mem;
2301 resource_size_t rio_mem_size;
771fe6b9
JG		 2302 struct radeon_clock clock;
2303 struct radeon_mc mc;
2304 struct radeon_gart gart;
2305 struct radeon_mode_info mode_info;
2306 struct radeon_scratch scratch;
75efdee1 2307 struct radeon_doorbell doorbell;
771fe6b9 2308 struct radeon_mman mman;
7465280c 2309 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2310 wait_queue_head_t fence_queue;
d6999bc7 2311 struct mutex ring_lock;
e32eb50d 2312 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2313 bool ib_pool_ready;
2314 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2315 struct radeon_irq irq;
2316 struct radeon_asic *asic;
2317 struct radeon_gem gem;
c93bb85b 2318 struct radeon_pm pm;
f2ba57b5 2319 struct radeon_uvd uvd;
d93f7937 2320 struct radeon_vce vce;
f657c2a7 2321 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2322 struct radeon_wb wb;
3ce0a23d 2323 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 2324 bool shutdown;
2325 bool suspend;
ad49f501 2326 bool need_dma32;
733289c2 2327 bool accel_working;
a0a53aa8 2328 bool fastfb_working; /* IGP feature*/
f9eaf9ae 2329 bool needs_reset;
e024e110 2330 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2331 const struct firmware *me_fw; /* all family ME firmware */
2332 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2333 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2334 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2335 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2336 const struct firmware *mec_fw; /* CIK MEC firmware */
f2c6b0f4 2337 const struct firmware *mec2_fw; /* KV MEC2 firmware */
21a93e13 2338 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2339 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2340 const struct firmware *uvd_fw; /* UVD firmware */
d93f7937 2341 const struct firmware *vce_fw; /* VCE firmware */
629bd33c 2342 bool new_fw;
16cdf04d 2343 struct r600_vram_scratch vram_scratch;
3e5cb98d 2344 int msi_enabled; /* msi enabled */
d8f60cfc 2345 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2346 struct radeon_rlc rlc;
963e81f9 2347 struct radeon_mec mec;
d4877cf2 2348 struct work_struct hotplug_work;
f122c610 2349 struct work_struct audio_work;
8f61b34c 2350 struct work_struct reset_work;
18917b60 2351 int num_crtc; /* number of crtcs */
40bacf16 2352 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
948bee3f 2353 bool has_uvd;
b530602f 2354 struct r600_audio audio; /* audio stuff */
ce8f5370 2355 struct notifier_block acpi_nb;
9eba4a93 2356 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2357 struct drm_file *hyperz_filp;
9eba4a93 2358 struct drm_file *cmask_filp;
f376b94f
AD		 2359 /* i2c buses */
2360 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2361 /* debugfs */
2362 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2363 unsigned debugfs_count;
721604a1
JG		 2364 /* virtual memory */
2365 struct radeon_vm_manager vm_manager;
6759a0a7 2366 struct mutex gpu_clock_mutex;
67e8e3f9
MO		 2367 /* memory stats */
2368 atomic64_t vram_usage;
2369 atomic64_t gtt_usage;
2370 atomic64_t num_bytes_moved;
fd64ca8a
LT		 2371 /* ACPI interface */
2372 struct radeon_atif atif;
e3a15920 2373 struct radeon_atcs atcs;
f61d5b46
AD		 2374 /* srbm instance registers */
2375 struct mutex srbm_mutex;
64d8a728
AD		 2376 /* clock, powergating flags */
2377 u32 cg_flags;
2378 u32 pg_flags;
10ebc0bc
DA		 2379
2380 struct dev_pm_domain vga_pm_domain;
2381 bool have_disp_power_ref;
4807c5a8 2382 u32 px_quirk_flags;
71ecc97e
AD		 2383
2384 /* tracking pinned memory */
2385 u64 vram_pin_size;
2386 u64 gart_pin_size;
341cb9e4
CK		 2387
2388 struct mutex mn_lock;
2389 DECLARE_HASHTABLE(mn_hash, 7);
771fe6b9
JG		 2390};
2391
90c4cde9 2392bool radeon_is_px(struct drm_device *dev);
771fe6b9
JG		 2393int radeon_device_init(struct radeon_device *rdev,
2394 struct drm_device *ddev,
2395 struct pci_dev *pdev,
2396 uint32_t flags);
2397void radeon_device_fini(struct radeon_device *rdev);
2398int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2399
59bc1d89
LK		 2400#define RADEON_MIN_MMIO_SIZE 0x10000
2401
2402static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2403 bool always_indirect)
2404{
2405 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2406 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2407 return readl(((void __iomem *)rdev->rmmio) + reg);
2408 else {
2409 unsigned long flags;
2410 uint32_t ret;
2411
2412 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2413 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2414 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2415 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2416
2417 return ret;
2418 }
2419}
2420
2421static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2422 bool always_indirect)
2423{
2424 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2425 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2426 else {
2427 unsigned long flags;
2428
2429 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
2430 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2431 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2432 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
2433 }
2434}
2435
6fcbef7a
AK		 2436u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2437void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2438
d5754ab8
AL		 2439u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2440void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
75efdee1 2441
4c788679
JG		 2442/*
2443 * Cast helper
2444 */
2445#define to_radeon_fence(p) ((struct radeon_fence *)(p))
771fe6b9
JG		 2446
2447/*
2448 * Registers read & write functions.
2449 */
a0533fbf
BH		 2450#define RREG8(reg) readb((rdev->rmmio) + (reg))
2451#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2452#define RREG16(reg) readw((rdev->rmmio) + (reg))
2453#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2454#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2455#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2456#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2457#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2458#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2459#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2460#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2461#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2462#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2463#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2464#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2465#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2466#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2467#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2468#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2469#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2470#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2471#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2472#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2473#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2474#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2475#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2476#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2477#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2478#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2479#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2480#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2481#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2482#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2483#define WREG32_P(reg, val, mask) \
2484 do { \
2485 uint32_t tmp_ = RREG32(reg); \
2486 tmp_ &= (mask); \
2487 tmp_ |= ((val) & ~(mask)); \
2488 WREG32(reg, tmp_); \
2489 } while (0)
d5169fc4 2490#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2491#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2492#define WREG32_PLL_P(reg, val, mask) \
2493 do { \
2494 uint32_t tmp_ = RREG32_PLL(reg); \
2495 tmp_ &= (mask); \
2496 tmp_ |= ((val) & ~(mask)); \
2497 WREG32_PLL(reg, tmp_); \
2498 } while (0)
2ef9bdfe 2499#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2500#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2501#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2502
d5754ab8
AL		 2503#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2504#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
75efdee1 2505
de1b2898
DA		 2506/*
2507 * Indirect registers accessor
2508 */
2509static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2510{
0a5b7b0b 2511 unsigned long flags;
de1b2898
DA		 2512 uint32_t r;
2513
0a5b7b0b 2514 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2515 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2516 r = RREG32(RADEON_PCIE_DATA);
0a5b7b0b 2517 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2518 return r;
2519}
2520
2521static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2522{
0a5b7b0b
AD		 2523 unsigned long flags;
2524
2525 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2526 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2527 WREG32(RADEON_PCIE_DATA, (v));
0a5b7b0b 2528 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
de1b2898
DA		 2529}
2530
1d5d0c34
AD		 2531static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2532{
fe78118c 2533 unsigned long flags;
1d5d0c34
AD		 2534 u32 r;
2535
fe78118c 2536 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2537 WREG32(TN_SMC_IND_INDEX_0, (reg));
2538 r = RREG32(TN_SMC_IND_DATA_0);
fe78118c 2539 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2540 return r;
2541}
2542
2543static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2544{
fe78118c
AD		 2545 unsigned long flags;
2546
2547 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2548 WREG32(TN_SMC_IND_INDEX_0, (reg));
2549 WREG32(TN_SMC_IND_DATA_0, (v));
fe78118c 2550 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
1d5d0c34
AD		 2551}
2552
ff82bbc4
AD		 2553static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2554{
0a5b7b0b 2555 unsigned long flags;
ff82bbc4
AD		 2556 u32 r;
2557
0a5b7b0b 2558 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2559 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2560 r = RREG32(R600_RCU_DATA);
0a5b7b0b 2561 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2562 return r;
2563}
2564
2565static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2566{
0a5b7b0b
AD		 2567 unsigned long flags;
2568
2569 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2570 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2571 WREG32(R600_RCU_DATA, (v));
0a5b7b0b 2572 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
ff82bbc4
AD		 2573}
2574
46f9564a
AD		 2575static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2576{
0a5b7b0b 2577 unsigned long flags;
46f9564a
AD		 2578 u32 r;
2579
0a5b7b0b 2580 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2581 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2582 r = RREG32(EVERGREEN_CG_IND_DATA);
0a5b7b0b 2583 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2584 return r;
2585}
2586
2587static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2588{
0a5b7b0b
AD		 2589 unsigned long flags;
2590
2591 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2592 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2593 WREG32(EVERGREEN_CG_IND_DATA, (v));
0a5b7b0b 2594 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
46f9564a
AD		 2595}
2596
792edd69
AD		 2597static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2598{
0a5b7b0b 2599 unsigned long flags;
792edd69
AD		 2600 u32 r;
2601
0a5b7b0b 2602 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2603 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2604 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
0a5b7b0b 2605 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2606 return r;
2607}
2608
2609static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2610{
0a5b7b0b
AD		 2611 unsigned long flags;
2612
2613 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2614 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2615 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
0a5b7b0b 2616 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2617}
2618
2619static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2620{
0a5b7b0b 2621 unsigned long flags;
792edd69
AD		 2622 u32 r;
2623
0a5b7b0b 2624 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2625 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2626 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
0a5b7b0b 2627 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2628 return r;
2629}
2630
2631static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2632{
0a5b7b0b
AD		 2633 unsigned long flags;
2634
2635 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
792edd69
AD		 2636 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2637 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
0a5b7b0b 2638 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
792edd69
AD		 2639}
2640
93656cdd
AD		 2641static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2642{
0a5b7b0b 2643 unsigned long flags;
93656cdd
AD		 2644 u32 r;
2645
0a5b7b0b 2646 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2647 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2648 r = RREG32(R600_UVD_CTX_DATA);
0a5b7b0b 2649 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2650 return r;
2651}
2652
2653static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2654{
0a5b7b0b
AD		 2655 unsigned long flags;
2656
2657 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2658 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2659 WREG32(R600_UVD_CTX_DATA, (v));
0a5b7b0b 2660 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
93656cdd
AD		 2661}
2662
1d58234d
AD		 2663
2664static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2665{
0a5b7b0b 2666 unsigned long flags;
1d58234d
AD		 2667 u32 r;
2668
0a5b7b0b 2669 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2670 WREG32(CIK_DIDT_IND_INDEX, (reg));
2671 r = RREG32(CIK_DIDT_IND_DATA);
0a5b7b0b 2672 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2673 return r;
2674}
2675
2676static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2677{
0a5b7b0b
AD		 2678 unsigned long flags;
2679
2680 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2681 WREG32(CIK_DIDT_IND_INDEX, (reg));
2682 WREG32(CIK_DIDT_IND_DATA, (v));
0a5b7b0b 2683 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
1d58234d
AD		 2684}
2685
771fe6b9
JG		 2686void r100_pll_errata_after_index(struct radeon_device *rdev);
2687
2688
2689/*
2690 * ASICs helpers.
2691 */
b995e433
DA		 2692#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2693 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2694#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2695 (rdev->family == CHIP_RV200) || \
2696 (rdev->family == CHIP_RS100) || \
2697 (rdev->family == CHIP_RS200) || \
2698 (rdev->family == CHIP_RV250) || \
2699 (rdev->family == CHIP_RV280) || \
2700 (rdev->family == CHIP_RS300))
2701#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2702 (rdev->family == CHIP_RV350) || \
2703 (rdev->family == CHIP_R350) || \
2704 (rdev->family == CHIP_RV380) || \
2705 (rdev->family == CHIP_R420) || \
2706 (rdev->family == CHIP_R423) || \
2707 (rdev->family == CHIP_RV410) || \
2708 (rdev->family == CHIP_RS400) || \
2709 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2710#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2711 (rdev->ddev->pdev->device == 0x9443) || \
2712 (rdev->ddev->pdev->device == 0x944B) || \
2713 (rdev->ddev->pdev->device == 0x9506) || \
2714 (rdev->ddev->pdev->device == 0x9509) || \
2715 (rdev->ddev->pdev->device == 0x950F) || \
2716 (rdev->ddev->pdev->device == 0x689C) || \
2717 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2718#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2719#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2720 (rdev->family == CHIP_RS690) || \
2721 (rdev->family == CHIP_RS740) || \
2722 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2723#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2724#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2725#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2726#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2727 (rdev->flags & RADEON_IS_IGP))
1fe18305 2728#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2729#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2730#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2731 (rdev->flags & RADEON_IS_IGP))
624d3524 2732#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2733#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2734#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
be0949f5
AD		 2735#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2736#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
89d2618d
AD		 2737#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2738 (rdev->family == CHIP_MULLINS))
771fe6b9 2739
dc50ba7f
AD		 2740#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2741 (rdev->ddev->pdev->device == 0x6850) || \
2742 (rdev->ddev->pdev->device == 0x6858) || \
2743 (rdev->ddev->pdev->device == 0x6859) || \
2744 (rdev->ddev->pdev->device == 0x6840) || \
2745 (rdev->ddev->pdev->device == 0x6841) || \
2746 (rdev->ddev->pdev->device == 0x6842) || \
2747 (rdev->ddev->pdev->device == 0x6843))
2748
771fe6b9
JG		 2749/*
2750 * BIOS helpers.
2751 */
2752#define RBIOS8(i) (rdev->bios[i])
2753#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2754#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2755
2756int radeon_combios_init(struct radeon_device *rdev);
2757void radeon_combios_fini(struct radeon_device *rdev);
2758int radeon_atombios_init(struct radeon_device *rdev);
2759void radeon_atombios_fini(struct radeon_device *rdev);
2760
2761
2762/*
2763 * RING helpers.
2764 */
ce580fab 2765#if DRM_DEBUG_CODE == 0
e32eb50d 2766static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2767{
e32eb50d
CK		 2768 ring->ring[ring->wptr++] = v;
2769 ring->wptr &= ring->ptr_mask;
2770 ring->count_dw--;
2771 ring->ring_free_dw--;
771fe6b9 2772}
ce580fab
AK		 2773#else
2774/* With debugging this is just too big to inline */
e32eb50d 2775void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
ce580fab 2776#endif
771fe6b9
JG		 2777
2778/*
2779 * ASICs macro.
2780 */
068a117c 2781#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2782#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2783#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2784#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2785#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2786#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
a2d07b74 2787#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
c5b3b850 2788#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
77497f27 2789#define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f))
05b07147
CK		 2790#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2791#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
03f62abd
CK		 2792#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2793#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2794#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2795#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
76a0df85
CK		 2796#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2797#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2798#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2799#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2800#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2801#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2802#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2803#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2804#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2805#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2806#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2807#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2808#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2809#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2810#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2811#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2812#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2813#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2814#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
27cd7769
AD		 2815#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2816#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2817#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2818#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2819#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2820#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2821#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2822#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2823#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2824#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2825#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2826#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2827#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2828#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
b59b7333 2829#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
6bd1c385 2830#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2831#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2832#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2833#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2834#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2835#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2836#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2837#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2838#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2839#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2840#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2841#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2842#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2843#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
69b62ad8 2844#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
157fa14d 2845#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
69b62ad8
AD		 2846#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2847#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2848#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2849#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
da321c8a
AD		 2850#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2851#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2852#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
914a8987 2853#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
da321c8a 2854#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2855#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2856#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2857#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2858#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2859#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2860#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2861#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2862#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2863#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2864#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2865#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2866#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
1c71bda0 2867#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
771fe6b9 2868
6cf8a3f5 2869/* Common functions */
700a0cc0 2870/* AGP */
90aca4d2 2871extern int radeon_gpu_reset(struct radeon_device *rdev);
1a0041b8 2872extern void radeon_pci_config_reset(struct radeon_device *rdev);
410a3418 2873extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2874extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2875extern int radeon_modeset_init(struct radeon_device *rdev);
2876extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2877extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2878extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2879extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2880extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2881extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2882extern void radeon_wb_fini(struct radeon_device *rdev);
2883extern int radeon_wb_init(struct radeon_device *rdev);
2884extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2885extern void radeon_surface_init(struct radeon_device *rdev);
2886extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2887extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2888extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2889extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2890extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
f72a113a
CK		 2891extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2892 uint32_t flags);
2893extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2894extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
d594e46a
JG		 2895extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2896extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
10ebc0bc
DA		 2897extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2898extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
53595338 2899extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2900extern void radeon_program_register_sequence(struct radeon_device *rdev,
2901 const u32 *registers,
2902 const u32 array_size);
6cf8a3f5 2903
721604a1
JG		 2904/*
2905 * vm
2906 */
2907int radeon_vm_manager_init(struct radeon_device *rdev);
2908void radeon_vm_manager_fini(struct radeon_device *rdev);
6d2f2944 2909int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2910void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
df0af440
CK		 2911struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2912 struct radeon_vm *vm,
2913 struct list_head *head);
ee60e29f
CK		 2914struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2915 struct radeon_vm *vm, int ring);
fa688343
CK		 2916void radeon_vm_flush(struct radeon_device *rdev,
2917 struct radeon_vm *vm,
2918 int ring);
ee60e29f
CK		 2919void radeon_vm_fence(struct radeon_device *rdev,
2920 struct radeon_vm *vm,
2921 struct radeon_fence *fence);
dce34bfd 2922uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
6d2f2944
CK		 2923int radeon_vm_update_page_directory(struct radeon_device *rdev,
2924 struct radeon_vm *vm);
036bf46a
CK		 2925int radeon_vm_clear_freed(struct radeon_device *rdev,
2926 struct radeon_vm *vm);
e31ad969
CK		 2927int radeon_vm_clear_invalids(struct radeon_device *rdev,
2928 struct radeon_vm *vm);
9c57a6bd 2929int radeon_vm_bo_update(struct radeon_device *rdev,
036bf46a 2930 struct radeon_bo_va *bo_va,
9c57a6bd 2931 struct ttm_mem_reg *mem);
721604a1
JG		 2932void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2933 struct radeon_bo *bo);
421ca7ab
CK		 2934struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2935 struct radeon_bo *bo);
e971bd5e
CK		 2936struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2937 struct radeon_vm *vm,
2938 struct radeon_bo *bo);
2939int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2940 struct radeon_bo_va *bo_va,
2941 uint64_t offset,
2942 uint32_t flags);
036bf46a
CK		 2943void radeon_vm_bo_rmv(struct radeon_device *rdev,
2944 struct radeon_bo_va *bo_va);
721604a1 2945
f122c610
AD		 2946/* audio */
2947void r600_audio_update_hdmi(struct work_struct *work);
b530602f
AD		 2948struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2949struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
832eafaf
AD		 2950void r600_audio_enable(struct radeon_device *rdev,
2951 struct r600_audio_pin *pin,
2952 bool enable);
2953void dce6_audio_enable(struct radeon_device *rdev,
2954 struct r600_audio_pin *pin,
2955 bool enable);
721604a1 2956
16cdf04d
AD		 2957/*
2958 * R600 vram scratch functions
2959 */
2960int r600_vram_scratch_init(struct radeon_device *rdev);
2961void r600_vram_scratch_fini(struct radeon_device *rdev);
2962
285484e2
JG		 2963/*
2964 * r600 cs checking helper
2965 */
2966unsigned r600_mip_minify(unsigned size, unsigned level);
2967bool r600_fmt_is_valid_color(u32 format);
2968bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2969int r600_fmt_get_blocksize(u32 format);
2970int r600_fmt_get_nblocksx(u32 format, u32 w);
2971int r600_fmt_get_nblocksy(u32 format, u32 h);
2972
3574dda4
DV		 2973/*
2974 * r600 functions used by radeon_encoder.c
2975 */
1b688d08
RM		 2976struct radeon_hdmi_acr {
2977 u32 clock;
2978
2979 int n_32khz;
2980 int cts_32khz;
2981
2982 int n_44_1khz;
2983 int cts_44_1khz;
2984
2985 int n_48khz;
2986 int cts_48khz;
2987
2988};
2989
e55d3e6c
RM		 2990extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2991
416a2bd2
AD		 2992extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2993 u32 tiling_pipe_num,
2994 u32 max_rb_num,
2995 u32 total_max_rb_num,
2996 u32 enabled_rb_mask);
fe251e2f 2997
e55d3e6c
RM		 2998/*
2999 * evergreen functions used by radeon_encoder.c
3000 */
3001
0af62b01 3002extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 3003extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 3004
c4917074
AD		 3005/* radeon_acpi.c */
3006#if defined(CONFIG_ACPI)
3007extern int radeon_acpi_init(struct radeon_device *rdev);
3008extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 3009extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
3010extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 3011 u8 perf_req, bool advertise);
dc50ba7f 3012extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 3013#else
3014static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
3015static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
3016#endif
d7a2952f 3017
c38f34b5
IH		 3018int radeon_cs_packet_parse(struct radeon_cs_parser *p,
3019 struct radeon_cs_packet *pkt,
3020 unsigned idx);
9ffb7a6d 3021bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 3022void radeon_cs_dump_packet(struct radeon_cs_parser *p,
3023 struct radeon_cs_packet *pkt);
e9716993
IH		 3024int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
3025 struct radeon_cs_reloc **cs_reloc,
3026 int nomm);
40592a17
IH		 3027int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
3028 uint32_t *vline_start_end,
3029 uint32_t *vline_status);
c38f34b5 3030
4c788679
JG		 3031#include "radeon_object.h"
3032
771fe6b9 3033#endif
Linux kernel - Deliverables
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