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drm: fix radeon DRM warnings when !CONFIG_DEBUG_FS
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31#include "radeon_object.h"
32
33/* TODO: Here are things that needs to be done :
34 * - surface allocator & initializer : (bit like scratch reg) should
35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
36 * related to surface
37 * - WB : write back stuff (do it bit like scratch reg things)
38 * - Vblank : look at Jesse's rework and what we should do
39 * - r600/r700: gart & cp
40 * - cs : clean cs ioctl use bitmap & things like that.
41 * - power management stuff
42 * - Barrier in gart code
43 * - Unmappabled vram ?
44 * - TESTING, TESTING, TESTING
45 */
46
47#include <asm/atomic.h>
48#include <linux/wait.h>
49#include <linux/list.h>
50#include <linux/kref.h>
51
c2142715 52#include "radeon_family.h"
771fe6b9
JG		 53#include "radeon_mode.h"
54#include "radeon_reg.h"
771fe6b9
JG		 55
56/*
57 * Modules parameters.
58 */
59extern int radeon_no_wb;
60extern int radeon_modeset;
61extern int radeon_dynclks;
62extern int radeon_r4xx_atom;
63extern int radeon_agpmode;
64extern int radeon_vram_limit;
65extern int radeon_gart_size;
66extern int radeon_benchmarking;
ecc0b326 67extern int radeon_testing;
771fe6b9 68extern int radeon_connector_table;
4ce001ab 69extern int radeon_tv;
771fe6b9
JG		 70
71/*
72 * Copy from radeon_drv.h so we don't have to include both and have conflicting
73 * symbol;
74 */
75#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
76#define RADEON_IB_POOL_SIZE 16
77#define RADEON_DEBUGFS_MAX_NUM_FILES 32
78#define RADEONFB_CONN_LIMIT 4
f657c2a7 79#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 80
771fe6b9
JG		 81/*
82 * Errata workarounds.
83 */
84enum radeon_pll_errata {
85 CHIP_ERRATA_R300_CG = 0x00000001,
86 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
87 CHIP_ERRATA_PLL_DELAY = 0x00000004
88};
89
90
91struct radeon_device;
92
93
94/*
95 * BIOS.
96 */
97bool radeon_get_bios(struct radeon_device *rdev);
98
3ce0a23d 99
771fe6b9 100/*
3ce0a23d 101 * Dummy page
771fe6b9 102 */
3ce0a23d
JG		 103struct radeon_dummy_page {
104 struct page *page;
105 dma_addr_t addr;
106};
107int radeon_dummy_page_init(struct radeon_device *rdev);
108void radeon_dummy_page_fini(struct radeon_device *rdev);
109
771fe6b9 110
3ce0a23d
JG		 111/*
112 * Clocks
113 */
771fe6b9
JG		 114struct radeon_clock {
115 struct radeon_pll p1pll;
116 struct radeon_pll p2pll;
117 struct radeon_pll spll;
118 struct radeon_pll mpll;
119 /* 10 Khz units */
120 uint32_t default_mclk;
121 uint32_t default_sclk;
122};
123
3ce0a23d 124
771fe6b9
JG		 125/*
126 * Fences.
127 */
128struct radeon_fence_driver {
129 uint32_t scratch_reg;
130 atomic_t seq;
131 uint32_t last_seq;
132 unsigned long count_timeout;
133 wait_queue_head_t queue;
134 rwlock_t lock;
135 struct list_head created;
136 struct list_head emited;
137 struct list_head signaled;
138};
139
140struct radeon_fence {
141 struct radeon_device *rdev;
142 struct kref kref;
143 struct list_head list;
144 /* protected by radeon_fence.lock */
145 uint32_t seq;
146 unsigned long timeout;
147 bool emited;
148 bool signaled;
149};
150
151int radeon_fence_driver_init(struct radeon_device *rdev);
152void radeon_fence_driver_fini(struct radeon_device *rdev);
153int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
154int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
155void radeon_fence_process(struct radeon_device *rdev);
156bool radeon_fence_signaled(struct radeon_fence *fence);
157int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
158int radeon_fence_wait_next(struct radeon_device *rdev);
159int radeon_fence_wait_last(struct radeon_device *rdev);
160struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
161void radeon_fence_unref(struct radeon_fence **fence);
162
e024e110
DA		 163/*
164 * Tiling registers
165 */
166struct radeon_surface_reg {
167 struct radeon_object *robj;
168};
169
170#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 171
172/*
173 * Radeon buffer.
174 */
175struct radeon_object;
176
177struct radeon_object_list {
178 struct list_head list;
179 struct radeon_object *robj;
180 uint64_t gpu_offset;
181 unsigned rdomain;
182 unsigned wdomain;
e024e110 183 uint32_t tiling_flags;
771fe6b9
JG		 184};
185
186int radeon_object_init(struct radeon_device *rdev);
187void radeon_object_fini(struct radeon_device *rdev);
188int radeon_object_create(struct radeon_device *rdev,
189 struct drm_gem_object *gobj,
190 unsigned long size,
191 bool kernel,
192 uint32_t domain,
193 bool interruptible,
194 struct radeon_object **robj_ptr);
195int radeon_object_kmap(struct radeon_object *robj, void **ptr);
196void radeon_object_kunmap(struct radeon_object *robj);
197void radeon_object_unref(struct radeon_object **robj);
198int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
199 uint64_t *gpu_addr);
200void radeon_object_unpin(struct radeon_object *robj);
201int radeon_object_wait(struct radeon_object *robj);
cefb87ef 202int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement);
771fe6b9
JG		 203int radeon_object_evict_vram(struct radeon_device *rdev);
204int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
205void radeon_object_force_delete(struct radeon_device *rdev);
206void radeon_object_list_add_object(struct radeon_object_list *lobj,
207 struct list_head *head);
208int radeon_object_list_validate(struct list_head *head, void *fence);
209void radeon_object_list_unvalidate(struct list_head *head);
210void radeon_object_list_clean(struct list_head *head);
211int radeon_object_fbdev_mmap(struct radeon_object *robj,
212 struct vm_area_struct *vma);
213unsigned long radeon_object_size(struct radeon_object *robj);
e024e110
DA		 214void radeon_object_clear_surface_reg(struct radeon_object *robj);
215int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
216 bool force_drop);
217void radeon_object_set_tiling_flags(struct radeon_object *robj,
218 uint32_t tiling_flags, uint32_t pitch);
219void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
220void radeon_bo_move_notify(struct ttm_buffer_object *bo,
221 struct ttm_mem_reg *mem);
222void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
771fe6b9
JG		 223/*
224 * GEM objects.
225 */
226struct radeon_gem {
227 struct list_head objects;
228};
229
230int radeon_gem_init(struct radeon_device *rdev);
231void radeon_gem_fini(struct radeon_device *rdev);
232int radeon_gem_object_create(struct radeon_device *rdev, int size,
233 int alignment, int initial_domain,
234 bool discardable, bool kernel,
235 bool interruptible,
236 struct drm_gem_object **obj);
237int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
238 uint64_t *gpu_addr);
239void radeon_gem_object_unpin(struct drm_gem_object *obj);
240
241
242/*
243 * GART structures, functions & helpers
244 */
245struct radeon_mc;
246
247struct radeon_gart_table_ram {
248 volatile uint32_t *ptr;
249};
250
251struct radeon_gart_table_vram {
252 struct radeon_object *robj;
253 volatile uint32_t *ptr;
254};
255
256union radeon_gart_table {
257 struct radeon_gart_table_ram ram;
258 struct radeon_gart_table_vram vram;
259};
260
261struct radeon_gart {
262 dma_addr_t table_addr;
263 unsigned num_gpu_pages;
264 unsigned num_cpu_pages;
265 unsigned table_size;
266 union radeon_gart_table table;
267 struct page **pages;
268 dma_addr_t *pages_addr;
269 bool ready;
270};
271
272int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
273void radeon_gart_table_ram_free(struct radeon_device *rdev);
274int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
275void radeon_gart_table_vram_free(struct radeon_device *rdev);
276int radeon_gart_init(struct radeon_device *rdev);
277void radeon_gart_fini(struct radeon_device *rdev);
278void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
279 int pages);
280int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
281 int pages, struct page **pagelist);
282
283
284/*
285 * GPU MC structures, functions & helpers
286 */
287struct radeon_mc {
288 resource_size_t aper_size;
289 resource_size_t aper_base;
290 resource_size_t agp_base;
7a50f01a
DA		 291 /* for some chips with <= 32MB we need to lie
292 * about vram size near mc fb location */
3ce0a23d
JG		 293 u64 mc_vram_size;
294 u64 gtt_location;
295 u64 gtt_size;
296 u64 gtt_start;
297 u64 gtt_end;
298 u64 vram_location;
299 u64 vram_start;
300 u64 vram_end;
771fe6b9 301 unsigned vram_width;
3ce0a23d 302 u64 real_vram_size;
771fe6b9
JG		 303 int vram_mtrr;
304 bool vram_is_ddr;
305};
306
307int radeon_mc_setup(struct radeon_device *rdev);
308
309
310/*
311 * GPU scratch registers structures, functions & helpers
312 */
313struct radeon_scratch {
314 unsigned num_reg;
315 bool free[32];
316 uint32_t reg[32];
317};
318
319int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
320void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
321
322
323/*
324 * IRQS.
325 */
326struct radeon_irq {
327 bool installed;
328 bool sw_int;
329 /* FIXME: use a define max crtc rather than hardcode it */
330 bool crtc_vblank_int[2];
331};
332
333int radeon_irq_kms_init(struct radeon_device *rdev);
334void radeon_irq_kms_fini(struct radeon_device *rdev);
335
336
337/*
338 * CP & ring.
339 */
340struct radeon_ib {
341 struct list_head list;
342 unsigned long idx;
343 uint64_t gpu_addr;
344 struct radeon_fence *fence;
513bcb46 345 uint32_t *ptr;
771fe6b9
JG		 346 uint32_t length_dw;
347};
348
ecb114a1
DA		 349/*
350 * locking -
351 * mutex protects scheduled_ibs, ready, alloc_bm
352 */
771fe6b9
JG		 353struct radeon_ib_pool {
354 struct mutex mutex;
355 struct radeon_object *robj;
356 struct list_head scheduled_ibs;
357 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
358 bool ready;
359 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
360};
361
362struct radeon_cp {
363 struct radeon_object *ring_obj;
364 volatile uint32_t *ring;
365 unsigned rptr;
366 unsigned wptr;
367 unsigned wptr_old;
368 unsigned ring_size;
369 unsigned ring_free_dw;
370 int count_dw;
371 uint64_t gpu_addr;
372 uint32_t align_mask;
373 uint32_t ptr_mask;
374 struct mutex mutex;
375 bool ready;
376};
377
3ce0a23d
JG		 378struct r600_blit {
379 struct radeon_object *shader_obj;
380 u64 shader_gpu_addr;
381 u32 vs_offset, ps_offset;
382 u32 state_offset;
383 u32 state_len;
384 u32 vb_used, vb_total;
385 struct radeon_ib *vb_ib;
386};
387
771fe6b9
JG		 388int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
389void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
390int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
391int radeon_ib_pool_init(struct radeon_device *rdev);
392void radeon_ib_pool_fini(struct radeon_device *rdev);
393int radeon_ib_test(struct radeon_device *rdev);
394/* Ring access between begin & end cannot sleep */
395void radeon_ring_free_size(struct radeon_device *rdev);
396int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
397void radeon_ring_unlock_commit(struct radeon_device *rdev);
398void radeon_ring_unlock_undo(struct radeon_device *rdev);
399int radeon_ring_test(struct radeon_device *rdev);
400int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
401void radeon_ring_fini(struct radeon_device *rdev);
402
403
404/*
405 * CS.
406 */
407struct radeon_cs_reloc {
408 struct drm_gem_object *gobj;
409 struct radeon_object *robj;
410 struct radeon_object_list lobj;
411 uint32_t handle;
412 uint32_t flags;
413};
414
415struct radeon_cs_chunk {
416 uint32_t chunk_id;
417 uint32_t length_dw;
513bcb46
DA		 418 int kpage_idx[2];
419 uint32_t *kpage[2];
771fe6b9 420 uint32_t *kdata;
513bcb46
DA		 421 void __user *user_ptr;
422 int last_copied_page;
423 int last_page_index;
771fe6b9
JG		 424};
425
426struct radeon_cs_parser {
427 struct radeon_device *rdev;
428 struct drm_file *filp;
429 /* chunks */
430 unsigned nchunks;
431 struct radeon_cs_chunk *chunks;
432 uint64_t *chunks_array;
433 /* IB */
434 unsigned idx;
435 /* relocations */
436 unsigned nrelocs;
437 struct radeon_cs_reloc *relocs;
438 struct radeon_cs_reloc **relocs_ptr;
439 struct list_head validated;
440 /* indices of various chunks */
441 int chunk_ib_idx;
442 int chunk_relocs_idx;
443 struct radeon_ib *ib;
444 void *track;
3ce0a23d 445 unsigned family;
513bcb46 446 int parser_error;
771fe6b9
JG		 447};
448
513bcb46
DA		 449extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
450extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
451
452
453static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
454{
455 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
456 u32 pg_idx, pg_offset;
457 u32 idx_value = 0;
458 int new_page;
459
460 pg_idx = (idx * 4) / PAGE_SIZE;
461 pg_offset = (idx * 4) % PAGE_SIZE;
462
463 if (ibc->kpage_idx[0] == pg_idx)
464 return ibc->kpage[0][pg_offset/4];
465 if (ibc->kpage_idx[1] == pg_idx)
466 return ibc->kpage[1][pg_offset/4];
467
468 new_page = radeon_cs_update_pages(p, pg_idx);
469 if (new_page < 0) {
470 p->parser_error = new_page;
471 return 0;
472 }
473
474 idx_value = ibc->kpage[new_page][pg_offset/4];
475 return idx_value;
476}
477
771fe6b9
JG		 478struct radeon_cs_packet {
479 unsigned idx;
480 unsigned type;
481 unsigned reg;
482 unsigned opcode;
483 int count;
484 unsigned one_reg_wr;
485};
486
487typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
488 struct radeon_cs_packet *pkt,
489 unsigned idx, unsigned reg);
490typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
491 struct radeon_cs_packet *pkt);
492
493
494/*
495 * AGP
496 */
497int radeon_agp_init(struct radeon_device *rdev);
498void radeon_agp_fini(struct radeon_device *rdev);
499
500
501/*
502 * Writeback
503 */
504struct radeon_wb {
505 struct radeon_object *wb_obj;
506 volatile uint32_t *wb;
507 uint64_t gpu_addr;
508};
509
c93bb85b
JG		 510/**
511 * struct radeon_pm - power management datas
512 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
513 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
514 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
515 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
516 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
517 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
518 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
519 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
520 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
521 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
522 * @needed_bandwidth: current bandwidth needs
523 *
524 * It keeps track of various data needed to take powermanagement decision.
525 * Bandwith need is used to determine minimun clock of the GPU and memory.
526 * Equation between gpu/memory clock and available bandwidth is hw dependent
527 * (type of memory, bus size, efficiency, ...)
528 */
529struct radeon_pm {
530 fixed20_12 max_bandwidth;
531 fixed20_12 igp_sideport_mclk;
532 fixed20_12 igp_system_mclk;
533 fixed20_12 igp_ht_link_clk;
534 fixed20_12 igp_ht_link_width;
535 fixed20_12 k8_bandwidth;
536 fixed20_12 sideport_bandwidth;
537 fixed20_12 ht_bandwidth;
538 fixed20_12 core_bandwidth;
539 fixed20_12 sclk;
540 fixed20_12 needed_bandwidth;
541};
542
771fe6b9
JG		 543
544/*
545 * Benchmarking
546 */
547void radeon_benchmark(struct radeon_device *rdev);
548
549
ecc0b326
MD		 550/*
551 * Testing
552 */
553void radeon_test_moves(struct radeon_device *rdev);
554
555
771fe6b9
JG		 556/*
557 * Debugfs
558 */
559int radeon_debugfs_add_files(struct radeon_device *rdev,
560 struct drm_info_list *files,
561 unsigned nfiles);
562int radeon_debugfs_fence_init(struct radeon_device *rdev);
563int r100_debugfs_rbbm_init(struct radeon_device *rdev);
564int r100_debugfs_cp_init(struct radeon_device *rdev);
565
566
567/*
568 * ASIC specific functions.
569 */
570struct radeon_asic {
068a117c 571 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 572 void (*fini)(struct radeon_device *rdev);
573 int (*resume)(struct radeon_device *rdev);
574 int (*suspend)(struct radeon_device *rdev);
771fe6b9
JG		 575 void (*errata)(struct radeon_device *rdev);
576 void (*vram_info)(struct radeon_device *rdev);
577 int (*gpu_reset)(struct radeon_device *rdev);
578 int (*mc_init)(struct radeon_device *rdev);
579 void (*mc_fini)(struct radeon_device *rdev);
580 int (*wb_init)(struct radeon_device *rdev);
581 void (*wb_fini)(struct radeon_device *rdev);
4aac0473
JG		 582 int (*gart_init)(struct radeon_device *rdev);
583 void (*gart_fini)(struct radeon_device *rdev);
771fe6b9
JG		 584 int (*gart_enable)(struct radeon_device *rdev);
585 void (*gart_disable)(struct radeon_device *rdev);
586 void (*gart_tlb_flush)(struct radeon_device *rdev);
587 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
588 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
589 void (*cp_fini)(struct radeon_device *rdev);
590 void (*cp_disable)(struct radeon_device *rdev);
3ce0a23d 591 void (*cp_commit)(struct radeon_device *rdev);
771fe6b9 592 void (*ring_start)(struct radeon_device *rdev);
3ce0a23d
JG		 593 int (*ring_test)(struct radeon_device *rdev);
594 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
595 int (*ib_test)(struct radeon_device *rdev);
771fe6b9
JG		 596 int (*irq_set)(struct radeon_device *rdev);
597 int (*irq_process)(struct radeon_device *rdev);
7ed220d7 598 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
771fe6b9
JG		 599 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
600 int (*cs_parse)(struct radeon_cs_parser *p);
601 int (*copy_blit)(struct radeon_device *rdev,
602 uint64_t src_offset,
603 uint64_t dst_offset,
604 unsigned num_pages,
605 struct radeon_fence *fence);
606 int (*copy_dma)(struct radeon_device *rdev,
607 uint64_t src_offset,
608 uint64_t dst_offset,
609 unsigned num_pages,
610 struct radeon_fence *fence);
611 int (*copy)(struct radeon_device *rdev,
612 uint64_t src_offset,
613 uint64_t dst_offset,
614 unsigned num_pages,
615 struct radeon_fence *fence);
616 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
617 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
618 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
619 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
e024e110
DA		 620 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
621 uint32_t tiling_flags, uint32_t pitch,
622 uint32_t offset, uint32_t obj_size);
623 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
c93bb85b 624 void (*bandwidth_update)(struct radeon_device *rdev);
771fe6b9
JG		 625};
626
21f9a437
JG		 627/*
628 * Asic structures
629 */
551ebd83
DA		 630struct r100_asic {
631 const unsigned *reg_safe_bm;
632 unsigned reg_safe_bm_size;
633};
634
21f9a437
JG		 635struct r300_asic {
636 const unsigned *reg_safe_bm;
637 unsigned reg_safe_bm_size;
638};
639
640struct r600_asic {
641 unsigned max_pipes;
642 unsigned max_tile_pipes;
643 unsigned max_simds;
644 unsigned max_backends;
645 unsigned max_gprs;
646 unsigned max_threads;
647 unsigned max_stack_entries;
648 unsigned max_hw_contexts;
649 unsigned max_gs_threads;
650 unsigned sx_max_export_size;
651 unsigned sx_max_export_pos_size;
652 unsigned sx_max_export_smx_size;
653 unsigned sq_num_cf_insts;
654};
655
656struct rv770_asic {
657 unsigned max_pipes;
658 unsigned max_tile_pipes;
659 unsigned max_simds;
660 unsigned max_backends;
661 unsigned max_gprs;
662 unsigned max_threads;
663 unsigned max_stack_entries;
664 unsigned max_hw_contexts;
665 unsigned max_gs_threads;
666 unsigned sx_max_export_size;
667 unsigned sx_max_export_pos_size;
668 unsigned sx_max_export_smx_size;
669 unsigned sq_num_cf_insts;
670 unsigned sx_num_of_sets;
671 unsigned sc_prim_fifo_size;
672 unsigned sc_hiz_tile_fifo_size;
673 unsigned sc_earlyz_tile_fifo_fize;
674};
675
068a117c
JG		 676union radeon_asic_config {
677 struct r300_asic r300;
551ebd83 678 struct r100_asic r100;
3ce0a23d
JG		 679 struct r600_asic r600;
680 struct rv770_asic rv770;
068a117c
JG		 681};
682
771fe6b9
JG		 683
684/*
685 * IOCTL.
686 */
687int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
688 struct drm_file *filp);
689int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
690 struct drm_file *filp);
691int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
692 struct drm_file *file_priv);
693int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
694 struct drm_file *file_priv);
695int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
696 struct drm_file *file_priv);
697int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
698 struct drm_file *file_priv);
699int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
700 struct drm_file *filp);
701int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
702 struct drm_file *filp);
703int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
704 struct drm_file *filp);
705int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
706 struct drm_file *filp);
707int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 708int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
709 struct drm_file *filp);
710int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
711 struct drm_file *filp);
771fe6b9
JG		 712
713
714/*
715 * Core structure, functions and helpers.
716 */
717typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
718typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
719
720struct radeon_device {
9f022ddf 721 struct device *dev;
771fe6b9
JG		 722 struct drm_device *ddev;
723 struct pci_dev *pdev;
724 /* ASIC */
068a117c 725 union radeon_asic_config config;
771fe6b9
JG		 726 enum radeon_family family;
727 unsigned long flags;
728 int usec_timeout;
729 enum radeon_pll_errata pll_errata;
730 int num_gb_pipes;
f779b3e5 731 int num_z_pipes;
771fe6b9
JG		 732 int disp_priority;
733 /* BIOS */
734 uint8_t *bios;
735 bool is_atom_bios;
736 uint16_t bios_header_start;
737 struct radeon_object *stollen_vga_memory;
738 struct fb_info *fbdev_info;
739 struct radeon_object *fbdev_robj;
740 struct radeon_framebuffer *fbdev_rfb;
741 /* Register mmio */
4c9bc75c
DA		 742 resource_size_t rmmio_base;
743 resource_size_t rmmio_size;
771fe6b9 744 void *rmmio;
771fe6b9
JG		 745 radeon_rreg_t mc_rreg;
746 radeon_wreg_t mc_wreg;
747 radeon_rreg_t pll_rreg;
748 radeon_wreg_t pll_wreg;
de1b2898 749 uint32_t pcie_reg_mask;
771fe6b9
JG		 750 radeon_rreg_t pciep_rreg;
751 radeon_wreg_t pciep_wreg;
752 struct radeon_clock clock;
753 struct radeon_mc mc;
754 struct radeon_gart gart;
755 struct radeon_mode_info mode_info;
756 struct radeon_scratch scratch;
757 struct radeon_mman mman;
758 struct radeon_fence_driver fence_drv;
759 struct radeon_cp cp;
760 struct radeon_ib_pool ib_pool;
761 struct radeon_irq irq;
762 struct radeon_asic *asic;
763 struct radeon_gem gem;
c93bb85b 764 struct radeon_pm pm;
f657c2a7 765 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9
JG		 766 struct mutex cs_mutex;
767 struct radeon_wb wb;
3ce0a23d 768 struct radeon_dummy_page dummy_page;
771fe6b9
JG		 769 bool gpu_lockup;
770 bool shutdown;
771 bool suspend;
ad49f501 772 bool need_dma32;
3ce0a23d 773 bool new_init_path;
733289c2 774 bool accel_working;
e024e110 775 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 776 const struct firmware *me_fw; /* all family ME firmware */
777 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
778 struct r600_blit r600_blit;
771fe6b9
JG		 779};
780
781int radeon_device_init(struct radeon_device *rdev,
782 struct drm_device *ddev,
783 struct pci_dev *pdev,
784 uint32_t flags);
785void radeon_device_fini(struct radeon_device *rdev);
786int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
787
3ce0a23d
JG		 788/* r600 blit */
789int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
790void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
791void r600_kms_blit_copy(struct radeon_device *rdev,
792 u64 src_gpu_addr, u64 dst_gpu_addr,
793 int size_bytes);
794
de1b2898
DA		 795static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
796{
797 if (reg < 0x10000)
798 return readl(((void __iomem *)rdev->rmmio) + reg);
799 else {
800 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
801 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
802 }
803}
804
805static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
806{
807 if (reg < 0x10000)
808 writel(v, ((void __iomem *)rdev->rmmio) + reg);
809 else {
810 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
811 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
812 }
813}
814
771fe6b9
JG		 815
816/*
817 * Registers read & write functions.
818 */
819#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
820#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
de1b2898 821#define RREG32(reg) r100_mm_rreg(rdev, (reg))
3ce0a23d 822#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
de1b2898 823#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
771fe6b9
JG		 824#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
825#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
826#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
827#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
828#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
829#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 830#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
831#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
771fe6b9
JG		 832#define WREG32_P(reg, val, mask) \
833 do { \
834 uint32_t tmp_ = RREG32(reg); \
835 tmp_ &= (mask); \
836 tmp_ |= ((val) & ~(mask)); \
837 WREG32(reg, tmp_); \
838 } while (0)
839#define WREG32_PLL_P(reg, val, mask) \
840 do { \
841 uint32_t tmp_ = RREG32_PLL(reg); \
842 tmp_ &= (mask); \
843 tmp_ |= ((val) & ~(mask)); \
844 WREG32_PLL(reg, tmp_); \
845 } while (0)
3ce0a23d 846#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
771fe6b9 847
de1b2898
DA		 848/*
849 * Indirect registers accessor
850 */
851static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
852{
853 uint32_t r;
854
855 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
856 r = RREG32(RADEON_PCIE_DATA);
857 return r;
858}
859
860static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
861{
862 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
863 WREG32(RADEON_PCIE_DATA, (v));
864}
865
771fe6b9
JG		 866void r100_pll_errata_after_index(struct radeon_device *rdev);
867
868
869/*
870 * ASICs helpers.
871 */
b995e433
DA		 872#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
873 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 874#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
875 (rdev->family == CHIP_RV200) || \
876 (rdev->family == CHIP_RS100) || \
877 (rdev->family == CHIP_RS200) || \
878 (rdev->family == CHIP_RV250) || \
879 (rdev->family == CHIP_RV280) || \
880 (rdev->family == CHIP_RS300))
881#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
882 (rdev->family == CHIP_RV350) || \
883 (rdev->family == CHIP_R350) || \
884 (rdev->family == CHIP_RV380) || \
885 (rdev->family == CHIP_R420) || \
886 (rdev->family == CHIP_R423) || \
887 (rdev->family == CHIP_RV410) || \
888 (rdev->family == CHIP_RS400) || \
889 (rdev->family == CHIP_RS480))
890#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
891#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
892#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
893
894
895/*
896 * BIOS helpers.
897 */
898#define RBIOS8(i) (rdev->bios[i])
899#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
900#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
901
902int radeon_combios_init(struct radeon_device *rdev);
903void radeon_combios_fini(struct radeon_device *rdev);
904int radeon_atombios_init(struct radeon_device *rdev);
905void radeon_atombios_fini(struct radeon_device *rdev);
906
907
908/*
909 * RING helpers.
910 */
771fe6b9
JG		 911static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
912{
913#if DRM_DEBUG_CODE
914 if (rdev->cp.count_dw <= 0) {
915 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
916 }
917#endif
918 rdev->cp.ring[rdev->cp.wptr++] = v;
919 rdev->cp.wptr &= rdev->cp.ptr_mask;
920 rdev->cp.count_dw--;
921 rdev->cp.ring_free_dw--;
922}
923
924
925/*
926 * ASICs macro.
927 */
068a117c 928#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 929#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
930#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
931#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
771fe6b9
JG		 932#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
933#define radeon_errata(rdev) (rdev)->asic->errata((rdev))
934#define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
935#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
936#define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
937#define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
938#define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
939#define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
4aac0473
JG		 940#define radeon_gpu_gart_init(rdev) (rdev)->asic->gart_init((rdev))
941#define radeon_gpu_gart_fini(rdev) (rdev)->asic->gart_fini((rdev))
771fe6b9
JG		 942#define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
943#define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
944#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
945#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
946#define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
947#define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
948#define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
3ce0a23d 949#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
771fe6b9 950#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
3ce0a23d
JG		 951#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
952#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
953#define radeon_ib_test(rdev) (rdev)->asic->ib_test((rdev))
771fe6b9
JG		 954#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
955#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
7ed220d7 956#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
771fe6b9
JG		 957#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
958#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
959#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
960#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
961#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
962#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
963#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
964#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
e024e110
DA		 965#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
966#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
c93bb85b 967#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
771fe6b9 968
6cf8a3f5 969/* Common functions */
4aac0473 970extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
21f9a437
JG		 971extern int radeon_modeset_init(struct radeon_device *rdev);
972extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 973extern bool radeon_card_posted(struct radeon_device *rdev);
21f9a437
JG		 974extern int radeon_clocks_init(struct radeon_device *rdev);
975extern void radeon_clocks_fini(struct radeon_device *rdev);
976extern void radeon_scratch_init(struct radeon_device *rdev);
977extern void radeon_surface_init(struct radeon_device *rdev);
978extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
6cf8a3f5 979
a18d7ea1 980/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
9f022ddf
JG		 981struct r100_mc_save {
982 u32 GENMO_WT;
983 u32 CRTC_EXT_CNTL;
984 u32 CRTC_GEN_CNTL;
985 u32 CRTC2_GEN_CNTL;
986 u32 CUR_OFFSET;
987 u32 CUR2_OFFSET;
988};
989extern void r100_cp_disable(struct radeon_device *rdev);
990extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
991extern void r100_cp_fini(struct radeon_device *rdev);
21f9a437 992extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
4aac0473
JG		 993extern int r100_pci_gart_init(struct radeon_device *rdev);
994extern void r100_pci_gart_fini(struct radeon_device *rdev);
21f9a437
JG		 995extern int r100_pci_gart_enable(struct radeon_device *rdev);
996extern void r100_pci_gart_disable(struct radeon_device *rdev);
997extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
9f022ddf
JG		 998extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
999extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
1000extern void r100_ib_fini(struct radeon_device *rdev);
1001extern int r100_ib_init(struct radeon_device *rdev);
1002extern void r100_irq_disable(struct radeon_device *rdev);
1003extern int r100_irq_set(struct radeon_device *rdev);
1004extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
1005extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
21f9a437 1006extern void r100_vram_init_sizes(struct radeon_device *rdev);
9f022ddf
JG		 1007extern void r100_wb_disable(struct radeon_device *rdev);
1008extern void r100_wb_fini(struct radeon_device *rdev);
1009extern int r100_wb_init(struct radeon_device *rdev);
1010
1011/* r300,r350,rv350,rv370,rv380 */
1012extern void r300_set_reg_safe(struct radeon_device *rdev);
1013extern void r300_mc_program(struct radeon_device *rdev);
1014extern void r300_vram_info(struct radeon_device *rdev);
4aac0473
JG		 1015extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1016extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1017extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
9f022ddf 1018extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
a18d7ea1 1019
905b6822 1020/* r420,r423,rv410 */
21f9a437
JG		 1021extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1022extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
9f022ddf 1023extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
905b6822 1024
21f9a437
JG		 1025/* rv515 */
1026extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1027
1028/* rs690, rs740 */
1029extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1030 struct drm_display_mode *mode1,
1031 struct drm_display_mode *mode2);
1032
1033/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1034extern bool r600_card_posted(struct radeon_device *rdev);
1035extern void r600_cp_stop(struct radeon_device *rdev);
1036extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1037extern int r600_cp_resume(struct radeon_device *rdev);
1038extern int r600_count_pipe_bits(uint32_t val);
1039extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1040extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
4aac0473 1041extern int r600_pcie_gart_init(struct radeon_device *rdev);
21f9a437
JG		 1042extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1043extern int r600_ib_test(struct radeon_device *rdev);
1044extern int r600_ring_test(struct radeon_device *rdev);
1045extern int r600_wb_init(struct radeon_device *rdev);
1046extern void r600_wb_fini(struct radeon_device *rdev);
1047extern void r600_scratch_init(struct radeon_device *rdev);
1048extern int r600_blit_init(struct radeon_device *rdev);
1049extern void r600_blit_fini(struct radeon_device *rdev);
1050extern int r600_cp_init_microcode(struct radeon_device *rdev);
fe62e1a4 1051extern int r600_gpu_reset(struct radeon_device *rdev);
21f9a437 1052
771fe6b9 1053#endif
Linux kernel - Deliverables
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