[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_asic.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */

#include <linux/console.h>
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/radeon_drm.h>
#include <linux/vgaarb.h>
#include <linux/vga_switcheroo.h>
#include "radeon_reg.h"
#include "radeon.h"
#include "radeon_asic.h"
#include "atom.h"

/*
 * Registers accessors functions.
 */
static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
{
	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
	BUG_ON(1);
	return 0;
}

static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
{
	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
		  reg, v);
	BUG_ON(1);
}

static void radeon_register_accessor_init(struct radeon_device *rdev)
{
	rdev->mc_rreg = &radeon_invalid_rreg;
	rdev->mc_wreg = &radeon_invalid_wreg;
	rdev->pll_rreg = &radeon_invalid_rreg;
	rdev->pll_wreg = &radeon_invalid_wreg;
	rdev->pciep_rreg = &radeon_invalid_rreg;
	rdev->pciep_wreg = &radeon_invalid_wreg;

	/* Don't change order as we are overridding accessor. */
	if (rdev->family < CHIP_RV515) {
		rdev->pcie_reg_mask = 0xff;
	} else {
		rdev->pcie_reg_mask = 0x7ff;
	}
	/* FIXME: not sure here */
	if (rdev->family <= CHIP_R580) {
		rdev->pll_rreg = &r100_pll_rreg;
		rdev->pll_wreg = &r100_pll_wreg;
	}
	if (rdev->family >= CHIP_R420) {
		rdev->mc_rreg = &r420_mc_rreg;
		rdev->mc_wreg = &r420_mc_wreg;
	}
	if (rdev->family >= CHIP_RV515) {
		rdev->mc_rreg = &rv515_mc_rreg;
		rdev->mc_wreg = &rv515_mc_wreg;
	}
	if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
		rdev->mc_rreg = &rs400_mc_rreg;
		rdev->mc_wreg = &rs400_mc_wreg;
	}
	if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
		rdev->mc_rreg = &rs690_mc_rreg;
		rdev->mc_wreg = &rs690_mc_wreg;
	}
	if (rdev->family == CHIP_RS600) {
		rdev->mc_rreg = &rs600_mc_rreg;
		rdev->mc_wreg = &rs600_mc_wreg;
	}
	if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) {
		rdev->pciep_rreg = &r600_pciep_rreg;
		rdev->pciep_wreg = &r600_pciep_wreg;
	}
}


/* helper to disable agp */
void radeon_agp_disable(struct radeon_device *rdev)
{
	rdev->flags &= ~RADEON_IS_AGP;
	if (rdev->family >= CHIP_R600) {
		DRM_INFO("Forcing AGP to PCIE mode\n");
		rdev->flags |= RADEON_IS_PCIE;
	} else if (rdev->family >= CHIP_RV515 ||
			rdev->family == CHIP_RV380 ||
			rdev->family == CHIP_RV410 ||
			rdev->family == CHIP_R423) {
		DRM_INFO("Forcing AGP to PCIE mode\n");
		rdev->flags |= RADEON_IS_PCIE;
		rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
		rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
	} else {
		DRM_INFO("Forcing AGP to PCI mode\n");
		rdev->flags |= RADEON_IS_PCI;
		rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
		rdev->asic->gart_set_page = &r100_pci_gart_set_page;
	}
	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
}

/*
 * ASIC
 */
int radeon_asic_init(struct radeon_device *rdev)
{
	radeon_register_accessor_init(rdev);
	switch (rdev->family) {
	case CHIP_R100:
	case CHIP_RV100:
	case CHIP_RS100:
	case CHIP_RV200:
	case CHIP_RS200:
		rdev->asic = &r100_asic;
		break;
	case CHIP_R200:
	case CHIP_RV250:
	case CHIP_RS300:
	case CHIP_RV280:
		rdev->asic = &r200_asic;
		break;
	case CHIP_R300:
	case CHIP_R350:
	case CHIP_RV350:
	case CHIP_RV380:
		if (rdev->flags & RADEON_IS_PCIE)
			rdev->asic = &r300_asic_pcie;
		else
			rdev->asic = &r300_asic;
		break;
	case CHIP_R420:
	case CHIP_R423:
	case CHIP_RV410:
		rdev->asic = &r420_asic;
		break;
	case CHIP_RS400:
	case CHIP_RS480:
		rdev->asic = &rs400_asic;
		break;
	case CHIP_RS600:
		rdev->asic = &rs600_asic;
		break;
	case CHIP_RS690:
	case CHIP_RS740:
		rdev->asic = &rs690_asic;
		break;
	case CHIP_RV515:
		rdev->asic = &rv515_asic;
		break;
	case CHIP_R520:
	case CHIP_RV530:
	case CHIP_RV560:
	case CHIP_RV570:
	case CHIP_R580:
		rdev->asic = &r520_asic;
		break;
	case CHIP_R600:
	case CHIP_RV610:
	case CHIP_RV630:
	case CHIP_RV620:
	case CHIP_RV635:
	case CHIP_RV670:
	case CHIP_RS780:
	case CHIP_RS880:
		rdev->asic = &r600_asic;
		break;
	case CHIP_RV770:
	case CHIP_RV730:
	case CHIP_RV710:
	case CHIP_RV740:
		rdev->asic = &rv770_asic;
		break;
	case CHIP_CEDAR:
	case CHIP_REDWOOD:
	case CHIP_JUNIPER:
	case CHIP_CYPRESS:
	case CHIP_HEMLOCK:
		rdev->asic = &evergreen_asic;
		break;
	default:
		/* FIXME: not supported yet */
		return -EINVAL;
	}

	if (rdev->flags & RADEON_IS_IGP) {
		rdev->asic->get_memory_clock = NULL;
		rdev->asic->set_memory_clock = NULL;
	}

	return 0;
}

/*
 * Wrapper around modesetting bits. Move to radeon_clocks.c?
 */
int radeon_clocks_init(struct radeon_device *rdev)
{
	int r;

	r = radeon_static_clocks_init(rdev->ddev);
	if (r) {
		return r;
	}
	DRM_INFO("Clocks initialized !\n");
	return 0;
}

void radeon_clocks_fini(struct radeon_device *rdev)
{
}
Commit	Line	Data
0a10c851 DV	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
	28
	29	#include <linux/console.h>
	30	#include <drm/drmP.h>
	31	#include <drm/drm_crtc_helper.h>
	32	#include <drm/radeon_drm.h>
	33	#include <linux/vgaarb.h>
	34	#include <linux/vga_switcheroo.h>
	35	#include "radeon_reg.h"
	36	#include "radeon.h"
	37	#include "radeon_asic.h"
	38	#include "atom.h"
	39
	40	/*
	41	* Registers accessors functions.
	42	*/
	43	static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
	44	{
	45	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
	46	BUG_ON(1);
	47	return 0;
	48	}
	49
	50	static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
	51	{
	52	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
	53	reg, v);
	54	BUG_ON(1);
	55	}
	56
	57	static void radeon_register_accessor_init(struct radeon_device *rdev)
	58	{
	59	rdev->mc_rreg = &radeon_invalid_rreg;
	60	rdev->mc_wreg = &radeon_invalid_wreg;
	61	rdev->pll_rreg = &radeon_invalid_rreg;
	62	rdev->pll_wreg = &radeon_invalid_wreg;
	63	rdev->pciep_rreg = &radeon_invalid_rreg;
	64	rdev->pciep_wreg = &radeon_invalid_wreg;
65
66	/* Don't change order as we are overridding accessor. */
67	if (rdev->family < CHIP_RV515) {
68	rdev->pcie_reg_mask = 0xff;
69	} else {
70	rdev->pcie_reg_mask = 0x7ff;
71	}
72	/* FIXME: not sure here */
73	if (rdev->family <= CHIP_R580) {
74	rdev->pll_rreg = &r100_pll_rreg;
75	rdev->pll_wreg = &r100_pll_wreg;
76	}
77	if (rdev->family >= CHIP_R420) {
78	rdev->mc_rreg = &r420_mc_rreg;
79	rdev->mc_wreg = &r420_mc_wreg;
80	}
81	if (rdev->family >= CHIP_RV515) {
82	rdev->mc_rreg = &rv515_mc_rreg;
83	rdev->mc_wreg = &rv515_mc_wreg;
84	}
85	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480) {
86	rdev->mc_rreg = &rs400_mc_rreg;
87	rdev->mc_wreg = &rs400_mc_wreg;
88	}
89	if (rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {
90	rdev->mc_rreg = &rs690_mc_rreg;
91	rdev->mc_wreg = &rs690_mc_wreg;
92	}
93	if (rdev->family == CHIP_RS600) {
94	rdev->mc_rreg = &rs600_mc_rreg;
95	rdev->mc_wreg = &rs600_mc_wreg;
96	}
97	if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) {
98	rdev->pciep_rreg = &r600_pciep_rreg;
99	rdev->pciep_wreg = &r600_pciep_wreg;
100	}
101	}
102
103
104	/* helper to disable agp */
105	void radeon_agp_disable(struct radeon_device *rdev)
106	{
107	rdev->flags &= ~RADEON_IS_AGP;
108	if (rdev->family >= CHIP_R600) {
109	DRM_INFO("Forcing AGP to PCIE mode\n");
110	rdev->flags \|= RADEON_IS_PCIE;
111	} else if (rdev->family >= CHIP_RV515 \|\|
112	rdev->family == CHIP_RV380 \|\|
113	rdev->family == CHIP_RV410 \|\|
114	rdev->family == CHIP_R423) {
115	DRM_INFO("Forcing AGP to PCIE mode\n");
116	rdev->flags \|= RADEON_IS_PCIE;
117	rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
118	rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
119	} else {
120	DRM_INFO("Forcing AGP to PCI mode\n");
121	rdev->flags \|= RADEON_IS_PCI;
122	rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
123	rdev->asic->gart_set_page = &r100_pci_gart_set_page;
124	}
125	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
126	}
127
128	/*
129	* ASIC
130	*/
131	int radeon_asic_init(struct radeon_device *rdev)
132	{
133	radeon_register_accessor_init(rdev);
134	switch (rdev->family) {
135	case CHIP_R100:
136	case CHIP_RV100:
137	case CHIP_RS100:
138	case CHIP_RV200:
139	case CHIP_RS200:
140	rdev->asic = &r100_asic;
141	break;
142	case CHIP_R200:
143	case CHIP_RV250:
144	case CHIP_RS300:
145	case CHIP_RV280:
146	rdev->asic = &r200_asic;
147	break;
148	case CHIP_R300:
149	case CHIP_R350:
150	case CHIP_RV350:
151	case CHIP_RV380:
152	if (rdev->flags & RADEON_IS_PCIE)
153	rdev->asic = &r300_asic_pcie;
154	else
155	rdev->asic = &r300_asic;
156	break;
157	case CHIP_R420:
158	case CHIP_R423:
159	case CHIP_RV410:
160	rdev->asic = &r420_asic;
161	break;
162	case CHIP_RS400:
163	case CHIP_RS480:
164	rdev->asic = &rs400_asic;
165	break;
166	case CHIP_RS600:
167	rdev->asic = &rs600_asic;
168	break;
169	case CHIP_RS690:
170	case CHIP_RS740:
171	rdev->asic = &rs690_asic;
172	break;
173	case CHIP_RV515:
174	rdev->asic = &rv515_asic;
175	break;
176	case CHIP_R520:
177	case CHIP_RV530:
178	case CHIP_RV560:
179	case CHIP_RV570:
180	case CHIP_R580:
181	rdev->asic = &r520_asic;
182	break;
183	case CHIP_R600:
184	case CHIP_RV610:
185	case CHIP_RV630:
186	case CHIP_RV620:
187	case CHIP_RV635:
188	case CHIP_RV670:
189	case CHIP_RS780:
190	case CHIP_RS880:
191	rdev->asic = &r600_asic;
192	break;
193	case CHIP_RV770:
194	case CHIP_RV730:
195	case CHIP_RV710:
196	case CHIP_RV740:
197	rdev->asic = &rv770_asic;
198	break;
199	case CHIP_CEDAR:
200	case CHIP_REDWOOD:
201	case CHIP_JUNIPER:
202	case CHIP_CYPRESS:
203	case CHIP_HEMLOCK:
204	rdev->asic = &evergreen_asic;
205	break;
206	default:
207	/* FIXME: not supported yet */
208	return -EINVAL;
209	}
210
211	if (rdev->flags & RADEON_IS_IGP) {
212	rdev->asic->get_memory_clock = NULL;
213	rdev->asic->set_memory_clock = NULL;
214	}
215
216	return 0;
217	}
218
219	/*
220	* Wrapper around modesetting bits. Move to radeon_clocks.c?
221	*/
222	int radeon_clocks_init(struct radeon_device *rdev)
223	{
224	int r;
225
226	r = radeon_static_clocks_init(rdev->ddev);
227	if (r) {
228	return r;
229	}
230	DRM_INFO("Clocks initialized !\n");
231	return 0;
232	}
233
234	void radeon_clocks_fini(struct radeon_device *rdev)
235	{
236	}