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drm/radeon/kms: reorganize page flip callbacks
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_asic.c
CommitLineData
0a10c851
DV		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/console.h>
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
33#include <linux/vgaarb.h>
34#include <linux/vga_switcheroo.h>
35#include "radeon_reg.h"
36#include "radeon.h"
37#include "radeon_asic.h"
38#include "atom.h"
39
40/*
41 * Registers accessors functions.
42 */
43static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
44{
45 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
46 BUG_ON(1);
47 return 0;
48}
49
50static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
51{
52 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
53 reg, v);
54 BUG_ON(1);
55}
56
57static void radeon_register_accessor_init(struct radeon_device *rdev)
58{
59 rdev->mc_rreg = &radeon_invalid_rreg;
60 rdev->mc_wreg = &radeon_invalid_wreg;
61 rdev->pll_rreg = &radeon_invalid_rreg;
62 rdev->pll_wreg = &radeon_invalid_wreg;
63 rdev->pciep_rreg = &radeon_invalid_rreg;
64 rdev->pciep_wreg = &radeon_invalid_wreg;
65
66 /* Don't change order as we are overridding accessor. */
67 if (rdev->family < CHIP_RV515) {
68 rdev->pcie_reg_mask = 0xff;
69 } else {
70 rdev->pcie_reg_mask = 0x7ff;
71 }
72 /* FIXME: not sure here */
73 if (rdev->family <= CHIP_R580) {
74 rdev->pll_rreg = &r100_pll_rreg;
75 rdev->pll_wreg = &r100_pll_wreg;
76 }
77 if (rdev->family >= CHIP_R420) {
78 rdev->mc_rreg = &r420_mc_rreg;
79 rdev->mc_wreg = &r420_mc_wreg;
80 }
81 if (rdev->family >= CHIP_RV515) {
82 rdev->mc_rreg = &rv515_mc_rreg;
83 rdev->mc_wreg = &rv515_mc_wreg;
84 }
85 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
86 rdev->mc_rreg = &rs400_mc_rreg;
87 rdev->mc_wreg = &rs400_mc_wreg;
88 }
89 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
90 rdev->mc_rreg = &rs690_mc_rreg;
91 rdev->mc_wreg = &rs690_mc_wreg;
92 }
93 if (rdev->family == CHIP_RS600) {
94 rdev->mc_rreg = &rs600_mc_rreg;
95 rdev->mc_wreg = &rs600_mc_wreg;
96 }
b4df8be1 97 if (rdev->family >= CHIP_R600) {
0a10c851
DV		 98 rdev->pciep_rreg = &r600_pciep_rreg;
99 rdev->pciep_wreg = &r600_pciep_wreg;
100 }
101}
102
103
104/* helper to disable agp */
105void radeon_agp_disable(struct radeon_device *rdev)
106{
107 rdev->flags &= ~RADEON_IS_AGP;
108 if (rdev->family >= CHIP_R600) {
109 DRM_INFO("Forcing AGP to PCIE mode\n");
110 rdev->flags |= RADEON_IS_PCIE;
111 } else if (rdev->family >= CHIP_RV515 ||
112 rdev->family == CHIP_RV380 ||
113 rdev->family == CHIP_RV410 ||
114 rdev->family == CHIP_R423) {
115 DRM_INFO("Forcing AGP to PCIE mode\n");
116 rdev->flags |= RADEON_IS_PCIE;
117 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
118 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
119 } else {
120 DRM_INFO("Forcing AGP to PCI mode\n");
121 rdev->flags |= RADEON_IS_PCI;
122 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
123 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
124 }
125 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
126}
127
128/*
129 * ASIC
130 */
48e7a5f1
DV		 131static struct radeon_asic r100_asic = {
132 .init = &r100_init,
133 .fini = &r100_fini,
134 .suspend = &r100_suspend,
135 .resume = &r100_resume,
136 .vga_set_state = &r100_vga_set_state,
225758d8 137 .gpu_is_lockup = &r100_gpu_is_lockup,
a2d07b74 138 .asic_reset = &r100_asic_reset,
48e7a5f1
DV		 139 .gart_tlb_flush = &r100_pci_gart_tlb_flush,
140 .gart_set_page = &r100_pci_gart_set_page,
48e7a5f1
DV		 141 .ring_start = &r100_ring_start,
142 .ring_test = &r100_ring_test,
4c87bc26
CK		 143 .ring = {
144 [RADEON_RING_TYPE_GFX_INDEX] = {
145 .ib_execute = &r100_ring_ib_execute,
146 .emit_fence = &r100_fence_ring_emit,
147 .emit_semaphore = &r100_semaphore_ring_emit,
148 }
149 },
48e7a5f1
DV		 150 .irq_set = &r100_irq_set,
151 .irq_process = &r100_irq_process,
152 .get_vblank_counter = &r100_get_vblank_counter,
48e7a5f1
DV		 153 .cs_parse = &r100_cs_parse,
154 .copy_blit = &r100_copy_blit,
155 .copy_dma = NULL,
156 .copy = &r100_copy_blit,
157 .get_engine_clock = &radeon_legacy_get_engine_clock,
158 .set_engine_clock = &radeon_legacy_set_engine_clock,
159 .get_memory_clock = &radeon_legacy_get_memory_clock,
160 .set_memory_clock = NULL,
161 .get_pcie_lanes = NULL,
162 .set_pcie_lanes = NULL,
163 .set_clock_gating = &radeon_legacy_set_clock_gating,
164 .set_surface_reg = r100_set_surface_reg,
165 .clear_surface_reg = r100_clear_surface_reg,
166 .bandwidth_update = &r100_bandwidth_update,
901ea57d
AD		 167 .hpd = {
168 .init = &r100_hpd_init,
169 .fini = &r100_hpd_fini,
170 .sense = &r100_hpd_sense,
171 .set_polarity = &r100_hpd_set_polarity,
172 },
48e7a5f1 173 .ioctl_wait_idle = NULL,
def9ba9c 174 .gui_idle = &r100_gui_idle,
49e02b73
AD		 175 .pm_misc = &r100_pm_misc,
176 .pm_prepare = &r100_pm_prepare,
177 .pm_finish = &r100_pm_finish,
ce8f5370
AD		 178 .pm_init_profile = &r100_pm_init_profile,
179 .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
0f9e006c
AD		 180 .pflip = {
181 .pre_page_flip = &r100_pre_page_flip,
182 .page_flip = &r100_page_flip,
183 .post_page_flip = &r100_post_page_flip,
184 },
3ae19b75 185 .wait_for_vblank = &r100_wait_for_vblank,
89e5181f 186 .mc_wait_for_idle = &r100_mc_wait_for_idle,
48e7a5f1
DV		 187};
188
189static struct radeon_asic r200_asic = {
190 .init = &r100_init,
191 .fini = &r100_fini,
192 .suspend = &r100_suspend,
193 .resume = &r100_resume,
194 .vga_set_state = &r100_vga_set_state,
225758d8 195 .gpu_is_lockup = &r100_gpu_is_lockup,
a2d07b74 196 .asic_reset = &r100_asic_reset,
48e7a5f1
DV		 197 .gart_tlb_flush = &r100_pci_gart_tlb_flush,
198 .gart_set_page = &r100_pci_gart_set_page,
48e7a5f1
DV		 199 .ring_start = &r100_ring_start,
200 .ring_test = &r100_ring_test,
4c87bc26
CK		 201 .ring = {
202 [RADEON_RING_TYPE_GFX_INDEX] = {
203 .ib_execute = &r100_ring_ib_execute,
204 .emit_fence = &r100_fence_ring_emit,
205 .emit_semaphore = &r100_semaphore_ring_emit,
206 }
207 },
48e7a5f1
DV		 208 .irq_set = &r100_irq_set,
209 .irq_process = &r100_irq_process,
210 .get_vblank_counter = &r100_get_vblank_counter,
48e7a5f1
DV		 211 .cs_parse = &r100_cs_parse,
212 .copy_blit = &r100_copy_blit,
213 .copy_dma = &r200_copy_dma,
214 .copy = &r100_copy_blit,
215 .get_engine_clock = &radeon_legacy_get_engine_clock,
216 .set_engine_clock = &radeon_legacy_set_engine_clock,
217 .get_memory_clock = &radeon_legacy_get_memory_clock,
218 .set_memory_clock = NULL,
219 .set_pcie_lanes = NULL,
220 .set_clock_gating = &radeon_legacy_set_clock_gating,
221 .set_surface_reg = r100_set_surface_reg,
222 .clear_surface_reg = r100_clear_surface_reg,
223 .bandwidth_update = &r100_bandwidth_update,
901ea57d
AD		 224 .hpd = {
225 .init = &r100_hpd_init,
226 .fini = &r100_hpd_fini,
227 .sense = &r100_hpd_sense,
228 .set_polarity = &r100_hpd_set_polarity,
229 },
48e7a5f1 230 .ioctl_wait_idle = NULL,
def9ba9c 231 .gui_idle = &r100_gui_idle,
49e02b73
AD		 232 .pm_misc = &r100_pm_misc,
233 .pm_prepare = &r100_pm_prepare,
234 .pm_finish = &r100_pm_finish,
ce8f5370
AD		 235 .pm_init_profile = &r100_pm_init_profile,
236 .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
0f9e006c
AD		 237 .pflip = {
238 .pre_page_flip = &r100_pre_page_flip,
239 .page_flip = &r100_page_flip,
240 .post_page_flip = &r100_post_page_flip,
241 },
3ae19b75 242 .wait_for_vblank = &r100_wait_for_vblank,
89e5181f 243 .mc_wait_for_idle = &r100_mc_wait_for_idle,
48e7a5f1
DV		 244};
245
246static struct radeon_asic r300_asic = {
247 .init = &r300_init,
248 .fini = &r300_fini,
249 .suspend = &r300_suspend,
250 .resume = &r300_resume,
251 .vga_set_state = &r100_vga_set_state,
225758d8 252 .gpu_is_lockup = &r300_gpu_is_lockup,
a2d07b74 253 .asic_reset = &r300_asic_reset,
48e7a5f1
DV		 254 .gart_tlb_flush = &r100_pci_gart_tlb_flush,
255 .gart_set_page = &r100_pci_gart_set_page,
48e7a5f1
DV		 256 .ring_start = &r300_ring_start,
257 .ring_test = &r100_ring_test,
4c87bc26
CK		 258 .ring = {
259 [RADEON_RING_TYPE_GFX_INDEX] = {
260 .ib_execute = &r100_ring_ib_execute,
261 .emit_fence = &r300_fence_ring_emit,
262 .emit_semaphore = &r100_semaphore_ring_emit,
263 }
264 },
48e7a5f1
DV		 265 .irq_set = &r100_irq_set,
266 .irq_process = &r100_irq_process,
267 .get_vblank_counter = &r100_get_vblank_counter,
48e7a5f1
DV		 268 .cs_parse = &r300_cs_parse,
269 .copy_blit = &r100_copy_blit,
270 .copy_dma = &r200_copy_dma,
271 .copy = &r100_copy_blit,
272 .get_engine_clock = &radeon_legacy_get_engine_clock,
273 .set_engine_clock = &radeon_legacy_set_engine_clock,
274 .get_memory_clock = &radeon_legacy_get_memory_clock,
275 .set_memory_clock = NULL,
276 .get_pcie_lanes = &rv370_get_pcie_lanes,
277 .set_pcie_lanes = &rv370_set_pcie_lanes,
278 .set_clock_gating = &radeon_legacy_set_clock_gating,
279 .set_surface_reg = r100_set_surface_reg,
280 .clear_surface_reg = r100_clear_surface_reg,
281 .bandwidth_update = &r100_bandwidth_update,
901ea57d
AD		 282 .hpd = {
283 .init = &r100_hpd_init,
284 .fini = &r100_hpd_fini,
285 .sense = &r100_hpd_sense,
286 .set_polarity = &r100_hpd_set_polarity,
287 },
48e7a5f1 288 .ioctl_wait_idle = NULL,
def9ba9c 289 .gui_idle = &r100_gui_idle,
49e02b73
AD		 290 .pm_misc = &r100_pm_misc,
291 .pm_prepare = &r100_pm_prepare,
292 .pm_finish = &r100_pm_finish,
ce8f5370
AD		 293 .pm_init_profile = &r100_pm_init_profile,
294 .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
0f9e006c
AD		 295 .pflip = {
296 .pre_page_flip = &r100_pre_page_flip,
297 .page_flip = &r100_page_flip,
298 .post_page_flip = &r100_post_page_flip,
299 },
3ae19b75 300 .wait_for_vblank = &r100_wait_for_vblank,
89e5181f 301 .mc_wait_for_idle = &r300_mc_wait_for_idle,
48e7a5f1
DV		 302};
303
304static struct radeon_asic r300_asic_pcie = {
305 .init = &r300_init,
306 .fini = &r300_fini,
307 .suspend = &r300_suspend,
308 .resume = &r300_resume,
309 .vga_set_state = &r100_vga_set_state,
225758d8 310 .gpu_is_lockup = &r300_gpu_is_lockup,
a2d07b74 311 .asic_reset = &r300_asic_reset,
48e7a5f1
DV		 312 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
313 .gart_set_page = &rv370_pcie_gart_set_page,
48e7a5f1
DV		 314 .ring_start = &r300_ring_start,
315 .ring_test = &r100_ring_test,
4c87bc26
CK		 316 .ring = {
317 [RADEON_RING_TYPE_GFX_INDEX] = {
318 .ib_execute = &r100_ring_ib_execute,
319 .emit_fence = &r300_fence_ring_emit,
320 .emit_semaphore = &r100_semaphore_ring_emit,
321 }
322 },
48e7a5f1
DV		 323 .irq_set = &r100_irq_set,
324 .irq_process = &r100_irq_process,
325 .get_vblank_counter = &r100_get_vblank_counter,
48e7a5f1
DV		 326 .cs_parse = &r300_cs_parse,
327 .copy_blit = &r100_copy_blit,
328 .copy_dma = &r200_copy_dma,
329 .copy = &r100_copy_blit,
330 .get_engine_clock = &radeon_legacy_get_engine_clock,
331 .set_engine_clock = &radeon_legacy_set_engine_clock,
332 .get_memory_clock = &radeon_legacy_get_memory_clock,
333 .set_memory_clock = NULL,
334 .set_pcie_lanes = &rv370_set_pcie_lanes,
335 .set_clock_gating = &radeon_legacy_set_clock_gating,
336 .set_surface_reg = r100_set_surface_reg,
337 .clear_surface_reg = r100_clear_surface_reg,
338 .bandwidth_update = &r100_bandwidth_update,
901ea57d
AD		 339 .hpd = {
340 .init = &r100_hpd_init,
341 .fini = &r100_hpd_fini,
342 .sense = &r100_hpd_sense,
343 .set_polarity = &r100_hpd_set_polarity,
344 },
48e7a5f1 345 .ioctl_wait_idle = NULL,
def9ba9c 346 .gui_idle = &r100_gui_idle,
49e02b73
AD		 347 .pm_misc = &r100_pm_misc,
348 .pm_prepare = &r100_pm_prepare,
349 .pm_finish = &r100_pm_finish,
ce8f5370
AD		 350 .pm_init_profile = &r100_pm_init_profile,
351 .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
0f9e006c
AD		 352 .pflip = {
353 .pre_page_flip = &r100_pre_page_flip,
354 .page_flip = &r100_page_flip,
355 .post_page_flip = &r100_post_page_flip,
356 },
3ae19b75 357 .wait_for_vblank = &r100_wait_for_vblank,
89e5181f 358 .mc_wait_for_idle = &r300_mc_wait_for_idle,
48e7a5f1
DV		 359};
360
361static struct radeon_asic r420_asic = {
362 .init = &r420_init,
363 .fini = &r420_fini,
364 .suspend = &r420_suspend,
365 .resume = &r420_resume,
366 .vga_set_state = &r100_vga_set_state,
225758d8 367 .gpu_is_lockup = &r300_gpu_is_lockup,
a2d07b74 368 .asic_reset = &r300_asic_reset,
48e7a5f1
DV		 369 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
370 .gart_set_page = &rv370_pcie_gart_set_page,
48e7a5f1
DV		 371 .ring_start = &r300_ring_start,
372 .ring_test = &r100_ring_test,
4c87bc26
CK		 373 .ring = {
374 [RADEON_RING_TYPE_GFX_INDEX] = {
375 .ib_execute = &r100_ring_ib_execute,
376 .emit_fence = &r300_fence_ring_emit,
377 .emit_semaphore = &r100_semaphore_ring_emit,
378 }
379 },
48e7a5f1
DV		 380 .irq_set = &r100_irq_set,
381 .irq_process = &r100_irq_process,
382 .get_vblank_counter = &r100_get_vblank_counter,
48e7a5f1
DV		 383 .cs_parse = &r300_cs_parse,
384 .copy_blit = &r100_copy_blit,
385 .copy_dma = &r200_copy_dma,
386 .copy = &r100_copy_blit,
387 .get_engine_clock = &radeon_atom_get_engine_clock,
388 .set_engine_clock = &radeon_atom_set_engine_clock,
389 .get_memory_clock = &radeon_atom_get_memory_clock,
390 .set_memory_clock = &radeon_atom_set_memory_clock,
391 .get_pcie_lanes = &rv370_get_pcie_lanes,
392 .set_pcie_lanes = &rv370_set_pcie_lanes,
393 .set_clock_gating = &radeon_atom_set_clock_gating,
394 .set_surface_reg = r100_set_surface_reg,
395 .clear_surface_reg = r100_clear_surface_reg,
396 .bandwidth_update = &r100_bandwidth_update,
901ea57d
AD		 397 .hpd = {
398 .init = &r100_hpd_init,
399 .fini = &r100_hpd_fini,
400 .sense = &r100_hpd_sense,
401 .set_polarity = &r100_hpd_set_polarity,
402 },
48e7a5f1 403 .ioctl_wait_idle = NULL,
def9ba9c 404 .gui_idle = &r100_gui_idle,
49e02b73
AD		 405 .pm_misc = &r100_pm_misc,
406 .pm_prepare = &r100_pm_prepare,
407 .pm_finish = &r100_pm_finish,
ce8f5370
AD		 408 .pm_init_profile = &r420_pm_init_profile,
409 .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
0f9e006c
AD		 410 .pflip = {
411 .pre_page_flip = &r100_pre_page_flip,
412 .page_flip = &r100_page_flip,
413 .post_page_flip = &r100_post_page_flip,
414 },
3ae19b75 415 .wait_for_vblank = &r100_wait_for_vblank,
89e5181f 416 .mc_wait_for_idle = &r300_mc_wait_for_idle,
48e7a5f1
DV		 417};
418
419static struct radeon_asic rs400_asic = {
420 .init = &rs400_init,
421 .fini = &rs400_fini,
422 .suspend = &rs400_suspend,
423 .resume = &rs400_resume,
424 .vga_set_state = &r100_vga_set_state,
225758d8 425 .gpu_is_lockup = &r300_gpu_is_lockup,
a2d07b74 426 .asic_reset = &r300_asic_reset,
48e7a5f1
DV		 427 .gart_tlb_flush = &rs400_gart_tlb_flush,
428 .gart_set_page = &rs400_gart_set_page,
48e7a5f1
DV		 429 .ring_start = &r300_ring_start,
430 .ring_test = &r100_ring_test,
4c87bc26
CK		 431 .ring = {
432 [RADEON_RING_TYPE_GFX_INDEX] = {
433 .ib_execute = &r100_ring_ib_execute,
434 .emit_fence = &r300_fence_ring_emit,
435 .emit_semaphore = &r100_semaphore_ring_emit,
436 }
437 },
48e7a5f1
DV		 438 .irq_set = &r100_irq_set,
439 .irq_process = &r100_irq_process,
440 .get_vblank_counter = &r100_get_vblank_counter,
48e7a5f1
DV		 441 .cs_parse = &r300_cs_parse,
442 .copy_blit = &r100_copy_blit,
443 .copy_dma = &r200_copy_dma,
444 .copy = &r100_copy_blit,
445 .get_engine_clock = &radeon_legacy_get_engine_clock,
446 .set_engine_clock = &radeon_legacy_set_engine_clock,
447 .get_memory_clock = &radeon_legacy_get_memory_clock,
448 .set_memory_clock = NULL,
449 .get_pcie_lanes = NULL,
450 .set_pcie_lanes = NULL,
451 .set_clock_gating = &radeon_legacy_set_clock_gating,
452 .set_surface_reg = r100_set_surface_reg,
453 .clear_surface_reg = r100_clear_surface_reg,
454 .bandwidth_update = &r100_bandwidth_update,
901ea57d
AD		 455 .hpd = {
456 .init = &r100_hpd_init,
457 .fini = &r100_hpd_fini,
458 .sense = &r100_hpd_sense,
459 .set_polarity = &r100_hpd_set_polarity,
460 },
48e7a5f1 461 .ioctl_wait_idle = NULL,
def9ba9c 462 .gui_idle = &r100_gui_idle,
49e02b73
AD		 463 .pm_misc = &r100_pm_misc,
464 .pm_prepare = &r100_pm_prepare,
465 .pm_finish = &r100_pm_finish,
ce8f5370
AD		 466 .pm_init_profile = &r100_pm_init_profile,
467 .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
0f9e006c
AD		 468 .pflip = {
469 .pre_page_flip = &r100_pre_page_flip,
470 .page_flip = &r100_page_flip,
471 .post_page_flip = &r100_post_page_flip,
472 },
3ae19b75 473 .wait_for_vblank = &r100_wait_for_vblank,
89e5181f 474 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
48e7a5f1
DV		 475};
476
477static struct radeon_asic rs600_asic = {
478 .init = &rs600_init,
479 .fini = &rs600_fini,
480 .suspend = &rs600_suspend,
481 .resume = &rs600_resume,
482 .vga_set_state = &r100_vga_set_state,
225758d8 483 .gpu_is_lockup = &r300_gpu_is_lockup,
90aca4d2 484 .asic_reset = &rs600_asic_reset,
48e7a5f1
DV		 485 .gart_tlb_flush = &rs600_gart_tlb_flush,
486 .gart_set_page = &rs600_gart_set_page,
48e7a5f1
DV		 487 .ring_start = &r300_ring_start,
488 .ring_test = &r100_ring_test,
4c87bc26
CK		 489 .ring = {
490 [RADEON_RING_TYPE_GFX_INDEX] = {
491 .ib_execute = &r100_ring_ib_execute,
492 .emit_fence = &r300_fence_ring_emit,
493 .emit_semaphore = &r100_semaphore_ring_emit,
494 }
495 },
48e7a5f1
DV		 496 .irq_set = &rs600_irq_set,
497 .irq_process = &rs600_irq_process,
498 .get_vblank_counter = &rs600_get_vblank_counter,
48e7a5f1
DV		 499 .cs_parse = &r300_cs_parse,
500 .copy_blit = &r100_copy_blit,
501 .copy_dma = &r200_copy_dma,
502 .copy = &r100_copy_blit,
503 .get_engine_clock = &radeon_atom_get_engine_clock,
504 .set_engine_clock = &radeon_atom_set_engine_clock,
505 .get_memory_clock = &radeon_atom_get_memory_clock,
506 .set_memory_clock = &radeon_atom_set_memory_clock,
507 .get_pcie_lanes = NULL,
508 .set_pcie_lanes = NULL,
509 .set_clock_gating = &radeon_atom_set_clock_gating,
510 .set_surface_reg = r100_set_surface_reg,
511 .clear_surface_reg = r100_clear_surface_reg,
512 .bandwidth_update = &rs600_bandwidth_update,
901ea57d
AD		 513 .hpd = {
514 .init = &rs600_hpd_init,
515 .fini = &rs600_hpd_fini,
516 .sense = &rs600_hpd_sense,
517 .set_polarity = &rs600_hpd_set_polarity,
518 },
48e7a5f1 519 .ioctl_wait_idle = NULL,
def9ba9c 520 .gui_idle = &r100_gui_idle,
49e02b73
AD		 521 .pm_misc = &rs600_pm_misc,
522 .pm_prepare = &rs600_pm_prepare,
523 .pm_finish = &rs600_pm_finish,
ce8f5370
AD		 524 .pm_init_profile = &r420_pm_init_profile,
525 .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
0f9e006c
AD		 526 .pflip = {
527 .pre_page_flip = &rs600_pre_page_flip,
528 .page_flip = &rs600_page_flip,
529 .post_page_flip = &rs600_post_page_flip,
530 },
3ae19b75 531 .wait_for_vblank = &avivo_wait_for_vblank,
89e5181f 532 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
48e7a5f1
DV		 533};
534
535static struct radeon_asic rs690_asic = {
536 .init = &rs690_init,
537 .fini = &rs690_fini,
538 .suspend = &rs690_suspend,
539 .resume = &rs690_resume,
540 .vga_set_state = &r100_vga_set_state,
225758d8 541 .gpu_is_lockup = &r300_gpu_is_lockup,
90aca4d2 542 .asic_reset = &rs600_asic_reset,
48e7a5f1
DV		 543 .gart_tlb_flush = &rs400_gart_tlb_flush,
544 .gart_set_page = &rs400_gart_set_page,
48e7a5f1
DV		 545 .ring_start = &r300_ring_start,
546 .ring_test = &r100_ring_test,
4c87bc26
CK		 547 .ring = {
548 [RADEON_RING_TYPE_GFX_INDEX] = {
549 .ib_execute = &r100_ring_ib_execute,
550 .emit_fence = &r300_fence_ring_emit,
551 .emit_semaphore = &r100_semaphore_ring_emit,
552 }
553 },
48e7a5f1
DV		 554 .irq_set = &rs600_irq_set,
555 .irq_process = &rs600_irq_process,
556 .get_vblank_counter = &rs600_get_vblank_counter,
48e7a5f1
DV		 557 .cs_parse = &r300_cs_parse,
558 .copy_blit = &r100_copy_blit,
559 .copy_dma = &r200_copy_dma,
560 .copy = &r200_copy_dma,
561 .get_engine_clock = &radeon_atom_get_engine_clock,
562 .set_engine_clock = &radeon_atom_set_engine_clock,
563 .get_memory_clock = &radeon_atom_get_memory_clock,
564 .set_memory_clock = &radeon_atom_set_memory_clock,
565 .get_pcie_lanes = NULL,
566 .set_pcie_lanes = NULL,
567 .set_clock_gating = &radeon_atom_set_clock_gating,
568 .set_surface_reg = r100_set_surface_reg,
569 .clear_surface_reg = r100_clear_surface_reg,
570 .bandwidth_update = &rs690_bandwidth_update,
901ea57d
AD		 571 .hpd = {
572 .init = &rs600_hpd_init,
573 .fini = &rs600_hpd_fini,
574 .sense = &rs600_hpd_sense,
575 .set_polarity = &rs600_hpd_set_polarity,
576 },
48e7a5f1 577 .ioctl_wait_idle = NULL,
def9ba9c 578 .gui_idle = &r100_gui_idle,
49e02b73
AD		 579 .pm_misc = &rs600_pm_misc,
580 .pm_prepare = &rs600_pm_prepare,
581 .pm_finish = &rs600_pm_finish,
ce8f5370
AD		 582 .pm_init_profile = &r420_pm_init_profile,
583 .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
0f9e006c
AD		 584 .pflip = {
585 .pre_page_flip = &rs600_pre_page_flip,
586 .page_flip = &rs600_page_flip,
587 .post_page_flip = &rs600_post_page_flip,
588 },
3ae19b75 589 .wait_for_vblank = &avivo_wait_for_vblank,
89e5181f 590 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
48e7a5f1
DV		 591};
592
593static struct radeon_asic rv515_asic = {
594 .init = &rv515_init,
595 .fini = &rv515_fini,
596 .suspend = &rv515_suspend,
597 .resume = &rv515_resume,
598 .vga_set_state = &r100_vga_set_state,
225758d8 599 .gpu_is_lockup = &r300_gpu_is_lockup,
90aca4d2 600 .asic_reset = &rs600_asic_reset,
48e7a5f1
DV		 601 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
602 .gart_set_page = &rv370_pcie_gart_set_page,
48e7a5f1
DV		 603 .ring_start = &rv515_ring_start,
604 .ring_test = &r100_ring_test,
4c87bc26
CK		 605 .ring = {
606 [RADEON_RING_TYPE_GFX_INDEX] = {
607 .ib_execute = &r100_ring_ib_execute,
608 .emit_fence = &r300_fence_ring_emit,
609 .emit_semaphore = &r100_semaphore_ring_emit,
610 }
611 },
48e7a5f1
DV		 612 .irq_set = &rs600_irq_set,
613 .irq_process = &rs600_irq_process,
614 .get_vblank_counter = &rs600_get_vblank_counter,
48e7a5f1
DV		 615 .cs_parse = &r300_cs_parse,
616 .copy_blit = &r100_copy_blit,
617 .copy_dma = &r200_copy_dma,
618 .copy = &r100_copy_blit,
619 .get_engine_clock = &radeon_atom_get_engine_clock,
620 .set_engine_clock = &radeon_atom_set_engine_clock,
621 .get_memory_clock = &radeon_atom_get_memory_clock,
622 .set_memory_clock = &radeon_atom_set_memory_clock,
623 .get_pcie_lanes = &rv370_get_pcie_lanes,
624 .set_pcie_lanes = &rv370_set_pcie_lanes,
625 .set_clock_gating = &radeon_atom_set_clock_gating,
626 .set_surface_reg = r100_set_surface_reg,
627 .clear_surface_reg = r100_clear_surface_reg,
628 .bandwidth_update = &rv515_bandwidth_update,
901ea57d
AD		 629 .hpd = {
630 .init = &rs600_hpd_init,
631 .fini = &rs600_hpd_fini,
632 .sense = &rs600_hpd_sense,
633 .set_polarity = &rs600_hpd_set_polarity,
634 },
48e7a5f1 635 .ioctl_wait_idle = NULL,
def9ba9c 636 .gui_idle = &r100_gui_idle,
49e02b73
AD		 637 .pm_misc = &rs600_pm_misc,
638 .pm_prepare = &rs600_pm_prepare,
639 .pm_finish = &rs600_pm_finish,
ce8f5370
AD		 640 .pm_init_profile = &r420_pm_init_profile,
641 .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
0f9e006c
AD		 642 .pflip = {
643 .pre_page_flip = &rs600_pre_page_flip,
644 .page_flip = &rs600_page_flip,
645 .post_page_flip = &rs600_post_page_flip,
646 },
3ae19b75 647 .wait_for_vblank = &avivo_wait_for_vblank,
89e5181f 648 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
48e7a5f1
DV		 649};
650
651static struct radeon_asic r520_asic = {
652 .init = &r520_init,
653 .fini = &rv515_fini,
654 .suspend = &rv515_suspend,
655 .resume = &r520_resume,
656 .vga_set_state = &r100_vga_set_state,
225758d8 657 .gpu_is_lockup = &r300_gpu_is_lockup,
90aca4d2 658 .asic_reset = &rs600_asic_reset,
48e7a5f1
DV		 659 .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
660 .gart_set_page = &rv370_pcie_gart_set_page,
48e7a5f1
DV		 661 .ring_start = &rv515_ring_start,
662 .ring_test = &r100_ring_test,
4c87bc26
CK		 663 .ring = {
664 [RADEON_RING_TYPE_GFX_INDEX] = {
665 .ib_execute = &r100_ring_ib_execute,
666 .emit_fence = &r300_fence_ring_emit,
667 .emit_semaphore = &r100_semaphore_ring_emit,
668 }
669 },
48e7a5f1
DV		 670 .irq_set = &rs600_irq_set,
671 .irq_process = &rs600_irq_process,
672 .get_vblank_counter = &rs600_get_vblank_counter,
48e7a5f1
DV		 673 .cs_parse = &r300_cs_parse,
674 .copy_blit = &r100_copy_blit,
675 .copy_dma = &r200_copy_dma,
676 .copy = &r100_copy_blit,
677 .get_engine_clock = &radeon_atom_get_engine_clock,
678 .set_engine_clock = &radeon_atom_set_engine_clock,
679 .get_memory_clock = &radeon_atom_get_memory_clock,
680 .set_memory_clock = &radeon_atom_set_memory_clock,
681 .get_pcie_lanes = &rv370_get_pcie_lanes,
682 .set_pcie_lanes = &rv370_set_pcie_lanes,
683 .set_clock_gating = &radeon_atom_set_clock_gating,
684 .set_surface_reg = r100_set_surface_reg,
685 .clear_surface_reg = r100_clear_surface_reg,
686 .bandwidth_update = &rv515_bandwidth_update,
901ea57d
AD		 687 .hpd = {
688 .init = &rs600_hpd_init,
689 .fini = &rs600_hpd_fini,
690 .sense = &rs600_hpd_sense,
691 .set_polarity = &rs600_hpd_set_polarity,
692 },
48e7a5f1 693 .ioctl_wait_idle = NULL,
def9ba9c 694 .gui_idle = &r100_gui_idle,
49e02b73
AD		 695 .pm_misc = &rs600_pm_misc,
696 .pm_prepare = &rs600_pm_prepare,
697 .pm_finish = &rs600_pm_finish,
ce8f5370
AD		 698 .pm_init_profile = &r420_pm_init_profile,
699 .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
0f9e006c
AD		 700 .pflip = {
701 .pre_page_flip = &rs600_pre_page_flip,
702 .page_flip = &rs600_page_flip,
703 .post_page_flip = &rs600_post_page_flip,
704 },
3ae19b75 705 .wait_for_vblank = &avivo_wait_for_vblank,
89e5181f 706 .mc_wait_for_idle = &r520_mc_wait_for_idle,
48e7a5f1
DV		 707};
708
709static struct radeon_asic r600_asic = {
710 .init = &r600_init,
711 .fini = &r600_fini,
712 .suspend = &r600_suspend,
713 .resume = &r600_resume,
48e7a5f1 714 .vga_set_state = &r600_vga_set_state,
225758d8 715 .gpu_is_lockup = &r600_gpu_is_lockup,
a2d07b74 716 .asic_reset = &r600_asic_reset,
48e7a5f1
DV		 717 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
718 .gart_set_page = &rs600_gart_set_page,
719 .ring_test = &r600_ring_test,
4c87bc26
CK		 720 .ring = {
721 [RADEON_RING_TYPE_GFX_INDEX] = {
722 .ib_execute = &r600_ring_ib_execute,
723 .emit_fence = &r600_fence_ring_emit,
724 .emit_semaphore = &r600_semaphore_ring_emit,
725 }
726 },
48e7a5f1
DV		 727 .irq_set = &r600_irq_set,
728 .irq_process = &r600_irq_process,
729 .get_vblank_counter = &rs600_get_vblank_counter,
48e7a5f1
DV		 730 .cs_parse = &r600_cs_parse,
731 .copy_blit = &r600_copy_blit,
20633442 732 .copy_dma = NULL,
48e7a5f1
DV		 733 .copy = &r600_copy_blit,
734 .get_engine_clock = &radeon_atom_get_engine_clock,
735 .set_engine_clock = &radeon_atom_set_engine_clock,
736 .get_memory_clock = &radeon_atom_get_memory_clock,
737 .set_memory_clock = &radeon_atom_set_memory_clock,
3313e3d4
AD		 738 .get_pcie_lanes = &r600_get_pcie_lanes,
739 .set_pcie_lanes = &r600_set_pcie_lanes,
48e7a5f1
DV		 740 .set_clock_gating = NULL,
741 .set_surface_reg = r600_set_surface_reg,
742 .clear_surface_reg = r600_clear_surface_reg,
743 .bandwidth_update = &rv515_bandwidth_update,
901ea57d
AD		 744 .hpd = {
745 .init = &r600_hpd_init,
746 .fini = &r600_hpd_fini,
747 .sense = &r600_hpd_sense,
748 .set_polarity = &r600_hpd_set_polarity,
749 },
48e7a5f1 750 .ioctl_wait_idle = r600_ioctl_wait_idle,
def9ba9c 751 .gui_idle = &r600_gui_idle,
49e02b73
AD		 752 .pm_misc = &r600_pm_misc,
753 .pm_prepare = &rs600_pm_prepare,
754 .pm_finish = &rs600_pm_finish,
ce8f5370
AD		 755 .pm_init_profile = &r600_pm_init_profile,
756 .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
0f9e006c
AD		 757 .pflip = {
758 .pre_page_flip = &rs600_pre_page_flip,
759 .page_flip = &rs600_page_flip,
760 .post_page_flip = &rs600_post_page_flip,
761 },
3ae19b75 762 .wait_for_vblank = &avivo_wait_for_vblank,
89e5181f 763 .mc_wait_for_idle = &r600_mc_wait_for_idle,
48e7a5f1
DV		 764};
765
f47299c5
AD		 766static struct radeon_asic rs780_asic = {
767 .init = &r600_init,
768 .fini = &r600_fini,
769 .suspend = &r600_suspend,
770 .resume = &r600_resume,
90aca4d2 771 .gpu_is_lockup = &r600_gpu_is_lockup,
f47299c5 772 .vga_set_state = &r600_vga_set_state,
a2d07b74 773 .asic_reset = &r600_asic_reset,
f47299c5
AD		 774 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
775 .gart_set_page = &rs600_gart_set_page,
776 .ring_test = &r600_ring_test,
4c87bc26
CK		 777 .ring = {
778 [RADEON_RING_TYPE_GFX_INDEX] = {
779 .ib_execute = &r600_ring_ib_execute,
780 .emit_fence = &r600_fence_ring_emit,
781 .emit_semaphore = &r600_semaphore_ring_emit,
782 }
783 },
f47299c5
AD		 784 .irq_set = &r600_irq_set,
785 .irq_process = &r600_irq_process,
786 .get_vblank_counter = &rs600_get_vblank_counter,
f47299c5
AD		 787 .cs_parse = &r600_cs_parse,
788 .copy_blit = &r600_copy_blit,
20633442 789 .copy_dma = NULL,
f47299c5
AD		 790 .copy = &r600_copy_blit,
791 .get_engine_clock = &radeon_atom_get_engine_clock,
792 .set_engine_clock = &radeon_atom_set_engine_clock,
793 .get_memory_clock = NULL,
794 .set_memory_clock = NULL,
795 .get_pcie_lanes = NULL,
796 .set_pcie_lanes = NULL,
797 .set_clock_gating = NULL,
798 .set_surface_reg = r600_set_surface_reg,
799 .clear_surface_reg = r600_clear_surface_reg,
800 .bandwidth_update = &rs690_bandwidth_update,
901ea57d
AD		 801 .hpd = {
802 .init = &r600_hpd_init,
803 .fini = &r600_hpd_fini,
804 .sense = &r600_hpd_sense,
805 .set_polarity = &r600_hpd_set_polarity,
806 },
f47299c5 807 .ioctl_wait_idle = r600_ioctl_wait_idle,
def9ba9c 808 .gui_idle = &r600_gui_idle,
49e02b73
AD		 809 .pm_misc = &r600_pm_misc,
810 .pm_prepare = &rs600_pm_prepare,
811 .pm_finish = &rs600_pm_finish,
ce8f5370
AD		 812 .pm_init_profile = &rs780_pm_init_profile,
813 .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
0f9e006c
AD		 814 .pflip = {
815 .pre_page_flip = &rs600_pre_page_flip,
816 .page_flip = &rs600_page_flip,
817 .post_page_flip = &rs600_post_page_flip,
818 },
3ae19b75 819 .wait_for_vblank = &avivo_wait_for_vblank,
89e5181f 820 .mc_wait_for_idle = &r600_mc_wait_for_idle,
f47299c5
AD		 821};
822
48e7a5f1
DV		 823static struct radeon_asic rv770_asic = {
824 .init = &rv770_init,
825 .fini = &rv770_fini,
826 .suspend = &rv770_suspend,
827 .resume = &rv770_resume,
a2d07b74 828 .asic_reset = &r600_asic_reset,
225758d8 829 .gpu_is_lockup = &r600_gpu_is_lockup,
48e7a5f1
DV		 830 .vga_set_state = &r600_vga_set_state,
831 .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
832 .gart_set_page = &rs600_gart_set_page,
833 .ring_test = &r600_ring_test,
4c87bc26
CK		 834 .ring = {
835 [RADEON_RING_TYPE_GFX_INDEX] = {
836 .ib_execute = &r600_ring_ib_execute,
837 .emit_fence = &r600_fence_ring_emit,
838 .emit_semaphore = &r600_semaphore_ring_emit,
839 }
840 },
48e7a5f1
DV		 841 .irq_set = &r600_irq_set,
842 .irq_process = &r600_irq_process,
843 .get_vblank_counter = &rs600_get_vblank_counter,
48e7a5f1
DV		 844 .cs_parse = &r600_cs_parse,
845 .copy_blit = &r600_copy_blit,
20633442 846 .copy_dma = NULL,
48e7a5f1
DV		 847 .copy = &r600_copy_blit,
848 .get_engine_clock = &radeon_atom_get_engine_clock,
849 .set_engine_clock = &radeon_atom_set_engine_clock,
850 .get_memory_clock = &radeon_atom_get_memory_clock,
851 .set_memory_clock = &radeon_atom_set_memory_clock,
3313e3d4
AD		 852 .get_pcie_lanes = &r600_get_pcie_lanes,
853 .set_pcie_lanes = &r600_set_pcie_lanes,
48e7a5f1
DV		 854 .set_clock_gating = &radeon_atom_set_clock_gating,
855 .set_surface_reg = r600_set_surface_reg,
856 .clear_surface_reg = r600_clear_surface_reg,
857 .bandwidth_update = &rv515_bandwidth_update,
901ea57d
AD		 858 .hpd = {
859 .init = &r600_hpd_init,
860 .fini = &r600_hpd_fini,
861 .sense = &r600_hpd_sense,
862 .set_polarity = &r600_hpd_set_polarity,
863 },
48e7a5f1 864 .ioctl_wait_idle = r600_ioctl_wait_idle,
def9ba9c 865 .gui_idle = &r600_gui_idle,
49e02b73
AD		 866 .pm_misc = &rv770_pm_misc,
867 .pm_prepare = &rs600_pm_prepare,
868 .pm_finish = &rs600_pm_finish,
ce8f5370
AD		 869 .pm_init_profile = &r600_pm_init_profile,
870 .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
0f9e006c
AD		 871 .pflip = {
872 .pre_page_flip = &rs600_pre_page_flip,
873 .page_flip = &rv770_page_flip,
874 .post_page_flip = &rs600_post_page_flip,
875 },
3ae19b75 876 .wait_for_vblank = &avivo_wait_for_vblank,
89e5181f 877 .mc_wait_for_idle = &r600_mc_wait_for_idle,
48e7a5f1
DV		 878};
879
880static struct radeon_asic evergreen_asic = {
881 .init = &evergreen_init,
882 .fini = &evergreen_fini,
883 .suspend = &evergreen_suspend,
884 .resume = &evergreen_resume,
225758d8 885 .gpu_is_lockup = &evergreen_gpu_is_lockup,
a2d07b74 886 .asic_reset = &evergreen_asic_reset,
48e7a5f1 887 .vga_set_state = &r600_vga_set_state,
0fcdb61e 888 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
48e7a5f1 889 .gart_set_page = &rs600_gart_set_page,
fe251e2f 890 .ring_test = &r600_ring_test,
4c87bc26
CK		 891 .ring = {
892 [RADEON_RING_TYPE_GFX_INDEX] = {
893 .ib_execute = &evergreen_ring_ib_execute,
894 .emit_fence = &r600_fence_ring_emit,
895 .emit_semaphore = &r600_semaphore_ring_emit,
896 }
897 },
45f9a39b
AD		 898 .irq_set = &evergreen_irq_set,
899 .irq_process = &evergreen_irq_process,
900 .get_vblank_counter = &evergreen_get_vblank_counter,
cb5fcbd5 901 .cs_parse = &evergreen_cs_parse,
fb3d9e97 902 .copy_blit = &r600_copy_blit,
20633442 903 .copy_dma = NULL,
fb3d9e97 904 .copy = &r600_copy_blit,
48e7a5f1
DV		 905 .get_engine_clock = &radeon_atom_get_engine_clock,
906 .set_engine_clock = &radeon_atom_set_engine_clock,
907 .get_memory_clock = &radeon_atom_get_memory_clock,
908 .set_memory_clock = &radeon_atom_set_memory_clock,
3313e3d4
AD		 909 .get_pcie_lanes = &r600_get_pcie_lanes,
910 .set_pcie_lanes = &r600_set_pcie_lanes,
48e7a5f1
DV		 911 .set_clock_gating = NULL,
912 .set_surface_reg = r600_set_surface_reg,
913 .clear_surface_reg = r600_clear_surface_reg,
914 .bandwidth_update = &evergreen_bandwidth_update,
901ea57d
AD		 915 .hpd = {
916 .init = &evergreen_hpd_init,
917 .fini = &evergreen_hpd_fini,
918 .sense = &evergreen_hpd_sense,
919 .set_polarity = &evergreen_hpd_set_polarity,
920 },
97bfd0ac 921 .ioctl_wait_idle = r600_ioctl_wait_idle,
def9ba9c 922 .gui_idle = &r600_gui_idle,
49e02b73
AD		 923 .pm_misc = &evergreen_pm_misc,
924 .pm_prepare = &evergreen_pm_prepare,
925 .pm_finish = &evergreen_pm_finish,
ce8f5370
AD		 926 .pm_init_profile = &r600_pm_init_profile,
927 .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
0f9e006c
AD		 928 .pflip = {
929 .pre_page_flip = &evergreen_pre_page_flip,
930 .page_flip = &evergreen_page_flip,
931 .post_page_flip = &evergreen_post_page_flip,
932 },
3ae19b75 933 .wait_for_vblank = &dce4_wait_for_vblank,
89e5181f 934 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
48e7a5f1
DV		 935};
936
958261d1
AD		 937static struct radeon_asic sumo_asic = {
938 .init = &evergreen_init,
939 .fini = &evergreen_fini,
940 .suspend = &evergreen_suspend,
941 .resume = &evergreen_resume,
958261d1
AD		 942 .gpu_is_lockup = &evergreen_gpu_is_lockup,
943 .asic_reset = &evergreen_asic_reset,
944 .vga_set_state = &r600_vga_set_state,
945 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
946 .gart_set_page = &rs600_gart_set_page,
947 .ring_test = &r600_ring_test,
4c87bc26
CK		 948 .ring = {
949 [RADEON_RING_TYPE_GFX_INDEX] = {
950 .ib_execute = &evergreen_ring_ib_execute,
951 .emit_fence = &r600_fence_ring_emit,
952 .emit_semaphore = &r600_semaphore_ring_emit,
953 }
954 },
958261d1
AD		 955 .irq_set = &evergreen_irq_set,
956 .irq_process = &evergreen_irq_process,
957 .get_vblank_counter = &evergreen_get_vblank_counter,
958261d1 958 .cs_parse = &evergreen_cs_parse,
fb3d9e97 959 .copy_blit = &r600_copy_blit,
20633442 960 .copy_dma = NULL,
fb3d9e97 961 .copy = &r600_copy_blit,
958261d1
AD		 962 .get_engine_clock = &radeon_atom_get_engine_clock,
963 .set_engine_clock = &radeon_atom_set_engine_clock,
964 .get_memory_clock = NULL,
965 .set_memory_clock = NULL,
966 .get_pcie_lanes = NULL,
967 .set_pcie_lanes = NULL,
968 .set_clock_gating = NULL,
969 .set_surface_reg = r600_set_surface_reg,
970 .clear_surface_reg = r600_clear_surface_reg,
971 .bandwidth_update = &evergreen_bandwidth_update,
901ea57d
AD		 972 .hpd = {
973 .init = &evergreen_hpd_init,
974 .fini = &evergreen_hpd_fini,
975 .sense = &evergreen_hpd_sense,
976 .set_polarity = &evergreen_hpd_set_polarity,
977 },
97bfd0ac 978 .ioctl_wait_idle = r600_ioctl_wait_idle,
958261d1
AD		 979 .gui_idle = &r600_gui_idle,
980 .pm_misc = &evergreen_pm_misc,
981 .pm_prepare = &evergreen_pm_prepare,
982 .pm_finish = &evergreen_pm_finish,
a4c9e2ee 983 .pm_init_profile = &sumo_pm_init_profile,
958261d1 984 .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
0f9e006c
AD		 985 .pflip = {
986 .pre_page_flip = &evergreen_pre_page_flip,
987 .page_flip = &evergreen_page_flip,
988 .post_page_flip = &evergreen_post_page_flip,
989 },
3ae19b75 990 .wait_for_vblank = &dce4_wait_for_vblank,
89e5181f 991 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
958261d1
AD		 992};
993
a43b7665
AD		 994static struct radeon_asic btc_asic = {
995 .init = &evergreen_init,
996 .fini = &evergreen_fini,
997 .suspend = &evergreen_suspend,
998 .resume = &evergreen_resume,
a43b7665
AD		 999 .gpu_is_lockup = &evergreen_gpu_is_lockup,
1000 .asic_reset = &evergreen_asic_reset,
1001 .vga_set_state = &r600_vga_set_state,
1002 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
1003 .gart_set_page = &rs600_gart_set_page,
1004 .ring_test = &r600_ring_test,
4c87bc26
CK		 1005 .ring = {
1006 [RADEON_RING_TYPE_GFX_INDEX] = {
1007 .ib_execute = &evergreen_ring_ib_execute,
1008 .emit_fence = &r600_fence_ring_emit,
1009 .emit_semaphore = &r600_semaphore_ring_emit,
1010 }
1011 },
a43b7665
AD		 1012 .irq_set = &evergreen_irq_set,
1013 .irq_process = &evergreen_irq_process,
1014 .get_vblank_counter = &evergreen_get_vblank_counter,
a43b7665 1015 .cs_parse = &evergreen_cs_parse,
fb3d9e97 1016 .copy_blit = &r600_copy_blit,
20633442 1017 .copy_dma = NULL,
fb3d9e97 1018 .copy = &r600_copy_blit,
a43b7665
AD		 1019 .get_engine_clock = &radeon_atom_get_engine_clock,
1020 .set_engine_clock = &radeon_atom_set_engine_clock,
1021 .get_memory_clock = &radeon_atom_get_memory_clock,
1022 .set_memory_clock = &radeon_atom_set_memory_clock,
1023 .get_pcie_lanes = NULL,
1024 .set_pcie_lanes = NULL,
1025 .set_clock_gating = NULL,
1026 .set_surface_reg = r600_set_surface_reg,
1027 .clear_surface_reg = r600_clear_surface_reg,
1028 .bandwidth_update = &evergreen_bandwidth_update,
901ea57d
AD		 1029 .hpd = {
1030 .init = &evergreen_hpd_init,
1031 .fini = &evergreen_hpd_fini,
1032 .sense = &evergreen_hpd_sense,
1033 .set_polarity = &evergreen_hpd_set_polarity,
1034 },
97bfd0ac 1035 .ioctl_wait_idle = r600_ioctl_wait_idle,
a43b7665
AD		 1036 .gui_idle = &r600_gui_idle,
1037 .pm_misc = &evergreen_pm_misc,
1038 .pm_prepare = &evergreen_pm_prepare,
1039 .pm_finish = &evergreen_pm_finish,
1040 .pm_init_profile = &r600_pm_init_profile,
1041 .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
0f9e006c
AD		 1042 .pflip = {
1043 .pre_page_flip = &evergreen_pre_page_flip,
1044 .page_flip = &evergreen_page_flip,
1045 .post_page_flip = &evergreen_post_page_flip,
1046 },
3ae19b75 1047 .wait_for_vblank = &dce4_wait_for_vblank,
89e5181f 1048 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
a43b7665
AD		 1049};
1050
721604a1
JG		 1051static const struct radeon_vm_funcs cayman_vm_funcs = {
1052 .init = &cayman_vm_init,
1053 .fini = &cayman_vm_fini,
1054 .bind = &cayman_vm_bind,
1055 .unbind = &cayman_vm_unbind,
1056 .tlb_flush = &cayman_vm_tlb_flush,
1057 .page_flags = &cayman_vm_page_flags,
1058 .set_page = &cayman_vm_set_page,
1059};
1060
e3487629
AD		 1061static struct radeon_asic cayman_asic = {
1062 .init = &cayman_init,
1063 .fini = &cayman_fini,
1064 .suspend = &cayman_suspend,
1065 .resume = &cayman_resume,
e3487629
AD		 1066 .gpu_is_lockup = &cayman_gpu_is_lockup,
1067 .asic_reset = &cayman_asic_reset,
1068 .vga_set_state = &r600_vga_set_state,
1069 .gart_tlb_flush = &cayman_pcie_gart_tlb_flush,
1070 .gart_set_page = &rs600_gart_set_page,
1071 .ring_test = &r600_ring_test,
4c87bc26
CK		 1072 .ring = {
1073 [RADEON_RING_TYPE_GFX_INDEX] = {
721604a1
JG		 1074 .ib_execute = &cayman_ring_ib_execute,
1075 .ib_parse = &evergreen_ib_parse,
b40e7e16 1076 .emit_fence = &cayman_fence_ring_emit,
4c87bc26
CK		 1077 .emit_semaphore = &r600_semaphore_ring_emit,
1078 },
1079 [CAYMAN_RING_TYPE_CP1_INDEX] = {
721604a1
JG		 1080 .ib_execute = &cayman_ring_ib_execute,
1081 .ib_parse = &evergreen_ib_parse,
b40e7e16 1082 .emit_fence = &cayman_fence_ring_emit,
4c87bc26
CK		 1083 .emit_semaphore = &r600_semaphore_ring_emit,
1084 },
1085 [CAYMAN_RING_TYPE_CP2_INDEX] = {
721604a1
JG		 1086 .ib_execute = &cayman_ring_ib_execute,
1087 .ib_parse = &evergreen_ib_parse,
b40e7e16 1088 .emit_fence = &cayman_fence_ring_emit,
4c87bc26
CK		 1089 .emit_semaphore = &r600_semaphore_ring_emit,
1090 }
1091 },
e3487629
AD		 1092 .irq_set = &evergreen_irq_set,
1093 .irq_process = &evergreen_irq_process,
1094 .get_vblank_counter = &evergreen_get_vblank_counter,
e3487629 1095 .cs_parse = &evergreen_cs_parse,
fb3d9e97 1096 .copy_blit = &r600_copy_blit,
20633442 1097 .copy_dma = NULL,
fb3d9e97 1098 .copy = &r600_copy_blit,
e3487629
AD		 1099 .get_engine_clock = &radeon_atom_get_engine_clock,
1100 .set_engine_clock = &radeon_atom_set_engine_clock,
1101 .get_memory_clock = &radeon_atom_get_memory_clock,
1102 .set_memory_clock = &radeon_atom_set_memory_clock,
1103 .get_pcie_lanes = NULL,
1104 .set_pcie_lanes = NULL,
1105 .set_clock_gating = NULL,
1106 .set_surface_reg = r600_set_surface_reg,
1107 .clear_surface_reg = r600_clear_surface_reg,
1108 .bandwidth_update = &evergreen_bandwidth_update,
901ea57d
AD		 1109 .hpd = {
1110 .init = &evergreen_hpd_init,
1111 .fini = &evergreen_hpd_fini,
1112 .sense = &evergreen_hpd_sense,
1113 .set_polarity = &evergreen_hpd_set_polarity,
1114 },
97bfd0ac 1115 .ioctl_wait_idle = r600_ioctl_wait_idle,
e3487629
AD		 1116 .gui_idle = &r600_gui_idle,
1117 .pm_misc = &evergreen_pm_misc,
1118 .pm_prepare = &evergreen_pm_prepare,
1119 .pm_finish = &evergreen_pm_finish,
1120 .pm_init_profile = &r600_pm_init_profile,
1121 .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
0f9e006c
AD		 1122 .pflip = {
1123 .pre_page_flip = &evergreen_pre_page_flip,
1124 .page_flip = &evergreen_page_flip,
1125 .post_page_flip = &evergreen_post_page_flip,
1126 },
3ae19b75 1127 .wait_for_vblank = &dce4_wait_for_vblank,
89e5181f 1128 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
e3487629
AD		 1129};
1130
0a10c851
DV		 1131int radeon_asic_init(struct radeon_device *rdev)
1132{
1133 radeon_register_accessor_init(rdev);
ba7e05e9
AD		 1134
1135 /* set the number of crtcs */
1136 if (rdev->flags & RADEON_SINGLE_CRTC)
1137 rdev->num_crtc = 1;
1138 else
1139 rdev->num_crtc = 2;
1140
3000bf39
AD		 1141 /* set the ring used for bo copies */
1142 rdev->copy_ring = RADEON_RING_TYPE_GFX_INDEX;
1143
0a10c851
DV		 1144 switch (rdev->family) {
1145 case CHIP_R100:
1146 case CHIP_RV100:
1147 case CHIP_RS100:
1148 case CHIP_RV200:
1149 case CHIP_RS200:
1150 rdev->asic = &r100_asic;
1151 break;
1152 case CHIP_R200:
1153 case CHIP_RV250:
1154 case CHIP_RS300:
1155 case CHIP_RV280:
1156 rdev->asic = &r200_asic;
1157 break;
1158 case CHIP_R300:
1159 case CHIP_R350:
1160 case CHIP_RV350:
1161 case CHIP_RV380:
1162 if (rdev->flags & RADEON_IS_PCIE)
1163 rdev->asic = &r300_asic_pcie;
1164 else
1165 rdev->asic = &r300_asic;
1166 break;
1167 case CHIP_R420:
1168 case CHIP_R423:
1169 case CHIP_RV410:
1170 rdev->asic = &r420_asic;
07bb084c
AD		 1171 /* handle macs */
1172 if (rdev->bios == NULL) {
1173 rdev->asic->get_engine_clock = &radeon_legacy_get_engine_clock;
1174 rdev->asic->set_engine_clock = &radeon_legacy_set_engine_clock;
1175 rdev->asic->get_memory_clock = &radeon_legacy_get_memory_clock;
1176 rdev->asic->set_memory_clock = NULL;
1177 }
0a10c851
DV		 1178 break;
1179 case CHIP_RS400:
1180 case CHIP_RS480:
1181 rdev->asic = &rs400_asic;
1182 break;
1183 case CHIP_RS600:
1184 rdev->asic = &rs600_asic;
1185 break;
1186 case CHIP_RS690:
1187 case CHIP_RS740:
1188 rdev->asic = &rs690_asic;
1189 break;
1190 case CHIP_RV515:
1191 rdev->asic = &rv515_asic;
1192 break;
1193 case CHIP_R520:
1194 case CHIP_RV530:
1195 case CHIP_RV560:
1196 case CHIP_RV570:
1197 case CHIP_R580:
1198 rdev->asic = &r520_asic;
1199 break;
1200 case CHIP_R600:
1201 case CHIP_RV610:
1202 case CHIP_RV630:
1203 case CHIP_RV620:
1204 case CHIP_RV635:
1205 case CHIP_RV670:
f47299c5
AD		 1206 rdev->asic = &r600_asic;
1207 break;
0a10c851
DV		 1208 case CHIP_RS780:
1209 case CHIP_RS880:
f47299c5 1210 rdev->asic = &rs780_asic;
0a10c851
DV		 1211 break;
1212 case CHIP_RV770:
1213 case CHIP_RV730:
1214 case CHIP_RV710:
1215 case CHIP_RV740:
1216 rdev->asic = &rv770_asic;
1217 break;
1218 case CHIP_CEDAR:
1219 case CHIP_REDWOOD:
1220 case CHIP_JUNIPER:
1221 case CHIP_CYPRESS:
1222 case CHIP_HEMLOCK:
ba7e05e9
AD		 1223 /* set num crtcs */
1224 if (rdev->family == CHIP_CEDAR)
1225 rdev->num_crtc = 4;
1226 else
1227 rdev->num_crtc = 6;
0a10c851
DV		 1228 rdev->asic = &evergreen_asic;
1229 break;
958261d1 1230 case CHIP_PALM:
89da5a37
AD		 1231 case CHIP_SUMO:
1232 case CHIP_SUMO2:
958261d1
AD		 1233 rdev->asic = &sumo_asic;
1234 break;
a43b7665
AD		 1235 case CHIP_BARTS:
1236 case CHIP_TURKS:
1237 case CHIP_CAICOS:
ba7e05e9
AD		 1238 /* set num crtcs */
1239 if (rdev->family == CHIP_CAICOS)
1240 rdev->num_crtc = 4;
1241 else
1242 rdev->num_crtc = 6;
a43b7665
AD		 1243 rdev->asic = &btc_asic;
1244 break;
e3487629
AD		 1245 case CHIP_CAYMAN:
1246 rdev->asic = &cayman_asic;
ba7e05e9
AD		 1247 /* set num crtcs */
1248 rdev->num_crtc = 6;
721604a1 1249 rdev->vm_manager.funcs = &cayman_vm_funcs;
e3487629 1250 break;
0a10c851
DV		 1251 default:
1252 /* FIXME: not supported yet */
1253 return -EINVAL;
1254 }
1255
1256 if (rdev->flags & RADEON_IS_IGP) {
1257 rdev->asic->get_memory_clock = NULL;
1258 rdev->asic->set_memory_clock = NULL;
1259 }
1260
1261 return 0;
1262}
1263
Linux kernel - Deliverables
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