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drm/radeon: add get_allowed_info_register function for r1xx-r5xx
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_asic.c
CommitLineData
0a10c851
DV		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/console.h>
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
33#include <linux/vgaarb.h>
34#include <linux/vga_switcheroo.h>
35#include "radeon_reg.h"
36#include "radeon.h"
37#include "radeon_asic.h"
38#include "atom.h"
39
40/*
41 * Registers accessors functions.
42 */
abf1dc67
AD		 43/**
44 * radeon_invalid_rreg - dummy reg read function
45 *
46 * @rdev: radeon device pointer
47 * @reg: offset of register
48 *
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
52 */
0a10c851
DV		 53static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54{
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
56 BUG_ON(1);
57 return 0;
58}
59
abf1dc67
AD		 60/**
61 * radeon_invalid_wreg - dummy reg write function
62 *
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
66 *
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
69 */
0a10c851
DV		 70static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
71{
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
73 reg, v);
74 BUG_ON(1);
75}
76
abf1dc67
AD		 77/**
78 * radeon_register_accessor_init - sets up the register accessor callbacks
79 *
80 * @rdev: radeon device pointer
81 *
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
84 */
0a10c851
DV		 85static void radeon_register_accessor_init(struct radeon_device *rdev)
86{
87 rdev->mc_rreg = &radeon_invalid_rreg;
88 rdev->mc_wreg = &radeon_invalid_wreg;
89 rdev->pll_rreg = &radeon_invalid_rreg;
90 rdev->pll_wreg = &radeon_invalid_wreg;
91 rdev->pciep_rreg = &radeon_invalid_rreg;
92 rdev->pciep_wreg = &radeon_invalid_wreg;
93
94 /* Don't change order as we are overridding accessor. */
95 if (rdev->family < CHIP_RV515) {
96 rdev->pcie_reg_mask = 0xff;
97 } else {
98 rdev->pcie_reg_mask = 0x7ff;
99 }
100 /* FIXME: not sure here */
101 if (rdev->family <= CHIP_R580) {
102 rdev->pll_rreg = &r100_pll_rreg;
103 rdev->pll_wreg = &r100_pll_wreg;
104 }
105 if (rdev->family >= CHIP_R420) {
106 rdev->mc_rreg = &r420_mc_rreg;
107 rdev->mc_wreg = &r420_mc_wreg;
108 }
109 if (rdev->family >= CHIP_RV515) {
110 rdev->mc_rreg = &rv515_mc_rreg;
111 rdev->mc_wreg = &rv515_mc_wreg;
112 }
113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
114 rdev->mc_rreg = &rs400_mc_rreg;
115 rdev->mc_wreg = &rs400_mc_wreg;
116 }
117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
118 rdev->mc_rreg = &rs690_mc_rreg;
119 rdev->mc_wreg = &rs690_mc_wreg;
120 }
121 if (rdev->family == CHIP_RS600) {
122 rdev->mc_rreg = &rs600_mc_rreg;
123 rdev->mc_wreg = &rs600_mc_wreg;
124 }
65337e60
SL		 125 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
126 rdev->mc_rreg = &rs780_mc_rreg;
127 rdev->mc_wreg = &rs780_mc_wreg;
128 }
6e2c3c0a
AD		 129
130 if (rdev->family >= CHIP_BONAIRE) {
131 rdev->pciep_rreg = &cik_pciep_rreg;
132 rdev->pciep_wreg = &cik_pciep_wreg;
133 } else if (rdev->family >= CHIP_R600) {
0a10c851
DV		 134 rdev->pciep_rreg = &r600_pciep_rreg;
135 rdev->pciep_wreg = &r600_pciep_wreg;
136 }
137}
138
18b53e90
AD		 139static int radeon_invalid_get_allowed_info_register(struct radeon_device *rdev,
140 u32 reg, u32 *val)
141{
142 return -EINVAL;
143}
0a10c851
DV		 144
145/* helper to disable agp */
abf1dc67
AD		 146/**
147 * radeon_agp_disable - AGP disable helper function
148 *
149 * @rdev: radeon device pointer
150 *
151 * Removes AGP flags and changes the gart callbacks on AGP
152 * cards when using the internal gart rather than AGP (all asics).
153 */
0a10c851
DV		 154void radeon_agp_disable(struct radeon_device *rdev)
155{
156 rdev->flags &= ~RADEON_IS_AGP;
157 if (rdev->family >= CHIP_R600) {
158 DRM_INFO("Forcing AGP to PCIE mode\n");
159 rdev->flags |= RADEON_IS_PCIE;
160 } else if (rdev->family >= CHIP_RV515 ||
161 rdev->family == CHIP_RV380 ||
162 rdev->family == CHIP_RV410 ||
163 rdev->family == CHIP_R423) {
164 DRM_INFO("Forcing AGP to PCIE mode\n");
165 rdev->flags |= RADEON_IS_PCIE;
c5b3b850 166 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
cb658906 167 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
c5b3b850 168 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
0a10c851
DV		 169 } else {
170 DRM_INFO("Forcing AGP to PCI mode\n");
171 rdev->flags |= RADEON_IS_PCI;
c5b3b850 172 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
cb658906 173 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
c5b3b850 174 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
0a10c851
DV		 175 }
176 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
177}
178
179/*
180 * ASIC
181 */
76a0df85
CK		 182
183static struct radeon_asic_ring r100_gfx_ring = {
184 .ib_execute = &r100_ring_ib_execute,
185 .emit_fence = &r100_fence_ring_emit,
186 .emit_semaphore = &r100_semaphore_ring_emit,
187 .cs_parse = &r100_cs_parse,
188 .ring_start = &r100_ring_start,
189 .ring_test = &r100_ring_test,
190 .ib_test = &r100_ib_test,
191 .is_lockup = &r100_gpu_is_lockup,
ea31bf69
AD		 192 .get_rptr = &r100_gfx_get_rptr,
193 .get_wptr = &r100_gfx_get_wptr,
194 .set_wptr = &r100_gfx_set_wptr,
76a0df85
CK		 195};
196
48e7a5f1
DV		 197static struct radeon_asic r100_asic = {
198 .init = &r100_init,
199 .fini = &r100_fini,
200 .suspend = &r100_suspend,
201 .resume = &r100_resume,
202 .vga_set_state = &r100_vga_set_state,
a2d07b74 203 .asic_reset = &r100_asic_reset,
124764f1 204 .mmio_hdp_flush = NULL,
54e88e06
AD		 205 .gui_idle = &r100_gui_idle,
206 .mc_wait_for_idle = &r100_mc_wait_for_idle,
18b53e90 207 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
c5b3b850
AD		 208 .gart = {
209 .tlb_flush = &r100_pci_gart_tlb_flush,
cb658906 210 .get_page_entry = &r100_pci_gart_get_page_entry,
c5b3b850
AD		 211 .set_page = &r100_pci_gart_set_page,
212 },
4c87bc26 213 .ring = {
76a0df85 214 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
4c87bc26 215 },
b35ea4ab
AD		 216 .irq = {
217 .set = &r100_irq_set,
218 .process = &r100_irq_process,
219 },
c79a49ca
AD		 220 .display = {
221 .bandwidth_update = &r100_bandwidth_update,
222 .get_vblank_counter = &r100_get_vblank_counter,
223 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 224 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 225 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 226 },
27cd7769
AD		 227 .copy = {
228 .blit = &r100_copy_blit,
229 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
230 .dma = NULL,
231 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
232 .copy = &r100_copy_blit,
233 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
234 },
9e6f3d02
AD		 235 .surface = {
236 .set_reg = r100_set_surface_reg,
237 .clear_reg = r100_clear_surface_reg,
238 },
901ea57d
AD		 239 .hpd = {
240 .init = &r100_hpd_init,
241 .fini = &r100_hpd_fini,
242 .sense = &r100_hpd_sense,
243 .set_polarity = &r100_hpd_set_polarity,
244 },
a02fa397
AD		 245 .pm = {
246 .misc = &r100_pm_misc,
247 .prepare = &r100_pm_prepare,
248 .finish = &r100_pm_finish,
249 .init_profile = &r100_pm_init_profile,
250 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 251 .get_engine_clock = &radeon_legacy_get_engine_clock,
252 .set_engine_clock = &radeon_legacy_set_engine_clock,
253 .get_memory_clock = &radeon_legacy_get_memory_clock,
254 .set_memory_clock = NULL,
255 .get_pcie_lanes = NULL,
256 .set_pcie_lanes = NULL,
257 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 258 },
0f9e006c 259 .pflip = {
0f9e006c 260 .page_flip = &r100_page_flip,
157fa14d 261 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 262 },
48e7a5f1
DV		 263};
264
265static struct radeon_asic r200_asic = {
266 .init = &r100_init,
267 .fini = &r100_fini,
268 .suspend = &r100_suspend,
269 .resume = &r100_resume,
270 .vga_set_state = &r100_vga_set_state,
a2d07b74 271 .asic_reset = &r100_asic_reset,
124764f1 272 .mmio_hdp_flush = NULL,
54e88e06
AD		 273 .gui_idle = &r100_gui_idle,
274 .mc_wait_for_idle = &r100_mc_wait_for_idle,
18b53e90 275 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
c5b3b850
AD		 276 .gart = {
277 .tlb_flush = &r100_pci_gart_tlb_flush,
cb658906 278 .get_page_entry = &r100_pci_gart_get_page_entry,
c5b3b850
AD		 279 .set_page = &r100_pci_gart_set_page,
280 },
4c87bc26 281 .ring = {
76a0df85 282 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
4c87bc26 283 },
b35ea4ab
AD		 284 .irq = {
285 .set = &r100_irq_set,
286 .process = &r100_irq_process,
287 },
c79a49ca
AD		 288 .display = {
289 .bandwidth_update = &r100_bandwidth_update,
290 .get_vblank_counter = &r100_get_vblank_counter,
291 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 292 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 293 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 294 },
27cd7769
AD		 295 .copy = {
296 .blit = &r100_copy_blit,
297 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
298 .dma = &r200_copy_dma,
299 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
300 .copy = &r100_copy_blit,
301 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
302 },
9e6f3d02
AD		 303 .surface = {
304 .set_reg = r100_set_surface_reg,
305 .clear_reg = r100_clear_surface_reg,
306 },
901ea57d
AD		 307 .hpd = {
308 .init = &r100_hpd_init,
309 .fini = &r100_hpd_fini,
310 .sense = &r100_hpd_sense,
311 .set_polarity = &r100_hpd_set_polarity,
312 },
a02fa397
AD		 313 .pm = {
314 .misc = &r100_pm_misc,
315 .prepare = &r100_pm_prepare,
316 .finish = &r100_pm_finish,
317 .init_profile = &r100_pm_init_profile,
318 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 319 .get_engine_clock = &radeon_legacy_get_engine_clock,
320 .set_engine_clock = &radeon_legacy_set_engine_clock,
321 .get_memory_clock = &radeon_legacy_get_memory_clock,
322 .set_memory_clock = NULL,
323 .get_pcie_lanes = NULL,
324 .set_pcie_lanes = NULL,
325 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 326 },
0f9e006c 327 .pflip = {
0f9e006c 328 .page_flip = &r100_page_flip,
157fa14d 329 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 330 },
48e7a5f1
DV		 331};
332
76a0df85
CK		 333static struct radeon_asic_ring r300_gfx_ring = {
334 .ib_execute = &r100_ring_ib_execute,
335 .emit_fence = &r300_fence_ring_emit,
336 .emit_semaphore = &r100_semaphore_ring_emit,
337 .cs_parse = &r300_cs_parse,
338 .ring_start = &r300_ring_start,
339 .ring_test = &r100_ring_test,
340 .ib_test = &r100_ib_test,
341 .is_lockup = &r100_gpu_is_lockup,
ea31bf69
AD		 342 .get_rptr = &r100_gfx_get_rptr,
343 .get_wptr = &r100_gfx_get_wptr,
344 .set_wptr = &r100_gfx_set_wptr,
76a0df85
CK		 345};
346
d8a74e18
AD		 347static struct radeon_asic_ring rv515_gfx_ring = {
348 .ib_execute = &r100_ring_ib_execute,
349 .emit_fence = &r300_fence_ring_emit,
350 .emit_semaphore = &r100_semaphore_ring_emit,
351 .cs_parse = &r300_cs_parse,
352 .ring_start = &rv515_ring_start,
353 .ring_test = &r100_ring_test,
354 .ib_test = &r100_ib_test,
355 .is_lockup = &r100_gpu_is_lockup,
356 .get_rptr = &r100_gfx_get_rptr,
357 .get_wptr = &r100_gfx_get_wptr,
358 .set_wptr = &r100_gfx_set_wptr,
359};
360
48e7a5f1
DV		 361static struct radeon_asic r300_asic = {
362 .init = &r300_init,
363 .fini = &r300_fini,
364 .suspend = &r300_suspend,
365 .resume = &r300_resume,
366 .vga_set_state = &r100_vga_set_state,
a2d07b74 367 .asic_reset = &r300_asic_reset,
124764f1 368 .mmio_hdp_flush = NULL,
54e88e06
AD		 369 .gui_idle = &r100_gui_idle,
370 .mc_wait_for_idle = &r300_mc_wait_for_idle,
18b53e90 371 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
c5b3b850
AD		 372 .gart = {
373 .tlb_flush = &r100_pci_gart_tlb_flush,
cb658906 374 .get_page_entry = &r100_pci_gart_get_page_entry,
c5b3b850
AD		 375 .set_page = &r100_pci_gart_set_page,
376 },
4c87bc26 377 .ring = {
76a0df85 378 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 379 },
b35ea4ab
AD		 380 .irq = {
381 .set = &r100_irq_set,
382 .process = &r100_irq_process,
383 },
c79a49ca
AD		 384 .display = {
385 .bandwidth_update = &r100_bandwidth_update,
386 .get_vblank_counter = &r100_get_vblank_counter,
387 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 388 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 389 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 390 },
27cd7769
AD		 391 .copy = {
392 .blit = &r100_copy_blit,
393 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
394 .dma = &r200_copy_dma,
395 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
396 .copy = &r100_copy_blit,
397 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
398 },
9e6f3d02
AD		 399 .surface = {
400 .set_reg = r100_set_surface_reg,
401 .clear_reg = r100_clear_surface_reg,
402 },
901ea57d
AD		 403 .hpd = {
404 .init = &r100_hpd_init,
405 .fini = &r100_hpd_fini,
406 .sense = &r100_hpd_sense,
407 .set_polarity = &r100_hpd_set_polarity,
408 },
a02fa397
AD		 409 .pm = {
410 .misc = &r100_pm_misc,
411 .prepare = &r100_pm_prepare,
412 .finish = &r100_pm_finish,
413 .init_profile = &r100_pm_init_profile,
414 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 415 .get_engine_clock = &radeon_legacy_get_engine_clock,
416 .set_engine_clock = &radeon_legacy_set_engine_clock,
417 .get_memory_clock = &radeon_legacy_get_memory_clock,
418 .set_memory_clock = NULL,
419 .get_pcie_lanes = &rv370_get_pcie_lanes,
420 .set_pcie_lanes = &rv370_set_pcie_lanes,
421 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 422 },
0f9e006c 423 .pflip = {
0f9e006c 424 .page_flip = &r100_page_flip,
157fa14d 425 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 426 },
48e7a5f1
DV		 427};
428
429static struct radeon_asic r300_asic_pcie = {
430 .init = &r300_init,
431 .fini = &r300_fini,
432 .suspend = &r300_suspend,
433 .resume = &r300_resume,
434 .vga_set_state = &r100_vga_set_state,
a2d07b74 435 .asic_reset = &r300_asic_reset,
124764f1 436 .mmio_hdp_flush = NULL,
54e88e06
AD		 437 .gui_idle = &r100_gui_idle,
438 .mc_wait_for_idle = &r300_mc_wait_for_idle,
18b53e90 439 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
c5b3b850
AD		 440 .gart = {
441 .tlb_flush = &rv370_pcie_gart_tlb_flush,
cb658906 442 .get_page_entry = &rv370_pcie_gart_get_page_entry,
c5b3b850
AD		 443 .set_page = &rv370_pcie_gart_set_page,
444 },
4c87bc26 445 .ring = {
76a0df85 446 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 447 },
b35ea4ab
AD		 448 .irq = {
449 .set = &r100_irq_set,
450 .process = &r100_irq_process,
451 },
c79a49ca
AD		 452 .display = {
453 .bandwidth_update = &r100_bandwidth_update,
454 .get_vblank_counter = &r100_get_vblank_counter,
455 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 456 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 457 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 458 },
27cd7769
AD		 459 .copy = {
460 .blit = &r100_copy_blit,
461 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
462 .dma = &r200_copy_dma,
463 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
464 .copy = &r100_copy_blit,
465 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
466 },
9e6f3d02
AD		 467 .surface = {
468 .set_reg = r100_set_surface_reg,
469 .clear_reg = r100_clear_surface_reg,
470 },
901ea57d
AD		 471 .hpd = {
472 .init = &r100_hpd_init,
473 .fini = &r100_hpd_fini,
474 .sense = &r100_hpd_sense,
475 .set_polarity = &r100_hpd_set_polarity,
476 },
a02fa397
AD		 477 .pm = {
478 .misc = &r100_pm_misc,
479 .prepare = &r100_pm_prepare,
480 .finish = &r100_pm_finish,
481 .init_profile = &r100_pm_init_profile,
482 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 483 .get_engine_clock = &radeon_legacy_get_engine_clock,
484 .set_engine_clock = &radeon_legacy_set_engine_clock,
485 .get_memory_clock = &radeon_legacy_get_memory_clock,
486 .set_memory_clock = NULL,
487 .get_pcie_lanes = &rv370_get_pcie_lanes,
488 .set_pcie_lanes = &rv370_set_pcie_lanes,
489 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 490 },
0f9e006c 491 .pflip = {
0f9e006c 492 .page_flip = &r100_page_flip,
157fa14d 493 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 494 },
48e7a5f1
DV		 495};
496
497static struct radeon_asic r420_asic = {
498 .init = &r420_init,
499 .fini = &r420_fini,
500 .suspend = &r420_suspend,
501 .resume = &r420_resume,
502 .vga_set_state = &r100_vga_set_state,
a2d07b74 503 .asic_reset = &r300_asic_reset,
124764f1 504 .mmio_hdp_flush = NULL,
54e88e06
AD		 505 .gui_idle = &r100_gui_idle,
506 .mc_wait_for_idle = &r300_mc_wait_for_idle,
18b53e90 507 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
c5b3b850
AD		 508 .gart = {
509 .tlb_flush = &rv370_pcie_gart_tlb_flush,
cb658906 510 .get_page_entry = &rv370_pcie_gart_get_page_entry,
c5b3b850
AD		 511 .set_page = &rv370_pcie_gart_set_page,
512 },
4c87bc26 513 .ring = {
76a0df85 514 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 515 },
b35ea4ab
AD		 516 .irq = {
517 .set = &r100_irq_set,
518 .process = &r100_irq_process,
519 },
c79a49ca
AD		 520 .display = {
521 .bandwidth_update = &r100_bandwidth_update,
522 .get_vblank_counter = &r100_get_vblank_counter,
523 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 524 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 525 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 526 },
27cd7769
AD		 527 .copy = {
528 .blit = &r100_copy_blit,
529 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
530 .dma = &r200_copy_dma,
531 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
532 .copy = &r100_copy_blit,
533 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
534 },
9e6f3d02
AD		 535 .surface = {
536 .set_reg = r100_set_surface_reg,
537 .clear_reg = r100_clear_surface_reg,
538 },
901ea57d
AD		 539 .hpd = {
540 .init = &r100_hpd_init,
541 .fini = &r100_hpd_fini,
542 .sense = &r100_hpd_sense,
543 .set_polarity = &r100_hpd_set_polarity,
544 },
a02fa397
AD		 545 .pm = {
546 .misc = &r100_pm_misc,
547 .prepare = &r100_pm_prepare,
548 .finish = &r100_pm_finish,
549 .init_profile = &r420_pm_init_profile,
550 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 551 .get_engine_clock = &radeon_atom_get_engine_clock,
552 .set_engine_clock = &radeon_atom_set_engine_clock,
553 .get_memory_clock = &radeon_atom_get_memory_clock,
554 .set_memory_clock = &radeon_atom_set_memory_clock,
555 .get_pcie_lanes = &rv370_get_pcie_lanes,
556 .set_pcie_lanes = &rv370_set_pcie_lanes,
557 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 558 },
0f9e006c 559 .pflip = {
0f9e006c 560 .page_flip = &r100_page_flip,
157fa14d 561 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 562 },
48e7a5f1
DV		 563};
564
565static struct radeon_asic rs400_asic = {
566 .init = &rs400_init,
567 .fini = &rs400_fini,
568 .suspend = &rs400_suspend,
569 .resume = &rs400_resume,
570 .vga_set_state = &r100_vga_set_state,
a2d07b74 571 .asic_reset = &r300_asic_reset,
124764f1 572 .mmio_hdp_flush = NULL,
54e88e06
AD		 573 .gui_idle = &r100_gui_idle,
574 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
18b53e90 575 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
c5b3b850
AD		 576 .gart = {
577 .tlb_flush = &rs400_gart_tlb_flush,
cb658906 578 .get_page_entry = &rs400_gart_get_page_entry,
c5b3b850
AD		 579 .set_page = &rs400_gart_set_page,
580 },
4c87bc26 581 .ring = {
76a0df85 582 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 583 },
b35ea4ab
AD		 584 .irq = {
585 .set = &r100_irq_set,
586 .process = &r100_irq_process,
587 },
c79a49ca
AD		 588 .display = {
589 .bandwidth_update = &r100_bandwidth_update,
590 .get_vblank_counter = &r100_get_vblank_counter,
591 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 592 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 593 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 594 },
27cd7769
AD		 595 .copy = {
596 .blit = &r100_copy_blit,
597 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
598 .dma = &r200_copy_dma,
599 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
600 .copy = &r100_copy_blit,
601 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
602 },
9e6f3d02
AD		 603 .surface = {
604 .set_reg = r100_set_surface_reg,
605 .clear_reg = r100_clear_surface_reg,
606 },
901ea57d
AD		 607 .hpd = {
608 .init = &r100_hpd_init,
609 .fini = &r100_hpd_fini,
610 .sense = &r100_hpd_sense,
611 .set_polarity = &r100_hpd_set_polarity,
612 },
a02fa397
AD		 613 .pm = {
614 .misc = &r100_pm_misc,
615 .prepare = &r100_pm_prepare,
616 .finish = &r100_pm_finish,
617 .init_profile = &r100_pm_init_profile,
618 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 619 .get_engine_clock = &radeon_legacy_get_engine_clock,
620 .set_engine_clock = &radeon_legacy_set_engine_clock,
621 .get_memory_clock = &radeon_legacy_get_memory_clock,
622 .set_memory_clock = NULL,
623 .get_pcie_lanes = NULL,
624 .set_pcie_lanes = NULL,
625 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 626 },
0f9e006c 627 .pflip = {
0f9e006c 628 .page_flip = &r100_page_flip,
157fa14d 629 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 630 },
48e7a5f1
DV		 631};
632
633static struct radeon_asic rs600_asic = {
634 .init = &rs600_init,
635 .fini = &rs600_fini,
636 .suspend = &rs600_suspend,
637 .resume = &rs600_resume,
638 .vga_set_state = &r100_vga_set_state,
90aca4d2 639 .asic_reset = &rs600_asic_reset,
124764f1 640 .mmio_hdp_flush = NULL,
54e88e06
AD		 641 .gui_idle = &r100_gui_idle,
642 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
18b53e90 643 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
c5b3b850
AD		 644 .gart = {
645 .tlb_flush = &rs600_gart_tlb_flush,
cb658906 646 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 647 .set_page = &rs600_gart_set_page,
648 },
4c87bc26 649 .ring = {
76a0df85 650 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 651 },
b35ea4ab
AD		 652 .irq = {
653 .set = &rs600_irq_set,
654 .process = &rs600_irq_process,
655 },
c79a49ca
AD		 656 .display = {
657 .bandwidth_update = &rs600_bandwidth_update,
658 .get_vblank_counter = &rs600_get_vblank_counter,
659 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 660 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 661 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 662 },
27cd7769
AD		 663 .copy = {
664 .blit = &r100_copy_blit,
665 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
666 .dma = &r200_copy_dma,
667 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
668 .copy = &r100_copy_blit,
669 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
670 },
9e6f3d02
AD		 671 .surface = {
672 .set_reg = r100_set_surface_reg,
673 .clear_reg = r100_clear_surface_reg,
674 },
901ea57d
AD		 675 .hpd = {
676 .init = &rs600_hpd_init,
677 .fini = &rs600_hpd_fini,
678 .sense = &rs600_hpd_sense,
679 .set_polarity = &rs600_hpd_set_polarity,
680 },
a02fa397
AD		 681 .pm = {
682 .misc = &rs600_pm_misc,
683 .prepare = &rs600_pm_prepare,
684 .finish = &rs600_pm_finish,
685 .init_profile = &r420_pm_init_profile,
686 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 687 .get_engine_clock = &radeon_atom_get_engine_clock,
688 .set_engine_clock = &radeon_atom_set_engine_clock,
689 .get_memory_clock = &radeon_atom_get_memory_clock,
690 .set_memory_clock = &radeon_atom_set_memory_clock,
691 .get_pcie_lanes = NULL,
692 .set_pcie_lanes = NULL,
693 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 694 },
0f9e006c 695 .pflip = {
0f9e006c 696 .page_flip = &rs600_page_flip,
157fa14d 697 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 698 },
48e7a5f1
DV		 699};
700
701static struct radeon_asic rs690_asic = {
702 .init = &rs690_init,
703 .fini = &rs690_fini,
704 .suspend = &rs690_suspend,
705 .resume = &rs690_resume,
706 .vga_set_state = &r100_vga_set_state,
90aca4d2 707 .asic_reset = &rs600_asic_reset,
124764f1 708 .mmio_hdp_flush = NULL,
54e88e06
AD		 709 .gui_idle = &r100_gui_idle,
710 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
18b53e90 711 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
c5b3b850
AD		 712 .gart = {
713 .tlb_flush = &rs400_gart_tlb_flush,
cb658906 714 .get_page_entry = &rs400_gart_get_page_entry,
c5b3b850
AD		 715 .set_page = &rs400_gart_set_page,
716 },
4c87bc26 717 .ring = {
76a0df85 718 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 719 },
b35ea4ab
AD		 720 .irq = {
721 .set = &rs600_irq_set,
722 .process = &rs600_irq_process,
723 },
c79a49ca
AD		 724 .display = {
725 .get_vblank_counter = &rs600_get_vblank_counter,
726 .bandwidth_update = &rs690_bandwidth_update,
727 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 728 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 729 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 730 },
27cd7769
AD		 731 .copy = {
732 .blit = &r100_copy_blit,
733 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
734 .dma = &r200_copy_dma,
735 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
736 .copy = &r200_copy_dma,
737 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
738 },
9e6f3d02
AD		 739 .surface = {
740 .set_reg = r100_set_surface_reg,
741 .clear_reg = r100_clear_surface_reg,
742 },
901ea57d
AD		 743 .hpd = {
744 .init = &rs600_hpd_init,
745 .fini = &rs600_hpd_fini,
746 .sense = &rs600_hpd_sense,
747 .set_polarity = &rs600_hpd_set_polarity,
748 },
a02fa397
AD		 749 .pm = {
750 .misc = &rs600_pm_misc,
751 .prepare = &rs600_pm_prepare,
752 .finish = &rs600_pm_finish,
753 .init_profile = &r420_pm_init_profile,
754 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 755 .get_engine_clock = &radeon_atom_get_engine_clock,
756 .set_engine_clock = &radeon_atom_set_engine_clock,
757 .get_memory_clock = &radeon_atom_get_memory_clock,
758 .set_memory_clock = &radeon_atom_set_memory_clock,
759 .get_pcie_lanes = NULL,
760 .set_pcie_lanes = NULL,
761 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 762 },
0f9e006c 763 .pflip = {
0f9e006c 764 .page_flip = &rs600_page_flip,
157fa14d 765 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 766 },
48e7a5f1
DV		 767};
768
769static struct radeon_asic rv515_asic = {
770 .init = &rv515_init,
771 .fini = &rv515_fini,
772 .suspend = &rv515_suspend,
773 .resume = &rv515_resume,
774 .vga_set_state = &r100_vga_set_state,
90aca4d2 775 .asic_reset = &rs600_asic_reset,
124764f1 776 .mmio_hdp_flush = NULL,
54e88e06
AD		 777 .gui_idle = &r100_gui_idle,
778 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
18b53e90 779 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
c5b3b850
AD		 780 .gart = {
781 .tlb_flush = &rv370_pcie_gart_tlb_flush,
cb658906 782 .get_page_entry = &rv370_pcie_gart_get_page_entry,
c5b3b850
AD		 783 .set_page = &rv370_pcie_gart_set_page,
784 },
4c87bc26 785 .ring = {
d8a74e18 786 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
4c87bc26 787 },
b35ea4ab
AD		 788 .irq = {
789 .set = &rs600_irq_set,
790 .process = &rs600_irq_process,
791 },
c79a49ca
AD		 792 .display = {
793 .get_vblank_counter = &rs600_get_vblank_counter,
794 .bandwidth_update = &rv515_bandwidth_update,
795 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 796 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 797 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 798 },
27cd7769
AD		 799 .copy = {
800 .blit = &r100_copy_blit,
801 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
802 .dma = &r200_copy_dma,
803 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
804 .copy = &r100_copy_blit,
805 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
806 },
9e6f3d02
AD		 807 .surface = {
808 .set_reg = r100_set_surface_reg,
809 .clear_reg = r100_clear_surface_reg,
810 },
901ea57d
AD		 811 .hpd = {
812 .init = &rs600_hpd_init,
813 .fini = &rs600_hpd_fini,
814 .sense = &rs600_hpd_sense,
815 .set_polarity = &rs600_hpd_set_polarity,
816 },
a02fa397
AD		 817 .pm = {
818 .misc = &rs600_pm_misc,
819 .prepare = &rs600_pm_prepare,
820 .finish = &rs600_pm_finish,
821 .init_profile = &r420_pm_init_profile,
822 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 823 .get_engine_clock = &radeon_atom_get_engine_clock,
824 .set_engine_clock = &radeon_atom_set_engine_clock,
825 .get_memory_clock = &radeon_atom_get_memory_clock,
826 .set_memory_clock = &radeon_atom_set_memory_clock,
827 .get_pcie_lanes = &rv370_get_pcie_lanes,
828 .set_pcie_lanes = &rv370_set_pcie_lanes,
829 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 830 },
0f9e006c 831 .pflip = {
0f9e006c 832 .page_flip = &rs600_page_flip,
157fa14d 833 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 834 },
48e7a5f1
DV		 835};
836
837static struct radeon_asic r520_asic = {
838 .init = &r520_init,
839 .fini = &rv515_fini,
840 .suspend = &rv515_suspend,
841 .resume = &r520_resume,
842 .vga_set_state = &r100_vga_set_state,
90aca4d2 843 .asic_reset = &rs600_asic_reset,
124764f1 844 .mmio_hdp_flush = NULL,
54e88e06
AD		 845 .gui_idle = &r100_gui_idle,
846 .mc_wait_for_idle = &r520_mc_wait_for_idle,
18b53e90 847 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
c5b3b850
AD		 848 .gart = {
849 .tlb_flush = &rv370_pcie_gart_tlb_flush,
cb658906 850 .get_page_entry = &rv370_pcie_gart_get_page_entry,
c5b3b850
AD		 851 .set_page = &rv370_pcie_gart_set_page,
852 },
4c87bc26 853 .ring = {
d8a74e18 854 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
4c87bc26 855 },
b35ea4ab
AD		 856 .irq = {
857 .set = &rs600_irq_set,
858 .process = &rs600_irq_process,
859 },
c79a49ca
AD		 860 .display = {
861 .bandwidth_update = &rv515_bandwidth_update,
862 .get_vblank_counter = &rs600_get_vblank_counter,
863 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 864 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 865 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 866 },
27cd7769
AD		 867 .copy = {
868 .blit = &r100_copy_blit,
869 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
870 .dma = &r200_copy_dma,
871 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
872 .copy = &r100_copy_blit,
873 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
874 },
9e6f3d02
AD		 875 .surface = {
876 .set_reg = r100_set_surface_reg,
877 .clear_reg = r100_clear_surface_reg,
878 },
901ea57d
AD		 879 .hpd = {
880 .init = &rs600_hpd_init,
881 .fini = &rs600_hpd_fini,
882 .sense = &rs600_hpd_sense,
883 .set_polarity = &rs600_hpd_set_polarity,
884 },
a02fa397
AD		 885 .pm = {
886 .misc = &rs600_pm_misc,
887 .prepare = &rs600_pm_prepare,
888 .finish = &rs600_pm_finish,
889 .init_profile = &r420_pm_init_profile,
890 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 891 .get_engine_clock = &radeon_atom_get_engine_clock,
892 .set_engine_clock = &radeon_atom_set_engine_clock,
893 .get_memory_clock = &radeon_atom_get_memory_clock,
894 .set_memory_clock = &radeon_atom_set_memory_clock,
895 .get_pcie_lanes = &rv370_get_pcie_lanes,
896 .set_pcie_lanes = &rv370_set_pcie_lanes,
897 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 898 },
0f9e006c 899 .pflip = {
0f9e006c 900 .page_flip = &rs600_page_flip,
157fa14d 901 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 902 },
48e7a5f1
DV		 903};
904
76a0df85
CK		 905static struct radeon_asic_ring r600_gfx_ring = {
906 .ib_execute = &r600_ring_ib_execute,
907 .emit_fence = &r600_fence_ring_emit,
908 .emit_semaphore = &r600_semaphore_ring_emit,
909 .cs_parse = &r600_cs_parse,
910 .ring_test = &r600_ring_test,
911 .ib_test = &r600_ib_test,
912 .is_lockup = &r600_gfx_is_lockup,
ea31bf69
AD		 913 .get_rptr = &r600_gfx_get_rptr,
914 .get_wptr = &r600_gfx_get_wptr,
915 .set_wptr = &r600_gfx_set_wptr,
76a0df85
CK		 916};
917
918static struct radeon_asic_ring r600_dma_ring = {
919 .ib_execute = &r600_dma_ring_ib_execute,
920 .emit_fence = &r600_dma_fence_ring_emit,
921 .emit_semaphore = &r600_dma_semaphore_ring_emit,
922 .cs_parse = &r600_dma_cs_parse,
923 .ring_test = &r600_dma_ring_test,
924 .ib_test = &r600_dma_ib_test,
925 .is_lockup = &r600_dma_is_lockup,
2e1e6dad
CK		 926 .get_rptr = &r600_dma_get_rptr,
927 .get_wptr = &r600_dma_get_wptr,
928 .set_wptr = &r600_dma_set_wptr,
76a0df85
CK		 929};
930
48e7a5f1
DV		 931static struct radeon_asic r600_asic = {
932 .init = &r600_init,
933 .fini = &r600_fini,
934 .suspend = &r600_suspend,
935 .resume = &r600_resume,
48e7a5f1 936 .vga_set_state = &r600_vga_set_state,
a2d07b74 937 .asic_reset = &r600_asic_reset,
124764f1 938 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 939 .gui_idle = &r600_gui_idle,
940 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 941 .get_xclk = &r600_get_xclk,
d0418894 942 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 943 .gart = {
944 .tlb_flush = &r600_pcie_gart_tlb_flush,
cb658906 945 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 946 .set_page = &rs600_gart_set_page,
947 },
4c87bc26 948 .ring = {
76a0df85
CK		 949 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
950 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
4c87bc26 951 },
b35ea4ab
AD		 952 .irq = {
953 .set = &r600_irq_set,
954 .process = &r600_irq_process,
955 },
c79a49ca
AD		 956 .display = {
957 .bandwidth_update = &rv515_bandwidth_update,
958 .get_vblank_counter = &rs600_get_vblank_counter,
959 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 960 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 961 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 962 },
27cd7769 963 .copy = {
8dddb993 964 .blit = &r600_copy_cpdma,
27cd7769 965 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
4d75658b
AD		 966 .dma = &r600_copy_dma,
967 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
bfea6a68 968 .copy = &r600_copy_cpdma,
aeea40cb 969 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
27cd7769 970 },
9e6f3d02
AD		 971 .surface = {
972 .set_reg = r600_set_surface_reg,
973 .clear_reg = r600_clear_surface_reg,
974 },
901ea57d
AD		 975 .hpd = {
976 .init = &r600_hpd_init,
977 .fini = &r600_hpd_fini,
978 .sense = &r600_hpd_sense,
979 .set_polarity = &r600_hpd_set_polarity,
980 },
a02fa397
AD		 981 .pm = {
982 .misc = &r600_pm_misc,
983 .prepare = &rs600_pm_prepare,
984 .finish = &rs600_pm_finish,
985 .init_profile = &r600_pm_init_profile,
986 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 987 .get_engine_clock = &radeon_atom_get_engine_clock,
988 .set_engine_clock = &radeon_atom_set_engine_clock,
989 .get_memory_clock = &radeon_atom_get_memory_clock,
990 .set_memory_clock = &radeon_atom_set_memory_clock,
991 .get_pcie_lanes = &r600_get_pcie_lanes,
992 .set_pcie_lanes = &r600_set_pcie_lanes,
993 .set_clock_gating = NULL,
6bd1c385 994 .get_temperature = &rv6xx_get_temp,
a02fa397 995 },
0f9e006c 996 .pflip = {
0f9e006c 997 .page_flip = &rs600_page_flip,
157fa14d 998 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 999 },
48e7a5f1
DV		 1000};
1001
856754c3
CK		 1002static struct radeon_asic_ring rv6xx_uvd_ring = {
1003 .ib_execute = &uvd_v1_0_ib_execute,
1004 .emit_fence = &uvd_v1_0_fence_emit,
1005 .emit_semaphore = &uvd_v1_0_semaphore_emit,
1006 .cs_parse = &radeon_uvd_cs_parse,
1007 .ring_test = &uvd_v1_0_ring_test,
1008 .ib_test = &uvd_v1_0_ib_test,
1009 .is_lockup = &radeon_ring_test_lockup,
1010 .get_rptr = &uvd_v1_0_get_rptr,
1011 .get_wptr = &uvd_v1_0_get_wptr,
1012 .set_wptr = &uvd_v1_0_set_wptr,
1013};
1014
ca361b65
AD		 1015static struct radeon_asic rv6xx_asic = {
1016 .init = &r600_init,
1017 .fini = &r600_fini,
1018 .suspend = &r600_suspend,
1019 .resume = &r600_resume,
1020 .vga_set_state = &r600_vga_set_state,
1021 .asic_reset = &r600_asic_reset,
124764f1 1022 .mmio_hdp_flush = r600_mmio_hdp_flush,
ca361b65
AD		 1023 .gui_idle = &r600_gui_idle,
1024 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1025 .get_xclk = &r600_get_xclk,
1026 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1027 .gart = {
1028 .tlb_flush = &r600_pcie_gart_tlb_flush,
cb658906 1029 .get_page_entry = &rs600_gart_get_page_entry,
ca361b65
AD		 1030 .set_page = &rs600_gart_set_page,
1031 },
1032 .ring = {
76a0df85
CK		 1033 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1034 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
856754c3 1035 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
ca361b65
AD		 1036 },
1037 .irq = {
1038 .set = &r600_irq_set,
1039 .process = &r600_irq_process,
1040 },
1041 .display = {
1042 .bandwidth_update = &rv515_bandwidth_update,
1043 .get_vblank_counter = &rs600_get_vblank_counter,
1044 .wait_for_vblank = &avivo_wait_for_vblank,
1045 .set_backlight_level = &atombios_set_backlight_level,
1046 .get_backlight_level = &atombios_get_backlight_level,
1047 },
1048 .copy = {
8dddb993 1049 .blit = &r600_copy_cpdma,
ca361b65
AD		 1050 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1051 .dma = &r600_copy_dma,
1052 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
bfea6a68 1053 .copy = &r600_copy_cpdma,
aeea40cb 1054 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
ca361b65
AD		 1055 },
1056 .surface = {
1057 .set_reg = r600_set_surface_reg,
1058 .clear_reg = r600_clear_surface_reg,
1059 },
1060 .hpd = {
1061 .init = &r600_hpd_init,
1062 .fini = &r600_hpd_fini,
1063 .sense = &r600_hpd_sense,
1064 .set_polarity = &r600_hpd_set_polarity,
1065 },
1066 .pm = {
1067 .misc = &r600_pm_misc,
1068 .prepare = &rs600_pm_prepare,
1069 .finish = &rs600_pm_finish,
1070 .init_profile = &r600_pm_init_profile,
1071 .get_dynpm_state = &r600_pm_get_dynpm_state,
1072 .get_engine_clock = &radeon_atom_get_engine_clock,
1073 .set_engine_clock = &radeon_atom_set_engine_clock,
1074 .get_memory_clock = &radeon_atom_get_memory_clock,
1075 .set_memory_clock = &radeon_atom_set_memory_clock,
1076 .get_pcie_lanes = &r600_get_pcie_lanes,
1077 .set_pcie_lanes = &r600_set_pcie_lanes,
1078 .set_clock_gating = NULL,
1079 .get_temperature = &rv6xx_get_temp,
1b9ba70a 1080 .set_uvd_clocks = &r600_set_uvd_clocks,
ca361b65 1081 },
4a6369e9
AD		 1082 .dpm = {
1083 .init = &rv6xx_dpm_init,
1084 .setup_asic = &rv6xx_setup_asic,
1085 .enable = &rv6xx_dpm_enable,
a4643ba3 1086 .late_enable = &r600_dpm_late_enable,
4a6369e9 1087 .disable = &rv6xx_dpm_disable,
98243917 1088 .pre_set_power_state = &r600_dpm_pre_set_power_state,
4a6369e9 1089 .set_power_state = &rv6xx_dpm_set_power_state,
98243917 1090 .post_set_power_state = &r600_dpm_post_set_power_state,
4a6369e9
AD		 1091 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1092 .fini = &rv6xx_dpm_fini,
1093 .get_sclk = &rv6xx_dpm_get_sclk,
1094 .get_mclk = &rv6xx_dpm_get_mclk,
1095 .print_power_state = &rv6xx_dpm_print_power_state,
242916a5 1096 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
f4f85a8c 1097 .force_performance_level = &rv6xx_dpm_force_performance_level,
d0a04d3b
AD		 1098 .get_current_sclk = &rv6xx_dpm_get_current_sclk,
1099 .get_current_mclk = &rv6xx_dpm_get_current_mclk,
4a6369e9 1100 },
ca361b65 1101 .pflip = {
ca361b65 1102 .page_flip = &rs600_page_flip,
157fa14d 1103 .page_flip_pending = &rs600_page_flip_pending,
ca361b65
AD		 1104 },
1105};
1106
f47299c5
AD		 1107static struct radeon_asic rs780_asic = {
1108 .init = &r600_init,
1109 .fini = &r600_fini,
1110 .suspend = &r600_suspend,
1111 .resume = &r600_resume,
f47299c5 1112 .vga_set_state = &r600_vga_set_state,
a2d07b74 1113 .asic_reset = &r600_asic_reset,
124764f1 1114 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1115 .gui_idle = &r600_gui_idle,
1116 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 1117 .get_xclk = &r600_get_xclk,
d0418894 1118 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1119 .gart = {
1120 .tlb_flush = &r600_pcie_gart_tlb_flush,
cb658906 1121 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 1122 .set_page = &rs600_gart_set_page,
1123 },
4c87bc26 1124 .ring = {
76a0df85
CK		 1125 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1126 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
856754c3 1127 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
4c87bc26 1128 },
b35ea4ab
AD		 1129 .irq = {
1130 .set = &r600_irq_set,
1131 .process = &r600_irq_process,
1132 },
c79a49ca
AD		 1133 .display = {
1134 .bandwidth_update = &rs690_bandwidth_update,
1135 .get_vblank_counter = &rs600_get_vblank_counter,
1136 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 1137 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1138 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 1139 },
27cd7769 1140 .copy = {
8dddb993 1141 .blit = &r600_copy_cpdma,
27cd7769 1142 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
4d75658b
AD		 1143 .dma = &r600_copy_dma,
1144 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
bfea6a68 1145 .copy = &r600_copy_cpdma,
aeea40cb 1146 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
27cd7769 1147 },
9e6f3d02
AD		 1148 .surface = {
1149 .set_reg = r600_set_surface_reg,
1150 .clear_reg = r600_clear_surface_reg,
1151 },
901ea57d
AD		 1152 .hpd = {
1153 .init = &r600_hpd_init,
1154 .fini = &r600_hpd_fini,
1155 .sense = &r600_hpd_sense,
1156 .set_polarity = &r600_hpd_set_polarity,
1157 },
a02fa397
AD		 1158 .pm = {
1159 .misc = &r600_pm_misc,
1160 .prepare = &rs600_pm_prepare,
1161 .finish = &rs600_pm_finish,
1162 .init_profile = &rs780_pm_init_profile,
1163 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1164 .get_engine_clock = &radeon_atom_get_engine_clock,
1165 .set_engine_clock = &radeon_atom_set_engine_clock,
1166 .get_memory_clock = NULL,
1167 .set_memory_clock = NULL,
1168 .get_pcie_lanes = NULL,
1169 .set_pcie_lanes = NULL,
1170 .set_clock_gating = NULL,
6bd1c385 1171 .get_temperature = &rv6xx_get_temp,
1b9ba70a 1172 .set_uvd_clocks = &r600_set_uvd_clocks,
a02fa397 1173 },
9d67006e
AD		 1174 .dpm = {
1175 .init = &rs780_dpm_init,
1176 .setup_asic = &rs780_dpm_setup_asic,
1177 .enable = &rs780_dpm_enable,
a4643ba3 1178 .late_enable = &r600_dpm_late_enable,
9d67006e 1179 .disable = &rs780_dpm_disable,
98243917 1180 .pre_set_power_state = &r600_dpm_pre_set_power_state,
9d67006e 1181 .set_power_state = &rs780_dpm_set_power_state,
98243917 1182 .post_set_power_state = &r600_dpm_post_set_power_state,
9d67006e
AD		 1183 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1184 .fini = &rs780_dpm_fini,
1185 .get_sclk = &rs780_dpm_get_sclk,
1186 .get_mclk = &rs780_dpm_get_mclk,
1187 .print_power_state = &rs780_dpm_print_power_state,
444bddc4 1188 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
63580c3e 1189 .force_performance_level = &rs780_dpm_force_performance_level,
3c94566c
AD		 1190 .get_current_sclk = &rs780_dpm_get_current_sclk,
1191 .get_current_mclk = &rs780_dpm_get_current_mclk,
9d67006e 1192 },
0f9e006c 1193 .pflip = {
0f9e006c 1194 .page_flip = &rs600_page_flip,
157fa14d 1195 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 1196 },
f47299c5
AD		 1197};
1198
76a0df85 1199static struct radeon_asic_ring rv770_uvd_ring = {
e409b128
CK		 1200 .ib_execute = &uvd_v1_0_ib_execute,
1201 .emit_fence = &uvd_v2_2_fence_emit,
1202 .emit_semaphore = &uvd_v1_0_semaphore_emit,
76a0df85 1203 .cs_parse = &radeon_uvd_cs_parse,
e409b128
CK		 1204 .ring_test = &uvd_v1_0_ring_test,
1205 .ib_test = &uvd_v1_0_ib_test,
76a0df85 1206 .is_lockup = &radeon_ring_test_lockup,
e409b128
CK		 1207 .get_rptr = &uvd_v1_0_get_rptr,
1208 .get_wptr = &uvd_v1_0_get_wptr,
1209 .set_wptr = &uvd_v1_0_set_wptr,
76a0df85
CK		 1210};
1211
48e7a5f1
DV		 1212static struct radeon_asic rv770_asic = {
1213 .init = &rv770_init,
1214 .fini = &rv770_fini,
1215 .suspend = &rv770_suspend,
1216 .resume = &rv770_resume,
a2d07b74 1217 .asic_reset = &r600_asic_reset,
48e7a5f1 1218 .vga_set_state = &r600_vga_set_state,
124764f1 1219 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1220 .gui_idle = &r600_gui_idle,
1221 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 1222 .get_xclk = &rv770_get_xclk,
d0418894 1223 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1224 .gart = {
1225 .tlb_flush = &r600_pcie_gart_tlb_flush,
cb658906 1226 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 1227 .set_page = &rs600_gart_set_page,
1228 },
4c87bc26 1229 .ring = {
76a0df85
CK		 1230 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1231 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1232 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1233 },
b35ea4ab
AD		 1234 .irq = {
1235 .set = &r600_irq_set,
1236 .process = &r600_irq_process,
1237 },
c79a49ca
AD		 1238 .display = {
1239 .bandwidth_update = &rv515_bandwidth_update,
1240 .get_vblank_counter = &rs600_get_vblank_counter,
1241 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 1242 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1243 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 1244 },
27cd7769 1245 .copy = {
8dddb993 1246 .blit = &r600_copy_cpdma,
27cd7769 1247 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
43fb7787 1248 .dma = &rv770_copy_dma,
4d75658b 1249 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
43fb7787 1250 .copy = &rv770_copy_dma,
2d6cc729 1251 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1252 },
9e6f3d02
AD		 1253 .surface = {
1254 .set_reg = r600_set_surface_reg,
1255 .clear_reg = r600_clear_surface_reg,
1256 },
901ea57d
AD		 1257 .hpd = {
1258 .init = &r600_hpd_init,
1259 .fini = &r600_hpd_fini,
1260 .sense = &r600_hpd_sense,
1261 .set_polarity = &r600_hpd_set_polarity,
1262 },
a02fa397
AD		 1263 .pm = {
1264 .misc = &rv770_pm_misc,
1265 .prepare = &rs600_pm_prepare,
1266 .finish = &rs600_pm_finish,
1267 .init_profile = &r600_pm_init_profile,
1268 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1269 .get_engine_clock = &radeon_atom_get_engine_clock,
1270 .set_engine_clock = &radeon_atom_set_engine_clock,
1271 .get_memory_clock = &radeon_atom_get_memory_clock,
1272 .set_memory_clock = &radeon_atom_set_memory_clock,
1273 .get_pcie_lanes = &r600_get_pcie_lanes,
1274 .set_pcie_lanes = &r600_set_pcie_lanes,
1275 .set_clock_gating = &radeon_atom_set_clock_gating,
ef0e6e65 1276 .set_uvd_clocks = &rv770_set_uvd_clocks,
6bd1c385 1277 .get_temperature = &rv770_get_temp,
a02fa397 1278 },
66229b20
AD		 1279 .dpm = {
1280 .init = &rv770_dpm_init,
1281 .setup_asic = &rv770_dpm_setup_asic,
1282 .enable = &rv770_dpm_enable,
a3f11245 1283 .late_enable = &rv770_dpm_late_enable,
66229b20 1284 .disable = &rv770_dpm_disable,
98243917 1285 .pre_set_power_state = &r600_dpm_pre_set_power_state,
66229b20 1286 .set_power_state = &rv770_dpm_set_power_state,
98243917 1287 .post_set_power_state = &r600_dpm_post_set_power_state,
66229b20
AD		 1288 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1289 .fini = &rv770_dpm_fini,
1290 .get_sclk = &rv770_dpm_get_sclk,
1291 .get_mclk = &rv770_dpm_get_mclk,
1292 .print_power_state = &rv770_dpm_print_power_state,
bd210d11 1293 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
8b5e6b7f 1294 .force_performance_level = &rv770_dpm_force_performance_level,
b06195d9 1295 .vblank_too_short = &rv770_dpm_vblank_too_short,
296deb71
AD		 1296 .get_current_sclk = &rv770_dpm_get_current_sclk,
1297 .get_current_mclk = &rv770_dpm_get_current_mclk,
66229b20 1298 },
0f9e006c 1299 .pflip = {
0f9e006c 1300 .page_flip = &rv770_page_flip,
157fa14d 1301 .page_flip_pending = &rv770_page_flip_pending,
0f9e006c 1302 },
48e7a5f1
DV		 1303};
1304
76a0df85
CK		 1305static struct radeon_asic_ring evergreen_gfx_ring = {
1306 .ib_execute = &evergreen_ring_ib_execute,
1307 .emit_fence = &r600_fence_ring_emit,
1308 .emit_semaphore = &r600_semaphore_ring_emit,
1309 .cs_parse = &evergreen_cs_parse,
1310 .ring_test = &r600_ring_test,
1311 .ib_test = &r600_ib_test,
1312 .is_lockup = &evergreen_gfx_is_lockup,
ea31bf69
AD		 1313 .get_rptr = &r600_gfx_get_rptr,
1314 .get_wptr = &r600_gfx_get_wptr,
1315 .set_wptr = &r600_gfx_set_wptr,
76a0df85
CK		 1316};
1317
1318static struct radeon_asic_ring evergreen_dma_ring = {
1319 .ib_execute = &evergreen_dma_ring_ib_execute,
1320 .emit_fence = &evergreen_dma_fence_ring_emit,
1321 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1322 .cs_parse = &evergreen_dma_cs_parse,
1323 .ring_test = &r600_dma_ring_test,
1324 .ib_test = &r600_dma_ib_test,
1325 .is_lockup = &evergreen_dma_is_lockup,
2e1e6dad
CK		 1326 .get_rptr = &r600_dma_get_rptr,
1327 .get_wptr = &r600_dma_get_wptr,
1328 .set_wptr = &r600_dma_set_wptr,
76a0df85
CK		 1329};
1330
48e7a5f1
DV		 1331static struct radeon_asic evergreen_asic = {
1332 .init = &evergreen_init,
1333 .fini = &evergreen_fini,
1334 .suspend = &evergreen_suspend,
1335 .resume = &evergreen_resume,
a2d07b74 1336 .asic_reset = &evergreen_asic_reset,
48e7a5f1 1337 .vga_set_state = &r600_vga_set_state,
124764f1 1338 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1339 .gui_idle = &r600_gui_idle,
1340 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1341 .get_xclk = &rv770_get_xclk,
d0418894 1342 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1343 .gart = {
1344 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
cb658906 1345 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 1346 .set_page = &rs600_gart_set_page,
1347 },
4c87bc26 1348 .ring = {
76a0df85
CK		 1349 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1350 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1351 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1352 },
b35ea4ab
AD		 1353 .irq = {
1354 .set = &evergreen_irq_set,
1355 .process = &evergreen_irq_process,
1356 },
c79a49ca
AD		 1357 .display = {
1358 .bandwidth_update = &evergreen_bandwidth_update,
1359 .get_vblank_counter = &evergreen_get_vblank_counter,
1360 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1361 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1362 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 1363 },
27cd7769 1364 .copy = {
8dddb993 1365 .blit = &r600_copy_cpdma,
27cd7769 1366 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1367 .dma = &evergreen_copy_dma,
1368 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1369 .copy = &evergreen_copy_dma,
1370 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1371 },
9e6f3d02
AD		 1372 .surface = {
1373 .set_reg = r600_set_surface_reg,
1374 .clear_reg = r600_clear_surface_reg,
1375 },
901ea57d
AD		 1376 .hpd = {
1377 .init = &evergreen_hpd_init,
1378 .fini = &evergreen_hpd_fini,
1379 .sense = &evergreen_hpd_sense,
1380 .set_polarity = &evergreen_hpd_set_polarity,
1381 },
a02fa397
AD		 1382 .pm = {
1383 .misc = &evergreen_pm_misc,
1384 .prepare = &evergreen_pm_prepare,
1385 .finish = &evergreen_pm_finish,
1386 .init_profile = &r600_pm_init_profile,
1387 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1388 .get_engine_clock = &radeon_atom_get_engine_clock,
1389 .set_engine_clock = &radeon_atom_set_engine_clock,
1390 .get_memory_clock = &radeon_atom_get_memory_clock,
1391 .set_memory_clock = &radeon_atom_set_memory_clock,
1392 .get_pcie_lanes = &r600_get_pcie_lanes,
1393 .set_pcie_lanes = &r600_set_pcie_lanes,
1394 .set_clock_gating = NULL,
a8b4925c 1395 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1396 .get_temperature = &evergreen_get_temp,
a02fa397 1397 },
dc50ba7f
AD		 1398 .dpm = {
1399 .init = &cypress_dpm_init,
1400 .setup_asic = &cypress_dpm_setup_asic,
1401 .enable = &cypress_dpm_enable,
a3f11245 1402 .late_enable = &rv770_dpm_late_enable,
dc50ba7f 1403 .disable = &cypress_dpm_disable,
98243917 1404 .pre_set_power_state = &r600_dpm_pre_set_power_state,
dc50ba7f 1405 .set_power_state = &cypress_dpm_set_power_state,
98243917 1406 .post_set_power_state = &r600_dpm_post_set_power_state,
dc50ba7f
AD		 1407 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1408 .fini = &cypress_dpm_fini,
1409 .get_sclk = &rv770_dpm_get_sclk,
1410 .get_mclk = &rv770_dpm_get_mclk,
1411 .print_power_state = &rv770_dpm_print_power_state,
bd210d11 1412 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
8b5e6b7f 1413 .force_performance_level = &rv770_dpm_force_performance_level,
d0b54bdc 1414 .vblank_too_short = &cypress_dpm_vblank_too_short,
296deb71
AD		 1415 .get_current_sclk = &rv770_dpm_get_current_sclk,
1416 .get_current_mclk = &rv770_dpm_get_current_mclk,
dc50ba7f 1417 },
0f9e006c 1418 .pflip = {
0f9e006c 1419 .page_flip = &evergreen_page_flip,
157fa14d 1420 .page_flip_pending = &evergreen_page_flip_pending,
0f9e006c 1421 },
48e7a5f1
DV		 1422};
1423
958261d1
AD		 1424static struct radeon_asic sumo_asic = {
1425 .init = &evergreen_init,
1426 .fini = &evergreen_fini,
1427 .suspend = &evergreen_suspend,
1428 .resume = &evergreen_resume,
958261d1
AD		 1429 .asic_reset = &evergreen_asic_reset,
1430 .vga_set_state = &r600_vga_set_state,
124764f1 1431 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1432 .gui_idle = &r600_gui_idle,
1433 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1434 .get_xclk = &r600_get_xclk,
d0418894 1435 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1436 .gart = {
1437 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
cb658906 1438 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 1439 .set_page = &rs600_gart_set_page,
1440 },
4c87bc26 1441 .ring = {
76a0df85
CK		 1442 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1443 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1444 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1445 },
b35ea4ab
AD		 1446 .irq = {
1447 .set = &evergreen_irq_set,
1448 .process = &evergreen_irq_process,
1449 },
c79a49ca
AD		 1450 .display = {
1451 .bandwidth_update = &evergreen_bandwidth_update,
1452 .get_vblank_counter = &evergreen_get_vblank_counter,
1453 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1454 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1455 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 1456 },
27cd7769 1457 .copy = {
8dddb993 1458 .blit = &r600_copy_cpdma,
27cd7769 1459 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1460 .dma = &evergreen_copy_dma,
1461 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1462 .copy = &evergreen_copy_dma,
1463 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1464 },
9e6f3d02
AD		 1465 .surface = {
1466 .set_reg = r600_set_surface_reg,
1467 .clear_reg = r600_clear_surface_reg,
1468 },
901ea57d
AD		 1469 .hpd = {
1470 .init = &evergreen_hpd_init,
1471 .fini = &evergreen_hpd_fini,
1472 .sense = &evergreen_hpd_sense,
1473 .set_polarity = &evergreen_hpd_set_polarity,
1474 },
a02fa397
AD		 1475 .pm = {
1476 .misc = &evergreen_pm_misc,
1477 .prepare = &evergreen_pm_prepare,
1478 .finish = &evergreen_pm_finish,
1479 .init_profile = &sumo_pm_init_profile,
1480 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1481 .get_engine_clock = &radeon_atom_get_engine_clock,
1482 .set_engine_clock = &radeon_atom_set_engine_clock,
1483 .get_memory_clock = NULL,
1484 .set_memory_clock = NULL,
1485 .get_pcie_lanes = NULL,
1486 .set_pcie_lanes = NULL,
1487 .set_clock_gating = NULL,
23d33ba3 1488 .set_uvd_clocks = &sumo_set_uvd_clocks,
6bd1c385 1489 .get_temperature = &sumo_get_temp,
a02fa397 1490 },
80ea2c12
AD		 1491 .dpm = {
1492 .init = &sumo_dpm_init,
1493 .setup_asic = &sumo_dpm_setup_asic,
1494 .enable = &sumo_dpm_enable,
14ec9fab 1495 .late_enable = &sumo_dpm_late_enable,
80ea2c12 1496 .disable = &sumo_dpm_disable,
422a56bc 1497 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
80ea2c12 1498 .set_power_state = &sumo_dpm_set_power_state,
422a56bc 1499 .post_set_power_state = &sumo_dpm_post_set_power_state,
80ea2c12
AD		 1500 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1501 .fini = &sumo_dpm_fini,
1502 .get_sclk = &sumo_dpm_get_sclk,
1503 .get_mclk = &sumo_dpm_get_mclk,
1504 .print_power_state = &sumo_dpm_print_power_state,
fb70160c 1505 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
5d5e5591 1506 .force_performance_level = &sumo_dpm_force_performance_level,
2f8e1eb7
AD		 1507 .get_current_sclk = &sumo_dpm_get_current_sclk,
1508 .get_current_mclk = &sumo_dpm_get_current_mclk,
80ea2c12 1509 },
0f9e006c 1510 .pflip = {
0f9e006c 1511 .page_flip = &evergreen_page_flip,
157fa14d 1512 .page_flip_pending = &evergreen_page_flip_pending,
0f9e006c 1513 },
958261d1
AD		 1514};
1515
a43b7665
AD		 1516static struct radeon_asic btc_asic = {
1517 .init = &evergreen_init,
1518 .fini = &evergreen_fini,
1519 .suspend = &evergreen_suspend,
1520 .resume = &evergreen_resume,
a43b7665
AD		 1521 .asic_reset = &evergreen_asic_reset,
1522 .vga_set_state = &r600_vga_set_state,
124764f1 1523 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1524 .gui_idle = &r600_gui_idle,
1525 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1526 .get_xclk = &rv770_get_xclk,
d0418894 1527 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1528 .gart = {
1529 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
cb658906 1530 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 1531 .set_page = &rs600_gart_set_page,
1532 },
4c87bc26 1533 .ring = {
76a0df85
CK		 1534 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1535 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1536 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1537 },
b35ea4ab
AD		 1538 .irq = {
1539 .set = &evergreen_irq_set,
1540 .process = &evergreen_irq_process,
1541 },
c79a49ca
AD		 1542 .display = {
1543 .bandwidth_update = &evergreen_bandwidth_update,
1544 .get_vblank_counter = &evergreen_get_vblank_counter,
1545 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1546 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1547 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 1548 },
27cd7769 1549 .copy = {
8dddb993 1550 .blit = &r600_copy_cpdma,
27cd7769 1551 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1552 .dma = &evergreen_copy_dma,
1553 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1554 .copy = &evergreen_copy_dma,
1555 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1556 },
9e6f3d02
AD		 1557 .surface = {
1558 .set_reg = r600_set_surface_reg,
1559 .clear_reg = r600_clear_surface_reg,
1560 },
901ea57d
AD		 1561 .hpd = {
1562 .init = &evergreen_hpd_init,
1563 .fini = &evergreen_hpd_fini,
1564 .sense = &evergreen_hpd_sense,
1565 .set_polarity = &evergreen_hpd_set_polarity,
1566 },
a02fa397
AD		 1567 .pm = {
1568 .misc = &evergreen_pm_misc,
1569 .prepare = &evergreen_pm_prepare,
1570 .finish = &evergreen_pm_finish,
27810fb2 1571 .init_profile = &btc_pm_init_profile,
a02fa397 1572 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1573 .get_engine_clock = &radeon_atom_get_engine_clock,
1574 .set_engine_clock = &radeon_atom_set_engine_clock,
1575 .get_memory_clock = &radeon_atom_get_memory_clock,
1576 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1577 .get_pcie_lanes = &r600_get_pcie_lanes,
1578 .set_pcie_lanes = &r600_set_pcie_lanes,
798bcf73 1579 .set_clock_gating = NULL,
a8b4925c 1580 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1581 .get_temperature = &evergreen_get_temp,
a02fa397 1582 },
6596afd4
AD		 1583 .dpm = {
1584 .init = &btc_dpm_init,
1585 .setup_asic = &btc_dpm_setup_asic,
1586 .enable = &btc_dpm_enable,
a3f11245 1587 .late_enable = &rv770_dpm_late_enable,
6596afd4 1588 .disable = &btc_dpm_disable,
e8a9539f 1589 .pre_set_power_state = &btc_dpm_pre_set_power_state,
6596afd4 1590 .set_power_state = &btc_dpm_set_power_state,
e8a9539f 1591 .post_set_power_state = &btc_dpm_post_set_power_state,
6596afd4
AD		 1592 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1593 .fini = &btc_dpm_fini,
e8a9539f
AD		 1594 .get_sclk = &btc_dpm_get_sclk,
1595 .get_mclk = &btc_dpm_get_mclk,
6596afd4 1596 .print_power_state = &rv770_dpm_print_power_state,
9f3f63f2 1597 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
8b5e6b7f 1598 .force_performance_level = &rv770_dpm_force_performance_level,
a84301c6 1599 .vblank_too_short = &btc_dpm_vblank_too_short,
99550ee9
AD		 1600 .get_current_sclk = &btc_dpm_get_current_sclk,
1601 .get_current_mclk = &btc_dpm_get_current_mclk,
6596afd4 1602 },
0f9e006c 1603 .pflip = {
0f9e006c 1604 .page_flip = &evergreen_page_flip,
157fa14d 1605 .page_flip_pending = &evergreen_page_flip_pending,
0f9e006c 1606 },
a43b7665
AD		 1607};
1608
76a0df85
CK		 1609static struct radeon_asic_ring cayman_gfx_ring = {
1610 .ib_execute = &cayman_ring_ib_execute,
1611 .ib_parse = &evergreen_ib_parse,
1612 .emit_fence = &cayman_fence_ring_emit,
1613 .emit_semaphore = &r600_semaphore_ring_emit,
1614 .cs_parse = &evergreen_cs_parse,
1615 .ring_test = &r600_ring_test,
1616 .ib_test = &r600_ib_test,
1617 .is_lockup = &cayman_gfx_is_lockup,
1618 .vm_flush = &cayman_vm_flush,
ea31bf69
AD		 1619 .get_rptr = &cayman_gfx_get_rptr,
1620 .get_wptr = &cayman_gfx_get_wptr,
1621 .set_wptr = &cayman_gfx_set_wptr,
76a0df85
CK		 1622};
1623
1624static struct radeon_asic_ring cayman_dma_ring = {
1625 .ib_execute = &cayman_dma_ring_ib_execute,
1626 .ib_parse = &evergreen_dma_ib_parse,
1627 .emit_fence = &evergreen_dma_fence_ring_emit,
1628 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1629 .cs_parse = &evergreen_dma_cs_parse,
1630 .ring_test = &r600_dma_ring_test,
1631 .ib_test = &r600_dma_ib_test,
1632 .is_lockup = &cayman_dma_is_lockup,
1633 .vm_flush = &cayman_dma_vm_flush,
ea31bf69
AD		 1634 .get_rptr = &cayman_dma_get_rptr,
1635 .get_wptr = &cayman_dma_get_wptr,
1636 .set_wptr = &cayman_dma_set_wptr
76a0df85
CK		 1637};
1638
1639static struct radeon_asic_ring cayman_uvd_ring = {
e409b128
CK		 1640 .ib_execute = &uvd_v1_0_ib_execute,
1641 .emit_fence = &uvd_v2_2_fence_emit,
1642 .emit_semaphore = &uvd_v3_1_semaphore_emit,
76a0df85 1643 .cs_parse = &radeon_uvd_cs_parse,
e409b128
CK		 1644 .ring_test = &uvd_v1_0_ring_test,
1645 .ib_test = &uvd_v1_0_ib_test,
76a0df85 1646 .is_lockup = &radeon_ring_test_lockup,
e409b128
CK		 1647 .get_rptr = &uvd_v1_0_get_rptr,
1648 .get_wptr = &uvd_v1_0_get_wptr,
1649 .set_wptr = &uvd_v1_0_set_wptr,
76a0df85
CK		 1650};
1651
e3487629
AD		 1652static struct radeon_asic cayman_asic = {
1653 .init = &cayman_init,
1654 .fini = &cayman_fini,
1655 .suspend = &cayman_suspend,
1656 .resume = &cayman_resume,
e3487629
AD		 1657 .asic_reset = &cayman_asic_reset,
1658 .vga_set_state = &r600_vga_set_state,
124764f1 1659 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1660 .gui_idle = &r600_gui_idle,
1661 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1662 .get_xclk = &rv770_get_xclk,
d0418894 1663 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1664 .gart = {
1665 .tlb_flush = &cayman_pcie_gart_tlb_flush,
cb658906 1666 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 1667 .set_page = &rs600_gart_set_page,
1668 },
05b07147
CK		 1669 .vm = {
1670 .init = &cayman_vm_init,
1671 .fini = &cayman_vm_fini,
03f62abd
CK		 1672 .copy_pages = &cayman_dma_vm_copy_pages,
1673 .write_pages = &cayman_dma_vm_write_pages,
1674 .set_pages = &cayman_dma_vm_set_pages,
1675 .pad_ib = &cayman_dma_vm_pad_ib,
05b07147 1676 },
4c87bc26 1677 .ring = {
76a0df85
CK		 1678 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1679 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1680 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1681 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1682 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1683 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
4c87bc26 1684 },
b35ea4ab
AD		 1685 .irq = {
1686 .set = &evergreen_irq_set,
1687 .process = &evergreen_irq_process,
1688 },
c79a49ca
AD		 1689 .display = {
1690 .bandwidth_update = &evergreen_bandwidth_update,
1691 .get_vblank_counter = &evergreen_get_vblank_counter,
1692 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1693 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1694 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 1695 },
27cd7769 1696 .copy = {
8dddb993 1697 .blit = &r600_copy_cpdma,
27cd7769 1698 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
f60cbd11
AD		 1699 .dma = &evergreen_copy_dma,
1700 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1701 .copy = &evergreen_copy_dma,
1702 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1703 },
9e6f3d02
AD		 1704 .surface = {
1705 .set_reg = r600_set_surface_reg,
1706 .clear_reg = r600_clear_surface_reg,
1707 },
901ea57d
AD		 1708 .hpd = {
1709 .init = &evergreen_hpd_init,
1710 .fini = &evergreen_hpd_fini,
1711 .sense = &evergreen_hpd_sense,
1712 .set_polarity = &evergreen_hpd_set_polarity,
1713 },
a02fa397
AD		 1714 .pm = {
1715 .misc = &evergreen_pm_misc,
1716 .prepare = &evergreen_pm_prepare,
1717 .finish = &evergreen_pm_finish,
27810fb2 1718 .init_profile = &btc_pm_init_profile,
a02fa397 1719 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1720 .get_engine_clock = &radeon_atom_get_engine_clock,
1721 .set_engine_clock = &radeon_atom_set_engine_clock,
1722 .get_memory_clock = &radeon_atom_get_memory_clock,
1723 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1724 .get_pcie_lanes = &r600_get_pcie_lanes,
1725 .set_pcie_lanes = &r600_set_pcie_lanes,
798bcf73 1726 .set_clock_gating = NULL,
a8b4925c 1727 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1728 .get_temperature = &evergreen_get_temp,
a02fa397 1729 },
69e0b57a
AD		 1730 .dpm = {
1731 .init = &ni_dpm_init,
1732 .setup_asic = &ni_dpm_setup_asic,
1733 .enable = &ni_dpm_enable,
a3f11245 1734 .late_enable = &rv770_dpm_late_enable,
69e0b57a 1735 .disable = &ni_dpm_disable,
fee3d744 1736 .pre_set_power_state = &ni_dpm_pre_set_power_state,
69e0b57a 1737 .set_power_state = &ni_dpm_set_power_state,
fee3d744 1738 .post_set_power_state = &ni_dpm_post_set_power_state,
69e0b57a
AD		 1739 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1740 .fini = &ni_dpm_fini,
1741 .get_sclk = &ni_dpm_get_sclk,
1742 .get_mclk = &ni_dpm_get_mclk,
1743 .print_power_state = &ni_dpm_print_power_state,
bdf0c4f0 1744 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
170a47f0 1745 .force_performance_level = &ni_dpm_force_performance_level,
76ad73e5 1746 .vblank_too_short = &ni_dpm_vblank_too_short,
1d633e3a
AD		 1747 .get_current_sclk = &ni_dpm_get_current_sclk,
1748 .get_current_mclk = &ni_dpm_get_current_mclk,
69e0b57a 1749 },
0f9e006c 1750 .pflip = {
0f9e006c 1751 .page_flip = &evergreen_page_flip,
157fa14d 1752 .page_flip_pending = &evergreen_page_flip_pending,
0f9e006c 1753 },
e3487629
AD		 1754};
1755
be63fe8c
AD		 1756static struct radeon_asic trinity_asic = {
1757 .init = &cayman_init,
1758 .fini = &cayman_fini,
1759 .suspend = &cayman_suspend,
1760 .resume = &cayman_resume,
be63fe8c
AD		 1761 .asic_reset = &cayman_asic_reset,
1762 .vga_set_state = &r600_vga_set_state,
124764f1 1763 .mmio_hdp_flush = r600_mmio_hdp_flush,
be63fe8c
AD		 1764 .gui_idle = &r600_gui_idle,
1765 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1766 .get_xclk = &r600_get_xclk,
d0418894 1767 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
be63fe8c
AD		 1768 .gart = {
1769 .tlb_flush = &cayman_pcie_gart_tlb_flush,
cb658906 1770 .get_page_entry = &rs600_gart_get_page_entry,
be63fe8c
AD		 1771 .set_page = &rs600_gart_set_page,
1772 },
05b07147
CK		 1773 .vm = {
1774 .init = &cayman_vm_init,
1775 .fini = &cayman_vm_fini,
03f62abd
CK		 1776 .copy_pages = &cayman_dma_vm_copy_pages,
1777 .write_pages = &cayman_dma_vm_write_pages,
1778 .set_pages = &cayman_dma_vm_set_pages,
1779 .pad_ib = &cayman_dma_vm_pad_ib,
05b07147 1780 },
be63fe8c 1781 .ring = {
76a0df85
CK		 1782 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1783 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1784 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1785 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1786 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1787 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
be63fe8c
AD		 1788 },
1789 .irq = {
1790 .set = &evergreen_irq_set,
1791 .process = &evergreen_irq_process,
1792 },
1793 .display = {
1794 .bandwidth_update = &dce6_bandwidth_update,
1795 .get_vblank_counter = &evergreen_get_vblank_counter,
1796 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1797 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1798 .get_backlight_level = &atombios_get_backlight_level,
be63fe8c
AD		 1799 },
1800 .copy = {
8dddb993 1801 .blit = &r600_copy_cpdma,
be63fe8c 1802 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
f60cbd11
AD		 1803 .dma = &evergreen_copy_dma,
1804 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1805 .copy = &evergreen_copy_dma,
1806 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
be63fe8c
AD		 1807 },
1808 .surface = {
1809 .set_reg = r600_set_surface_reg,
1810 .clear_reg = r600_clear_surface_reg,
1811 },
1812 .hpd = {
1813 .init = &evergreen_hpd_init,
1814 .fini = &evergreen_hpd_fini,
1815 .sense = &evergreen_hpd_sense,
1816 .set_polarity = &evergreen_hpd_set_polarity,
1817 },
1818 .pm = {
1819 .misc = &evergreen_pm_misc,
1820 .prepare = &evergreen_pm_prepare,
1821 .finish = &evergreen_pm_finish,
1822 .init_profile = &sumo_pm_init_profile,
1823 .get_dynpm_state = &r600_pm_get_dynpm_state,
1824 .get_engine_clock = &radeon_atom_get_engine_clock,
1825 .set_engine_clock = &radeon_atom_set_engine_clock,
1826 .get_memory_clock = NULL,
1827 .set_memory_clock = NULL,
1828 .get_pcie_lanes = NULL,
1829 .set_pcie_lanes = NULL,
1830 .set_clock_gating = NULL,
23d33ba3 1831 .set_uvd_clocks = &sumo_set_uvd_clocks,
29a15221 1832 .get_temperature = &tn_get_temp,
be63fe8c 1833 },
d70229f7
AD		 1834 .dpm = {
1835 .init = &trinity_dpm_init,
1836 .setup_asic = &trinity_dpm_setup_asic,
1837 .enable = &trinity_dpm_enable,
bda44c1a 1838 .late_enable = &trinity_dpm_late_enable,
d70229f7 1839 .disable = &trinity_dpm_disable,
a284c48a 1840 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
d70229f7 1841 .set_power_state = &trinity_dpm_set_power_state,
a284c48a 1842 .post_set_power_state = &trinity_dpm_post_set_power_state,
d70229f7
AD		 1843 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
1844 .fini = &trinity_dpm_fini,
1845 .get_sclk = &trinity_dpm_get_sclk,
1846 .get_mclk = &trinity_dpm_get_mclk,
1847 .print_power_state = &trinity_dpm_print_power_state,
490ab931 1848 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
9b5de596 1849 .force_performance_level = &trinity_dpm_force_performance_level,
11877060 1850 .enable_bapm = &trinity_dpm_enable_bapm,
7ce9cdae
AD		 1851 .get_current_sclk = &trinity_dpm_get_current_sclk,
1852 .get_current_mclk = &trinity_dpm_get_current_mclk,
d70229f7 1853 },
be63fe8c 1854 .pflip = {
be63fe8c 1855 .page_flip = &evergreen_page_flip,
157fa14d 1856 .page_flip_pending = &evergreen_page_flip_pending,
be63fe8c
AD		 1857 },
1858};
1859
76a0df85
CK		 1860static struct radeon_asic_ring si_gfx_ring = {
1861 .ib_execute = &si_ring_ib_execute,
1862 .ib_parse = &si_ib_parse,
1863 .emit_fence = &si_fence_ring_emit,
1864 .emit_semaphore = &r600_semaphore_ring_emit,
1865 .cs_parse = NULL,
1866 .ring_test = &r600_ring_test,
1867 .ib_test = &r600_ib_test,
1868 .is_lockup = &si_gfx_is_lockup,
1869 .vm_flush = &si_vm_flush,
ea31bf69
AD		 1870 .get_rptr = &cayman_gfx_get_rptr,
1871 .get_wptr = &cayman_gfx_get_wptr,
1872 .set_wptr = &cayman_gfx_set_wptr,
76a0df85
CK		 1873};
1874
1875static struct radeon_asic_ring si_dma_ring = {
1876 .ib_execute = &cayman_dma_ring_ib_execute,
1877 .ib_parse = &evergreen_dma_ib_parse,
1878 .emit_fence = &evergreen_dma_fence_ring_emit,
1879 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1880 .cs_parse = NULL,
1881 .ring_test = &r600_dma_ring_test,
1882 .ib_test = &r600_dma_ib_test,
1883 .is_lockup = &si_dma_is_lockup,
1884 .vm_flush = &si_dma_vm_flush,
ea31bf69
AD		 1885 .get_rptr = &cayman_dma_get_rptr,
1886 .get_wptr = &cayman_dma_get_wptr,
1887 .set_wptr = &cayman_dma_set_wptr,
76a0df85
CK		 1888};
1889
02779c08
AD		 1890static struct radeon_asic si_asic = {
1891 .init = &si_init,
1892 .fini = &si_fini,
1893 .suspend = &si_suspend,
1894 .resume = &si_resume,
02779c08
AD		 1895 .asic_reset = &si_asic_reset,
1896 .vga_set_state = &r600_vga_set_state,
124764f1 1897 .mmio_hdp_flush = r600_mmio_hdp_flush,
02779c08
AD		 1898 .gui_idle = &r600_gui_idle,
1899 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1900 .get_xclk = &si_get_xclk,
d0418894 1901 .get_gpu_clock_counter = &si_get_gpu_clock_counter,
02779c08
AD		 1902 .gart = {
1903 .tlb_flush = &si_pcie_gart_tlb_flush,
cb658906 1904 .get_page_entry = &rs600_gart_get_page_entry,
02779c08
AD		 1905 .set_page = &rs600_gart_set_page,
1906 },
05b07147
CK		 1907 .vm = {
1908 .init = &si_vm_init,
1909 .fini = &si_vm_fini,
03f62abd
CK		 1910 .copy_pages = &si_dma_vm_copy_pages,
1911 .write_pages = &si_dma_vm_write_pages,
1912 .set_pages = &si_dma_vm_set_pages,
1913 .pad_ib = &cayman_dma_vm_pad_ib,
05b07147 1914 },
02779c08 1915 .ring = {
76a0df85
CK		 1916 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1917 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1918 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1919 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1920 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1921 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
02779c08
AD		 1922 },
1923 .irq = {
1924 .set = &si_irq_set,
1925 .process = &si_irq_process,
1926 },
1927 .display = {
1928 .bandwidth_update = &dce6_bandwidth_update,
1929 .get_vblank_counter = &evergreen_get_vblank_counter,
1930 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1931 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1932 .get_backlight_level = &atombios_get_backlight_level,
02779c08
AD		 1933 },
1934 .copy = {
5c722739 1935 .blit = &r600_copy_cpdma,
02779c08 1936 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
8c5fd7ef
AD		 1937 .dma = &si_copy_dma,
1938 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1939 .copy = &si_copy_dma,
1940 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
02779c08
AD		 1941 },
1942 .surface = {
1943 .set_reg = r600_set_surface_reg,
1944 .clear_reg = r600_clear_surface_reg,
1945 },
1946 .hpd = {
1947 .init = &evergreen_hpd_init,
1948 .fini = &evergreen_hpd_fini,
1949 .sense = &evergreen_hpd_sense,
1950 .set_polarity = &evergreen_hpd_set_polarity,
1951 },
1952 .pm = {
1953 .misc = &evergreen_pm_misc,
1954 .prepare = &evergreen_pm_prepare,
1955 .finish = &evergreen_pm_finish,
1956 .init_profile = &sumo_pm_init_profile,
1957 .get_dynpm_state = &r600_pm_get_dynpm_state,
1958 .get_engine_clock = &radeon_atom_get_engine_clock,
1959 .set_engine_clock = &radeon_atom_set_engine_clock,
1960 .get_memory_clock = &radeon_atom_get_memory_clock,
1961 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1962 .get_pcie_lanes = &r600_get_pcie_lanes,
1963 .set_pcie_lanes = &r600_set_pcie_lanes,
02779c08 1964 .set_clock_gating = NULL,
2539eb02 1965 .set_uvd_clocks = &si_set_uvd_clocks,
6bd1c385 1966 .get_temperature = &si_get_temp,
02779c08 1967 },
a9e61410
AD		 1968 .dpm = {
1969 .init = &si_dpm_init,
1970 .setup_asic = &si_dpm_setup_asic,
1971 .enable = &si_dpm_enable,
963c115d 1972 .late_enable = &si_dpm_late_enable,
a9e61410
AD		 1973 .disable = &si_dpm_disable,
1974 .pre_set_power_state = &si_dpm_pre_set_power_state,
1975 .set_power_state = &si_dpm_set_power_state,
1976 .post_set_power_state = &si_dpm_post_set_power_state,
1977 .display_configuration_changed = &si_dpm_display_configuration_changed,
1978 .fini = &si_dpm_fini,
1979 .get_sclk = &ni_dpm_get_sclk,
1980 .get_mclk = &ni_dpm_get_mclk,
1981 .print_power_state = &ni_dpm_print_power_state,
7982128c 1982 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
a160a6a3 1983 .force_performance_level = &si_dpm_force_performance_level,
f4dec318 1984 .vblank_too_short = &ni_dpm_vblank_too_short,
5e8150a6
AD		 1985 .fan_ctrl_set_mode = &si_fan_ctrl_set_mode,
1986 .fan_ctrl_get_mode = &si_fan_ctrl_get_mode,
1987 .get_fan_speed_percent = &si_fan_ctrl_get_fan_speed_percent,
1988 .set_fan_speed_percent = &si_fan_ctrl_set_fan_speed_percent,
ca1110bc
AD		 1989 .get_current_sclk = &si_dpm_get_current_sclk,
1990 .get_current_mclk = &si_dpm_get_current_mclk,
a9e61410 1991 },
02779c08 1992 .pflip = {
02779c08 1993 .page_flip = &evergreen_page_flip,
157fa14d 1994 .page_flip_pending = &evergreen_page_flip_pending,
02779c08
AD		 1995 },
1996};
1997
76a0df85
CK		 1998static struct radeon_asic_ring ci_gfx_ring = {
1999 .ib_execute = &cik_ring_ib_execute,
2000 .ib_parse = &cik_ib_parse,
2001 .emit_fence = &cik_fence_gfx_ring_emit,
2002 .emit_semaphore = &cik_semaphore_ring_emit,
2003 .cs_parse = NULL,
2004 .ring_test = &cik_ring_test,
2005 .ib_test = &cik_ib_test,
2006 .is_lockup = &cik_gfx_is_lockup,
2007 .vm_flush = &cik_vm_flush,
ea31bf69
AD		 2008 .get_rptr = &cik_gfx_get_rptr,
2009 .get_wptr = &cik_gfx_get_wptr,
2010 .set_wptr = &cik_gfx_set_wptr,
76a0df85
CK		 2011};
2012
2013static struct radeon_asic_ring ci_cp_ring = {
2014 .ib_execute = &cik_ring_ib_execute,
2015 .ib_parse = &cik_ib_parse,
2016 .emit_fence = &cik_fence_compute_ring_emit,
2017 .emit_semaphore = &cik_semaphore_ring_emit,
2018 .cs_parse = NULL,
2019 .ring_test = &cik_ring_test,
2020 .ib_test = &cik_ib_test,
2021 .is_lockup = &cik_gfx_is_lockup,
2022 .vm_flush = &cik_vm_flush,
ea31bf69
AD		 2023 .get_rptr = &cik_compute_get_rptr,
2024 .get_wptr = &cik_compute_get_wptr,
2025 .set_wptr = &cik_compute_set_wptr,
76a0df85
CK		 2026};
2027
2028static struct radeon_asic_ring ci_dma_ring = {
2029 .ib_execute = &cik_sdma_ring_ib_execute,
2030 .ib_parse = &cik_ib_parse,
2031 .emit_fence = &cik_sdma_fence_ring_emit,
2032 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2033 .cs_parse = NULL,
2034 .ring_test = &cik_sdma_ring_test,
2035 .ib_test = &cik_sdma_ib_test,
2036 .is_lockup = &cik_sdma_is_lockup,
2037 .vm_flush = &cik_dma_vm_flush,
ea31bf69
AD		 2038 .get_rptr = &cik_sdma_get_rptr,
2039 .get_wptr = &cik_sdma_get_wptr,
2040 .set_wptr = &cik_sdma_set_wptr,
76a0df85
CK		 2041};
2042
d93f7937
CK		 2043static struct radeon_asic_ring ci_vce_ring = {
2044 .ib_execute = &radeon_vce_ib_execute,
2045 .emit_fence = &radeon_vce_fence_emit,
2046 .emit_semaphore = &radeon_vce_semaphore_emit,
2047 .cs_parse = &radeon_vce_cs_parse,
2048 .ring_test = &radeon_vce_ring_test,
2049 .ib_test = &radeon_vce_ib_test,
2050 .is_lockup = &radeon_ring_test_lockup,
2051 .get_rptr = &vce_v1_0_get_rptr,
2052 .get_wptr = &vce_v1_0_get_wptr,
2053 .set_wptr = &vce_v1_0_set_wptr,
2054};
2055
0672e27b
AD		 2056static struct radeon_asic ci_asic = {
2057 .init = &cik_init,
2058 .fini = &cik_fini,
2059 .suspend = &cik_suspend,
2060 .resume = &cik_resume,
2061 .asic_reset = &cik_asic_reset,
2062 .vga_set_state = &r600_vga_set_state,
72a9987e 2063 .mmio_hdp_flush = &r600_mmio_hdp_flush,
0672e27b
AD		 2064 .gui_idle = &r600_gui_idle,
2065 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2066 .get_xclk = &cik_get_xclk,
2067 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2068 .gart = {
2069 .tlb_flush = &cik_pcie_gart_tlb_flush,
cb658906 2070 .get_page_entry = &rs600_gart_get_page_entry,
0672e27b
AD		 2071 .set_page = &rs600_gart_set_page,
2072 },
2073 .vm = {
2074 .init = &cik_vm_init,
2075 .fini = &cik_vm_fini,
03f62abd
CK		 2076 .copy_pages = &cik_sdma_vm_copy_pages,
2077 .write_pages = &cik_sdma_vm_write_pages,
2078 .set_pages = &cik_sdma_vm_set_pages,
2079 .pad_ib = &cik_sdma_vm_pad_ib,
0672e27b
AD		 2080 },
2081 .ring = {
76a0df85
CK		 2082 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2083 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2084 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2085 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2086 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2087 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
d93f7937
CK		 2088 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2089 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
0672e27b
AD		 2090 },
2091 .irq = {
2092 .set = &cik_irq_set,
2093 .process = &cik_irq_process,
2094 },
2095 .display = {
2096 .bandwidth_update = &dce8_bandwidth_update,
2097 .get_vblank_counter = &evergreen_get_vblank_counter,
2098 .wait_for_vblank = &dce4_wait_for_vblank,
7272c9d2
SL		 2099 .set_backlight_level = &atombios_set_backlight_level,
2100 .get_backlight_level = &atombios_get_backlight_level,
0672e27b
AD		 2101 },
2102 .copy = {
7819678f 2103 .blit = &cik_copy_cpdma,
0672e27b
AD		 2104 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2105 .dma = &cik_copy_dma,
2106 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
b5be1a83
CK		 2107 .copy = &cik_copy_dma,
2108 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
0672e27b
AD		 2109 },
2110 .surface = {
2111 .set_reg = r600_set_surface_reg,
2112 .clear_reg = r600_clear_surface_reg,
2113 },
2114 .hpd = {
2115 .init = &evergreen_hpd_init,
2116 .fini = &evergreen_hpd_fini,
2117 .sense = &evergreen_hpd_sense,
2118 .set_polarity = &evergreen_hpd_set_polarity,
2119 },
2120 .pm = {
2121 .misc = &evergreen_pm_misc,
2122 .prepare = &evergreen_pm_prepare,
2123 .finish = &evergreen_pm_finish,
2124 .init_profile = &sumo_pm_init_profile,
2125 .get_dynpm_state = &r600_pm_get_dynpm_state,
2126 .get_engine_clock = &radeon_atom_get_engine_clock,
2127 .set_engine_clock = &radeon_atom_set_engine_clock,
2128 .get_memory_clock = &radeon_atom_get_memory_clock,
2129 .set_memory_clock = &radeon_atom_set_memory_clock,
2130 .get_pcie_lanes = NULL,
2131 .set_pcie_lanes = NULL,
2132 .set_clock_gating = NULL,
2133 .set_uvd_clocks = &cik_set_uvd_clocks,
5ad6bf91 2134 .set_vce_clocks = &cik_set_vce_clocks,
286d9cc6 2135 .get_temperature = &ci_get_temp,
0672e27b 2136 },
cc8dbbb4
AD		 2137 .dpm = {
2138 .init = &ci_dpm_init,
2139 .setup_asic = &ci_dpm_setup_asic,
2140 .enable = &ci_dpm_enable,
90208427 2141 .late_enable = &ci_dpm_late_enable,
cc8dbbb4
AD		 2142 .disable = &ci_dpm_disable,
2143 .pre_set_power_state = &ci_dpm_pre_set_power_state,
2144 .set_power_state = &ci_dpm_set_power_state,
2145 .post_set_power_state = &ci_dpm_post_set_power_state,
2146 .display_configuration_changed = &ci_dpm_display_configuration_changed,
2147 .fini = &ci_dpm_fini,
2148 .get_sclk = &ci_dpm_get_sclk,
2149 .get_mclk = &ci_dpm_get_mclk,
2150 .print_power_state = &ci_dpm_print_power_state,
94b4adc5 2151 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
89536fd6 2152 .force_performance_level = &ci_dpm_force_performance_level,
5496131e 2153 .vblank_too_short = &ci_dpm_vblank_too_short,
942bdf7f 2154 .powergate_uvd = &ci_dpm_powergate_uvd,
36689e57
OC		 2155 .fan_ctrl_set_mode = &ci_fan_ctrl_set_mode,
2156 .fan_ctrl_get_mode = &ci_fan_ctrl_get_mode,
2157 .get_fan_speed_percent = &ci_fan_ctrl_get_fan_speed_percent,
2158 .set_fan_speed_percent = &ci_fan_ctrl_set_fan_speed_percent,
dbbd3c81
AD		 2159 .get_current_sclk = &ci_dpm_get_current_sclk,
2160 .get_current_mclk = &ci_dpm_get_current_mclk,
cc8dbbb4 2161 },
0672e27b 2162 .pflip = {
0672e27b 2163 .page_flip = &evergreen_page_flip,
157fa14d 2164 .page_flip_pending = &evergreen_page_flip_pending,
0672e27b
AD		 2165 },
2166};
2167
2168static struct radeon_asic kv_asic = {
2169 .init = &cik_init,
2170 .fini = &cik_fini,
2171 .suspend = &cik_suspend,
2172 .resume = &cik_resume,
2173 .asic_reset = &cik_asic_reset,
2174 .vga_set_state = &r600_vga_set_state,
72a9987e 2175 .mmio_hdp_flush = &r600_mmio_hdp_flush,
0672e27b
AD		 2176 .gui_idle = &r600_gui_idle,
2177 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2178 .get_xclk = &cik_get_xclk,
2179 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2180 .gart = {
2181 .tlb_flush = &cik_pcie_gart_tlb_flush,
cb658906 2182 .get_page_entry = &rs600_gart_get_page_entry,
0672e27b
AD		 2183 .set_page = &rs600_gart_set_page,
2184 },
2185 .vm = {
2186 .init = &cik_vm_init,
2187 .fini = &cik_vm_fini,
03f62abd
CK		 2188 .copy_pages = &cik_sdma_vm_copy_pages,
2189 .write_pages = &cik_sdma_vm_write_pages,
2190 .set_pages = &cik_sdma_vm_set_pages,
2191 .pad_ib = &cik_sdma_vm_pad_ib,
0672e27b
AD		 2192 },
2193 .ring = {
76a0df85
CK		 2194 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2195 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2196 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2197 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2198 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2199 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
d93f7937
CK		 2200 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2201 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
0672e27b
AD		 2202 },
2203 .irq = {
2204 .set = &cik_irq_set,
2205 .process = &cik_irq_process,
2206 },
2207 .display = {
2208 .bandwidth_update = &dce8_bandwidth_update,
2209 .get_vblank_counter = &evergreen_get_vblank_counter,
2210 .wait_for_vblank = &dce4_wait_for_vblank,
7272c9d2
SL		 2211 .set_backlight_level = &atombios_set_backlight_level,
2212 .get_backlight_level = &atombios_get_backlight_level,
0672e27b
AD		 2213 },
2214 .copy = {
7819678f 2215 .blit = &cik_copy_cpdma,
0672e27b
AD		 2216 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2217 .dma = &cik_copy_dma,
2218 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2219 .copy = &cik_copy_dma,
2220 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2221 },
2222 .surface = {
2223 .set_reg = r600_set_surface_reg,
2224 .clear_reg = r600_clear_surface_reg,
2225 },
2226 .hpd = {
2227 .init = &evergreen_hpd_init,
2228 .fini = &evergreen_hpd_fini,
2229 .sense = &evergreen_hpd_sense,
2230 .set_polarity = &evergreen_hpd_set_polarity,
2231 },
2232 .pm = {
2233 .misc = &evergreen_pm_misc,
2234 .prepare = &evergreen_pm_prepare,
2235 .finish = &evergreen_pm_finish,
2236 .init_profile = &sumo_pm_init_profile,
2237 .get_dynpm_state = &r600_pm_get_dynpm_state,
2238 .get_engine_clock = &radeon_atom_get_engine_clock,
2239 .set_engine_clock = &radeon_atom_set_engine_clock,
2240 .get_memory_clock = &radeon_atom_get_memory_clock,
2241 .set_memory_clock = &radeon_atom_set_memory_clock,
2242 .get_pcie_lanes = NULL,
2243 .set_pcie_lanes = NULL,
2244 .set_clock_gating = NULL,
2245 .set_uvd_clocks = &cik_set_uvd_clocks,
5ad6bf91 2246 .set_vce_clocks = &cik_set_vce_clocks,
286d9cc6 2247 .get_temperature = &kv_get_temp,
0672e27b 2248 },
41a524ab
AD		 2249 .dpm = {
2250 .init = &kv_dpm_init,
2251 .setup_asic = &kv_dpm_setup_asic,
2252 .enable = &kv_dpm_enable,
d8852c34 2253 .late_enable = &kv_dpm_late_enable,
41a524ab
AD		 2254 .disable = &kv_dpm_disable,
2255 .pre_set_power_state = &kv_dpm_pre_set_power_state,
2256 .set_power_state = &kv_dpm_set_power_state,
2257 .post_set_power_state = &kv_dpm_post_set_power_state,
2258 .display_configuration_changed = &kv_dpm_display_configuration_changed,
2259 .fini = &kv_dpm_fini,
2260 .get_sclk = &kv_dpm_get_sclk,
2261 .get_mclk = &kv_dpm_get_mclk,
2262 .print_power_state = &kv_dpm_print_power_state,
ae3e40e8 2263 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2b4c8022 2264 .force_performance_level = &kv_dpm_force_performance_level,
77df508a 2265 .powergate_uvd = &kv_dpm_powergate_uvd,
b7a5ae97 2266 .enable_bapm = &kv_dpm_enable_bapm,
9b23bad0
AD		 2267 .get_current_sclk = &kv_dpm_get_current_sclk,
2268 .get_current_mclk = &kv_dpm_get_current_mclk,
41a524ab 2269 },
0672e27b 2270 .pflip = {
0672e27b 2271 .page_flip = &evergreen_page_flip,
157fa14d 2272 .page_flip_pending = &evergreen_page_flip_pending,
0672e27b
AD		 2273 },
2274};
2275
abf1dc67
AD		 2276/**
2277 * radeon_asic_init - register asic specific callbacks
2278 *
2279 * @rdev: radeon device pointer
2280 *
2281 * Registers the appropriate asic specific callbacks for each
2282 * chip family. Also sets other asics specific info like the number
2283 * of crtcs and the register aperture accessors (all asics).
2284 * Returns 0 for success.
2285 */
0a10c851
DV		 2286int radeon_asic_init(struct radeon_device *rdev)
2287{
2288 radeon_register_accessor_init(rdev);
ba7e05e9
AD		 2289
2290 /* set the number of crtcs */
2291 if (rdev->flags & RADEON_SINGLE_CRTC)
2292 rdev->num_crtc = 1;
2293 else
2294 rdev->num_crtc = 2;
2295
948bee3f
AD		 2296 rdev->has_uvd = false;
2297
0a10c851
DV		 2298 switch (rdev->family) {
2299 case CHIP_R100:
2300 case CHIP_RV100:
2301 case CHIP_RS100:
2302 case CHIP_RV200:
2303 case CHIP_RS200:
2304 rdev->asic = &r100_asic;
2305 break;
2306 case CHIP_R200:
2307 case CHIP_RV250:
2308 case CHIP_RS300:
2309 case CHIP_RV280:
2310 rdev->asic = &r200_asic;
2311 break;
2312 case CHIP_R300:
2313 case CHIP_R350:
2314 case CHIP_RV350:
2315 case CHIP_RV380:
2316 if (rdev->flags & RADEON_IS_PCIE)
2317 rdev->asic = &r300_asic_pcie;
2318 else
2319 rdev->asic = &r300_asic;
2320 break;
2321 case CHIP_R420:
2322 case CHIP_R423:
2323 case CHIP_RV410:
2324 rdev->asic = &r420_asic;
07bb084c
AD		 2325 /* handle macs */
2326 if (rdev->bios == NULL) {
798bcf73
AD		 2327 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2328 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2329 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2330 rdev->asic->pm.set_memory_clock = NULL;
37e9b6a6 2331 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
07bb084c 2332 }
0a10c851
DV		 2333 break;
2334 case CHIP_RS400:
2335 case CHIP_RS480:
2336 rdev->asic = &rs400_asic;
2337 break;
2338 case CHIP_RS600:
2339 rdev->asic = &rs600_asic;
2340 break;
2341 case CHIP_RS690:
2342 case CHIP_RS740:
2343 rdev->asic = &rs690_asic;
2344 break;
2345 case CHIP_RV515:
2346 rdev->asic = &rv515_asic;
2347 break;
2348 case CHIP_R520:
2349 case CHIP_RV530:
2350 case CHIP_RV560:
2351 case CHIP_RV570:
2352 case CHIP_R580:
2353 rdev->asic = &r520_asic;
2354 break;
2355 case CHIP_R600:
ca361b65
AD		 2356 rdev->asic = &r600_asic;
2357 break;
0a10c851
DV		 2358 case CHIP_RV610:
2359 case CHIP_RV630:
2360 case CHIP_RV620:
2361 case CHIP_RV635:
2362 case CHIP_RV670:
ca361b65
AD		 2363 rdev->asic = &rv6xx_asic;
2364 rdev->has_uvd = true;
f47299c5 2365 break;
0a10c851
DV		 2366 case CHIP_RS780:
2367 case CHIP_RS880:
f47299c5 2368 rdev->asic = &rs780_asic;
bdc99722
AD		 2369 /* 760G/780V/880V don't have UVD */
2370 if ((rdev->pdev->device == 0x9616)||
2371 (rdev->pdev->device == 0x9611)||
2372 (rdev->pdev->device == 0x9613)||
2373 (rdev->pdev->device == 0x9711)||
2374 (rdev->pdev->device == 0x9713))
2375 rdev->has_uvd = false;
2376 else
2377 rdev->has_uvd = true;
0a10c851
DV		 2378 break;
2379 case CHIP_RV770:
2380 case CHIP_RV730:
2381 case CHIP_RV710:
2382 case CHIP_RV740:
2383 rdev->asic = &rv770_asic;
948bee3f 2384 rdev->has_uvd = true;
0a10c851
DV		 2385 break;
2386 case CHIP_CEDAR:
2387 case CHIP_REDWOOD:
2388 case CHIP_JUNIPER:
2389 case CHIP_CYPRESS:
2390 case CHIP_HEMLOCK:
ba7e05e9
AD		 2391 /* set num crtcs */
2392 if (rdev->family == CHIP_CEDAR)
2393 rdev->num_crtc = 4;
2394 else
2395 rdev->num_crtc = 6;
0a10c851 2396 rdev->asic = &evergreen_asic;
948bee3f 2397 rdev->has_uvd = true;
0a10c851 2398 break;
958261d1 2399 case CHIP_PALM:
89da5a37
AD		 2400 case CHIP_SUMO:
2401 case CHIP_SUMO2:
958261d1 2402 rdev->asic = &sumo_asic;
948bee3f 2403 rdev->has_uvd = true;
958261d1 2404 break;
a43b7665
AD		 2405 case CHIP_BARTS:
2406 case CHIP_TURKS:
2407 case CHIP_CAICOS:
ba7e05e9
AD		 2408 /* set num crtcs */
2409 if (rdev->family == CHIP_CAICOS)
2410 rdev->num_crtc = 4;
2411 else
2412 rdev->num_crtc = 6;
a43b7665 2413 rdev->asic = &btc_asic;
948bee3f 2414 rdev->has_uvd = true;
a43b7665 2415 break;
e3487629
AD		 2416 case CHIP_CAYMAN:
2417 rdev->asic = &cayman_asic;
ba7e05e9
AD		 2418 /* set num crtcs */
2419 rdev->num_crtc = 6;
948bee3f 2420 rdev->has_uvd = true;
e3487629 2421 break;
be63fe8c
AD		 2422 case CHIP_ARUBA:
2423 rdev->asic = &trinity_asic;
2424 /* set num crtcs */
2425 rdev->num_crtc = 4;
948bee3f 2426 rdev->has_uvd = true;
be63fe8c 2427 break;
02779c08
AD		 2428 case CHIP_TAHITI:
2429 case CHIP_PITCAIRN:
2430 case CHIP_VERDE:
e737a14c 2431 case CHIP_OLAND:
86a45cac 2432 case CHIP_HAINAN:
02779c08
AD		 2433 rdev->asic = &si_asic;
2434 /* set num crtcs */
86a45cac
AD		 2435 if (rdev->family == CHIP_HAINAN)
2436 rdev->num_crtc = 0;
2437 else if (rdev->family == CHIP_OLAND)
e737a14c
AD		 2438 rdev->num_crtc = 2;
2439 else
2440 rdev->num_crtc = 6;
948bee3f
AD		 2441 if (rdev->family == CHIP_HAINAN)
2442 rdev->has_uvd = false;
2443 else
2444 rdev->has_uvd = true;
0116e1ef
AD		 2445 switch (rdev->family) {
2446 case CHIP_TAHITI:
2447 rdev->cg_flags =
090f4b6a 2448 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2449 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2450 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2451 RADEON_CG_SUPPORT_GFX_CGLS |
2452 RADEON_CG_SUPPORT_GFX_CGTS |
2453 RADEON_CG_SUPPORT_GFX_CP_LS |
2454 RADEON_CG_SUPPORT_MC_MGCG |
2455 RADEON_CG_SUPPORT_SDMA_MGCG |
2456 RADEON_CG_SUPPORT_BIF_LS |
2457 RADEON_CG_SUPPORT_VCE_MGCG |
2458 RADEON_CG_SUPPORT_UVD_MGCG |
2459 RADEON_CG_SUPPORT_HDP_LS |
2460 RADEON_CG_SUPPORT_HDP_MGCG;
2461 rdev->pg_flags = 0;
2462 break;
2463 case CHIP_PITCAIRN:
2464 rdev->cg_flags =
090f4b6a 2465 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2466 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2467 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2468 RADEON_CG_SUPPORT_GFX_CGLS |
2469 RADEON_CG_SUPPORT_GFX_CGTS |
2470 RADEON_CG_SUPPORT_GFX_CP_LS |
2471 RADEON_CG_SUPPORT_GFX_RLC_LS |
2472 RADEON_CG_SUPPORT_MC_LS |
2473 RADEON_CG_SUPPORT_MC_MGCG |
2474 RADEON_CG_SUPPORT_SDMA_MGCG |
2475 RADEON_CG_SUPPORT_BIF_LS |
2476 RADEON_CG_SUPPORT_VCE_MGCG |
2477 RADEON_CG_SUPPORT_UVD_MGCG |
2478 RADEON_CG_SUPPORT_HDP_LS |
2479 RADEON_CG_SUPPORT_HDP_MGCG;
2480 rdev->pg_flags = 0;
2481 break;
2482 case CHIP_VERDE:
2483 rdev->cg_flags =
090f4b6a 2484 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2485 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2486 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2487 RADEON_CG_SUPPORT_GFX_CGLS |
2488 RADEON_CG_SUPPORT_GFX_CGTS |
2489 RADEON_CG_SUPPORT_GFX_CP_LS |
2490 RADEON_CG_SUPPORT_GFX_RLC_LS |
2491 RADEON_CG_SUPPORT_MC_LS |
2492 RADEON_CG_SUPPORT_MC_MGCG |
2493 RADEON_CG_SUPPORT_SDMA_MGCG |
2494 RADEON_CG_SUPPORT_BIF_LS |
2495 RADEON_CG_SUPPORT_VCE_MGCG |
2496 RADEON_CG_SUPPORT_UVD_MGCG |
2497 RADEON_CG_SUPPORT_HDP_LS |
2498 RADEON_CG_SUPPORT_HDP_MGCG;
ca6ebb39 2499 rdev->pg_flags = 0 |
2b19d17f 2500 /*RADEON_PG_SUPPORT_GFX_PG | */
ca6ebb39 2501 RADEON_PG_SUPPORT_SDMA;
0116e1ef
AD		 2502 break;
2503 case CHIP_OLAND:
2504 rdev->cg_flags =
090f4b6a 2505 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2506 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2507 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2508 RADEON_CG_SUPPORT_GFX_CGLS |
2509 RADEON_CG_SUPPORT_GFX_CGTS |
2510 RADEON_CG_SUPPORT_GFX_CP_LS |
2511 RADEON_CG_SUPPORT_GFX_RLC_LS |
2512 RADEON_CG_SUPPORT_MC_LS |
2513 RADEON_CG_SUPPORT_MC_MGCG |
2514 RADEON_CG_SUPPORT_SDMA_MGCG |
2515 RADEON_CG_SUPPORT_BIF_LS |
2516 RADEON_CG_SUPPORT_UVD_MGCG |
2517 RADEON_CG_SUPPORT_HDP_LS |
2518 RADEON_CG_SUPPORT_HDP_MGCG;
2519 rdev->pg_flags = 0;
2520 break;
2521 case CHIP_HAINAN:
2522 rdev->cg_flags =
090f4b6a 2523 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2524 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2525 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2526 RADEON_CG_SUPPORT_GFX_CGLS |
2527 RADEON_CG_SUPPORT_GFX_CGTS |
2528 RADEON_CG_SUPPORT_GFX_CP_LS |
2529 RADEON_CG_SUPPORT_GFX_RLC_LS |
2530 RADEON_CG_SUPPORT_MC_LS |
2531 RADEON_CG_SUPPORT_MC_MGCG |
2532 RADEON_CG_SUPPORT_SDMA_MGCG |
2533 RADEON_CG_SUPPORT_BIF_LS |
2534 RADEON_CG_SUPPORT_HDP_LS |
2535 RADEON_CG_SUPPORT_HDP_MGCG;
2536 rdev->pg_flags = 0;
2537 break;
2538 default:
2539 rdev->cg_flags = 0;
2540 rdev->pg_flags = 0;
2541 break;
2542 }
02779c08 2543 break;
0672e27b 2544 case CHIP_BONAIRE:
41971b37 2545 case CHIP_HAWAII:
0672e27b
AD		 2546 rdev->asic = &ci_asic;
2547 rdev->num_crtc = 6;
22c775ce 2548 rdev->has_uvd = true;
41971b37
AD		 2549 if (rdev->family == CHIP_BONAIRE) {
2550 rdev->cg_flags =
2551 RADEON_CG_SUPPORT_GFX_MGCG |
2552 RADEON_CG_SUPPORT_GFX_MGLS |
6960948d 2553 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
41971b37
AD		 2554 RADEON_CG_SUPPORT_GFX_CGLS |
2555 RADEON_CG_SUPPORT_GFX_CGTS |
2556 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2557 RADEON_CG_SUPPORT_GFX_CP_LS |
2558 RADEON_CG_SUPPORT_MC_LS |
2559 RADEON_CG_SUPPORT_MC_MGCG |
2560 RADEON_CG_SUPPORT_SDMA_MGCG |
2561 RADEON_CG_SUPPORT_SDMA_LS |
2562 RADEON_CG_SUPPORT_BIF_LS |
2563 RADEON_CG_SUPPORT_VCE_MGCG |
2564 RADEON_CG_SUPPORT_UVD_MGCG |
2565 RADEON_CG_SUPPORT_HDP_LS |
2566 RADEON_CG_SUPPORT_HDP_MGCG;
2567 rdev->pg_flags = 0;
2568 } else {
2569 rdev->cg_flags =
2570 RADEON_CG_SUPPORT_GFX_MGCG |
2571 RADEON_CG_SUPPORT_GFX_MGLS |
6960948d 2572 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
41971b37
AD		 2573 RADEON_CG_SUPPORT_GFX_CGLS |
2574 RADEON_CG_SUPPORT_GFX_CGTS |
2575 RADEON_CG_SUPPORT_GFX_CP_LS |
2576 RADEON_CG_SUPPORT_MC_LS |
2577 RADEON_CG_SUPPORT_MC_MGCG |
2578 RADEON_CG_SUPPORT_SDMA_MGCG |
2579 RADEON_CG_SUPPORT_SDMA_LS |
2580 RADEON_CG_SUPPORT_BIF_LS |
2581 RADEON_CG_SUPPORT_VCE_MGCG |
2582 RADEON_CG_SUPPORT_UVD_MGCG |
2583 RADEON_CG_SUPPORT_HDP_LS |
2584 RADEON_CG_SUPPORT_HDP_MGCG;
2585 rdev->pg_flags = 0;
2586 }
0672e27b
AD		 2587 break;
2588 case CHIP_KAVERI:
2589 case CHIP_KABINI:
b0a9f22a 2590 case CHIP_MULLINS:
0672e27b
AD		 2591 rdev->asic = &kv_asic;
2592 /* set num crtcs */
473359bc 2593 if (rdev->family == CHIP_KAVERI) {
0672e27b 2594 rdev->num_crtc = 4;
473359bc 2595 rdev->cg_flags =
773dc10a 2596 RADEON_CG_SUPPORT_GFX_MGCG |
473359bc 2597 RADEON_CG_SUPPORT_GFX_MGLS |
6960948d 2598 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
473359bc
AD		 2599 RADEON_CG_SUPPORT_GFX_CGLS |
2600 RADEON_CG_SUPPORT_GFX_CGTS |
2601 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2602 RADEON_CG_SUPPORT_GFX_CP_LS |
2603 RADEON_CG_SUPPORT_SDMA_MGCG |
2604 RADEON_CG_SUPPORT_SDMA_LS |
2605 RADEON_CG_SUPPORT_BIF_LS |
2606 RADEON_CG_SUPPORT_VCE_MGCG |
2607 RADEON_CG_SUPPORT_UVD_MGCG |
2608 RADEON_CG_SUPPORT_HDP_LS |
2609 RADEON_CG_SUPPORT_HDP_MGCG;
2610 rdev->pg_flags = 0;
2b19d17f 2611 /*RADEON_PG_SUPPORT_GFX_PG |
473359bc
AD		 2612 RADEON_PG_SUPPORT_GFX_SMG |
2613 RADEON_PG_SUPPORT_GFX_DMG |
2614 RADEON_PG_SUPPORT_UVD |
2615 RADEON_PG_SUPPORT_VCE |
2616 RADEON_PG_SUPPORT_CP |
2617 RADEON_PG_SUPPORT_GDS |
2618 RADEON_PG_SUPPORT_RLC_SMU_HS |
2619 RADEON_PG_SUPPORT_ACP |
2620 RADEON_PG_SUPPORT_SAMU;*/
2621 } else {
0672e27b 2622 rdev->num_crtc = 2;
473359bc 2623 rdev->cg_flags =
773dc10a 2624 RADEON_CG_SUPPORT_GFX_MGCG |
473359bc 2625 RADEON_CG_SUPPORT_GFX_MGLS |
6960948d 2626 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
473359bc
AD		 2627 RADEON_CG_SUPPORT_GFX_CGLS |
2628 RADEON_CG_SUPPORT_GFX_CGTS |
2629 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2630 RADEON_CG_SUPPORT_GFX_CP_LS |
2631 RADEON_CG_SUPPORT_SDMA_MGCG |
2632 RADEON_CG_SUPPORT_SDMA_LS |
2633 RADEON_CG_SUPPORT_BIF_LS |
2634 RADEON_CG_SUPPORT_VCE_MGCG |
2635 RADEON_CG_SUPPORT_UVD_MGCG |
2636 RADEON_CG_SUPPORT_HDP_LS |
2637 RADEON_CG_SUPPORT_HDP_MGCG;
2638 rdev->pg_flags = 0;
2b19d17f 2639 /*RADEON_PG_SUPPORT_GFX_PG |
473359bc
AD		 2640 RADEON_PG_SUPPORT_GFX_SMG |
2641 RADEON_PG_SUPPORT_UVD |
2642 RADEON_PG_SUPPORT_VCE |
2643 RADEON_PG_SUPPORT_CP |
2644 RADEON_PG_SUPPORT_GDS |
2645 RADEON_PG_SUPPORT_RLC_SMU_HS |
2646 RADEON_PG_SUPPORT_SAMU;*/
2647 }
22c775ce 2648 rdev->has_uvd = true;
0672e27b 2649 break;
0a10c851
DV		 2650 default:
2651 /* FIXME: not supported yet */
2652 return -EINVAL;
2653 }
2654
2655 if (rdev->flags & RADEON_IS_IGP) {
798bcf73
AD		 2656 rdev->asic->pm.get_memory_clock = NULL;
2657 rdev->asic->pm.set_memory_clock = NULL;
0a10c851
DV		 2658 }
2659
2660 return 0;
2661}
2662
Linux kernel - Deliverables
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