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drm/radeon/dpm: add debugfs support for rv6xx
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_asic.c
CommitLineData
0a10c851
DV		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/console.h>
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
33#include <linux/vgaarb.h>
34#include <linux/vga_switcheroo.h>
35#include "radeon_reg.h"
36#include "radeon.h"
37#include "radeon_asic.h"
38#include "atom.h"
39
40/*
41 * Registers accessors functions.
42 */
abf1dc67
AD		 43/**
44 * radeon_invalid_rreg - dummy reg read function
45 *
46 * @rdev: radeon device pointer
47 * @reg: offset of register
48 *
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
52 */
0a10c851
DV		 53static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54{
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
56 BUG_ON(1);
57 return 0;
58}
59
abf1dc67
AD		 60/**
61 * radeon_invalid_wreg - dummy reg write function
62 *
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
66 *
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
69 */
0a10c851
DV		 70static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
71{
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
73 reg, v);
74 BUG_ON(1);
75}
76
abf1dc67
AD		 77/**
78 * radeon_register_accessor_init - sets up the register accessor callbacks
79 *
80 * @rdev: radeon device pointer
81 *
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
84 */
0a10c851
DV		 85static void radeon_register_accessor_init(struct radeon_device *rdev)
86{
87 rdev->mc_rreg = &radeon_invalid_rreg;
88 rdev->mc_wreg = &radeon_invalid_wreg;
89 rdev->pll_rreg = &radeon_invalid_rreg;
90 rdev->pll_wreg = &radeon_invalid_wreg;
91 rdev->pciep_rreg = &radeon_invalid_rreg;
92 rdev->pciep_wreg = &radeon_invalid_wreg;
93
94 /* Don't change order as we are overridding accessor. */
95 if (rdev->family < CHIP_RV515) {
96 rdev->pcie_reg_mask = 0xff;
97 } else {
98 rdev->pcie_reg_mask = 0x7ff;
99 }
100 /* FIXME: not sure here */
101 if (rdev->family <= CHIP_R580) {
102 rdev->pll_rreg = &r100_pll_rreg;
103 rdev->pll_wreg = &r100_pll_wreg;
104 }
105 if (rdev->family >= CHIP_R420) {
106 rdev->mc_rreg = &r420_mc_rreg;
107 rdev->mc_wreg = &r420_mc_wreg;
108 }
109 if (rdev->family >= CHIP_RV515) {
110 rdev->mc_rreg = &rv515_mc_rreg;
111 rdev->mc_wreg = &rv515_mc_wreg;
112 }
113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
114 rdev->mc_rreg = &rs400_mc_rreg;
115 rdev->mc_wreg = &rs400_mc_wreg;
116 }
117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
118 rdev->mc_rreg = &rs690_mc_rreg;
119 rdev->mc_wreg = &rs690_mc_wreg;
120 }
121 if (rdev->family == CHIP_RS600) {
122 rdev->mc_rreg = &rs600_mc_rreg;
123 rdev->mc_wreg = &rs600_mc_wreg;
124 }
65337e60
SL		 125 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
126 rdev->mc_rreg = &rs780_mc_rreg;
127 rdev->mc_wreg = &rs780_mc_wreg;
128 }
6e2c3c0a
AD		 129
130 if (rdev->family >= CHIP_BONAIRE) {
131 rdev->pciep_rreg = &cik_pciep_rreg;
132 rdev->pciep_wreg = &cik_pciep_wreg;
133 } else if (rdev->family >= CHIP_R600) {
0a10c851
DV		 134 rdev->pciep_rreg = &r600_pciep_rreg;
135 rdev->pciep_wreg = &r600_pciep_wreg;
136 }
137}
138
139
140/* helper to disable agp */
abf1dc67
AD		 141/**
142 * radeon_agp_disable - AGP disable helper function
143 *
144 * @rdev: radeon device pointer
145 *
146 * Removes AGP flags and changes the gart callbacks on AGP
147 * cards when using the internal gart rather than AGP (all asics).
148 */
0a10c851
DV		 149void radeon_agp_disable(struct radeon_device *rdev)
150{
151 rdev->flags &= ~RADEON_IS_AGP;
152 if (rdev->family >= CHIP_R600) {
153 DRM_INFO("Forcing AGP to PCIE mode\n");
154 rdev->flags |= RADEON_IS_PCIE;
155 } else if (rdev->family >= CHIP_RV515 ||
156 rdev->family == CHIP_RV380 ||
157 rdev->family == CHIP_RV410 ||
158 rdev->family == CHIP_R423) {
159 DRM_INFO("Forcing AGP to PCIE mode\n");
160 rdev->flags |= RADEON_IS_PCIE;
c5b3b850
AD		 161 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
162 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
0a10c851
DV		 163 } else {
164 DRM_INFO("Forcing AGP to PCI mode\n");
165 rdev->flags |= RADEON_IS_PCI;
c5b3b850
AD		 166 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
167 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
0a10c851
DV		 168 }
169 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
170}
171
172/*
173 * ASIC
174 */
48e7a5f1
DV		 175static struct radeon_asic r100_asic = {
176 .init = &r100_init,
177 .fini = &r100_fini,
178 .suspend = &r100_suspend,
179 .resume = &r100_resume,
180 .vga_set_state = &r100_vga_set_state,
a2d07b74 181 .asic_reset = &r100_asic_reset,
54e88e06
AD		 182 .ioctl_wait_idle = NULL,
183 .gui_idle = &r100_gui_idle,
184 .mc_wait_for_idle = &r100_mc_wait_for_idle,
c5b3b850
AD		 185 .gart = {
186 .tlb_flush = &r100_pci_gart_tlb_flush,
187 .set_page = &r100_pci_gart_set_page,
188 },
4c87bc26
CK		 189 .ring = {
190 [RADEON_RING_TYPE_GFX_INDEX] = {
191 .ib_execute = &r100_ring_ib_execute,
192 .emit_fence = &r100_fence_ring_emit,
193 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 194 .cs_parse = &r100_cs_parse,
f712812e
AD		 195 .ring_start = &r100_ring_start,
196 .ring_test = &r100_ring_test,
197 .ib_test = &r100_ib_test,
312c4a8c 198 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 199 .get_rptr = &radeon_ring_generic_get_rptr,
200 .get_wptr = &radeon_ring_generic_get_wptr,
201 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 202 }
203 },
b35ea4ab
AD		 204 .irq = {
205 .set = &r100_irq_set,
206 .process = &r100_irq_process,
207 },
c79a49ca
AD		 208 .display = {
209 .bandwidth_update = &r100_bandwidth_update,
210 .get_vblank_counter = &r100_get_vblank_counter,
211 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 212 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 213 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 214 },
27cd7769
AD		 215 .copy = {
216 .blit = &r100_copy_blit,
217 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
218 .dma = NULL,
219 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
220 .copy = &r100_copy_blit,
221 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
222 },
9e6f3d02
AD		 223 .surface = {
224 .set_reg = r100_set_surface_reg,
225 .clear_reg = r100_clear_surface_reg,
226 },
901ea57d
AD		 227 .hpd = {
228 .init = &r100_hpd_init,
229 .fini = &r100_hpd_fini,
230 .sense = &r100_hpd_sense,
231 .set_polarity = &r100_hpd_set_polarity,
232 },
a02fa397
AD		 233 .pm = {
234 .misc = &r100_pm_misc,
235 .prepare = &r100_pm_prepare,
236 .finish = &r100_pm_finish,
237 .init_profile = &r100_pm_init_profile,
238 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 239 .get_engine_clock = &radeon_legacy_get_engine_clock,
240 .set_engine_clock = &radeon_legacy_set_engine_clock,
241 .get_memory_clock = &radeon_legacy_get_memory_clock,
242 .set_memory_clock = NULL,
243 .get_pcie_lanes = NULL,
244 .set_pcie_lanes = NULL,
245 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 246 },
0f9e006c
AD		 247 .pflip = {
248 .pre_page_flip = &r100_pre_page_flip,
249 .page_flip = &r100_page_flip,
250 .post_page_flip = &r100_post_page_flip,
251 },
48e7a5f1
DV		 252};
253
254static struct radeon_asic r200_asic = {
255 .init = &r100_init,
256 .fini = &r100_fini,
257 .suspend = &r100_suspend,
258 .resume = &r100_resume,
259 .vga_set_state = &r100_vga_set_state,
a2d07b74 260 .asic_reset = &r100_asic_reset,
54e88e06
AD		 261 .ioctl_wait_idle = NULL,
262 .gui_idle = &r100_gui_idle,
263 .mc_wait_for_idle = &r100_mc_wait_for_idle,
c5b3b850
AD		 264 .gart = {
265 .tlb_flush = &r100_pci_gart_tlb_flush,
266 .set_page = &r100_pci_gart_set_page,
267 },
4c87bc26
CK		 268 .ring = {
269 [RADEON_RING_TYPE_GFX_INDEX] = {
270 .ib_execute = &r100_ring_ib_execute,
271 .emit_fence = &r100_fence_ring_emit,
272 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 273 .cs_parse = &r100_cs_parse,
f712812e
AD		 274 .ring_start = &r100_ring_start,
275 .ring_test = &r100_ring_test,
276 .ib_test = &r100_ib_test,
312c4a8c 277 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 278 .get_rptr = &radeon_ring_generic_get_rptr,
279 .get_wptr = &radeon_ring_generic_get_wptr,
280 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 281 }
282 },
b35ea4ab
AD		 283 .irq = {
284 .set = &r100_irq_set,
285 .process = &r100_irq_process,
286 },
c79a49ca
AD		 287 .display = {
288 .bandwidth_update = &r100_bandwidth_update,
289 .get_vblank_counter = &r100_get_vblank_counter,
290 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 291 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 292 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 293 },
27cd7769
AD		 294 .copy = {
295 .blit = &r100_copy_blit,
296 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
297 .dma = &r200_copy_dma,
298 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
299 .copy = &r100_copy_blit,
300 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
301 },
9e6f3d02
AD		 302 .surface = {
303 .set_reg = r100_set_surface_reg,
304 .clear_reg = r100_clear_surface_reg,
305 },
901ea57d
AD		 306 .hpd = {
307 .init = &r100_hpd_init,
308 .fini = &r100_hpd_fini,
309 .sense = &r100_hpd_sense,
310 .set_polarity = &r100_hpd_set_polarity,
311 },
a02fa397
AD		 312 .pm = {
313 .misc = &r100_pm_misc,
314 .prepare = &r100_pm_prepare,
315 .finish = &r100_pm_finish,
316 .init_profile = &r100_pm_init_profile,
317 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 318 .get_engine_clock = &radeon_legacy_get_engine_clock,
319 .set_engine_clock = &radeon_legacy_set_engine_clock,
320 .get_memory_clock = &radeon_legacy_get_memory_clock,
321 .set_memory_clock = NULL,
322 .get_pcie_lanes = NULL,
323 .set_pcie_lanes = NULL,
324 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 325 },
0f9e006c
AD		 326 .pflip = {
327 .pre_page_flip = &r100_pre_page_flip,
328 .page_flip = &r100_page_flip,
329 .post_page_flip = &r100_post_page_flip,
330 },
48e7a5f1
DV		 331};
332
333static struct radeon_asic r300_asic = {
334 .init = &r300_init,
335 .fini = &r300_fini,
336 .suspend = &r300_suspend,
337 .resume = &r300_resume,
338 .vga_set_state = &r100_vga_set_state,
a2d07b74 339 .asic_reset = &r300_asic_reset,
54e88e06
AD		 340 .ioctl_wait_idle = NULL,
341 .gui_idle = &r100_gui_idle,
342 .mc_wait_for_idle = &r300_mc_wait_for_idle,
c5b3b850
AD		 343 .gart = {
344 .tlb_flush = &r100_pci_gart_tlb_flush,
345 .set_page = &r100_pci_gart_set_page,
346 },
4c87bc26
CK		 347 .ring = {
348 [RADEON_RING_TYPE_GFX_INDEX] = {
349 .ib_execute = &r100_ring_ib_execute,
350 .emit_fence = &r300_fence_ring_emit,
351 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 352 .cs_parse = &r300_cs_parse,
f712812e
AD		 353 .ring_start = &r300_ring_start,
354 .ring_test = &r100_ring_test,
355 .ib_test = &r100_ib_test,
8ba957b5 356 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 357 .get_rptr = &radeon_ring_generic_get_rptr,
358 .get_wptr = &radeon_ring_generic_get_wptr,
359 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 360 }
361 },
b35ea4ab
AD		 362 .irq = {
363 .set = &r100_irq_set,
364 .process = &r100_irq_process,
365 },
c79a49ca
AD		 366 .display = {
367 .bandwidth_update = &r100_bandwidth_update,
368 .get_vblank_counter = &r100_get_vblank_counter,
369 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 370 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 371 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 372 },
27cd7769
AD		 373 .copy = {
374 .blit = &r100_copy_blit,
375 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
376 .dma = &r200_copy_dma,
377 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
378 .copy = &r100_copy_blit,
379 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
380 },
9e6f3d02
AD		 381 .surface = {
382 .set_reg = r100_set_surface_reg,
383 .clear_reg = r100_clear_surface_reg,
384 },
901ea57d
AD		 385 .hpd = {
386 .init = &r100_hpd_init,
387 .fini = &r100_hpd_fini,
388 .sense = &r100_hpd_sense,
389 .set_polarity = &r100_hpd_set_polarity,
390 },
a02fa397
AD		 391 .pm = {
392 .misc = &r100_pm_misc,
393 .prepare = &r100_pm_prepare,
394 .finish = &r100_pm_finish,
395 .init_profile = &r100_pm_init_profile,
396 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 397 .get_engine_clock = &radeon_legacy_get_engine_clock,
398 .set_engine_clock = &radeon_legacy_set_engine_clock,
399 .get_memory_clock = &radeon_legacy_get_memory_clock,
400 .set_memory_clock = NULL,
401 .get_pcie_lanes = &rv370_get_pcie_lanes,
402 .set_pcie_lanes = &rv370_set_pcie_lanes,
403 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 404 },
0f9e006c
AD		 405 .pflip = {
406 .pre_page_flip = &r100_pre_page_flip,
407 .page_flip = &r100_page_flip,
408 .post_page_flip = &r100_post_page_flip,
409 },
48e7a5f1
DV		 410};
411
412static struct radeon_asic r300_asic_pcie = {
413 .init = &r300_init,
414 .fini = &r300_fini,
415 .suspend = &r300_suspend,
416 .resume = &r300_resume,
417 .vga_set_state = &r100_vga_set_state,
a2d07b74 418 .asic_reset = &r300_asic_reset,
54e88e06
AD		 419 .ioctl_wait_idle = NULL,
420 .gui_idle = &r100_gui_idle,
421 .mc_wait_for_idle = &r300_mc_wait_for_idle,
c5b3b850
AD		 422 .gart = {
423 .tlb_flush = &rv370_pcie_gart_tlb_flush,
424 .set_page = &rv370_pcie_gart_set_page,
425 },
4c87bc26
CK		 426 .ring = {
427 [RADEON_RING_TYPE_GFX_INDEX] = {
428 .ib_execute = &r100_ring_ib_execute,
429 .emit_fence = &r300_fence_ring_emit,
430 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 431 .cs_parse = &r300_cs_parse,
f712812e
AD		 432 .ring_start = &r300_ring_start,
433 .ring_test = &r100_ring_test,
434 .ib_test = &r100_ib_test,
8ba957b5 435 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 436 .get_rptr = &radeon_ring_generic_get_rptr,
437 .get_wptr = &radeon_ring_generic_get_wptr,
438 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 439 }
440 },
b35ea4ab
AD		 441 .irq = {
442 .set = &r100_irq_set,
443 .process = &r100_irq_process,
444 },
c79a49ca
AD		 445 .display = {
446 .bandwidth_update = &r100_bandwidth_update,
447 .get_vblank_counter = &r100_get_vblank_counter,
448 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 449 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 450 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 451 },
27cd7769
AD		 452 .copy = {
453 .blit = &r100_copy_blit,
454 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
455 .dma = &r200_copy_dma,
456 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
457 .copy = &r100_copy_blit,
458 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
459 },
9e6f3d02
AD		 460 .surface = {
461 .set_reg = r100_set_surface_reg,
462 .clear_reg = r100_clear_surface_reg,
463 },
901ea57d
AD		 464 .hpd = {
465 .init = &r100_hpd_init,
466 .fini = &r100_hpd_fini,
467 .sense = &r100_hpd_sense,
468 .set_polarity = &r100_hpd_set_polarity,
469 },
a02fa397
AD		 470 .pm = {
471 .misc = &r100_pm_misc,
472 .prepare = &r100_pm_prepare,
473 .finish = &r100_pm_finish,
474 .init_profile = &r100_pm_init_profile,
475 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 476 .get_engine_clock = &radeon_legacy_get_engine_clock,
477 .set_engine_clock = &radeon_legacy_set_engine_clock,
478 .get_memory_clock = &radeon_legacy_get_memory_clock,
479 .set_memory_clock = NULL,
480 .get_pcie_lanes = &rv370_get_pcie_lanes,
481 .set_pcie_lanes = &rv370_set_pcie_lanes,
482 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 483 },
0f9e006c
AD		 484 .pflip = {
485 .pre_page_flip = &r100_pre_page_flip,
486 .page_flip = &r100_page_flip,
487 .post_page_flip = &r100_post_page_flip,
488 },
48e7a5f1
DV		 489};
490
491static struct radeon_asic r420_asic = {
492 .init = &r420_init,
493 .fini = &r420_fini,
494 .suspend = &r420_suspend,
495 .resume = &r420_resume,
496 .vga_set_state = &r100_vga_set_state,
a2d07b74 497 .asic_reset = &r300_asic_reset,
54e88e06
AD		 498 .ioctl_wait_idle = NULL,
499 .gui_idle = &r100_gui_idle,
500 .mc_wait_for_idle = &r300_mc_wait_for_idle,
c5b3b850
AD		 501 .gart = {
502 .tlb_flush = &rv370_pcie_gart_tlb_flush,
503 .set_page = &rv370_pcie_gart_set_page,
504 },
4c87bc26
CK		 505 .ring = {
506 [RADEON_RING_TYPE_GFX_INDEX] = {
507 .ib_execute = &r100_ring_ib_execute,
508 .emit_fence = &r300_fence_ring_emit,
509 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 510 .cs_parse = &r300_cs_parse,
f712812e
AD		 511 .ring_start = &r300_ring_start,
512 .ring_test = &r100_ring_test,
513 .ib_test = &r100_ib_test,
8ba957b5 514 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 515 .get_rptr = &radeon_ring_generic_get_rptr,
516 .get_wptr = &radeon_ring_generic_get_wptr,
517 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 518 }
519 },
b35ea4ab
AD		 520 .irq = {
521 .set = &r100_irq_set,
522 .process = &r100_irq_process,
523 },
c79a49ca
AD		 524 .display = {
525 .bandwidth_update = &r100_bandwidth_update,
526 .get_vblank_counter = &r100_get_vblank_counter,
527 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 528 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 529 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 530 },
27cd7769
AD		 531 .copy = {
532 .blit = &r100_copy_blit,
533 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
534 .dma = &r200_copy_dma,
535 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
536 .copy = &r100_copy_blit,
537 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
538 },
9e6f3d02
AD		 539 .surface = {
540 .set_reg = r100_set_surface_reg,
541 .clear_reg = r100_clear_surface_reg,
542 },
901ea57d
AD		 543 .hpd = {
544 .init = &r100_hpd_init,
545 .fini = &r100_hpd_fini,
546 .sense = &r100_hpd_sense,
547 .set_polarity = &r100_hpd_set_polarity,
548 },
a02fa397
AD		 549 .pm = {
550 .misc = &r100_pm_misc,
551 .prepare = &r100_pm_prepare,
552 .finish = &r100_pm_finish,
553 .init_profile = &r420_pm_init_profile,
554 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 555 .get_engine_clock = &radeon_atom_get_engine_clock,
556 .set_engine_clock = &radeon_atom_set_engine_clock,
557 .get_memory_clock = &radeon_atom_get_memory_clock,
558 .set_memory_clock = &radeon_atom_set_memory_clock,
559 .get_pcie_lanes = &rv370_get_pcie_lanes,
560 .set_pcie_lanes = &rv370_set_pcie_lanes,
561 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 562 },
0f9e006c
AD		 563 .pflip = {
564 .pre_page_flip = &r100_pre_page_flip,
565 .page_flip = &r100_page_flip,
566 .post_page_flip = &r100_post_page_flip,
567 },
48e7a5f1
DV		 568};
569
570static struct radeon_asic rs400_asic = {
571 .init = &rs400_init,
572 .fini = &rs400_fini,
573 .suspend = &rs400_suspend,
574 .resume = &rs400_resume,
575 .vga_set_state = &r100_vga_set_state,
a2d07b74 576 .asic_reset = &r300_asic_reset,
54e88e06
AD		 577 .ioctl_wait_idle = NULL,
578 .gui_idle = &r100_gui_idle,
579 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
c5b3b850
AD		 580 .gart = {
581 .tlb_flush = &rs400_gart_tlb_flush,
582 .set_page = &rs400_gart_set_page,
583 },
4c87bc26
CK		 584 .ring = {
585 [RADEON_RING_TYPE_GFX_INDEX] = {
586 .ib_execute = &r100_ring_ib_execute,
587 .emit_fence = &r300_fence_ring_emit,
588 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 589 .cs_parse = &r300_cs_parse,
f712812e
AD		 590 .ring_start = &r300_ring_start,
591 .ring_test = &r100_ring_test,
592 .ib_test = &r100_ib_test,
8ba957b5 593 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 594 .get_rptr = &radeon_ring_generic_get_rptr,
595 .get_wptr = &radeon_ring_generic_get_wptr,
596 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 597 }
598 },
b35ea4ab
AD		 599 .irq = {
600 .set = &r100_irq_set,
601 .process = &r100_irq_process,
602 },
c79a49ca
AD		 603 .display = {
604 .bandwidth_update = &r100_bandwidth_update,
605 .get_vblank_counter = &r100_get_vblank_counter,
606 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 607 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 608 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 609 },
27cd7769
AD		 610 .copy = {
611 .blit = &r100_copy_blit,
612 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
613 .dma = &r200_copy_dma,
614 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
615 .copy = &r100_copy_blit,
616 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
617 },
9e6f3d02
AD		 618 .surface = {
619 .set_reg = r100_set_surface_reg,
620 .clear_reg = r100_clear_surface_reg,
621 },
901ea57d
AD		 622 .hpd = {
623 .init = &r100_hpd_init,
624 .fini = &r100_hpd_fini,
625 .sense = &r100_hpd_sense,
626 .set_polarity = &r100_hpd_set_polarity,
627 },
a02fa397
AD		 628 .pm = {
629 .misc = &r100_pm_misc,
630 .prepare = &r100_pm_prepare,
631 .finish = &r100_pm_finish,
632 .init_profile = &r100_pm_init_profile,
633 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 634 .get_engine_clock = &radeon_legacy_get_engine_clock,
635 .set_engine_clock = &radeon_legacy_set_engine_clock,
636 .get_memory_clock = &radeon_legacy_get_memory_clock,
637 .set_memory_clock = NULL,
638 .get_pcie_lanes = NULL,
639 .set_pcie_lanes = NULL,
640 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 641 },
0f9e006c
AD		 642 .pflip = {
643 .pre_page_flip = &r100_pre_page_flip,
644 .page_flip = &r100_page_flip,
645 .post_page_flip = &r100_post_page_flip,
646 },
48e7a5f1
DV		 647};
648
649static struct radeon_asic rs600_asic = {
650 .init = &rs600_init,
651 .fini = &rs600_fini,
652 .suspend = &rs600_suspend,
653 .resume = &rs600_resume,
654 .vga_set_state = &r100_vga_set_state,
90aca4d2 655 .asic_reset = &rs600_asic_reset,
54e88e06
AD		 656 .ioctl_wait_idle = NULL,
657 .gui_idle = &r100_gui_idle,
658 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
c5b3b850
AD		 659 .gart = {
660 .tlb_flush = &rs600_gart_tlb_flush,
661 .set_page = &rs600_gart_set_page,
662 },
4c87bc26
CK		 663 .ring = {
664 [RADEON_RING_TYPE_GFX_INDEX] = {
665 .ib_execute = &r100_ring_ib_execute,
666 .emit_fence = &r300_fence_ring_emit,
667 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 668 .cs_parse = &r300_cs_parse,
f712812e
AD		 669 .ring_start = &r300_ring_start,
670 .ring_test = &r100_ring_test,
671 .ib_test = &r100_ib_test,
8ba957b5 672 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 673 .get_rptr = &radeon_ring_generic_get_rptr,
674 .get_wptr = &radeon_ring_generic_get_wptr,
675 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 676 }
677 },
b35ea4ab
AD		 678 .irq = {
679 .set = &rs600_irq_set,
680 .process = &rs600_irq_process,
681 },
c79a49ca
AD		 682 .display = {
683 .bandwidth_update = &rs600_bandwidth_update,
684 .get_vblank_counter = &rs600_get_vblank_counter,
685 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 686 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 687 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 688 .hdmi_enable = &r600_hdmi_enable,
689 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 690 },
27cd7769
AD		 691 .copy = {
692 .blit = &r100_copy_blit,
693 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
694 .dma = &r200_copy_dma,
695 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
696 .copy = &r100_copy_blit,
697 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
698 },
9e6f3d02
AD		 699 .surface = {
700 .set_reg = r100_set_surface_reg,
701 .clear_reg = r100_clear_surface_reg,
702 },
901ea57d
AD		 703 .hpd = {
704 .init = &rs600_hpd_init,
705 .fini = &rs600_hpd_fini,
706 .sense = &rs600_hpd_sense,
707 .set_polarity = &rs600_hpd_set_polarity,
708 },
a02fa397
AD		 709 .pm = {
710 .misc = &rs600_pm_misc,
711 .prepare = &rs600_pm_prepare,
712 .finish = &rs600_pm_finish,
713 .init_profile = &r420_pm_init_profile,
714 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 715 .get_engine_clock = &radeon_atom_get_engine_clock,
716 .set_engine_clock = &radeon_atom_set_engine_clock,
717 .get_memory_clock = &radeon_atom_get_memory_clock,
718 .set_memory_clock = &radeon_atom_set_memory_clock,
719 .get_pcie_lanes = NULL,
720 .set_pcie_lanes = NULL,
721 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 722 },
0f9e006c
AD		 723 .pflip = {
724 .pre_page_flip = &rs600_pre_page_flip,
725 .page_flip = &rs600_page_flip,
726 .post_page_flip = &rs600_post_page_flip,
727 },
48e7a5f1
DV		 728};
729
730static struct radeon_asic rs690_asic = {
731 .init = &rs690_init,
732 .fini = &rs690_fini,
733 .suspend = &rs690_suspend,
734 .resume = &rs690_resume,
735 .vga_set_state = &r100_vga_set_state,
90aca4d2 736 .asic_reset = &rs600_asic_reset,
54e88e06
AD		 737 .ioctl_wait_idle = NULL,
738 .gui_idle = &r100_gui_idle,
739 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
c5b3b850
AD		 740 .gart = {
741 .tlb_flush = &rs400_gart_tlb_flush,
742 .set_page = &rs400_gart_set_page,
743 },
4c87bc26
CK		 744 .ring = {
745 [RADEON_RING_TYPE_GFX_INDEX] = {
746 .ib_execute = &r100_ring_ib_execute,
747 .emit_fence = &r300_fence_ring_emit,
748 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 749 .cs_parse = &r300_cs_parse,
f712812e
AD		 750 .ring_start = &r300_ring_start,
751 .ring_test = &r100_ring_test,
752 .ib_test = &r100_ib_test,
8ba957b5 753 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 754 .get_rptr = &radeon_ring_generic_get_rptr,
755 .get_wptr = &radeon_ring_generic_get_wptr,
756 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 757 }
758 },
b35ea4ab
AD		 759 .irq = {
760 .set = &rs600_irq_set,
761 .process = &rs600_irq_process,
762 },
c79a49ca
AD		 763 .display = {
764 .get_vblank_counter = &rs600_get_vblank_counter,
765 .bandwidth_update = &rs690_bandwidth_update,
766 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 767 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 768 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 769 .hdmi_enable = &r600_hdmi_enable,
770 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 771 },
27cd7769
AD		 772 .copy = {
773 .blit = &r100_copy_blit,
774 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
775 .dma = &r200_copy_dma,
776 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
777 .copy = &r200_copy_dma,
778 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
779 },
9e6f3d02
AD		 780 .surface = {
781 .set_reg = r100_set_surface_reg,
782 .clear_reg = r100_clear_surface_reg,
783 },
901ea57d
AD		 784 .hpd = {
785 .init = &rs600_hpd_init,
786 .fini = &rs600_hpd_fini,
787 .sense = &rs600_hpd_sense,
788 .set_polarity = &rs600_hpd_set_polarity,
789 },
a02fa397
AD		 790 .pm = {
791 .misc = &rs600_pm_misc,
792 .prepare = &rs600_pm_prepare,
793 .finish = &rs600_pm_finish,
794 .init_profile = &r420_pm_init_profile,
795 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 796 .get_engine_clock = &radeon_atom_get_engine_clock,
797 .set_engine_clock = &radeon_atom_set_engine_clock,
798 .get_memory_clock = &radeon_atom_get_memory_clock,
799 .set_memory_clock = &radeon_atom_set_memory_clock,
800 .get_pcie_lanes = NULL,
801 .set_pcie_lanes = NULL,
802 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 803 },
0f9e006c
AD		 804 .pflip = {
805 .pre_page_flip = &rs600_pre_page_flip,
806 .page_flip = &rs600_page_flip,
807 .post_page_flip = &rs600_post_page_flip,
808 },
48e7a5f1
DV		 809};
810
811static struct radeon_asic rv515_asic = {
812 .init = &rv515_init,
813 .fini = &rv515_fini,
814 .suspend = &rv515_suspend,
815 .resume = &rv515_resume,
816 .vga_set_state = &r100_vga_set_state,
90aca4d2 817 .asic_reset = &rs600_asic_reset,
54e88e06
AD		 818 .ioctl_wait_idle = NULL,
819 .gui_idle = &r100_gui_idle,
820 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
c5b3b850
AD		 821 .gart = {
822 .tlb_flush = &rv370_pcie_gart_tlb_flush,
823 .set_page = &rv370_pcie_gart_set_page,
824 },
4c87bc26
CK		 825 .ring = {
826 [RADEON_RING_TYPE_GFX_INDEX] = {
827 .ib_execute = &r100_ring_ib_execute,
828 .emit_fence = &r300_fence_ring_emit,
829 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 830 .cs_parse = &r300_cs_parse,
f712812e
AD		 831 .ring_start = &rv515_ring_start,
832 .ring_test = &r100_ring_test,
833 .ib_test = &r100_ib_test,
8ba957b5 834 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 835 .get_rptr = &radeon_ring_generic_get_rptr,
836 .get_wptr = &radeon_ring_generic_get_wptr,
837 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 838 }
839 },
b35ea4ab
AD		 840 .irq = {
841 .set = &rs600_irq_set,
842 .process = &rs600_irq_process,
843 },
c79a49ca
AD		 844 .display = {
845 .get_vblank_counter = &rs600_get_vblank_counter,
846 .bandwidth_update = &rv515_bandwidth_update,
847 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 848 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 849 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 850 },
27cd7769
AD		 851 .copy = {
852 .blit = &r100_copy_blit,
853 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
854 .dma = &r200_copy_dma,
855 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
856 .copy = &r100_copy_blit,
857 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
858 },
9e6f3d02
AD		 859 .surface = {
860 .set_reg = r100_set_surface_reg,
861 .clear_reg = r100_clear_surface_reg,
862 },
901ea57d
AD		 863 .hpd = {
864 .init = &rs600_hpd_init,
865 .fini = &rs600_hpd_fini,
866 .sense = &rs600_hpd_sense,
867 .set_polarity = &rs600_hpd_set_polarity,
868 },
a02fa397
AD		 869 .pm = {
870 .misc = &rs600_pm_misc,
871 .prepare = &rs600_pm_prepare,
872 .finish = &rs600_pm_finish,
873 .init_profile = &r420_pm_init_profile,
874 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 875 .get_engine_clock = &radeon_atom_get_engine_clock,
876 .set_engine_clock = &radeon_atom_set_engine_clock,
877 .get_memory_clock = &radeon_atom_get_memory_clock,
878 .set_memory_clock = &radeon_atom_set_memory_clock,
879 .get_pcie_lanes = &rv370_get_pcie_lanes,
880 .set_pcie_lanes = &rv370_set_pcie_lanes,
881 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 882 },
0f9e006c
AD		 883 .pflip = {
884 .pre_page_flip = &rs600_pre_page_flip,
885 .page_flip = &rs600_page_flip,
886 .post_page_flip = &rs600_post_page_flip,
887 },
48e7a5f1
DV		 888};
889
890static struct radeon_asic r520_asic = {
891 .init = &r520_init,
892 .fini = &rv515_fini,
893 .suspend = &rv515_suspend,
894 .resume = &r520_resume,
895 .vga_set_state = &r100_vga_set_state,
90aca4d2 896 .asic_reset = &rs600_asic_reset,
54e88e06
AD		 897 .ioctl_wait_idle = NULL,
898 .gui_idle = &r100_gui_idle,
899 .mc_wait_for_idle = &r520_mc_wait_for_idle,
c5b3b850
AD		 900 .gart = {
901 .tlb_flush = &rv370_pcie_gart_tlb_flush,
902 .set_page = &rv370_pcie_gart_set_page,
903 },
4c87bc26
CK		 904 .ring = {
905 [RADEON_RING_TYPE_GFX_INDEX] = {
906 .ib_execute = &r100_ring_ib_execute,
907 .emit_fence = &r300_fence_ring_emit,
908 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 909 .cs_parse = &r300_cs_parse,
f712812e
AD		 910 .ring_start = &rv515_ring_start,
911 .ring_test = &r100_ring_test,
912 .ib_test = &r100_ib_test,
8ba957b5 913 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 914 .get_rptr = &radeon_ring_generic_get_rptr,
915 .get_wptr = &radeon_ring_generic_get_wptr,
916 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 917 }
918 },
b35ea4ab
AD		 919 .irq = {
920 .set = &rs600_irq_set,
921 .process = &rs600_irq_process,
922 },
c79a49ca
AD		 923 .display = {
924 .bandwidth_update = &rv515_bandwidth_update,
925 .get_vblank_counter = &rs600_get_vblank_counter,
926 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 927 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 928 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 929 },
27cd7769
AD		 930 .copy = {
931 .blit = &r100_copy_blit,
932 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
933 .dma = &r200_copy_dma,
934 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
935 .copy = &r100_copy_blit,
936 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
937 },
9e6f3d02
AD		 938 .surface = {
939 .set_reg = r100_set_surface_reg,
940 .clear_reg = r100_clear_surface_reg,
941 },
901ea57d
AD		 942 .hpd = {
943 .init = &rs600_hpd_init,
944 .fini = &rs600_hpd_fini,
945 .sense = &rs600_hpd_sense,
946 .set_polarity = &rs600_hpd_set_polarity,
947 },
a02fa397
AD		 948 .pm = {
949 .misc = &rs600_pm_misc,
950 .prepare = &rs600_pm_prepare,
951 .finish = &rs600_pm_finish,
952 .init_profile = &r420_pm_init_profile,
953 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 954 .get_engine_clock = &radeon_atom_get_engine_clock,
955 .set_engine_clock = &radeon_atom_set_engine_clock,
956 .get_memory_clock = &radeon_atom_get_memory_clock,
957 .set_memory_clock = &radeon_atom_set_memory_clock,
958 .get_pcie_lanes = &rv370_get_pcie_lanes,
959 .set_pcie_lanes = &rv370_set_pcie_lanes,
960 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 961 },
0f9e006c
AD		 962 .pflip = {
963 .pre_page_flip = &rs600_pre_page_flip,
964 .page_flip = &rs600_page_flip,
965 .post_page_flip = &rs600_post_page_flip,
966 },
48e7a5f1
DV		 967};
968
969static struct radeon_asic r600_asic = {
970 .init = &r600_init,
971 .fini = &r600_fini,
972 .suspend = &r600_suspend,
973 .resume = &r600_resume,
48e7a5f1 974 .vga_set_state = &r600_vga_set_state,
a2d07b74 975 .asic_reset = &r600_asic_reset,
54e88e06
AD		 976 .ioctl_wait_idle = r600_ioctl_wait_idle,
977 .gui_idle = &r600_gui_idle,
978 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 979 .get_xclk = &r600_get_xclk,
d0418894 980 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 981 .gart = {
982 .tlb_flush = &r600_pcie_gart_tlb_flush,
983 .set_page = &rs600_gart_set_page,
984 },
4c87bc26
CK		 985 .ring = {
986 [RADEON_RING_TYPE_GFX_INDEX] = {
987 .ib_execute = &r600_ring_ib_execute,
988 .emit_fence = &r600_fence_ring_emit,
989 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 990 .cs_parse = &r600_cs_parse,
f712812e
AD		 991 .ring_test = &r600_ring_test,
992 .ib_test = &r600_ib_test,
123bc183 993 .is_lockup = &r600_gfx_is_lockup,
f93bdefe
AD		 994 .get_rptr = &radeon_ring_generic_get_rptr,
995 .get_wptr = &radeon_ring_generic_get_wptr,
996 .set_wptr = &radeon_ring_generic_set_wptr,
4d75658b
AD		 997 },
998 [R600_RING_TYPE_DMA_INDEX] = {
999 .ib_execute = &r600_dma_ring_ib_execute,
1000 .emit_fence = &r600_dma_fence_ring_emit,
1001 .emit_semaphore = &r600_dma_semaphore_ring_emit,
cf4ccd01 1002 .cs_parse = &r600_dma_cs_parse,
4d75658b
AD		 1003 .ring_test = &r600_dma_ring_test,
1004 .ib_test = &r600_dma_ib_test,
1005 .is_lockup = &r600_dma_is_lockup,
f93bdefe
AD		 1006 .get_rptr = &radeon_ring_generic_get_rptr,
1007 .get_wptr = &radeon_ring_generic_get_wptr,
1008 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 1009 }
1010 },
b35ea4ab
AD		 1011 .irq = {
1012 .set = &r600_irq_set,
1013 .process = &r600_irq_process,
1014 },
c79a49ca
AD		 1015 .display = {
1016 .bandwidth_update = &rv515_bandwidth_update,
1017 .get_vblank_counter = &rs600_get_vblank_counter,
1018 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 1019 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1020 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1021 .hdmi_enable = &r600_hdmi_enable,
1022 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 1023 },
27cd7769
AD		 1024 .copy = {
1025 .blit = &r600_copy_blit,
1026 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
4d75658b
AD		 1027 .dma = &r600_copy_dma,
1028 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1029 .copy = &r600_copy_dma,
1030 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1031 },
9e6f3d02
AD		 1032 .surface = {
1033 .set_reg = r600_set_surface_reg,
1034 .clear_reg = r600_clear_surface_reg,
1035 },
901ea57d
AD		 1036 .hpd = {
1037 .init = &r600_hpd_init,
1038 .fini = &r600_hpd_fini,
1039 .sense = &r600_hpd_sense,
1040 .set_polarity = &r600_hpd_set_polarity,
1041 },
a02fa397
AD		 1042 .pm = {
1043 .misc = &r600_pm_misc,
1044 .prepare = &rs600_pm_prepare,
1045 .finish = &rs600_pm_finish,
1046 .init_profile = &r600_pm_init_profile,
1047 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1048 .get_engine_clock = &radeon_atom_get_engine_clock,
1049 .set_engine_clock = &radeon_atom_set_engine_clock,
1050 .get_memory_clock = &radeon_atom_get_memory_clock,
1051 .set_memory_clock = &radeon_atom_set_memory_clock,
1052 .get_pcie_lanes = &r600_get_pcie_lanes,
1053 .set_pcie_lanes = &r600_set_pcie_lanes,
1054 .set_clock_gating = NULL,
6bd1c385 1055 .get_temperature = &rv6xx_get_temp,
a02fa397 1056 },
0f9e006c
AD		 1057 .pflip = {
1058 .pre_page_flip = &rs600_pre_page_flip,
1059 .page_flip = &rs600_page_flip,
1060 .post_page_flip = &rs600_post_page_flip,
1061 },
48e7a5f1
DV		 1062};
1063
ca361b65
AD		 1064static struct radeon_asic rv6xx_asic = {
1065 .init = &r600_init,
1066 .fini = &r600_fini,
1067 .suspend = &r600_suspend,
1068 .resume = &r600_resume,
1069 .vga_set_state = &r600_vga_set_state,
1070 .asic_reset = &r600_asic_reset,
1071 .ioctl_wait_idle = r600_ioctl_wait_idle,
1072 .gui_idle = &r600_gui_idle,
1073 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1074 .get_xclk = &r600_get_xclk,
1075 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1076 .gart = {
1077 .tlb_flush = &r600_pcie_gart_tlb_flush,
1078 .set_page = &rs600_gart_set_page,
1079 },
1080 .ring = {
1081 [RADEON_RING_TYPE_GFX_INDEX] = {
1082 .ib_execute = &r600_ring_ib_execute,
1083 .emit_fence = &r600_fence_ring_emit,
1084 .emit_semaphore = &r600_semaphore_ring_emit,
1085 .cs_parse = &r600_cs_parse,
1086 .ring_test = &r600_ring_test,
1087 .ib_test = &r600_ib_test,
1088 .is_lockup = &r600_gfx_is_lockup,
1089 .get_rptr = &radeon_ring_generic_get_rptr,
1090 .get_wptr = &radeon_ring_generic_get_wptr,
1091 .set_wptr = &radeon_ring_generic_set_wptr,
1092 },
1093 [R600_RING_TYPE_DMA_INDEX] = {
1094 .ib_execute = &r600_dma_ring_ib_execute,
1095 .emit_fence = &r600_dma_fence_ring_emit,
1096 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1097 .cs_parse = &r600_dma_cs_parse,
1098 .ring_test = &r600_dma_ring_test,
1099 .ib_test = &r600_dma_ib_test,
1100 .is_lockup = &r600_dma_is_lockup,
1101 .get_rptr = &radeon_ring_generic_get_rptr,
1102 .get_wptr = &radeon_ring_generic_get_wptr,
1103 .set_wptr = &radeon_ring_generic_set_wptr,
1104 }
1105 },
1106 .irq = {
1107 .set = &r600_irq_set,
1108 .process = &r600_irq_process,
1109 },
1110 .display = {
1111 .bandwidth_update = &rv515_bandwidth_update,
1112 .get_vblank_counter = &rs600_get_vblank_counter,
1113 .wait_for_vblank = &avivo_wait_for_vblank,
1114 .set_backlight_level = &atombios_set_backlight_level,
1115 .get_backlight_level = &atombios_get_backlight_level,
1116 },
1117 .copy = {
1118 .blit = &r600_copy_blit,
1119 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1120 .dma = &r600_copy_dma,
1121 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1122 .copy = &r600_copy_dma,
1123 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1124 },
1125 .surface = {
1126 .set_reg = r600_set_surface_reg,
1127 .clear_reg = r600_clear_surface_reg,
1128 },
1129 .hpd = {
1130 .init = &r600_hpd_init,
1131 .fini = &r600_hpd_fini,
1132 .sense = &r600_hpd_sense,
1133 .set_polarity = &r600_hpd_set_polarity,
1134 },
1135 .pm = {
1136 .misc = &r600_pm_misc,
1137 .prepare = &rs600_pm_prepare,
1138 .finish = &rs600_pm_finish,
1139 .init_profile = &r600_pm_init_profile,
1140 .get_dynpm_state = &r600_pm_get_dynpm_state,
1141 .get_engine_clock = &radeon_atom_get_engine_clock,
1142 .set_engine_clock = &radeon_atom_set_engine_clock,
1143 .get_memory_clock = &radeon_atom_get_memory_clock,
1144 .set_memory_clock = &radeon_atom_set_memory_clock,
1145 .get_pcie_lanes = &r600_get_pcie_lanes,
1146 .set_pcie_lanes = &r600_set_pcie_lanes,
1147 .set_clock_gating = NULL,
1148 .get_temperature = &rv6xx_get_temp,
1149 },
4a6369e9
AD		 1150 .dpm = {
1151 .init = &rv6xx_dpm_init,
1152 .setup_asic = &rv6xx_setup_asic,
1153 .enable = &rv6xx_dpm_enable,
1154 .disable = &rv6xx_dpm_disable,
98243917 1155 .pre_set_power_state = &r600_dpm_pre_set_power_state,
4a6369e9 1156 .set_power_state = &rv6xx_dpm_set_power_state,
98243917 1157 .post_set_power_state = &r600_dpm_post_set_power_state,
4a6369e9
AD		 1158 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1159 .fini = &rv6xx_dpm_fini,
1160 .get_sclk = &rv6xx_dpm_get_sclk,
1161 .get_mclk = &rv6xx_dpm_get_mclk,
1162 .print_power_state = &rv6xx_dpm_print_power_state,
242916a5 1163 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
4a6369e9 1164 },
ca361b65
AD		 1165 .pflip = {
1166 .pre_page_flip = &rs600_pre_page_flip,
1167 .page_flip = &rs600_page_flip,
1168 .post_page_flip = &rs600_post_page_flip,
1169 },
1170};
1171
f47299c5
AD		 1172static struct radeon_asic rs780_asic = {
1173 .init = &r600_init,
1174 .fini = &r600_fini,
1175 .suspend = &r600_suspend,
1176 .resume = &r600_resume,
f47299c5 1177 .vga_set_state = &r600_vga_set_state,
a2d07b74 1178 .asic_reset = &r600_asic_reset,
54e88e06
AD		 1179 .ioctl_wait_idle = r600_ioctl_wait_idle,
1180 .gui_idle = &r600_gui_idle,
1181 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 1182 .get_xclk = &r600_get_xclk,
d0418894 1183 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1184 .gart = {
1185 .tlb_flush = &r600_pcie_gart_tlb_flush,
1186 .set_page = &rs600_gart_set_page,
1187 },
4c87bc26
CK		 1188 .ring = {
1189 [RADEON_RING_TYPE_GFX_INDEX] = {
1190 .ib_execute = &r600_ring_ib_execute,
1191 .emit_fence = &r600_fence_ring_emit,
1192 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1193 .cs_parse = &r600_cs_parse,
f712812e
AD		 1194 .ring_test = &r600_ring_test,
1195 .ib_test = &r600_ib_test,
123bc183 1196 .is_lockup = &r600_gfx_is_lockup,
f93bdefe
AD		 1197 .get_rptr = &radeon_ring_generic_get_rptr,
1198 .get_wptr = &radeon_ring_generic_get_wptr,
1199 .set_wptr = &radeon_ring_generic_set_wptr,
4d75658b
AD		 1200 },
1201 [R600_RING_TYPE_DMA_INDEX] = {
1202 .ib_execute = &r600_dma_ring_ib_execute,
1203 .emit_fence = &r600_dma_fence_ring_emit,
1204 .emit_semaphore = &r600_dma_semaphore_ring_emit,
cf4ccd01 1205 .cs_parse = &r600_dma_cs_parse,
4d75658b
AD		 1206 .ring_test = &r600_dma_ring_test,
1207 .ib_test = &r600_dma_ib_test,
1208 .is_lockup = &r600_dma_is_lockup,
f93bdefe
AD		 1209 .get_rptr = &radeon_ring_generic_get_rptr,
1210 .get_wptr = &radeon_ring_generic_get_wptr,
1211 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 1212 }
1213 },
b35ea4ab
AD		 1214 .irq = {
1215 .set = &r600_irq_set,
1216 .process = &r600_irq_process,
1217 },
c79a49ca
AD		 1218 .display = {
1219 .bandwidth_update = &rs690_bandwidth_update,
1220 .get_vblank_counter = &rs600_get_vblank_counter,
1221 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 1222 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1223 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1224 .hdmi_enable = &r600_hdmi_enable,
1225 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 1226 },
27cd7769
AD		 1227 .copy = {
1228 .blit = &r600_copy_blit,
1229 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
4d75658b
AD		 1230 .dma = &r600_copy_dma,
1231 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1232 .copy = &r600_copy_dma,
1233 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1234 },
9e6f3d02
AD		 1235 .surface = {
1236 .set_reg = r600_set_surface_reg,
1237 .clear_reg = r600_clear_surface_reg,
1238 },
901ea57d
AD		 1239 .hpd = {
1240 .init = &r600_hpd_init,
1241 .fini = &r600_hpd_fini,
1242 .sense = &r600_hpd_sense,
1243 .set_polarity = &r600_hpd_set_polarity,
1244 },
a02fa397
AD		 1245 .pm = {
1246 .misc = &r600_pm_misc,
1247 .prepare = &rs600_pm_prepare,
1248 .finish = &rs600_pm_finish,
1249 .init_profile = &rs780_pm_init_profile,
1250 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1251 .get_engine_clock = &radeon_atom_get_engine_clock,
1252 .set_engine_clock = &radeon_atom_set_engine_clock,
1253 .get_memory_clock = NULL,
1254 .set_memory_clock = NULL,
1255 .get_pcie_lanes = NULL,
1256 .set_pcie_lanes = NULL,
1257 .set_clock_gating = NULL,
6bd1c385 1258 .get_temperature = &rv6xx_get_temp,
a02fa397 1259 },
9d67006e
AD		 1260 .dpm = {
1261 .init = &rs780_dpm_init,
1262 .setup_asic = &rs780_dpm_setup_asic,
1263 .enable = &rs780_dpm_enable,
1264 .disable = &rs780_dpm_disable,
98243917 1265 .pre_set_power_state = &r600_dpm_pre_set_power_state,
9d67006e 1266 .set_power_state = &rs780_dpm_set_power_state,
98243917 1267 .post_set_power_state = &r600_dpm_post_set_power_state,
9d67006e
AD		 1268 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1269 .fini = &rs780_dpm_fini,
1270 .get_sclk = &rs780_dpm_get_sclk,
1271 .get_mclk = &rs780_dpm_get_mclk,
1272 .print_power_state = &rs780_dpm_print_power_state,
1273 },
0f9e006c
AD		 1274 .pflip = {
1275 .pre_page_flip = &rs600_pre_page_flip,
1276 .page_flip = &rs600_page_flip,
1277 .post_page_flip = &rs600_post_page_flip,
1278 },
f47299c5
AD		 1279};
1280
48e7a5f1
DV		 1281static struct radeon_asic rv770_asic = {
1282 .init = &rv770_init,
1283 .fini = &rv770_fini,
1284 .suspend = &rv770_suspend,
1285 .resume = &rv770_resume,
a2d07b74 1286 .asic_reset = &r600_asic_reset,
48e7a5f1 1287 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1288 .ioctl_wait_idle = r600_ioctl_wait_idle,
1289 .gui_idle = &r600_gui_idle,
1290 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 1291 .get_xclk = &rv770_get_xclk,
d0418894 1292 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1293 .gart = {
1294 .tlb_flush = &r600_pcie_gart_tlb_flush,
1295 .set_page = &rs600_gart_set_page,
1296 },
4c87bc26
CK		 1297 .ring = {
1298 [RADEON_RING_TYPE_GFX_INDEX] = {
1299 .ib_execute = &r600_ring_ib_execute,
1300 .emit_fence = &r600_fence_ring_emit,
1301 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1302 .cs_parse = &r600_cs_parse,
f712812e
AD		 1303 .ring_test = &r600_ring_test,
1304 .ib_test = &r600_ib_test,
123bc183 1305 .is_lockup = &r600_gfx_is_lockup,
f93bdefe
AD		 1306 .get_rptr = &radeon_ring_generic_get_rptr,
1307 .get_wptr = &radeon_ring_generic_get_wptr,
1308 .set_wptr = &radeon_ring_generic_set_wptr,
4d75658b
AD		 1309 },
1310 [R600_RING_TYPE_DMA_INDEX] = {
1311 .ib_execute = &r600_dma_ring_ib_execute,
1312 .emit_fence = &r600_dma_fence_ring_emit,
1313 .emit_semaphore = &r600_dma_semaphore_ring_emit,
cf4ccd01 1314 .cs_parse = &r600_dma_cs_parse,
4d75658b
AD		 1315 .ring_test = &r600_dma_ring_test,
1316 .ib_test = &r600_dma_ib_test,
1317 .is_lockup = &r600_dma_is_lockup,
f93bdefe
AD		 1318 .get_rptr = &radeon_ring_generic_get_rptr,
1319 .get_wptr = &radeon_ring_generic_get_wptr,
1320 .set_wptr = &radeon_ring_generic_set_wptr,
f2ba57b5
CK		 1321 },
1322 [R600_RING_TYPE_UVD_INDEX] = {
1323 .ib_execute = &r600_uvd_ib_execute,
1324 .emit_fence = &r600_uvd_fence_emit,
1325 .emit_semaphore = &r600_uvd_semaphore_emit,
1326 .cs_parse = &radeon_uvd_cs_parse,
1327 .ring_test = &r600_uvd_ring_test,
1328 .ib_test = &r600_uvd_ib_test,
1329 .is_lockup = &radeon_ring_test_lockup,
f93bdefe
AD		 1330 .get_rptr = &radeon_ring_generic_get_rptr,
1331 .get_wptr = &radeon_ring_generic_get_wptr,
1332 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 1333 }
1334 },
b35ea4ab
AD		 1335 .irq = {
1336 .set = &r600_irq_set,
1337 .process = &r600_irq_process,
1338 },
c79a49ca
AD		 1339 .display = {
1340 .bandwidth_update = &rv515_bandwidth_update,
1341 .get_vblank_counter = &rs600_get_vblank_counter,
1342 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 1343 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1344 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1345 .hdmi_enable = &r600_hdmi_enable,
1346 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 1347 },
27cd7769
AD		 1348 .copy = {
1349 .blit = &r600_copy_blit,
1350 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
43fb7787 1351 .dma = &rv770_copy_dma,
4d75658b 1352 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
43fb7787 1353 .copy = &rv770_copy_dma,
2d6cc729 1354 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1355 },
9e6f3d02
AD		 1356 .surface = {
1357 .set_reg = r600_set_surface_reg,
1358 .clear_reg = r600_clear_surface_reg,
1359 },
901ea57d
AD		 1360 .hpd = {
1361 .init = &r600_hpd_init,
1362 .fini = &r600_hpd_fini,
1363 .sense = &r600_hpd_sense,
1364 .set_polarity = &r600_hpd_set_polarity,
1365 },
a02fa397
AD		 1366 .pm = {
1367 .misc = &rv770_pm_misc,
1368 .prepare = &rs600_pm_prepare,
1369 .finish = &rs600_pm_finish,
1370 .init_profile = &r600_pm_init_profile,
1371 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1372 .get_engine_clock = &radeon_atom_get_engine_clock,
1373 .set_engine_clock = &radeon_atom_set_engine_clock,
1374 .get_memory_clock = &radeon_atom_get_memory_clock,
1375 .set_memory_clock = &radeon_atom_set_memory_clock,
1376 .get_pcie_lanes = &r600_get_pcie_lanes,
1377 .set_pcie_lanes = &r600_set_pcie_lanes,
1378 .set_clock_gating = &radeon_atom_set_clock_gating,
ef0e6e65 1379 .set_uvd_clocks = &rv770_set_uvd_clocks,
6bd1c385 1380 .get_temperature = &rv770_get_temp,
a02fa397 1381 },
66229b20
AD		 1382 .dpm = {
1383 .init = &rv770_dpm_init,
1384 .setup_asic = &rv770_dpm_setup_asic,
1385 .enable = &rv770_dpm_enable,
1386 .disable = &rv770_dpm_disable,
98243917 1387 .pre_set_power_state = &r600_dpm_pre_set_power_state,
66229b20 1388 .set_power_state = &rv770_dpm_set_power_state,
98243917 1389 .post_set_power_state = &r600_dpm_post_set_power_state,
66229b20
AD		 1390 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1391 .fini = &rv770_dpm_fini,
1392 .get_sclk = &rv770_dpm_get_sclk,
1393 .get_mclk = &rv770_dpm_get_mclk,
1394 .print_power_state = &rv770_dpm_print_power_state,
1395 },
0f9e006c
AD		 1396 .pflip = {
1397 .pre_page_flip = &rs600_pre_page_flip,
1398 .page_flip = &rv770_page_flip,
1399 .post_page_flip = &rs600_post_page_flip,
1400 },
48e7a5f1
DV		 1401};
1402
1403static struct radeon_asic evergreen_asic = {
1404 .init = &evergreen_init,
1405 .fini = &evergreen_fini,
1406 .suspend = &evergreen_suspend,
1407 .resume = &evergreen_resume,
a2d07b74 1408 .asic_reset = &evergreen_asic_reset,
48e7a5f1 1409 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1410 .ioctl_wait_idle = r600_ioctl_wait_idle,
1411 .gui_idle = &r600_gui_idle,
1412 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1413 .get_xclk = &rv770_get_xclk,
d0418894 1414 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1415 .gart = {
1416 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1417 .set_page = &rs600_gart_set_page,
1418 },
4c87bc26
CK		 1419 .ring = {
1420 [RADEON_RING_TYPE_GFX_INDEX] = {
1421 .ib_execute = &evergreen_ring_ib_execute,
1422 .emit_fence = &r600_fence_ring_emit,
1423 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1424 .cs_parse = &evergreen_cs_parse,
f712812e
AD		 1425 .ring_test = &r600_ring_test,
1426 .ib_test = &r600_ib_test,
123bc183 1427 .is_lockup = &evergreen_gfx_is_lockup,
f93bdefe
AD		 1428 .get_rptr = &radeon_ring_generic_get_rptr,
1429 .get_wptr = &radeon_ring_generic_get_wptr,
1430 .set_wptr = &radeon_ring_generic_set_wptr,
233d1ad5
AD		 1431 },
1432 [R600_RING_TYPE_DMA_INDEX] = {
1433 .ib_execute = &evergreen_dma_ring_ib_execute,
1434 .emit_fence = &evergreen_dma_fence_ring_emit,
1435 .emit_semaphore = &r600_dma_semaphore_ring_emit,
d2ead3ea 1436 .cs_parse = &evergreen_dma_cs_parse,
233d1ad5
AD		 1437 .ring_test = &r600_dma_ring_test,
1438 .ib_test = &r600_dma_ib_test,
123bc183 1439 .is_lockup = &evergreen_dma_is_lockup,
f93bdefe
AD		 1440 .get_rptr = &radeon_ring_generic_get_rptr,
1441 .get_wptr = &radeon_ring_generic_get_wptr,
1442 .set_wptr = &radeon_ring_generic_set_wptr,
f2ba57b5
CK		 1443 },
1444 [R600_RING_TYPE_UVD_INDEX] = {
1445 .ib_execute = &r600_uvd_ib_execute,
1446 .emit_fence = &r600_uvd_fence_emit,
1447 .emit_semaphore = &r600_uvd_semaphore_emit,
1448 .cs_parse = &radeon_uvd_cs_parse,
1449 .ring_test = &r600_uvd_ring_test,
1450 .ib_test = &r600_uvd_ib_test,
1451 .is_lockup = &radeon_ring_test_lockup,
f93bdefe
AD		 1452 .get_rptr = &radeon_ring_generic_get_rptr,
1453 .get_wptr = &radeon_ring_generic_get_wptr,
1454 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 1455 }
1456 },
b35ea4ab
AD		 1457 .irq = {
1458 .set = &evergreen_irq_set,
1459 .process = &evergreen_irq_process,
1460 },
c79a49ca
AD		 1461 .display = {
1462 .bandwidth_update = &evergreen_bandwidth_update,
1463 .get_vblank_counter = &evergreen_get_vblank_counter,
1464 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1465 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1466 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1467 .hdmi_enable = &evergreen_hdmi_enable,
1468 .hdmi_setmode = &evergreen_hdmi_setmode,
c79a49ca 1469 },
27cd7769
AD		 1470 .copy = {
1471 .blit = &r600_copy_blit,
1472 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1473 .dma = &evergreen_copy_dma,
1474 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1475 .copy = &evergreen_copy_dma,
1476 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1477 },
9e6f3d02
AD		 1478 .surface = {
1479 .set_reg = r600_set_surface_reg,
1480 .clear_reg = r600_clear_surface_reg,
1481 },
901ea57d
AD		 1482 .hpd = {
1483 .init = &evergreen_hpd_init,
1484 .fini = &evergreen_hpd_fini,
1485 .sense = &evergreen_hpd_sense,
1486 .set_polarity = &evergreen_hpd_set_polarity,
1487 },
a02fa397
AD		 1488 .pm = {
1489 .misc = &evergreen_pm_misc,
1490 .prepare = &evergreen_pm_prepare,
1491 .finish = &evergreen_pm_finish,
1492 .init_profile = &r600_pm_init_profile,
1493 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1494 .get_engine_clock = &radeon_atom_get_engine_clock,
1495 .set_engine_clock = &radeon_atom_set_engine_clock,
1496 .get_memory_clock = &radeon_atom_get_memory_clock,
1497 .set_memory_clock = &radeon_atom_set_memory_clock,
1498 .get_pcie_lanes = &r600_get_pcie_lanes,
1499 .set_pcie_lanes = &r600_set_pcie_lanes,
1500 .set_clock_gating = NULL,
a8b4925c 1501 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1502 .get_temperature = &evergreen_get_temp,
a02fa397 1503 },
dc50ba7f
AD		 1504 .dpm = {
1505 .init = &cypress_dpm_init,
1506 .setup_asic = &cypress_dpm_setup_asic,
1507 .enable = &cypress_dpm_enable,
1508 .disable = &cypress_dpm_disable,
98243917 1509 .pre_set_power_state = &r600_dpm_pre_set_power_state,
dc50ba7f 1510 .set_power_state = &cypress_dpm_set_power_state,
98243917 1511 .post_set_power_state = &r600_dpm_post_set_power_state,
dc50ba7f
AD		 1512 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1513 .fini = &cypress_dpm_fini,
1514 .get_sclk = &rv770_dpm_get_sclk,
1515 .get_mclk = &rv770_dpm_get_mclk,
1516 .print_power_state = &rv770_dpm_print_power_state,
1517 },
0f9e006c
AD		 1518 .pflip = {
1519 .pre_page_flip = &evergreen_pre_page_flip,
1520 .page_flip = &evergreen_page_flip,
1521 .post_page_flip = &evergreen_post_page_flip,
1522 },
48e7a5f1
DV		 1523};
1524
958261d1
AD		 1525static struct radeon_asic sumo_asic = {
1526 .init = &evergreen_init,
1527 .fini = &evergreen_fini,
1528 .suspend = &evergreen_suspend,
1529 .resume = &evergreen_resume,
958261d1
AD		 1530 .asic_reset = &evergreen_asic_reset,
1531 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1532 .ioctl_wait_idle = r600_ioctl_wait_idle,
1533 .gui_idle = &r600_gui_idle,
1534 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1535 .get_xclk = &r600_get_xclk,
d0418894 1536 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1537 .gart = {
1538 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1539 .set_page = &rs600_gart_set_page,
1540 },
4c87bc26
CK		 1541 .ring = {
1542 [RADEON_RING_TYPE_GFX_INDEX] = {
1543 .ib_execute = &evergreen_ring_ib_execute,
1544 .emit_fence = &r600_fence_ring_emit,
1545 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1546 .cs_parse = &evergreen_cs_parse,
f712812e
AD		 1547 .ring_test = &r600_ring_test,
1548 .ib_test = &r600_ib_test,
123bc183 1549 .is_lockup = &evergreen_gfx_is_lockup,
f93bdefe
AD		 1550 .get_rptr = &radeon_ring_generic_get_rptr,
1551 .get_wptr = &radeon_ring_generic_get_wptr,
1552 .set_wptr = &radeon_ring_generic_set_wptr,
eb0c19c5 1553 },
233d1ad5
AD		 1554 [R600_RING_TYPE_DMA_INDEX] = {
1555 .ib_execute = &evergreen_dma_ring_ib_execute,
1556 .emit_fence = &evergreen_dma_fence_ring_emit,
1557 .emit_semaphore = &r600_dma_semaphore_ring_emit,
d2ead3ea 1558 .cs_parse = &evergreen_dma_cs_parse,
233d1ad5
AD		 1559 .ring_test = &r600_dma_ring_test,
1560 .ib_test = &r600_dma_ib_test,
123bc183 1561 .is_lockup = &evergreen_dma_is_lockup,
f93bdefe
AD		 1562 .get_rptr = &radeon_ring_generic_get_rptr,
1563 .get_wptr = &radeon_ring_generic_get_wptr,
1564 .set_wptr = &radeon_ring_generic_set_wptr,
f2ba57b5
CK		 1565 },
1566 [R600_RING_TYPE_UVD_INDEX] = {
1567 .ib_execute = &r600_uvd_ib_execute,
1568 .emit_fence = &r600_uvd_fence_emit,
1569 .emit_semaphore = &r600_uvd_semaphore_emit,
1570 .cs_parse = &radeon_uvd_cs_parse,
1571 .ring_test = &r600_uvd_ring_test,
1572 .ib_test = &r600_uvd_ib_test,
1573 .is_lockup = &radeon_ring_test_lockup,
f93bdefe
AD		 1574 .get_rptr = &radeon_ring_generic_get_rptr,
1575 .get_wptr = &radeon_ring_generic_get_wptr,
1576 .set_wptr = &radeon_ring_generic_set_wptr,
233d1ad5 1577 }
4c87bc26 1578 },
b35ea4ab
AD		 1579 .irq = {
1580 .set = &evergreen_irq_set,
1581 .process = &evergreen_irq_process,
1582 },
c79a49ca
AD		 1583 .display = {
1584 .bandwidth_update = &evergreen_bandwidth_update,
1585 .get_vblank_counter = &evergreen_get_vblank_counter,
1586 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1587 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1588 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1589 .hdmi_enable = &evergreen_hdmi_enable,
1590 .hdmi_setmode = &evergreen_hdmi_setmode,
c79a49ca 1591 },
27cd7769
AD		 1592 .copy = {
1593 .blit = &r600_copy_blit,
1594 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1595 .dma = &evergreen_copy_dma,
1596 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1597 .copy = &evergreen_copy_dma,
1598 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1599 },
9e6f3d02
AD		 1600 .surface = {
1601 .set_reg = r600_set_surface_reg,
1602 .clear_reg = r600_clear_surface_reg,
1603 },
901ea57d
AD		 1604 .hpd = {
1605 .init = &evergreen_hpd_init,
1606 .fini = &evergreen_hpd_fini,
1607 .sense = &evergreen_hpd_sense,
1608 .set_polarity = &evergreen_hpd_set_polarity,
1609 },
a02fa397
AD		 1610 .pm = {
1611 .misc = &evergreen_pm_misc,
1612 .prepare = &evergreen_pm_prepare,
1613 .finish = &evergreen_pm_finish,
1614 .init_profile = &sumo_pm_init_profile,
1615 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1616 .get_engine_clock = &radeon_atom_get_engine_clock,
1617 .set_engine_clock = &radeon_atom_set_engine_clock,
1618 .get_memory_clock = NULL,
1619 .set_memory_clock = NULL,
1620 .get_pcie_lanes = NULL,
1621 .set_pcie_lanes = NULL,
1622 .set_clock_gating = NULL,
23d33ba3 1623 .set_uvd_clocks = &sumo_set_uvd_clocks,
6bd1c385 1624 .get_temperature = &sumo_get_temp,
a02fa397 1625 },
80ea2c12
AD		 1626 .dpm = {
1627 .init = &sumo_dpm_init,
1628 .setup_asic = &sumo_dpm_setup_asic,
1629 .enable = &sumo_dpm_enable,
1630 .disable = &sumo_dpm_disable,
422a56bc 1631 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
80ea2c12 1632 .set_power_state = &sumo_dpm_set_power_state,
422a56bc 1633 .post_set_power_state = &sumo_dpm_post_set_power_state,
80ea2c12
AD		 1634 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1635 .fini = &sumo_dpm_fini,
1636 .get_sclk = &sumo_dpm_get_sclk,
1637 .get_mclk = &sumo_dpm_get_mclk,
1638 .print_power_state = &sumo_dpm_print_power_state,
1639 },
0f9e006c
AD		 1640 .pflip = {
1641 .pre_page_flip = &evergreen_pre_page_flip,
1642 .page_flip = &evergreen_page_flip,
1643 .post_page_flip = &evergreen_post_page_flip,
1644 },
958261d1
AD		 1645};
1646
a43b7665
AD		 1647static struct radeon_asic btc_asic = {
1648 .init = &evergreen_init,
1649 .fini = &evergreen_fini,
1650 .suspend = &evergreen_suspend,
1651 .resume = &evergreen_resume,
a43b7665
AD		 1652 .asic_reset = &evergreen_asic_reset,
1653 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1654 .ioctl_wait_idle = r600_ioctl_wait_idle,
1655 .gui_idle = &r600_gui_idle,
1656 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1657 .get_xclk = &rv770_get_xclk,
d0418894 1658 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1659 .gart = {
1660 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1661 .set_page = &rs600_gart_set_page,
1662 },
4c87bc26
CK		 1663 .ring = {
1664 [RADEON_RING_TYPE_GFX_INDEX] = {
1665 .ib_execute = &evergreen_ring_ib_execute,
1666 .emit_fence = &r600_fence_ring_emit,
1667 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1668 .cs_parse = &evergreen_cs_parse,
f712812e
AD		 1669 .ring_test = &r600_ring_test,
1670 .ib_test = &r600_ib_test,
123bc183 1671 .is_lockup = &evergreen_gfx_is_lockup,
f93bdefe
AD		 1672 .get_rptr = &radeon_ring_generic_get_rptr,
1673 .get_wptr = &radeon_ring_generic_get_wptr,
1674 .set_wptr = &radeon_ring_generic_set_wptr,
233d1ad5
AD		 1675 },
1676 [R600_RING_TYPE_DMA_INDEX] = {
1677 .ib_execute = &evergreen_dma_ring_ib_execute,
1678 .emit_fence = &evergreen_dma_fence_ring_emit,
1679 .emit_semaphore = &r600_dma_semaphore_ring_emit,
d2ead3ea 1680 .cs_parse = &evergreen_dma_cs_parse,
233d1ad5
AD		 1681 .ring_test = &r600_dma_ring_test,
1682 .ib_test = &r600_dma_ib_test,
123bc183 1683 .is_lockup = &evergreen_dma_is_lockup,
f93bdefe
AD		 1684 .get_rptr = &radeon_ring_generic_get_rptr,
1685 .get_wptr = &radeon_ring_generic_get_wptr,
1686 .set_wptr = &radeon_ring_generic_set_wptr,
f2ba57b5
CK		 1687 },
1688 [R600_RING_TYPE_UVD_INDEX] = {
1689 .ib_execute = &r600_uvd_ib_execute,
1690 .emit_fence = &r600_uvd_fence_emit,
1691 .emit_semaphore = &r600_uvd_semaphore_emit,
1692 .cs_parse = &radeon_uvd_cs_parse,
1693 .ring_test = &r600_uvd_ring_test,
1694 .ib_test = &r600_uvd_ib_test,
1695 .is_lockup = &radeon_ring_test_lockup,
f93bdefe
AD		 1696 .get_rptr = &radeon_ring_generic_get_rptr,
1697 .get_wptr = &radeon_ring_generic_get_wptr,
1698 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 1699 }
1700 },
b35ea4ab
AD		 1701 .irq = {
1702 .set = &evergreen_irq_set,
1703 .process = &evergreen_irq_process,
1704 },
c79a49ca
AD		 1705 .display = {
1706 .bandwidth_update = &evergreen_bandwidth_update,
1707 .get_vblank_counter = &evergreen_get_vblank_counter,
1708 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1709 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1710 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1711 .hdmi_enable = &evergreen_hdmi_enable,
1712 .hdmi_setmode = &evergreen_hdmi_setmode,
c79a49ca 1713 },
27cd7769
AD		 1714 .copy = {
1715 .blit = &r600_copy_blit,
1716 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1717 .dma = &evergreen_copy_dma,
1718 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1719 .copy = &evergreen_copy_dma,
1720 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1721 },
9e6f3d02
AD		 1722 .surface = {
1723 .set_reg = r600_set_surface_reg,
1724 .clear_reg = r600_clear_surface_reg,
1725 },
901ea57d
AD		 1726 .hpd = {
1727 .init = &evergreen_hpd_init,
1728 .fini = &evergreen_hpd_fini,
1729 .sense = &evergreen_hpd_sense,
1730 .set_polarity = &evergreen_hpd_set_polarity,
1731 },
a02fa397
AD		 1732 .pm = {
1733 .misc = &evergreen_pm_misc,
1734 .prepare = &evergreen_pm_prepare,
1735 .finish = &evergreen_pm_finish,
27810fb2 1736 .init_profile = &btc_pm_init_profile,
a02fa397 1737 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1738 .get_engine_clock = &radeon_atom_get_engine_clock,
1739 .set_engine_clock = &radeon_atom_set_engine_clock,
1740 .get_memory_clock = &radeon_atom_get_memory_clock,
1741 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1742 .get_pcie_lanes = &r600_get_pcie_lanes,
1743 .set_pcie_lanes = &r600_set_pcie_lanes,
798bcf73 1744 .set_clock_gating = NULL,
a8b4925c 1745 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1746 .get_temperature = &evergreen_get_temp,
a02fa397 1747 },
6596afd4
AD		 1748 .dpm = {
1749 .init = &btc_dpm_init,
1750 .setup_asic = &btc_dpm_setup_asic,
1751 .enable = &btc_dpm_enable,
1752 .disable = &btc_dpm_disable,
e8a9539f 1753 .pre_set_power_state = &btc_dpm_pre_set_power_state,
6596afd4 1754 .set_power_state = &btc_dpm_set_power_state,
e8a9539f 1755 .post_set_power_state = &btc_dpm_post_set_power_state,
6596afd4
AD		 1756 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1757 .fini = &btc_dpm_fini,
e8a9539f
AD		 1758 .get_sclk = &btc_dpm_get_sclk,
1759 .get_mclk = &btc_dpm_get_mclk,
6596afd4
AD		 1760 .print_power_state = &rv770_dpm_print_power_state,
1761 },
0f9e006c
AD		 1762 .pflip = {
1763 .pre_page_flip = &evergreen_pre_page_flip,
1764 .page_flip = &evergreen_page_flip,
1765 .post_page_flip = &evergreen_post_page_flip,
1766 },
a43b7665
AD		 1767};
1768
e3487629
AD		 1769static struct radeon_asic cayman_asic = {
1770 .init = &cayman_init,
1771 .fini = &cayman_fini,
1772 .suspend = &cayman_suspend,
1773 .resume = &cayman_resume,
e3487629
AD		 1774 .asic_reset = &cayman_asic_reset,
1775 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1776 .ioctl_wait_idle = r600_ioctl_wait_idle,
1777 .gui_idle = &r600_gui_idle,
1778 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1779 .get_xclk = &rv770_get_xclk,
d0418894 1780 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1781 .gart = {
1782 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1783 .set_page = &rs600_gart_set_page,
1784 },
05b07147
CK		 1785 .vm = {
1786 .init = &cayman_vm_init,
1787 .fini = &cayman_vm_fini,
df160044 1788 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
05b07147
CK		 1789 .set_page = &cayman_vm_set_page,
1790 },
4c87bc26
CK		 1791 .ring = {
1792 [RADEON_RING_TYPE_GFX_INDEX] = {
721604a1
JG		 1793 .ib_execute = &cayman_ring_ib_execute,
1794 .ib_parse = &evergreen_ib_parse,
b40e7e16 1795 .emit_fence = &cayman_fence_ring_emit,
4c87bc26 1796 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1797 .cs_parse = &evergreen_cs_parse,
f712812e
AD		 1798 .ring_test = &r600_ring_test,
1799 .ib_test = &r600_ib_test,
123bc183 1800 .is_lockup = &cayman_gfx_is_lockup,
9b40e5d8 1801 .vm_flush = &cayman_vm_flush,
f93bdefe
AD		 1802 .get_rptr = &radeon_ring_generic_get_rptr,
1803 .get_wptr = &radeon_ring_generic_get_wptr,
1804 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 1805 },
1806 [CAYMAN_RING_TYPE_CP1_INDEX] = {
721604a1
JG		 1807 .ib_execute = &cayman_ring_ib_execute,
1808 .ib_parse = &evergreen_ib_parse,
b40e7e16 1809 .emit_fence = &cayman_fence_ring_emit,
4c87bc26 1810 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1811 .cs_parse = &evergreen_cs_parse,
f712812e
AD		 1812 .ring_test = &r600_ring_test,
1813 .ib_test = &r600_ib_test,
123bc183 1814 .is_lockup = &cayman_gfx_is_lockup,
9b40e5d8 1815 .vm_flush = &cayman_vm_flush,
f93bdefe
AD		 1816 .get_rptr = &radeon_ring_generic_get_rptr,
1817 .get_wptr = &radeon_ring_generic_get_wptr,
1818 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 1819 },
1820 [CAYMAN_RING_TYPE_CP2_INDEX] = {
721604a1
JG		 1821 .ib_execute = &cayman_ring_ib_execute,
1822 .ib_parse = &evergreen_ib_parse,
b40e7e16 1823 .emit_fence = &cayman_fence_ring_emit,
4c87bc26 1824 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1825 .cs_parse = &evergreen_cs_parse,
f712812e
AD		 1826 .ring_test = &r600_ring_test,
1827 .ib_test = &r600_ib_test,
123bc183 1828 .is_lockup = &cayman_gfx_is_lockup,
9b40e5d8 1829 .vm_flush = &cayman_vm_flush,
f93bdefe
AD		 1830 .get_rptr = &radeon_ring_generic_get_rptr,
1831 .get_wptr = &radeon_ring_generic_get_wptr,
1832 .set_wptr = &radeon_ring_generic_set_wptr,
f60cbd11
AD		 1833 },
1834 [R600_RING_TYPE_DMA_INDEX] = {
1835 .ib_execute = &cayman_dma_ring_ib_execute,
cd459e52 1836 .ib_parse = &evergreen_dma_ib_parse,
f60cbd11
AD		 1837 .emit_fence = &evergreen_dma_fence_ring_emit,
1838 .emit_semaphore = &r600_dma_semaphore_ring_emit,
d2ead3ea 1839 .cs_parse = &evergreen_dma_cs_parse,
f60cbd11
AD		 1840 .ring_test = &r600_dma_ring_test,
1841 .ib_test = &r600_dma_ib_test,
1842 .is_lockup = &cayman_dma_is_lockup,
1843 .vm_flush = &cayman_dma_vm_flush,
f93bdefe
AD		 1844 .get_rptr = &radeon_ring_generic_get_rptr,
1845 .get_wptr = &radeon_ring_generic_get_wptr,
1846 .set_wptr = &radeon_ring_generic_set_wptr,
f60cbd11
AD		 1847 },
1848 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1849 .ib_execute = &cayman_dma_ring_ib_execute,
cd459e52 1850 .ib_parse = &evergreen_dma_ib_parse,
f60cbd11
AD		 1851 .emit_fence = &evergreen_dma_fence_ring_emit,
1852 .emit_semaphore = &r600_dma_semaphore_ring_emit,
d2ead3ea 1853 .cs_parse = &evergreen_dma_cs_parse,
f60cbd11
AD		 1854 .ring_test = &r600_dma_ring_test,
1855 .ib_test = &r600_dma_ib_test,
1856 .is_lockup = &cayman_dma_is_lockup,
1857 .vm_flush = &cayman_dma_vm_flush,
f93bdefe
AD		 1858 .get_rptr = &radeon_ring_generic_get_rptr,
1859 .get_wptr = &radeon_ring_generic_get_wptr,
1860 .set_wptr = &radeon_ring_generic_set_wptr,
f2ba57b5
CK		 1861 },
1862 [R600_RING_TYPE_UVD_INDEX] = {
1863 .ib_execute = &r600_uvd_ib_execute,
1864 .emit_fence = &r600_uvd_fence_emit,
1865 .emit_semaphore = &cayman_uvd_semaphore_emit,
1866 .cs_parse = &radeon_uvd_cs_parse,
1867 .ring_test = &r600_uvd_ring_test,
1868 .ib_test = &r600_uvd_ib_test,
1869 .is_lockup = &radeon_ring_test_lockup,
f93bdefe
AD		 1870 .get_rptr = &radeon_ring_generic_get_rptr,
1871 .get_wptr = &radeon_ring_generic_get_wptr,
1872 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 1873 }
1874 },
b35ea4ab
AD		 1875 .irq = {
1876 .set = &evergreen_irq_set,
1877 .process = &evergreen_irq_process,
1878 },
c79a49ca
AD		 1879 .display = {
1880 .bandwidth_update = &evergreen_bandwidth_update,
1881 .get_vblank_counter = &evergreen_get_vblank_counter,
1882 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1883 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1884 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1885 .hdmi_enable = &evergreen_hdmi_enable,
1886 .hdmi_setmode = &evergreen_hdmi_setmode,
c79a49ca 1887 },
27cd7769
AD		 1888 .copy = {
1889 .blit = &r600_copy_blit,
1890 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
f60cbd11
AD		 1891 .dma = &evergreen_copy_dma,
1892 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1893 .copy = &evergreen_copy_dma,
1894 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1895 },
9e6f3d02
AD		 1896 .surface = {
1897 .set_reg = r600_set_surface_reg,
1898 .clear_reg = r600_clear_surface_reg,
1899 },
901ea57d
AD		 1900 .hpd = {
1901 .init = &evergreen_hpd_init,
1902 .fini = &evergreen_hpd_fini,
1903 .sense = &evergreen_hpd_sense,
1904 .set_polarity = &evergreen_hpd_set_polarity,
1905 },
a02fa397
AD		 1906 .pm = {
1907 .misc = &evergreen_pm_misc,
1908 .prepare = &evergreen_pm_prepare,
1909 .finish = &evergreen_pm_finish,
27810fb2 1910 .init_profile = &btc_pm_init_profile,
a02fa397 1911 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1912 .get_engine_clock = &radeon_atom_get_engine_clock,
1913 .set_engine_clock = &radeon_atom_set_engine_clock,
1914 .get_memory_clock = &radeon_atom_get_memory_clock,
1915 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1916 .get_pcie_lanes = &r600_get_pcie_lanes,
1917 .set_pcie_lanes = &r600_set_pcie_lanes,
798bcf73 1918 .set_clock_gating = NULL,
a8b4925c 1919 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1920 .get_temperature = &evergreen_get_temp,
a02fa397 1921 },
69e0b57a
AD		 1922 .dpm = {
1923 .init = &ni_dpm_init,
1924 .setup_asic = &ni_dpm_setup_asic,
1925 .enable = &ni_dpm_enable,
1926 .disable = &ni_dpm_disable,
fee3d744 1927 .pre_set_power_state = &ni_dpm_pre_set_power_state,
69e0b57a 1928 .set_power_state = &ni_dpm_set_power_state,
fee3d744 1929 .post_set_power_state = &ni_dpm_post_set_power_state,
69e0b57a
AD		 1930 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1931 .fini = &ni_dpm_fini,
1932 .get_sclk = &ni_dpm_get_sclk,
1933 .get_mclk = &ni_dpm_get_mclk,
1934 .print_power_state = &ni_dpm_print_power_state,
1935 },
0f9e006c
AD		 1936 .pflip = {
1937 .pre_page_flip = &evergreen_pre_page_flip,
1938 .page_flip = &evergreen_page_flip,
1939 .post_page_flip = &evergreen_post_page_flip,
1940 },
e3487629
AD		 1941};
1942
be63fe8c
AD		 1943static struct radeon_asic trinity_asic = {
1944 .init = &cayman_init,
1945 .fini = &cayman_fini,
1946 .suspend = &cayman_suspend,
1947 .resume = &cayman_resume,
be63fe8c
AD		 1948 .asic_reset = &cayman_asic_reset,
1949 .vga_set_state = &r600_vga_set_state,
1950 .ioctl_wait_idle = r600_ioctl_wait_idle,
1951 .gui_idle = &r600_gui_idle,
1952 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1953 .get_xclk = &r600_get_xclk,
d0418894 1954 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
be63fe8c
AD		 1955 .gart = {
1956 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1957 .set_page = &rs600_gart_set_page,
1958 },
05b07147
CK		 1959 .vm = {
1960 .init = &cayman_vm_init,
1961 .fini = &cayman_vm_fini,
df160044 1962 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
05b07147
CK		 1963 .set_page = &cayman_vm_set_page,
1964 },
be63fe8c
AD		 1965 .ring = {
1966 [RADEON_RING_TYPE_GFX_INDEX] = {
1967 .ib_execute = &cayman_ring_ib_execute,
1968 .ib_parse = &evergreen_ib_parse,
1969 .emit_fence = &cayman_fence_ring_emit,
1970 .emit_semaphore = &r600_semaphore_ring_emit,
1971 .cs_parse = &evergreen_cs_parse,
1972 .ring_test = &r600_ring_test,
1973 .ib_test = &r600_ib_test,
123bc183 1974 .is_lockup = &cayman_gfx_is_lockup,
9b40e5d8 1975 .vm_flush = &cayman_vm_flush,
f93bdefe
AD		 1976 .get_rptr = &radeon_ring_generic_get_rptr,
1977 .get_wptr = &radeon_ring_generic_get_wptr,
1978 .set_wptr = &radeon_ring_generic_set_wptr,
be63fe8c
AD		 1979 },
1980 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1981 .ib_execute = &cayman_ring_ib_execute,
1982 .ib_parse = &evergreen_ib_parse,
1983 .emit_fence = &cayman_fence_ring_emit,
1984 .emit_semaphore = &r600_semaphore_ring_emit,
1985 .cs_parse = &evergreen_cs_parse,
1986 .ring_test = &r600_ring_test,
1987 .ib_test = &r600_ib_test,
123bc183 1988 .is_lockup = &cayman_gfx_is_lockup,
9b40e5d8 1989 .vm_flush = &cayman_vm_flush,
f93bdefe
AD		 1990 .get_rptr = &radeon_ring_generic_get_rptr,
1991 .get_wptr = &radeon_ring_generic_get_wptr,
1992 .set_wptr = &radeon_ring_generic_set_wptr,
be63fe8c
AD		 1993 },
1994 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1995 .ib_execute = &cayman_ring_ib_execute,
1996 .ib_parse = &evergreen_ib_parse,
1997 .emit_fence = &cayman_fence_ring_emit,
1998 .emit_semaphore = &r600_semaphore_ring_emit,
1999 .cs_parse = &evergreen_cs_parse,
2000 .ring_test = &r600_ring_test,
2001 .ib_test = &r600_ib_test,
123bc183 2002 .is_lockup = &cayman_gfx_is_lockup,
9b40e5d8 2003 .vm_flush = &cayman_vm_flush,
f93bdefe
AD		 2004 .get_rptr = &radeon_ring_generic_get_rptr,
2005 .get_wptr = &radeon_ring_generic_get_wptr,
2006 .set_wptr = &radeon_ring_generic_set_wptr,
f60cbd11
AD		 2007 },
2008 [R600_RING_TYPE_DMA_INDEX] = {
2009 .ib_execute = &cayman_dma_ring_ib_execute,
cd459e52 2010 .ib_parse = &evergreen_dma_ib_parse,
f60cbd11
AD		 2011 .emit_fence = &evergreen_dma_fence_ring_emit,
2012 .emit_semaphore = &r600_dma_semaphore_ring_emit,
d2ead3ea 2013 .cs_parse = &evergreen_dma_cs_parse,
f60cbd11
AD		 2014 .ring_test = &r600_dma_ring_test,
2015 .ib_test = &r600_dma_ib_test,
2016 .is_lockup = &cayman_dma_is_lockup,
2017 .vm_flush = &cayman_dma_vm_flush,
f93bdefe
AD		 2018 .get_rptr = &radeon_ring_generic_get_rptr,
2019 .get_wptr = &radeon_ring_generic_get_wptr,
2020 .set_wptr = &radeon_ring_generic_set_wptr,
f60cbd11
AD		 2021 },
2022 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2023 .ib_execute = &cayman_dma_ring_ib_execute,
cd459e52 2024 .ib_parse = &evergreen_dma_ib_parse,
f60cbd11
AD		 2025 .emit_fence = &evergreen_dma_fence_ring_emit,
2026 .emit_semaphore = &r600_dma_semaphore_ring_emit,
d2ead3ea 2027 .cs_parse = &evergreen_dma_cs_parse,
f60cbd11
AD		 2028 .ring_test = &r600_dma_ring_test,
2029 .ib_test = &r600_dma_ib_test,
2030 .is_lockup = &cayman_dma_is_lockup,
2031 .vm_flush = &cayman_dma_vm_flush,
f93bdefe
AD		 2032 .get_rptr = &radeon_ring_generic_get_rptr,
2033 .get_wptr = &radeon_ring_generic_get_wptr,
2034 .set_wptr = &radeon_ring_generic_set_wptr,
f2ba57b5
CK		 2035 },
2036 [R600_RING_TYPE_UVD_INDEX] = {
2037 .ib_execute = &r600_uvd_ib_execute,
2038 .emit_fence = &r600_uvd_fence_emit,
2039 .emit_semaphore = &cayman_uvd_semaphore_emit,
2040 .cs_parse = &radeon_uvd_cs_parse,
2041 .ring_test = &r600_uvd_ring_test,
2042 .ib_test = &r600_uvd_ib_test,
2043 .is_lockup = &radeon_ring_test_lockup,
f93bdefe
AD		 2044 .get_rptr = &radeon_ring_generic_get_rptr,
2045 .get_wptr = &radeon_ring_generic_get_wptr,
2046 .set_wptr = &radeon_ring_generic_set_wptr,
be63fe8c
AD		 2047 }
2048 },
2049 .irq = {
2050 .set = &evergreen_irq_set,
2051 .process = &evergreen_irq_process,
2052 },
2053 .display = {
2054 .bandwidth_update = &dce6_bandwidth_update,
2055 .get_vblank_counter = &evergreen_get_vblank_counter,
2056 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 2057 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 2058 .get_backlight_level = &atombios_get_backlight_level,
be63fe8c
AD		 2059 },
2060 .copy = {
2061 .blit = &r600_copy_blit,
2062 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
f60cbd11
AD		 2063 .dma = &evergreen_copy_dma,
2064 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 2065 .copy = &evergreen_copy_dma,
2066 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
be63fe8c
AD		 2067 },
2068 .surface = {
2069 .set_reg = r600_set_surface_reg,
2070 .clear_reg = r600_clear_surface_reg,
2071 },
2072 .hpd = {
2073 .init = &evergreen_hpd_init,
2074 .fini = &evergreen_hpd_fini,
2075 .sense = &evergreen_hpd_sense,
2076 .set_polarity = &evergreen_hpd_set_polarity,
2077 },
2078 .pm = {
2079 .misc = &evergreen_pm_misc,
2080 .prepare = &evergreen_pm_prepare,
2081 .finish = &evergreen_pm_finish,
2082 .init_profile = &sumo_pm_init_profile,
2083 .get_dynpm_state = &r600_pm_get_dynpm_state,
2084 .get_engine_clock = &radeon_atom_get_engine_clock,
2085 .set_engine_clock = &radeon_atom_set_engine_clock,
2086 .get_memory_clock = NULL,
2087 .set_memory_clock = NULL,
2088 .get_pcie_lanes = NULL,
2089 .set_pcie_lanes = NULL,
2090 .set_clock_gating = NULL,
23d33ba3 2091 .set_uvd_clocks = &sumo_set_uvd_clocks,
29a15221 2092 .get_temperature = &tn_get_temp,
be63fe8c 2093 },
d70229f7
AD		 2094 .dpm = {
2095 .init = &trinity_dpm_init,
2096 .setup_asic = &trinity_dpm_setup_asic,
2097 .enable = &trinity_dpm_enable,
2098 .disable = &trinity_dpm_disable,
a284c48a 2099 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
d70229f7 2100 .set_power_state = &trinity_dpm_set_power_state,
a284c48a 2101 .post_set_power_state = &trinity_dpm_post_set_power_state,
d70229f7
AD		 2102 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
2103 .fini = &trinity_dpm_fini,
2104 .get_sclk = &trinity_dpm_get_sclk,
2105 .get_mclk = &trinity_dpm_get_mclk,
2106 .print_power_state = &trinity_dpm_print_power_state,
2107 },
be63fe8c
AD		 2108 .pflip = {
2109 .pre_page_flip = &evergreen_pre_page_flip,
2110 .page_flip = &evergreen_page_flip,
2111 .post_page_flip = &evergreen_post_page_flip,
2112 },
2113};
2114
02779c08
AD		 2115static struct radeon_asic si_asic = {
2116 .init = &si_init,
2117 .fini = &si_fini,
2118 .suspend = &si_suspend,
2119 .resume = &si_resume,
02779c08
AD		 2120 .asic_reset = &si_asic_reset,
2121 .vga_set_state = &r600_vga_set_state,
2122 .ioctl_wait_idle = r600_ioctl_wait_idle,
2123 .gui_idle = &r600_gui_idle,
2124 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 2125 .get_xclk = &si_get_xclk,
d0418894 2126 .get_gpu_clock_counter = &si_get_gpu_clock_counter,
02779c08
AD		 2127 .gart = {
2128 .tlb_flush = &si_pcie_gart_tlb_flush,
2129 .set_page = &rs600_gart_set_page,
2130 },
05b07147
CK		 2131 .vm = {
2132 .init = &si_vm_init,
2133 .fini = &si_vm_fini,
df160044 2134 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
82ffd92b 2135 .set_page = &si_vm_set_page,
05b07147 2136 },
02779c08
AD		 2137 .ring = {
2138 [RADEON_RING_TYPE_GFX_INDEX] = {
2139 .ib_execute = &si_ring_ib_execute,
2140 .ib_parse = &si_ib_parse,
2141 .emit_fence = &si_fence_ring_emit,
2142 .emit_semaphore = &r600_semaphore_ring_emit,
2143 .cs_parse = NULL,
2144 .ring_test = &r600_ring_test,
2145 .ib_test = &r600_ib_test,
123bc183 2146 .is_lockup = &si_gfx_is_lockup,
ee60e29f 2147 .vm_flush = &si_vm_flush,
f93bdefe
AD		 2148 .get_rptr = &radeon_ring_generic_get_rptr,
2149 .get_wptr = &radeon_ring_generic_get_wptr,
2150 .set_wptr = &radeon_ring_generic_set_wptr,
02779c08
AD		 2151 },
2152 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2153 .ib_execute = &si_ring_ib_execute,
2154 .ib_parse = &si_ib_parse,
2155 .emit_fence = &si_fence_ring_emit,
2156 .emit_semaphore = &r600_semaphore_ring_emit,
2157 .cs_parse = NULL,
2158 .ring_test = &r600_ring_test,
2159 .ib_test = &r600_ib_test,
123bc183 2160 .is_lockup = &si_gfx_is_lockup,
ee60e29f 2161 .vm_flush = &si_vm_flush,
f93bdefe
AD		 2162 .get_rptr = &radeon_ring_generic_get_rptr,
2163 .get_wptr = &radeon_ring_generic_get_wptr,
2164 .set_wptr = &radeon_ring_generic_set_wptr,
02779c08
AD		 2165 },
2166 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2167 .ib_execute = &si_ring_ib_execute,
2168 .ib_parse = &si_ib_parse,
2169 .emit_fence = &si_fence_ring_emit,
2170 .emit_semaphore = &r600_semaphore_ring_emit,
2171 .cs_parse = NULL,
2172 .ring_test = &r600_ring_test,
2173 .ib_test = &r600_ib_test,
123bc183 2174 .is_lockup = &si_gfx_is_lockup,
ee60e29f 2175 .vm_flush = &si_vm_flush,
f93bdefe
AD		 2176 .get_rptr = &radeon_ring_generic_get_rptr,
2177 .get_wptr = &radeon_ring_generic_get_wptr,
2178 .set_wptr = &radeon_ring_generic_set_wptr,
8c5fd7ef
AD		 2179 },
2180 [R600_RING_TYPE_DMA_INDEX] = {
2181 .ib_execute = &cayman_dma_ring_ib_execute,
cd459e52 2182 .ib_parse = &evergreen_dma_ib_parse,
8c5fd7ef
AD		 2183 .emit_fence = &evergreen_dma_fence_ring_emit,
2184 .emit_semaphore = &r600_dma_semaphore_ring_emit,
2185 .cs_parse = NULL,
2186 .ring_test = &r600_dma_ring_test,
2187 .ib_test = &r600_dma_ib_test,
123bc183 2188 .is_lockup = &si_dma_is_lockup,
8c5fd7ef 2189 .vm_flush = &si_dma_vm_flush,
f93bdefe
AD		 2190 .get_rptr = &radeon_ring_generic_get_rptr,
2191 .get_wptr = &radeon_ring_generic_get_wptr,
2192 .set_wptr = &radeon_ring_generic_set_wptr,
8c5fd7ef
AD		 2193 },
2194 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2195 .ib_execute = &cayman_dma_ring_ib_execute,
cd459e52 2196 .ib_parse = &evergreen_dma_ib_parse,
8c5fd7ef
AD		 2197 .emit_fence = &evergreen_dma_fence_ring_emit,
2198 .emit_semaphore = &r600_dma_semaphore_ring_emit,
2199 .cs_parse = NULL,
2200 .ring_test = &r600_dma_ring_test,
2201 .ib_test = &r600_dma_ib_test,
123bc183 2202 .is_lockup = &si_dma_is_lockup,
8c5fd7ef 2203 .vm_flush = &si_dma_vm_flush,
f93bdefe
AD		 2204 .get_rptr = &radeon_ring_generic_get_rptr,
2205 .get_wptr = &radeon_ring_generic_get_wptr,
2206 .set_wptr = &radeon_ring_generic_set_wptr,
f2ba57b5
CK		 2207 },
2208 [R600_RING_TYPE_UVD_INDEX] = {
2209 .ib_execute = &r600_uvd_ib_execute,
2210 .emit_fence = &r600_uvd_fence_emit,
2211 .emit_semaphore = &cayman_uvd_semaphore_emit,
2212 .cs_parse = &radeon_uvd_cs_parse,
2213 .ring_test = &r600_uvd_ring_test,
2214 .ib_test = &r600_uvd_ib_test,
2215 .is_lockup = &radeon_ring_test_lockup,
f93bdefe
AD		 2216 .get_rptr = &radeon_ring_generic_get_rptr,
2217 .get_wptr = &radeon_ring_generic_get_wptr,
2218 .set_wptr = &radeon_ring_generic_set_wptr,
02779c08
AD		 2219 }
2220 },
2221 .irq = {
2222 .set = &si_irq_set,
2223 .process = &si_irq_process,
2224 },
2225 .display = {
2226 .bandwidth_update = &dce6_bandwidth_update,
2227 .get_vblank_counter = &evergreen_get_vblank_counter,
2228 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 2229 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 2230 .get_backlight_level = &atombios_get_backlight_level,
02779c08
AD		 2231 },
2232 .copy = {
2233 .blit = NULL,
2234 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
8c5fd7ef
AD		 2235 .dma = &si_copy_dma,
2236 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 2237 .copy = &si_copy_dma,
2238 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
02779c08
AD		 2239 },
2240 .surface = {
2241 .set_reg = r600_set_surface_reg,
2242 .clear_reg = r600_clear_surface_reg,
2243 },
2244 .hpd = {
2245 .init = &evergreen_hpd_init,
2246 .fini = &evergreen_hpd_fini,
2247 .sense = &evergreen_hpd_sense,
2248 .set_polarity = &evergreen_hpd_set_polarity,
2249 },
2250 .pm = {
2251 .misc = &evergreen_pm_misc,
2252 .prepare = &evergreen_pm_prepare,
2253 .finish = &evergreen_pm_finish,
2254 .init_profile = &sumo_pm_init_profile,
2255 .get_dynpm_state = &r600_pm_get_dynpm_state,
2256 .get_engine_clock = &radeon_atom_get_engine_clock,
2257 .set_engine_clock = &radeon_atom_set_engine_clock,
2258 .get_memory_clock = &radeon_atom_get_memory_clock,
2259 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 2260 .get_pcie_lanes = &r600_get_pcie_lanes,
2261 .set_pcie_lanes = &r600_set_pcie_lanes,
02779c08 2262 .set_clock_gating = NULL,
2539eb02 2263 .set_uvd_clocks = &si_set_uvd_clocks,
6bd1c385 2264 .get_temperature = &si_get_temp,
02779c08 2265 },
a9e61410
AD		 2266 .dpm = {
2267 .init = &si_dpm_init,
2268 .setup_asic = &si_dpm_setup_asic,
2269 .enable = &si_dpm_enable,
2270 .disable = &si_dpm_disable,
2271 .pre_set_power_state = &si_dpm_pre_set_power_state,
2272 .set_power_state = &si_dpm_set_power_state,
2273 .post_set_power_state = &si_dpm_post_set_power_state,
2274 .display_configuration_changed = &si_dpm_display_configuration_changed,
2275 .fini = &si_dpm_fini,
2276 .get_sclk = &ni_dpm_get_sclk,
2277 .get_mclk = &ni_dpm_get_mclk,
2278 .print_power_state = &ni_dpm_print_power_state,
2279 },
02779c08
AD		 2280 .pflip = {
2281 .pre_page_flip = &evergreen_pre_page_flip,
2282 .page_flip = &evergreen_page_flip,
2283 .post_page_flip = &evergreen_post_page_flip,
2284 },
2285};
2286
0672e27b
AD		 2287static struct radeon_asic ci_asic = {
2288 .init = &cik_init,
2289 .fini = &cik_fini,
2290 .suspend = &cik_suspend,
2291 .resume = &cik_resume,
2292 .asic_reset = &cik_asic_reset,
2293 .vga_set_state = &r600_vga_set_state,
2294 .ioctl_wait_idle = NULL,
2295 .gui_idle = &r600_gui_idle,
2296 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2297 .get_xclk = &cik_get_xclk,
2298 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2299 .gart = {
2300 .tlb_flush = &cik_pcie_gart_tlb_flush,
2301 .set_page = &rs600_gart_set_page,
2302 },
2303 .vm = {
2304 .init = &cik_vm_init,
2305 .fini = &cik_vm_fini,
2306 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2307 .set_page = &cik_vm_set_page,
2308 },
2309 .ring = {
2310 [RADEON_RING_TYPE_GFX_INDEX] = {
2311 .ib_execute = &cik_ring_ib_execute,
2312 .ib_parse = &cik_ib_parse,
2313 .emit_fence = &cik_fence_gfx_ring_emit,
2314 .emit_semaphore = &cik_semaphore_ring_emit,
2315 .cs_parse = NULL,
2316 .ring_test = &cik_ring_test,
2317 .ib_test = &cik_ib_test,
2318 .is_lockup = &cik_gfx_is_lockup,
2319 .vm_flush = &cik_vm_flush,
2320 .get_rptr = &radeon_ring_generic_get_rptr,
2321 .get_wptr = &radeon_ring_generic_get_wptr,
2322 .set_wptr = &radeon_ring_generic_set_wptr,
2323 },
2324 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2325 .ib_execute = &cik_ring_ib_execute,
2326 .ib_parse = &cik_ib_parse,
2327 .emit_fence = &cik_fence_compute_ring_emit,
2328 .emit_semaphore = &cik_semaphore_ring_emit,
2329 .cs_parse = NULL,
2330 .ring_test = &cik_ring_test,
2331 .ib_test = &cik_ib_test,
2332 .is_lockup = &cik_gfx_is_lockup,
2333 .vm_flush = &cik_vm_flush,
2334 .get_rptr = &cik_compute_ring_get_rptr,
2335 .get_wptr = &cik_compute_ring_get_wptr,
2336 .set_wptr = &cik_compute_ring_set_wptr,
2337 },
2338 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2339 .ib_execute = &cik_ring_ib_execute,
2340 .ib_parse = &cik_ib_parse,
2341 .emit_fence = &cik_fence_compute_ring_emit,
2342 .emit_semaphore = &cik_semaphore_ring_emit,
2343 .cs_parse = NULL,
2344 .ring_test = &cik_ring_test,
2345 .ib_test = &cik_ib_test,
2346 .is_lockup = &cik_gfx_is_lockup,
2347 .vm_flush = &cik_vm_flush,
2348 .get_rptr = &cik_compute_ring_get_rptr,
2349 .get_wptr = &cik_compute_ring_get_wptr,
2350 .set_wptr = &cik_compute_ring_set_wptr,
2351 },
2352 [R600_RING_TYPE_DMA_INDEX] = {
2353 .ib_execute = &cik_sdma_ring_ib_execute,
2354 .ib_parse = &cik_ib_parse,
2355 .emit_fence = &cik_sdma_fence_ring_emit,
2356 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2357 .cs_parse = NULL,
2358 .ring_test = &cik_sdma_ring_test,
2359 .ib_test = &cik_sdma_ib_test,
2360 .is_lockup = &cik_sdma_is_lockup,
2361 .vm_flush = &cik_dma_vm_flush,
2362 .get_rptr = &radeon_ring_generic_get_rptr,
2363 .get_wptr = &radeon_ring_generic_get_wptr,
2364 .set_wptr = &radeon_ring_generic_set_wptr,
2365 },
2366 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2367 .ib_execute = &cik_sdma_ring_ib_execute,
2368 .ib_parse = &cik_ib_parse,
2369 .emit_fence = &cik_sdma_fence_ring_emit,
2370 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2371 .cs_parse = NULL,
2372 .ring_test = &cik_sdma_ring_test,
2373 .ib_test = &cik_sdma_ib_test,
2374 .is_lockup = &cik_sdma_is_lockup,
2375 .vm_flush = &cik_dma_vm_flush,
2376 .get_rptr = &radeon_ring_generic_get_rptr,
2377 .get_wptr = &radeon_ring_generic_get_wptr,
2378 .set_wptr = &radeon_ring_generic_set_wptr,
2379 },
2380 [R600_RING_TYPE_UVD_INDEX] = {
2381 .ib_execute = &r600_uvd_ib_execute,
2382 .emit_fence = &r600_uvd_fence_emit,
2383 .emit_semaphore = &cayman_uvd_semaphore_emit,
2384 .cs_parse = &radeon_uvd_cs_parse,
2385 .ring_test = &r600_uvd_ring_test,
2386 .ib_test = &r600_uvd_ib_test,
2387 .is_lockup = &radeon_ring_test_lockup,
2388 .get_rptr = &radeon_ring_generic_get_rptr,
2389 .get_wptr = &radeon_ring_generic_get_wptr,
2390 .set_wptr = &radeon_ring_generic_set_wptr,
2391 }
2392 },
2393 .irq = {
2394 .set = &cik_irq_set,
2395 .process = &cik_irq_process,
2396 },
2397 .display = {
2398 .bandwidth_update = &dce8_bandwidth_update,
2399 .get_vblank_counter = &evergreen_get_vblank_counter,
2400 .wait_for_vblank = &dce4_wait_for_vblank,
2401 },
2402 .copy = {
2403 .blit = NULL,
2404 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2405 .dma = &cik_copy_dma,
2406 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2407 .copy = &cik_copy_dma,
2408 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2409 },
2410 .surface = {
2411 .set_reg = r600_set_surface_reg,
2412 .clear_reg = r600_clear_surface_reg,
2413 },
2414 .hpd = {
2415 .init = &evergreen_hpd_init,
2416 .fini = &evergreen_hpd_fini,
2417 .sense = &evergreen_hpd_sense,
2418 .set_polarity = &evergreen_hpd_set_polarity,
2419 },
2420 .pm = {
2421 .misc = &evergreen_pm_misc,
2422 .prepare = &evergreen_pm_prepare,
2423 .finish = &evergreen_pm_finish,
2424 .init_profile = &sumo_pm_init_profile,
2425 .get_dynpm_state = &r600_pm_get_dynpm_state,
2426 .get_engine_clock = &radeon_atom_get_engine_clock,
2427 .set_engine_clock = &radeon_atom_set_engine_clock,
2428 .get_memory_clock = &radeon_atom_get_memory_clock,
2429 .set_memory_clock = &radeon_atom_set_memory_clock,
2430 .get_pcie_lanes = NULL,
2431 .set_pcie_lanes = NULL,
2432 .set_clock_gating = NULL,
2433 .set_uvd_clocks = &cik_set_uvd_clocks,
2434 },
2435 .pflip = {
2436 .pre_page_flip = &evergreen_pre_page_flip,
2437 .page_flip = &evergreen_page_flip,
2438 .post_page_flip = &evergreen_post_page_flip,
2439 },
2440};
2441
2442static struct radeon_asic kv_asic = {
2443 .init = &cik_init,
2444 .fini = &cik_fini,
2445 .suspend = &cik_suspend,
2446 .resume = &cik_resume,
2447 .asic_reset = &cik_asic_reset,
2448 .vga_set_state = &r600_vga_set_state,
2449 .ioctl_wait_idle = NULL,
2450 .gui_idle = &r600_gui_idle,
2451 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2452 .get_xclk = &cik_get_xclk,
2453 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2454 .gart = {
2455 .tlb_flush = &cik_pcie_gart_tlb_flush,
2456 .set_page = &rs600_gart_set_page,
2457 },
2458 .vm = {
2459 .init = &cik_vm_init,
2460 .fini = &cik_vm_fini,
2461 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2462 .set_page = &cik_vm_set_page,
2463 },
2464 .ring = {
2465 [RADEON_RING_TYPE_GFX_INDEX] = {
2466 .ib_execute = &cik_ring_ib_execute,
2467 .ib_parse = &cik_ib_parse,
2468 .emit_fence = &cik_fence_gfx_ring_emit,
2469 .emit_semaphore = &cik_semaphore_ring_emit,
2470 .cs_parse = NULL,
2471 .ring_test = &cik_ring_test,
2472 .ib_test = &cik_ib_test,
2473 .is_lockup = &cik_gfx_is_lockup,
2474 .vm_flush = &cik_vm_flush,
2475 .get_rptr = &radeon_ring_generic_get_rptr,
2476 .get_wptr = &radeon_ring_generic_get_wptr,
2477 .set_wptr = &radeon_ring_generic_set_wptr,
2478 },
2479 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2480 .ib_execute = &cik_ring_ib_execute,
2481 .ib_parse = &cik_ib_parse,
2482 .emit_fence = &cik_fence_compute_ring_emit,
2483 .emit_semaphore = &cik_semaphore_ring_emit,
2484 .cs_parse = NULL,
2485 .ring_test = &cik_ring_test,
2486 .ib_test = &cik_ib_test,
2487 .is_lockup = &cik_gfx_is_lockup,
2488 .vm_flush = &cik_vm_flush,
2489 .get_rptr = &cik_compute_ring_get_rptr,
2490 .get_wptr = &cik_compute_ring_get_wptr,
2491 .set_wptr = &cik_compute_ring_set_wptr,
2492 },
2493 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2494 .ib_execute = &cik_ring_ib_execute,
2495 .ib_parse = &cik_ib_parse,
2496 .emit_fence = &cik_fence_compute_ring_emit,
2497 .emit_semaphore = &cik_semaphore_ring_emit,
2498 .cs_parse = NULL,
2499 .ring_test = &cik_ring_test,
2500 .ib_test = &cik_ib_test,
2501 .is_lockup = &cik_gfx_is_lockup,
2502 .vm_flush = &cik_vm_flush,
2503 .get_rptr = &cik_compute_ring_get_rptr,
2504 .get_wptr = &cik_compute_ring_get_wptr,
2505 .set_wptr = &cik_compute_ring_set_wptr,
2506 },
2507 [R600_RING_TYPE_DMA_INDEX] = {
2508 .ib_execute = &cik_sdma_ring_ib_execute,
2509 .ib_parse = &cik_ib_parse,
2510 .emit_fence = &cik_sdma_fence_ring_emit,
2511 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2512 .cs_parse = NULL,
2513 .ring_test = &cik_sdma_ring_test,
2514 .ib_test = &cik_sdma_ib_test,
2515 .is_lockup = &cik_sdma_is_lockup,
2516 .vm_flush = &cik_dma_vm_flush,
2517 .get_rptr = &radeon_ring_generic_get_rptr,
2518 .get_wptr = &radeon_ring_generic_get_wptr,
2519 .set_wptr = &radeon_ring_generic_set_wptr,
2520 },
2521 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2522 .ib_execute = &cik_sdma_ring_ib_execute,
2523 .ib_parse = &cik_ib_parse,
2524 .emit_fence = &cik_sdma_fence_ring_emit,
2525 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2526 .cs_parse = NULL,
2527 .ring_test = &cik_sdma_ring_test,
2528 .ib_test = &cik_sdma_ib_test,
2529 .is_lockup = &cik_sdma_is_lockup,
2530 .vm_flush = &cik_dma_vm_flush,
2531 .get_rptr = &radeon_ring_generic_get_rptr,
2532 .get_wptr = &radeon_ring_generic_get_wptr,
2533 .set_wptr = &radeon_ring_generic_set_wptr,
2534 },
2535 [R600_RING_TYPE_UVD_INDEX] = {
2536 .ib_execute = &r600_uvd_ib_execute,
2537 .emit_fence = &r600_uvd_fence_emit,
2538 .emit_semaphore = &cayman_uvd_semaphore_emit,
2539 .cs_parse = &radeon_uvd_cs_parse,
2540 .ring_test = &r600_uvd_ring_test,
2541 .ib_test = &r600_uvd_ib_test,
2542 .is_lockup = &radeon_ring_test_lockup,
2543 .get_rptr = &radeon_ring_generic_get_rptr,
2544 .get_wptr = &radeon_ring_generic_get_wptr,
2545 .set_wptr = &radeon_ring_generic_set_wptr,
2546 }
2547 },
2548 .irq = {
2549 .set = &cik_irq_set,
2550 .process = &cik_irq_process,
2551 },
2552 .display = {
2553 .bandwidth_update = &dce8_bandwidth_update,
2554 .get_vblank_counter = &evergreen_get_vblank_counter,
2555 .wait_for_vblank = &dce4_wait_for_vblank,
2556 },
2557 .copy = {
2558 .blit = NULL,
2559 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2560 .dma = &cik_copy_dma,
2561 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2562 .copy = &cik_copy_dma,
2563 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2564 },
2565 .surface = {
2566 .set_reg = r600_set_surface_reg,
2567 .clear_reg = r600_clear_surface_reg,
2568 },
2569 .hpd = {
2570 .init = &evergreen_hpd_init,
2571 .fini = &evergreen_hpd_fini,
2572 .sense = &evergreen_hpd_sense,
2573 .set_polarity = &evergreen_hpd_set_polarity,
2574 },
2575 .pm = {
2576 .misc = &evergreen_pm_misc,
2577 .prepare = &evergreen_pm_prepare,
2578 .finish = &evergreen_pm_finish,
2579 .init_profile = &sumo_pm_init_profile,
2580 .get_dynpm_state = &r600_pm_get_dynpm_state,
2581 .get_engine_clock = &radeon_atom_get_engine_clock,
2582 .set_engine_clock = &radeon_atom_set_engine_clock,
2583 .get_memory_clock = &radeon_atom_get_memory_clock,
2584 .set_memory_clock = &radeon_atom_set_memory_clock,
2585 .get_pcie_lanes = NULL,
2586 .set_pcie_lanes = NULL,
2587 .set_clock_gating = NULL,
2588 .set_uvd_clocks = &cik_set_uvd_clocks,
2589 },
2590 .pflip = {
2591 .pre_page_flip = &evergreen_pre_page_flip,
2592 .page_flip = &evergreen_page_flip,
2593 .post_page_flip = &evergreen_post_page_flip,
2594 },
2595};
2596
abf1dc67
AD		 2597/**
2598 * radeon_asic_init - register asic specific callbacks
2599 *
2600 * @rdev: radeon device pointer
2601 *
2602 * Registers the appropriate asic specific callbacks for each
2603 * chip family. Also sets other asics specific info like the number
2604 * of crtcs and the register aperture accessors (all asics).
2605 * Returns 0 for success.
2606 */
0a10c851
DV		 2607int radeon_asic_init(struct radeon_device *rdev)
2608{
2609 radeon_register_accessor_init(rdev);
ba7e05e9
AD		 2610
2611 /* set the number of crtcs */
2612 if (rdev->flags & RADEON_SINGLE_CRTC)
2613 rdev->num_crtc = 1;
2614 else
2615 rdev->num_crtc = 2;
2616
948bee3f
AD		 2617 rdev->has_uvd = false;
2618
0a10c851
DV		 2619 switch (rdev->family) {
2620 case CHIP_R100:
2621 case CHIP_RV100:
2622 case CHIP_RS100:
2623 case CHIP_RV200:
2624 case CHIP_RS200:
2625 rdev->asic = &r100_asic;
2626 break;
2627 case CHIP_R200:
2628 case CHIP_RV250:
2629 case CHIP_RS300:
2630 case CHIP_RV280:
2631 rdev->asic = &r200_asic;
2632 break;
2633 case CHIP_R300:
2634 case CHIP_R350:
2635 case CHIP_RV350:
2636 case CHIP_RV380:
2637 if (rdev->flags & RADEON_IS_PCIE)
2638 rdev->asic = &r300_asic_pcie;
2639 else
2640 rdev->asic = &r300_asic;
2641 break;
2642 case CHIP_R420:
2643 case CHIP_R423:
2644 case CHIP_RV410:
2645 rdev->asic = &r420_asic;
07bb084c
AD		 2646 /* handle macs */
2647 if (rdev->bios == NULL) {
798bcf73
AD		 2648 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2649 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2650 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2651 rdev->asic->pm.set_memory_clock = NULL;
37e9b6a6 2652 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
07bb084c 2653 }
0a10c851
DV		 2654 break;
2655 case CHIP_RS400:
2656 case CHIP_RS480:
2657 rdev->asic = &rs400_asic;
2658 break;
2659 case CHIP_RS600:
2660 rdev->asic = &rs600_asic;
2661 break;
2662 case CHIP_RS690:
2663 case CHIP_RS740:
2664 rdev->asic = &rs690_asic;
2665 break;
2666 case CHIP_RV515:
2667 rdev->asic = &rv515_asic;
2668 break;
2669 case CHIP_R520:
2670 case CHIP_RV530:
2671 case CHIP_RV560:
2672 case CHIP_RV570:
2673 case CHIP_R580:
2674 rdev->asic = &r520_asic;
2675 break;
2676 case CHIP_R600:
ca361b65
AD		 2677 rdev->asic = &r600_asic;
2678 break;
0a10c851
DV		 2679 case CHIP_RV610:
2680 case CHIP_RV630:
2681 case CHIP_RV620:
2682 case CHIP_RV635:
2683 case CHIP_RV670:
ca361b65
AD		 2684 rdev->asic = &rv6xx_asic;
2685 rdev->has_uvd = true;
f47299c5 2686 break;
0a10c851
DV		 2687 case CHIP_RS780:
2688 case CHIP_RS880:
f47299c5 2689 rdev->asic = &rs780_asic;
948bee3f 2690 rdev->has_uvd = true;
0a10c851
DV		 2691 break;
2692 case CHIP_RV770:
2693 case CHIP_RV730:
2694 case CHIP_RV710:
2695 case CHIP_RV740:
2696 rdev->asic = &rv770_asic;
948bee3f 2697 rdev->has_uvd = true;
0a10c851
DV		 2698 break;
2699 case CHIP_CEDAR:
2700 case CHIP_REDWOOD:
2701 case CHIP_JUNIPER:
2702 case CHIP_CYPRESS:
2703 case CHIP_HEMLOCK:
ba7e05e9
AD		 2704 /* set num crtcs */
2705 if (rdev->family == CHIP_CEDAR)
2706 rdev->num_crtc = 4;
2707 else
2708 rdev->num_crtc = 6;
0a10c851 2709 rdev->asic = &evergreen_asic;
948bee3f 2710 rdev->has_uvd = true;
0a10c851 2711 break;
958261d1 2712 case CHIP_PALM:
89da5a37
AD		 2713 case CHIP_SUMO:
2714 case CHIP_SUMO2:
958261d1 2715 rdev->asic = &sumo_asic;
948bee3f 2716 rdev->has_uvd = true;
958261d1 2717 break;
a43b7665
AD		 2718 case CHIP_BARTS:
2719 case CHIP_TURKS:
2720 case CHIP_CAICOS:
ba7e05e9
AD		 2721 /* set num crtcs */
2722 if (rdev->family == CHIP_CAICOS)
2723 rdev->num_crtc = 4;
2724 else
2725 rdev->num_crtc = 6;
a43b7665 2726 rdev->asic = &btc_asic;
948bee3f 2727 rdev->has_uvd = true;
a43b7665 2728 break;
e3487629
AD		 2729 case CHIP_CAYMAN:
2730 rdev->asic = &cayman_asic;
ba7e05e9
AD		 2731 /* set num crtcs */
2732 rdev->num_crtc = 6;
948bee3f 2733 rdev->has_uvd = true;
e3487629 2734 break;
be63fe8c
AD		 2735 case CHIP_ARUBA:
2736 rdev->asic = &trinity_asic;
2737 /* set num crtcs */
2738 rdev->num_crtc = 4;
948bee3f 2739 rdev->has_uvd = true;
be63fe8c 2740 break;
02779c08
AD		 2741 case CHIP_TAHITI:
2742 case CHIP_PITCAIRN:
2743 case CHIP_VERDE:
e737a14c 2744 case CHIP_OLAND:
86a45cac 2745 case CHIP_HAINAN:
02779c08
AD		 2746 rdev->asic = &si_asic;
2747 /* set num crtcs */
86a45cac
AD		 2748 if (rdev->family == CHIP_HAINAN)
2749 rdev->num_crtc = 0;
2750 else if (rdev->family == CHIP_OLAND)
e737a14c
AD		 2751 rdev->num_crtc = 2;
2752 else
2753 rdev->num_crtc = 6;
948bee3f
AD		 2754 if (rdev->family == CHIP_HAINAN)
2755 rdev->has_uvd = false;
2756 else
2757 rdev->has_uvd = true;
02779c08 2758 break;
0672e27b
AD		 2759 case CHIP_BONAIRE:
2760 rdev->asic = &ci_asic;
2761 rdev->num_crtc = 6;
2762 break;
2763 case CHIP_KAVERI:
2764 case CHIP_KABINI:
2765 rdev->asic = &kv_asic;
2766 /* set num crtcs */
2767 if (rdev->family == CHIP_KAVERI)
2768 rdev->num_crtc = 4;
2769 else
2770 rdev->num_crtc = 2;
2771 break;
0a10c851
DV		 2772 default:
2773 /* FIXME: not supported yet */
2774 return -EINVAL;
2775 }
2776
2777 if (rdev->flags & RADEON_IS_IGP) {
798bcf73
AD		 2778 rdev->asic->pm.get_memory_clock = NULL;
2779 rdev->asic->pm.set_memory_clock = NULL;
0a10c851
DV		 2780 }
2781
2782 return 0;
2783}
2784
Linux kernel - Deliverables
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