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drm/radeon: add si dpm quirk list
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_asic.c
CommitLineData
0a10c851
DV		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/console.h>
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
33#include <linux/vgaarb.h>
34#include <linux/vga_switcheroo.h>
35#include "radeon_reg.h"
36#include "radeon.h"
37#include "radeon_asic.h"
38#include "atom.h"
39
40/*
41 * Registers accessors functions.
42 */
abf1dc67
AD		 43/**
44 * radeon_invalid_rreg - dummy reg read function
45 *
46 * @rdev: radeon device pointer
47 * @reg: offset of register
48 *
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
52 */
0a10c851
DV		 53static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54{
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
56 BUG_ON(1);
57 return 0;
58}
59
abf1dc67
AD		 60/**
61 * radeon_invalid_wreg - dummy reg write function
62 *
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
66 *
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
69 */
0a10c851
DV		 70static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
71{
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
73 reg, v);
74 BUG_ON(1);
75}
76
abf1dc67
AD		 77/**
78 * radeon_register_accessor_init - sets up the register accessor callbacks
79 *
80 * @rdev: radeon device pointer
81 *
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
84 */
0a10c851
DV		 85static void radeon_register_accessor_init(struct radeon_device *rdev)
86{
87 rdev->mc_rreg = &radeon_invalid_rreg;
88 rdev->mc_wreg = &radeon_invalid_wreg;
89 rdev->pll_rreg = &radeon_invalid_rreg;
90 rdev->pll_wreg = &radeon_invalid_wreg;
91 rdev->pciep_rreg = &radeon_invalid_rreg;
92 rdev->pciep_wreg = &radeon_invalid_wreg;
93
94 /* Don't change order as we are overridding accessor. */
95 if (rdev->family < CHIP_RV515) {
96 rdev->pcie_reg_mask = 0xff;
97 } else {
98 rdev->pcie_reg_mask = 0x7ff;
99 }
100 /* FIXME: not sure here */
101 if (rdev->family <= CHIP_R580) {
102 rdev->pll_rreg = &r100_pll_rreg;
103 rdev->pll_wreg = &r100_pll_wreg;
104 }
105 if (rdev->family >= CHIP_R420) {
106 rdev->mc_rreg = &r420_mc_rreg;
107 rdev->mc_wreg = &r420_mc_wreg;
108 }
109 if (rdev->family >= CHIP_RV515) {
110 rdev->mc_rreg = &rv515_mc_rreg;
111 rdev->mc_wreg = &rv515_mc_wreg;
112 }
113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
114 rdev->mc_rreg = &rs400_mc_rreg;
115 rdev->mc_wreg = &rs400_mc_wreg;
116 }
117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
118 rdev->mc_rreg = &rs690_mc_rreg;
119 rdev->mc_wreg = &rs690_mc_wreg;
120 }
121 if (rdev->family == CHIP_RS600) {
122 rdev->mc_rreg = &rs600_mc_rreg;
123 rdev->mc_wreg = &rs600_mc_wreg;
124 }
65337e60
SL		 125 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
126 rdev->mc_rreg = &rs780_mc_rreg;
127 rdev->mc_wreg = &rs780_mc_wreg;
128 }
6e2c3c0a
AD		 129
130 if (rdev->family >= CHIP_BONAIRE) {
131 rdev->pciep_rreg = &cik_pciep_rreg;
132 rdev->pciep_wreg = &cik_pciep_wreg;
133 } else if (rdev->family >= CHIP_R600) {
0a10c851
DV		 134 rdev->pciep_rreg = &r600_pciep_rreg;
135 rdev->pciep_wreg = &r600_pciep_wreg;
136 }
137}
138
139
140/* helper to disable agp */
abf1dc67
AD		 141/**
142 * radeon_agp_disable - AGP disable helper function
143 *
144 * @rdev: radeon device pointer
145 *
146 * Removes AGP flags and changes the gart callbacks on AGP
147 * cards when using the internal gart rather than AGP (all asics).
148 */
0a10c851
DV		 149void radeon_agp_disable(struct radeon_device *rdev)
150{
151 rdev->flags &= ~RADEON_IS_AGP;
152 if (rdev->family >= CHIP_R600) {
153 DRM_INFO("Forcing AGP to PCIE mode\n");
154 rdev->flags |= RADEON_IS_PCIE;
155 } else if (rdev->family >= CHIP_RV515 ||
156 rdev->family == CHIP_RV380 ||
157 rdev->family == CHIP_RV410 ||
158 rdev->family == CHIP_R423) {
159 DRM_INFO("Forcing AGP to PCIE mode\n");
160 rdev->flags |= RADEON_IS_PCIE;
c5b3b850
AD		 161 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
162 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
0a10c851
DV		 163 } else {
164 DRM_INFO("Forcing AGP to PCI mode\n");
165 rdev->flags |= RADEON_IS_PCI;
c5b3b850
AD		 166 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
167 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
0a10c851
DV		 168 }
169 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
170}
171
172/*
173 * ASIC
174 */
76a0df85
CK		 175
176static struct radeon_asic_ring r100_gfx_ring = {
177 .ib_execute = &r100_ring_ib_execute,
178 .emit_fence = &r100_fence_ring_emit,
179 .emit_semaphore = &r100_semaphore_ring_emit,
180 .cs_parse = &r100_cs_parse,
181 .ring_start = &r100_ring_start,
182 .ring_test = &r100_ring_test,
183 .ib_test = &r100_ib_test,
184 .is_lockup = &r100_gpu_is_lockup,
ea31bf69
AD		 185 .get_rptr = &r100_gfx_get_rptr,
186 .get_wptr = &r100_gfx_get_wptr,
187 .set_wptr = &r100_gfx_set_wptr,
76a0df85
CK		 188};
189
48e7a5f1
DV		 190static struct radeon_asic r100_asic = {
191 .init = &r100_init,
192 .fini = &r100_fini,
193 .suspend = &r100_suspend,
194 .resume = &r100_resume,
195 .vga_set_state = &r100_vga_set_state,
a2d07b74 196 .asic_reset = &r100_asic_reset,
124764f1 197 .mmio_hdp_flush = NULL,
54e88e06
AD		 198 .gui_idle = &r100_gui_idle,
199 .mc_wait_for_idle = &r100_mc_wait_for_idle,
c5b3b850
AD		 200 .gart = {
201 .tlb_flush = &r100_pci_gart_tlb_flush,
202 .set_page = &r100_pci_gart_set_page,
203 },
4c87bc26 204 .ring = {
76a0df85 205 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
4c87bc26 206 },
b35ea4ab
AD		 207 .irq = {
208 .set = &r100_irq_set,
209 .process = &r100_irq_process,
210 },
c79a49ca
AD		 211 .display = {
212 .bandwidth_update = &r100_bandwidth_update,
213 .get_vblank_counter = &r100_get_vblank_counter,
214 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 215 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 216 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 217 },
27cd7769
AD		 218 .copy = {
219 .blit = &r100_copy_blit,
220 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
221 .dma = NULL,
222 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
223 .copy = &r100_copy_blit,
224 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
225 },
9e6f3d02
AD		 226 .surface = {
227 .set_reg = r100_set_surface_reg,
228 .clear_reg = r100_clear_surface_reg,
229 },
901ea57d
AD		 230 .hpd = {
231 .init = &r100_hpd_init,
232 .fini = &r100_hpd_fini,
233 .sense = &r100_hpd_sense,
234 .set_polarity = &r100_hpd_set_polarity,
235 },
a02fa397
AD		 236 .pm = {
237 .misc = &r100_pm_misc,
238 .prepare = &r100_pm_prepare,
239 .finish = &r100_pm_finish,
240 .init_profile = &r100_pm_init_profile,
241 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 242 .get_engine_clock = &radeon_legacy_get_engine_clock,
243 .set_engine_clock = &radeon_legacy_set_engine_clock,
244 .get_memory_clock = &radeon_legacy_get_memory_clock,
245 .set_memory_clock = NULL,
246 .get_pcie_lanes = NULL,
247 .set_pcie_lanes = NULL,
248 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 249 },
0f9e006c 250 .pflip = {
0f9e006c 251 .page_flip = &r100_page_flip,
157fa14d 252 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 253 },
48e7a5f1
DV		 254};
255
256static struct radeon_asic r200_asic = {
257 .init = &r100_init,
258 .fini = &r100_fini,
259 .suspend = &r100_suspend,
260 .resume = &r100_resume,
261 .vga_set_state = &r100_vga_set_state,
a2d07b74 262 .asic_reset = &r100_asic_reset,
124764f1 263 .mmio_hdp_flush = NULL,
54e88e06
AD		 264 .gui_idle = &r100_gui_idle,
265 .mc_wait_for_idle = &r100_mc_wait_for_idle,
c5b3b850
AD		 266 .gart = {
267 .tlb_flush = &r100_pci_gart_tlb_flush,
268 .set_page = &r100_pci_gart_set_page,
269 },
4c87bc26 270 .ring = {
76a0df85 271 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
4c87bc26 272 },
b35ea4ab
AD		 273 .irq = {
274 .set = &r100_irq_set,
275 .process = &r100_irq_process,
276 },
c79a49ca
AD		 277 .display = {
278 .bandwidth_update = &r100_bandwidth_update,
279 .get_vblank_counter = &r100_get_vblank_counter,
280 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 281 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 282 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 283 },
27cd7769
AD		 284 .copy = {
285 .blit = &r100_copy_blit,
286 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
287 .dma = &r200_copy_dma,
288 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
289 .copy = &r100_copy_blit,
290 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
291 },
9e6f3d02
AD		 292 .surface = {
293 .set_reg = r100_set_surface_reg,
294 .clear_reg = r100_clear_surface_reg,
295 },
901ea57d
AD		 296 .hpd = {
297 .init = &r100_hpd_init,
298 .fini = &r100_hpd_fini,
299 .sense = &r100_hpd_sense,
300 .set_polarity = &r100_hpd_set_polarity,
301 },
a02fa397
AD		 302 .pm = {
303 .misc = &r100_pm_misc,
304 .prepare = &r100_pm_prepare,
305 .finish = &r100_pm_finish,
306 .init_profile = &r100_pm_init_profile,
307 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 308 .get_engine_clock = &radeon_legacy_get_engine_clock,
309 .set_engine_clock = &radeon_legacy_set_engine_clock,
310 .get_memory_clock = &radeon_legacy_get_memory_clock,
311 .set_memory_clock = NULL,
312 .get_pcie_lanes = NULL,
313 .set_pcie_lanes = NULL,
314 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 315 },
0f9e006c 316 .pflip = {
0f9e006c 317 .page_flip = &r100_page_flip,
157fa14d 318 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 319 },
48e7a5f1
DV		 320};
321
76a0df85
CK		 322static struct radeon_asic_ring r300_gfx_ring = {
323 .ib_execute = &r100_ring_ib_execute,
324 .emit_fence = &r300_fence_ring_emit,
325 .emit_semaphore = &r100_semaphore_ring_emit,
326 .cs_parse = &r300_cs_parse,
327 .ring_start = &r300_ring_start,
328 .ring_test = &r100_ring_test,
329 .ib_test = &r100_ib_test,
330 .is_lockup = &r100_gpu_is_lockup,
ea31bf69
AD		 331 .get_rptr = &r100_gfx_get_rptr,
332 .get_wptr = &r100_gfx_get_wptr,
333 .set_wptr = &r100_gfx_set_wptr,
76a0df85
CK		 334};
335
48e7a5f1
DV		 336static struct radeon_asic r300_asic = {
337 .init = &r300_init,
338 .fini = &r300_fini,
339 .suspend = &r300_suspend,
340 .resume = &r300_resume,
341 .vga_set_state = &r100_vga_set_state,
a2d07b74 342 .asic_reset = &r300_asic_reset,
124764f1 343 .mmio_hdp_flush = NULL,
54e88e06
AD		 344 .gui_idle = &r100_gui_idle,
345 .mc_wait_for_idle = &r300_mc_wait_for_idle,
c5b3b850
AD		 346 .gart = {
347 .tlb_flush = &r100_pci_gart_tlb_flush,
348 .set_page = &r100_pci_gart_set_page,
349 },
4c87bc26 350 .ring = {
76a0df85 351 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 352 },
b35ea4ab
AD		 353 .irq = {
354 .set = &r100_irq_set,
355 .process = &r100_irq_process,
356 },
c79a49ca
AD		 357 .display = {
358 .bandwidth_update = &r100_bandwidth_update,
359 .get_vblank_counter = &r100_get_vblank_counter,
360 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 361 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 362 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 363 },
27cd7769
AD		 364 .copy = {
365 .blit = &r100_copy_blit,
366 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
367 .dma = &r200_copy_dma,
368 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
369 .copy = &r100_copy_blit,
370 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
371 },
9e6f3d02
AD		 372 .surface = {
373 .set_reg = r100_set_surface_reg,
374 .clear_reg = r100_clear_surface_reg,
375 },
901ea57d
AD		 376 .hpd = {
377 .init = &r100_hpd_init,
378 .fini = &r100_hpd_fini,
379 .sense = &r100_hpd_sense,
380 .set_polarity = &r100_hpd_set_polarity,
381 },
a02fa397
AD		 382 .pm = {
383 .misc = &r100_pm_misc,
384 .prepare = &r100_pm_prepare,
385 .finish = &r100_pm_finish,
386 .init_profile = &r100_pm_init_profile,
387 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 388 .get_engine_clock = &radeon_legacy_get_engine_clock,
389 .set_engine_clock = &radeon_legacy_set_engine_clock,
390 .get_memory_clock = &radeon_legacy_get_memory_clock,
391 .set_memory_clock = NULL,
392 .get_pcie_lanes = &rv370_get_pcie_lanes,
393 .set_pcie_lanes = &rv370_set_pcie_lanes,
394 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 395 },
0f9e006c 396 .pflip = {
0f9e006c 397 .page_flip = &r100_page_flip,
157fa14d 398 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 399 },
48e7a5f1
DV		 400};
401
402static struct radeon_asic r300_asic_pcie = {
403 .init = &r300_init,
404 .fini = &r300_fini,
405 .suspend = &r300_suspend,
406 .resume = &r300_resume,
407 .vga_set_state = &r100_vga_set_state,
a2d07b74 408 .asic_reset = &r300_asic_reset,
124764f1 409 .mmio_hdp_flush = NULL,
54e88e06
AD		 410 .gui_idle = &r100_gui_idle,
411 .mc_wait_for_idle = &r300_mc_wait_for_idle,
c5b3b850
AD		 412 .gart = {
413 .tlb_flush = &rv370_pcie_gart_tlb_flush,
414 .set_page = &rv370_pcie_gart_set_page,
415 },
4c87bc26 416 .ring = {
76a0df85 417 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 418 },
b35ea4ab
AD		 419 .irq = {
420 .set = &r100_irq_set,
421 .process = &r100_irq_process,
422 },
c79a49ca
AD		 423 .display = {
424 .bandwidth_update = &r100_bandwidth_update,
425 .get_vblank_counter = &r100_get_vblank_counter,
426 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 427 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 428 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 429 },
27cd7769
AD		 430 .copy = {
431 .blit = &r100_copy_blit,
432 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
433 .dma = &r200_copy_dma,
434 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
435 .copy = &r100_copy_blit,
436 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
437 },
9e6f3d02
AD		 438 .surface = {
439 .set_reg = r100_set_surface_reg,
440 .clear_reg = r100_clear_surface_reg,
441 },
901ea57d
AD		 442 .hpd = {
443 .init = &r100_hpd_init,
444 .fini = &r100_hpd_fini,
445 .sense = &r100_hpd_sense,
446 .set_polarity = &r100_hpd_set_polarity,
447 },
a02fa397
AD		 448 .pm = {
449 .misc = &r100_pm_misc,
450 .prepare = &r100_pm_prepare,
451 .finish = &r100_pm_finish,
452 .init_profile = &r100_pm_init_profile,
453 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 454 .get_engine_clock = &radeon_legacy_get_engine_clock,
455 .set_engine_clock = &radeon_legacy_set_engine_clock,
456 .get_memory_clock = &radeon_legacy_get_memory_clock,
457 .set_memory_clock = NULL,
458 .get_pcie_lanes = &rv370_get_pcie_lanes,
459 .set_pcie_lanes = &rv370_set_pcie_lanes,
460 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 461 },
0f9e006c 462 .pflip = {
0f9e006c 463 .page_flip = &r100_page_flip,
157fa14d 464 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 465 },
48e7a5f1
DV		 466};
467
468static struct radeon_asic r420_asic = {
469 .init = &r420_init,
470 .fini = &r420_fini,
471 .suspend = &r420_suspend,
472 .resume = &r420_resume,
473 .vga_set_state = &r100_vga_set_state,
a2d07b74 474 .asic_reset = &r300_asic_reset,
124764f1 475 .mmio_hdp_flush = NULL,
54e88e06
AD		 476 .gui_idle = &r100_gui_idle,
477 .mc_wait_for_idle = &r300_mc_wait_for_idle,
c5b3b850
AD		 478 .gart = {
479 .tlb_flush = &rv370_pcie_gart_tlb_flush,
480 .set_page = &rv370_pcie_gart_set_page,
481 },
4c87bc26 482 .ring = {
76a0df85 483 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 484 },
b35ea4ab
AD		 485 .irq = {
486 .set = &r100_irq_set,
487 .process = &r100_irq_process,
488 },
c79a49ca
AD		 489 .display = {
490 .bandwidth_update = &r100_bandwidth_update,
491 .get_vblank_counter = &r100_get_vblank_counter,
492 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 493 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 494 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 495 },
27cd7769
AD		 496 .copy = {
497 .blit = &r100_copy_blit,
498 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
499 .dma = &r200_copy_dma,
500 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
501 .copy = &r100_copy_blit,
502 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
503 },
9e6f3d02
AD		 504 .surface = {
505 .set_reg = r100_set_surface_reg,
506 .clear_reg = r100_clear_surface_reg,
507 },
901ea57d
AD		 508 .hpd = {
509 .init = &r100_hpd_init,
510 .fini = &r100_hpd_fini,
511 .sense = &r100_hpd_sense,
512 .set_polarity = &r100_hpd_set_polarity,
513 },
a02fa397
AD		 514 .pm = {
515 .misc = &r100_pm_misc,
516 .prepare = &r100_pm_prepare,
517 .finish = &r100_pm_finish,
518 .init_profile = &r420_pm_init_profile,
519 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 520 .get_engine_clock = &radeon_atom_get_engine_clock,
521 .set_engine_clock = &radeon_atom_set_engine_clock,
522 .get_memory_clock = &radeon_atom_get_memory_clock,
523 .set_memory_clock = &radeon_atom_set_memory_clock,
524 .get_pcie_lanes = &rv370_get_pcie_lanes,
525 .set_pcie_lanes = &rv370_set_pcie_lanes,
526 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 527 },
0f9e006c 528 .pflip = {
0f9e006c 529 .page_flip = &r100_page_flip,
157fa14d 530 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 531 },
48e7a5f1
DV		 532};
533
534static struct radeon_asic rs400_asic = {
535 .init = &rs400_init,
536 .fini = &rs400_fini,
537 .suspend = &rs400_suspend,
538 .resume = &rs400_resume,
539 .vga_set_state = &r100_vga_set_state,
a2d07b74 540 .asic_reset = &r300_asic_reset,
124764f1 541 .mmio_hdp_flush = NULL,
54e88e06
AD		 542 .gui_idle = &r100_gui_idle,
543 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
c5b3b850
AD		 544 .gart = {
545 .tlb_flush = &rs400_gart_tlb_flush,
546 .set_page = &rs400_gart_set_page,
547 },
4c87bc26 548 .ring = {
76a0df85 549 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 550 },
b35ea4ab
AD		 551 .irq = {
552 .set = &r100_irq_set,
553 .process = &r100_irq_process,
554 },
c79a49ca
AD		 555 .display = {
556 .bandwidth_update = &r100_bandwidth_update,
557 .get_vblank_counter = &r100_get_vblank_counter,
558 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 559 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 560 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 561 },
27cd7769
AD		 562 .copy = {
563 .blit = &r100_copy_blit,
564 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
565 .dma = &r200_copy_dma,
566 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
567 .copy = &r100_copy_blit,
568 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
569 },
9e6f3d02
AD		 570 .surface = {
571 .set_reg = r100_set_surface_reg,
572 .clear_reg = r100_clear_surface_reg,
573 },
901ea57d
AD		 574 .hpd = {
575 .init = &r100_hpd_init,
576 .fini = &r100_hpd_fini,
577 .sense = &r100_hpd_sense,
578 .set_polarity = &r100_hpd_set_polarity,
579 },
a02fa397
AD		 580 .pm = {
581 .misc = &r100_pm_misc,
582 .prepare = &r100_pm_prepare,
583 .finish = &r100_pm_finish,
584 .init_profile = &r100_pm_init_profile,
585 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 586 .get_engine_clock = &radeon_legacy_get_engine_clock,
587 .set_engine_clock = &radeon_legacy_set_engine_clock,
588 .get_memory_clock = &radeon_legacy_get_memory_clock,
589 .set_memory_clock = NULL,
590 .get_pcie_lanes = NULL,
591 .set_pcie_lanes = NULL,
592 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 593 },
0f9e006c 594 .pflip = {
0f9e006c 595 .page_flip = &r100_page_flip,
157fa14d 596 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 597 },
48e7a5f1
DV		 598};
599
600static struct radeon_asic rs600_asic = {
601 .init = &rs600_init,
602 .fini = &rs600_fini,
603 .suspend = &rs600_suspend,
604 .resume = &rs600_resume,
605 .vga_set_state = &r100_vga_set_state,
90aca4d2 606 .asic_reset = &rs600_asic_reset,
124764f1 607 .mmio_hdp_flush = NULL,
54e88e06
AD		 608 .gui_idle = &r100_gui_idle,
609 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
c5b3b850
AD		 610 .gart = {
611 .tlb_flush = &rs600_gart_tlb_flush,
612 .set_page = &rs600_gart_set_page,
613 },
4c87bc26 614 .ring = {
76a0df85 615 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 616 },
b35ea4ab
AD		 617 .irq = {
618 .set = &rs600_irq_set,
619 .process = &rs600_irq_process,
620 },
c79a49ca
AD		 621 .display = {
622 .bandwidth_update = &rs600_bandwidth_update,
623 .get_vblank_counter = &rs600_get_vblank_counter,
624 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 625 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 626 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 627 .hdmi_enable = &r600_hdmi_enable,
628 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 629 },
27cd7769
AD		 630 .copy = {
631 .blit = &r100_copy_blit,
632 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
633 .dma = &r200_copy_dma,
634 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
635 .copy = &r100_copy_blit,
636 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
637 },
9e6f3d02
AD		 638 .surface = {
639 .set_reg = r100_set_surface_reg,
640 .clear_reg = r100_clear_surface_reg,
641 },
901ea57d
AD		 642 .hpd = {
643 .init = &rs600_hpd_init,
644 .fini = &rs600_hpd_fini,
645 .sense = &rs600_hpd_sense,
646 .set_polarity = &rs600_hpd_set_polarity,
647 },
a02fa397
AD		 648 .pm = {
649 .misc = &rs600_pm_misc,
650 .prepare = &rs600_pm_prepare,
651 .finish = &rs600_pm_finish,
652 .init_profile = &r420_pm_init_profile,
653 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 654 .get_engine_clock = &radeon_atom_get_engine_clock,
655 .set_engine_clock = &radeon_atom_set_engine_clock,
656 .get_memory_clock = &radeon_atom_get_memory_clock,
657 .set_memory_clock = &radeon_atom_set_memory_clock,
658 .get_pcie_lanes = NULL,
659 .set_pcie_lanes = NULL,
660 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 661 },
0f9e006c 662 .pflip = {
0f9e006c 663 .page_flip = &rs600_page_flip,
157fa14d 664 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 665 },
48e7a5f1
DV		 666};
667
668static struct radeon_asic rs690_asic = {
669 .init = &rs690_init,
670 .fini = &rs690_fini,
671 .suspend = &rs690_suspend,
672 .resume = &rs690_resume,
673 .vga_set_state = &r100_vga_set_state,
90aca4d2 674 .asic_reset = &rs600_asic_reset,
124764f1 675 .mmio_hdp_flush = NULL,
54e88e06
AD		 676 .gui_idle = &r100_gui_idle,
677 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
c5b3b850
AD		 678 .gart = {
679 .tlb_flush = &rs400_gart_tlb_flush,
680 .set_page = &rs400_gart_set_page,
681 },
4c87bc26 682 .ring = {
76a0df85 683 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 684 },
b35ea4ab
AD		 685 .irq = {
686 .set = &rs600_irq_set,
687 .process = &rs600_irq_process,
688 },
c79a49ca
AD		 689 .display = {
690 .get_vblank_counter = &rs600_get_vblank_counter,
691 .bandwidth_update = &rs690_bandwidth_update,
692 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 693 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 694 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 695 .hdmi_enable = &r600_hdmi_enable,
696 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 697 },
27cd7769
AD		 698 .copy = {
699 .blit = &r100_copy_blit,
700 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
701 .dma = &r200_copy_dma,
702 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
703 .copy = &r200_copy_dma,
704 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
705 },
9e6f3d02
AD		 706 .surface = {
707 .set_reg = r100_set_surface_reg,
708 .clear_reg = r100_clear_surface_reg,
709 },
901ea57d
AD		 710 .hpd = {
711 .init = &rs600_hpd_init,
712 .fini = &rs600_hpd_fini,
713 .sense = &rs600_hpd_sense,
714 .set_polarity = &rs600_hpd_set_polarity,
715 },
a02fa397
AD		 716 .pm = {
717 .misc = &rs600_pm_misc,
718 .prepare = &rs600_pm_prepare,
719 .finish = &rs600_pm_finish,
720 .init_profile = &r420_pm_init_profile,
721 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 722 .get_engine_clock = &radeon_atom_get_engine_clock,
723 .set_engine_clock = &radeon_atom_set_engine_clock,
724 .get_memory_clock = &radeon_atom_get_memory_clock,
725 .set_memory_clock = &radeon_atom_set_memory_clock,
726 .get_pcie_lanes = NULL,
727 .set_pcie_lanes = NULL,
728 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 729 },
0f9e006c 730 .pflip = {
0f9e006c 731 .page_flip = &rs600_page_flip,
157fa14d 732 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 733 },
48e7a5f1
DV		 734};
735
736static struct radeon_asic rv515_asic = {
737 .init = &rv515_init,
738 .fini = &rv515_fini,
739 .suspend = &rv515_suspend,
740 .resume = &rv515_resume,
741 .vga_set_state = &r100_vga_set_state,
90aca4d2 742 .asic_reset = &rs600_asic_reset,
124764f1 743 .mmio_hdp_flush = NULL,
54e88e06
AD		 744 .gui_idle = &r100_gui_idle,
745 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
c5b3b850
AD		 746 .gart = {
747 .tlb_flush = &rv370_pcie_gart_tlb_flush,
748 .set_page = &rv370_pcie_gart_set_page,
749 },
4c87bc26 750 .ring = {
76a0df85 751 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 752 },
b35ea4ab
AD		 753 .irq = {
754 .set = &rs600_irq_set,
755 .process = &rs600_irq_process,
756 },
c79a49ca
AD		 757 .display = {
758 .get_vblank_counter = &rs600_get_vblank_counter,
759 .bandwidth_update = &rv515_bandwidth_update,
760 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 761 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 762 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 763 },
27cd7769
AD		 764 .copy = {
765 .blit = &r100_copy_blit,
766 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
767 .dma = &r200_copy_dma,
768 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
769 .copy = &r100_copy_blit,
770 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
771 },
9e6f3d02
AD		 772 .surface = {
773 .set_reg = r100_set_surface_reg,
774 .clear_reg = r100_clear_surface_reg,
775 },
901ea57d
AD		 776 .hpd = {
777 .init = &rs600_hpd_init,
778 .fini = &rs600_hpd_fini,
779 .sense = &rs600_hpd_sense,
780 .set_polarity = &rs600_hpd_set_polarity,
781 },
a02fa397
AD		 782 .pm = {
783 .misc = &rs600_pm_misc,
784 .prepare = &rs600_pm_prepare,
785 .finish = &rs600_pm_finish,
786 .init_profile = &r420_pm_init_profile,
787 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 788 .get_engine_clock = &radeon_atom_get_engine_clock,
789 .set_engine_clock = &radeon_atom_set_engine_clock,
790 .get_memory_clock = &radeon_atom_get_memory_clock,
791 .set_memory_clock = &radeon_atom_set_memory_clock,
792 .get_pcie_lanes = &rv370_get_pcie_lanes,
793 .set_pcie_lanes = &rv370_set_pcie_lanes,
794 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 795 },
0f9e006c 796 .pflip = {
0f9e006c 797 .page_flip = &rs600_page_flip,
157fa14d 798 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 799 },
48e7a5f1
DV		 800};
801
802static struct radeon_asic r520_asic = {
803 .init = &r520_init,
804 .fini = &rv515_fini,
805 .suspend = &rv515_suspend,
806 .resume = &r520_resume,
807 .vga_set_state = &r100_vga_set_state,
90aca4d2 808 .asic_reset = &rs600_asic_reset,
124764f1 809 .mmio_hdp_flush = NULL,
54e88e06
AD		 810 .gui_idle = &r100_gui_idle,
811 .mc_wait_for_idle = &r520_mc_wait_for_idle,
c5b3b850
AD		 812 .gart = {
813 .tlb_flush = &rv370_pcie_gart_tlb_flush,
814 .set_page = &rv370_pcie_gart_set_page,
815 },
4c87bc26 816 .ring = {
76a0df85 817 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 818 },
b35ea4ab
AD		 819 .irq = {
820 .set = &rs600_irq_set,
821 .process = &rs600_irq_process,
822 },
c79a49ca
AD		 823 .display = {
824 .bandwidth_update = &rv515_bandwidth_update,
825 .get_vblank_counter = &rs600_get_vblank_counter,
826 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 827 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 828 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 829 },
27cd7769
AD		 830 .copy = {
831 .blit = &r100_copy_blit,
832 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
833 .dma = &r200_copy_dma,
834 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
835 .copy = &r100_copy_blit,
836 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
837 },
9e6f3d02
AD		 838 .surface = {
839 .set_reg = r100_set_surface_reg,
840 .clear_reg = r100_clear_surface_reg,
841 },
901ea57d
AD		 842 .hpd = {
843 .init = &rs600_hpd_init,
844 .fini = &rs600_hpd_fini,
845 .sense = &rs600_hpd_sense,
846 .set_polarity = &rs600_hpd_set_polarity,
847 },
a02fa397
AD		 848 .pm = {
849 .misc = &rs600_pm_misc,
850 .prepare = &rs600_pm_prepare,
851 .finish = &rs600_pm_finish,
852 .init_profile = &r420_pm_init_profile,
853 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 854 .get_engine_clock = &radeon_atom_get_engine_clock,
855 .set_engine_clock = &radeon_atom_set_engine_clock,
856 .get_memory_clock = &radeon_atom_get_memory_clock,
857 .set_memory_clock = &radeon_atom_set_memory_clock,
858 .get_pcie_lanes = &rv370_get_pcie_lanes,
859 .set_pcie_lanes = &rv370_set_pcie_lanes,
860 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 861 },
0f9e006c 862 .pflip = {
0f9e006c 863 .page_flip = &rs600_page_flip,
157fa14d 864 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 865 },
48e7a5f1
DV		 866};
867
76a0df85
CK		 868static struct radeon_asic_ring r600_gfx_ring = {
869 .ib_execute = &r600_ring_ib_execute,
870 .emit_fence = &r600_fence_ring_emit,
871 .emit_semaphore = &r600_semaphore_ring_emit,
872 .cs_parse = &r600_cs_parse,
873 .ring_test = &r600_ring_test,
874 .ib_test = &r600_ib_test,
875 .is_lockup = &r600_gfx_is_lockup,
ea31bf69
AD		 876 .get_rptr = &r600_gfx_get_rptr,
877 .get_wptr = &r600_gfx_get_wptr,
878 .set_wptr = &r600_gfx_set_wptr,
76a0df85
CK		 879};
880
881static struct radeon_asic_ring r600_dma_ring = {
882 .ib_execute = &r600_dma_ring_ib_execute,
883 .emit_fence = &r600_dma_fence_ring_emit,
884 .emit_semaphore = &r600_dma_semaphore_ring_emit,
885 .cs_parse = &r600_dma_cs_parse,
886 .ring_test = &r600_dma_ring_test,
887 .ib_test = &r600_dma_ib_test,
888 .is_lockup = &r600_dma_is_lockup,
2e1e6dad
CK		 889 .get_rptr = &r600_dma_get_rptr,
890 .get_wptr = &r600_dma_get_wptr,
891 .set_wptr = &r600_dma_set_wptr,
76a0df85
CK		 892};
893
48e7a5f1
DV		 894static struct radeon_asic r600_asic = {
895 .init = &r600_init,
896 .fini = &r600_fini,
897 .suspend = &r600_suspend,
898 .resume = &r600_resume,
48e7a5f1 899 .vga_set_state = &r600_vga_set_state,
a2d07b74 900 .asic_reset = &r600_asic_reset,
124764f1 901 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 902 .gui_idle = &r600_gui_idle,
903 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 904 .get_xclk = &r600_get_xclk,
d0418894 905 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 906 .gart = {
907 .tlb_flush = &r600_pcie_gart_tlb_flush,
908 .set_page = &rs600_gart_set_page,
909 },
4c87bc26 910 .ring = {
76a0df85
CK		 911 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
912 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
4c87bc26 913 },
b35ea4ab
AD		 914 .irq = {
915 .set = &r600_irq_set,
916 .process = &r600_irq_process,
917 },
c79a49ca
AD		 918 .display = {
919 .bandwidth_update = &rv515_bandwidth_update,
920 .get_vblank_counter = &rs600_get_vblank_counter,
921 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 922 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 923 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 924 .hdmi_enable = &r600_hdmi_enable,
925 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 926 },
27cd7769 927 .copy = {
8dddb993 928 .blit = &r600_copy_cpdma,
27cd7769 929 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
4d75658b
AD		 930 .dma = &r600_copy_dma,
931 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
bfea6a68 932 .copy = &r600_copy_cpdma,
aeea40cb 933 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
27cd7769 934 },
9e6f3d02
AD		 935 .surface = {
936 .set_reg = r600_set_surface_reg,
937 .clear_reg = r600_clear_surface_reg,
938 },
901ea57d
AD		 939 .hpd = {
940 .init = &r600_hpd_init,
941 .fini = &r600_hpd_fini,
942 .sense = &r600_hpd_sense,
943 .set_polarity = &r600_hpd_set_polarity,
944 },
a02fa397
AD		 945 .pm = {
946 .misc = &r600_pm_misc,
947 .prepare = &rs600_pm_prepare,
948 .finish = &rs600_pm_finish,
949 .init_profile = &r600_pm_init_profile,
950 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 951 .get_engine_clock = &radeon_atom_get_engine_clock,
952 .set_engine_clock = &radeon_atom_set_engine_clock,
953 .get_memory_clock = &radeon_atom_get_memory_clock,
954 .set_memory_clock = &radeon_atom_set_memory_clock,
955 .get_pcie_lanes = &r600_get_pcie_lanes,
956 .set_pcie_lanes = &r600_set_pcie_lanes,
957 .set_clock_gating = NULL,
6bd1c385 958 .get_temperature = &rv6xx_get_temp,
a02fa397 959 },
0f9e006c 960 .pflip = {
0f9e006c 961 .page_flip = &rs600_page_flip,
157fa14d 962 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 963 },
48e7a5f1
DV		 964};
965
856754c3
CK		 966static struct radeon_asic_ring rv6xx_uvd_ring = {
967 .ib_execute = &uvd_v1_0_ib_execute,
968 .emit_fence = &uvd_v1_0_fence_emit,
969 .emit_semaphore = &uvd_v1_0_semaphore_emit,
970 .cs_parse = &radeon_uvd_cs_parse,
971 .ring_test = &uvd_v1_0_ring_test,
972 .ib_test = &uvd_v1_0_ib_test,
973 .is_lockup = &radeon_ring_test_lockup,
974 .get_rptr = &uvd_v1_0_get_rptr,
975 .get_wptr = &uvd_v1_0_get_wptr,
976 .set_wptr = &uvd_v1_0_set_wptr,
977};
978
ca361b65
AD		 979static struct radeon_asic rv6xx_asic = {
980 .init = &r600_init,
981 .fini = &r600_fini,
982 .suspend = &r600_suspend,
983 .resume = &r600_resume,
984 .vga_set_state = &r600_vga_set_state,
985 .asic_reset = &r600_asic_reset,
124764f1 986 .mmio_hdp_flush = r600_mmio_hdp_flush,
ca361b65
AD		 987 .gui_idle = &r600_gui_idle,
988 .mc_wait_for_idle = &r600_mc_wait_for_idle,
989 .get_xclk = &r600_get_xclk,
990 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
991 .gart = {
992 .tlb_flush = &r600_pcie_gart_tlb_flush,
993 .set_page = &rs600_gart_set_page,
994 },
995 .ring = {
76a0df85
CK		 996 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
997 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
856754c3 998 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
ca361b65
AD		 999 },
1000 .irq = {
1001 .set = &r600_irq_set,
1002 .process = &r600_irq_process,
1003 },
1004 .display = {
1005 .bandwidth_update = &rv515_bandwidth_update,
1006 .get_vblank_counter = &rs600_get_vblank_counter,
1007 .wait_for_vblank = &avivo_wait_for_vblank,
1008 .set_backlight_level = &atombios_set_backlight_level,
1009 .get_backlight_level = &atombios_get_backlight_level,
99d79aa2
AD		 1010 .hdmi_enable = &r600_hdmi_enable,
1011 .hdmi_setmode = &r600_hdmi_setmode,
ca361b65
AD		 1012 },
1013 .copy = {
8dddb993 1014 .blit = &r600_copy_cpdma,
ca361b65
AD		 1015 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1016 .dma = &r600_copy_dma,
1017 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
bfea6a68 1018 .copy = &r600_copy_cpdma,
aeea40cb 1019 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
ca361b65
AD		 1020 },
1021 .surface = {
1022 .set_reg = r600_set_surface_reg,
1023 .clear_reg = r600_clear_surface_reg,
1024 },
1025 .hpd = {
1026 .init = &r600_hpd_init,
1027 .fini = &r600_hpd_fini,
1028 .sense = &r600_hpd_sense,
1029 .set_polarity = &r600_hpd_set_polarity,
1030 },
1031 .pm = {
1032 .misc = &r600_pm_misc,
1033 .prepare = &rs600_pm_prepare,
1034 .finish = &rs600_pm_finish,
1035 .init_profile = &r600_pm_init_profile,
1036 .get_dynpm_state = &r600_pm_get_dynpm_state,
1037 .get_engine_clock = &radeon_atom_get_engine_clock,
1038 .set_engine_clock = &radeon_atom_set_engine_clock,
1039 .get_memory_clock = &radeon_atom_get_memory_clock,
1040 .set_memory_clock = &radeon_atom_set_memory_clock,
1041 .get_pcie_lanes = &r600_get_pcie_lanes,
1042 .set_pcie_lanes = &r600_set_pcie_lanes,
1043 .set_clock_gating = NULL,
1044 .get_temperature = &rv6xx_get_temp,
1b9ba70a 1045 .set_uvd_clocks = &r600_set_uvd_clocks,
ca361b65 1046 },
4a6369e9
AD		 1047 .dpm = {
1048 .init = &rv6xx_dpm_init,
1049 .setup_asic = &rv6xx_setup_asic,
1050 .enable = &rv6xx_dpm_enable,
a4643ba3 1051 .late_enable = &r600_dpm_late_enable,
4a6369e9 1052 .disable = &rv6xx_dpm_disable,
98243917 1053 .pre_set_power_state = &r600_dpm_pre_set_power_state,
4a6369e9 1054 .set_power_state = &rv6xx_dpm_set_power_state,
98243917 1055 .post_set_power_state = &r600_dpm_post_set_power_state,
4a6369e9
AD		 1056 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1057 .fini = &rv6xx_dpm_fini,
1058 .get_sclk = &rv6xx_dpm_get_sclk,
1059 .get_mclk = &rv6xx_dpm_get_mclk,
1060 .print_power_state = &rv6xx_dpm_print_power_state,
242916a5 1061 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
f4f85a8c 1062 .force_performance_level = &rv6xx_dpm_force_performance_level,
4a6369e9 1063 },
ca361b65 1064 .pflip = {
ca361b65 1065 .page_flip = &rs600_page_flip,
157fa14d 1066 .page_flip_pending = &rs600_page_flip_pending,
ca361b65
AD		 1067 },
1068};
1069
f47299c5
AD		 1070static struct radeon_asic rs780_asic = {
1071 .init = &r600_init,
1072 .fini = &r600_fini,
1073 .suspend = &r600_suspend,
1074 .resume = &r600_resume,
f47299c5 1075 .vga_set_state = &r600_vga_set_state,
a2d07b74 1076 .asic_reset = &r600_asic_reset,
124764f1 1077 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1078 .gui_idle = &r600_gui_idle,
1079 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 1080 .get_xclk = &r600_get_xclk,
d0418894 1081 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1082 .gart = {
1083 .tlb_flush = &r600_pcie_gart_tlb_flush,
1084 .set_page = &rs600_gart_set_page,
1085 },
4c87bc26 1086 .ring = {
76a0df85
CK		 1087 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1088 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
856754c3 1089 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
4c87bc26 1090 },
b35ea4ab
AD		 1091 .irq = {
1092 .set = &r600_irq_set,
1093 .process = &r600_irq_process,
1094 },
c79a49ca
AD		 1095 .display = {
1096 .bandwidth_update = &rs690_bandwidth_update,
1097 .get_vblank_counter = &rs600_get_vblank_counter,
1098 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 1099 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1100 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1101 .hdmi_enable = &r600_hdmi_enable,
1102 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 1103 },
27cd7769 1104 .copy = {
8dddb993 1105 .blit = &r600_copy_cpdma,
27cd7769 1106 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
4d75658b
AD		 1107 .dma = &r600_copy_dma,
1108 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
bfea6a68 1109 .copy = &r600_copy_cpdma,
aeea40cb 1110 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
27cd7769 1111 },
9e6f3d02
AD		 1112 .surface = {
1113 .set_reg = r600_set_surface_reg,
1114 .clear_reg = r600_clear_surface_reg,
1115 },
901ea57d
AD		 1116 .hpd = {
1117 .init = &r600_hpd_init,
1118 .fini = &r600_hpd_fini,
1119 .sense = &r600_hpd_sense,
1120 .set_polarity = &r600_hpd_set_polarity,
1121 },
a02fa397
AD		 1122 .pm = {
1123 .misc = &r600_pm_misc,
1124 .prepare = &rs600_pm_prepare,
1125 .finish = &rs600_pm_finish,
1126 .init_profile = &rs780_pm_init_profile,
1127 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1128 .get_engine_clock = &radeon_atom_get_engine_clock,
1129 .set_engine_clock = &radeon_atom_set_engine_clock,
1130 .get_memory_clock = NULL,
1131 .set_memory_clock = NULL,
1132 .get_pcie_lanes = NULL,
1133 .set_pcie_lanes = NULL,
1134 .set_clock_gating = NULL,
6bd1c385 1135 .get_temperature = &rv6xx_get_temp,
1b9ba70a 1136 .set_uvd_clocks = &r600_set_uvd_clocks,
a02fa397 1137 },
9d67006e
AD		 1138 .dpm = {
1139 .init = &rs780_dpm_init,
1140 .setup_asic = &rs780_dpm_setup_asic,
1141 .enable = &rs780_dpm_enable,
a4643ba3 1142 .late_enable = &r600_dpm_late_enable,
9d67006e 1143 .disable = &rs780_dpm_disable,
98243917 1144 .pre_set_power_state = &r600_dpm_pre_set_power_state,
9d67006e 1145 .set_power_state = &rs780_dpm_set_power_state,
98243917 1146 .post_set_power_state = &r600_dpm_post_set_power_state,
9d67006e
AD		 1147 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1148 .fini = &rs780_dpm_fini,
1149 .get_sclk = &rs780_dpm_get_sclk,
1150 .get_mclk = &rs780_dpm_get_mclk,
1151 .print_power_state = &rs780_dpm_print_power_state,
444bddc4 1152 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
63580c3e 1153 .force_performance_level = &rs780_dpm_force_performance_level,
9d67006e 1154 },
0f9e006c 1155 .pflip = {
0f9e006c 1156 .page_flip = &rs600_page_flip,
157fa14d 1157 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 1158 },
f47299c5
AD		 1159};
1160
76a0df85 1161static struct radeon_asic_ring rv770_uvd_ring = {
e409b128
CK		 1162 .ib_execute = &uvd_v1_0_ib_execute,
1163 .emit_fence = &uvd_v2_2_fence_emit,
1164 .emit_semaphore = &uvd_v1_0_semaphore_emit,
76a0df85 1165 .cs_parse = &radeon_uvd_cs_parse,
e409b128
CK		 1166 .ring_test = &uvd_v1_0_ring_test,
1167 .ib_test = &uvd_v1_0_ib_test,
76a0df85 1168 .is_lockup = &radeon_ring_test_lockup,
e409b128
CK		 1169 .get_rptr = &uvd_v1_0_get_rptr,
1170 .get_wptr = &uvd_v1_0_get_wptr,
1171 .set_wptr = &uvd_v1_0_set_wptr,
76a0df85
CK		 1172};
1173
48e7a5f1
DV		 1174static struct radeon_asic rv770_asic = {
1175 .init = &rv770_init,
1176 .fini = &rv770_fini,
1177 .suspend = &rv770_suspend,
1178 .resume = &rv770_resume,
a2d07b74 1179 .asic_reset = &r600_asic_reset,
48e7a5f1 1180 .vga_set_state = &r600_vga_set_state,
124764f1 1181 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1182 .gui_idle = &r600_gui_idle,
1183 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 1184 .get_xclk = &rv770_get_xclk,
d0418894 1185 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1186 .gart = {
1187 .tlb_flush = &r600_pcie_gart_tlb_flush,
1188 .set_page = &rs600_gart_set_page,
1189 },
4c87bc26 1190 .ring = {
76a0df85
CK		 1191 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1192 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1193 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1194 },
b35ea4ab
AD		 1195 .irq = {
1196 .set = &r600_irq_set,
1197 .process = &r600_irq_process,
1198 },
c79a49ca
AD		 1199 .display = {
1200 .bandwidth_update = &rv515_bandwidth_update,
1201 .get_vblank_counter = &rs600_get_vblank_counter,
1202 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 1203 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1204 .get_backlight_level = &atombios_get_backlight_level,
a973bea1 1205 .hdmi_enable = &r600_hdmi_enable,
8f33a156 1206 .hdmi_setmode = &dce3_1_hdmi_setmode,
c79a49ca 1207 },
27cd7769 1208 .copy = {
8dddb993 1209 .blit = &r600_copy_cpdma,
27cd7769 1210 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
43fb7787 1211 .dma = &rv770_copy_dma,
4d75658b 1212 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
43fb7787 1213 .copy = &rv770_copy_dma,
2d6cc729 1214 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1215 },
9e6f3d02
AD		 1216 .surface = {
1217 .set_reg = r600_set_surface_reg,
1218 .clear_reg = r600_clear_surface_reg,
1219 },
901ea57d
AD		 1220 .hpd = {
1221 .init = &r600_hpd_init,
1222 .fini = &r600_hpd_fini,
1223 .sense = &r600_hpd_sense,
1224 .set_polarity = &r600_hpd_set_polarity,
1225 },
a02fa397
AD		 1226 .pm = {
1227 .misc = &rv770_pm_misc,
1228 .prepare = &rs600_pm_prepare,
1229 .finish = &rs600_pm_finish,
1230 .init_profile = &r600_pm_init_profile,
1231 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1232 .get_engine_clock = &radeon_atom_get_engine_clock,
1233 .set_engine_clock = &radeon_atom_set_engine_clock,
1234 .get_memory_clock = &radeon_atom_get_memory_clock,
1235 .set_memory_clock = &radeon_atom_set_memory_clock,
1236 .get_pcie_lanes = &r600_get_pcie_lanes,
1237 .set_pcie_lanes = &r600_set_pcie_lanes,
1238 .set_clock_gating = &radeon_atom_set_clock_gating,
ef0e6e65 1239 .set_uvd_clocks = &rv770_set_uvd_clocks,
6bd1c385 1240 .get_temperature = &rv770_get_temp,
a02fa397 1241 },
66229b20
AD		 1242 .dpm = {
1243 .init = &rv770_dpm_init,
1244 .setup_asic = &rv770_dpm_setup_asic,
1245 .enable = &rv770_dpm_enable,
a3f11245 1246 .late_enable = &rv770_dpm_late_enable,
66229b20 1247 .disable = &rv770_dpm_disable,
98243917 1248 .pre_set_power_state = &r600_dpm_pre_set_power_state,
66229b20 1249 .set_power_state = &rv770_dpm_set_power_state,
98243917 1250 .post_set_power_state = &r600_dpm_post_set_power_state,
66229b20
AD		 1251 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1252 .fini = &rv770_dpm_fini,
1253 .get_sclk = &rv770_dpm_get_sclk,
1254 .get_mclk = &rv770_dpm_get_mclk,
1255 .print_power_state = &rv770_dpm_print_power_state,
bd210d11 1256 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
8b5e6b7f 1257 .force_performance_level = &rv770_dpm_force_performance_level,
b06195d9 1258 .vblank_too_short = &rv770_dpm_vblank_too_short,
66229b20 1259 },
0f9e006c 1260 .pflip = {
0f9e006c 1261 .page_flip = &rv770_page_flip,
157fa14d 1262 .page_flip_pending = &rv770_page_flip_pending,
0f9e006c 1263 },
48e7a5f1
DV		 1264};
1265
76a0df85
CK		 1266static struct radeon_asic_ring evergreen_gfx_ring = {
1267 .ib_execute = &evergreen_ring_ib_execute,
1268 .emit_fence = &r600_fence_ring_emit,
1269 .emit_semaphore = &r600_semaphore_ring_emit,
1270 .cs_parse = &evergreen_cs_parse,
1271 .ring_test = &r600_ring_test,
1272 .ib_test = &r600_ib_test,
1273 .is_lockup = &evergreen_gfx_is_lockup,
ea31bf69
AD		 1274 .get_rptr = &r600_gfx_get_rptr,
1275 .get_wptr = &r600_gfx_get_wptr,
1276 .set_wptr = &r600_gfx_set_wptr,
76a0df85
CK		 1277};
1278
1279static struct radeon_asic_ring evergreen_dma_ring = {
1280 .ib_execute = &evergreen_dma_ring_ib_execute,
1281 .emit_fence = &evergreen_dma_fence_ring_emit,
1282 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1283 .cs_parse = &evergreen_dma_cs_parse,
1284 .ring_test = &r600_dma_ring_test,
1285 .ib_test = &r600_dma_ib_test,
1286 .is_lockup = &evergreen_dma_is_lockup,
2e1e6dad
CK		 1287 .get_rptr = &r600_dma_get_rptr,
1288 .get_wptr = &r600_dma_get_wptr,
1289 .set_wptr = &r600_dma_set_wptr,
76a0df85
CK		 1290};
1291
48e7a5f1
DV		 1292static struct radeon_asic evergreen_asic = {
1293 .init = &evergreen_init,
1294 .fini = &evergreen_fini,
1295 .suspend = &evergreen_suspend,
1296 .resume = &evergreen_resume,
a2d07b74 1297 .asic_reset = &evergreen_asic_reset,
48e7a5f1 1298 .vga_set_state = &r600_vga_set_state,
124764f1 1299 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1300 .gui_idle = &r600_gui_idle,
1301 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1302 .get_xclk = &rv770_get_xclk,
d0418894 1303 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1304 .gart = {
1305 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1306 .set_page = &rs600_gart_set_page,
1307 },
4c87bc26 1308 .ring = {
76a0df85
CK		 1309 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1310 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1311 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1312 },
b35ea4ab
AD		 1313 .irq = {
1314 .set = &evergreen_irq_set,
1315 .process = &evergreen_irq_process,
1316 },
c79a49ca
AD		 1317 .display = {
1318 .bandwidth_update = &evergreen_bandwidth_update,
1319 .get_vblank_counter = &evergreen_get_vblank_counter,
1320 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1321 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1322 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1323 .hdmi_enable = &evergreen_hdmi_enable,
1324 .hdmi_setmode = &evergreen_hdmi_setmode,
c79a49ca 1325 },
27cd7769 1326 .copy = {
8dddb993 1327 .blit = &r600_copy_cpdma,
27cd7769 1328 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1329 .dma = &evergreen_copy_dma,
1330 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1331 .copy = &evergreen_copy_dma,
1332 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1333 },
9e6f3d02
AD		 1334 .surface = {
1335 .set_reg = r600_set_surface_reg,
1336 .clear_reg = r600_clear_surface_reg,
1337 },
901ea57d
AD		 1338 .hpd = {
1339 .init = &evergreen_hpd_init,
1340 .fini = &evergreen_hpd_fini,
1341 .sense = &evergreen_hpd_sense,
1342 .set_polarity = &evergreen_hpd_set_polarity,
1343 },
a02fa397
AD		 1344 .pm = {
1345 .misc = &evergreen_pm_misc,
1346 .prepare = &evergreen_pm_prepare,
1347 .finish = &evergreen_pm_finish,
1348 .init_profile = &r600_pm_init_profile,
1349 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1350 .get_engine_clock = &radeon_atom_get_engine_clock,
1351 .set_engine_clock = &radeon_atom_set_engine_clock,
1352 .get_memory_clock = &radeon_atom_get_memory_clock,
1353 .set_memory_clock = &radeon_atom_set_memory_clock,
1354 .get_pcie_lanes = &r600_get_pcie_lanes,
1355 .set_pcie_lanes = &r600_set_pcie_lanes,
1356 .set_clock_gating = NULL,
a8b4925c 1357 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1358 .get_temperature = &evergreen_get_temp,
a02fa397 1359 },
dc50ba7f
AD		 1360 .dpm = {
1361 .init = &cypress_dpm_init,
1362 .setup_asic = &cypress_dpm_setup_asic,
1363 .enable = &cypress_dpm_enable,
a3f11245 1364 .late_enable = &rv770_dpm_late_enable,
dc50ba7f 1365 .disable = &cypress_dpm_disable,
98243917 1366 .pre_set_power_state = &r600_dpm_pre_set_power_state,
dc50ba7f 1367 .set_power_state = &cypress_dpm_set_power_state,
98243917 1368 .post_set_power_state = &r600_dpm_post_set_power_state,
dc50ba7f
AD		 1369 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1370 .fini = &cypress_dpm_fini,
1371 .get_sclk = &rv770_dpm_get_sclk,
1372 .get_mclk = &rv770_dpm_get_mclk,
1373 .print_power_state = &rv770_dpm_print_power_state,
bd210d11 1374 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
8b5e6b7f 1375 .force_performance_level = &rv770_dpm_force_performance_level,
d0b54bdc 1376 .vblank_too_short = &cypress_dpm_vblank_too_short,
dc50ba7f 1377 },
0f9e006c 1378 .pflip = {
0f9e006c 1379 .page_flip = &evergreen_page_flip,
157fa14d 1380 .page_flip_pending = &evergreen_page_flip_pending,
0f9e006c 1381 },
48e7a5f1
DV		 1382};
1383
958261d1
AD		 1384static struct radeon_asic sumo_asic = {
1385 .init = &evergreen_init,
1386 .fini = &evergreen_fini,
1387 .suspend = &evergreen_suspend,
1388 .resume = &evergreen_resume,
958261d1
AD		 1389 .asic_reset = &evergreen_asic_reset,
1390 .vga_set_state = &r600_vga_set_state,
124764f1 1391 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1392 .gui_idle = &r600_gui_idle,
1393 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1394 .get_xclk = &r600_get_xclk,
d0418894 1395 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1396 .gart = {
1397 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1398 .set_page = &rs600_gart_set_page,
1399 },
4c87bc26 1400 .ring = {
76a0df85
CK		 1401 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1402 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1403 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1404 },
b35ea4ab
AD		 1405 .irq = {
1406 .set = &evergreen_irq_set,
1407 .process = &evergreen_irq_process,
1408 },
c79a49ca
AD		 1409 .display = {
1410 .bandwidth_update = &evergreen_bandwidth_update,
1411 .get_vblank_counter = &evergreen_get_vblank_counter,
1412 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1413 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1414 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1415 .hdmi_enable = &evergreen_hdmi_enable,
1416 .hdmi_setmode = &evergreen_hdmi_setmode,
c79a49ca 1417 },
27cd7769 1418 .copy = {
8dddb993 1419 .blit = &r600_copy_cpdma,
27cd7769 1420 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1421 .dma = &evergreen_copy_dma,
1422 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1423 .copy = &evergreen_copy_dma,
1424 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1425 },
9e6f3d02
AD		 1426 .surface = {
1427 .set_reg = r600_set_surface_reg,
1428 .clear_reg = r600_clear_surface_reg,
1429 },
901ea57d
AD		 1430 .hpd = {
1431 .init = &evergreen_hpd_init,
1432 .fini = &evergreen_hpd_fini,
1433 .sense = &evergreen_hpd_sense,
1434 .set_polarity = &evergreen_hpd_set_polarity,
1435 },
a02fa397
AD		 1436 .pm = {
1437 .misc = &evergreen_pm_misc,
1438 .prepare = &evergreen_pm_prepare,
1439 .finish = &evergreen_pm_finish,
1440 .init_profile = &sumo_pm_init_profile,
1441 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1442 .get_engine_clock = &radeon_atom_get_engine_clock,
1443 .set_engine_clock = &radeon_atom_set_engine_clock,
1444 .get_memory_clock = NULL,
1445 .set_memory_clock = NULL,
1446 .get_pcie_lanes = NULL,
1447 .set_pcie_lanes = NULL,
1448 .set_clock_gating = NULL,
23d33ba3 1449 .set_uvd_clocks = &sumo_set_uvd_clocks,
6bd1c385 1450 .get_temperature = &sumo_get_temp,
a02fa397 1451 },
80ea2c12
AD		 1452 .dpm = {
1453 .init = &sumo_dpm_init,
1454 .setup_asic = &sumo_dpm_setup_asic,
1455 .enable = &sumo_dpm_enable,
14ec9fab 1456 .late_enable = &sumo_dpm_late_enable,
80ea2c12 1457 .disable = &sumo_dpm_disable,
422a56bc 1458 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
80ea2c12 1459 .set_power_state = &sumo_dpm_set_power_state,
422a56bc 1460 .post_set_power_state = &sumo_dpm_post_set_power_state,
80ea2c12
AD		 1461 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1462 .fini = &sumo_dpm_fini,
1463 .get_sclk = &sumo_dpm_get_sclk,
1464 .get_mclk = &sumo_dpm_get_mclk,
1465 .print_power_state = &sumo_dpm_print_power_state,
fb70160c 1466 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
5d5e5591 1467 .force_performance_level = &sumo_dpm_force_performance_level,
80ea2c12 1468 },
0f9e006c 1469 .pflip = {
0f9e006c 1470 .page_flip = &evergreen_page_flip,
157fa14d 1471 .page_flip_pending = &evergreen_page_flip_pending,
0f9e006c 1472 },
958261d1
AD		 1473};
1474
a43b7665
AD		 1475static struct radeon_asic btc_asic = {
1476 .init = &evergreen_init,
1477 .fini = &evergreen_fini,
1478 .suspend = &evergreen_suspend,
1479 .resume = &evergreen_resume,
a43b7665
AD		 1480 .asic_reset = &evergreen_asic_reset,
1481 .vga_set_state = &r600_vga_set_state,
124764f1 1482 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1483 .gui_idle = &r600_gui_idle,
1484 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1485 .get_xclk = &rv770_get_xclk,
d0418894 1486 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1487 .gart = {
1488 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1489 .set_page = &rs600_gart_set_page,
1490 },
4c87bc26 1491 .ring = {
76a0df85
CK		 1492 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1493 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1494 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1495 },
b35ea4ab
AD		 1496 .irq = {
1497 .set = &evergreen_irq_set,
1498 .process = &evergreen_irq_process,
1499 },
c79a49ca
AD		 1500 .display = {
1501 .bandwidth_update = &evergreen_bandwidth_update,
1502 .get_vblank_counter = &evergreen_get_vblank_counter,
1503 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1504 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1505 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1506 .hdmi_enable = &evergreen_hdmi_enable,
1507 .hdmi_setmode = &evergreen_hdmi_setmode,
c79a49ca 1508 },
27cd7769 1509 .copy = {
8dddb993 1510 .blit = &r600_copy_cpdma,
27cd7769 1511 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1512 .dma = &evergreen_copy_dma,
1513 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1514 .copy = &evergreen_copy_dma,
1515 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1516 },
9e6f3d02
AD		 1517 .surface = {
1518 .set_reg = r600_set_surface_reg,
1519 .clear_reg = r600_clear_surface_reg,
1520 },
901ea57d
AD		 1521 .hpd = {
1522 .init = &evergreen_hpd_init,
1523 .fini = &evergreen_hpd_fini,
1524 .sense = &evergreen_hpd_sense,
1525 .set_polarity = &evergreen_hpd_set_polarity,
1526 },
a02fa397
AD		 1527 .pm = {
1528 .misc = &evergreen_pm_misc,
1529 .prepare = &evergreen_pm_prepare,
1530 .finish = &evergreen_pm_finish,
27810fb2 1531 .init_profile = &btc_pm_init_profile,
a02fa397 1532 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1533 .get_engine_clock = &radeon_atom_get_engine_clock,
1534 .set_engine_clock = &radeon_atom_set_engine_clock,
1535 .get_memory_clock = &radeon_atom_get_memory_clock,
1536 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1537 .get_pcie_lanes = &r600_get_pcie_lanes,
1538 .set_pcie_lanes = &r600_set_pcie_lanes,
798bcf73 1539 .set_clock_gating = NULL,
a8b4925c 1540 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1541 .get_temperature = &evergreen_get_temp,
a02fa397 1542 },
6596afd4
AD		 1543 .dpm = {
1544 .init = &btc_dpm_init,
1545 .setup_asic = &btc_dpm_setup_asic,
1546 .enable = &btc_dpm_enable,
a3f11245 1547 .late_enable = &rv770_dpm_late_enable,
6596afd4 1548 .disable = &btc_dpm_disable,
e8a9539f 1549 .pre_set_power_state = &btc_dpm_pre_set_power_state,
6596afd4 1550 .set_power_state = &btc_dpm_set_power_state,
e8a9539f 1551 .post_set_power_state = &btc_dpm_post_set_power_state,
6596afd4
AD		 1552 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1553 .fini = &btc_dpm_fini,
e8a9539f
AD		 1554 .get_sclk = &btc_dpm_get_sclk,
1555 .get_mclk = &btc_dpm_get_mclk,
6596afd4 1556 .print_power_state = &rv770_dpm_print_power_state,
9f3f63f2 1557 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
8b5e6b7f 1558 .force_performance_level = &rv770_dpm_force_performance_level,
a84301c6 1559 .vblank_too_short = &btc_dpm_vblank_too_short,
6596afd4 1560 },
0f9e006c 1561 .pflip = {
0f9e006c 1562 .page_flip = &evergreen_page_flip,
157fa14d 1563 .page_flip_pending = &evergreen_page_flip_pending,
0f9e006c 1564 },
a43b7665
AD		 1565};
1566
76a0df85
CK		 1567static struct radeon_asic_ring cayman_gfx_ring = {
1568 .ib_execute = &cayman_ring_ib_execute,
1569 .ib_parse = &evergreen_ib_parse,
1570 .emit_fence = &cayman_fence_ring_emit,
1571 .emit_semaphore = &r600_semaphore_ring_emit,
1572 .cs_parse = &evergreen_cs_parse,
1573 .ring_test = &r600_ring_test,
1574 .ib_test = &r600_ib_test,
1575 .is_lockup = &cayman_gfx_is_lockup,
1576 .vm_flush = &cayman_vm_flush,
ea31bf69
AD		 1577 .get_rptr = &cayman_gfx_get_rptr,
1578 .get_wptr = &cayman_gfx_get_wptr,
1579 .set_wptr = &cayman_gfx_set_wptr,
76a0df85
CK		 1580};
1581
1582static struct radeon_asic_ring cayman_dma_ring = {
1583 .ib_execute = &cayman_dma_ring_ib_execute,
1584 .ib_parse = &evergreen_dma_ib_parse,
1585 .emit_fence = &evergreen_dma_fence_ring_emit,
1586 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1587 .cs_parse = &evergreen_dma_cs_parse,
1588 .ring_test = &r600_dma_ring_test,
1589 .ib_test = &r600_dma_ib_test,
1590 .is_lockup = &cayman_dma_is_lockup,
1591 .vm_flush = &cayman_dma_vm_flush,
ea31bf69
AD		 1592 .get_rptr = &cayman_dma_get_rptr,
1593 .get_wptr = &cayman_dma_get_wptr,
1594 .set_wptr = &cayman_dma_set_wptr
76a0df85
CK		 1595};
1596
1597static struct radeon_asic_ring cayman_uvd_ring = {
e409b128
CK		 1598 .ib_execute = &uvd_v1_0_ib_execute,
1599 .emit_fence = &uvd_v2_2_fence_emit,
1600 .emit_semaphore = &uvd_v3_1_semaphore_emit,
76a0df85 1601 .cs_parse = &radeon_uvd_cs_parse,
e409b128
CK		 1602 .ring_test = &uvd_v1_0_ring_test,
1603 .ib_test = &uvd_v1_0_ib_test,
76a0df85 1604 .is_lockup = &radeon_ring_test_lockup,
e409b128
CK		 1605 .get_rptr = &uvd_v1_0_get_rptr,
1606 .get_wptr = &uvd_v1_0_get_wptr,
1607 .set_wptr = &uvd_v1_0_set_wptr,
76a0df85
CK		 1608};
1609
e3487629
AD		 1610static struct radeon_asic cayman_asic = {
1611 .init = &cayman_init,
1612 .fini = &cayman_fini,
1613 .suspend = &cayman_suspend,
1614 .resume = &cayman_resume,
e3487629
AD		 1615 .asic_reset = &cayman_asic_reset,
1616 .vga_set_state = &r600_vga_set_state,
124764f1 1617 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1618 .gui_idle = &r600_gui_idle,
1619 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1620 .get_xclk = &rv770_get_xclk,
d0418894 1621 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1622 .gart = {
1623 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1624 .set_page = &rs600_gart_set_page,
1625 },
05b07147
CK		 1626 .vm = {
1627 .init = &cayman_vm_init,
1628 .fini = &cayman_vm_fini,
03f62abd
CK		 1629 .copy_pages = &cayman_dma_vm_copy_pages,
1630 .write_pages = &cayman_dma_vm_write_pages,
1631 .set_pages = &cayman_dma_vm_set_pages,
1632 .pad_ib = &cayman_dma_vm_pad_ib,
05b07147 1633 },
4c87bc26 1634 .ring = {
76a0df85
CK		 1635 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1636 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1637 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1638 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1639 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1640 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
4c87bc26 1641 },
b35ea4ab
AD		 1642 .irq = {
1643 .set = &evergreen_irq_set,
1644 .process = &evergreen_irq_process,
1645 },
c79a49ca
AD		 1646 .display = {
1647 .bandwidth_update = &evergreen_bandwidth_update,
1648 .get_vblank_counter = &evergreen_get_vblank_counter,
1649 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1650 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1651 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1652 .hdmi_enable = &evergreen_hdmi_enable,
1653 .hdmi_setmode = &evergreen_hdmi_setmode,
c79a49ca 1654 },
27cd7769 1655 .copy = {
8dddb993 1656 .blit = &r600_copy_cpdma,
27cd7769 1657 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
f60cbd11
AD		 1658 .dma = &evergreen_copy_dma,
1659 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1660 .copy = &evergreen_copy_dma,
1661 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1662 },
9e6f3d02
AD		 1663 .surface = {
1664 .set_reg = r600_set_surface_reg,
1665 .clear_reg = r600_clear_surface_reg,
1666 },
901ea57d
AD		 1667 .hpd = {
1668 .init = &evergreen_hpd_init,
1669 .fini = &evergreen_hpd_fini,
1670 .sense = &evergreen_hpd_sense,
1671 .set_polarity = &evergreen_hpd_set_polarity,
1672 },
a02fa397
AD		 1673 .pm = {
1674 .misc = &evergreen_pm_misc,
1675 .prepare = &evergreen_pm_prepare,
1676 .finish = &evergreen_pm_finish,
27810fb2 1677 .init_profile = &btc_pm_init_profile,
a02fa397 1678 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1679 .get_engine_clock = &radeon_atom_get_engine_clock,
1680 .set_engine_clock = &radeon_atom_set_engine_clock,
1681 .get_memory_clock = &radeon_atom_get_memory_clock,
1682 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1683 .get_pcie_lanes = &r600_get_pcie_lanes,
1684 .set_pcie_lanes = &r600_set_pcie_lanes,
798bcf73 1685 .set_clock_gating = NULL,
a8b4925c 1686 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1687 .get_temperature = &evergreen_get_temp,
a02fa397 1688 },
69e0b57a
AD		 1689 .dpm = {
1690 .init = &ni_dpm_init,
1691 .setup_asic = &ni_dpm_setup_asic,
1692 .enable = &ni_dpm_enable,
a3f11245 1693 .late_enable = &rv770_dpm_late_enable,
69e0b57a 1694 .disable = &ni_dpm_disable,
fee3d744 1695 .pre_set_power_state = &ni_dpm_pre_set_power_state,
69e0b57a 1696 .set_power_state = &ni_dpm_set_power_state,
fee3d744 1697 .post_set_power_state = &ni_dpm_post_set_power_state,
69e0b57a
AD		 1698 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1699 .fini = &ni_dpm_fini,
1700 .get_sclk = &ni_dpm_get_sclk,
1701 .get_mclk = &ni_dpm_get_mclk,
1702 .print_power_state = &ni_dpm_print_power_state,
bdf0c4f0 1703 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
170a47f0 1704 .force_performance_level = &ni_dpm_force_performance_level,
76ad73e5 1705 .vblank_too_short = &ni_dpm_vblank_too_short,
69e0b57a 1706 },
0f9e006c 1707 .pflip = {
0f9e006c 1708 .page_flip = &evergreen_page_flip,
157fa14d 1709 .page_flip_pending = &evergreen_page_flip_pending,
0f9e006c 1710 },
e3487629
AD		 1711};
1712
be63fe8c
AD		 1713static struct radeon_asic trinity_asic = {
1714 .init = &cayman_init,
1715 .fini = &cayman_fini,
1716 .suspend = &cayman_suspend,
1717 .resume = &cayman_resume,
be63fe8c
AD		 1718 .asic_reset = &cayman_asic_reset,
1719 .vga_set_state = &r600_vga_set_state,
124764f1 1720 .mmio_hdp_flush = r600_mmio_hdp_flush,
be63fe8c
AD		 1721 .gui_idle = &r600_gui_idle,
1722 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1723 .get_xclk = &r600_get_xclk,
d0418894 1724 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
be63fe8c
AD		 1725 .gart = {
1726 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1727 .set_page = &rs600_gart_set_page,
1728 },
05b07147
CK		 1729 .vm = {
1730 .init = &cayman_vm_init,
1731 .fini = &cayman_vm_fini,
03f62abd
CK		 1732 .copy_pages = &cayman_dma_vm_copy_pages,
1733 .write_pages = &cayman_dma_vm_write_pages,
1734 .set_pages = &cayman_dma_vm_set_pages,
1735 .pad_ib = &cayman_dma_vm_pad_ib,
05b07147 1736 },
be63fe8c 1737 .ring = {
76a0df85
CK		 1738 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1739 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1740 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1741 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1742 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1743 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
be63fe8c
AD		 1744 },
1745 .irq = {
1746 .set = &evergreen_irq_set,
1747 .process = &evergreen_irq_process,
1748 },
1749 .display = {
1750 .bandwidth_update = &dce6_bandwidth_update,
1751 .get_vblank_counter = &evergreen_get_vblank_counter,
1752 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1753 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1754 .get_backlight_level = &atombios_get_backlight_level,
b530602f
AD		 1755 .hdmi_enable = &evergreen_hdmi_enable,
1756 .hdmi_setmode = &evergreen_hdmi_setmode,
be63fe8c
AD		 1757 },
1758 .copy = {
8dddb993 1759 .blit = &r600_copy_cpdma,
be63fe8c 1760 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
f60cbd11
AD		 1761 .dma = &evergreen_copy_dma,
1762 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1763 .copy = &evergreen_copy_dma,
1764 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
be63fe8c
AD		 1765 },
1766 .surface = {
1767 .set_reg = r600_set_surface_reg,
1768 .clear_reg = r600_clear_surface_reg,
1769 },
1770 .hpd = {
1771 .init = &evergreen_hpd_init,
1772 .fini = &evergreen_hpd_fini,
1773 .sense = &evergreen_hpd_sense,
1774 .set_polarity = &evergreen_hpd_set_polarity,
1775 },
1776 .pm = {
1777 .misc = &evergreen_pm_misc,
1778 .prepare = &evergreen_pm_prepare,
1779 .finish = &evergreen_pm_finish,
1780 .init_profile = &sumo_pm_init_profile,
1781 .get_dynpm_state = &r600_pm_get_dynpm_state,
1782 .get_engine_clock = &radeon_atom_get_engine_clock,
1783 .set_engine_clock = &radeon_atom_set_engine_clock,
1784 .get_memory_clock = NULL,
1785 .set_memory_clock = NULL,
1786 .get_pcie_lanes = NULL,
1787 .set_pcie_lanes = NULL,
1788 .set_clock_gating = NULL,
23d33ba3 1789 .set_uvd_clocks = &sumo_set_uvd_clocks,
29a15221 1790 .get_temperature = &tn_get_temp,
be63fe8c 1791 },
d70229f7
AD		 1792 .dpm = {
1793 .init = &trinity_dpm_init,
1794 .setup_asic = &trinity_dpm_setup_asic,
1795 .enable = &trinity_dpm_enable,
bda44c1a 1796 .late_enable = &trinity_dpm_late_enable,
d70229f7 1797 .disable = &trinity_dpm_disable,
a284c48a 1798 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
d70229f7 1799 .set_power_state = &trinity_dpm_set_power_state,
a284c48a 1800 .post_set_power_state = &trinity_dpm_post_set_power_state,
d70229f7
AD		 1801 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
1802 .fini = &trinity_dpm_fini,
1803 .get_sclk = &trinity_dpm_get_sclk,
1804 .get_mclk = &trinity_dpm_get_mclk,
1805 .print_power_state = &trinity_dpm_print_power_state,
490ab931 1806 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
9b5de596 1807 .force_performance_level = &trinity_dpm_force_performance_level,
11877060 1808 .enable_bapm = &trinity_dpm_enable_bapm,
d70229f7 1809 },
be63fe8c 1810 .pflip = {
be63fe8c 1811 .page_flip = &evergreen_page_flip,
157fa14d 1812 .page_flip_pending = &evergreen_page_flip_pending,
be63fe8c
AD		 1813 },
1814};
1815
76a0df85
CK		 1816static struct radeon_asic_ring si_gfx_ring = {
1817 .ib_execute = &si_ring_ib_execute,
1818 .ib_parse = &si_ib_parse,
1819 .emit_fence = &si_fence_ring_emit,
1820 .emit_semaphore = &r600_semaphore_ring_emit,
1821 .cs_parse = NULL,
1822 .ring_test = &r600_ring_test,
1823 .ib_test = &r600_ib_test,
1824 .is_lockup = &si_gfx_is_lockup,
1825 .vm_flush = &si_vm_flush,
ea31bf69
AD		 1826 .get_rptr = &cayman_gfx_get_rptr,
1827 .get_wptr = &cayman_gfx_get_wptr,
1828 .set_wptr = &cayman_gfx_set_wptr,
76a0df85
CK		 1829};
1830
1831static struct radeon_asic_ring si_dma_ring = {
1832 .ib_execute = &cayman_dma_ring_ib_execute,
1833 .ib_parse = &evergreen_dma_ib_parse,
1834 .emit_fence = &evergreen_dma_fence_ring_emit,
1835 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1836 .cs_parse = NULL,
1837 .ring_test = &r600_dma_ring_test,
1838 .ib_test = &r600_dma_ib_test,
1839 .is_lockup = &si_dma_is_lockup,
1840 .vm_flush = &si_dma_vm_flush,
ea31bf69
AD		 1841 .get_rptr = &cayman_dma_get_rptr,
1842 .get_wptr = &cayman_dma_get_wptr,
1843 .set_wptr = &cayman_dma_set_wptr,
76a0df85
CK		 1844};
1845
02779c08
AD		 1846static struct radeon_asic si_asic = {
1847 .init = &si_init,
1848 .fini = &si_fini,
1849 .suspend = &si_suspend,
1850 .resume = &si_resume,
02779c08
AD		 1851 .asic_reset = &si_asic_reset,
1852 .vga_set_state = &r600_vga_set_state,
124764f1 1853 .mmio_hdp_flush = r600_mmio_hdp_flush,
02779c08
AD		 1854 .gui_idle = &r600_gui_idle,
1855 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1856 .get_xclk = &si_get_xclk,
d0418894 1857 .get_gpu_clock_counter = &si_get_gpu_clock_counter,
02779c08
AD		 1858 .gart = {
1859 .tlb_flush = &si_pcie_gart_tlb_flush,
1860 .set_page = &rs600_gart_set_page,
1861 },
05b07147
CK		 1862 .vm = {
1863 .init = &si_vm_init,
1864 .fini = &si_vm_fini,
03f62abd
CK		 1865 .copy_pages = &si_dma_vm_copy_pages,
1866 .write_pages = &si_dma_vm_write_pages,
1867 .set_pages = &si_dma_vm_set_pages,
1868 .pad_ib = &cayman_dma_vm_pad_ib,
05b07147 1869 },
02779c08 1870 .ring = {
76a0df85
CK		 1871 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1872 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1873 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1874 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1875 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1876 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
02779c08
AD		 1877 },
1878 .irq = {
1879 .set = &si_irq_set,
1880 .process = &si_irq_process,
1881 },
1882 .display = {
1883 .bandwidth_update = &dce6_bandwidth_update,
1884 .get_vblank_counter = &evergreen_get_vblank_counter,
1885 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1886 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1887 .get_backlight_level = &atombios_get_backlight_level,
b530602f
AD		 1888 .hdmi_enable = &evergreen_hdmi_enable,
1889 .hdmi_setmode = &evergreen_hdmi_setmode,
02779c08
AD		 1890 },
1891 .copy = {
5c722739 1892 .blit = &r600_copy_cpdma,
02779c08 1893 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
8c5fd7ef
AD		 1894 .dma = &si_copy_dma,
1895 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1896 .copy = &si_copy_dma,
1897 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
02779c08
AD		 1898 },
1899 .surface = {
1900 .set_reg = r600_set_surface_reg,
1901 .clear_reg = r600_clear_surface_reg,
1902 },
1903 .hpd = {
1904 .init = &evergreen_hpd_init,
1905 .fini = &evergreen_hpd_fini,
1906 .sense = &evergreen_hpd_sense,
1907 .set_polarity = &evergreen_hpd_set_polarity,
1908 },
1909 .pm = {
1910 .misc = &evergreen_pm_misc,
1911 .prepare = &evergreen_pm_prepare,
1912 .finish = &evergreen_pm_finish,
1913 .init_profile = &sumo_pm_init_profile,
1914 .get_dynpm_state = &r600_pm_get_dynpm_state,
1915 .get_engine_clock = &radeon_atom_get_engine_clock,
1916 .set_engine_clock = &radeon_atom_set_engine_clock,
1917 .get_memory_clock = &radeon_atom_get_memory_clock,
1918 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1919 .get_pcie_lanes = &r600_get_pcie_lanes,
1920 .set_pcie_lanes = &r600_set_pcie_lanes,
02779c08 1921 .set_clock_gating = NULL,
2539eb02 1922 .set_uvd_clocks = &si_set_uvd_clocks,
6bd1c385 1923 .get_temperature = &si_get_temp,
02779c08 1924 },
a9e61410
AD		 1925 .dpm = {
1926 .init = &si_dpm_init,
1927 .setup_asic = &si_dpm_setup_asic,
1928 .enable = &si_dpm_enable,
963c115d 1929 .late_enable = &si_dpm_late_enable,
a9e61410
AD		 1930 .disable = &si_dpm_disable,
1931 .pre_set_power_state = &si_dpm_pre_set_power_state,
1932 .set_power_state = &si_dpm_set_power_state,
1933 .post_set_power_state = &si_dpm_post_set_power_state,
1934 .display_configuration_changed = &si_dpm_display_configuration_changed,
1935 .fini = &si_dpm_fini,
1936 .get_sclk = &ni_dpm_get_sclk,
1937 .get_mclk = &ni_dpm_get_mclk,
1938 .print_power_state = &ni_dpm_print_power_state,
7982128c 1939 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
a160a6a3 1940 .force_performance_level = &si_dpm_force_performance_level,
f4dec318 1941 .vblank_too_short = &ni_dpm_vblank_too_short,
a9e61410 1942 },
02779c08 1943 .pflip = {
02779c08 1944 .page_flip = &evergreen_page_flip,
157fa14d 1945 .page_flip_pending = &evergreen_page_flip_pending,
02779c08
AD		 1946 },
1947};
1948
76a0df85
CK		 1949static struct radeon_asic_ring ci_gfx_ring = {
1950 .ib_execute = &cik_ring_ib_execute,
1951 .ib_parse = &cik_ib_parse,
1952 .emit_fence = &cik_fence_gfx_ring_emit,
1953 .emit_semaphore = &cik_semaphore_ring_emit,
1954 .cs_parse = NULL,
1955 .ring_test = &cik_ring_test,
1956 .ib_test = &cik_ib_test,
1957 .is_lockup = &cik_gfx_is_lockup,
1958 .vm_flush = &cik_vm_flush,
ea31bf69
AD		 1959 .get_rptr = &cik_gfx_get_rptr,
1960 .get_wptr = &cik_gfx_get_wptr,
1961 .set_wptr = &cik_gfx_set_wptr,
76a0df85
CK		 1962};
1963
1964static struct radeon_asic_ring ci_cp_ring = {
1965 .ib_execute = &cik_ring_ib_execute,
1966 .ib_parse = &cik_ib_parse,
1967 .emit_fence = &cik_fence_compute_ring_emit,
1968 .emit_semaphore = &cik_semaphore_ring_emit,
1969 .cs_parse = NULL,
1970 .ring_test = &cik_ring_test,
1971 .ib_test = &cik_ib_test,
1972 .is_lockup = &cik_gfx_is_lockup,
1973 .vm_flush = &cik_vm_flush,
ea31bf69
AD		 1974 .get_rptr = &cik_compute_get_rptr,
1975 .get_wptr = &cik_compute_get_wptr,
1976 .set_wptr = &cik_compute_set_wptr,
76a0df85
CK		 1977};
1978
1979static struct radeon_asic_ring ci_dma_ring = {
1980 .ib_execute = &cik_sdma_ring_ib_execute,
1981 .ib_parse = &cik_ib_parse,
1982 .emit_fence = &cik_sdma_fence_ring_emit,
1983 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
1984 .cs_parse = NULL,
1985 .ring_test = &cik_sdma_ring_test,
1986 .ib_test = &cik_sdma_ib_test,
1987 .is_lockup = &cik_sdma_is_lockup,
1988 .vm_flush = &cik_dma_vm_flush,
ea31bf69
AD		 1989 .get_rptr = &cik_sdma_get_rptr,
1990 .get_wptr = &cik_sdma_get_wptr,
1991 .set_wptr = &cik_sdma_set_wptr,
76a0df85
CK		 1992};
1993
d93f7937
CK		 1994static struct radeon_asic_ring ci_vce_ring = {
1995 .ib_execute = &radeon_vce_ib_execute,
1996 .emit_fence = &radeon_vce_fence_emit,
1997 .emit_semaphore = &radeon_vce_semaphore_emit,
1998 .cs_parse = &radeon_vce_cs_parse,
1999 .ring_test = &radeon_vce_ring_test,
2000 .ib_test = &radeon_vce_ib_test,
2001 .is_lockup = &radeon_ring_test_lockup,
2002 .get_rptr = &vce_v1_0_get_rptr,
2003 .get_wptr = &vce_v1_0_get_wptr,
2004 .set_wptr = &vce_v1_0_set_wptr,
2005};
2006
0672e27b
AD		 2007static struct radeon_asic ci_asic = {
2008 .init = &cik_init,
2009 .fini = &cik_fini,
2010 .suspend = &cik_suspend,
2011 .resume = &cik_resume,
2012 .asic_reset = &cik_asic_reset,
2013 .vga_set_state = &r600_vga_set_state,
72a9987e 2014 .mmio_hdp_flush = &r600_mmio_hdp_flush,
0672e27b
AD		 2015 .gui_idle = &r600_gui_idle,
2016 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2017 .get_xclk = &cik_get_xclk,
2018 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2019 .gart = {
2020 .tlb_flush = &cik_pcie_gart_tlb_flush,
2021 .set_page = &rs600_gart_set_page,
2022 },
2023 .vm = {
2024 .init = &cik_vm_init,
2025 .fini = &cik_vm_fini,
03f62abd
CK		 2026 .copy_pages = &cik_sdma_vm_copy_pages,
2027 .write_pages = &cik_sdma_vm_write_pages,
2028 .set_pages = &cik_sdma_vm_set_pages,
2029 .pad_ib = &cik_sdma_vm_pad_ib,
0672e27b
AD		 2030 },
2031 .ring = {
76a0df85
CK		 2032 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2033 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2034 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2035 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2036 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2037 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
d93f7937
CK		 2038 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2039 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
0672e27b
AD		 2040 },
2041 .irq = {
2042 .set = &cik_irq_set,
2043 .process = &cik_irq_process,
2044 },
2045 .display = {
2046 .bandwidth_update = &dce8_bandwidth_update,
2047 .get_vblank_counter = &evergreen_get_vblank_counter,
2048 .wait_for_vblank = &dce4_wait_for_vblank,
7272c9d2
SL		 2049 .set_backlight_level = &atombios_set_backlight_level,
2050 .get_backlight_level = &atombios_get_backlight_level,
b530602f
AD		 2051 .hdmi_enable = &evergreen_hdmi_enable,
2052 .hdmi_setmode = &evergreen_hdmi_setmode,
0672e27b
AD		 2053 },
2054 .copy = {
7819678f 2055 .blit = &cik_copy_cpdma,
0672e27b
AD		 2056 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2057 .dma = &cik_copy_dma,
2058 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
b5be1a83
CK		 2059 .copy = &cik_copy_dma,
2060 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
0672e27b
AD		 2061 },
2062 .surface = {
2063 .set_reg = r600_set_surface_reg,
2064 .clear_reg = r600_clear_surface_reg,
2065 },
2066 .hpd = {
2067 .init = &evergreen_hpd_init,
2068 .fini = &evergreen_hpd_fini,
2069 .sense = &evergreen_hpd_sense,
2070 .set_polarity = &evergreen_hpd_set_polarity,
2071 },
2072 .pm = {
2073 .misc = &evergreen_pm_misc,
2074 .prepare = &evergreen_pm_prepare,
2075 .finish = &evergreen_pm_finish,
2076 .init_profile = &sumo_pm_init_profile,
2077 .get_dynpm_state = &r600_pm_get_dynpm_state,
2078 .get_engine_clock = &radeon_atom_get_engine_clock,
2079 .set_engine_clock = &radeon_atom_set_engine_clock,
2080 .get_memory_clock = &radeon_atom_get_memory_clock,
2081 .set_memory_clock = &radeon_atom_set_memory_clock,
2082 .get_pcie_lanes = NULL,
2083 .set_pcie_lanes = NULL,
2084 .set_clock_gating = NULL,
2085 .set_uvd_clocks = &cik_set_uvd_clocks,
5ad6bf91 2086 .set_vce_clocks = &cik_set_vce_clocks,
286d9cc6 2087 .get_temperature = &ci_get_temp,
0672e27b 2088 },
cc8dbbb4
AD		 2089 .dpm = {
2090 .init = &ci_dpm_init,
2091 .setup_asic = &ci_dpm_setup_asic,
2092 .enable = &ci_dpm_enable,
90208427 2093 .late_enable = &ci_dpm_late_enable,
cc8dbbb4
AD		 2094 .disable = &ci_dpm_disable,
2095 .pre_set_power_state = &ci_dpm_pre_set_power_state,
2096 .set_power_state = &ci_dpm_set_power_state,
2097 .post_set_power_state = &ci_dpm_post_set_power_state,
2098 .display_configuration_changed = &ci_dpm_display_configuration_changed,
2099 .fini = &ci_dpm_fini,
2100 .get_sclk = &ci_dpm_get_sclk,
2101 .get_mclk = &ci_dpm_get_mclk,
2102 .print_power_state = &ci_dpm_print_power_state,
94b4adc5 2103 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
89536fd6 2104 .force_performance_level = &ci_dpm_force_performance_level,
5496131e 2105 .vblank_too_short = &ci_dpm_vblank_too_short,
942bdf7f 2106 .powergate_uvd = &ci_dpm_powergate_uvd,
cc8dbbb4 2107 },
0672e27b 2108 .pflip = {
0672e27b 2109 .page_flip = &evergreen_page_flip,
157fa14d 2110 .page_flip_pending = &evergreen_page_flip_pending,
0672e27b
AD		 2111 },
2112};
2113
2114static struct radeon_asic kv_asic = {
2115 .init = &cik_init,
2116 .fini = &cik_fini,
2117 .suspend = &cik_suspend,
2118 .resume = &cik_resume,
2119 .asic_reset = &cik_asic_reset,
2120 .vga_set_state = &r600_vga_set_state,
72a9987e 2121 .mmio_hdp_flush = &r600_mmio_hdp_flush,
0672e27b
AD		 2122 .gui_idle = &r600_gui_idle,
2123 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2124 .get_xclk = &cik_get_xclk,
2125 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2126 .gart = {
2127 .tlb_flush = &cik_pcie_gart_tlb_flush,
2128 .set_page = &rs600_gart_set_page,
2129 },
2130 .vm = {
2131 .init = &cik_vm_init,
2132 .fini = &cik_vm_fini,
03f62abd
CK		 2133 .copy_pages = &cik_sdma_vm_copy_pages,
2134 .write_pages = &cik_sdma_vm_write_pages,
2135 .set_pages = &cik_sdma_vm_set_pages,
2136 .pad_ib = &cik_sdma_vm_pad_ib,
0672e27b
AD		 2137 },
2138 .ring = {
76a0df85
CK		 2139 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2140 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2141 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2142 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2143 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2144 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
d93f7937
CK		 2145 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2146 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
0672e27b
AD		 2147 },
2148 .irq = {
2149 .set = &cik_irq_set,
2150 .process = &cik_irq_process,
2151 },
2152 .display = {
2153 .bandwidth_update = &dce8_bandwidth_update,
2154 .get_vblank_counter = &evergreen_get_vblank_counter,
2155 .wait_for_vblank = &dce4_wait_for_vblank,
7272c9d2
SL		 2156 .set_backlight_level = &atombios_set_backlight_level,
2157 .get_backlight_level = &atombios_get_backlight_level,
b530602f
AD		 2158 .hdmi_enable = &evergreen_hdmi_enable,
2159 .hdmi_setmode = &evergreen_hdmi_setmode,
0672e27b
AD		 2160 },
2161 .copy = {
7819678f 2162 .blit = &cik_copy_cpdma,
0672e27b
AD		 2163 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2164 .dma = &cik_copy_dma,
2165 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2166 .copy = &cik_copy_dma,
2167 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2168 },
2169 .surface = {
2170 .set_reg = r600_set_surface_reg,
2171 .clear_reg = r600_clear_surface_reg,
2172 },
2173 .hpd = {
2174 .init = &evergreen_hpd_init,
2175 .fini = &evergreen_hpd_fini,
2176 .sense = &evergreen_hpd_sense,
2177 .set_polarity = &evergreen_hpd_set_polarity,
2178 },
2179 .pm = {
2180 .misc = &evergreen_pm_misc,
2181 .prepare = &evergreen_pm_prepare,
2182 .finish = &evergreen_pm_finish,
2183 .init_profile = &sumo_pm_init_profile,
2184 .get_dynpm_state = &r600_pm_get_dynpm_state,
2185 .get_engine_clock = &radeon_atom_get_engine_clock,
2186 .set_engine_clock = &radeon_atom_set_engine_clock,
2187 .get_memory_clock = &radeon_atom_get_memory_clock,
2188 .set_memory_clock = &radeon_atom_set_memory_clock,
2189 .get_pcie_lanes = NULL,
2190 .set_pcie_lanes = NULL,
2191 .set_clock_gating = NULL,
2192 .set_uvd_clocks = &cik_set_uvd_clocks,
5ad6bf91 2193 .set_vce_clocks = &cik_set_vce_clocks,
286d9cc6 2194 .get_temperature = &kv_get_temp,
0672e27b 2195 },
41a524ab
AD		 2196 .dpm = {
2197 .init = &kv_dpm_init,
2198 .setup_asic = &kv_dpm_setup_asic,
2199 .enable = &kv_dpm_enable,
d8852c34 2200 .late_enable = &kv_dpm_late_enable,
41a524ab
AD		 2201 .disable = &kv_dpm_disable,
2202 .pre_set_power_state = &kv_dpm_pre_set_power_state,
2203 .set_power_state = &kv_dpm_set_power_state,
2204 .post_set_power_state = &kv_dpm_post_set_power_state,
2205 .display_configuration_changed = &kv_dpm_display_configuration_changed,
2206 .fini = &kv_dpm_fini,
2207 .get_sclk = &kv_dpm_get_sclk,
2208 .get_mclk = &kv_dpm_get_mclk,
2209 .print_power_state = &kv_dpm_print_power_state,
ae3e40e8 2210 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2b4c8022 2211 .force_performance_level = &kv_dpm_force_performance_level,
77df508a 2212 .powergate_uvd = &kv_dpm_powergate_uvd,
b7a5ae97 2213 .enable_bapm = &kv_dpm_enable_bapm,
41a524ab 2214 },
0672e27b 2215 .pflip = {
0672e27b 2216 .page_flip = &evergreen_page_flip,
157fa14d 2217 .page_flip_pending = &evergreen_page_flip_pending,
0672e27b
AD		 2218 },
2219};
2220
abf1dc67
AD		 2221/**
2222 * radeon_asic_init - register asic specific callbacks
2223 *
2224 * @rdev: radeon device pointer
2225 *
2226 * Registers the appropriate asic specific callbacks for each
2227 * chip family. Also sets other asics specific info like the number
2228 * of crtcs and the register aperture accessors (all asics).
2229 * Returns 0 for success.
2230 */
0a10c851
DV		 2231int radeon_asic_init(struct radeon_device *rdev)
2232{
2233 radeon_register_accessor_init(rdev);
ba7e05e9
AD		 2234
2235 /* set the number of crtcs */
2236 if (rdev->flags & RADEON_SINGLE_CRTC)
2237 rdev->num_crtc = 1;
2238 else
2239 rdev->num_crtc = 2;
2240
948bee3f
AD		 2241 rdev->has_uvd = false;
2242
0a10c851
DV		 2243 switch (rdev->family) {
2244 case CHIP_R100:
2245 case CHIP_RV100:
2246 case CHIP_RS100:
2247 case CHIP_RV200:
2248 case CHIP_RS200:
2249 rdev->asic = &r100_asic;
2250 break;
2251 case CHIP_R200:
2252 case CHIP_RV250:
2253 case CHIP_RS300:
2254 case CHIP_RV280:
2255 rdev->asic = &r200_asic;
2256 break;
2257 case CHIP_R300:
2258 case CHIP_R350:
2259 case CHIP_RV350:
2260 case CHIP_RV380:
2261 if (rdev->flags & RADEON_IS_PCIE)
2262 rdev->asic = &r300_asic_pcie;
2263 else
2264 rdev->asic = &r300_asic;
2265 break;
2266 case CHIP_R420:
2267 case CHIP_R423:
2268 case CHIP_RV410:
2269 rdev->asic = &r420_asic;
07bb084c
AD		 2270 /* handle macs */
2271 if (rdev->bios == NULL) {
798bcf73
AD		 2272 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2273 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2274 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2275 rdev->asic->pm.set_memory_clock = NULL;
37e9b6a6 2276 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
07bb084c 2277 }
0a10c851
DV		 2278 break;
2279 case CHIP_RS400:
2280 case CHIP_RS480:
2281 rdev->asic = &rs400_asic;
2282 break;
2283 case CHIP_RS600:
2284 rdev->asic = &rs600_asic;
2285 break;
2286 case CHIP_RS690:
2287 case CHIP_RS740:
2288 rdev->asic = &rs690_asic;
2289 break;
2290 case CHIP_RV515:
2291 rdev->asic = &rv515_asic;
2292 break;
2293 case CHIP_R520:
2294 case CHIP_RV530:
2295 case CHIP_RV560:
2296 case CHIP_RV570:
2297 case CHIP_R580:
2298 rdev->asic = &r520_asic;
2299 break;
2300 case CHIP_R600:
ca361b65
AD		 2301 rdev->asic = &r600_asic;
2302 break;
0a10c851
DV		 2303 case CHIP_RV610:
2304 case CHIP_RV630:
2305 case CHIP_RV620:
2306 case CHIP_RV635:
2307 case CHIP_RV670:
ca361b65
AD		 2308 rdev->asic = &rv6xx_asic;
2309 rdev->has_uvd = true;
f47299c5 2310 break;
0a10c851
DV		 2311 case CHIP_RS780:
2312 case CHIP_RS880:
f47299c5 2313 rdev->asic = &rs780_asic;
bdc99722
AD		 2314 /* 760G/780V/880V don't have UVD */
2315 if ((rdev->pdev->device == 0x9616)||
2316 (rdev->pdev->device == 0x9611)||
2317 (rdev->pdev->device == 0x9613)||
2318 (rdev->pdev->device == 0x9711)||
2319 (rdev->pdev->device == 0x9713))
2320 rdev->has_uvd = false;
2321 else
2322 rdev->has_uvd = true;
0a10c851
DV		 2323 break;
2324 case CHIP_RV770:
2325 case CHIP_RV730:
2326 case CHIP_RV710:
2327 case CHIP_RV740:
2328 rdev->asic = &rv770_asic;
948bee3f 2329 rdev->has_uvd = true;
0a10c851
DV		 2330 break;
2331 case CHIP_CEDAR:
2332 case CHIP_REDWOOD:
2333 case CHIP_JUNIPER:
2334 case CHIP_CYPRESS:
2335 case CHIP_HEMLOCK:
ba7e05e9
AD		 2336 /* set num crtcs */
2337 if (rdev->family == CHIP_CEDAR)
2338 rdev->num_crtc = 4;
2339 else
2340 rdev->num_crtc = 6;
0a10c851 2341 rdev->asic = &evergreen_asic;
948bee3f 2342 rdev->has_uvd = true;
0a10c851 2343 break;
958261d1 2344 case CHIP_PALM:
89da5a37
AD		 2345 case CHIP_SUMO:
2346 case CHIP_SUMO2:
958261d1 2347 rdev->asic = &sumo_asic;
948bee3f 2348 rdev->has_uvd = true;
958261d1 2349 break;
a43b7665
AD		 2350 case CHIP_BARTS:
2351 case CHIP_TURKS:
2352 case CHIP_CAICOS:
ba7e05e9
AD		 2353 /* set num crtcs */
2354 if (rdev->family == CHIP_CAICOS)
2355 rdev->num_crtc = 4;
2356 else
2357 rdev->num_crtc = 6;
a43b7665 2358 rdev->asic = &btc_asic;
948bee3f 2359 rdev->has_uvd = true;
a43b7665 2360 break;
e3487629
AD		 2361 case CHIP_CAYMAN:
2362 rdev->asic = &cayman_asic;
ba7e05e9
AD		 2363 /* set num crtcs */
2364 rdev->num_crtc = 6;
948bee3f 2365 rdev->has_uvd = true;
e3487629 2366 break;
be63fe8c
AD		 2367 case CHIP_ARUBA:
2368 rdev->asic = &trinity_asic;
2369 /* set num crtcs */
2370 rdev->num_crtc = 4;
948bee3f 2371 rdev->has_uvd = true;
be63fe8c 2372 break;
02779c08
AD		 2373 case CHIP_TAHITI:
2374 case CHIP_PITCAIRN:
2375 case CHIP_VERDE:
e737a14c 2376 case CHIP_OLAND:
86a45cac 2377 case CHIP_HAINAN:
02779c08
AD		 2378 rdev->asic = &si_asic;
2379 /* set num crtcs */
86a45cac
AD		 2380 if (rdev->family == CHIP_HAINAN)
2381 rdev->num_crtc = 0;
2382 else if (rdev->family == CHIP_OLAND)
e737a14c
AD		 2383 rdev->num_crtc = 2;
2384 else
2385 rdev->num_crtc = 6;
948bee3f
AD		 2386 if (rdev->family == CHIP_HAINAN)
2387 rdev->has_uvd = false;
2388 else
2389 rdev->has_uvd = true;
0116e1ef
AD		 2390 switch (rdev->family) {
2391 case CHIP_TAHITI:
2392 rdev->cg_flags =
090f4b6a 2393 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2394 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2395 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2396 RADEON_CG_SUPPORT_GFX_CGLS |
2397 RADEON_CG_SUPPORT_GFX_CGTS |
2398 RADEON_CG_SUPPORT_GFX_CP_LS |
2399 RADEON_CG_SUPPORT_MC_MGCG |
2400 RADEON_CG_SUPPORT_SDMA_MGCG |
2401 RADEON_CG_SUPPORT_BIF_LS |
2402 RADEON_CG_SUPPORT_VCE_MGCG |
2403 RADEON_CG_SUPPORT_UVD_MGCG |
2404 RADEON_CG_SUPPORT_HDP_LS |
2405 RADEON_CG_SUPPORT_HDP_MGCG;
2406 rdev->pg_flags = 0;
2407 break;
2408 case CHIP_PITCAIRN:
2409 rdev->cg_flags =
090f4b6a 2410 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2411 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2412 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2413 RADEON_CG_SUPPORT_GFX_CGLS |
2414 RADEON_CG_SUPPORT_GFX_CGTS |
2415 RADEON_CG_SUPPORT_GFX_CP_LS |
2416 RADEON_CG_SUPPORT_GFX_RLC_LS |
2417 RADEON_CG_SUPPORT_MC_LS |
2418 RADEON_CG_SUPPORT_MC_MGCG |
2419 RADEON_CG_SUPPORT_SDMA_MGCG |
2420 RADEON_CG_SUPPORT_BIF_LS |
2421 RADEON_CG_SUPPORT_VCE_MGCG |
2422 RADEON_CG_SUPPORT_UVD_MGCG |
2423 RADEON_CG_SUPPORT_HDP_LS |
2424 RADEON_CG_SUPPORT_HDP_MGCG;
2425 rdev->pg_flags = 0;
2426 break;
2427 case CHIP_VERDE:
2428 rdev->cg_flags =
090f4b6a 2429 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2430 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2431 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2432 RADEON_CG_SUPPORT_GFX_CGLS |
2433 RADEON_CG_SUPPORT_GFX_CGTS |
2434 RADEON_CG_SUPPORT_GFX_CP_LS |
2435 RADEON_CG_SUPPORT_GFX_RLC_LS |
2436 RADEON_CG_SUPPORT_MC_LS |
2437 RADEON_CG_SUPPORT_MC_MGCG |
2438 RADEON_CG_SUPPORT_SDMA_MGCG |
2439 RADEON_CG_SUPPORT_BIF_LS |
2440 RADEON_CG_SUPPORT_VCE_MGCG |
2441 RADEON_CG_SUPPORT_UVD_MGCG |
2442 RADEON_CG_SUPPORT_HDP_LS |
2443 RADEON_CG_SUPPORT_HDP_MGCG;
ca6ebb39 2444 rdev->pg_flags = 0 |
2b19d17f 2445 /*RADEON_PG_SUPPORT_GFX_PG | */
ca6ebb39 2446 RADEON_PG_SUPPORT_SDMA;
0116e1ef
AD		 2447 break;
2448 case CHIP_OLAND:
2449 rdev->cg_flags =
090f4b6a 2450 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2451 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2452 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2453 RADEON_CG_SUPPORT_GFX_CGLS |
2454 RADEON_CG_SUPPORT_GFX_CGTS |
2455 RADEON_CG_SUPPORT_GFX_CP_LS |
2456 RADEON_CG_SUPPORT_GFX_RLC_LS |
2457 RADEON_CG_SUPPORT_MC_LS |
2458 RADEON_CG_SUPPORT_MC_MGCG |
2459 RADEON_CG_SUPPORT_SDMA_MGCG |
2460 RADEON_CG_SUPPORT_BIF_LS |
2461 RADEON_CG_SUPPORT_UVD_MGCG |
2462 RADEON_CG_SUPPORT_HDP_LS |
2463 RADEON_CG_SUPPORT_HDP_MGCG;
2464 rdev->pg_flags = 0;
2465 break;
2466 case CHIP_HAINAN:
2467 rdev->cg_flags =
090f4b6a 2468 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2469 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2470 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2471 RADEON_CG_SUPPORT_GFX_CGLS |
2472 RADEON_CG_SUPPORT_GFX_CGTS |
2473 RADEON_CG_SUPPORT_GFX_CP_LS |
2474 RADEON_CG_SUPPORT_GFX_RLC_LS |
2475 RADEON_CG_SUPPORT_MC_LS |
2476 RADEON_CG_SUPPORT_MC_MGCG |
2477 RADEON_CG_SUPPORT_SDMA_MGCG |
2478 RADEON_CG_SUPPORT_BIF_LS |
2479 RADEON_CG_SUPPORT_HDP_LS |
2480 RADEON_CG_SUPPORT_HDP_MGCG;
2481 rdev->pg_flags = 0;
2482 break;
2483 default:
2484 rdev->cg_flags = 0;
2485 rdev->pg_flags = 0;
2486 break;
2487 }
02779c08 2488 break;
0672e27b 2489 case CHIP_BONAIRE:
41971b37 2490 case CHIP_HAWAII:
0672e27b
AD		 2491 rdev->asic = &ci_asic;
2492 rdev->num_crtc = 6;
22c775ce 2493 rdev->has_uvd = true;
41971b37
AD		 2494 if (rdev->family == CHIP_BONAIRE) {
2495 rdev->cg_flags =
2496 RADEON_CG_SUPPORT_GFX_MGCG |
2497 RADEON_CG_SUPPORT_GFX_MGLS |
6960948d 2498 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
41971b37
AD		 2499 RADEON_CG_SUPPORT_GFX_CGLS |
2500 RADEON_CG_SUPPORT_GFX_CGTS |
2501 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2502 RADEON_CG_SUPPORT_GFX_CP_LS |
2503 RADEON_CG_SUPPORT_MC_LS |
2504 RADEON_CG_SUPPORT_MC_MGCG |
2505 RADEON_CG_SUPPORT_SDMA_MGCG |
2506 RADEON_CG_SUPPORT_SDMA_LS |
2507 RADEON_CG_SUPPORT_BIF_LS |
2508 RADEON_CG_SUPPORT_VCE_MGCG |
2509 RADEON_CG_SUPPORT_UVD_MGCG |
2510 RADEON_CG_SUPPORT_HDP_LS |
2511 RADEON_CG_SUPPORT_HDP_MGCG;
2512 rdev->pg_flags = 0;
2513 } else {
2514 rdev->cg_flags =
2515 RADEON_CG_SUPPORT_GFX_MGCG |
2516 RADEON_CG_SUPPORT_GFX_MGLS |
6960948d 2517 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
41971b37
AD		 2518 RADEON_CG_SUPPORT_GFX_CGLS |
2519 RADEON_CG_SUPPORT_GFX_CGTS |
2520 RADEON_CG_SUPPORT_GFX_CP_LS |
2521 RADEON_CG_SUPPORT_MC_LS |
2522 RADEON_CG_SUPPORT_MC_MGCG |
2523 RADEON_CG_SUPPORT_SDMA_MGCG |
2524 RADEON_CG_SUPPORT_SDMA_LS |
2525 RADEON_CG_SUPPORT_BIF_LS |
2526 RADEON_CG_SUPPORT_VCE_MGCG |
2527 RADEON_CG_SUPPORT_UVD_MGCG |
2528 RADEON_CG_SUPPORT_HDP_LS |
2529 RADEON_CG_SUPPORT_HDP_MGCG;
2530 rdev->pg_flags = 0;
2531 }
0672e27b
AD		 2532 break;
2533 case CHIP_KAVERI:
2534 case CHIP_KABINI:
b0a9f22a 2535 case CHIP_MULLINS:
0672e27b
AD		 2536 rdev->asic = &kv_asic;
2537 /* set num crtcs */
473359bc 2538 if (rdev->family == CHIP_KAVERI) {
0672e27b 2539 rdev->num_crtc = 4;
473359bc 2540 rdev->cg_flags =
773dc10a 2541 RADEON_CG_SUPPORT_GFX_MGCG |
473359bc 2542 RADEON_CG_SUPPORT_GFX_MGLS |
6960948d 2543 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
473359bc
AD		 2544 RADEON_CG_SUPPORT_GFX_CGLS |
2545 RADEON_CG_SUPPORT_GFX_CGTS |
2546 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2547 RADEON_CG_SUPPORT_GFX_CP_LS |
2548 RADEON_CG_SUPPORT_SDMA_MGCG |
2549 RADEON_CG_SUPPORT_SDMA_LS |
2550 RADEON_CG_SUPPORT_BIF_LS |
2551 RADEON_CG_SUPPORT_VCE_MGCG |
2552 RADEON_CG_SUPPORT_UVD_MGCG |
2553 RADEON_CG_SUPPORT_HDP_LS |
2554 RADEON_CG_SUPPORT_HDP_MGCG;
2555 rdev->pg_flags = 0;
2b19d17f 2556 /*RADEON_PG_SUPPORT_GFX_PG |
473359bc
AD		 2557 RADEON_PG_SUPPORT_GFX_SMG |
2558 RADEON_PG_SUPPORT_GFX_DMG |
2559 RADEON_PG_SUPPORT_UVD |
2560 RADEON_PG_SUPPORT_VCE |
2561 RADEON_PG_SUPPORT_CP |
2562 RADEON_PG_SUPPORT_GDS |
2563 RADEON_PG_SUPPORT_RLC_SMU_HS |
2564 RADEON_PG_SUPPORT_ACP |
2565 RADEON_PG_SUPPORT_SAMU;*/
2566 } else {
0672e27b 2567 rdev->num_crtc = 2;
473359bc 2568 rdev->cg_flags =
773dc10a 2569 RADEON_CG_SUPPORT_GFX_MGCG |
473359bc 2570 RADEON_CG_SUPPORT_GFX_MGLS |
6960948d 2571 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
473359bc
AD		 2572 RADEON_CG_SUPPORT_GFX_CGLS |
2573 RADEON_CG_SUPPORT_GFX_CGTS |
2574 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2575 RADEON_CG_SUPPORT_GFX_CP_LS |
2576 RADEON_CG_SUPPORT_SDMA_MGCG |
2577 RADEON_CG_SUPPORT_SDMA_LS |
2578 RADEON_CG_SUPPORT_BIF_LS |
2579 RADEON_CG_SUPPORT_VCE_MGCG |
2580 RADEON_CG_SUPPORT_UVD_MGCG |
2581 RADEON_CG_SUPPORT_HDP_LS |
2582 RADEON_CG_SUPPORT_HDP_MGCG;
2583 rdev->pg_flags = 0;
2b19d17f 2584 /*RADEON_PG_SUPPORT_GFX_PG |
473359bc
AD		 2585 RADEON_PG_SUPPORT_GFX_SMG |
2586 RADEON_PG_SUPPORT_UVD |
2587 RADEON_PG_SUPPORT_VCE |
2588 RADEON_PG_SUPPORT_CP |
2589 RADEON_PG_SUPPORT_GDS |
2590 RADEON_PG_SUPPORT_RLC_SMU_HS |
2591 RADEON_PG_SUPPORT_SAMU;*/
2592 }
22c775ce 2593 rdev->has_uvd = true;
0672e27b 2594 break;
0a10c851
DV		 2595 default:
2596 /* FIXME: not supported yet */
2597 return -EINVAL;
2598 }
2599
2600 if (rdev->flags & RADEON_IS_IGP) {
798bcf73
AD		 2601 rdev->asic->pm.get_memory_clock = NULL;
2602 rdev->asic->pm.set_memory_clock = NULL;
0a10c851
DV		 2603 }
2604
2605 return 0;
2606}
2607
Linux kernel - Deliverables
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