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drm/radeon/tn: implement get_current_sclk/mclk
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_asic.c
CommitLineData
0a10c851
DV		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/console.h>
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
33#include <linux/vgaarb.h>
34#include <linux/vga_switcheroo.h>
35#include "radeon_reg.h"
36#include "radeon.h"
37#include "radeon_asic.h"
38#include "atom.h"
39
40/*
41 * Registers accessors functions.
42 */
abf1dc67
AD		 43/**
44 * radeon_invalid_rreg - dummy reg read function
45 *
46 * @rdev: radeon device pointer
47 * @reg: offset of register
48 *
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
52 */
0a10c851
DV		 53static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54{
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
56 BUG_ON(1);
57 return 0;
58}
59
abf1dc67
AD		 60/**
61 * radeon_invalid_wreg - dummy reg write function
62 *
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
66 *
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
69 */
0a10c851
DV		 70static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
71{
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
73 reg, v);
74 BUG_ON(1);
75}
76
abf1dc67
AD		 77/**
78 * radeon_register_accessor_init - sets up the register accessor callbacks
79 *
80 * @rdev: radeon device pointer
81 *
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
84 */
0a10c851
DV		 85static void radeon_register_accessor_init(struct radeon_device *rdev)
86{
87 rdev->mc_rreg = &radeon_invalid_rreg;
88 rdev->mc_wreg = &radeon_invalid_wreg;
89 rdev->pll_rreg = &radeon_invalid_rreg;
90 rdev->pll_wreg = &radeon_invalid_wreg;
91 rdev->pciep_rreg = &radeon_invalid_rreg;
92 rdev->pciep_wreg = &radeon_invalid_wreg;
93
94 /* Don't change order as we are overridding accessor. */
95 if (rdev->family < CHIP_RV515) {
96 rdev->pcie_reg_mask = 0xff;
97 } else {
98 rdev->pcie_reg_mask = 0x7ff;
99 }
100 /* FIXME: not sure here */
101 if (rdev->family <= CHIP_R580) {
102 rdev->pll_rreg = &r100_pll_rreg;
103 rdev->pll_wreg = &r100_pll_wreg;
104 }
105 if (rdev->family >= CHIP_R420) {
106 rdev->mc_rreg = &r420_mc_rreg;
107 rdev->mc_wreg = &r420_mc_wreg;
108 }
109 if (rdev->family >= CHIP_RV515) {
110 rdev->mc_rreg = &rv515_mc_rreg;
111 rdev->mc_wreg = &rv515_mc_wreg;
112 }
113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
114 rdev->mc_rreg = &rs400_mc_rreg;
115 rdev->mc_wreg = &rs400_mc_wreg;
116 }
117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
118 rdev->mc_rreg = &rs690_mc_rreg;
119 rdev->mc_wreg = &rs690_mc_wreg;
120 }
121 if (rdev->family == CHIP_RS600) {
122 rdev->mc_rreg = &rs600_mc_rreg;
123 rdev->mc_wreg = &rs600_mc_wreg;
124 }
65337e60
SL		 125 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
126 rdev->mc_rreg = &rs780_mc_rreg;
127 rdev->mc_wreg = &rs780_mc_wreg;
128 }
6e2c3c0a
AD		 129
130 if (rdev->family >= CHIP_BONAIRE) {
131 rdev->pciep_rreg = &cik_pciep_rreg;
132 rdev->pciep_wreg = &cik_pciep_wreg;
133 } else if (rdev->family >= CHIP_R600) {
0a10c851
DV		 134 rdev->pciep_rreg = &r600_pciep_rreg;
135 rdev->pciep_wreg = &r600_pciep_wreg;
136 }
137}
138
139
140/* helper to disable agp */
abf1dc67
AD		 141/**
142 * radeon_agp_disable - AGP disable helper function
143 *
144 * @rdev: radeon device pointer
145 *
146 * Removes AGP flags and changes the gart callbacks on AGP
147 * cards when using the internal gart rather than AGP (all asics).
148 */
0a10c851
DV		 149void radeon_agp_disable(struct radeon_device *rdev)
150{
151 rdev->flags &= ~RADEON_IS_AGP;
152 if (rdev->family >= CHIP_R600) {
153 DRM_INFO("Forcing AGP to PCIE mode\n");
154 rdev->flags |= RADEON_IS_PCIE;
155 } else if (rdev->family >= CHIP_RV515 ||
156 rdev->family == CHIP_RV380 ||
157 rdev->family == CHIP_RV410 ||
158 rdev->family == CHIP_R423) {
159 DRM_INFO("Forcing AGP to PCIE mode\n");
160 rdev->flags |= RADEON_IS_PCIE;
c5b3b850 161 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
cb658906 162 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
c5b3b850 163 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
0a10c851
DV		 164 } else {
165 DRM_INFO("Forcing AGP to PCI mode\n");
166 rdev->flags |= RADEON_IS_PCI;
c5b3b850 167 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
cb658906 168 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
c5b3b850 169 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
0a10c851
DV		 170 }
171 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
172}
173
174/*
175 * ASIC
176 */
76a0df85
CK		 177
178static struct radeon_asic_ring r100_gfx_ring = {
179 .ib_execute = &r100_ring_ib_execute,
180 .emit_fence = &r100_fence_ring_emit,
181 .emit_semaphore = &r100_semaphore_ring_emit,
182 .cs_parse = &r100_cs_parse,
183 .ring_start = &r100_ring_start,
184 .ring_test = &r100_ring_test,
185 .ib_test = &r100_ib_test,
186 .is_lockup = &r100_gpu_is_lockup,
ea31bf69
AD		 187 .get_rptr = &r100_gfx_get_rptr,
188 .get_wptr = &r100_gfx_get_wptr,
189 .set_wptr = &r100_gfx_set_wptr,
76a0df85
CK		 190};
191
48e7a5f1
DV		 192static struct radeon_asic r100_asic = {
193 .init = &r100_init,
194 .fini = &r100_fini,
195 .suspend = &r100_suspend,
196 .resume = &r100_resume,
197 .vga_set_state = &r100_vga_set_state,
a2d07b74 198 .asic_reset = &r100_asic_reset,
124764f1 199 .mmio_hdp_flush = NULL,
54e88e06
AD		 200 .gui_idle = &r100_gui_idle,
201 .mc_wait_for_idle = &r100_mc_wait_for_idle,
c5b3b850
AD		 202 .gart = {
203 .tlb_flush = &r100_pci_gart_tlb_flush,
cb658906 204 .get_page_entry = &r100_pci_gart_get_page_entry,
c5b3b850
AD		 205 .set_page = &r100_pci_gart_set_page,
206 },
4c87bc26 207 .ring = {
76a0df85 208 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
4c87bc26 209 },
b35ea4ab
AD		 210 .irq = {
211 .set = &r100_irq_set,
212 .process = &r100_irq_process,
213 },
c79a49ca
AD		 214 .display = {
215 .bandwidth_update = &r100_bandwidth_update,
216 .get_vblank_counter = &r100_get_vblank_counter,
217 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 218 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 219 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 220 },
27cd7769
AD		 221 .copy = {
222 .blit = &r100_copy_blit,
223 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
224 .dma = NULL,
225 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
226 .copy = &r100_copy_blit,
227 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
228 },
9e6f3d02
AD		 229 .surface = {
230 .set_reg = r100_set_surface_reg,
231 .clear_reg = r100_clear_surface_reg,
232 },
901ea57d
AD		 233 .hpd = {
234 .init = &r100_hpd_init,
235 .fini = &r100_hpd_fini,
236 .sense = &r100_hpd_sense,
237 .set_polarity = &r100_hpd_set_polarity,
238 },
a02fa397
AD		 239 .pm = {
240 .misc = &r100_pm_misc,
241 .prepare = &r100_pm_prepare,
242 .finish = &r100_pm_finish,
243 .init_profile = &r100_pm_init_profile,
244 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 245 .get_engine_clock = &radeon_legacy_get_engine_clock,
246 .set_engine_clock = &radeon_legacy_set_engine_clock,
247 .get_memory_clock = &radeon_legacy_get_memory_clock,
248 .set_memory_clock = NULL,
249 .get_pcie_lanes = NULL,
250 .set_pcie_lanes = NULL,
251 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 252 },
0f9e006c 253 .pflip = {
0f9e006c 254 .page_flip = &r100_page_flip,
157fa14d 255 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 256 },
48e7a5f1
DV		 257};
258
259static struct radeon_asic r200_asic = {
260 .init = &r100_init,
261 .fini = &r100_fini,
262 .suspend = &r100_suspend,
263 .resume = &r100_resume,
264 .vga_set_state = &r100_vga_set_state,
a2d07b74 265 .asic_reset = &r100_asic_reset,
124764f1 266 .mmio_hdp_flush = NULL,
54e88e06
AD		 267 .gui_idle = &r100_gui_idle,
268 .mc_wait_for_idle = &r100_mc_wait_for_idle,
c5b3b850
AD		 269 .gart = {
270 .tlb_flush = &r100_pci_gart_tlb_flush,
cb658906 271 .get_page_entry = &r100_pci_gart_get_page_entry,
c5b3b850
AD		 272 .set_page = &r100_pci_gart_set_page,
273 },
4c87bc26 274 .ring = {
76a0df85 275 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
4c87bc26 276 },
b35ea4ab
AD		 277 .irq = {
278 .set = &r100_irq_set,
279 .process = &r100_irq_process,
280 },
c79a49ca
AD		 281 .display = {
282 .bandwidth_update = &r100_bandwidth_update,
283 .get_vblank_counter = &r100_get_vblank_counter,
284 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 285 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 286 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 287 },
27cd7769
AD		 288 .copy = {
289 .blit = &r100_copy_blit,
290 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
291 .dma = &r200_copy_dma,
292 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
293 .copy = &r100_copy_blit,
294 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
295 },
9e6f3d02
AD		 296 .surface = {
297 .set_reg = r100_set_surface_reg,
298 .clear_reg = r100_clear_surface_reg,
299 },
901ea57d
AD		 300 .hpd = {
301 .init = &r100_hpd_init,
302 .fini = &r100_hpd_fini,
303 .sense = &r100_hpd_sense,
304 .set_polarity = &r100_hpd_set_polarity,
305 },
a02fa397
AD		 306 .pm = {
307 .misc = &r100_pm_misc,
308 .prepare = &r100_pm_prepare,
309 .finish = &r100_pm_finish,
310 .init_profile = &r100_pm_init_profile,
311 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 312 .get_engine_clock = &radeon_legacy_get_engine_clock,
313 .set_engine_clock = &radeon_legacy_set_engine_clock,
314 .get_memory_clock = &radeon_legacy_get_memory_clock,
315 .set_memory_clock = NULL,
316 .get_pcie_lanes = NULL,
317 .set_pcie_lanes = NULL,
318 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 319 },
0f9e006c 320 .pflip = {
0f9e006c 321 .page_flip = &r100_page_flip,
157fa14d 322 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 323 },
48e7a5f1
DV		 324};
325
76a0df85
CK		 326static struct radeon_asic_ring r300_gfx_ring = {
327 .ib_execute = &r100_ring_ib_execute,
328 .emit_fence = &r300_fence_ring_emit,
329 .emit_semaphore = &r100_semaphore_ring_emit,
330 .cs_parse = &r300_cs_parse,
331 .ring_start = &r300_ring_start,
332 .ring_test = &r100_ring_test,
333 .ib_test = &r100_ib_test,
334 .is_lockup = &r100_gpu_is_lockup,
ea31bf69
AD		 335 .get_rptr = &r100_gfx_get_rptr,
336 .get_wptr = &r100_gfx_get_wptr,
337 .set_wptr = &r100_gfx_set_wptr,
76a0df85
CK		 338};
339
d8a74e18
AD		 340static struct radeon_asic_ring rv515_gfx_ring = {
341 .ib_execute = &r100_ring_ib_execute,
342 .emit_fence = &r300_fence_ring_emit,
343 .emit_semaphore = &r100_semaphore_ring_emit,
344 .cs_parse = &r300_cs_parse,
345 .ring_start = &rv515_ring_start,
346 .ring_test = &r100_ring_test,
347 .ib_test = &r100_ib_test,
348 .is_lockup = &r100_gpu_is_lockup,
349 .get_rptr = &r100_gfx_get_rptr,
350 .get_wptr = &r100_gfx_get_wptr,
351 .set_wptr = &r100_gfx_set_wptr,
352};
353
48e7a5f1
DV		 354static struct radeon_asic r300_asic = {
355 .init = &r300_init,
356 .fini = &r300_fini,
357 .suspend = &r300_suspend,
358 .resume = &r300_resume,
359 .vga_set_state = &r100_vga_set_state,
a2d07b74 360 .asic_reset = &r300_asic_reset,
124764f1 361 .mmio_hdp_flush = NULL,
54e88e06
AD		 362 .gui_idle = &r100_gui_idle,
363 .mc_wait_for_idle = &r300_mc_wait_for_idle,
c5b3b850
AD		 364 .gart = {
365 .tlb_flush = &r100_pci_gart_tlb_flush,
cb658906 366 .get_page_entry = &r100_pci_gart_get_page_entry,
c5b3b850
AD		 367 .set_page = &r100_pci_gart_set_page,
368 },
4c87bc26 369 .ring = {
76a0df85 370 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 371 },
b35ea4ab
AD		 372 .irq = {
373 .set = &r100_irq_set,
374 .process = &r100_irq_process,
375 },
c79a49ca
AD		 376 .display = {
377 .bandwidth_update = &r100_bandwidth_update,
378 .get_vblank_counter = &r100_get_vblank_counter,
379 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 380 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 381 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 382 },
27cd7769
AD		 383 .copy = {
384 .blit = &r100_copy_blit,
385 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
386 .dma = &r200_copy_dma,
387 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
388 .copy = &r100_copy_blit,
389 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
390 },
9e6f3d02
AD		 391 .surface = {
392 .set_reg = r100_set_surface_reg,
393 .clear_reg = r100_clear_surface_reg,
394 },
901ea57d
AD		 395 .hpd = {
396 .init = &r100_hpd_init,
397 .fini = &r100_hpd_fini,
398 .sense = &r100_hpd_sense,
399 .set_polarity = &r100_hpd_set_polarity,
400 },
a02fa397
AD		 401 .pm = {
402 .misc = &r100_pm_misc,
403 .prepare = &r100_pm_prepare,
404 .finish = &r100_pm_finish,
405 .init_profile = &r100_pm_init_profile,
406 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 407 .get_engine_clock = &radeon_legacy_get_engine_clock,
408 .set_engine_clock = &radeon_legacy_set_engine_clock,
409 .get_memory_clock = &radeon_legacy_get_memory_clock,
410 .set_memory_clock = NULL,
411 .get_pcie_lanes = &rv370_get_pcie_lanes,
412 .set_pcie_lanes = &rv370_set_pcie_lanes,
413 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 414 },
0f9e006c 415 .pflip = {
0f9e006c 416 .page_flip = &r100_page_flip,
157fa14d 417 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 418 },
48e7a5f1
DV		 419};
420
421static struct radeon_asic r300_asic_pcie = {
422 .init = &r300_init,
423 .fini = &r300_fini,
424 .suspend = &r300_suspend,
425 .resume = &r300_resume,
426 .vga_set_state = &r100_vga_set_state,
a2d07b74 427 .asic_reset = &r300_asic_reset,
124764f1 428 .mmio_hdp_flush = NULL,
54e88e06
AD		 429 .gui_idle = &r100_gui_idle,
430 .mc_wait_for_idle = &r300_mc_wait_for_idle,
c5b3b850
AD		 431 .gart = {
432 .tlb_flush = &rv370_pcie_gart_tlb_flush,
cb658906 433 .get_page_entry = &rv370_pcie_gart_get_page_entry,
c5b3b850
AD		 434 .set_page = &rv370_pcie_gart_set_page,
435 },
4c87bc26 436 .ring = {
76a0df85 437 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 438 },
b35ea4ab
AD		 439 .irq = {
440 .set = &r100_irq_set,
441 .process = &r100_irq_process,
442 },
c79a49ca
AD		 443 .display = {
444 .bandwidth_update = &r100_bandwidth_update,
445 .get_vblank_counter = &r100_get_vblank_counter,
446 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 447 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 448 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 449 },
27cd7769
AD		 450 .copy = {
451 .blit = &r100_copy_blit,
452 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
453 .dma = &r200_copy_dma,
454 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
455 .copy = &r100_copy_blit,
456 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
457 },
9e6f3d02
AD		 458 .surface = {
459 .set_reg = r100_set_surface_reg,
460 .clear_reg = r100_clear_surface_reg,
461 },
901ea57d
AD		 462 .hpd = {
463 .init = &r100_hpd_init,
464 .fini = &r100_hpd_fini,
465 .sense = &r100_hpd_sense,
466 .set_polarity = &r100_hpd_set_polarity,
467 },
a02fa397
AD		 468 .pm = {
469 .misc = &r100_pm_misc,
470 .prepare = &r100_pm_prepare,
471 .finish = &r100_pm_finish,
472 .init_profile = &r100_pm_init_profile,
473 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 474 .get_engine_clock = &radeon_legacy_get_engine_clock,
475 .set_engine_clock = &radeon_legacy_set_engine_clock,
476 .get_memory_clock = &radeon_legacy_get_memory_clock,
477 .set_memory_clock = NULL,
478 .get_pcie_lanes = &rv370_get_pcie_lanes,
479 .set_pcie_lanes = &rv370_set_pcie_lanes,
480 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 481 },
0f9e006c 482 .pflip = {
0f9e006c 483 .page_flip = &r100_page_flip,
157fa14d 484 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 485 },
48e7a5f1
DV		 486};
487
488static struct radeon_asic r420_asic = {
489 .init = &r420_init,
490 .fini = &r420_fini,
491 .suspend = &r420_suspend,
492 .resume = &r420_resume,
493 .vga_set_state = &r100_vga_set_state,
a2d07b74 494 .asic_reset = &r300_asic_reset,
124764f1 495 .mmio_hdp_flush = NULL,
54e88e06
AD		 496 .gui_idle = &r100_gui_idle,
497 .mc_wait_for_idle = &r300_mc_wait_for_idle,
c5b3b850
AD		 498 .gart = {
499 .tlb_flush = &rv370_pcie_gart_tlb_flush,
cb658906 500 .get_page_entry = &rv370_pcie_gart_get_page_entry,
c5b3b850
AD		 501 .set_page = &rv370_pcie_gart_set_page,
502 },
4c87bc26 503 .ring = {
76a0df85 504 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 505 },
b35ea4ab
AD		 506 .irq = {
507 .set = &r100_irq_set,
508 .process = &r100_irq_process,
509 },
c79a49ca
AD		 510 .display = {
511 .bandwidth_update = &r100_bandwidth_update,
512 .get_vblank_counter = &r100_get_vblank_counter,
513 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 514 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 515 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 516 },
27cd7769
AD		 517 .copy = {
518 .blit = &r100_copy_blit,
519 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
520 .dma = &r200_copy_dma,
521 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
522 .copy = &r100_copy_blit,
523 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
524 },
9e6f3d02
AD		 525 .surface = {
526 .set_reg = r100_set_surface_reg,
527 .clear_reg = r100_clear_surface_reg,
528 },
901ea57d
AD		 529 .hpd = {
530 .init = &r100_hpd_init,
531 .fini = &r100_hpd_fini,
532 .sense = &r100_hpd_sense,
533 .set_polarity = &r100_hpd_set_polarity,
534 },
a02fa397
AD		 535 .pm = {
536 .misc = &r100_pm_misc,
537 .prepare = &r100_pm_prepare,
538 .finish = &r100_pm_finish,
539 .init_profile = &r420_pm_init_profile,
540 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 541 .get_engine_clock = &radeon_atom_get_engine_clock,
542 .set_engine_clock = &radeon_atom_set_engine_clock,
543 .get_memory_clock = &radeon_atom_get_memory_clock,
544 .set_memory_clock = &radeon_atom_set_memory_clock,
545 .get_pcie_lanes = &rv370_get_pcie_lanes,
546 .set_pcie_lanes = &rv370_set_pcie_lanes,
547 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 548 },
0f9e006c 549 .pflip = {
0f9e006c 550 .page_flip = &r100_page_flip,
157fa14d 551 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 552 },
48e7a5f1
DV		 553};
554
555static struct radeon_asic rs400_asic = {
556 .init = &rs400_init,
557 .fini = &rs400_fini,
558 .suspend = &rs400_suspend,
559 .resume = &rs400_resume,
560 .vga_set_state = &r100_vga_set_state,
a2d07b74 561 .asic_reset = &r300_asic_reset,
124764f1 562 .mmio_hdp_flush = NULL,
54e88e06
AD		 563 .gui_idle = &r100_gui_idle,
564 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
c5b3b850
AD		 565 .gart = {
566 .tlb_flush = &rs400_gart_tlb_flush,
cb658906 567 .get_page_entry = &rs400_gart_get_page_entry,
c5b3b850
AD		 568 .set_page = &rs400_gart_set_page,
569 },
4c87bc26 570 .ring = {
76a0df85 571 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 572 },
b35ea4ab
AD		 573 .irq = {
574 .set = &r100_irq_set,
575 .process = &r100_irq_process,
576 },
c79a49ca
AD		 577 .display = {
578 .bandwidth_update = &r100_bandwidth_update,
579 .get_vblank_counter = &r100_get_vblank_counter,
580 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 581 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 582 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 583 },
27cd7769
AD		 584 .copy = {
585 .blit = &r100_copy_blit,
586 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
587 .dma = &r200_copy_dma,
588 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
589 .copy = &r100_copy_blit,
590 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
591 },
9e6f3d02
AD		 592 .surface = {
593 .set_reg = r100_set_surface_reg,
594 .clear_reg = r100_clear_surface_reg,
595 },
901ea57d
AD		 596 .hpd = {
597 .init = &r100_hpd_init,
598 .fini = &r100_hpd_fini,
599 .sense = &r100_hpd_sense,
600 .set_polarity = &r100_hpd_set_polarity,
601 },
a02fa397
AD		 602 .pm = {
603 .misc = &r100_pm_misc,
604 .prepare = &r100_pm_prepare,
605 .finish = &r100_pm_finish,
606 .init_profile = &r100_pm_init_profile,
607 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 608 .get_engine_clock = &radeon_legacy_get_engine_clock,
609 .set_engine_clock = &radeon_legacy_set_engine_clock,
610 .get_memory_clock = &radeon_legacy_get_memory_clock,
611 .set_memory_clock = NULL,
612 .get_pcie_lanes = NULL,
613 .set_pcie_lanes = NULL,
614 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 615 },
0f9e006c 616 .pflip = {
0f9e006c 617 .page_flip = &r100_page_flip,
157fa14d 618 .page_flip_pending = &r100_page_flip_pending,
0f9e006c 619 },
48e7a5f1
DV		 620};
621
622static struct radeon_asic rs600_asic = {
623 .init = &rs600_init,
624 .fini = &rs600_fini,
625 .suspend = &rs600_suspend,
626 .resume = &rs600_resume,
627 .vga_set_state = &r100_vga_set_state,
90aca4d2 628 .asic_reset = &rs600_asic_reset,
124764f1 629 .mmio_hdp_flush = NULL,
54e88e06
AD		 630 .gui_idle = &r100_gui_idle,
631 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
c5b3b850
AD		 632 .gart = {
633 .tlb_flush = &rs600_gart_tlb_flush,
cb658906 634 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 635 .set_page = &rs600_gart_set_page,
636 },
4c87bc26 637 .ring = {
76a0df85 638 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 639 },
b35ea4ab
AD		 640 .irq = {
641 .set = &rs600_irq_set,
642 .process = &rs600_irq_process,
643 },
c79a49ca
AD		 644 .display = {
645 .bandwidth_update = &rs600_bandwidth_update,
646 .get_vblank_counter = &rs600_get_vblank_counter,
647 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 648 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 649 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 650 },
27cd7769
AD		 651 .copy = {
652 .blit = &r100_copy_blit,
653 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
654 .dma = &r200_copy_dma,
655 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
656 .copy = &r100_copy_blit,
657 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
658 },
9e6f3d02
AD		 659 .surface = {
660 .set_reg = r100_set_surface_reg,
661 .clear_reg = r100_clear_surface_reg,
662 },
901ea57d
AD		 663 .hpd = {
664 .init = &rs600_hpd_init,
665 .fini = &rs600_hpd_fini,
666 .sense = &rs600_hpd_sense,
667 .set_polarity = &rs600_hpd_set_polarity,
668 },
a02fa397
AD		 669 .pm = {
670 .misc = &rs600_pm_misc,
671 .prepare = &rs600_pm_prepare,
672 .finish = &rs600_pm_finish,
673 .init_profile = &r420_pm_init_profile,
674 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 675 .get_engine_clock = &radeon_atom_get_engine_clock,
676 .set_engine_clock = &radeon_atom_set_engine_clock,
677 .get_memory_clock = &radeon_atom_get_memory_clock,
678 .set_memory_clock = &radeon_atom_set_memory_clock,
679 .get_pcie_lanes = NULL,
680 .set_pcie_lanes = NULL,
681 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 682 },
0f9e006c 683 .pflip = {
0f9e006c 684 .page_flip = &rs600_page_flip,
157fa14d 685 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 686 },
48e7a5f1
DV		 687};
688
689static struct radeon_asic rs690_asic = {
690 .init = &rs690_init,
691 .fini = &rs690_fini,
692 .suspend = &rs690_suspend,
693 .resume = &rs690_resume,
694 .vga_set_state = &r100_vga_set_state,
90aca4d2 695 .asic_reset = &rs600_asic_reset,
124764f1 696 .mmio_hdp_flush = NULL,
54e88e06
AD		 697 .gui_idle = &r100_gui_idle,
698 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
c5b3b850
AD		 699 .gart = {
700 .tlb_flush = &rs400_gart_tlb_flush,
cb658906 701 .get_page_entry = &rs400_gart_get_page_entry,
c5b3b850
AD		 702 .set_page = &rs400_gart_set_page,
703 },
4c87bc26 704 .ring = {
76a0df85 705 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 706 },
b35ea4ab
AD		 707 .irq = {
708 .set = &rs600_irq_set,
709 .process = &rs600_irq_process,
710 },
c79a49ca
AD		 711 .display = {
712 .get_vblank_counter = &rs600_get_vblank_counter,
713 .bandwidth_update = &rs690_bandwidth_update,
714 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 715 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 716 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 717 },
27cd7769
AD		 718 .copy = {
719 .blit = &r100_copy_blit,
720 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
721 .dma = &r200_copy_dma,
722 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
723 .copy = &r200_copy_dma,
724 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
725 },
9e6f3d02
AD		 726 .surface = {
727 .set_reg = r100_set_surface_reg,
728 .clear_reg = r100_clear_surface_reg,
729 },
901ea57d
AD		 730 .hpd = {
731 .init = &rs600_hpd_init,
732 .fini = &rs600_hpd_fini,
733 .sense = &rs600_hpd_sense,
734 .set_polarity = &rs600_hpd_set_polarity,
735 },
a02fa397
AD		 736 .pm = {
737 .misc = &rs600_pm_misc,
738 .prepare = &rs600_pm_prepare,
739 .finish = &rs600_pm_finish,
740 .init_profile = &r420_pm_init_profile,
741 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 742 .get_engine_clock = &radeon_atom_get_engine_clock,
743 .set_engine_clock = &radeon_atom_set_engine_clock,
744 .get_memory_clock = &radeon_atom_get_memory_clock,
745 .set_memory_clock = &radeon_atom_set_memory_clock,
746 .get_pcie_lanes = NULL,
747 .set_pcie_lanes = NULL,
748 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 749 },
0f9e006c 750 .pflip = {
0f9e006c 751 .page_flip = &rs600_page_flip,
157fa14d 752 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 753 },
48e7a5f1
DV		 754};
755
756static struct radeon_asic rv515_asic = {
757 .init = &rv515_init,
758 .fini = &rv515_fini,
759 .suspend = &rv515_suspend,
760 .resume = &rv515_resume,
761 .vga_set_state = &r100_vga_set_state,
90aca4d2 762 .asic_reset = &rs600_asic_reset,
124764f1 763 .mmio_hdp_flush = NULL,
54e88e06
AD		 764 .gui_idle = &r100_gui_idle,
765 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
c5b3b850
AD		 766 .gart = {
767 .tlb_flush = &rv370_pcie_gart_tlb_flush,
cb658906 768 .get_page_entry = &rv370_pcie_gart_get_page_entry,
c5b3b850
AD		 769 .set_page = &rv370_pcie_gart_set_page,
770 },
4c87bc26 771 .ring = {
d8a74e18 772 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
4c87bc26 773 },
b35ea4ab
AD		 774 .irq = {
775 .set = &rs600_irq_set,
776 .process = &rs600_irq_process,
777 },
c79a49ca
AD		 778 .display = {
779 .get_vblank_counter = &rs600_get_vblank_counter,
780 .bandwidth_update = &rv515_bandwidth_update,
781 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 782 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 783 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 784 },
27cd7769
AD		 785 .copy = {
786 .blit = &r100_copy_blit,
787 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
788 .dma = &r200_copy_dma,
789 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
790 .copy = &r100_copy_blit,
791 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
792 },
9e6f3d02
AD		 793 .surface = {
794 .set_reg = r100_set_surface_reg,
795 .clear_reg = r100_clear_surface_reg,
796 },
901ea57d
AD		 797 .hpd = {
798 .init = &rs600_hpd_init,
799 .fini = &rs600_hpd_fini,
800 .sense = &rs600_hpd_sense,
801 .set_polarity = &rs600_hpd_set_polarity,
802 },
a02fa397
AD		 803 .pm = {
804 .misc = &rs600_pm_misc,
805 .prepare = &rs600_pm_prepare,
806 .finish = &rs600_pm_finish,
807 .init_profile = &r420_pm_init_profile,
808 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 809 .get_engine_clock = &radeon_atom_get_engine_clock,
810 .set_engine_clock = &radeon_atom_set_engine_clock,
811 .get_memory_clock = &radeon_atom_get_memory_clock,
812 .set_memory_clock = &radeon_atom_set_memory_clock,
813 .get_pcie_lanes = &rv370_get_pcie_lanes,
814 .set_pcie_lanes = &rv370_set_pcie_lanes,
815 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 816 },
0f9e006c 817 .pflip = {
0f9e006c 818 .page_flip = &rs600_page_flip,
157fa14d 819 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 820 },
48e7a5f1
DV		 821};
822
823static struct radeon_asic r520_asic = {
824 .init = &r520_init,
825 .fini = &rv515_fini,
826 .suspend = &rv515_suspend,
827 .resume = &r520_resume,
828 .vga_set_state = &r100_vga_set_state,
90aca4d2 829 .asic_reset = &rs600_asic_reset,
124764f1 830 .mmio_hdp_flush = NULL,
54e88e06
AD		 831 .gui_idle = &r100_gui_idle,
832 .mc_wait_for_idle = &r520_mc_wait_for_idle,
c5b3b850
AD		 833 .gart = {
834 .tlb_flush = &rv370_pcie_gart_tlb_flush,
cb658906 835 .get_page_entry = &rv370_pcie_gart_get_page_entry,
c5b3b850
AD		 836 .set_page = &rv370_pcie_gart_set_page,
837 },
4c87bc26 838 .ring = {
d8a74e18 839 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
4c87bc26 840 },
b35ea4ab
AD		 841 .irq = {
842 .set = &rs600_irq_set,
843 .process = &rs600_irq_process,
844 },
c79a49ca
AD		 845 .display = {
846 .bandwidth_update = &rv515_bandwidth_update,
847 .get_vblank_counter = &rs600_get_vblank_counter,
848 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 849 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 850 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 851 },
27cd7769
AD		 852 .copy = {
853 .blit = &r100_copy_blit,
854 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
855 .dma = &r200_copy_dma,
856 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
857 .copy = &r100_copy_blit,
858 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
859 },
9e6f3d02
AD		 860 .surface = {
861 .set_reg = r100_set_surface_reg,
862 .clear_reg = r100_clear_surface_reg,
863 },
901ea57d
AD		 864 .hpd = {
865 .init = &rs600_hpd_init,
866 .fini = &rs600_hpd_fini,
867 .sense = &rs600_hpd_sense,
868 .set_polarity = &rs600_hpd_set_polarity,
869 },
a02fa397
AD		 870 .pm = {
871 .misc = &rs600_pm_misc,
872 .prepare = &rs600_pm_prepare,
873 .finish = &rs600_pm_finish,
874 .init_profile = &r420_pm_init_profile,
875 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 876 .get_engine_clock = &radeon_atom_get_engine_clock,
877 .set_engine_clock = &radeon_atom_set_engine_clock,
878 .get_memory_clock = &radeon_atom_get_memory_clock,
879 .set_memory_clock = &radeon_atom_set_memory_clock,
880 .get_pcie_lanes = &rv370_get_pcie_lanes,
881 .set_pcie_lanes = &rv370_set_pcie_lanes,
882 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 883 },
0f9e006c 884 .pflip = {
0f9e006c 885 .page_flip = &rs600_page_flip,
157fa14d 886 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 887 },
48e7a5f1
DV		 888};
889
76a0df85
CK		 890static struct radeon_asic_ring r600_gfx_ring = {
891 .ib_execute = &r600_ring_ib_execute,
892 .emit_fence = &r600_fence_ring_emit,
893 .emit_semaphore = &r600_semaphore_ring_emit,
894 .cs_parse = &r600_cs_parse,
895 .ring_test = &r600_ring_test,
896 .ib_test = &r600_ib_test,
897 .is_lockup = &r600_gfx_is_lockup,
ea31bf69
AD		 898 .get_rptr = &r600_gfx_get_rptr,
899 .get_wptr = &r600_gfx_get_wptr,
900 .set_wptr = &r600_gfx_set_wptr,
76a0df85
CK		 901};
902
903static struct radeon_asic_ring r600_dma_ring = {
904 .ib_execute = &r600_dma_ring_ib_execute,
905 .emit_fence = &r600_dma_fence_ring_emit,
906 .emit_semaphore = &r600_dma_semaphore_ring_emit,
907 .cs_parse = &r600_dma_cs_parse,
908 .ring_test = &r600_dma_ring_test,
909 .ib_test = &r600_dma_ib_test,
910 .is_lockup = &r600_dma_is_lockup,
2e1e6dad
CK		 911 .get_rptr = &r600_dma_get_rptr,
912 .get_wptr = &r600_dma_get_wptr,
913 .set_wptr = &r600_dma_set_wptr,
76a0df85
CK		 914};
915
48e7a5f1
DV		 916static struct radeon_asic r600_asic = {
917 .init = &r600_init,
918 .fini = &r600_fini,
919 .suspend = &r600_suspend,
920 .resume = &r600_resume,
48e7a5f1 921 .vga_set_state = &r600_vga_set_state,
a2d07b74 922 .asic_reset = &r600_asic_reset,
124764f1 923 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 924 .gui_idle = &r600_gui_idle,
925 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 926 .get_xclk = &r600_get_xclk,
d0418894 927 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 928 .gart = {
929 .tlb_flush = &r600_pcie_gart_tlb_flush,
cb658906 930 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 931 .set_page = &rs600_gart_set_page,
932 },
4c87bc26 933 .ring = {
76a0df85
CK		 934 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
935 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
4c87bc26 936 },
b35ea4ab
AD		 937 .irq = {
938 .set = &r600_irq_set,
939 .process = &r600_irq_process,
940 },
c79a49ca
AD		 941 .display = {
942 .bandwidth_update = &rv515_bandwidth_update,
943 .get_vblank_counter = &rs600_get_vblank_counter,
944 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 945 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 946 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 947 },
27cd7769 948 .copy = {
8dddb993 949 .blit = &r600_copy_cpdma,
27cd7769 950 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
4d75658b
AD		 951 .dma = &r600_copy_dma,
952 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
bfea6a68 953 .copy = &r600_copy_cpdma,
aeea40cb 954 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
27cd7769 955 },
9e6f3d02
AD		 956 .surface = {
957 .set_reg = r600_set_surface_reg,
958 .clear_reg = r600_clear_surface_reg,
959 },
901ea57d
AD		 960 .hpd = {
961 .init = &r600_hpd_init,
962 .fini = &r600_hpd_fini,
963 .sense = &r600_hpd_sense,
964 .set_polarity = &r600_hpd_set_polarity,
965 },
a02fa397
AD		 966 .pm = {
967 .misc = &r600_pm_misc,
968 .prepare = &rs600_pm_prepare,
969 .finish = &rs600_pm_finish,
970 .init_profile = &r600_pm_init_profile,
971 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 972 .get_engine_clock = &radeon_atom_get_engine_clock,
973 .set_engine_clock = &radeon_atom_set_engine_clock,
974 .get_memory_clock = &radeon_atom_get_memory_clock,
975 .set_memory_clock = &radeon_atom_set_memory_clock,
976 .get_pcie_lanes = &r600_get_pcie_lanes,
977 .set_pcie_lanes = &r600_set_pcie_lanes,
978 .set_clock_gating = NULL,
6bd1c385 979 .get_temperature = &rv6xx_get_temp,
a02fa397 980 },
0f9e006c 981 .pflip = {
0f9e006c 982 .page_flip = &rs600_page_flip,
157fa14d 983 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 984 },
48e7a5f1
DV		 985};
986
856754c3
CK		 987static struct radeon_asic_ring rv6xx_uvd_ring = {
988 .ib_execute = &uvd_v1_0_ib_execute,
989 .emit_fence = &uvd_v1_0_fence_emit,
990 .emit_semaphore = &uvd_v1_0_semaphore_emit,
991 .cs_parse = &radeon_uvd_cs_parse,
992 .ring_test = &uvd_v1_0_ring_test,
993 .ib_test = &uvd_v1_0_ib_test,
994 .is_lockup = &radeon_ring_test_lockup,
995 .get_rptr = &uvd_v1_0_get_rptr,
996 .get_wptr = &uvd_v1_0_get_wptr,
997 .set_wptr = &uvd_v1_0_set_wptr,
998};
999
ca361b65
AD		 1000static struct radeon_asic rv6xx_asic = {
1001 .init = &r600_init,
1002 .fini = &r600_fini,
1003 .suspend = &r600_suspend,
1004 .resume = &r600_resume,
1005 .vga_set_state = &r600_vga_set_state,
1006 .asic_reset = &r600_asic_reset,
124764f1 1007 .mmio_hdp_flush = r600_mmio_hdp_flush,
ca361b65
AD		 1008 .gui_idle = &r600_gui_idle,
1009 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1010 .get_xclk = &r600_get_xclk,
1011 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1012 .gart = {
1013 .tlb_flush = &r600_pcie_gart_tlb_flush,
cb658906 1014 .get_page_entry = &rs600_gart_get_page_entry,
ca361b65
AD		 1015 .set_page = &rs600_gart_set_page,
1016 },
1017 .ring = {
76a0df85
CK		 1018 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1019 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
856754c3 1020 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
ca361b65
AD		 1021 },
1022 .irq = {
1023 .set = &r600_irq_set,
1024 .process = &r600_irq_process,
1025 },
1026 .display = {
1027 .bandwidth_update = &rv515_bandwidth_update,
1028 .get_vblank_counter = &rs600_get_vblank_counter,
1029 .wait_for_vblank = &avivo_wait_for_vblank,
1030 .set_backlight_level = &atombios_set_backlight_level,
1031 .get_backlight_level = &atombios_get_backlight_level,
1032 },
1033 .copy = {
8dddb993 1034 .blit = &r600_copy_cpdma,
ca361b65
AD		 1035 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1036 .dma = &r600_copy_dma,
1037 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
bfea6a68 1038 .copy = &r600_copy_cpdma,
aeea40cb 1039 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
ca361b65
AD		 1040 },
1041 .surface = {
1042 .set_reg = r600_set_surface_reg,
1043 .clear_reg = r600_clear_surface_reg,
1044 },
1045 .hpd = {
1046 .init = &r600_hpd_init,
1047 .fini = &r600_hpd_fini,
1048 .sense = &r600_hpd_sense,
1049 .set_polarity = &r600_hpd_set_polarity,
1050 },
1051 .pm = {
1052 .misc = &r600_pm_misc,
1053 .prepare = &rs600_pm_prepare,
1054 .finish = &rs600_pm_finish,
1055 .init_profile = &r600_pm_init_profile,
1056 .get_dynpm_state = &r600_pm_get_dynpm_state,
1057 .get_engine_clock = &radeon_atom_get_engine_clock,
1058 .set_engine_clock = &radeon_atom_set_engine_clock,
1059 .get_memory_clock = &radeon_atom_get_memory_clock,
1060 .set_memory_clock = &radeon_atom_set_memory_clock,
1061 .get_pcie_lanes = &r600_get_pcie_lanes,
1062 .set_pcie_lanes = &r600_set_pcie_lanes,
1063 .set_clock_gating = NULL,
1064 .get_temperature = &rv6xx_get_temp,
1b9ba70a 1065 .set_uvd_clocks = &r600_set_uvd_clocks,
ca361b65 1066 },
4a6369e9
AD		 1067 .dpm = {
1068 .init = &rv6xx_dpm_init,
1069 .setup_asic = &rv6xx_setup_asic,
1070 .enable = &rv6xx_dpm_enable,
a4643ba3 1071 .late_enable = &r600_dpm_late_enable,
4a6369e9 1072 .disable = &rv6xx_dpm_disable,
98243917 1073 .pre_set_power_state = &r600_dpm_pre_set_power_state,
4a6369e9 1074 .set_power_state = &rv6xx_dpm_set_power_state,
98243917 1075 .post_set_power_state = &r600_dpm_post_set_power_state,
4a6369e9
AD		 1076 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1077 .fini = &rv6xx_dpm_fini,
1078 .get_sclk = &rv6xx_dpm_get_sclk,
1079 .get_mclk = &rv6xx_dpm_get_mclk,
1080 .print_power_state = &rv6xx_dpm_print_power_state,
242916a5 1081 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
f4f85a8c 1082 .force_performance_level = &rv6xx_dpm_force_performance_level,
d0a04d3b
AD		 1083 .get_current_sclk = &rv6xx_dpm_get_current_sclk,
1084 .get_current_mclk = &rv6xx_dpm_get_current_mclk,
4a6369e9 1085 },
ca361b65 1086 .pflip = {
ca361b65 1087 .page_flip = &rs600_page_flip,
157fa14d 1088 .page_flip_pending = &rs600_page_flip_pending,
ca361b65
AD		 1089 },
1090};
1091
f47299c5
AD		 1092static struct radeon_asic rs780_asic = {
1093 .init = &r600_init,
1094 .fini = &r600_fini,
1095 .suspend = &r600_suspend,
1096 .resume = &r600_resume,
f47299c5 1097 .vga_set_state = &r600_vga_set_state,
a2d07b74 1098 .asic_reset = &r600_asic_reset,
124764f1 1099 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1100 .gui_idle = &r600_gui_idle,
1101 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 1102 .get_xclk = &r600_get_xclk,
d0418894 1103 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1104 .gart = {
1105 .tlb_flush = &r600_pcie_gart_tlb_flush,
cb658906 1106 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 1107 .set_page = &rs600_gart_set_page,
1108 },
4c87bc26 1109 .ring = {
76a0df85
CK		 1110 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1111 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
856754c3 1112 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
4c87bc26 1113 },
b35ea4ab
AD		 1114 .irq = {
1115 .set = &r600_irq_set,
1116 .process = &r600_irq_process,
1117 },
c79a49ca
AD		 1118 .display = {
1119 .bandwidth_update = &rs690_bandwidth_update,
1120 .get_vblank_counter = &rs600_get_vblank_counter,
1121 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 1122 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1123 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 1124 },
27cd7769 1125 .copy = {
8dddb993 1126 .blit = &r600_copy_cpdma,
27cd7769 1127 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
4d75658b
AD		 1128 .dma = &r600_copy_dma,
1129 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
bfea6a68 1130 .copy = &r600_copy_cpdma,
aeea40cb 1131 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
27cd7769 1132 },
9e6f3d02
AD		 1133 .surface = {
1134 .set_reg = r600_set_surface_reg,
1135 .clear_reg = r600_clear_surface_reg,
1136 },
901ea57d
AD		 1137 .hpd = {
1138 .init = &r600_hpd_init,
1139 .fini = &r600_hpd_fini,
1140 .sense = &r600_hpd_sense,
1141 .set_polarity = &r600_hpd_set_polarity,
1142 },
a02fa397
AD		 1143 .pm = {
1144 .misc = &r600_pm_misc,
1145 .prepare = &rs600_pm_prepare,
1146 .finish = &rs600_pm_finish,
1147 .init_profile = &rs780_pm_init_profile,
1148 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1149 .get_engine_clock = &radeon_atom_get_engine_clock,
1150 .set_engine_clock = &radeon_atom_set_engine_clock,
1151 .get_memory_clock = NULL,
1152 .set_memory_clock = NULL,
1153 .get_pcie_lanes = NULL,
1154 .set_pcie_lanes = NULL,
1155 .set_clock_gating = NULL,
6bd1c385 1156 .get_temperature = &rv6xx_get_temp,
1b9ba70a 1157 .set_uvd_clocks = &r600_set_uvd_clocks,
a02fa397 1158 },
9d67006e
AD		 1159 .dpm = {
1160 .init = &rs780_dpm_init,
1161 .setup_asic = &rs780_dpm_setup_asic,
1162 .enable = &rs780_dpm_enable,
a4643ba3 1163 .late_enable = &r600_dpm_late_enable,
9d67006e 1164 .disable = &rs780_dpm_disable,
98243917 1165 .pre_set_power_state = &r600_dpm_pre_set_power_state,
9d67006e 1166 .set_power_state = &rs780_dpm_set_power_state,
98243917 1167 .post_set_power_state = &r600_dpm_post_set_power_state,
9d67006e
AD		 1168 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1169 .fini = &rs780_dpm_fini,
1170 .get_sclk = &rs780_dpm_get_sclk,
1171 .get_mclk = &rs780_dpm_get_mclk,
1172 .print_power_state = &rs780_dpm_print_power_state,
444bddc4 1173 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
63580c3e 1174 .force_performance_level = &rs780_dpm_force_performance_level,
3c94566c
AD		 1175 .get_current_sclk = &rs780_dpm_get_current_sclk,
1176 .get_current_mclk = &rs780_dpm_get_current_mclk,
9d67006e 1177 },
0f9e006c 1178 .pflip = {
0f9e006c 1179 .page_flip = &rs600_page_flip,
157fa14d 1180 .page_flip_pending = &rs600_page_flip_pending,
0f9e006c 1181 },
f47299c5
AD		 1182};
1183
76a0df85 1184static struct radeon_asic_ring rv770_uvd_ring = {
e409b128
CK		 1185 .ib_execute = &uvd_v1_0_ib_execute,
1186 .emit_fence = &uvd_v2_2_fence_emit,
1187 .emit_semaphore = &uvd_v1_0_semaphore_emit,
76a0df85 1188 .cs_parse = &radeon_uvd_cs_parse,
e409b128
CK		 1189 .ring_test = &uvd_v1_0_ring_test,
1190 .ib_test = &uvd_v1_0_ib_test,
76a0df85 1191 .is_lockup = &radeon_ring_test_lockup,
e409b128
CK		 1192 .get_rptr = &uvd_v1_0_get_rptr,
1193 .get_wptr = &uvd_v1_0_get_wptr,
1194 .set_wptr = &uvd_v1_0_set_wptr,
76a0df85
CK		 1195};
1196
48e7a5f1
DV		 1197static struct radeon_asic rv770_asic = {
1198 .init = &rv770_init,
1199 .fini = &rv770_fini,
1200 .suspend = &rv770_suspend,
1201 .resume = &rv770_resume,
a2d07b74 1202 .asic_reset = &r600_asic_reset,
48e7a5f1 1203 .vga_set_state = &r600_vga_set_state,
124764f1 1204 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1205 .gui_idle = &r600_gui_idle,
1206 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 1207 .get_xclk = &rv770_get_xclk,
d0418894 1208 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1209 .gart = {
1210 .tlb_flush = &r600_pcie_gart_tlb_flush,
cb658906 1211 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 1212 .set_page = &rs600_gart_set_page,
1213 },
4c87bc26 1214 .ring = {
76a0df85
CK		 1215 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1216 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1217 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1218 },
b35ea4ab
AD		 1219 .irq = {
1220 .set = &r600_irq_set,
1221 .process = &r600_irq_process,
1222 },
c79a49ca
AD		 1223 .display = {
1224 .bandwidth_update = &rv515_bandwidth_update,
1225 .get_vblank_counter = &rs600_get_vblank_counter,
1226 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 1227 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1228 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 1229 },
27cd7769 1230 .copy = {
8dddb993 1231 .blit = &r600_copy_cpdma,
27cd7769 1232 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
43fb7787 1233 .dma = &rv770_copy_dma,
4d75658b 1234 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
43fb7787 1235 .copy = &rv770_copy_dma,
2d6cc729 1236 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1237 },
9e6f3d02
AD		 1238 .surface = {
1239 .set_reg = r600_set_surface_reg,
1240 .clear_reg = r600_clear_surface_reg,
1241 },
901ea57d
AD		 1242 .hpd = {
1243 .init = &r600_hpd_init,
1244 .fini = &r600_hpd_fini,
1245 .sense = &r600_hpd_sense,
1246 .set_polarity = &r600_hpd_set_polarity,
1247 },
a02fa397
AD		 1248 .pm = {
1249 .misc = &rv770_pm_misc,
1250 .prepare = &rs600_pm_prepare,
1251 .finish = &rs600_pm_finish,
1252 .init_profile = &r600_pm_init_profile,
1253 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1254 .get_engine_clock = &radeon_atom_get_engine_clock,
1255 .set_engine_clock = &radeon_atom_set_engine_clock,
1256 .get_memory_clock = &radeon_atom_get_memory_clock,
1257 .set_memory_clock = &radeon_atom_set_memory_clock,
1258 .get_pcie_lanes = &r600_get_pcie_lanes,
1259 .set_pcie_lanes = &r600_set_pcie_lanes,
1260 .set_clock_gating = &radeon_atom_set_clock_gating,
ef0e6e65 1261 .set_uvd_clocks = &rv770_set_uvd_clocks,
6bd1c385 1262 .get_temperature = &rv770_get_temp,
a02fa397 1263 },
66229b20
AD		 1264 .dpm = {
1265 .init = &rv770_dpm_init,
1266 .setup_asic = &rv770_dpm_setup_asic,
1267 .enable = &rv770_dpm_enable,
a3f11245 1268 .late_enable = &rv770_dpm_late_enable,
66229b20 1269 .disable = &rv770_dpm_disable,
98243917 1270 .pre_set_power_state = &r600_dpm_pre_set_power_state,
66229b20 1271 .set_power_state = &rv770_dpm_set_power_state,
98243917 1272 .post_set_power_state = &r600_dpm_post_set_power_state,
66229b20
AD		 1273 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1274 .fini = &rv770_dpm_fini,
1275 .get_sclk = &rv770_dpm_get_sclk,
1276 .get_mclk = &rv770_dpm_get_mclk,
1277 .print_power_state = &rv770_dpm_print_power_state,
bd210d11 1278 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
8b5e6b7f 1279 .force_performance_level = &rv770_dpm_force_performance_level,
b06195d9 1280 .vblank_too_short = &rv770_dpm_vblank_too_short,
296deb71
AD		 1281 .get_current_sclk = &rv770_dpm_get_current_sclk,
1282 .get_current_mclk = &rv770_dpm_get_current_mclk,
66229b20 1283 },
0f9e006c 1284 .pflip = {
0f9e006c 1285 .page_flip = &rv770_page_flip,
157fa14d 1286 .page_flip_pending = &rv770_page_flip_pending,
0f9e006c 1287 },
48e7a5f1
DV		 1288};
1289
76a0df85
CK		 1290static struct radeon_asic_ring evergreen_gfx_ring = {
1291 .ib_execute = &evergreen_ring_ib_execute,
1292 .emit_fence = &r600_fence_ring_emit,
1293 .emit_semaphore = &r600_semaphore_ring_emit,
1294 .cs_parse = &evergreen_cs_parse,
1295 .ring_test = &r600_ring_test,
1296 .ib_test = &r600_ib_test,
1297 .is_lockup = &evergreen_gfx_is_lockup,
ea31bf69
AD		 1298 .get_rptr = &r600_gfx_get_rptr,
1299 .get_wptr = &r600_gfx_get_wptr,
1300 .set_wptr = &r600_gfx_set_wptr,
76a0df85
CK		 1301};
1302
1303static struct radeon_asic_ring evergreen_dma_ring = {
1304 .ib_execute = &evergreen_dma_ring_ib_execute,
1305 .emit_fence = &evergreen_dma_fence_ring_emit,
1306 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1307 .cs_parse = &evergreen_dma_cs_parse,
1308 .ring_test = &r600_dma_ring_test,
1309 .ib_test = &r600_dma_ib_test,
1310 .is_lockup = &evergreen_dma_is_lockup,
2e1e6dad
CK		 1311 .get_rptr = &r600_dma_get_rptr,
1312 .get_wptr = &r600_dma_get_wptr,
1313 .set_wptr = &r600_dma_set_wptr,
76a0df85
CK		 1314};
1315
48e7a5f1
DV		 1316static struct radeon_asic evergreen_asic = {
1317 .init = &evergreen_init,
1318 .fini = &evergreen_fini,
1319 .suspend = &evergreen_suspend,
1320 .resume = &evergreen_resume,
a2d07b74 1321 .asic_reset = &evergreen_asic_reset,
48e7a5f1 1322 .vga_set_state = &r600_vga_set_state,
124764f1 1323 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1324 .gui_idle = &r600_gui_idle,
1325 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1326 .get_xclk = &rv770_get_xclk,
d0418894 1327 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1328 .gart = {
1329 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
cb658906 1330 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 1331 .set_page = &rs600_gart_set_page,
1332 },
4c87bc26 1333 .ring = {
76a0df85
CK		 1334 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1335 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1336 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1337 },
b35ea4ab
AD		 1338 .irq = {
1339 .set = &evergreen_irq_set,
1340 .process = &evergreen_irq_process,
1341 },
c79a49ca
AD		 1342 .display = {
1343 .bandwidth_update = &evergreen_bandwidth_update,
1344 .get_vblank_counter = &evergreen_get_vblank_counter,
1345 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1346 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1347 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 1348 },
27cd7769 1349 .copy = {
8dddb993 1350 .blit = &r600_copy_cpdma,
27cd7769 1351 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1352 .dma = &evergreen_copy_dma,
1353 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1354 .copy = &evergreen_copy_dma,
1355 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1356 },
9e6f3d02
AD		 1357 .surface = {
1358 .set_reg = r600_set_surface_reg,
1359 .clear_reg = r600_clear_surface_reg,
1360 },
901ea57d
AD		 1361 .hpd = {
1362 .init = &evergreen_hpd_init,
1363 .fini = &evergreen_hpd_fini,
1364 .sense = &evergreen_hpd_sense,
1365 .set_polarity = &evergreen_hpd_set_polarity,
1366 },
a02fa397
AD		 1367 .pm = {
1368 .misc = &evergreen_pm_misc,
1369 .prepare = &evergreen_pm_prepare,
1370 .finish = &evergreen_pm_finish,
1371 .init_profile = &r600_pm_init_profile,
1372 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1373 .get_engine_clock = &radeon_atom_get_engine_clock,
1374 .set_engine_clock = &radeon_atom_set_engine_clock,
1375 .get_memory_clock = &radeon_atom_get_memory_clock,
1376 .set_memory_clock = &radeon_atom_set_memory_clock,
1377 .get_pcie_lanes = &r600_get_pcie_lanes,
1378 .set_pcie_lanes = &r600_set_pcie_lanes,
1379 .set_clock_gating = NULL,
a8b4925c 1380 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1381 .get_temperature = &evergreen_get_temp,
a02fa397 1382 },
dc50ba7f
AD		 1383 .dpm = {
1384 .init = &cypress_dpm_init,
1385 .setup_asic = &cypress_dpm_setup_asic,
1386 .enable = &cypress_dpm_enable,
a3f11245 1387 .late_enable = &rv770_dpm_late_enable,
dc50ba7f 1388 .disable = &cypress_dpm_disable,
98243917 1389 .pre_set_power_state = &r600_dpm_pre_set_power_state,
dc50ba7f 1390 .set_power_state = &cypress_dpm_set_power_state,
98243917 1391 .post_set_power_state = &r600_dpm_post_set_power_state,
dc50ba7f
AD		 1392 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1393 .fini = &cypress_dpm_fini,
1394 .get_sclk = &rv770_dpm_get_sclk,
1395 .get_mclk = &rv770_dpm_get_mclk,
1396 .print_power_state = &rv770_dpm_print_power_state,
bd210d11 1397 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
8b5e6b7f 1398 .force_performance_level = &rv770_dpm_force_performance_level,
d0b54bdc 1399 .vblank_too_short = &cypress_dpm_vblank_too_short,
296deb71
AD		 1400 .get_current_sclk = &rv770_dpm_get_current_sclk,
1401 .get_current_mclk = &rv770_dpm_get_current_mclk,
dc50ba7f 1402 },
0f9e006c 1403 .pflip = {
0f9e006c 1404 .page_flip = &evergreen_page_flip,
157fa14d 1405 .page_flip_pending = &evergreen_page_flip_pending,
0f9e006c 1406 },
48e7a5f1
DV		 1407};
1408
958261d1
AD		 1409static struct radeon_asic sumo_asic = {
1410 .init = &evergreen_init,
1411 .fini = &evergreen_fini,
1412 .suspend = &evergreen_suspend,
1413 .resume = &evergreen_resume,
958261d1
AD		 1414 .asic_reset = &evergreen_asic_reset,
1415 .vga_set_state = &r600_vga_set_state,
124764f1 1416 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1417 .gui_idle = &r600_gui_idle,
1418 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1419 .get_xclk = &r600_get_xclk,
d0418894 1420 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1421 .gart = {
1422 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
cb658906 1423 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 1424 .set_page = &rs600_gart_set_page,
1425 },
4c87bc26 1426 .ring = {
76a0df85
CK		 1427 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1428 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1429 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1430 },
b35ea4ab
AD		 1431 .irq = {
1432 .set = &evergreen_irq_set,
1433 .process = &evergreen_irq_process,
1434 },
c79a49ca
AD		 1435 .display = {
1436 .bandwidth_update = &evergreen_bandwidth_update,
1437 .get_vblank_counter = &evergreen_get_vblank_counter,
1438 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1439 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1440 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 1441 },
27cd7769 1442 .copy = {
8dddb993 1443 .blit = &r600_copy_cpdma,
27cd7769 1444 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1445 .dma = &evergreen_copy_dma,
1446 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1447 .copy = &evergreen_copy_dma,
1448 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1449 },
9e6f3d02
AD		 1450 .surface = {
1451 .set_reg = r600_set_surface_reg,
1452 .clear_reg = r600_clear_surface_reg,
1453 },
901ea57d
AD		 1454 .hpd = {
1455 .init = &evergreen_hpd_init,
1456 .fini = &evergreen_hpd_fini,
1457 .sense = &evergreen_hpd_sense,
1458 .set_polarity = &evergreen_hpd_set_polarity,
1459 },
a02fa397
AD		 1460 .pm = {
1461 .misc = &evergreen_pm_misc,
1462 .prepare = &evergreen_pm_prepare,
1463 .finish = &evergreen_pm_finish,
1464 .init_profile = &sumo_pm_init_profile,
1465 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1466 .get_engine_clock = &radeon_atom_get_engine_clock,
1467 .set_engine_clock = &radeon_atom_set_engine_clock,
1468 .get_memory_clock = NULL,
1469 .set_memory_clock = NULL,
1470 .get_pcie_lanes = NULL,
1471 .set_pcie_lanes = NULL,
1472 .set_clock_gating = NULL,
23d33ba3 1473 .set_uvd_clocks = &sumo_set_uvd_clocks,
6bd1c385 1474 .get_temperature = &sumo_get_temp,
a02fa397 1475 },
80ea2c12
AD		 1476 .dpm = {
1477 .init = &sumo_dpm_init,
1478 .setup_asic = &sumo_dpm_setup_asic,
1479 .enable = &sumo_dpm_enable,
14ec9fab 1480 .late_enable = &sumo_dpm_late_enable,
80ea2c12 1481 .disable = &sumo_dpm_disable,
422a56bc 1482 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
80ea2c12 1483 .set_power_state = &sumo_dpm_set_power_state,
422a56bc 1484 .post_set_power_state = &sumo_dpm_post_set_power_state,
80ea2c12
AD		 1485 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1486 .fini = &sumo_dpm_fini,
1487 .get_sclk = &sumo_dpm_get_sclk,
1488 .get_mclk = &sumo_dpm_get_mclk,
1489 .print_power_state = &sumo_dpm_print_power_state,
fb70160c 1490 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
5d5e5591 1491 .force_performance_level = &sumo_dpm_force_performance_level,
2f8e1eb7
AD		 1492 .get_current_sclk = &sumo_dpm_get_current_sclk,
1493 .get_current_mclk = &sumo_dpm_get_current_mclk,
80ea2c12 1494 },
0f9e006c 1495 .pflip = {
0f9e006c 1496 .page_flip = &evergreen_page_flip,
157fa14d 1497 .page_flip_pending = &evergreen_page_flip_pending,
0f9e006c 1498 },
958261d1
AD		 1499};
1500
a43b7665
AD		 1501static struct radeon_asic btc_asic = {
1502 .init = &evergreen_init,
1503 .fini = &evergreen_fini,
1504 .suspend = &evergreen_suspend,
1505 .resume = &evergreen_resume,
a43b7665
AD		 1506 .asic_reset = &evergreen_asic_reset,
1507 .vga_set_state = &r600_vga_set_state,
124764f1 1508 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1509 .gui_idle = &r600_gui_idle,
1510 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1511 .get_xclk = &rv770_get_xclk,
d0418894 1512 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1513 .gart = {
1514 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
cb658906 1515 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 1516 .set_page = &rs600_gart_set_page,
1517 },
4c87bc26 1518 .ring = {
76a0df85
CK		 1519 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1520 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1521 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1522 },
b35ea4ab
AD		 1523 .irq = {
1524 .set = &evergreen_irq_set,
1525 .process = &evergreen_irq_process,
1526 },
c79a49ca
AD		 1527 .display = {
1528 .bandwidth_update = &evergreen_bandwidth_update,
1529 .get_vblank_counter = &evergreen_get_vblank_counter,
1530 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1531 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1532 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 1533 },
27cd7769 1534 .copy = {
8dddb993 1535 .blit = &r600_copy_cpdma,
27cd7769 1536 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1537 .dma = &evergreen_copy_dma,
1538 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1539 .copy = &evergreen_copy_dma,
1540 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1541 },
9e6f3d02
AD		 1542 .surface = {
1543 .set_reg = r600_set_surface_reg,
1544 .clear_reg = r600_clear_surface_reg,
1545 },
901ea57d
AD		 1546 .hpd = {
1547 .init = &evergreen_hpd_init,
1548 .fini = &evergreen_hpd_fini,
1549 .sense = &evergreen_hpd_sense,
1550 .set_polarity = &evergreen_hpd_set_polarity,
1551 },
a02fa397
AD		 1552 .pm = {
1553 .misc = &evergreen_pm_misc,
1554 .prepare = &evergreen_pm_prepare,
1555 .finish = &evergreen_pm_finish,
27810fb2 1556 .init_profile = &btc_pm_init_profile,
a02fa397 1557 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1558 .get_engine_clock = &radeon_atom_get_engine_clock,
1559 .set_engine_clock = &radeon_atom_set_engine_clock,
1560 .get_memory_clock = &radeon_atom_get_memory_clock,
1561 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1562 .get_pcie_lanes = &r600_get_pcie_lanes,
1563 .set_pcie_lanes = &r600_set_pcie_lanes,
798bcf73 1564 .set_clock_gating = NULL,
a8b4925c 1565 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1566 .get_temperature = &evergreen_get_temp,
a02fa397 1567 },
6596afd4
AD		 1568 .dpm = {
1569 .init = &btc_dpm_init,
1570 .setup_asic = &btc_dpm_setup_asic,
1571 .enable = &btc_dpm_enable,
a3f11245 1572 .late_enable = &rv770_dpm_late_enable,
6596afd4 1573 .disable = &btc_dpm_disable,
e8a9539f 1574 .pre_set_power_state = &btc_dpm_pre_set_power_state,
6596afd4 1575 .set_power_state = &btc_dpm_set_power_state,
e8a9539f 1576 .post_set_power_state = &btc_dpm_post_set_power_state,
6596afd4
AD		 1577 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1578 .fini = &btc_dpm_fini,
e8a9539f
AD		 1579 .get_sclk = &btc_dpm_get_sclk,
1580 .get_mclk = &btc_dpm_get_mclk,
6596afd4 1581 .print_power_state = &rv770_dpm_print_power_state,
9f3f63f2 1582 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
8b5e6b7f 1583 .force_performance_level = &rv770_dpm_force_performance_level,
a84301c6 1584 .vblank_too_short = &btc_dpm_vblank_too_short,
99550ee9
AD		 1585 .get_current_sclk = &btc_dpm_get_current_sclk,
1586 .get_current_mclk = &btc_dpm_get_current_mclk,
6596afd4 1587 },
0f9e006c 1588 .pflip = {
0f9e006c 1589 .page_flip = &evergreen_page_flip,
157fa14d 1590 .page_flip_pending = &evergreen_page_flip_pending,
0f9e006c 1591 },
a43b7665
AD		 1592};
1593
76a0df85
CK		 1594static struct radeon_asic_ring cayman_gfx_ring = {
1595 .ib_execute = &cayman_ring_ib_execute,
1596 .ib_parse = &evergreen_ib_parse,
1597 .emit_fence = &cayman_fence_ring_emit,
1598 .emit_semaphore = &r600_semaphore_ring_emit,
1599 .cs_parse = &evergreen_cs_parse,
1600 .ring_test = &r600_ring_test,
1601 .ib_test = &r600_ib_test,
1602 .is_lockup = &cayman_gfx_is_lockup,
1603 .vm_flush = &cayman_vm_flush,
ea31bf69
AD		 1604 .get_rptr = &cayman_gfx_get_rptr,
1605 .get_wptr = &cayman_gfx_get_wptr,
1606 .set_wptr = &cayman_gfx_set_wptr,
76a0df85
CK		 1607};
1608
1609static struct radeon_asic_ring cayman_dma_ring = {
1610 .ib_execute = &cayman_dma_ring_ib_execute,
1611 .ib_parse = &evergreen_dma_ib_parse,
1612 .emit_fence = &evergreen_dma_fence_ring_emit,
1613 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1614 .cs_parse = &evergreen_dma_cs_parse,
1615 .ring_test = &r600_dma_ring_test,
1616 .ib_test = &r600_dma_ib_test,
1617 .is_lockup = &cayman_dma_is_lockup,
1618 .vm_flush = &cayman_dma_vm_flush,
ea31bf69
AD		 1619 .get_rptr = &cayman_dma_get_rptr,
1620 .get_wptr = &cayman_dma_get_wptr,
1621 .set_wptr = &cayman_dma_set_wptr
76a0df85
CK		 1622};
1623
1624static struct radeon_asic_ring cayman_uvd_ring = {
e409b128
CK		 1625 .ib_execute = &uvd_v1_0_ib_execute,
1626 .emit_fence = &uvd_v2_2_fence_emit,
1627 .emit_semaphore = &uvd_v3_1_semaphore_emit,
76a0df85 1628 .cs_parse = &radeon_uvd_cs_parse,
e409b128
CK		 1629 .ring_test = &uvd_v1_0_ring_test,
1630 .ib_test = &uvd_v1_0_ib_test,
76a0df85 1631 .is_lockup = &radeon_ring_test_lockup,
e409b128
CK		 1632 .get_rptr = &uvd_v1_0_get_rptr,
1633 .get_wptr = &uvd_v1_0_get_wptr,
1634 .set_wptr = &uvd_v1_0_set_wptr,
76a0df85
CK		 1635};
1636
e3487629
AD		 1637static struct radeon_asic cayman_asic = {
1638 .init = &cayman_init,
1639 .fini = &cayman_fini,
1640 .suspend = &cayman_suspend,
1641 .resume = &cayman_resume,
e3487629
AD		 1642 .asic_reset = &cayman_asic_reset,
1643 .vga_set_state = &r600_vga_set_state,
124764f1 1644 .mmio_hdp_flush = r600_mmio_hdp_flush,
54e88e06
AD		 1645 .gui_idle = &r600_gui_idle,
1646 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1647 .get_xclk = &rv770_get_xclk,
d0418894 1648 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1649 .gart = {
1650 .tlb_flush = &cayman_pcie_gart_tlb_flush,
cb658906 1651 .get_page_entry = &rs600_gart_get_page_entry,
c5b3b850
AD		 1652 .set_page = &rs600_gart_set_page,
1653 },
05b07147
CK		 1654 .vm = {
1655 .init = &cayman_vm_init,
1656 .fini = &cayman_vm_fini,
03f62abd
CK		 1657 .copy_pages = &cayman_dma_vm_copy_pages,
1658 .write_pages = &cayman_dma_vm_write_pages,
1659 .set_pages = &cayman_dma_vm_set_pages,
1660 .pad_ib = &cayman_dma_vm_pad_ib,
05b07147 1661 },
4c87bc26 1662 .ring = {
76a0df85
CK		 1663 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1664 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1665 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1666 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1667 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1668 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
4c87bc26 1669 },
b35ea4ab
AD		 1670 .irq = {
1671 .set = &evergreen_irq_set,
1672 .process = &evergreen_irq_process,
1673 },
c79a49ca
AD		 1674 .display = {
1675 .bandwidth_update = &evergreen_bandwidth_update,
1676 .get_vblank_counter = &evergreen_get_vblank_counter,
1677 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1678 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1679 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 1680 },
27cd7769 1681 .copy = {
8dddb993 1682 .blit = &r600_copy_cpdma,
27cd7769 1683 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
f60cbd11
AD		 1684 .dma = &evergreen_copy_dma,
1685 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1686 .copy = &evergreen_copy_dma,
1687 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1688 },
9e6f3d02
AD		 1689 .surface = {
1690 .set_reg = r600_set_surface_reg,
1691 .clear_reg = r600_clear_surface_reg,
1692 },
901ea57d
AD		 1693 .hpd = {
1694 .init = &evergreen_hpd_init,
1695 .fini = &evergreen_hpd_fini,
1696 .sense = &evergreen_hpd_sense,
1697 .set_polarity = &evergreen_hpd_set_polarity,
1698 },
a02fa397
AD		 1699 .pm = {
1700 .misc = &evergreen_pm_misc,
1701 .prepare = &evergreen_pm_prepare,
1702 .finish = &evergreen_pm_finish,
27810fb2 1703 .init_profile = &btc_pm_init_profile,
a02fa397 1704 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1705 .get_engine_clock = &radeon_atom_get_engine_clock,
1706 .set_engine_clock = &radeon_atom_set_engine_clock,
1707 .get_memory_clock = &radeon_atom_get_memory_clock,
1708 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1709 .get_pcie_lanes = &r600_get_pcie_lanes,
1710 .set_pcie_lanes = &r600_set_pcie_lanes,
798bcf73 1711 .set_clock_gating = NULL,
a8b4925c 1712 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1713 .get_temperature = &evergreen_get_temp,
a02fa397 1714 },
69e0b57a
AD		 1715 .dpm = {
1716 .init = &ni_dpm_init,
1717 .setup_asic = &ni_dpm_setup_asic,
1718 .enable = &ni_dpm_enable,
a3f11245 1719 .late_enable = &rv770_dpm_late_enable,
69e0b57a 1720 .disable = &ni_dpm_disable,
fee3d744 1721 .pre_set_power_state = &ni_dpm_pre_set_power_state,
69e0b57a 1722 .set_power_state = &ni_dpm_set_power_state,
fee3d744 1723 .post_set_power_state = &ni_dpm_post_set_power_state,
69e0b57a
AD		 1724 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1725 .fini = &ni_dpm_fini,
1726 .get_sclk = &ni_dpm_get_sclk,
1727 .get_mclk = &ni_dpm_get_mclk,
1728 .print_power_state = &ni_dpm_print_power_state,
bdf0c4f0 1729 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
170a47f0 1730 .force_performance_level = &ni_dpm_force_performance_level,
76ad73e5 1731 .vblank_too_short = &ni_dpm_vblank_too_short,
1d633e3a
AD		 1732 .get_current_sclk = &ni_dpm_get_current_sclk,
1733 .get_current_mclk = &ni_dpm_get_current_mclk,
69e0b57a 1734 },
0f9e006c 1735 .pflip = {
0f9e006c 1736 .page_flip = &evergreen_page_flip,
157fa14d 1737 .page_flip_pending = &evergreen_page_flip_pending,
0f9e006c 1738 },
e3487629
AD		 1739};
1740
be63fe8c
AD		 1741static struct radeon_asic trinity_asic = {
1742 .init = &cayman_init,
1743 .fini = &cayman_fini,
1744 .suspend = &cayman_suspend,
1745 .resume = &cayman_resume,
be63fe8c
AD		 1746 .asic_reset = &cayman_asic_reset,
1747 .vga_set_state = &r600_vga_set_state,
124764f1 1748 .mmio_hdp_flush = r600_mmio_hdp_flush,
be63fe8c
AD		 1749 .gui_idle = &r600_gui_idle,
1750 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1751 .get_xclk = &r600_get_xclk,
d0418894 1752 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
be63fe8c
AD		 1753 .gart = {
1754 .tlb_flush = &cayman_pcie_gart_tlb_flush,
cb658906 1755 .get_page_entry = &rs600_gart_get_page_entry,
be63fe8c
AD		 1756 .set_page = &rs600_gart_set_page,
1757 },
05b07147
CK		 1758 .vm = {
1759 .init = &cayman_vm_init,
1760 .fini = &cayman_vm_fini,
03f62abd
CK		 1761 .copy_pages = &cayman_dma_vm_copy_pages,
1762 .write_pages = &cayman_dma_vm_write_pages,
1763 .set_pages = &cayman_dma_vm_set_pages,
1764 .pad_ib = &cayman_dma_vm_pad_ib,
05b07147 1765 },
be63fe8c 1766 .ring = {
76a0df85
CK		 1767 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1768 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1769 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1770 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1771 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1772 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
be63fe8c
AD		 1773 },
1774 .irq = {
1775 .set = &evergreen_irq_set,
1776 .process = &evergreen_irq_process,
1777 },
1778 .display = {
1779 .bandwidth_update = &dce6_bandwidth_update,
1780 .get_vblank_counter = &evergreen_get_vblank_counter,
1781 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1782 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1783 .get_backlight_level = &atombios_get_backlight_level,
be63fe8c
AD		 1784 },
1785 .copy = {
8dddb993 1786 .blit = &r600_copy_cpdma,
be63fe8c 1787 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
f60cbd11
AD		 1788 .dma = &evergreen_copy_dma,
1789 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1790 .copy = &evergreen_copy_dma,
1791 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
be63fe8c
AD		 1792 },
1793 .surface = {
1794 .set_reg = r600_set_surface_reg,
1795 .clear_reg = r600_clear_surface_reg,
1796 },
1797 .hpd = {
1798 .init = &evergreen_hpd_init,
1799 .fini = &evergreen_hpd_fini,
1800 .sense = &evergreen_hpd_sense,
1801 .set_polarity = &evergreen_hpd_set_polarity,
1802 },
1803 .pm = {
1804 .misc = &evergreen_pm_misc,
1805 .prepare = &evergreen_pm_prepare,
1806 .finish = &evergreen_pm_finish,
1807 .init_profile = &sumo_pm_init_profile,
1808 .get_dynpm_state = &r600_pm_get_dynpm_state,
1809 .get_engine_clock = &radeon_atom_get_engine_clock,
1810 .set_engine_clock = &radeon_atom_set_engine_clock,
1811 .get_memory_clock = NULL,
1812 .set_memory_clock = NULL,
1813 .get_pcie_lanes = NULL,
1814 .set_pcie_lanes = NULL,
1815 .set_clock_gating = NULL,
23d33ba3 1816 .set_uvd_clocks = &sumo_set_uvd_clocks,
29a15221 1817 .get_temperature = &tn_get_temp,
be63fe8c 1818 },
d70229f7
AD		 1819 .dpm = {
1820 .init = &trinity_dpm_init,
1821 .setup_asic = &trinity_dpm_setup_asic,
1822 .enable = &trinity_dpm_enable,
bda44c1a 1823 .late_enable = &trinity_dpm_late_enable,
d70229f7 1824 .disable = &trinity_dpm_disable,
a284c48a 1825 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
d70229f7 1826 .set_power_state = &trinity_dpm_set_power_state,
a284c48a 1827 .post_set_power_state = &trinity_dpm_post_set_power_state,
d70229f7
AD		 1828 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
1829 .fini = &trinity_dpm_fini,
1830 .get_sclk = &trinity_dpm_get_sclk,
1831 .get_mclk = &trinity_dpm_get_mclk,
1832 .print_power_state = &trinity_dpm_print_power_state,
490ab931 1833 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
9b5de596 1834 .force_performance_level = &trinity_dpm_force_performance_level,
11877060 1835 .enable_bapm = &trinity_dpm_enable_bapm,
7ce9cdae
AD		 1836 .get_current_sclk = &trinity_dpm_get_current_sclk,
1837 .get_current_mclk = &trinity_dpm_get_current_mclk,
d70229f7 1838 },
be63fe8c 1839 .pflip = {
be63fe8c 1840 .page_flip = &evergreen_page_flip,
157fa14d 1841 .page_flip_pending = &evergreen_page_flip_pending,
be63fe8c
AD		 1842 },
1843};
1844
76a0df85
CK		 1845static struct radeon_asic_ring si_gfx_ring = {
1846 .ib_execute = &si_ring_ib_execute,
1847 .ib_parse = &si_ib_parse,
1848 .emit_fence = &si_fence_ring_emit,
1849 .emit_semaphore = &r600_semaphore_ring_emit,
1850 .cs_parse = NULL,
1851 .ring_test = &r600_ring_test,
1852 .ib_test = &r600_ib_test,
1853 .is_lockup = &si_gfx_is_lockup,
1854 .vm_flush = &si_vm_flush,
ea31bf69
AD		 1855 .get_rptr = &cayman_gfx_get_rptr,
1856 .get_wptr = &cayman_gfx_get_wptr,
1857 .set_wptr = &cayman_gfx_set_wptr,
76a0df85
CK		 1858};
1859
1860static struct radeon_asic_ring si_dma_ring = {
1861 .ib_execute = &cayman_dma_ring_ib_execute,
1862 .ib_parse = &evergreen_dma_ib_parse,
1863 .emit_fence = &evergreen_dma_fence_ring_emit,
1864 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1865 .cs_parse = NULL,
1866 .ring_test = &r600_dma_ring_test,
1867 .ib_test = &r600_dma_ib_test,
1868 .is_lockup = &si_dma_is_lockup,
1869 .vm_flush = &si_dma_vm_flush,
ea31bf69
AD		 1870 .get_rptr = &cayman_dma_get_rptr,
1871 .get_wptr = &cayman_dma_get_wptr,
1872 .set_wptr = &cayman_dma_set_wptr,
76a0df85
CK		 1873};
1874
02779c08
AD		 1875static struct radeon_asic si_asic = {
1876 .init = &si_init,
1877 .fini = &si_fini,
1878 .suspend = &si_suspend,
1879 .resume = &si_resume,
02779c08
AD		 1880 .asic_reset = &si_asic_reset,
1881 .vga_set_state = &r600_vga_set_state,
124764f1 1882 .mmio_hdp_flush = r600_mmio_hdp_flush,
02779c08
AD		 1883 .gui_idle = &r600_gui_idle,
1884 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1885 .get_xclk = &si_get_xclk,
d0418894 1886 .get_gpu_clock_counter = &si_get_gpu_clock_counter,
02779c08
AD		 1887 .gart = {
1888 .tlb_flush = &si_pcie_gart_tlb_flush,
cb658906 1889 .get_page_entry = &rs600_gart_get_page_entry,
02779c08
AD		 1890 .set_page = &rs600_gart_set_page,
1891 },
05b07147
CK		 1892 .vm = {
1893 .init = &si_vm_init,
1894 .fini = &si_vm_fini,
03f62abd
CK		 1895 .copy_pages = &si_dma_vm_copy_pages,
1896 .write_pages = &si_dma_vm_write_pages,
1897 .set_pages = &si_dma_vm_set_pages,
1898 .pad_ib = &cayman_dma_vm_pad_ib,
05b07147 1899 },
02779c08 1900 .ring = {
76a0df85
CK		 1901 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1902 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1903 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1904 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1905 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1906 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
02779c08
AD		 1907 },
1908 .irq = {
1909 .set = &si_irq_set,
1910 .process = &si_irq_process,
1911 },
1912 .display = {
1913 .bandwidth_update = &dce6_bandwidth_update,
1914 .get_vblank_counter = &evergreen_get_vblank_counter,
1915 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1916 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1917 .get_backlight_level = &atombios_get_backlight_level,
02779c08
AD		 1918 },
1919 .copy = {
5c722739 1920 .blit = &r600_copy_cpdma,
02779c08 1921 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
8c5fd7ef
AD		 1922 .dma = &si_copy_dma,
1923 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1924 .copy = &si_copy_dma,
1925 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
02779c08
AD		 1926 },
1927 .surface = {
1928 .set_reg = r600_set_surface_reg,
1929 .clear_reg = r600_clear_surface_reg,
1930 },
1931 .hpd = {
1932 .init = &evergreen_hpd_init,
1933 .fini = &evergreen_hpd_fini,
1934 .sense = &evergreen_hpd_sense,
1935 .set_polarity = &evergreen_hpd_set_polarity,
1936 },
1937 .pm = {
1938 .misc = &evergreen_pm_misc,
1939 .prepare = &evergreen_pm_prepare,
1940 .finish = &evergreen_pm_finish,
1941 .init_profile = &sumo_pm_init_profile,
1942 .get_dynpm_state = &r600_pm_get_dynpm_state,
1943 .get_engine_clock = &radeon_atom_get_engine_clock,
1944 .set_engine_clock = &radeon_atom_set_engine_clock,
1945 .get_memory_clock = &radeon_atom_get_memory_clock,
1946 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1947 .get_pcie_lanes = &r600_get_pcie_lanes,
1948 .set_pcie_lanes = &r600_set_pcie_lanes,
02779c08 1949 .set_clock_gating = NULL,
2539eb02 1950 .set_uvd_clocks = &si_set_uvd_clocks,
6bd1c385 1951 .get_temperature = &si_get_temp,
02779c08 1952 },
a9e61410
AD		 1953 .dpm = {
1954 .init = &si_dpm_init,
1955 .setup_asic = &si_dpm_setup_asic,
1956 .enable = &si_dpm_enable,
963c115d 1957 .late_enable = &si_dpm_late_enable,
a9e61410
AD		 1958 .disable = &si_dpm_disable,
1959 .pre_set_power_state = &si_dpm_pre_set_power_state,
1960 .set_power_state = &si_dpm_set_power_state,
1961 .post_set_power_state = &si_dpm_post_set_power_state,
1962 .display_configuration_changed = &si_dpm_display_configuration_changed,
1963 .fini = &si_dpm_fini,
1964 .get_sclk = &ni_dpm_get_sclk,
1965 .get_mclk = &ni_dpm_get_mclk,
1966 .print_power_state = &ni_dpm_print_power_state,
7982128c 1967 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
a160a6a3 1968 .force_performance_level = &si_dpm_force_performance_level,
f4dec318 1969 .vblank_too_short = &ni_dpm_vblank_too_short,
5e8150a6
AD		 1970 .fan_ctrl_set_mode = &si_fan_ctrl_set_mode,
1971 .fan_ctrl_get_mode = &si_fan_ctrl_get_mode,
1972 .get_fan_speed_percent = &si_fan_ctrl_get_fan_speed_percent,
1973 .set_fan_speed_percent = &si_fan_ctrl_set_fan_speed_percent,
ca1110bc
AD		 1974 .get_current_sclk = &si_dpm_get_current_sclk,
1975 .get_current_mclk = &si_dpm_get_current_mclk,
a9e61410 1976 },
02779c08 1977 .pflip = {
02779c08 1978 .page_flip = &evergreen_page_flip,
157fa14d 1979 .page_flip_pending = &evergreen_page_flip_pending,
02779c08
AD		 1980 },
1981};
1982
76a0df85
CK		 1983static struct radeon_asic_ring ci_gfx_ring = {
1984 .ib_execute = &cik_ring_ib_execute,
1985 .ib_parse = &cik_ib_parse,
1986 .emit_fence = &cik_fence_gfx_ring_emit,
1987 .emit_semaphore = &cik_semaphore_ring_emit,
1988 .cs_parse = NULL,
1989 .ring_test = &cik_ring_test,
1990 .ib_test = &cik_ib_test,
1991 .is_lockup = &cik_gfx_is_lockup,
1992 .vm_flush = &cik_vm_flush,
ea31bf69
AD		 1993 .get_rptr = &cik_gfx_get_rptr,
1994 .get_wptr = &cik_gfx_get_wptr,
1995 .set_wptr = &cik_gfx_set_wptr,
76a0df85
CK		 1996};
1997
1998static struct radeon_asic_ring ci_cp_ring = {
1999 .ib_execute = &cik_ring_ib_execute,
2000 .ib_parse = &cik_ib_parse,
2001 .emit_fence = &cik_fence_compute_ring_emit,
2002 .emit_semaphore = &cik_semaphore_ring_emit,
2003 .cs_parse = NULL,
2004 .ring_test = &cik_ring_test,
2005 .ib_test = &cik_ib_test,
2006 .is_lockup = &cik_gfx_is_lockup,
2007 .vm_flush = &cik_vm_flush,
ea31bf69
AD		 2008 .get_rptr = &cik_compute_get_rptr,
2009 .get_wptr = &cik_compute_get_wptr,
2010 .set_wptr = &cik_compute_set_wptr,
76a0df85
CK		 2011};
2012
2013static struct radeon_asic_ring ci_dma_ring = {
2014 .ib_execute = &cik_sdma_ring_ib_execute,
2015 .ib_parse = &cik_ib_parse,
2016 .emit_fence = &cik_sdma_fence_ring_emit,
2017 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2018 .cs_parse = NULL,
2019 .ring_test = &cik_sdma_ring_test,
2020 .ib_test = &cik_sdma_ib_test,
2021 .is_lockup = &cik_sdma_is_lockup,
2022 .vm_flush = &cik_dma_vm_flush,
ea31bf69
AD		 2023 .get_rptr = &cik_sdma_get_rptr,
2024 .get_wptr = &cik_sdma_get_wptr,
2025 .set_wptr = &cik_sdma_set_wptr,
76a0df85
CK		 2026};
2027
d93f7937
CK		 2028static struct radeon_asic_ring ci_vce_ring = {
2029 .ib_execute = &radeon_vce_ib_execute,
2030 .emit_fence = &radeon_vce_fence_emit,
2031 .emit_semaphore = &radeon_vce_semaphore_emit,
2032 .cs_parse = &radeon_vce_cs_parse,
2033 .ring_test = &radeon_vce_ring_test,
2034 .ib_test = &radeon_vce_ib_test,
2035 .is_lockup = &radeon_ring_test_lockup,
2036 .get_rptr = &vce_v1_0_get_rptr,
2037 .get_wptr = &vce_v1_0_get_wptr,
2038 .set_wptr = &vce_v1_0_set_wptr,
2039};
2040
0672e27b
AD		 2041static struct radeon_asic ci_asic = {
2042 .init = &cik_init,
2043 .fini = &cik_fini,
2044 .suspend = &cik_suspend,
2045 .resume = &cik_resume,
2046 .asic_reset = &cik_asic_reset,
2047 .vga_set_state = &r600_vga_set_state,
72a9987e 2048 .mmio_hdp_flush = &r600_mmio_hdp_flush,
0672e27b
AD		 2049 .gui_idle = &r600_gui_idle,
2050 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2051 .get_xclk = &cik_get_xclk,
2052 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2053 .gart = {
2054 .tlb_flush = &cik_pcie_gart_tlb_flush,
cb658906 2055 .get_page_entry = &rs600_gart_get_page_entry,
0672e27b
AD		 2056 .set_page = &rs600_gart_set_page,
2057 },
2058 .vm = {
2059 .init = &cik_vm_init,
2060 .fini = &cik_vm_fini,
03f62abd
CK		 2061 .copy_pages = &cik_sdma_vm_copy_pages,
2062 .write_pages = &cik_sdma_vm_write_pages,
2063 .set_pages = &cik_sdma_vm_set_pages,
2064 .pad_ib = &cik_sdma_vm_pad_ib,
0672e27b
AD		 2065 },
2066 .ring = {
76a0df85
CK		 2067 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2068 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2069 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2070 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2071 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2072 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
d93f7937
CK		 2073 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2074 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
0672e27b
AD		 2075 },
2076 .irq = {
2077 .set = &cik_irq_set,
2078 .process = &cik_irq_process,
2079 },
2080 .display = {
2081 .bandwidth_update = &dce8_bandwidth_update,
2082 .get_vblank_counter = &evergreen_get_vblank_counter,
2083 .wait_for_vblank = &dce4_wait_for_vblank,
7272c9d2
SL		 2084 .set_backlight_level = &atombios_set_backlight_level,
2085 .get_backlight_level = &atombios_get_backlight_level,
0672e27b
AD		 2086 },
2087 .copy = {
7819678f 2088 .blit = &cik_copy_cpdma,
0672e27b
AD		 2089 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2090 .dma = &cik_copy_dma,
2091 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
b5be1a83
CK		 2092 .copy = &cik_copy_dma,
2093 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
0672e27b
AD		 2094 },
2095 .surface = {
2096 .set_reg = r600_set_surface_reg,
2097 .clear_reg = r600_clear_surface_reg,
2098 },
2099 .hpd = {
2100 .init = &evergreen_hpd_init,
2101 .fini = &evergreen_hpd_fini,
2102 .sense = &evergreen_hpd_sense,
2103 .set_polarity = &evergreen_hpd_set_polarity,
2104 },
2105 .pm = {
2106 .misc = &evergreen_pm_misc,
2107 .prepare = &evergreen_pm_prepare,
2108 .finish = &evergreen_pm_finish,
2109 .init_profile = &sumo_pm_init_profile,
2110 .get_dynpm_state = &r600_pm_get_dynpm_state,
2111 .get_engine_clock = &radeon_atom_get_engine_clock,
2112 .set_engine_clock = &radeon_atom_set_engine_clock,
2113 .get_memory_clock = &radeon_atom_get_memory_clock,
2114 .set_memory_clock = &radeon_atom_set_memory_clock,
2115 .get_pcie_lanes = NULL,
2116 .set_pcie_lanes = NULL,
2117 .set_clock_gating = NULL,
2118 .set_uvd_clocks = &cik_set_uvd_clocks,
5ad6bf91 2119 .set_vce_clocks = &cik_set_vce_clocks,
286d9cc6 2120 .get_temperature = &ci_get_temp,
0672e27b 2121 },
cc8dbbb4
AD		 2122 .dpm = {
2123 .init = &ci_dpm_init,
2124 .setup_asic = &ci_dpm_setup_asic,
2125 .enable = &ci_dpm_enable,
90208427 2126 .late_enable = &ci_dpm_late_enable,
cc8dbbb4
AD		 2127 .disable = &ci_dpm_disable,
2128 .pre_set_power_state = &ci_dpm_pre_set_power_state,
2129 .set_power_state = &ci_dpm_set_power_state,
2130 .post_set_power_state = &ci_dpm_post_set_power_state,
2131 .display_configuration_changed = &ci_dpm_display_configuration_changed,
2132 .fini = &ci_dpm_fini,
2133 .get_sclk = &ci_dpm_get_sclk,
2134 .get_mclk = &ci_dpm_get_mclk,
2135 .print_power_state = &ci_dpm_print_power_state,
94b4adc5 2136 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
89536fd6 2137 .force_performance_level = &ci_dpm_force_performance_level,
5496131e 2138 .vblank_too_short = &ci_dpm_vblank_too_short,
942bdf7f 2139 .powergate_uvd = &ci_dpm_powergate_uvd,
36689e57
OC		 2140 .fan_ctrl_set_mode = &ci_fan_ctrl_set_mode,
2141 .fan_ctrl_get_mode = &ci_fan_ctrl_get_mode,
2142 .get_fan_speed_percent = &ci_fan_ctrl_get_fan_speed_percent,
2143 .set_fan_speed_percent = &ci_fan_ctrl_set_fan_speed_percent,
dbbd3c81
AD		 2144 .get_current_sclk = &ci_dpm_get_current_sclk,
2145 .get_current_mclk = &ci_dpm_get_current_mclk,
cc8dbbb4 2146 },
0672e27b 2147 .pflip = {
0672e27b 2148 .page_flip = &evergreen_page_flip,
157fa14d 2149 .page_flip_pending = &evergreen_page_flip_pending,
0672e27b
AD		 2150 },
2151};
2152
2153static struct radeon_asic kv_asic = {
2154 .init = &cik_init,
2155 .fini = &cik_fini,
2156 .suspend = &cik_suspend,
2157 .resume = &cik_resume,
2158 .asic_reset = &cik_asic_reset,
2159 .vga_set_state = &r600_vga_set_state,
72a9987e 2160 .mmio_hdp_flush = &r600_mmio_hdp_flush,
0672e27b
AD		 2161 .gui_idle = &r600_gui_idle,
2162 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2163 .get_xclk = &cik_get_xclk,
2164 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2165 .gart = {
2166 .tlb_flush = &cik_pcie_gart_tlb_flush,
cb658906 2167 .get_page_entry = &rs600_gart_get_page_entry,
0672e27b
AD		 2168 .set_page = &rs600_gart_set_page,
2169 },
2170 .vm = {
2171 .init = &cik_vm_init,
2172 .fini = &cik_vm_fini,
03f62abd
CK		 2173 .copy_pages = &cik_sdma_vm_copy_pages,
2174 .write_pages = &cik_sdma_vm_write_pages,
2175 .set_pages = &cik_sdma_vm_set_pages,
2176 .pad_ib = &cik_sdma_vm_pad_ib,
0672e27b
AD		 2177 },
2178 .ring = {
76a0df85
CK		 2179 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2180 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2181 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2182 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2183 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2184 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
d93f7937
CK		 2185 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2186 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
0672e27b
AD		 2187 },
2188 .irq = {
2189 .set = &cik_irq_set,
2190 .process = &cik_irq_process,
2191 },
2192 .display = {
2193 .bandwidth_update = &dce8_bandwidth_update,
2194 .get_vblank_counter = &evergreen_get_vblank_counter,
2195 .wait_for_vblank = &dce4_wait_for_vblank,
7272c9d2
SL		 2196 .set_backlight_level = &atombios_set_backlight_level,
2197 .get_backlight_level = &atombios_get_backlight_level,
0672e27b
AD		 2198 },
2199 .copy = {
7819678f 2200 .blit = &cik_copy_cpdma,
0672e27b
AD		 2201 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2202 .dma = &cik_copy_dma,
2203 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2204 .copy = &cik_copy_dma,
2205 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2206 },
2207 .surface = {
2208 .set_reg = r600_set_surface_reg,
2209 .clear_reg = r600_clear_surface_reg,
2210 },
2211 .hpd = {
2212 .init = &evergreen_hpd_init,
2213 .fini = &evergreen_hpd_fini,
2214 .sense = &evergreen_hpd_sense,
2215 .set_polarity = &evergreen_hpd_set_polarity,
2216 },
2217 .pm = {
2218 .misc = &evergreen_pm_misc,
2219 .prepare = &evergreen_pm_prepare,
2220 .finish = &evergreen_pm_finish,
2221 .init_profile = &sumo_pm_init_profile,
2222 .get_dynpm_state = &r600_pm_get_dynpm_state,
2223 .get_engine_clock = &radeon_atom_get_engine_clock,
2224 .set_engine_clock = &radeon_atom_set_engine_clock,
2225 .get_memory_clock = &radeon_atom_get_memory_clock,
2226 .set_memory_clock = &radeon_atom_set_memory_clock,
2227 .get_pcie_lanes = NULL,
2228 .set_pcie_lanes = NULL,
2229 .set_clock_gating = NULL,
2230 .set_uvd_clocks = &cik_set_uvd_clocks,
5ad6bf91 2231 .set_vce_clocks = &cik_set_vce_clocks,
286d9cc6 2232 .get_temperature = &kv_get_temp,
0672e27b 2233 },
41a524ab
AD		 2234 .dpm = {
2235 .init = &kv_dpm_init,
2236 .setup_asic = &kv_dpm_setup_asic,
2237 .enable = &kv_dpm_enable,
d8852c34 2238 .late_enable = &kv_dpm_late_enable,
41a524ab
AD		 2239 .disable = &kv_dpm_disable,
2240 .pre_set_power_state = &kv_dpm_pre_set_power_state,
2241 .set_power_state = &kv_dpm_set_power_state,
2242 .post_set_power_state = &kv_dpm_post_set_power_state,
2243 .display_configuration_changed = &kv_dpm_display_configuration_changed,
2244 .fini = &kv_dpm_fini,
2245 .get_sclk = &kv_dpm_get_sclk,
2246 .get_mclk = &kv_dpm_get_mclk,
2247 .print_power_state = &kv_dpm_print_power_state,
ae3e40e8 2248 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2b4c8022 2249 .force_performance_level = &kv_dpm_force_performance_level,
77df508a 2250 .powergate_uvd = &kv_dpm_powergate_uvd,
b7a5ae97 2251 .enable_bapm = &kv_dpm_enable_bapm,
41a524ab 2252 },
0672e27b 2253 .pflip = {
0672e27b 2254 .page_flip = &evergreen_page_flip,
157fa14d 2255 .page_flip_pending = &evergreen_page_flip_pending,
0672e27b
AD		 2256 },
2257};
2258
abf1dc67
AD		 2259/**
2260 * radeon_asic_init - register asic specific callbacks
2261 *
2262 * @rdev: radeon device pointer
2263 *
2264 * Registers the appropriate asic specific callbacks for each
2265 * chip family. Also sets other asics specific info like the number
2266 * of crtcs and the register aperture accessors (all asics).
2267 * Returns 0 for success.
2268 */
0a10c851
DV		 2269int radeon_asic_init(struct radeon_device *rdev)
2270{
2271 radeon_register_accessor_init(rdev);
ba7e05e9
AD		 2272
2273 /* set the number of crtcs */
2274 if (rdev->flags & RADEON_SINGLE_CRTC)
2275 rdev->num_crtc = 1;
2276 else
2277 rdev->num_crtc = 2;
2278
948bee3f
AD		 2279 rdev->has_uvd = false;
2280
0a10c851
DV		 2281 switch (rdev->family) {
2282 case CHIP_R100:
2283 case CHIP_RV100:
2284 case CHIP_RS100:
2285 case CHIP_RV200:
2286 case CHIP_RS200:
2287 rdev->asic = &r100_asic;
2288 break;
2289 case CHIP_R200:
2290 case CHIP_RV250:
2291 case CHIP_RS300:
2292 case CHIP_RV280:
2293 rdev->asic = &r200_asic;
2294 break;
2295 case CHIP_R300:
2296 case CHIP_R350:
2297 case CHIP_RV350:
2298 case CHIP_RV380:
2299 if (rdev->flags & RADEON_IS_PCIE)
2300 rdev->asic = &r300_asic_pcie;
2301 else
2302 rdev->asic = &r300_asic;
2303 break;
2304 case CHIP_R420:
2305 case CHIP_R423:
2306 case CHIP_RV410:
2307 rdev->asic = &r420_asic;
07bb084c
AD		 2308 /* handle macs */
2309 if (rdev->bios == NULL) {
798bcf73
AD		 2310 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2311 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2312 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2313 rdev->asic->pm.set_memory_clock = NULL;
37e9b6a6 2314 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
07bb084c 2315 }
0a10c851
DV		 2316 break;
2317 case CHIP_RS400:
2318 case CHIP_RS480:
2319 rdev->asic = &rs400_asic;
2320 break;
2321 case CHIP_RS600:
2322 rdev->asic = &rs600_asic;
2323 break;
2324 case CHIP_RS690:
2325 case CHIP_RS740:
2326 rdev->asic = &rs690_asic;
2327 break;
2328 case CHIP_RV515:
2329 rdev->asic = &rv515_asic;
2330 break;
2331 case CHIP_R520:
2332 case CHIP_RV530:
2333 case CHIP_RV560:
2334 case CHIP_RV570:
2335 case CHIP_R580:
2336 rdev->asic = &r520_asic;
2337 break;
2338 case CHIP_R600:
ca361b65
AD		 2339 rdev->asic = &r600_asic;
2340 break;
0a10c851
DV		 2341 case CHIP_RV610:
2342 case CHIP_RV630:
2343 case CHIP_RV620:
2344 case CHIP_RV635:
2345 case CHIP_RV670:
ca361b65
AD		 2346 rdev->asic = &rv6xx_asic;
2347 rdev->has_uvd = true;
f47299c5 2348 break;
0a10c851
DV		 2349 case CHIP_RS780:
2350 case CHIP_RS880:
f47299c5 2351 rdev->asic = &rs780_asic;
bdc99722
AD		 2352 /* 760G/780V/880V don't have UVD */
2353 if ((rdev->pdev->device == 0x9616)||
2354 (rdev->pdev->device == 0x9611)||
2355 (rdev->pdev->device == 0x9613)||
2356 (rdev->pdev->device == 0x9711)||
2357 (rdev->pdev->device == 0x9713))
2358 rdev->has_uvd = false;
2359 else
2360 rdev->has_uvd = true;
0a10c851
DV		 2361 break;
2362 case CHIP_RV770:
2363 case CHIP_RV730:
2364 case CHIP_RV710:
2365 case CHIP_RV740:
2366 rdev->asic = &rv770_asic;
948bee3f 2367 rdev->has_uvd = true;
0a10c851
DV		 2368 break;
2369 case CHIP_CEDAR:
2370 case CHIP_REDWOOD:
2371 case CHIP_JUNIPER:
2372 case CHIP_CYPRESS:
2373 case CHIP_HEMLOCK:
ba7e05e9
AD		 2374 /* set num crtcs */
2375 if (rdev->family == CHIP_CEDAR)
2376 rdev->num_crtc = 4;
2377 else
2378 rdev->num_crtc = 6;
0a10c851 2379 rdev->asic = &evergreen_asic;
948bee3f 2380 rdev->has_uvd = true;
0a10c851 2381 break;
958261d1 2382 case CHIP_PALM:
89da5a37
AD		 2383 case CHIP_SUMO:
2384 case CHIP_SUMO2:
958261d1 2385 rdev->asic = &sumo_asic;
948bee3f 2386 rdev->has_uvd = true;
958261d1 2387 break;
a43b7665
AD		 2388 case CHIP_BARTS:
2389 case CHIP_TURKS:
2390 case CHIP_CAICOS:
ba7e05e9
AD		 2391 /* set num crtcs */
2392 if (rdev->family == CHIP_CAICOS)
2393 rdev->num_crtc = 4;
2394 else
2395 rdev->num_crtc = 6;
a43b7665 2396 rdev->asic = &btc_asic;
948bee3f 2397 rdev->has_uvd = true;
a43b7665 2398 break;
e3487629
AD		 2399 case CHIP_CAYMAN:
2400 rdev->asic = &cayman_asic;
ba7e05e9
AD		 2401 /* set num crtcs */
2402 rdev->num_crtc = 6;
948bee3f 2403 rdev->has_uvd = true;
e3487629 2404 break;
be63fe8c
AD		 2405 case CHIP_ARUBA:
2406 rdev->asic = &trinity_asic;
2407 /* set num crtcs */
2408 rdev->num_crtc = 4;
948bee3f 2409 rdev->has_uvd = true;
be63fe8c 2410 break;
02779c08
AD		 2411 case CHIP_TAHITI:
2412 case CHIP_PITCAIRN:
2413 case CHIP_VERDE:
e737a14c 2414 case CHIP_OLAND:
86a45cac 2415 case CHIP_HAINAN:
02779c08
AD		 2416 rdev->asic = &si_asic;
2417 /* set num crtcs */
86a45cac
AD		 2418 if (rdev->family == CHIP_HAINAN)
2419 rdev->num_crtc = 0;
2420 else if (rdev->family == CHIP_OLAND)
e737a14c
AD		 2421 rdev->num_crtc = 2;
2422 else
2423 rdev->num_crtc = 6;
948bee3f
AD		 2424 if (rdev->family == CHIP_HAINAN)
2425 rdev->has_uvd = false;
2426 else
2427 rdev->has_uvd = true;
0116e1ef
AD		 2428 switch (rdev->family) {
2429 case CHIP_TAHITI:
2430 rdev->cg_flags =
090f4b6a 2431 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2432 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2433 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2434 RADEON_CG_SUPPORT_GFX_CGLS |
2435 RADEON_CG_SUPPORT_GFX_CGTS |
2436 RADEON_CG_SUPPORT_GFX_CP_LS |
2437 RADEON_CG_SUPPORT_MC_MGCG |
2438 RADEON_CG_SUPPORT_SDMA_MGCG |
2439 RADEON_CG_SUPPORT_BIF_LS |
2440 RADEON_CG_SUPPORT_VCE_MGCG |
2441 RADEON_CG_SUPPORT_UVD_MGCG |
2442 RADEON_CG_SUPPORT_HDP_LS |
2443 RADEON_CG_SUPPORT_HDP_MGCG;
2444 rdev->pg_flags = 0;
2445 break;
2446 case CHIP_PITCAIRN:
2447 rdev->cg_flags =
090f4b6a 2448 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2449 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2450 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2451 RADEON_CG_SUPPORT_GFX_CGLS |
2452 RADEON_CG_SUPPORT_GFX_CGTS |
2453 RADEON_CG_SUPPORT_GFX_CP_LS |
2454 RADEON_CG_SUPPORT_GFX_RLC_LS |
2455 RADEON_CG_SUPPORT_MC_LS |
2456 RADEON_CG_SUPPORT_MC_MGCG |
2457 RADEON_CG_SUPPORT_SDMA_MGCG |
2458 RADEON_CG_SUPPORT_BIF_LS |
2459 RADEON_CG_SUPPORT_VCE_MGCG |
2460 RADEON_CG_SUPPORT_UVD_MGCG |
2461 RADEON_CG_SUPPORT_HDP_LS |
2462 RADEON_CG_SUPPORT_HDP_MGCG;
2463 rdev->pg_flags = 0;
2464 break;
2465 case CHIP_VERDE:
2466 rdev->cg_flags =
090f4b6a 2467 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2468 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2469 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2470 RADEON_CG_SUPPORT_GFX_CGLS |
2471 RADEON_CG_SUPPORT_GFX_CGTS |
2472 RADEON_CG_SUPPORT_GFX_CP_LS |
2473 RADEON_CG_SUPPORT_GFX_RLC_LS |
2474 RADEON_CG_SUPPORT_MC_LS |
2475 RADEON_CG_SUPPORT_MC_MGCG |
2476 RADEON_CG_SUPPORT_SDMA_MGCG |
2477 RADEON_CG_SUPPORT_BIF_LS |
2478 RADEON_CG_SUPPORT_VCE_MGCG |
2479 RADEON_CG_SUPPORT_UVD_MGCG |
2480 RADEON_CG_SUPPORT_HDP_LS |
2481 RADEON_CG_SUPPORT_HDP_MGCG;
ca6ebb39 2482 rdev->pg_flags = 0 |
2b19d17f 2483 /*RADEON_PG_SUPPORT_GFX_PG | */
ca6ebb39 2484 RADEON_PG_SUPPORT_SDMA;
0116e1ef
AD		 2485 break;
2486 case CHIP_OLAND:
2487 rdev->cg_flags =
090f4b6a 2488 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2489 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2490 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2491 RADEON_CG_SUPPORT_GFX_CGLS |
2492 RADEON_CG_SUPPORT_GFX_CGTS |
2493 RADEON_CG_SUPPORT_GFX_CP_LS |
2494 RADEON_CG_SUPPORT_GFX_RLC_LS |
2495 RADEON_CG_SUPPORT_MC_LS |
2496 RADEON_CG_SUPPORT_MC_MGCG |
2497 RADEON_CG_SUPPORT_SDMA_MGCG |
2498 RADEON_CG_SUPPORT_BIF_LS |
2499 RADEON_CG_SUPPORT_UVD_MGCG |
2500 RADEON_CG_SUPPORT_HDP_LS |
2501 RADEON_CG_SUPPORT_HDP_MGCG;
2502 rdev->pg_flags = 0;
2503 break;
2504 case CHIP_HAINAN:
2505 rdev->cg_flags =
090f4b6a 2506 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2507 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2508 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2509 RADEON_CG_SUPPORT_GFX_CGLS |
2510 RADEON_CG_SUPPORT_GFX_CGTS |
2511 RADEON_CG_SUPPORT_GFX_CP_LS |
2512 RADEON_CG_SUPPORT_GFX_RLC_LS |
2513 RADEON_CG_SUPPORT_MC_LS |
2514 RADEON_CG_SUPPORT_MC_MGCG |
2515 RADEON_CG_SUPPORT_SDMA_MGCG |
2516 RADEON_CG_SUPPORT_BIF_LS |
2517 RADEON_CG_SUPPORT_HDP_LS |
2518 RADEON_CG_SUPPORT_HDP_MGCG;
2519 rdev->pg_flags = 0;
2520 break;
2521 default:
2522 rdev->cg_flags = 0;
2523 rdev->pg_flags = 0;
2524 break;
2525 }
02779c08 2526 break;
0672e27b 2527 case CHIP_BONAIRE:
41971b37 2528 case CHIP_HAWAII:
0672e27b
AD		 2529 rdev->asic = &ci_asic;
2530 rdev->num_crtc = 6;
22c775ce 2531 rdev->has_uvd = true;
41971b37
AD		 2532 if (rdev->family == CHIP_BONAIRE) {
2533 rdev->cg_flags =
2534 RADEON_CG_SUPPORT_GFX_MGCG |
2535 RADEON_CG_SUPPORT_GFX_MGLS |
6960948d 2536 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
41971b37
AD		 2537 RADEON_CG_SUPPORT_GFX_CGLS |
2538 RADEON_CG_SUPPORT_GFX_CGTS |
2539 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2540 RADEON_CG_SUPPORT_GFX_CP_LS |
2541 RADEON_CG_SUPPORT_MC_LS |
2542 RADEON_CG_SUPPORT_MC_MGCG |
2543 RADEON_CG_SUPPORT_SDMA_MGCG |
2544 RADEON_CG_SUPPORT_SDMA_LS |
2545 RADEON_CG_SUPPORT_BIF_LS |
2546 RADEON_CG_SUPPORT_VCE_MGCG |
2547 RADEON_CG_SUPPORT_UVD_MGCG |
2548 RADEON_CG_SUPPORT_HDP_LS |
2549 RADEON_CG_SUPPORT_HDP_MGCG;
2550 rdev->pg_flags = 0;
2551 } else {
2552 rdev->cg_flags =
2553 RADEON_CG_SUPPORT_GFX_MGCG |
2554 RADEON_CG_SUPPORT_GFX_MGLS |
6960948d 2555 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
41971b37
AD		 2556 RADEON_CG_SUPPORT_GFX_CGLS |
2557 RADEON_CG_SUPPORT_GFX_CGTS |
2558 RADEON_CG_SUPPORT_GFX_CP_LS |
2559 RADEON_CG_SUPPORT_MC_LS |
2560 RADEON_CG_SUPPORT_MC_MGCG |
2561 RADEON_CG_SUPPORT_SDMA_MGCG |
2562 RADEON_CG_SUPPORT_SDMA_LS |
2563 RADEON_CG_SUPPORT_BIF_LS |
2564 RADEON_CG_SUPPORT_VCE_MGCG |
2565 RADEON_CG_SUPPORT_UVD_MGCG |
2566 RADEON_CG_SUPPORT_HDP_LS |
2567 RADEON_CG_SUPPORT_HDP_MGCG;
2568 rdev->pg_flags = 0;
2569 }
0672e27b
AD		 2570 break;
2571 case CHIP_KAVERI:
2572 case CHIP_KABINI:
b0a9f22a 2573 case CHIP_MULLINS:
0672e27b
AD		 2574 rdev->asic = &kv_asic;
2575 /* set num crtcs */
473359bc 2576 if (rdev->family == CHIP_KAVERI) {
0672e27b 2577 rdev->num_crtc = 4;
473359bc 2578 rdev->cg_flags =
773dc10a 2579 RADEON_CG_SUPPORT_GFX_MGCG |
473359bc 2580 RADEON_CG_SUPPORT_GFX_MGLS |
6960948d 2581 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
473359bc
AD		 2582 RADEON_CG_SUPPORT_GFX_CGLS |
2583 RADEON_CG_SUPPORT_GFX_CGTS |
2584 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2585 RADEON_CG_SUPPORT_GFX_CP_LS |
2586 RADEON_CG_SUPPORT_SDMA_MGCG |
2587 RADEON_CG_SUPPORT_SDMA_LS |
2588 RADEON_CG_SUPPORT_BIF_LS |
2589 RADEON_CG_SUPPORT_VCE_MGCG |
2590 RADEON_CG_SUPPORT_UVD_MGCG |
2591 RADEON_CG_SUPPORT_HDP_LS |
2592 RADEON_CG_SUPPORT_HDP_MGCG;
2593 rdev->pg_flags = 0;
2b19d17f 2594 /*RADEON_PG_SUPPORT_GFX_PG |
473359bc
AD		 2595 RADEON_PG_SUPPORT_GFX_SMG |
2596 RADEON_PG_SUPPORT_GFX_DMG |
2597 RADEON_PG_SUPPORT_UVD |
2598 RADEON_PG_SUPPORT_VCE |
2599 RADEON_PG_SUPPORT_CP |
2600 RADEON_PG_SUPPORT_GDS |
2601 RADEON_PG_SUPPORT_RLC_SMU_HS |
2602 RADEON_PG_SUPPORT_ACP |
2603 RADEON_PG_SUPPORT_SAMU;*/
2604 } else {
0672e27b 2605 rdev->num_crtc = 2;
473359bc 2606 rdev->cg_flags =
773dc10a 2607 RADEON_CG_SUPPORT_GFX_MGCG |
473359bc 2608 RADEON_CG_SUPPORT_GFX_MGLS |
6960948d 2609 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
473359bc
AD		 2610 RADEON_CG_SUPPORT_GFX_CGLS |
2611 RADEON_CG_SUPPORT_GFX_CGTS |
2612 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2613 RADEON_CG_SUPPORT_GFX_CP_LS |
2614 RADEON_CG_SUPPORT_SDMA_MGCG |
2615 RADEON_CG_SUPPORT_SDMA_LS |
2616 RADEON_CG_SUPPORT_BIF_LS |
2617 RADEON_CG_SUPPORT_VCE_MGCG |
2618 RADEON_CG_SUPPORT_UVD_MGCG |
2619 RADEON_CG_SUPPORT_HDP_LS |
2620 RADEON_CG_SUPPORT_HDP_MGCG;
2621 rdev->pg_flags = 0;
2b19d17f 2622 /*RADEON_PG_SUPPORT_GFX_PG |
473359bc
AD		 2623 RADEON_PG_SUPPORT_GFX_SMG |
2624 RADEON_PG_SUPPORT_UVD |
2625 RADEON_PG_SUPPORT_VCE |
2626 RADEON_PG_SUPPORT_CP |
2627 RADEON_PG_SUPPORT_GDS |
2628 RADEON_PG_SUPPORT_RLC_SMU_HS |
2629 RADEON_PG_SUPPORT_SAMU;*/
2630 }
22c775ce 2631 rdev->has_uvd = true;
0672e27b 2632 break;
0a10c851
DV		 2633 default:
2634 /* FIXME: not supported yet */
2635 return -EINVAL;
2636 }
2637
2638 if (rdev->flags & RADEON_IS_IGP) {
798bcf73
AD		 2639 rdev->asic->pm.get_memory_clock = NULL;
2640 rdev->asic->pm.set_memory_clock = NULL;
0a10c851
DV		 2641 }
2642
2643 return 0;
2644}
2645
Linux kernel - Deliverables
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