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drm/radeon/dpm: add late_enable for rv7xx-NI
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_asic.c
CommitLineData
0a10c851
DV		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/console.h>
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
33#include <linux/vgaarb.h>
34#include <linux/vga_switcheroo.h>
35#include "radeon_reg.h"
36#include "radeon.h"
37#include "radeon_asic.h"
38#include "atom.h"
39
40/*
41 * Registers accessors functions.
42 */
abf1dc67
AD		 43/**
44 * radeon_invalid_rreg - dummy reg read function
45 *
46 * @rdev: radeon device pointer
47 * @reg: offset of register
48 *
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
52 */
0a10c851
DV		 53static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54{
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
56 BUG_ON(1);
57 return 0;
58}
59
abf1dc67
AD		 60/**
61 * radeon_invalid_wreg - dummy reg write function
62 *
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
66 *
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
69 */
0a10c851
DV		 70static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
71{
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
73 reg, v);
74 BUG_ON(1);
75}
76
abf1dc67
AD		 77/**
78 * radeon_register_accessor_init - sets up the register accessor callbacks
79 *
80 * @rdev: radeon device pointer
81 *
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
84 */
0a10c851
DV		 85static void radeon_register_accessor_init(struct radeon_device *rdev)
86{
87 rdev->mc_rreg = &radeon_invalid_rreg;
88 rdev->mc_wreg = &radeon_invalid_wreg;
89 rdev->pll_rreg = &radeon_invalid_rreg;
90 rdev->pll_wreg = &radeon_invalid_wreg;
91 rdev->pciep_rreg = &radeon_invalid_rreg;
92 rdev->pciep_wreg = &radeon_invalid_wreg;
93
94 /* Don't change order as we are overridding accessor. */
95 if (rdev->family < CHIP_RV515) {
96 rdev->pcie_reg_mask = 0xff;
97 } else {
98 rdev->pcie_reg_mask = 0x7ff;
99 }
100 /* FIXME: not sure here */
101 if (rdev->family <= CHIP_R580) {
102 rdev->pll_rreg = &r100_pll_rreg;
103 rdev->pll_wreg = &r100_pll_wreg;
104 }
105 if (rdev->family >= CHIP_R420) {
106 rdev->mc_rreg = &r420_mc_rreg;
107 rdev->mc_wreg = &r420_mc_wreg;
108 }
109 if (rdev->family >= CHIP_RV515) {
110 rdev->mc_rreg = &rv515_mc_rreg;
111 rdev->mc_wreg = &rv515_mc_wreg;
112 }
113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
114 rdev->mc_rreg = &rs400_mc_rreg;
115 rdev->mc_wreg = &rs400_mc_wreg;
116 }
117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
118 rdev->mc_rreg = &rs690_mc_rreg;
119 rdev->mc_wreg = &rs690_mc_wreg;
120 }
121 if (rdev->family == CHIP_RS600) {
122 rdev->mc_rreg = &rs600_mc_rreg;
123 rdev->mc_wreg = &rs600_mc_wreg;
124 }
65337e60
SL		 125 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
126 rdev->mc_rreg = &rs780_mc_rreg;
127 rdev->mc_wreg = &rs780_mc_wreg;
128 }
6e2c3c0a
AD		 129
130 if (rdev->family >= CHIP_BONAIRE) {
131 rdev->pciep_rreg = &cik_pciep_rreg;
132 rdev->pciep_wreg = &cik_pciep_wreg;
133 } else if (rdev->family >= CHIP_R600) {
0a10c851
DV		 134 rdev->pciep_rreg = &r600_pciep_rreg;
135 rdev->pciep_wreg = &r600_pciep_wreg;
136 }
137}
138
139
140/* helper to disable agp */
abf1dc67
AD		 141/**
142 * radeon_agp_disable - AGP disable helper function
143 *
144 * @rdev: radeon device pointer
145 *
146 * Removes AGP flags and changes the gart callbacks on AGP
147 * cards when using the internal gart rather than AGP (all asics).
148 */
0a10c851
DV		 149void radeon_agp_disable(struct radeon_device *rdev)
150{
151 rdev->flags &= ~RADEON_IS_AGP;
152 if (rdev->family >= CHIP_R600) {
153 DRM_INFO("Forcing AGP to PCIE mode\n");
154 rdev->flags |= RADEON_IS_PCIE;
155 } else if (rdev->family >= CHIP_RV515 ||
156 rdev->family == CHIP_RV380 ||
157 rdev->family == CHIP_RV410 ||
158 rdev->family == CHIP_R423) {
159 DRM_INFO("Forcing AGP to PCIE mode\n");
160 rdev->flags |= RADEON_IS_PCIE;
c5b3b850
AD		 161 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
162 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
0a10c851
DV		 163 } else {
164 DRM_INFO("Forcing AGP to PCI mode\n");
165 rdev->flags |= RADEON_IS_PCI;
c5b3b850
AD		 166 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
167 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
0a10c851
DV		 168 }
169 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
170}
171
172/*
173 * ASIC
174 */
76a0df85
CK		 175
176static struct radeon_asic_ring r100_gfx_ring = {
177 .ib_execute = &r100_ring_ib_execute,
178 .emit_fence = &r100_fence_ring_emit,
179 .emit_semaphore = &r100_semaphore_ring_emit,
180 .cs_parse = &r100_cs_parse,
181 .ring_start = &r100_ring_start,
182 .ring_test = &r100_ring_test,
183 .ib_test = &r100_ib_test,
184 .is_lockup = &r100_gpu_is_lockup,
185 .get_rptr = &radeon_ring_generic_get_rptr,
186 .get_wptr = &radeon_ring_generic_get_wptr,
187 .set_wptr = &radeon_ring_generic_set_wptr,
188};
189
48e7a5f1
DV		 190static struct radeon_asic r100_asic = {
191 .init = &r100_init,
192 .fini = &r100_fini,
193 .suspend = &r100_suspend,
194 .resume = &r100_resume,
195 .vga_set_state = &r100_vga_set_state,
a2d07b74 196 .asic_reset = &r100_asic_reset,
54e88e06
AD		 197 .ioctl_wait_idle = NULL,
198 .gui_idle = &r100_gui_idle,
199 .mc_wait_for_idle = &r100_mc_wait_for_idle,
c5b3b850
AD		 200 .gart = {
201 .tlb_flush = &r100_pci_gart_tlb_flush,
202 .set_page = &r100_pci_gart_set_page,
203 },
4c87bc26 204 .ring = {
76a0df85 205 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
4c87bc26 206 },
b35ea4ab
AD		 207 .irq = {
208 .set = &r100_irq_set,
209 .process = &r100_irq_process,
210 },
c79a49ca
AD		 211 .display = {
212 .bandwidth_update = &r100_bandwidth_update,
213 .get_vblank_counter = &r100_get_vblank_counter,
214 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 215 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 216 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 217 },
27cd7769
AD		 218 .copy = {
219 .blit = &r100_copy_blit,
220 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
221 .dma = NULL,
222 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
223 .copy = &r100_copy_blit,
224 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
225 },
9e6f3d02
AD		 226 .surface = {
227 .set_reg = r100_set_surface_reg,
228 .clear_reg = r100_clear_surface_reg,
229 },
901ea57d
AD		 230 .hpd = {
231 .init = &r100_hpd_init,
232 .fini = &r100_hpd_fini,
233 .sense = &r100_hpd_sense,
234 .set_polarity = &r100_hpd_set_polarity,
235 },
a02fa397
AD		 236 .pm = {
237 .misc = &r100_pm_misc,
238 .prepare = &r100_pm_prepare,
239 .finish = &r100_pm_finish,
240 .init_profile = &r100_pm_init_profile,
241 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 242 .get_engine_clock = &radeon_legacy_get_engine_clock,
243 .set_engine_clock = &radeon_legacy_set_engine_clock,
244 .get_memory_clock = &radeon_legacy_get_memory_clock,
245 .set_memory_clock = NULL,
246 .get_pcie_lanes = NULL,
247 .set_pcie_lanes = NULL,
248 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 249 },
0f9e006c
AD		 250 .pflip = {
251 .pre_page_flip = &r100_pre_page_flip,
252 .page_flip = &r100_page_flip,
253 .post_page_flip = &r100_post_page_flip,
254 },
48e7a5f1
DV		 255};
256
257static struct radeon_asic r200_asic = {
258 .init = &r100_init,
259 .fini = &r100_fini,
260 .suspend = &r100_suspend,
261 .resume = &r100_resume,
262 .vga_set_state = &r100_vga_set_state,
a2d07b74 263 .asic_reset = &r100_asic_reset,
54e88e06
AD		 264 .ioctl_wait_idle = NULL,
265 .gui_idle = &r100_gui_idle,
266 .mc_wait_for_idle = &r100_mc_wait_for_idle,
c5b3b850
AD		 267 .gart = {
268 .tlb_flush = &r100_pci_gart_tlb_flush,
269 .set_page = &r100_pci_gart_set_page,
270 },
4c87bc26 271 .ring = {
76a0df85 272 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
4c87bc26 273 },
b35ea4ab
AD		 274 .irq = {
275 .set = &r100_irq_set,
276 .process = &r100_irq_process,
277 },
c79a49ca
AD		 278 .display = {
279 .bandwidth_update = &r100_bandwidth_update,
280 .get_vblank_counter = &r100_get_vblank_counter,
281 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 282 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 283 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 284 },
27cd7769
AD		 285 .copy = {
286 .blit = &r100_copy_blit,
287 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
288 .dma = &r200_copy_dma,
289 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
290 .copy = &r100_copy_blit,
291 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
292 },
9e6f3d02
AD		 293 .surface = {
294 .set_reg = r100_set_surface_reg,
295 .clear_reg = r100_clear_surface_reg,
296 },
901ea57d
AD		 297 .hpd = {
298 .init = &r100_hpd_init,
299 .fini = &r100_hpd_fini,
300 .sense = &r100_hpd_sense,
301 .set_polarity = &r100_hpd_set_polarity,
302 },
a02fa397
AD		 303 .pm = {
304 .misc = &r100_pm_misc,
305 .prepare = &r100_pm_prepare,
306 .finish = &r100_pm_finish,
307 .init_profile = &r100_pm_init_profile,
308 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 309 .get_engine_clock = &radeon_legacy_get_engine_clock,
310 .set_engine_clock = &radeon_legacy_set_engine_clock,
311 .get_memory_clock = &radeon_legacy_get_memory_clock,
312 .set_memory_clock = NULL,
313 .get_pcie_lanes = NULL,
314 .set_pcie_lanes = NULL,
315 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 316 },
0f9e006c
AD		 317 .pflip = {
318 .pre_page_flip = &r100_pre_page_flip,
319 .page_flip = &r100_page_flip,
320 .post_page_flip = &r100_post_page_flip,
321 },
48e7a5f1
DV		 322};
323
76a0df85
CK		 324static struct radeon_asic_ring r300_gfx_ring = {
325 .ib_execute = &r100_ring_ib_execute,
326 .emit_fence = &r300_fence_ring_emit,
327 .emit_semaphore = &r100_semaphore_ring_emit,
328 .cs_parse = &r300_cs_parse,
329 .ring_start = &r300_ring_start,
330 .ring_test = &r100_ring_test,
331 .ib_test = &r100_ib_test,
332 .is_lockup = &r100_gpu_is_lockup,
333 .get_rptr = &radeon_ring_generic_get_rptr,
334 .get_wptr = &radeon_ring_generic_get_wptr,
335 .set_wptr = &radeon_ring_generic_set_wptr,
336};
337
48e7a5f1
DV		 338static struct radeon_asic r300_asic = {
339 .init = &r300_init,
340 .fini = &r300_fini,
341 .suspend = &r300_suspend,
342 .resume = &r300_resume,
343 .vga_set_state = &r100_vga_set_state,
a2d07b74 344 .asic_reset = &r300_asic_reset,
54e88e06
AD		 345 .ioctl_wait_idle = NULL,
346 .gui_idle = &r100_gui_idle,
347 .mc_wait_for_idle = &r300_mc_wait_for_idle,
c5b3b850
AD		 348 .gart = {
349 .tlb_flush = &r100_pci_gart_tlb_flush,
350 .set_page = &r100_pci_gart_set_page,
351 },
4c87bc26 352 .ring = {
76a0df85 353 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 354 },
b35ea4ab
AD		 355 .irq = {
356 .set = &r100_irq_set,
357 .process = &r100_irq_process,
358 },
c79a49ca
AD		 359 .display = {
360 .bandwidth_update = &r100_bandwidth_update,
361 .get_vblank_counter = &r100_get_vblank_counter,
362 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 363 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 364 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 365 },
27cd7769
AD		 366 .copy = {
367 .blit = &r100_copy_blit,
368 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
369 .dma = &r200_copy_dma,
370 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
371 .copy = &r100_copy_blit,
372 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
373 },
9e6f3d02
AD		 374 .surface = {
375 .set_reg = r100_set_surface_reg,
376 .clear_reg = r100_clear_surface_reg,
377 },
901ea57d
AD		 378 .hpd = {
379 .init = &r100_hpd_init,
380 .fini = &r100_hpd_fini,
381 .sense = &r100_hpd_sense,
382 .set_polarity = &r100_hpd_set_polarity,
383 },
a02fa397
AD		 384 .pm = {
385 .misc = &r100_pm_misc,
386 .prepare = &r100_pm_prepare,
387 .finish = &r100_pm_finish,
388 .init_profile = &r100_pm_init_profile,
389 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 390 .get_engine_clock = &radeon_legacy_get_engine_clock,
391 .set_engine_clock = &radeon_legacy_set_engine_clock,
392 .get_memory_clock = &radeon_legacy_get_memory_clock,
393 .set_memory_clock = NULL,
394 .get_pcie_lanes = &rv370_get_pcie_lanes,
395 .set_pcie_lanes = &rv370_set_pcie_lanes,
396 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 397 },
0f9e006c
AD		 398 .pflip = {
399 .pre_page_flip = &r100_pre_page_flip,
400 .page_flip = &r100_page_flip,
401 .post_page_flip = &r100_post_page_flip,
402 },
48e7a5f1
DV		 403};
404
405static struct radeon_asic r300_asic_pcie = {
406 .init = &r300_init,
407 .fini = &r300_fini,
408 .suspend = &r300_suspend,
409 .resume = &r300_resume,
410 .vga_set_state = &r100_vga_set_state,
a2d07b74 411 .asic_reset = &r300_asic_reset,
54e88e06
AD		 412 .ioctl_wait_idle = NULL,
413 .gui_idle = &r100_gui_idle,
414 .mc_wait_for_idle = &r300_mc_wait_for_idle,
c5b3b850
AD		 415 .gart = {
416 .tlb_flush = &rv370_pcie_gart_tlb_flush,
417 .set_page = &rv370_pcie_gart_set_page,
418 },
4c87bc26 419 .ring = {
76a0df85 420 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 421 },
b35ea4ab
AD		 422 .irq = {
423 .set = &r100_irq_set,
424 .process = &r100_irq_process,
425 },
c79a49ca
AD		 426 .display = {
427 .bandwidth_update = &r100_bandwidth_update,
428 .get_vblank_counter = &r100_get_vblank_counter,
429 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 430 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 431 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 432 },
27cd7769
AD		 433 .copy = {
434 .blit = &r100_copy_blit,
435 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
436 .dma = &r200_copy_dma,
437 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
438 .copy = &r100_copy_blit,
439 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
440 },
9e6f3d02
AD		 441 .surface = {
442 .set_reg = r100_set_surface_reg,
443 .clear_reg = r100_clear_surface_reg,
444 },
901ea57d
AD		 445 .hpd = {
446 .init = &r100_hpd_init,
447 .fini = &r100_hpd_fini,
448 .sense = &r100_hpd_sense,
449 .set_polarity = &r100_hpd_set_polarity,
450 },
a02fa397
AD		 451 .pm = {
452 .misc = &r100_pm_misc,
453 .prepare = &r100_pm_prepare,
454 .finish = &r100_pm_finish,
455 .init_profile = &r100_pm_init_profile,
456 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 457 .get_engine_clock = &radeon_legacy_get_engine_clock,
458 .set_engine_clock = &radeon_legacy_set_engine_clock,
459 .get_memory_clock = &radeon_legacy_get_memory_clock,
460 .set_memory_clock = NULL,
461 .get_pcie_lanes = &rv370_get_pcie_lanes,
462 .set_pcie_lanes = &rv370_set_pcie_lanes,
463 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 464 },
0f9e006c
AD		 465 .pflip = {
466 .pre_page_flip = &r100_pre_page_flip,
467 .page_flip = &r100_page_flip,
468 .post_page_flip = &r100_post_page_flip,
469 },
48e7a5f1
DV		 470};
471
472static struct radeon_asic r420_asic = {
473 .init = &r420_init,
474 .fini = &r420_fini,
475 .suspend = &r420_suspend,
476 .resume = &r420_resume,
477 .vga_set_state = &r100_vga_set_state,
a2d07b74 478 .asic_reset = &r300_asic_reset,
54e88e06
AD		 479 .ioctl_wait_idle = NULL,
480 .gui_idle = &r100_gui_idle,
481 .mc_wait_for_idle = &r300_mc_wait_for_idle,
c5b3b850
AD		 482 .gart = {
483 .tlb_flush = &rv370_pcie_gart_tlb_flush,
484 .set_page = &rv370_pcie_gart_set_page,
485 },
4c87bc26 486 .ring = {
76a0df85 487 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 488 },
b35ea4ab
AD		 489 .irq = {
490 .set = &r100_irq_set,
491 .process = &r100_irq_process,
492 },
c79a49ca
AD		 493 .display = {
494 .bandwidth_update = &r100_bandwidth_update,
495 .get_vblank_counter = &r100_get_vblank_counter,
496 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 497 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 498 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 499 },
27cd7769
AD		 500 .copy = {
501 .blit = &r100_copy_blit,
502 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
503 .dma = &r200_copy_dma,
504 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
505 .copy = &r100_copy_blit,
506 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
507 },
9e6f3d02
AD		 508 .surface = {
509 .set_reg = r100_set_surface_reg,
510 .clear_reg = r100_clear_surface_reg,
511 },
901ea57d
AD		 512 .hpd = {
513 .init = &r100_hpd_init,
514 .fini = &r100_hpd_fini,
515 .sense = &r100_hpd_sense,
516 .set_polarity = &r100_hpd_set_polarity,
517 },
a02fa397
AD		 518 .pm = {
519 .misc = &r100_pm_misc,
520 .prepare = &r100_pm_prepare,
521 .finish = &r100_pm_finish,
522 .init_profile = &r420_pm_init_profile,
523 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 524 .get_engine_clock = &radeon_atom_get_engine_clock,
525 .set_engine_clock = &radeon_atom_set_engine_clock,
526 .get_memory_clock = &radeon_atom_get_memory_clock,
527 .set_memory_clock = &radeon_atom_set_memory_clock,
528 .get_pcie_lanes = &rv370_get_pcie_lanes,
529 .set_pcie_lanes = &rv370_set_pcie_lanes,
530 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 531 },
0f9e006c
AD		 532 .pflip = {
533 .pre_page_flip = &r100_pre_page_flip,
534 .page_flip = &r100_page_flip,
535 .post_page_flip = &r100_post_page_flip,
536 },
48e7a5f1
DV		 537};
538
539static struct radeon_asic rs400_asic = {
540 .init = &rs400_init,
541 .fini = &rs400_fini,
542 .suspend = &rs400_suspend,
543 .resume = &rs400_resume,
544 .vga_set_state = &r100_vga_set_state,
a2d07b74 545 .asic_reset = &r300_asic_reset,
54e88e06
AD		 546 .ioctl_wait_idle = NULL,
547 .gui_idle = &r100_gui_idle,
548 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
c5b3b850
AD		 549 .gart = {
550 .tlb_flush = &rs400_gart_tlb_flush,
551 .set_page = &rs400_gart_set_page,
552 },
4c87bc26 553 .ring = {
76a0df85 554 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 555 },
b35ea4ab
AD		 556 .irq = {
557 .set = &r100_irq_set,
558 .process = &r100_irq_process,
559 },
c79a49ca
AD		 560 .display = {
561 .bandwidth_update = &r100_bandwidth_update,
562 .get_vblank_counter = &r100_get_vblank_counter,
563 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 564 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 565 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 566 },
27cd7769
AD		 567 .copy = {
568 .blit = &r100_copy_blit,
569 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
570 .dma = &r200_copy_dma,
571 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
572 .copy = &r100_copy_blit,
573 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
574 },
9e6f3d02
AD		 575 .surface = {
576 .set_reg = r100_set_surface_reg,
577 .clear_reg = r100_clear_surface_reg,
578 },
901ea57d
AD		 579 .hpd = {
580 .init = &r100_hpd_init,
581 .fini = &r100_hpd_fini,
582 .sense = &r100_hpd_sense,
583 .set_polarity = &r100_hpd_set_polarity,
584 },
a02fa397
AD		 585 .pm = {
586 .misc = &r100_pm_misc,
587 .prepare = &r100_pm_prepare,
588 .finish = &r100_pm_finish,
589 .init_profile = &r100_pm_init_profile,
590 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 591 .get_engine_clock = &radeon_legacy_get_engine_clock,
592 .set_engine_clock = &radeon_legacy_set_engine_clock,
593 .get_memory_clock = &radeon_legacy_get_memory_clock,
594 .set_memory_clock = NULL,
595 .get_pcie_lanes = NULL,
596 .set_pcie_lanes = NULL,
597 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 598 },
0f9e006c
AD		 599 .pflip = {
600 .pre_page_flip = &r100_pre_page_flip,
601 .page_flip = &r100_page_flip,
602 .post_page_flip = &r100_post_page_flip,
603 },
48e7a5f1
DV		 604};
605
606static struct radeon_asic rs600_asic = {
607 .init = &rs600_init,
608 .fini = &rs600_fini,
609 .suspend = &rs600_suspend,
610 .resume = &rs600_resume,
611 .vga_set_state = &r100_vga_set_state,
90aca4d2 612 .asic_reset = &rs600_asic_reset,
54e88e06
AD		 613 .ioctl_wait_idle = NULL,
614 .gui_idle = &r100_gui_idle,
615 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
c5b3b850
AD		 616 .gart = {
617 .tlb_flush = &rs600_gart_tlb_flush,
618 .set_page = &rs600_gart_set_page,
619 },
4c87bc26 620 .ring = {
76a0df85 621 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 622 },
b35ea4ab
AD		 623 .irq = {
624 .set = &rs600_irq_set,
625 .process = &rs600_irq_process,
626 },
c79a49ca
AD		 627 .display = {
628 .bandwidth_update = &rs600_bandwidth_update,
629 .get_vblank_counter = &rs600_get_vblank_counter,
630 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 631 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 632 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 633 .hdmi_enable = &r600_hdmi_enable,
634 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 635 },
27cd7769
AD		 636 .copy = {
637 .blit = &r100_copy_blit,
638 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
639 .dma = &r200_copy_dma,
640 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
641 .copy = &r100_copy_blit,
642 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
643 },
9e6f3d02
AD		 644 .surface = {
645 .set_reg = r100_set_surface_reg,
646 .clear_reg = r100_clear_surface_reg,
647 },
901ea57d
AD		 648 .hpd = {
649 .init = &rs600_hpd_init,
650 .fini = &rs600_hpd_fini,
651 .sense = &rs600_hpd_sense,
652 .set_polarity = &rs600_hpd_set_polarity,
653 },
a02fa397
AD		 654 .pm = {
655 .misc = &rs600_pm_misc,
656 .prepare = &rs600_pm_prepare,
657 .finish = &rs600_pm_finish,
658 .init_profile = &r420_pm_init_profile,
659 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 660 .get_engine_clock = &radeon_atom_get_engine_clock,
661 .set_engine_clock = &radeon_atom_set_engine_clock,
662 .get_memory_clock = &radeon_atom_get_memory_clock,
663 .set_memory_clock = &radeon_atom_set_memory_clock,
664 .get_pcie_lanes = NULL,
665 .set_pcie_lanes = NULL,
666 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 667 },
0f9e006c
AD		 668 .pflip = {
669 .pre_page_flip = &rs600_pre_page_flip,
670 .page_flip = &rs600_page_flip,
671 .post_page_flip = &rs600_post_page_flip,
672 },
48e7a5f1
DV		 673};
674
675static struct radeon_asic rs690_asic = {
676 .init = &rs690_init,
677 .fini = &rs690_fini,
678 .suspend = &rs690_suspend,
679 .resume = &rs690_resume,
680 .vga_set_state = &r100_vga_set_state,
90aca4d2 681 .asic_reset = &rs600_asic_reset,
54e88e06
AD		 682 .ioctl_wait_idle = NULL,
683 .gui_idle = &r100_gui_idle,
684 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
c5b3b850
AD		 685 .gart = {
686 .tlb_flush = &rs400_gart_tlb_flush,
687 .set_page = &rs400_gart_set_page,
688 },
4c87bc26 689 .ring = {
76a0df85 690 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 691 },
b35ea4ab
AD		 692 .irq = {
693 .set = &rs600_irq_set,
694 .process = &rs600_irq_process,
695 },
c79a49ca
AD		 696 .display = {
697 .get_vblank_counter = &rs600_get_vblank_counter,
698 .bandwidth_update = &rs690_bandwidth_update,
699 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 700 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 701 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 702 .hdmi_enable = &r600_hdmi_enable,
703 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 704 },
27cd7769
AD		 705 .copy = {
706 .blit = &r100_copy_blit,
707 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
708 .dma = &r200_copy_dma,
709 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
710 .copy = &r200_copy_dma,
711 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
712 },
9e6f3d02
AD		 713 .surface = {
714 .set_reg = r100_set_surface_reg,
715 .clear_reg = r100_clear_surface_reg,
716 },
901ea57d
AD		 717 .hpd = {
718 .init = &rs600_hpd_init,
719 .fini = &rs600_hpd_fini,
720 .sense = &rs600_hpd_sense,
721 .set_polarity = &rs600_hpd_set_polarity,
722 },
a02fa397
AD		 723 .pm = {
724 .misc = &rs600_pm_misc,
725 .prepare = &rs600_pm_prepare,
726 .finish = &rs600_pm_finish,
727 .init_profile = &r420_pm_init_profile,
728 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 729 .get_engine_clock = &radeon_atom_get_engine_clock,
730 .set_engine_clock = &radeon_atom_set_engine_clock,
731 .get_memory_clock = &radeon_atom_get_memory_clock,
732 .set_memory_clock = &radeon_atom_set_memory_clock,
733 .get_pcie_lanes = NULL,
734 .set_pcie_lanes = NULL,
735 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 736 },
0f9e006c
AD		 737 .pflip = {
738 .pre_page_flip = &rs600_pre_page_flip,
739 .page_flip = &rs600_page_flip,
740 .post_page_flip = &rs600_post_page_flip,
741 },
48e7a5f1
DV		 742};
743
744static struct radeon_asic rv515_asic = {
745 .init = &rv515_init,
746 .fini = &rv515_fini,
747 .suspend = &rv515_suspend,
748 .resume = &rv515_resume,
749 .vga_set_state = &r100_vga_set_state,
90aca4d2 750 .asic_reset = &rs600_asic_reset,
54e88e06
AD		 751 .ioctl_wait_idle = NULL,
752 .gui_idle = &r100_gui_idle,
753 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
c5b3b850
AD		 754 .gart = {
755 .tlb_flush = &rv370_pcie_gart_tlb_flush,
756 .set_page = &rv370_pcie_gart_set_page,
757 },
4c87bc26 758 .ring = {
76a0df85 759 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 760 },
b35ea4ab
AD		 761 .irq = {
762 .set = &rs600_irq_set,
763 .process = &rs600_irq_process,
764 },
c79a49ca
AD		 765 .display = {
766 .get_vblank_counter = &rs600_get_vblank_counter,
767 .bandwidth_update = &rv515_bandwidth_update,
768 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 769 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 770 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 771 },
27cd7769
AD		 772 .copy = {
773 .blit = &r100_copy_blit,
774 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
775 .dma = &r200_copy_dma,
776 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
777 .copy = &r100_copy_blit,
778 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
779 },
9e6f3d02
AD		 780 .surface = {
781 .set_reg = r100_set_surface_reg,
782 .clear_reg = r100_clear_surface_reg,
783 },
901ea57d
AD		 784 .hpd = {
785 .init = &rs600_hpd_init,
786 .fini = &rs600_hpd_fini,
787 .sense = &rs600_hpd_sense,
788 .set_polarity = &rs600_hpd_set_polarity,
789 },
a02fa397
AD		 790 .pm = {
791 .misc = &rs600_pm_misc,
792 .prepare = &rs600_pm_prepare,
793 .finish = &rs600_pm_finish,
794 .init_profile = &r420_pm_init_profile,
795 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 796 .get_engine_clock = &radeon_atom_get_engine_clock,
797 .set_engine_clock = &radeon_atom_set_engine_clock,
798 .get_memory_clock = &radeon_atom_get_memory_clock,
799 .set_memory_clock = &radeon_atom_set_memory_clock,
800 .get_pcie_lanes = &rv370_get_pcie_lanes,
801 .set_pcie_lanes = &rv370_set_pcie_lanes,
802 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 803 },
0f9e006c
AD		 804 .pflip = {
805 .pre_page_flip = &rs600_pre_page_flip,
806 .page_flip = &rs600_page_flip,
807 .post_page_flip = &rs600_post_page_flip,
808 },
48e7a5f1
DV		 809};
810
811static struct radeon_asic r520_asic = {
812 .init = &r520_init,
813 .fini = &rv515_fini,
814 .suspend = &rv515_suspend,
815 .resume = &r520_resume,
816 .vga_set_state = &r100_vga_set_state,
90aca4d2 817 .asic_reset = &rs600_asic_reset,
54e88e06
AD		 818 .ioctl_wait_idle = NULL,
819 .gui_idle = &r100_gui_idle,
820 .mc_wait_for_idle = &r520_mc_wait_for_idle,
c5b3b850
AD		 821 .gart = {
822 .tlb_flush = &rv370_pcie_gart_tlb_flush,
823 .set_page = &rv370_pcie_gart_set_page,
824 },
4c87bc26 825 .ring = {
76a0df85 826 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
4c87bc26 827 },
b35ea4ab
AD		 828 .irq = {
829 .set = &rs600_irq_set,
830 .process = &rs600_irq_process,
831 },
c79a49ca
AD		 832 .display = {
833 .bandwidth_update = &rv515_bandwidth_update,
834 .get_vblank_counter = &rs600_get_vblank_counter,
835 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 836 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 837 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 838 },
27cd7769
AD		 839 .copy = {
840 .blit = &r100_copy_blit,
841 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
842 .dma = &r200_copy_dma,
843 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
844 .copy = &r100_copy_blit,
845 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
846 },
9e6f3d02
AD		 847 .surface = {
848 .set_reg = r100_set_surface_reg,
849 .clear_reg = r100_clear_surface_reg,
850 },
901ea57d
AD		 851 .hpd = {
852 .init = &rs600_hpd_init,
853 .fini = &rs600_hpd_fini,
854 .sense = &rs600_hpd_sense,
855 .set_polarity = &rs600_hpd_set_polarity,
856 },
a02fa397
AD		 857 .pm = {
858 .misc = &rs600_pm_misc,
859 .prepare = &rs600_pm_prepare,
860 .finish = &rs600_pm_finish,
861 .init_profile = &r420_pm_init_profile,
862 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 863 .get_engine_clock = &radeon_atom_get_engine_clock,
864 .set_engine_clock = &radeon_atom_set_engine_clock,
865 .get_memory_clock = &radeon_atom_get_memory_clock,
866 .set_memory_clock = &radeon_atom_set_memory_clock,
867 .get_pcie_lanes = &rv370_get_pcie_lanes,
868 .set_pcie_lanes = &rv370_set_pcie_lanes,
869 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 870 },
0f9e006c
AD		 871 .pflip = {
872 .pre_page_flip = &rs600_pre_page_flip,
873 .page_flip = &rs600_page_flip,
874 .post_page_flip = &rs600_post_page_flip,
875 },
48e7a5f1
DV		 876};
877
76a0df85
CK		 878static struct radeon_asic_ring r600_gfx_ring = {
879 .ib_execute = &r600_ring_ib_execute,
880 .emit_fence = &r600_fence_ring_emit,
881 .emit_semaphore = &r600_semaphore_ring_emit,
882 .cs_parse = &r600_cs_parse,
883 .ring_test = &r600_ring_test,
884 .ib_test = &r600_ib_test,
885 .is_lockup = &r600_gfx_is_lockup,
886 .get_rptr = &radeon_ring_generic_get_rptr,
887 .get_wptr = &radeon_ring_generic_get_wptr,
888 .set_wptr = &radeon_ring_generic_set_wptr,
889};
890
891static struct radeon_asic_ring r600_dma_ring = {
892 .ib_execute = &r600_dma_ring_ib_execute,
893 .emit_fence = &r600_dma_fence_ring_emit,
894 .emit_semaphore = &r600_dma_semaphore_ring_emit,
895 .cs_parse = &r600_dma_cs_parse,
896 .ring_test = &r600_dma_ring_test,
897 .ib_test = &r600_dma_ib_test,
898 .is_lockup = &r600_dma_is_lockup,
2e1e6dad
CK		 899 .get_rptr = &r600_dma_get_rptr,
900 .get_wptr = &r600_dma_get_wptr,
901 .set_wptr = &r600_dma_set_wptr,
76a0df85
CK		 902};
903
48e7a5f1
DV		 904static struct radeon_asic r600_asic = {
905 .init = &r600_init,
906 .fini = &r600_fini,
907 .suspend = &r600_suspend,
908 .resume = &r600_resume,
48e7a5f1 909 .vga_set_state = &r600_vga_set_state,
a2d07b74 910 .asic_reset = &r600_asic_reset,
54e88e06
AD		 911 .ioctl_wait_idle = r600_ioctl_wait_idle,
912 .gui_idle = &r600_gui_idle,
913 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 914 .get_xclk = &r600_get_xclk,
d0418894 915 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 916 .gart = {
917 .tlb_flush = &r600_pcie_gart_tlb_flush,
918 .set_page = &rs600_gart_set_page,
919 },
4c87bc26 920 .ring = {
76a0df85
CK		 921 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
922 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
4c87bc26 923 },
b35ea4ab
AD		 924 .irq = {
925 .set = &r600_irq_set,
926 .process = &r600_irq_process,
927 },
c79a49ca
AD		 928 .display = {
929 .bandwidth_update = &rv515_bandwidth_update,
930 .get_vblank_counter = &rs600_get_vblank_counter,
931 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 932 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 933 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 934 .hdmi_enable = &r600_hdmi_enable,
935 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 936 },
27cd7769 937 .copy = {
8dddb993 938 .blit = &r600_copy_cpdma,
27cd7769 939 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
4d75658b
AD		 940 .dma = &r600_copy_dma,
941 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
bfea6a68 942 .copy = &r600_copy_cpdma,
aeea40cb 943 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
27cd7769 944 },
9e6f3d02
AD		 945 .surface = {
946 .set_reg = r600_set_surface_reg,
947 .clear_reg = r600_clear_surface_reg,
948 },
901ea57d
AD		 949 .hpd = {
950 .init = &r600_hpd_init,
951 .fini = &r600_hpd_fini,
952 .sense = &r600_hpd_sense,
953 .set_polarity = &r600_hpd_set_polarity,
954 },
a02fa397
AD		 955 .pm = {
956 .misc = &r600_pm_misc,
957 .prepare = &rs600_pm_prepare,
958 .finish = &rs600_pm_finish,
959 .init_profile = &r600_pm_init_profile,
960 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 961 .get_engine_clock = &radeon_atom_get_engine_clock,
962 .set_engine_clock = &radeon_atom_set_engine_clock,
963 .get_memory_clock = &radeon_atom_get_memory_clock,
964 .set_memory_clock = &radeon_atom_set_memory_clock,
965 .get_pcie_lanes = &r600_get_pcie_lanes,
966 .set_pcie_lanes = &r600_set_pcie_lanes,
967 .set_clock_gating = NULL,
6bd1c385 968 .get_temperature = &rv6xx_get_temp,
a02fa397 969 },
0f9e006c
AD		 970 .pflip = {
971 .pre_page_flip = &rs600_pre_page_flip,
972 .page_flip = &rs600_page_flip,
973 .post_page_flip = &rs600_post_page_flip,
974 },
48e7a5f1
DV		 975};
976
ca361b65
AD		 977static struct radeon_asic rv6xx_asic = {
978 .init = &r600_init,
979 .fini = &r600_fini,
980 .suspend = &r600_suspend,
981 .resume = &r600_resume,
982 .vga_set_state = &r600_vga_set_state,
983 .asic_reset = &r600_asic_reset,
984 .ioctl_wait_idle = r600_ioctl_wait_idle,
985 .gui_idle = &r600_gui_idle,
986 .mc_wait_for_idle = &r600_mc_wait_for_idle,
987 .get_xclk = &r600_get_xclk,
988 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
989 .gart = {
990 .tlb_flush = &r600_pcie_gart_tlb_flush,
991 .set_page = &rs600_gart_set_page,
992 },
993 .ring = {
76a0df85
CK		 994 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
995 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
ca361b65
AD		 996 },
997 .irq = {
998 .set = &r600_irq_set,
999 .process = &r600_irq_process,
1000 },
1001 .display = {
1002 .bandwidth_update = &rv515_bandwidth_update,
1003 .get_vblank_counter = &rs600_get_vblank_counter,
1004 .wait_for_vblank = &avivo_wait_for_vblank,
1005 .set_backlight_level = &atombios_set_backlight_level,
1006 .get_backlight_level = &atombios_get_backlight_level,
99d79aa2
AD		 1007 .hdmi_enable = &r600_hdmi_enable,
1008 .hdmi_setmode = &r600_hdmi_setmode,
ca361b65
AD		 1009 },
1010 .copy = {
8dddb993 1011 .blit = &r600_copy_cpdma,
ca361b65
AD		 1012 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1013 .dma = &r600_copy_dma,
1014 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
bfea6a68 1015 .copy = &r600_copy_cpdma,
aeea40cb 1016 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
ca361b65
AD		 1017 },
1018 .surface = {
1019 .set_reg = r600_set_surface_reg,
1020 .clear_reg = r600_clear_surface_reg,
1021 },
1022 .hpd = {
1023 .init = &r600_hpd_init,
1024 .fini = &r600_hpd_fini,
1025 .sense = &r600_hpd_sense,
1026 .set_polarity = &r600_hpd_set_polarity,
1027 },
1028 .pm = {
1029 .misc = &r600_pm_misc,
1030 .prepare = &rs600_pm_prepare,
1031 .finish = &rs600_pm_finish,
1032 .init_profile = &r600_pm_init_profile,
1033 .get_dynpm_state = &r600_pm_get_dynpm_state,
1034 .get_engine_clock = &radeon_atom_get_engine_clock,
1035 .set_engine_clock = &radeon_atom_set_engine_clock,
1036 .get_memory_clock = &radeon_atom_get_memory_clock,
1037 .set_memory_clock = &radeon_atom_set_memory_clock,
1038 .get_pcie_lanes = &r600_get_pcie_lanes,
1039 .set_pcie_lanes = &r600_set_pcie_lanes,
1040 .set_clock_gating = NULL,
1041 .get_temperature = &rv6xx_get_temp,
1b9ba70a 1042 .set_uvd_clocks = &r600_set_uvd_clocks,
ca361b65 1043 },
4a6369e9
AD		 1044 .dpm = {
1045 .init = &rv6xx_dpm_init,
1046 .setup_asic = &rv6xx_setup_asic,
1047 .enable = &rv6xx_dpm_enable,
a4643ba3 1048 .late_enable = &r600_dpm_late_enable,
4a6369e9 1049 .disable = &rv6xx_dpm_disable,
98243917 1050 .pre_set_power_state = &r600_dpm_pre_set_power_state,
4a6369e9 1051 .set_power_state = &rv6xx_dpm_set_power_state,
98243917 1052 .post_set_power_state = &r600_dpm_post_set_power_state,
4a6369e9
AD		 1053 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1054 .fini = &rv6xx_dpm_fini,
1055 .get_sclk = &rv6xx_dpm_get_sclk,
1056 .get_mclk = &rv6xx_dpm_get_mclk,
1057 .print_power_state = &rv6xx_dpm_print_power_state,
242916a5 1058 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
f4f85a8c 1059 .force_performance_level = &rv6xx_dpm_force_performance_level,
4a6369e9 1060 },
ca361b65
AD		 1061 .pflip = {
1062 .pre_page_flip = &rs600_pre_page_flip,
1063 .page_flip = &rs600_page_flip,
1064 .post_page_flip = &rs600_post_page_flip,
1065 },
1066};
1067
f47299c5
AD		 1068static struct radeon_asic rs780_asic = {
1069 .init = &r600_init,
1070 .fini = &r600_fini,
1071 .suspend = &r600_suspend,
1072 .resume = &r600_resume,
f47299c5 1073 .vga_set_state = &r600_vga_set_state,
a2d07b74 1074 .asic_reset = &r600_asic_reset,
54e88e06
AD		 1075 .ioctl_wait_idle = r600_ioctl_wait_idle,
1076 .gui_idle = &r600_gui_idle,
1077 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 1078 .get_xclk = &r600_get_xclk,
d0418894 1079 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1080 .gart = {
1081 .tlb_flush = &r600_pcie_gart_tlb_flush,
1082 .set_page = &rs600_gart_set_page,
1083 },
4c87bc26 1084 .ring = {
76a0df85
CK		 1085 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1086 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
4c87bc26 1087 },
b35ea4ab
AD		 1088 .irq = {
1089 .set = &r600_irq_set,
1090 .process = &r600_irq_process,
1091 },
c79a49ca
AD		 1092 .display = {
1093 .bandwidth_update = &rs690_bandwidth_update,
1094 .get_vblank_counter = &rs600_get_vblank_counter,
1095 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 1096 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1097 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1098 .hdmi_enable = &r600_hdmi_enable,
1099 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 1100 },
27cd7769 1101 .copy = {
8dddb993 1102 .blit = &r600_copy_cpdma,
27cd7769 1103 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
4d75658b
AD		 1104 .dma = &r600_copy_dma,
1105 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
bfea6a68 1106 .copy = &r600_copy_cpdma,
aeea40cb 1107 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
27cd7769 1108 },
9e6f3d02
AD		 1109 .surface = {
1110 .set_reg = r600_set_surface_reg,
1111 .clear_reg = r600_clear_surface_reg,
1112 },
901ea57d
AD		 1113 .hpd = {
1114 .init = &r600_hpd_init,
1115 .fini = &r600_hpd_fini,
1116 .sense = &r600_hpd_sense,
1117 .set_polarity = &r600_hpd_set_polarity,
1118 },
a02fa397
AD		 1119 .pm = {
1120 .misc = &r600_pm_misc,
1121 .prepare = &rs600_pm_prepare,
1122 .finish = &rs600_pm_finish,
1123 .init_profile = &rs780_pm_init_profile,
1124 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1125 .get_engine_clock = &radeon_atom_get_engine_clock,
1126 .set_engine_clock = &radeon_atom_set_engine_clock,
1127 .get_memory_clock = NULL,
1128 .set_memory_clock = NULL,
1129 .get_pcie_lanes = NULL,
1130 .set_pcie_lanes = NULL,
1131 .set_clock_gating = NULL,
6bd1c385 1132 .get_temperature = &rv6xx_get_temp,
1b9ba70a 1133 .set_uvd_clocks = &r600_set_uvd_clocks,
a02fa397 1134 },
9d67006e
AD		 1135 .dpm = {
1136 .init = &rs780_dpm_init,
1137 .setup_asic = &rs780_dpm_setup_asic,
1138 .enable = &rs780_dpm_enable,
a4643ba3 1139 .late_enable = &r600_dpm_late_enable,
9d67006e 1140 .disable = &rs780_dpm_disable,
98243917 1141 .pre_set_power_state = &r600_dpm_pre_set_power_state,
9d67006e 1142 .set_power_state = &rs780_dpm_set_power_state,
98243917 1143 .post_set_power_state = &r600_dpm_post_set_power_state,
9d67006e
AD		 1144 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1145 .fini = &rs780_dpm_fini,
1146 .get_sclk = &rs780_dpm_get_sclk,
1147 .get_mclk = &rs780_dpm_get_mclk,
1148 .print_power_state = &rs780_dpm_print_power_state,
444bddc4 1149 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
63580c3e 1150 .force_performance_level = &rs780_dpm_force_performance_level,
9d67006e 1151 },
0f9e006c
AD		 1152 .pflip = {
1153 .pre_page_flip = &rs600_pre_page_flip,
1154 .page_flip = &rs600_page_flip,
1155 .post_page_flip = &rs600_post_page_flip,
1156 },
f47299c5
AD		 1157};
1158
76a0df85 1159static struct radeon_asic_ring rv770_uvd_ring = {
e409b128
CK		 1160 .ib_execute = &uvd_v1_0_ib_execute,
1161 .emit_fence = &uvd_v2_2_fence_emit,
1162 .emit_semaphore = &uvd_v1_0_semaphore_emit,
76a0df85 1163 .cs_parse = &radeon_uvd_cs_parse,
e409b128
CK		 1164 .ring_test = &uvd_v1_0_ring_test,
1165 .ib_test = &uvd_v1_0_ib_test,
76a0df85 1166 .is_lockup = &radeon_ring_test_lockup,
e409b128
CK		 1167 .get_rptr = &uvd_v1_0_get_rptr,
1168 .get_wptr = &uvd_v1_0_get_wptr,
1169 .set_wptr = &uvd_v1_0_set_wptr,
76a0df85
CK		 1170};
1171
48e7a5f1
DV		 1172static struct radeon_asic rv770_asic = {
1173 .init = &rv770_init,
1174 .fini = &rv770_fini,
1175 .suspend = &rv770_suspend,
1176 .resume = &rv770_resume,
a2d07b74 1177 .asic_reset = &r600_asic_reset,
48e7a5f1 1178 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1179 .ioctl_wait_idle = r600_ioctl_wait_idle,
1180 .gui_idle = &r600_gui_idle,
1181 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 1182 .get_xclk = &rv770_get_xclk,
d0418894 1183 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1184 .gart = {
1185 .tlb_flush = &r600_pcie_gart_tlb_flush,
1186 .set_page = &rs600_gart_set_page,
1187 },
4c87bc26 1188 .ring = {
76a0df85
CK		 1189 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1190 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1191 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1192 },
b35ea4ab
AD		 1193 .irq = {
1194 .set = &r600_irq_set,
1195 .process = &r600_irq_process,
1196 },
c79a49ca
AD		 1197 .display = {
1198 .bandwidth_update = &rv515_bandwidth_update,
1199 .get_vblank_counter = &rs600_get_vblank_counter,
1200 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 1201 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1202 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1203 .hdmi_enable = &r600_hdmi_enable,
1204 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 1205 },
27cd7769 1206 .copy = {
8dddb993 1207 .blit = &r600_copy_cpdma,
27cd7769 1208 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
43fb7787 1209 .dma = &rv770_copy_dma,
4d75658b 1210 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
43fb7787 1211 .copy = &rv770_copy_dma,
2d6cc729 1212 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1213 },
9e6f3d02
AD		 1214 .surface = {
1215 .set_reg = r600_set_surface_reg,
1216 .clear_reg = r600_clear_surface_reg,
1217 },
901ea57d
AD		 1218 .hpd = {
1219 .init = &r600_hpd_init,
1220 .fini = &r600_hpd_fini,
1221 .sense = &r600_hpd_sense,
1222 .set_polarity = &r600_hpd_set_polarity,
1223 },
a02fa397
AD		 1224 .pm = {
1225 .misc = &rv770_pm_misc,
1226 .prepare = &rs600_pm_prepare,
1227 .finish = &rs600_pm_finish,
1228 .init_profile = &r600_pm_init_profile,
1229 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1230 .get_engine_clock = &radeon_atom_get_engine_clock,
1231 .set_engine_clock = &radeon_atom_set_engine_clock,
1232 .get_memory_clock = &radeon_atom_get_memory_clock,
1233 .set_memory_clock = &radeon_atom_set_memory_clock,
1234 .get_pcie_lanes = &r600_get_pcie_lanes,
1235 .set_pcie_lanes = &r600_set_pcie_lanes,
1236 .set_clock_gating = &radeon_atom_set_clock_gating,
ef0e6e65 1237 .set_uvd_clocks = &rv770_set_uvd_clocks,
6bd1c385 1238 .get_temperature = &rv770_get_temp,
a02fa397 1239 },
66229b20
AD		 1240 .dpm = {
1241 .init = &rv770_dpm_init,
1242 .setup_asic = &rv770_dpm_setup_asic,
1243 .enable = &rv770_dpm_enable,
a3f11245 1244 .late_enable = &rv770_dpm_late_enable,
66229b20 1245 .disable = &rv770_dpm_disable,
98243917 1246 .pre_set_power_state = &r600_dpm_pre_set_power_state,
66229b20 1247 .set_power_state = &rv770_dpm_set_power_state,
98243917 1248 .post_set_power_state = &r600_dpm_post_set_power_state,
66229b20
AD		 1249 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1250 .fini = &rv770_dpm_fini,
1251 .get_sclk = &rv770_dpm_get_sclk,
1252 .get_mclk = &rv770_dpm_get_mclk,
1253 .print_power_state = &rv770_dpm_print_power_state,
bd210d11 1254 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
8b5e6b7f 1255 .force_performance_level = &rv770_dpm_force_performance_level,
b06195d9 1256 .vblank_too_short = &rv770_dpm_vblank_too_short,
66229b20 1257 },
0f9e006c
AD		 1258 .pflip = {
1259 .pre_page_flip = &rs600_pre_page_flip,
1260 .page_flip = &rv770_page_flip,
1261 .post_page_flip = &rs600_post_page_flip,
1262 },
48e7a5f1
DV		 1263};
1264
76a0df85
CK		 1265static struct radeon_asic_ring evergreen_gfx_ring = {
1266 .ib_execute = &evergreen_ring_ib_execute,
1267 .emit_fence = &r600_fence_ring_emit,
1268 .emit_semaphore = &r600_semaphore_ring_emit,
1269 .cs_parse = &evergreen_cs_parse,
1270 .ring_test = &r600_ring_test,
1271 .ib_test = &r600_ib_test,
1272 .is_lockup = &evergreen_gfx_is_lockup,
1273 .get_rptr = &radeon_ring_generic_get_rptr,
1274 .get_wptr = &radeon_ring_generic_get_wptr,
1275 .set_wptr = &radeon_ring_generic_set_wptr,
1276};
1277
1278static struct radeon_asic_ring evergreen_dma_ring = {
1279 .ib_execute = &evergreen_dma_ring_ib_execute,
1280 .emit_fence = &evergreen_dma_fence_ring_emit,
1281 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1282 .cs_parse = &evergreen_dma_cs_parse,
1283 .ring_test = &r600_dma_ring_test,
1284 .ib_test = &r600_dma_ib_test,
1285 .is_lockup = &evergreen_dma_is_lockup,
2e1e6dad
CK		 1286 .get_rptr = &r600_dma_get_rptr,
1287 .get_wptr = &r600_dma_get_wptr,
1288 .set_wptr = &r600_dma_set_wptr,
76a0df85
CK		 1289};
1290
48e7a5f1
DV		 1291static struct radeon_asic evergreen_asic = {
1292 .init = &evergreen_init,
1293 .fini = &evergreen_fini,
1294 .suspend = &evergreen_suspend,
1295 .resume = &evergreen_resume,
a2d07b74 1296 .asic_reset = &evergreen_asic_reset,
48e7a5f1 1297 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1298 .ioctl_wait_idle = r600_ioctl_wait_idle,
1299 .gui_idle = &r600_gui_idle,
1300 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1301 .get_xclk = &rv770_get_xclk,
d0418894 1302 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1303 .gart = {
1304 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1305 .set_page = &rs600_gart_set_page,
1306 },
4c87bc26 1307 .ring = {
76a0df85
CK		 1308 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1309 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1310 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1311 },
b35ea4ab
AD		 1312 .irq = {
1313 .set = &evergreen_irq_set,
1314 .process = &evergreen_irq_process,
1315 },
c79a49ca
AD		 1316 .display = {
1317 .bandwidth_update = &evergreen_bandwidth_update,
1318 .get_vblank_counter = &evergreen_get_vblank_counter,
1319 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1320 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1321 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1322 .hdmi_enable = &evergreen_hdmi_enable,
1323 .hdmi_setmode = &evergreen_hdmi_setmode,
c79a49ca 1324 },
27cd7769 1325 .copy = {
8dddb993 1326 .blit = &r600_copy_cpdma,
27cd7769 1327 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1328 .dma = &evergreen_copy_dma,
1329 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1330 .copy = &evergreen_copy_dma,
1331 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1332 },
9e6f3d02
AD		 1333 .surface = {
1334 .set_reg = r600_set_surface_reg,
1335 .clear_reg = r600_clear_surface_reg,
1336 },
901ea57d
AD		 1337 .hpd = {
1338 .init = &evergreen_hpd_init,
1339 .fini = &evergreen_hpd_fini,
1340 .sense = &evergreen_hpd_sense,
1341 .set_polarity = &evergreen_hpd_set_polarity,
1342 },
a02fa397
AD		 1343 .pm = {
1344 .misc = &evergreen_pm_misc,
1345 .prepare = &evergreen_pm_prepare,
1346 .finish = &evergreen_pm_finish,
1347 .init_profile = &r600_pm_init_profile,
1348 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1349 .get_engine_clock = &radeon_atom_get_engine_clock,
1350 .set_engine_clock = &radeon_atom_set_engine_clock,
1351 .get_memory_clock = &radeon_atom_get_memory_clock,
1352 .set_memory_clock = &radeon_atom_set_memory_clock,
1353 .get_pcie_lanes = &r600_get_pcie_lanes,
1354 .set_pcie_lanes = &r600_set_pcie_lanes,
1355 .set_clock_gating = NULL,
a8b4925c 1356 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1357 .get_temperature = &evergreen_get_temp,
a02fa397 1358 },
dc50ba7f
AD		 1359 .dpm = {
1360 .init = &cypress_dpm_init,
1361 .setup_asic = &cypress_dpm_setup_asic,
1362 .enable = &cypress_dpm_enable,
a3f11245 1363 .late_enable = &rv770_dpm_late_enable,
dc50ba7f 1364 .disable = &cypress_dpm_disable,
98243917 1365 .pre_set_power_state = &r600_dpm_pre_set_power_state,
dc50ba7f 1366 .set_power_state = &cypress_dpm_set_power_state,
98243917 1367 .post_set_power_state = &r600_dpm_post_set_power_state,
dc50ba7f
AD		 1368 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1369 .fini = &cypress_dpm_fini,
1370 .get_sclk = &rv770_dpm_get_sclk,
1371 .get_mclk = &rv770_dpm_get_mclk,
1372 .print_power_state = &rv770_dpm_print_power_state,
bd210d11 1373 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
8b5e6b7f 1374 .force_performance_level = &rv770_dpm_force_performance_level,
d0b54bdc 1375 .vblank_too_short = &cypress_dpm_vblank_too_short,
dc50ba7f 1376 },
0f9e006c
AD		 1377 .pflip = {
1378 .pre_page_flip = &evergreen_pre_page_flip,
1379 .page_flip = &evergreen_page_flip,
1380 .post_page_flip = &evergreen_post_page_flip,
1381 },
48e7a5f1
DV		 1382};
1383
958261d1
AD		 1384static struct radeon_asic sumo_asic = {
1385 .init = &evergreen_init,
1386 .fini = &evergreen_fini,
1387 .suspend = &evergreen_suspend,
1388 .resume = &evergreen_resume,
958261d1
AD		 1389 .asic_reset = &evergreen_asic_reset,
1390 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1391 .ioctl_wait_idle = r600_ioctl_wait_idle,
1392 .gui_idle = &r600_gui_idle,
1393 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1394 .get_xclk = &r600_get_xclk,
d0418894 1395 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1396 .gart = {
1397 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1398 .set_page = &rs600_gart_set_page,
1399 },
4c87bc26 1400 .ring = {
76a0df85
CK		 1401 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1402 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1403 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1404 },
b35ea4ab
AD		 1405 .irq = {
1406 .set = &evergreen_irq_set,
1407 .process = &evergreen_irq_process,
1408 },
c79a49ca
AD		 1409 .display = {
1410 .bandwidth_update = &evergreen_bandwidth_update,
1411 .get_vblank_counter = &evergreen_get_vblank_counter,
1412 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1413 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1414 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1415 .hdmi_enable = &evergreen_hdmi_enable,
1416 .hdmi_setmode = &evergreen_hdmi_setmode,
c79a49ca 1417 },
27cd7769 1418 .copy = {
8dddb993 1419 .blit = &r600_copy_cpdma,
27cd7769 1420 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1421 .dma = &evergreen_copy_dma,
1422 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1423 .copy = &evergreen_copy_dma,
1424 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1425 },
9e6f3d02
AD		 1426 .surface = {
1427 .set_reg = r600_set_surface_reg,
1428 .clear_reg = r600_clear_surface_reg,
1429 },
901ea57d
AD		 1430 .hpd = {
1431 .init = &evergreen_hpd_init,
1432 .fini = &evergreen_hpd_fini,
1433 .sense = &evergreen_hpd_sense,
1434 .set_polarity = &evergreen_hpd_set_polarity,
1435 },
a02fa397
AD		 1436 .pm = {
1437 .misc = &evergreen_pm_misc,
1438 .prepare = &evergreen_pm_prepare,
1439 .finish = &evergreen_pm_finish,
1440 .init_profile = &sumo_pm_init_profile,
1441 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1442 .get_engine_clock = &radeon_atom_get_engine_clock,
1443 .set_engine_clock = &radeon_atom_set_engine_clock,
1444 .get_memory_clock = NULL,
1445 .set_memory_clock = NULL,
1446 .get_pcie_lanes = NULL,
1447 .set_pcie_lanes = NULL,
1448 .set_clock_gating = NULL,
23d33ba3 1449 .set_uvd_clocks = &sumo_set_uvd_clocks,
6bd1c385 1450 .get_temperature = &sumo_get_temp,
a02fa397 1451 },
80ea2c12
AD		 1452 .dpm = {
1453 .init = &sumo_dpm_init,
1454 .setup_asic = &sumo_dpm_setup_asic,
1455 .enable = &sumo_dpm_enable,
1456 .disable = &sumo_dpm_disable,
422a56bc 1457 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
80ea2c12 1458 .set_power_state = &sumo_dpm_set_power_state,
422a56bc 1459 .post_set_power_state = &sumo_dpm_post_set_power_state,
80ea2c12
AD		 1460 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1461 .fini = &sumo_dpm_fini,
1462 .get_sclk = &sumo_dpm_get_sclk,
1463 .get_mclk = &sumo_dpm_get_mclk,
1464 .print_power_state = &sumo_dpm_print_power_state,
fb70160c 1465 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
5d5e5591 1466 .force_performance_level = &sumo_dpm_force_performance_level,
80ea2c12 1467 },
0f9e006c
AD		 1468 .pflip = {
1469 .pre_page_flip = &evergreen_pre_page_flip,
1470 .page_flip = &evergreen_page_flip,
1471 .post_page_flip = &evergreen_post_page_flip,
1472 },
958261d1
AD		 1473};
1474
a43b7665
AD		 1475static struct radeon_asic btc_asic = {
1476 .init = &evergreen_init,
1477 .fini = &evergreen_fini,
1478 .suspend = &evergreen_suspend,
1479 .resume = &evergreen_resume,
a43b7665
AD		 1480 .asic_reset = &evergreen_asic_reset,
1481 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1482 .ioctl_wait_idle = r600_ioctl_wait_idle,
1483 .gui_idle = &r600_gui_idle,
1484 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1485 .get_xclk = &rv770_get_xclk,
d0418894 1486 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1487 .gart = {
1488 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1489 .set_page = &rs600_gart_set_page,
1490 },
4c87bc26 1491 .ring = {
76a0df85
CK		 1492 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1493 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1494 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
4c87bc26 1495 },
b35ea4ab
AD		 1496 .irq = {
1497 .set = &evergreen_irq_set,
1498 .process = &evergreen_irq_process,
1499 },
c79a49ca
AD		 1500 .display = {
1501 .bandwidth_update = &evergreen_bandwidth_update,
1502 .get_vblank_counter = &evergreen_get_vblank_counter,
1503 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1504 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1505 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1506 .hdmi_enable = &evergreen_hdmi_enable,
1507 .hdmi_setmode = &evergreen_hdmi_setmode,
c79a49ca 1508 },
27cd7769 1509 .copy = {
8dddb993 1510 .blit = &r600_copy_cpdma,
27cd7769 1511 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1512 .dma = &evergreen_copy_dma,
1513 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1514 .copy = &evergreen_copy_dma,
1515 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1516 },
9e6f3d02
AD		 1517 .surface = {
1518 .set_reg = r600_set_surface_reg,
1519 .clear_reg = r600_clear_surface_reg,
1520 },
901ea57d
AD		 1521 .hpd = {
1522 .init = &evergreen_hpd_init,
1523 .fini = &evergreen_hpd_fini,
1524 .sense = &evergreen_hpd_sense,
1525 .set_polarity = &evergreen_hpd_set_polarity,
1526 },
a02fa397
AD		 1527 .pm = {
1528 .misc = &evergreen_pm_misc,
1529 .prepare = &evergreen_pm_prepare,
1530 .finish = &evergreen_pm_finish,
27810fb2 1531 .init_profile = &btc_pm_init_profile,
a02fa397 1532 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1533 .get_engine_clock = &radeon_atom_get_engine_clock,
1534 .set_engine_clock = &radeon_atom_set_engine_clock,
1535 .get_memory_clock = &radeon_atom_get_memory_clock,
1536 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1537 .get_pcie_lanes = &r600_get_pcie_lanes,
1538 .set_pcie_lanes = &r600_set_pcie_lanes,
798bcf73 1539 .set_clock_gating = NULL,
a8b4925c 1540 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1541 .get_temperature = &evergreen_get_temp,
a02fa397 1542 },
6596afd4
AD		 1543 .dpm = {
1544 .init = &btc_dpm_init,
1545 .setup_asic = &btc_dpm_setup_asic,
1546 .enable = &btc_dpm_enable,
a3f11245 1547 .late_enable = &rv770_dpm_late_enable,
6596afd4 1548 .disable = &btc_dpm_disable,
e8a9539f 1549 .pre_set_power_state = &btc_dpm_pre_set_power_state,
6596afd4 1550 .set_power_state = &btc_dpm_set_power_state,
e8a9539f 1551 .post_set_power_state = &btc_dpm_post_set_power_state,
6596afd4
AD		 1552 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1553 .fini = &btc_dpm_fini,
e8a9539f
AD		 1554 .get_sclk = &btc_dpm_get_sclk,
1555 .get_mclk = &btc_dpm_get_mclk,
6596afd4 1556 .print_power_state = &rv770_dpm_print_power_state,
bd210d11 1557 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
8b5e6b7f 1558 .force_performance_level = &rv770_dpm_force_performance_level,
a84301c6 1559 .vblank_too_short = &btc_dpm_vblank_too_short,
6596afd4 1560 },
0f9e006c
AD		 1561 .pflip = {
1562 .pre_page_flip = &evergreen_pre_page_flip,
1563 .page_flip = &evergreen_page_flip,
1564 .post_page_flip = &evergreen_post_page_flip,
1565 },
a43b7665
AD		 1566};
1567
76a0df85
CK		 1568static struct radeon_asic_ring cayman_gfx_ring = {
1569 .ib_execute = &cayman_ring_ib_execute,
1570 .ib_parse = &evergreen_ib_parse,
1571 .emit_fence = &cayman_fence_ring_emit,
1572 .emit_semaphore = &r600_semaphore_ring_emit,
1573 .cs_parse = &evergreen_cs_parse,
1574 .ring_test = &r600_ring_test,
1575 .ib_test = &r600_ib_test,
1576 .is_lockup = &cayman_gfx_is_lockup,
1577 .vm_flush = &cayman_vm_flush,
1578 .get_rptr = &radeon_ring_generic_get_rptr,
1579 .get_wptr = &radeon_ring_generic_get_wptr,
1580 .set_wptr = &radeon_ring_generic_set_wptr,
1581};
1582
1583static struct radeon_asic_ring cayman_dma_ring = {
1584 .ib_execute = &cayman_dma_ring_ib_execute,
1585 .ib_parse = &evergreen_dma_ib_parse,
1586 .emit_fence = &evergreen_dma_fence_ring_emit,
1587 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1588 .cs_parse = &evergreen_dma_cs_parse,
1589 .ring_test = &r600_dma_ring_test,
1590 .ib_test = &r600_dma_ib_test,
1591 .is_lockup = &cayman_dma_is_lockup,
1592 .vm_flush = &cayman_dma_vm_flush,
2e1e6dad
CK		 1593 .get_rptr = &r600_dma_get_rptr,
1594 .get_wptr = &r600_dma_get_wptr,
1595 .set_wptr = &r600_dma_set_wptr
76a0df85
CK		 1596};
1597
1598static struct radeon_asic_ring cayman_uvd_ring = {
e409b128
CK		 1599 .ib_execute = &uvd_v1_0_ib_execute,
1600 .emit_fence = &uvd_v2_2_fence_emit,
1601 .emit_semaphore = &uvd_v3_1_semaphore_emit,
76a0df85 1602 .cs_parse = &radeon_uvd_cs_parse,
e409b128
CK		 1603 .ring_test = &uvd_v1_0_ring_test,
1604 .ib_test = &uvd_v1_0_ib_test,
76a0df85 1605 .is_lockup = &radeon_ring_test_lockup,
e409b128
CK		 1606 .get_rptr = &uvd_v1_0_get_rptr,
1607 .get_wptr = &uvd_v1_0_get_wptr,
1608 .set_wptr = &uvd_v1_0_set_wptr,
76a0df85
CK		 1609};
1610
e3487629
AD		 1611static struct radeon_asic cayman_asic = {
1612 .init = &cayman_init,
1613 .fini = &cayman_fini,
1614 .suspend = &cayman_suspend,
1615 .resume = &cayman_resume,
e3487629
AD		 1616 .asic_reset = &cayman_asic_reset,
1617 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1618 .ioctl_wait_idle = r600_ioctl_wait_idle,
1619 .gui_idle = &r600_gui_idle,
1620 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1621 .get_xclk = &rv770_get_xclk,
d0418894 1622 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1623 .gart = {
1624 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1625 .set_page = &rs600_gart_set_page,
1626 },
05b07147
CK		 1627 .vm = {
1628 .init = &cayman_vm_init,
1629 .fini = &cayman_vm_fini,
24c16439 1630 .set_page = &cayman_dma_vm_set_page,
05b07147 1631 },
4c87bc26 1632 .ring = {
76a0df85
CK		 1633 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1634 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1635 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1636 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1637 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1638 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
4c87bc26 1639 },
b35ea4ab
AD		 1640 .irq = {
1641 .set = &evergreen_irq_set,
1642 .process = &evergreen_irq_process,
1643 },
c79a49ca
AD		 1644 .display = {
1645 .bandwidth_update = &evergreen_bandwidth_update,
1646 .get_vblank_counter = &evergreen_get_vblank_counter,
1647 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1648 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1649 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1650 .hdmi_enable = &evergreen_hdmi_enable,
1651 .hdmi_setmode = &evergreen_hdmi_setmode,
c79a49ca 1652 },
27cd7769 1653 .copy = {
8dddb993 1654 .blit = &r600_copy_cpdma,
27cd7769 1655 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
f60cbd11
AD		 1656 .dma = &evergreen_copy_dma,
1657 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1658 .copy = &evergreen_copy_dma,
1659 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1660 },
9e6f3d02
AD		 1661 .surface = {
1662 .set_reg = r600_set_surface_reg,
1663 .clear_reg = r600_clear_surface_reg,
1664 },
901ea57d
AD		 1665 .hpd = {
1666 .init = &evergreen_hpd_init,
1667 .fini = &evergreen_hpd_fini,
1668 .sense = &evergreen_hpd_sense,
1669 .set_polarity = &evergreen_hpd_set_polarity,
1670 },
a02fa397
AD		 1671 .pm = {
1672 .misc = &evergreen_pm_misc,
1673 .prepare = &evergreen_pm_prepare,
1674 .finish = &evergreen_pm_finish,
27810fb2 1675 .init_profile = &btc_pm_init_profile,
a02fa397 1676 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1677 .get_engine_clock = &radeon_atom_get_engine_clock,
1678 .set_engine_clock = &radeon_atom_set_engine_clock,
1679 .get_memory_clock = &radeon_atom_get_memory_clock,
1680 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1681 .get_pcie_lanes = &r600_get_pcie_lanes,
1682 .set_pcie_lanes = &r600_set_pcie_lanes,
798bcf73 1683 .set_clock_gating = NULL,
a8b4925c 1684 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1685 .get_temperature = &evergreen_get_temp,
a02fa397 1686 },
69e0b57a
AD		 1687 .dpm = {
1688 .init = &ni_dpm_init,
1689 .setup_asic = &ni_dpm_setup_asic,
1690 .enable = &ni_dpm_enable,
a3f11245 1691 .late_enable = &rv770_dpm_late_enable,
69e0b57a 1692 .disable = &ni_dpm_disable,
fee3d744 1693 .pre_set_power_state = &ni_dpm_pre_set_power_state,
69e0b57a 1694 .set_power_state = &ni_dpm_set_power_state,
fee3d744 1695 .post_set_power_state = &ni_dpm_post_set_power_state,
69e0b57a
AD		 1696 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1697 .fini = &ni_dpm_fini,
1698 .get_sclk = &ni_dpm_get_sclk,
1699 .get_mclk = &ni_dpm_get_mclk,
1700 .print_power_state = &ni_dpm_print_power_state,
bdf0c4f0 1701 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
170a47f0 1702 .force_performance_level = &ni_dpm_force_performance_level,
76ad73e5 1703 .vblank_too_short = &ni_dpm_vblank_too_short,
69e0b57a 1704 },
0f9e006c
AD		 1705 .pflip = {
1706 .pre_page_flip = &evergreen_pre_page_flip,
1707 .page_flip = &evergreen_page_flip,
1708 .post_page_flip = &evergreen_post_page_flip,
1709 },
e3487629
AD		 1710};
1711
be63fe8c
AD		 1712static struct radeon_asic trinity_asic = {
1713 .init = &cayman_init,
1714 .fini = &cayman_fini,
1715 .suspend = &cayman_suspend,
1716 .resume = &cayman_resume,
be63fe8c
AD		 1717 .asic_reset = &cayman_asic_reset,
1718 .vga_set_state = &r600_vga_set_state,
1719 .ioctl_wait_idle = r600_ioctl_wait_idle,
1720 .gui_idle = &r600_gui_idle,
1721 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1722 .get_xclk = &r600_get_xclk,
d0418894 1723 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
be63fe8c
AD		 1724 .gart = {
1725 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1726 .set_page = &rs600_gart_set_page,
1727 },
05b07147
CK		 1728 .vm = {
1729 .init = &cayman_vm_init,
1730 .fini = &cayman_vm_fini,
24c16439 1731 .set_page = &cayman_dma_vm_set_page,
05b07147 1732 },
be63fe8c 1733 .ring = {
76a0df85
CK		 1734 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1735 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1736 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1737 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1738 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1739 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
be63fe8c
AD		 1740 },
1741 .irq = {
1742 .set = &evergreen_irq_set,
1743 .process = &evergreen_irq_process,
1744 },
1745 .display = {
1746 .bandwidth_update = &dce6_bandwidth_update,
1747 .get_vblank_counter = &evergreen_get_vblank_counter,
1748 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1749 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1750 .get_backlight_level = &atombios_get_backlight_level,
b530602f
AD		 1751 .hdmi_enable = &evergreen_hdmi_enable,
1752 .hdmi_setmode = &evergreen_hdmi_setmode,
be63fe8c
AD		 1753 },
1754 .copy = {
8dddb993 1755 .blit = &r600_copy_cpdma,
be63fe8c 1756 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
f60cbd11
AD		 1757 .dma = &evergreen_copy_dma,
1758 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1759 .copy = &evergreen_copy_dma,
1760 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
be63fe8c
AD		 1761 },
1762 .surface = {
1763 .set_reg = r600_set_surface_reg,
1764 .clear_reg = r600_clear_surface_reg,
1765 },
1766 .hpd = {
1767 .init = &evergreen_hpd_init,
1768 .fini = &evergreen_hpd_fini,
1769 .sense = &evergreen_hpd_sense,
1770 .set_polarity = &evergreen_hpd_set_polarity,
1771 },
1772 .pm = {
1773 .misc = &evergreen_pm_misc,
1774 .prepare = &evergreen_pm_prepare,
1775 .finish = &evergreen_pm_finish,
1776 .init_profile = &sumo_pm_init_profile,
1777 .get_dynpm_state = &r600_pm_get_dynpm_state,
1778 .get_engine_clock = &radeon_atom_get_engine_clock,
1779 .set_engine_clock = &radeon_atom_set_engine_clock,
1780 .get_memory_clock = NULL,
1781 .set_memory_clock = NULL,
1782 .get_pcie_lanes = NULL,
1783 .set_pcie_lanes = NULL,
1784 .set_clock_gating = NULL,
23d33ba3 1785 .set_uvd_clocks = &sumo_set_uvd_clocks,
29a15221 1786 .get_temperature = &tn_get_temp,
be63fe8c 1787 },
d70229f7
AD		 1788 .dpm = {
1789 .init = &trinity_dpm_init,
1790 .setup_asic = &trinity_dpm_setup_asic,
1791 .enable = &trinity_dpm_enable,
1792 .disable = &trinity_dpm_disable,
a284c48a 1793 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
d70229f7 1794 .set_power_state = &trinity_dpm_set_power_state,
a284c48a 1795 .post_set_power_state = &trinity_dpm_post_set_power_state,
d70229f7
AD		 1796 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
1797 .fini = &trinity_dpm_fini,
1798 .get_sclk = &trinity_dpm_get_sclk,
1799 .get_mclk = &trinity_dpm_get_mclk,
1800 .print_power_state = &trinity_dpm_print_power_state,
490ab931 1801 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
9b5de596 1802 .force_performance_level = &trinity_dpm_force_performance_level,
11877060 1803 .enable_bapm = &trinity_dpm_enable_bapm,
d70229f7 1804 },
be63fe8c
AD		 1805 .pflip = {
1806 .pre_page_flip = &evergreen_pre_page_flip,
1807 .page_flip = &evergreen_page_flip,
1808 .post_page_flip = &evergreen_post_page_flip,
1809 },
1810};
1811
76a0df85
CK		 1812static struct radeon_asic_ring si_gfx_ring = {
1813 .ib_execute = &si_ring_ib_execute,
1814 .ib_parse = &si_ib_parse,
1815 .emit_fence = &si_fence_ring_emit,
1816 .emit_semaphore = &r600_semaphore_ring_emit,
1817 .cs_parse = NULL,
1818 .ring_test = &r600_ring_test,
1819 .ib_test = &r600_ib_test,
1820 .is_lockup = &si_gfx_is_lockup,
1821 .vm_flush = &si_vm_flush,
1822 .get_rptr = &radeon_ring_generic_get_rptr,
1823 .get_wptr = &radeon_ring_generic_get_wptr,
1824 .set_wptr = &radeon_ring_generic_set_wptr,
1825};
1826
1827static struct radeon_asic_ring si_dma_ring = {
1828 .ib_execute = &cayman_dma_ring_ib_execute,
1829 .ib_parse = &evergreen_dma_ib_parse,
1830 .emit_fence = &evergreen_dma_fence_ring_emit,
1831 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1832 .cs_parse = NULL,
1833 .ring_test = &r600_dma_ring_test,
1834 .ib_test = &r600_dma_ib_test,
1835 .is_lockup = &si_dma_is_lockup,
1836 .vm_flush = &si_dma_vm_flush,
2e1e6dad
CK		 1837 .get_rptr = &r600_dma_get_rptr,
1838 .get_wptr = &r600_dma_get_wptr,
1839 .set_wptr = &r600_dma_set_wptr,
76a0df85
CK		 1840};
1841
02779c08
AD		 1842static struct radeon_asic si_asic = {
1843 .init = &si_init,
1844 .fini = &si_fini,
1845 .suspend = &si_suspend,
1846 .resume = &si_resume,
02779c08
AD		 1847 .asic_reset = &si_asic_reset,
1848 .vga_set_state = &r600_vga_set_state,
1849 .ioctl_wait_idle = r600_ioctl_wait_idle,
1850 .gui_idle = &r600_gui_idle,
1851 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1852 .get_xclk = &si_get_xclk,
d0418894 1853 .get_gpu_clock_counter = &si_get_gpu_clock_counter,
02779c08
AD		 1854 .gart = {
1855 .tlb_flush = &si_pcie_gart_tlb_flush,
1856 .set_page = &rs600_gart_set_page,
1857 },
05b07147
CK		 1858 .vm = {
1859 .init = &si_vm_init,
1860 .fini = &si_vm_fini,
24c16439 1861 .set_page = &si_dma_vm_set_page,
05b07147 1862 },
02779c08 1863 .ring = {
76a0df85
CK		 1864 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1865 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1866 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1867 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1868 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1869 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
02779c08
AD		 1870 },
1871 .irq = {
1872 .set = &si_irq_set,
1873 .process = &si_irq_process,
1874 },
1875 .display = {
1876 .bandwidth_update = &dce6_bandwidth_update,
1877 .get_vblank_counter = &evergreen_get_vblank_counter,
1878 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1879 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1880 .get_backlight_level = &atombios_get_backlight_level,
b530602f
AD		 1881 .hdmi_enable = &evergreen_hdmi_enable,
1882 .hdmi_setmode = &evergreen_hdmi_setmode,
02779c08
AD		 1883 },
1884 .copy = {
5c722739 1885 .blit = &r600_copy_cpdma,
02779c08 1886 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
8c5fd7ef
AD		 1887 .dma = &si_copy_dma,
1888 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1889 .copy = &si_copy_dma,
1890 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
02779c08
AD		 1891 },
1892 .surface = {
1893 .set_reg = r600_set_surface_reg,
1894 .clear_reg = r600_clear_surface_reg,
1895 },
1896 .hpd = {
1897 .init = &evergreen_hpd_init,
1898 .fini = &evergreen_hpd_fini,
1899 .sense = &evergreen_hpd_sense,
1900 .set_polarity = &evergreen_hpd_set_polarity,
1901 },
1902 .pm = {
1903 .misc = &evergreen_pm_misc,
1904 .prepare = &evergreen_pm_prepare,
1905 .finish = &evergreen_pm_finish,
1906 .init_profile = &sumo_pm_init_profile,
1907 .get_dynpm_state = &r600_pm_get_dynpm_state,
1908 .get_engine_clock = &radeon_atom_get_engine_clock,
1909 .set_engine_clock = &radeon_atom_set_engine_clock,
1910 .get_memory_clock = &radeon_atom_get_memory_clock,
1911 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1912 .get_pcie_lanes = &r600_get_pcie_lanes,
1913 .set_pcie_lanes = &r600_set_pcie_lanes,
02779c08 1914 .set_clock_gating = NULL,
2539eb02 1915 .set_uvd_clocks = &si_set_uvd_clocks,
6bd1c385 1916 .get_temperature = &si_get_temp,
02779c08 1917 },
a9e61410
AD		 1918 .dpm = {
1919 .init = &si_dpm_init,
1920 .setup_asic = &si_dpm_setup_asic,
1921 .enable = &si_dpm_enable,
1922 .disable = &si_dpm_disable,
1923 .pre_set_power_state = &si_dpm_pre_set_power_state,
1924 .set_power_state = &si_dpm_set_power_state,
1925 .post_set_power_state = &si_dpm_post_set_power_state,
1926 .display_configuration_changed = &si_dpm_display_configuration_changed,
1927 .fini = &si_dpm_fini,
1928 .get_sclk = &ni_dpm_get_sclk,
1929 .get_mclk = &ni_dpm_get_mclk,
1930 .print_power_state = &ni_dpm_print_power_state,
7982128c 1931 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
a160a6a3 1932 .force_performance_level = &si_dpm_force_performance_level,
f4dec318 1933 .vblank_too_short = &ni_dpm_vblank_too_short,
a9e61410 1934 },
02779c08
AD		 1935 .pflip = {
1936 .pre_page_flip = &evergreen_pre_page_flip,
1937 .page_flip = &evergreen_page_flip,
1938 .post_page_flip = &evergreen_post_page_flip,
1939 },
1940};
1941
76a0df85
CK		 1942static struct radeon_asic_ring ci_gfx_ring = {
1943 .ib_execute = &cik_ring_ib_execute,
1944 .ib_parse = &cik_ib_parse,
1945 .emit_fence = &cik_fence_gfx_ring_emit,
1946 .emit_semaphore = &cik_semaphore_ring_emit,
1947 .cs_parse = NULL,
1948 .ring_test = &cik_ring_test,
1949 .ib_test = &cik_ib_test,
1950 .is_lockup = &cik_gfx_is_lockup,
1951 .vm_flush = &cik_vm_flush,
1952 .get_rptr = &radeon_ring_generic_get_rptr,
1953 .get_wptr = &radeon_ring_generic_get_wptr,
1954 .set_wptr = &radeon_ring_generic_set_wptr,
1955};
1956
1957static struct radeon_asic_ring ci_cp_ring = {
1958 .ib_execute = &cik_ring_ib_execute,
1959 .ib_parse = &cik_ib_parse,
1960 .emit_fence = &cik_fence_compute_ring_emit,
1961 .emit_semaphore = &cik_semaphore_ring_emit,
1962 .cs_parse = NULL,
1963 .ring_test = &cik_ring_test,
1964 .ib_test = &cik_ib_test,
1965 .is_lockup = &cik_gfx_is_lockup,
1966 .vm_flush = &cik_vm_flush,
1967 .get_rptr = &cik_compute_ring_get_rptr,
1968 .get_wptr = &cik_compute_ring_get_wptr,
1969 .set_wptr = &cik_compute_ring_set_wptr,
1970};
1971
1972static struct radeon_asic_ring ci_dma_ring = {
1973 .ib_execute = &cik_sdma_ring_ib_execute,
1974 .ib_parse = &cik_ib_parse,
1975 .emit_fence = &cik_sdma_fence_ring_emit,
1976 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
1977 .cs_parse = NULL,
1978 .ring_test = &cik_sdma_ring_test,
1979 .ib_test = &cik_sdma_ib_test,
1980 .is_lockup = &cik_sdma_is_lockup,
1981 .vm_flush = &cik_dma_vm_flush,
2e1e6dad
CK		 1982 .get_rptr = &r600_dma_get_rptr,
1983 .get_wptr = &r600_dma_get_wptr,
1984 .set_wptr = &r600_dma_set_wptr,
76a0df85
CK		 1985};
1986
0672e27b
AD		 1987static struct radeon_asic ci_asic = {
1988 .init = &cik_init,
1989 .fini = &cik_fini,
1990 .suspend = &cik_suspend,
1991 .resume = &cik_resume,
1992 .asic_reset = &cik_asic_reset,
1993 .vga_set_state = &r600_vga_set_state,
1994 .ioctl_wait_idle = NULL,
1995 .gui_idle = &r600_gui_idle,
1996 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1997 .get_xclk = &cik_get_xclk,
1998 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
1999 .gart = {
2000 .tlb_flush = &cik_pcie_gart_tlb_flush,
2001 .set_page = &rs600_gart_set_page,
2002 },
2003 .vm = {
2004 .init = &cik_vm_init,
2005 .fini = &cik_vm_fini,
24c16439 2006 .set_page = &cik_sdma_vm_set_page,
0672e27b
AD		 2007 },
2008 .ring = {
76a0df85
CK		 2009 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2010 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2011 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2012 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2013 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2014 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
0672e27b
AD		 2015 },
2016 .irq = {
2017 .set = &cik_irq_set,
2018 .process = &cik_irq_process,
2019 },
2020 .display = {
2021 .bandwidth_update = &dce8_bandwidth_update,
2022 .get_vblank_counter = &evergreen_get_vblank_counter,
2023 .wait_for_vblank = &dce4_wait_for_vblank,
7272c9d2
SL		 2024 .set_backlight_level = &atombios_set_backlight_level,
2025 .get_backlight_level = &atombios_get_backlight_level,
b530602f
AD		 2026 .hdmi_enable = &evergreen_hdmi_enable,
2027 .hdmi_setmode = &evergreen_hdmi_setmode,
0672e27b
AD		 2028 },
2029 .copy = {
2030 .blit = NULL,
2031 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2032 .dma = &cik_copy_dma,
2033 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2034 .copy = &cik_copy_dma,
2035 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2036 },
2037 .surface = {
2038 .set_reg = r600_set_surface_reg,
2039 .clear_reg = r600_clear_surface_reg,
2040 },
2041 .hpd = {
2042 .init = &evergreen_hpd_init,
2043 .fini = &evergreen_hpd_fini,
2044 .sense = &evergreen_hpd_sense,
2045 .set_polarity = &evergreen_hpd_set_polarity,
2046 },
2047 .pm = {
2048 .misc = &evergreen_pm_misc,
2049 .prepare = &evergreen_pm_prepare,
2050 .finish = &evergreen_pm_finish,
2051 .init_profile = &sumo_pm_init_profile,
2052 .get_dynpm_state = &r600_pm_get_dynpm_state,
2053 .get_engine_clock = &radeon_atom_get_engine_clock,
2054 .set_engine_clock = &radeon_atom_set_engine_clock,
2055 .get_memory_clock = &radeon_atom_get_memory_clock,
2056 .set_memory_clock = &radeon_atom_set_memory_clock,
2057 .get_pcie_lanes = NULL,
2058 .set_pcie_lanes = NULL,
2059 .set_clock_gating = NULL,
2060 .set_uvd_clocks = &cik_set_uvd_clocks,
286d9cc6 2061 .get_temperature = &ci_get_temp,
0672e27b 2062 },
cc8dbbb4
AD		 2063 .dpm = {
2064 .init = &ci_dpm_init,
2065 .setup_asic = &ci_dpm_setup_asic,
2066 .enable = &ci_dpm_enable,
2067 .disable = &ci_dpm_disable,
2068 .pre_set_power_state = &ci_dpm_pre_set_power_state,
2069 .set_power_state = &ci_dpm_set_power_state,
2070 .post_set_power_state = &ci_dpm_post_set_power_state,
2071 .display_configuration_changed = &ci_dpm_display_configuration_changed,
2072 .fini = &ci_dpm_fini,
2073 .get_sclk = &ci_dpm_get_sclk,
2074 .get_mclk = &ci_dpm_get_mclk,
2075 .print_power_state = &ci_dpm_print_power_state,
94b4adc5 2076 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
89536fd6 2077 .force_performance_level = &ci_dpm_force_performance_level,
5496131e 2078 .vblank_too_short = &ci_dpm_vblank_too_short,
942bdf7f 2079 .powergate_uvd = &ci_dpm_powergate_uvd,
cc8dbbb4 2080 },
0672e27b
AD		 2081 .pflip = {
2082 .pre_page_flip = &evergreen_pre_page_flip,
2083 .page_flip = &evergreen_page_flip,
2084 .post_page_flip = &evergreen_post_page_flip,
2085 },
2086};
2087
2088static struct radeon_asic kv_asic = {
2089 .init = &cik_init,
2090 .fini = &cik_fini,
2091 .suspend = &cik_suspend,
2092 .resume = &cik_resume,
2093 .asic_reset = &cik_asic_reset,
2094 .vga_set_state = &r600_vga_set_state,
2095 .ioctl_wait_idle = NULL,
2096 .gui_idle = &r600_gui_idle,
2097 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2098 .get_xclk = &cik_get_xclk,
2099 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2100 .gart = {
2101 .tlb_flush = &cik_pcie_gart_tlb_flush,
2102 .set_page = &rs600_gart_set_page,
2103 },
2104 .vm = {
2105 .init = &cik_vm_init,
2106 .fini = &cik_vm_fini,
24c16439 2107 .set_page = &cik_sdma_vm_set_page,
0672e27b
AD		 2108 },
2109 .ring = {
76a0df85
CK		 2110 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2111 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2112 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2113 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2114 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2115 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
0672e27b
AD		 2116 },
2117 .irq = {
2118 .set = &cik_irq_set,
2119 .process = &cik_irq_process,
2120 },
2121 .display = {
2122 .bandwidth_update = &dce8_bandwidth_update,
2123 .get_vblank_counter = &evergreen_get_vblank_counter,
2124 .wait_for_vblank = &dce4_wait_for_vblank,
7272c9d2
SL		 2125 .set_backlight_level = &atombios_set_backlight_level,
2126 .get_backlight_level = &atombios_get_backlight_level,
b530602f
AD		 2127 .hdmi_enable = &evergreen_hdmi_enable,
2128 .hdmi_setmode = &evergreen_hdmi_setmode,
0672e27b
AD		 2129 },
2130 .copy = {
2131 .blit = NULL,
2132 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2133 .dma = &cik_copy_dma,
2134 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2135 .copy = &cik_copy_dma,
2136 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2137 },
2138 .surface = {
2139 .set_reg = r600_set_surface_reg,
2140 .clear_reg = r600_clear_surface_reg,
2141 },
2142 .hpd = {
2143 .init = &evergreen_hpd_init,
2144 .fini = &evergreen_hpd_fini,
2145 .sense = &evergreen_hpd_sense,
2146 .set_polarity = &evergreen_hpd_set_polarity,
2147 },
2148 .pm = {
2149 .misc = &evergreen_pm_misc,
2150 .prepare = &evergreen_pm_prepare,
2151 .finish = &evergreen_pm_finish,
2152 .init_profile = &sumo_pm_init_profile,
2153 .get_dynpm_state = &r600_pm_get_dynpm_state,
2154 .get_engine_clock = &radeon_atom_get_engine_clock,
2155 .set_engine_clock = &radeon_atom_set_engine_clock,
2156 .get_memory_clock = &radeon_atom_get_memory_clock,
2157 .set_memory_clock = &radeon_atom_set_memory_clock,
2158 .get_pcie_lanes = NULL,
2159 .set_pcie_lanes = NULL,
2160 .set_clock_gating = NULL,
2161 .set_uvd_clocks = &cik_set_uvd_clocks,
286d9cc6 2162 .get_temperature = &kv_get_temp,
0672e27b 2163 },
41a524ab
AD		 2164 .dpm = {
2165 .init = &kv_dpm_init,
2166 .setup_asic = &kv_dpm_setup_asic,
2167 .enable = &kv_dpm_enable,
2168 .disable = &kv_dpm_disable,
2169 .pre_set_power_state = &kv_dpm_pre_set_power_state,
2170 .set_power_state = &kv_dpm_set_power_state,
2171 .post_set_power_state = &kv_dpm_post_set_power_state,
2172 .display_configuration_changed = &kv_dpm_display_configuration_changed,
2173 .fini = &kv_dpm_fini,
2174 .get_sclk = &kv_dpm_get_sclk,
2175 .get_mclk = &kv_dpm_get_mclk,
2176 .print_power_state = &kv_dpm_print_power_state,
ae3e40e8 2177 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2b4c8022 2178 .force_performance_level = &kv_dpm_force_performance_level,
77df508a 2179 .powergate_uvd = &kv_dpm_powergate_uvd,
b7a5ae97 2180 .enable_bapm = &kv_dpm_enable_bapm,
41a524ab 2181 },
0672e27b
AD		 2182 .pflip = {
2183 .pre_page_flip = &evergreen_pre_page_flip,
2184 .page_flip = &evergreen_page_flip,
2185 .post_page_flip = &evergreen_post_page_flip,
2186 },
2187};
2188
abf1dc67
AD		 2189/**
2190 * radeon_asic_init - register asic specific callbacks
2191 *
2192 * @rdev: radeon device pointer
2193 *
2194 * Registers the appropriate asic specific callbacks for each
2195 * chip family. Also sets other asics specific info like the number
2196 * of crtcs and the register aperture accessors (all asics).
2197 * Returns 0 for success.
2198 */
0a10c851
DV		 2199int radeon_asic_init(struct radeon_device *rdev)
2200{
2201 radeon_register_accessor_init(rdev);
ba7e05e9
AD		 2202
2203 /* set the number of crtcs */
2204 if (rdev->flags & RADEON_SINGLE_CRTC)
2205 rdev->num_crtc = 1;
2206 else
2207 rdev->num_crtc = 2;
2208
948bee3f
AD		 2209 rdev->has_uvd = false;
2210
0a10c851
DV		 2211 switch (rdev->family) {
2212 case CHIP_R100:
2213 case CHIP_RV100:
2214 case CHIP_RS100:
2215 case CHIP_RV200:
2216 case CHIP_RS200:
2217 rdev->asic = &r100_asic;
2218 break;
2219 case CHIP_R200:
2220 case CHIP_RV250:
2221 case CHIP_RS300:
2222 case CHIP_RV280:
2223 rdev->asic = &r200_asic;
2224 break;
2225 case CHIP_R300:
2226 case CHIP_R350:
2227 case CHIP_RV350:
2228 case CHIP_RV380:
2229 if (rdev->flags & RADEON_IS_PCIE)
2230 rdev->asic = &r300_asic_pcie;
2231 else
2232 rdev->asic = &r300_asic;
2233 break;
2234 case CHIP_R420:
2235 case CHIP_R423:
2236 case CHIP_RV410:
2237 rdev->asic = &r420_asic;
07bb084c
AD		 2238 /* handle macs */
2239 if (rdev->bios == NULL) {
798bcf73
AD		 2240 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2241 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2242 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2243 rdev->asic->pm.set_memory_clock = NULL;
37e9b6a6 2244 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
07bb084c 2245 }
0a10c851
DV		 2246 break;
2247 case CHIP_RS400:
2248 case CHIP_RS480:
2249 rdev->asic = &rs400_asic;
2250 break;
2251 case CHIP_RS600:
2252 rdev->asic = &rs600_asic;
2253 break;
2254 case CHIP_RS690:
2255 case CHIP_RS740:
2256 rdev->asic = &rs690_asic;
2257 break;
2258 case CHIP_RV515:
2259 rdev->asic = &rv515_asic;
2260 break;
2261 case CHIP_R520:
2262 case CHIP_RV530:
2263 case CHIP_RV560:
2264 case CHIP_RV570:
2265 case CHIP_R580:
2266 rdev->asic = &r520_asic;
2267 break;
2268 case CHIP_R600:
ca361b65
AD		 2269 rdev->asic = &r600_asic;
2270 break;
0a10c851
DV		 2271 case CHIP_RV610:
2272 case CHIP_RV630:
2273 case CHIP_RV620:
2274 case CHIP_RV635:
2275 case CHIP_RV670:
ca361b65
AD		 2276 rdev->asic = &rv6xx_asic;
2277 rdev->has_uvd = true;
f47299c5 2278 break;
0a10c851
DV		 2279 case CHIP_RS780:
2280 case CHIP_RS880:
f47299c5 2281 rdev->asic = &rs780_asic;
948bee3f 2282 rdev->has_uvd = true;
0a10c851
DV		 2283 break;
2284 case CHIP_RV770:
2285 case CHIP_RV730:
2286 case CHIP_RV710:
2287 case CHIP_RV740:
2288 rdev->asic = &rv770_asic;
948bee3f 2289 rdev->has_uvd = true;
0a10c851
DV		 2290 break;
2291 case CHIP_CEDAR:
2292 case CHIP_REDWOOD:
2293 case CHIP_JUNIPER:
2294 case CHIP_CYPRESS:
2295 case CHIP_HEMLOCK:
ba7e05e9
AD		 2296 /* set num crtcs */
2297 if (rdev->family == CHIP_CEDAR)
2298 rdev->num_crtc = 4;
2299 else
2300 rdev->num_crtc = 6;
0a10c851 2301 rdev->asic = &evergreen_asic;
948bee3f 2302 rdev->has_uvd = true;
0a10c851 2303 break;
958261d1 2304 case CHIP_PALM:
89da5a37
AD		 2305 case CHIP_SUMO:
2306 case CHIP_SUMO2:
958261d1 2307 rdev->asic = &sumo_asic;
948bee3f 2308 rdev->has_uvd = true;
958261d1 2309 break;
a43b7665
AD		 2310 case CHIP_BARTS:
2311 case CHIP_TURKS:
2312 case CHIP_CAICOS:
ba7e05e9
AD		 2313 /* set num crtcs */
2314 if (rdev->family == CHIP_CAICOS)
2315 rdev->num_crtc = 4;
2316 else
2317 rdev->num_crtc = 6;
a43b7665 2318 rdev->asic = &btc_asic;
948bee3f 2319 rdev->has_uvd = true;
a43b7665 2320 break;
e3487629
AD		 2321 case CHIP_CAYMAN:
2322 rdev->asic = &cayman_asic;
ba7e05e9
AD		 2323 /* set num crtcs */
2324 rdev->num_crtc = 6;
948bee3f 2325 rdev->has_uvd = true;
e3487629 2326 break;
be63fe8c
AD		 2327 case CHIP_ARUBA:
2328 rdev->asic = &trinity_asic;
2329 /* set num crtcs */
2330 rdev->num_crtc = 4;
948bee3f 2331 rdev->has_uvd = true;
be63fe8c 2332 break;
02779c08
AD		 2333 case CHIP_TAHITI:
2334 case CHIP_PITCAIRN:
2335 case CHIP_VERDE:
e737a14c 2336 case CHIP_OLAND:
86a45cac 2337 case CHIP_HAINAN:
02779c08
AD		 2338 rdev->asic = &si_asic;
2339 /* set num crtcs */
86a45cac
AD		 2340 if (rdev->family == CHIP_HAINAN)
2341 rdev->num_crtc = 0;
2342 else if (rdev->family == CHIP_OLAND)
e737a14c
AD		 2343 rdev->num_crtc = 2;
2344 else
2345 rdev->num_crtc = 6;
948bee3f
AD		 2346 if (rdev->family == CHIP_HAINAN)
2347 rdev->has_uvd = false;
2348 else
2349 rdev->has_uvd = true;
0116e1ef
AD		 2350 switch (rdev->family) {
2351 case CHIP_TAHITI:
2352 rdev->cg_flags =
090f4b6a 2353 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2354 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2355 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2356 RADEON_CG_SUPPORT_GFX_CGLS |
2357 RADEON_CG_SUPPORT_GFX_CGTS |
2358 RADEON_CG_SUPPORT_GFX_CP_LS |
2359 RADEON_CG_SUPPORT_MC_MGCG |
2360 RADEON_CG_SUPPORT_SDMA_MGCG |
2361 RADEON_CG_SUPPORT_BIF_LS |
2362 RADEON_CG_SUPPORT_VCE_MGCG |
2363 RADEON_CG_SUPPORT_UVD_MGCG |
2364 RADEON_CG_SUPPORT_HDP_LS |
2365 RADEON_CG_SUPPORT_HDP_MGCG;
2366 rdev->pg_flags = 0;
2367 break;
2368 case CHIP_PITCAIRN:
2369 rdev->cg_flags =
090f4b6a 2370 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2371 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2372 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2373 RADEON_CG_SUPPORT_GFX_CGLS |
2374 RADEON_CG_SUPPORT_GFX_CGTS |
2375 RADEON_CG_SUPPORT_GFX_CP_LS |
2376 RADEON_CG_SUPPORT_GFX_RLC_LS |
2377 RADEON_CG_SUPPORT_MC_LS |
2378 RADEON_CG_SUPPORT_MC_MGCG |
2379 RADEON_CG_SUPPORT_SDMA_MGCG |
2380 RADEON_CG_SUPPORT_BIF_LS |
2381 RADEON_CG_SUPPORT_VCE_MGCG |
2382 RADEON_CG_SUPPORT_UVD_MGCG |
2383 RADEON_CG_SUPPORT_HDP_LS |
2384 RADEON_CG_SUPPORT_HDP_MGCG;
2385 rdev->pg_flags = 0;
2386 break;
2387 case CHIP_VERDE:
2388 rdev->cg_flags =
090f4b6a 2389 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2390 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2391 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2392 RADEON_CG_SUPPORT_GFX_CGLS |
2393 RADEON_CG_SUPPORT_GFX_CGTS |
2394 RADEON_CG_SUPPORT_GFX_CP_LS |
2395 RADEON_CG_SUPPORT_GFX_RLC_LS |
2396 RADEON_CG_SUPPORT_MC_LS |
2397 RADEON_CG_SUPPORT_MC_MGCG |
2398 RADEON_CG_SUPPORT_SDMA_MGCG |
2399 RADEON_CG_SUPPORT_BIF_LS |
2400 RADEON_CG_SUPPORT_VCE_MGCG |
2401 RADEON_CG_SUPPORT_UVD_MGCG |
2402 RADEON_CG_SUPPORT_HDP_LS |
2403 RADEON_CG_SUPPORT_HDP_MGCG;
ca6ebb39 2404 rdev->pg_flags = 0 |
2b19d17f 2405 /*RADEON_PG_SUPPORT_GFX_PG | */
ca6ebb39 2406 RADEON_PG_SUPPORT_SDMA;
0116e1ef
AD		 2407 break;
2408 case CHIP_OLAND:
2409 rdev->cg_flags =
090f4b6a 2410 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2411 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2412 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2413 RADEON_CG_SUPPORT_GFX_CGLS |
2414 RADEON_CG_SUPPORT_GFX_CGTS |
2415 RADEON_CG_SUPPORT_GFX_CP_LS |
2416 RADEON_CG_SUPPORT_GFX_RLC_LS |
2417 RADEON_CG_SUPPORT_MC_LS |
2418 RADEON_CG_SUPPORT_MC_MGCG |
2419 RADEON_CG_SUPPORT_SDMA_MGCG |
2420 RADEON_CG_SUPPORT_BIF_LS |
2421 RADEON_CG_SUPPORT_UVD_MGCG |
2422 RADEON_CG_SUPPORT_HDP_LS |
2423 RADEON_CG_SUPPORT_HDP_MGCG;
2424 rdev->pg_flags = 0;
2425 break;
2426 case CHIP_HAINAN:
2427 rdev->cg_flags =
090f4b6a 2428 RADEON_CG_SUPPORT_GFX_MGCG |
0116e1ef 2429 RADEON_CG_SUPPORT_GFX_MGLS |
e16866ec 2430 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
0116e1ef
AD		 2431 RADEON_CG_SUPPORT_GFX_CGLS |
2432 RADEON_CG_SUPPORT_GFX_CGTS |
2433 RADEON_CG_SUPPORT_GFX_CP_LS |
2434 RADEON_CG_SUPPORT_GFX_RLC_LS |
2435 RADEON_CG_SUPPORT_MC_LS |
2436 RADEON_CG_SUPPORT_MC_MGCG |
2437 RADEON_CG_SUPPORT_SDMA_MGCG |
2438 RADEON_CG_SUPPORT_BIF_LS |
2439 RADEON_CG_SUPPORT_HDP_LS |
2440 RADEON_CG_SUPPORT_HDP_MGCG;
2441 rdev->pg_flags = 0;
2442 break;
2443 default:
2444 rdev->cg_flags = 0;
2445 rdev->pg_flags = 0;
2446 break;
2447 }
02779c08 2448 break;
0672e27b 2449 case CHIP_BONAIRE:
41971b37 2450 case CHIP_HAWAII:
0672e27b
AD		 2451 rdev->asic = &ci_asic;
2452 rdev->num_crtc = 6;
22c775ce 2453 rdev->has_uvd = true;
41971b37
AD		 2454 if (rdev->family == CHIP_BONAIRE) {
2455 rdev->cg_flags =
2456 RADEON_CG_SUPPORT_GFX_MGCG |
2457 RADEON_CG_SUPPORT_GFX_MGLS |
2458 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2459 RADEON_CG_SUPPORT_GFX_CGLS |
2460 RADEON_CG_SUPPORT_GFX_CGTS |
2461 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2462 RADEON_CG_SUPPORT_GFX_CP_LS |
2463 RADEON_CG_SUPPORT_MC_LS |
2464 RADEON_CG_SUPPORT_MC_MGCG |
2465 RADEON_CG_SUPPORT_SDMA_MGCG |
2466 RADEON_CG_SUPPORT_SDMA_LS |
2467 RADEON_CG_SUPPORT_BIF_LS |
2468 RADEON_CG_SUPPORT_VCE_MGCG |
2469 RADEON_CG_SUPPORT_UVD_MGCG |
2470 RADEON_CG_SUPPORT_HDP_LS |
2471 RADEON_CG_SUPPORT_HDP_MGCG;
2472 rdev->pg_flags = 0;
2473 } else {
2474 rdev->cg_flags =
2475 RADEON_CG_SUPPORT_GFX_MGCG |
2476 RADEON_CG_SUPPORT_GFX_MGLS |
2477 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2478 RADEON_CG_SUPPORT_GFX_CGLS |
2479 RADEON_CG_SUPPORT_GFX_CGTS |
2480 RADEON_CG_SUPPORT_GFX_CP_LS |
2481 RADEON_CG_SUPPORT_MC_LS |
2482 RADEON_CG_SUPPORT_MC_MGCG |
2483 RADEON_CG_SUPPORT_SDMA_MGCG |
2484 RADEON_CG_SUPPORT_SDMA_LS |
2485 RADEON_CG_SUPPORT_BIF_LS |
2486 RADEON_CG_SUPPORT_VCE_MGCG |
2487 RADEON_CG_SUPPORT_UVD_MGCG |
2488 RADEON_CG_SUPPORT_HDP_LS |
2489 RADEON_CG_SUPPORT_HDP_MGCG;
2490 rdev->pg_flags = 0;
2491 }
0672e27b
AD		 2492 break;
2493 case CHIP_KAVERI:
2494 case CHIP_KABINI:
2495 rdev->asic = &kv_asic;
2496 /* set num crtcs */
473359bc 2497 if (rdev->family == CHIP_KAVERI) {
0672e27b 2498 rdev->num_crtc = 4;
473359bc 2499 rdev->cg_flags =
773dc10a 2500 RADEON_CG_SUPPORT_GFX_MGCG |
473359bc
AD		 2501 RADEON_CG_SUPPORT_GFX_MGLS |
2502 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2503 RADEON_CG_SUPPORT_GFX_CGLS |
2504 RADEON_CG_SUPPORT_GFX_CGTS |
2505 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2506 RADEON_CG_SUPPORT_GFX_CP_LS |
2507 RADEON_CG_SUPPORT_SDMA_MGCG |
2508 RADEON_CG_SUPPORT_SDMA_LS |
2509 RADEON_CG_SUPPORT_BIF_LS |
2510 RADEON_CG_SUPPORT_VCE_MGCG |
2511 RADEON_CG_SUPPORT_UVD_MGCG |
2512 RADEON_CG_SUPPORT_HDP_LS |
2513 RADEON_CG_SUPPORT_HDP_MGCG;
2514 rdev->pg_flags = 0;
2b19d17f 2515 /*RADEON_PG_SUPPORT_GFX_PG |
473359bc
AD		 2516 RADEON_PG_SUPPORT_GFX_SMG |
2517 RADEON_PG_SUPPORT_GFX_DMG |
2518 RADEON_PG_SUPPORT_UVD |
2519 RADEON_PG_SUPPORT_VCE |
2520 RADEON_PG_SUPPORT_CP |
2521 RADEON_PG_SUPPORT_GDS |
2522 RADEON_PG_SUPPORT_RLC_SMU_HS |
2523 RADEON_PG_SUPPORT_ACP |
2524 RADEON_PG_SUPPORT_SAMU;*/
2525 } else {
0672e27b 2526 rdev->num_crtc = 2;
473359bc 2527 rdev->cg_flags =
773dc10a 2528 RADEON_CG_SUPPORT_GFX_MGCG |
473359bc
AD		 2529 RADEON_CG_SUPPORT_GFX_MGLS |
2530 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2531 RADEON_CG_SUPPORT_GFX_CGLS |
2532 RADEON_CG_SUPPORT_GFX_CGTS |
2533 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2534 RADEON_CG_SUPPORT_GFX_CP_LS |
2535 RADEON_CG_SUPPORT_SDMA_MGCG |
2536 RADEON_CG_SUPPORT_SDMA_LS |
2537 RADEON_CG_SUPPORT_BIF_LS |
2538 RADEON_CG_SUPPORT_VCE_MGCG |
2539 RADEON_CG_SUPPORT_UVD_MGCG |
2540 RADEON_CG_SUPPORT_HDP_LS |
2541 RADEON_CG_SUPPORT_HDP_MGCG;
2542 rdev->pg_flags = 0;
2b19d17f 2543 /*RADEON_PG_SUPPORT_GFX_PG |
473359bc
AD		 2544 RADEON_PG_SUPPORT_GFX_SMG |
2545 RADEON_PG_SUPPORT_UVD |
2546 RADEON_PG_SUPPORT_VCE |
2547 RADEON_PG_SUPPORT_CP |
2548 RADEON_PG_SUPPORT_GDS |
2549 RADEON_PG_SUPPORT_RLC_SMU_HS |
2550 RADEON_PG_SUPPORT_SAMU;*/
2551 }
22c775ce 2552 rdev->has_uvd = true;
0672e27b 2553 break;
0a10c851
DV		 2554 default:
2555 /* FIXME: not supported yet */
2556 return -EINVAL;
2557 }
2558
2559 if (rdev->flags & RADEON_IS_IGP) {
798bcf73
AD		 2560 rdev->asic->pm.get_memory_clock = NULL;
2561 rdev->asic->pm.set_memory_clock = NULL;
0a10c851
DV		 2562 }
2563
2564 return 0;
2565}
2566
Linux kernel - Deliverables
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