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drm/radeon/kms: add atom helper functions for dpm (v3)
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_asic.c
CommitLineData
0a10c851
DV		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/console.h>
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
33#include <linux/vgaarb.h>
34#include <linux/vga_switcheroo.h>
35#include "radeon_reg.h"
36#include "radeon.h"
37#include "radeon_asic.h"
38#include "atom.h"
39
40/*
41 * Registers accessors functions.
42 */
abf1dc67
AD		 43/**
44 * radeon_invalid_rreg - dummy reg read function
45 *
46 * @rdev: radeon device pointer
47 * @reg: offset of register
48 *
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
52 */
0a10c851
DV		 53static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54{
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
56 BUG_ON(1);
57 return 0;
58}
59
abf1dc67
AD		 60/**
61 * radeon_invalid_wreg - dummy reg write function
62 *
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
66 *
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
69 */
0a10c851
DV		 70static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
71{
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
73 reg, v);
74 BUG_ON(1);
75}
76
abf1dc67
AD		 77/**
78 * radeon_register_accessor_init - sets up the register accessor callbacks
79 *
80 * @rdev: radeon device pointer
81 *
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
84 */
0a10c851
DV		 85static void radeon_register_accessor_init(struct radeon_device *rdev)
86{
87 rdev->mc_rreg = &radeon_invalid_rreg;
88 rdev->mc_wreg = &radeon_invalid_wreg;
89 rdev->pll_rreg = &radeon_invalid_rreg;
90 rdev->pll_wreg = &radeon_invalid_wreg;
91 rdev->pciep_rreg = &radeon_invalid_rreg;
92 rdev->pciep_wreg = &radeon_invalid_wreg;
93
94 /* Don't change order as we are overridding accessor. */
95 if (rdev->family < CHIP_RV515) {
96 rdev->pcie_reg_mask = 0xff;
97 } else {
98 rdev->pcie_reg_mask = 0x7ff;
99 }
100 /* FIXME: not sure here */
101 if (rdev->family <= CHIP_R580) {
102 rdev->pll_rreg = &r100_pll_rreg;
103 rdev->pll_wreg = &r100_pll_wreg;
104 }
105 if (rdev->family >= CHIP_R420) {
106 rdev->mc_rreg = &r420_mc_rreg;
107 rdev->mc_wreg = &r420_mc_wreg;
108 }
109 if (rdev->family >= CHIP_RV515) {
110 rdev->mc_rreg = &rv515_mc_rreg;
111 rdev->mc_wreg = &rv515_mc_wreg;
112 }
113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
114 rdev->mc_rreg = &rs400_mc_rreg;
115 rdev->mc_wreg = &rs400_mc_wreg;
116 }
117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
118 rdev->mc_rreg = &rs690_mc_rreg;
119 rdev->mc_wreg = &rs690_mc_wreg;
120 }
121 if (rdev->family == CHIP_RS600) {
122 rdev->mc_rreg = &rs600_mc_rreg;
123 rdev->mc_wreg = &rs600_mc_wreg;
124 }
65337e60
SL		 125 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
126 rdev->mc_rreg = &rs780_mc_rreg;
127 rdev->mc_wreg = &rs780_mc_wreg;
128 }
6e2c3c0a
AD		 129
130 if (rdev->family >= CHIP_BONAIRE) {
131 rdev->pciep_rreg = &cik_pciep_rreg;
132 rdev->pciep_wreg = &cik_pciep_wreg;
133 } else if (rdev->family >= CHIP_R600) {
0a10c851
DV		 134 rdev->pciep_rreg = &r600_pciep_rreg;
135 rdev->pciep_wreg = &r600_pciep_wreg;
136 }
137}
138
139
140/* helper to disable agp */
abf1dc67
AD		 141/**
142 * radeon_agp_disable - AGP disable helper function
143 *
144 * @rdev: radeon device pointer
145 *
146 * Removes AGP flags and changes the gart callbacks on AGP
147 * cards when using the internal gart rather than AGP (all asics).
148 */
0a10c851
DV		 149void radeon_agp_disable(struct radeon_device *rdev)
150{
151 rdev->flags &= ~RADEON_IS_AGP;
152 if (rdev->family >= CHIP_R600) {
153 DRM_INFO("Forcing AGP to PCIE mode\n");
154 rdev->flags |= RADEON_IS_PCIE;
155 } else if (rdev->family >= CHIP_RV515 ||
156 rdev->family == CHIP_RV380 ||
157 rdev->family == CHIP_RV410 ||
158 rdev->family == CHIP_R423) {
159 DRM_INFO("Forcing AGP to PCIE mode\n");
160 rdev->flags |= RADEON_IS_PCIE;
c5b3b850
AD		 161 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
162 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
0a10c851
DV		 163 } else {
164 DRM_INFO("Forcing AGP to PCI mode\n");
165 rdev->flags |= RADEON_IS_PCI;
c5b3b850
AD		 166 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
167 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
0a10c851
DV		 168 }
169 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
170}
171
172/*
173 * ASIC
174 */
48e7a5f1
DV		 175static struct radeon_asic r100_asic = {
176 .init = &r100_init,
177 .fini = &r100_fini,
178 .suspend = &r100_suspend,
179 .resume = &r100_resume,
180 .vga_set_state = &r100_vga_set_state,
a2d07b74 181 .asic_reset = &r100_asic_reset,
54e88e06
AD		 182 .ioctl_wait_idle = NULL,
183 .gui_idle = &r100_gui_idle,
184 .mc_wait_for_idle = &r100_mc_wait_for_idle,
c5b3b850
AD		 185 .gart = {
186 .tlb_flush = &r100_pci_gart_tlb_flush,
187 .set_page = &r100_pci_gart_set_page,
188 },
4c87bc26
CK		 189 .ring = {
190 [RADEON_RING_TYPE_GFX_INDEX] = {
191 .ib_execute = &r100_ring_ib_execute,
192 .emit_fence = &r100_fence_ring_emit,
193 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 194 .cs_parse = &r100_cs_parse,
f712812e
AD		 195 .ring_start = &r100_ring_start,
196 .ring_test = &r100_ring_test,
197 .ib_test = &r100_ib_test,
312c4a8c 198 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 199 .get_rptr = &radeon_ring_generic_get_rptr,
200 .get_wptr = &radeon_ring_generic_get_wptr,
201 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 202 }
203 },
b35ea4ab
AD		 204 .irq = {
205 .set = &r100_irq_set,
206 .process = &r100_irq_process,
207 },
c79a49ca
AD		 208 .display = {
209 .bandwidth_update = &r100_bandwidth_update,
210 .get_vblank_counter = &r100_get_vblank_counter,
211 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 212 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 213 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 214 },
27cd7769
AD		 215 .copy = {
216 .blit = &r100_copy_blit,
217 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
218 .dma = NULL,
219 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
220 .copy = &r100_copy_blit,
221 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
222 },
9e6f3d02
AD		 223 .surface = {
224 .set_reg = r100_set_surface_reg,
225 .clear_reg = r100_clear_surface_reg,
226 },
901ea57d
AD		 227 .hpd = {
228 .init = &r100_hpd_init,
229 .fini = &r100_hpd_fini,
230 .sense = &r100_hpd_sense,
231 .set_polarity = &r100_hpd_set_polarity,
232 },
a02fa397
AD		 233 .pm = {
234 .misc = &r100_pm_misc,
235 .prepare = &r100_pm_prepare,
236 .finish = &r100_pm_finish,
237 .init_profile = &r100_pm_init_profile,
238 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 239 .get_engine_clock = &radeon_legacy_get_engine_clock,
240 .set_engine_clock = &radeon_legacy_set_engine_clock,
241 .get_memory_clock = &radeon_legacy_get_memory_clock,
242 .set_memory_clock = NULL,
243 .get_pcie_lanes = NULL,
244 .set_pcie_lanes = NULL,
245 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 246 },
0f9e006c
AD		 247 .pflip = {
248 .pre_page_flip = &r100_pre_page_flip,
249 .page_flip = &r100_page_flip,
250 .post_page_flip = &r100_post_page_flip,
251 },
48e7a5f1
DV		 252};
253
254static struct radeon_asic r200_asic = {
255 .init = &r100_init,
256 .fini = &r100_fini,
257 .suspend = &r100_suspend,
258 .resume = &r100_resume,
259 .vga_set_state = &r100_vga_set_state,
a2d07b74 260 .asic_reset = &r100_asic_reset,
54e88e06
AD		 261 .ioctl_wait_idle = NULL,
262 .gui_idle = &r100_gui_idle,
263 .mc_wait_for_idle = &r100_mc_wait_for_idle,
c5b3b850
AD		 264 .gart = {
265 .tlb_flush = &r100_pci_gart_tlb_flush,
266 .set_page = &r100_pci_gart_set_page,
267 },
4c87bc26
CK		 268 .ring = {
269 [RADEON_RING_TYPE_GFX_INDEX] = {
270 .ib_execute = &r100_ring_ib_execute,
271 .emit_fence = &r100_fence_ring_emit,
272 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 273 .cs_parse = &r100_cs_parse,
f712812e
AD		 274 .ring_start = &r100_ring_start,
275 .ring_test = &r100_ring_test,
276 .ib_test = &r100_ib_test,
312c4a8c 277 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 278 .get_rptr = &radeon_ring_generic_get_rptr,
279 .get_wptr = &radeon_ring_generic_get_wptr,
280 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 281 }
282 },
b35ea4ab
AD		 283 .irq = {
284 .set = &r100_irq_set,
285 .process = &r100_irq_process,
286 },
c79a49ca
AD		 287 .display = {
288 .bandwidth_update = &r100_bandwidth_update,
289 .get_vblank_counter = &r100_get_vblank_counter,
290 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 291 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 292 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 293 },
27cd7769
AD		 294 .copy = {
295 .blit = &r100_copy_blit,
296 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
297 .dma = &r200_copy_dma,
298 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
299 .copy = &r100_copy_blit,
300 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
301 },
9e6f3d02
AD		 302 .surface = {
303 .set_reg = r100_set_surface_reg,
304 .clear_reg = r100_clear_surface_reg,
305 },
901ea57d
AD		 306 .hpd = {
307 .init = &r100_hpd_init,
308 .fini = &r100_hpd_fini,
309 .sense = &r100_hpd_sense,
310 .set_polarity = &r100_hpd_set_polarity,
311 },
a02fa397
AD		 312 .pm = {
313 .misc = &r100_pm_misc,
314 .prepare = &r100_pm_prepare,
315 .finish = &r100_pm_finish,
316 .init_profile = &r100_pm_init_profile,
317 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 318 .get_engine_clock = &radeon_legacy_get_engine_clock,
319 .set_engine_clock = &radeon_legacy_set_engine_clock,
320 .get_memory_clock = &radeon_legacy_get_memory_clock,
321 .set_memory_clock = NULL,
322 .get_pcie_lanes = NULL,
323 .set_pcie_lanes = NULL,
324 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 325 },
0f9e006c
AD		 326 .pflip = {
327 .pre_page_flip = &r100_pre_page_flip,
328 .page_flip = &r100_page_flip,
329 .post_page_flip = &r100_post_page_flip,
330 },
48e7a5f1
DV		 331};
332
333static struct radeon_asic r300_asic = {
334 .init = &r300_init,
335 .fini = &r300_fini,
336 .suspend = &r300_suspend,
337 .resume = &r300_resume,
338 .vga_set_state = &r100_vga_set_state,
a2d07b74 339 .asic_reset = &r300_asic_reset,
54e88e06
AD		 340 .ioctl_wait_idle = NULL,
341 .gui_idle = &r100_gui_idle,
342 .mc_wait_for_idle = &r300_mc_wait_for_idle,
c5b3b850
AD		 343 .gart = {
344 .tlb_flush = &r100_pci_gart_tlb_flush,
345 .set_page = &r100_pci_gart_set_page,
346 },
4c87bc26
CK		 347 .ring = {
348 [RADEON_RING_TYPE_GFX_INDEX] = {
349 .ib_execute = &r100_ring_ib_execute,
350 .emit_fence = &r300_fence_ring_emit,
351 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 352 .cs_parse = &r300_cs_parse,
f712812e
AD		 353 .ring_start = &r300_ring_start,
354 .ring_test = &r100_ring_test,
355 .ib_test = &r100_ib_test,
8ba957b5 356 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 357 .get_rptr = &radeon_ring_generic_get_rptr,
358 .get_wptr = &radeon_ring_generic_get_wptr,
359 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 360 }
361 },
b35ea4ab
AD		 362 .irq = {
363 .set = &r100_irq_set,
364 .process = &r100_irq_process,
365 },
c79a49ca
AD		 366 .display = {
367 .bandwidth_update = &r100_bandwidth_update,
368 .get_vblank_counter = &r100_get_vblank_counter,
369 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 370 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 371 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 372 },
27cd7769
AD		 373 .copy = {
374 .blit = &r100_copy_blit,
375 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
376 .dma = &r200_copy_dma,
377 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
378 .copy = &r100_copy_blit,
379 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
380 },
9e6f3d02
AD		 381 .surface = {
382 .set_reg = r100_set_surface_reg,
383 .clear_reg = r100_clear_surface_reg,
384 },
901ea57d
AD		 385 .hpd = {
386 .init = &r100_hpd_init,
387 .fini = &r100_hpd_fini,
388 .sense = &r100_hpd_sense,
389 .set_polarity = &r100_hpd_set_polarity,
390 },
a02fa397
AD		 391 .pm = {
392 .misc = &r100_pm_misc,
393 .prepare = &r100_pm_prepare,
394 .finish = &r100_pm_finish,
395 .init_profile = &r100_pm_init_profile,
396 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 397 .get_engine_clock = &radeon_legacy_get_engine_clock,
398 .set_engine_clock = &radeon_legacy_set_engine_clock,
399 .get_memory_clock = &radeon_legacy_get_memory_clock,
400 .set_memory_clock = NULL,
401 .get_pcie_lanes = &rv370_get_pcie_lanes,
402 .set_pcie_lanes = &rv370_set_pcie_lanes,
403 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 404 },
0f9e006c
AD		 405 .pflip = {
406 .pre_page_flip = &r100_pre_page_flip,
407 .page_flip = &r100_page_flip,
408 .post_page_flip = &r100_post_page_flip,
409 },
48e7a5f1
DV		 410};
411
412static struct radeon_asic r300_asic_pcie = {
413 .init = &r300_init,
414 .fini = &r300_fini,
415 .suspend = &r300_suspend,
416 .resume = &r300_resume,
417 .vga_set_state = &r100_vga_set_state,
a2d07b74 418 .asic_reset = &r300_asic_reset,
54e88e06
AD		 419 .ioctl_wait_idle = NULL,
420 .gui_idle = &r100_gui_idle,
421 .mc_wait_for_idle = &r300_mc_wait_for_idle,
c5b3b850
AD		 422 .gart = {
423 .tlb_flush = &rv370_pcie_gart_tlb_flush,
424 .set_page = &rv370_pcie_gart_set_page,
425 },
4c87bc26
CK		 426 .ring = {
427 [RADEON_RING_TYPE_GFX_INDEX] = {
428 .ib_execute = &r100_ring_ib_execute,
429 .emit_fence = &r300_fence_ring_emit,
430 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 431 .cs_parse = &r300_cs_parse,
f712812e
AD		 432 .ring_start = &r300_ring_start,
433 .ring_test = &r100_ring_test,
434 .ib_test = &r100_ib_test,
8ba957b5 435 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 436 .get_rptr = &radeon_ring_generic_get_rptr,
437 .get_wptr = &radeon_ring_generic_get_wptr,
438 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 439 }
440 },
b35ea4ab
AD		 441 .irq = {
442 .set = &r100_irq_set,
443 .process = &r100_irq_process,
444 },
c79a49ca
AD		 445 .display = {
446 .bandwidth_update = &r100_bandwidth_update,
447 .get_vblank_counter = &r100_get_vblank_counter,
448 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 449 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 450 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 451 },
27cd7769
AD		 452 .copy = {
453 .blit = &r100_copy_blit,
454 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
455 .dma = &r200_copy_dma,
456 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
457 .copy = &r100_copy_blit,
458 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
459 },
9e6f3d02
AD		 460 .surface = {
461 .set_reg = r100_set_surface_reg,
462 .clear_reg = r100_clear_surface_reg,
463 },
901ea57d
AD		 464 .hpd = {
465 .init = &r100_hpd_init,
466 .fini = &r100_hpd_fini,
467 .sense = &r100_hpd_sense,
468 .set_polarity = &r100_hpd_set_polarity,
469 },
a02fa397
AD		 470 .pm = {
471 .misc = &r100_pm_misc,
472 .prepare = &r100_pm_prepare,
473 .finish = &r100_pm_finish,
474 .init_profile = &r100_pm_init_profile,
475 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 476 .get_engine_clock = &radeon_legacy_get_engine_clock,
477 .set_engine_clock = &radeon_legacy_set_engine_clock,
478 .get_memory_clock = &radeon_legacy_get_memory_clock,
479 .set_memory_clock = NULL,
480 .get_pcie_lanes = &rv370_get_pcie_lanes,
481 .set_pcie_lanes = &rv370_set_pcie_lanes,
482 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 483 },
0f9e006c
AD		 484 .pflip = {
485 .pre_page_flip = &r100_pre_page_flip,
486 .page_flip = &r100_page_flip,
487 .post_page_flip = &r100_post_page_flip,
488 },
48e7a5f1
DV		 489};
490
491static struct radeon_asic r420_asic = {
492 .init = &r420_init,
493 .fini = &r420_fini,
494 .suspend = &r420_suspend,
495 .resume = &r420_resume,
496 .vga_set_state = &r100_vga_set_state,
a2d07b74 497 .asic_reset = &r300_asic_reset,
54e88e06
AD		 498 .ioctl_wait_idle = NULL,
499 .gui_idle = &r100_gui_idle,
500 .mc_wait_for_idle = &r300_mc_wait_for_idle,
c5b3b850
AD		 501 .gart = {
502 .tlb_flush = &rv370_pcie_gart_tlb_flush,
503 .set_page = &rv370_pcie_gart_set_page,
504 },
4c87bc26
CK		 505 .ring = {
506 [RADEON_RING_TYPE_GFX_INDEX] = {
507 .ib_execute = &r100_ring_ib_execute,
508 .emit_fence = &r300_fence_ring_emit,
509 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 510 .cs_parse = &r300_cs_parse,
f712812e
AD		 511 .ring_start = &r300_ring_start,
512 .ring_test = &r100_ring_test,
513 .ib_test = &r100_ib_test,
8ba957b5 514 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 515 .get_rptr = &radeon_ring_generic_get_rptr,
516 .get_wptr = &radeon_ring_generic_get_wptr,
517 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 518 }
519 },
b35ea4ab
AD		 520 .irq = {
521 .set = &r100_irq_set,
522 .process = &r100_irq_process,
523 },
c79a49ca
AD		 524 .display = {
525 .bandwidth_update = &r100_bandwidth_update,
526 .get_vblank_counter = &r100_get_vblank_counter,
527 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 528 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 529 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 530 },
27cd7769
AD		 531 .copy = {
532 .blit = &r100_copy_blit,
533 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
534 .dma = &r200_copy_dma,
535 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
536 .copy = &r100_copy_blit,
537 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
538 },
9e6f3d02
AD		 539 .surface = {
540 .set_reg = r100_set_surface_reg,
541 .clear_reg = r100_clear_surface_reg,
542 },
901ea57d
AD		 543 .hpd = {
544 .init = &r100_hpd_init,
545 .fini = &r100_hpd_fini,
546 .sense = &r100_hpd_sense,
547 .set_polarity = &r100_hpd_set_polarity,
548 },
a02fa397
AD		 549 .pm = {
550 .misc = &r100_pm_misc,
551 .prepare = &r100_pm_prepare,
552 .finish = &r100_pm_finish,
553 .init_profile = &r420_pm_init_profile,
554 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 555 .get_engine_clock = &radeon_atom_get_engine_clock,
556 .set_engine_clock = &radeon_atom_set_engine_clock,
557 .get_memory_clock = &radeon_atom_get_memory_clock,
558 .set_memory_clock = &radeon_atom_set_memory_clock,
559 .get_pcie_lanes = &rv370_get_pcie_lanes,
560 .set_pcie_lanes = &rv370_set_pcie_lanes,
561 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 562 },
0f9e006c
AD		 563 .pflip = {
564 .pre_page_flip = &r100_pre_page_flip,
565 .page_flip = &r100_page_flip,
566 .post_page_flip = &r100_post_page_flip,
567 },
48e7a5f1
DV		 568};
569
570static struct radeon_asic rs400_asic = {
571 .init = &rs400_init,
572 .fini = &rs400_fini,
573 .suspend = &rs400_suspend,
574 .resume = &rs400_resume,
575 .vga_set_state = &r100_vga_set_state,
a2d07b74 576 .asic_reset = &r300_asic_reset,
54e88e06
AD		 577 .ioctl_wait_idle = NULL,
578 .gui_idle = &r100_gui_idle,
579 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
c5b3b850
AD		 580 .gart = {
581 .tlb_flush = &rs400_gart_tlb_flush,
582 .set_page = &rs400_gart_set_page,
583 },
4c87bc26
CK		 584 .ring = {
585 [RADEON_RING_TYPE_GFX_INDEX] = {
586 .ib_execute = &r100_ring_ib_execute,
587 .emit_fence = &r300_fence_ring_emit,
588 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 589 .cs_parse = &r300_cs_parse,
f712812e
AD		 590 .ring_start = &r300_ring_start,
591 .ring_test = &r100_ring_test,
592 .ib_test = &r100_ib_test,
8ba957b5 593 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 594 .get_rptr = &radeon_ring_generic_get_rptr,
595 .get_wptr = &radeon_ring_generic_get_wptr,
596 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 597 }
598 },
b35ea4ab
AD		 599 .irq = {
600 .set = &r100_irq_set,
601 .process = &r100_irq_process,
602 },
c79a49ca
AD		 603 .display = {
604 .bandwidth_update = &r100_bandwidth_update,
605 .get_vblank_counter = &r100_get_vblank_counter,
606 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 607 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 608 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 609 },
27cd7769
AD		 610 .copy = {
611 .blit = &r100_copy_blit,
612 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
613 .dma = &r200_copy_dma,
614 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
615 .copy = &r100_copy_blit,
616 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
617 },
9e6f3d02
AD		 618 .surface = {
619 .set_reg = r100_set_surface_reg,
620 .clear_reg = r100_clear_surface_reg,
621 },
901ea57d
AD		 622 .hpd = {
623 .init = &r100_hpd_init,
624 .fini = &r100_hpd_fini,
625 .sense = &r100_hpd_sense,
626 .set_polarity = &r100_hpd_set_polarity,
627 },
a02fa397
AD		 628 .pm = {
629 .misc = &r100_pm_misc,
630 .prepare = &r100_pm_prepare,
631 .finish = &r100_pm_finish,
632 .init_profile = &r100_pm_init_profile,
633 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 634 .get_engine_clock = &radeon_legacy_get_engine_clock,
635 .set_engine_clock = &radeon_legacy_set_engine_clock,
636 .get_memory_clock = &radeon_legacy_get_memory_clock,
637 .set_memory_clock = NULL,
638 .get_pcie_lanes = NULL,
639 .set_pcie_lanes = NULL,
640 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 641 },
0f9e006c
AD		 642 .pflip = {
643 .pre_page_flip = &r100_pre_page_flip,
644 .page_flip = &r100_page_flip,
645 .post_page_flip = &r100_post_page_flip,
646 },
48e7a5f1
DV		 647};
648
649static struct radeon_asic rs600_asic = {
650 .init = &rs600_init,
651 .fini = &rs600_fini,
652 .suspend = &rs600_suspend,
653 .resume = &rs600_resume,
654 .vga_set_state = &r100_vga_set_state,
90aca4d2 655 .asic_reset = &rs600_asic_reset,
54e88e06
AD		 656 .ioctl_wait_idle = NULL,
657 .gui_idle = &r100_gui_idle,
658 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
c5b3b850
AD		 659 .gart = {
660 .tlb_flush = &rs600_gart_tlb_flush,
661 .set_page = &rs600_gart_set_page,
662 },
4c87bc26
CK		 663 .ring = {
664 [RADEON_RING_TYPE_GFX_INDEX] = {
665 .ib_execute = &r100_ring_ib_execute,
666 .emit_fence = &r300_fence_ring_emit,
667 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 668 .cs_parse = &r300_cs_parse,
f712812e
AD		 669 .ring_start = &r300_ring_start,
670 .ring_test = &r100_ring_test,
671 .ib_test = &r100_ib_test,
8ba957b5 672 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 673 .get_rptr = &radeon_ring_generic_get_rptr,
674 .get_wptr = &radeon_ring_generic_get_wptr,
675 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 676 }
677 },
b35ea4ab
AD		 678 .irq = {
679 .set = &rs600_irq_set,
680 .process = &rs600_irq_process,
681 },
c79a49ca
AD		 682 .display = {
683 .bandwidth_update = &rs600_bandwidth_update,
684 .get_vblank_counter = &rs600_get_vblank_counter,
685 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 686 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 687 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 688 .hdmi_enable = &r600_hdmi_enable,
689 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 690 },
27cd7769
AD		 691 .copy = {
692 .blit = &r100_copy_blit,
693 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
694 .dma = &r200_copy_dma,
695 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
696 .copy = &r100_copy_blit,
697 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
698 },
9e6f3d02
AD		 699 .surface = {
700 .set_reg = r100_set_surface_reg,
701 .clear_reg = r100_clear_surface_reg,
702 },
901ea57d
AD		 703 .hpd = {
704 .init = &rs600_hpd_init,
705 .fini = &rs600_hpd_fini,
706 .sense = &rs600_hpd_sense,
707 .set_polarity = &rs600_hpd_set_polarity,
708 },
a02fa397
AD		 709 .pm = {
710 .misc = &rs600_pm_misc,
711 .prepare = &rs600_pm_prepare,
712 .finish = &rs600_pm_finish,
713 .init_profile = &r420_pm_init_profile,
714 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 715 .get_engine_clock = &radeon_atom_get_engine_clock,
716 .set_engine_clock = &radeon_atom_set_engine_clock,
717 .get_memory_clock = &radeon_atom_get_memory_clock,
718 .set_memory_clock = &radeon_atom_set_memory_clock,
719 .get_pcie_lanes = NULL,
720 .set_pcie_lanes = NULL,
721 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 722 },
0f9e006c
AD		 723 .pflip = {
724 .pre_page_flip = &rs600_pre_page_flip,
725 .page_flip = &rs600_page_flip,
726 .post_page_flip = &rs600_post_page_flip,
727 },
48e7a5f1
DV		 728};
729
730static struct radeon_asic rs690_asic = {
731 .init = &rs690_init,
732 .fini = &rs690_fini,
733 .suspend = &rs690_suspend,
734 .resume = &rs690_resume,
735 .vga_set_state = &r100_vga_set_state,
90aca4d2 736 .asic_reset = &rs600_asic_reset,
54e88e06
AD		 737 .ioctl_wait_idle = NULL,
738 .gui_idle = &r100_gui_idle,
739 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
c5b3b850
AD		 740 .gart = {
741 .tlb_flush = &rs400_gart_tlb_flush,
742 .set_page = &rs400_gart_set_page,
743 },
4c87bc26
CK		 744 .ring = {
745 [RADEON_RING_TYPE_GFX_INDEX] = {
746 .ib_execute = &r100_ring_ib_execute,
747 .emit_fence = &r300_fence_ring_emit,
748 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 749 .cs_parse = &r300_cs_parse,
f712812e
AD		 750 .ring_start = &r300_ring_start,
751 .ring_test = &r100_ring_test,
752 .ib_test = &r100_ib_test,
8ba957b5 753 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 754 .get_rptr = &radeon_ring_generic_get_rptr,
755 .get_wptr = &radeon_ring_generic_get_wptr,
756 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 757 }
758 },
b35ea4ab
AD		 759 .irq = {
760 .set = &rs600_irq_set,
761 .process = &rs600_irq_process,
762 },
c79a49ca
AD		 763 .display = {
764 .get_vblank_counter = &rs600_get_vblank_counter,
765 .bandwidth_update = &rs690_bandwidth_update,
766 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 767 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 768 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 769 .hdmi_enable = &r600_hdmi_enable,
770 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 771 },
27cd7769
AD		 772 .copy = {
773 .blit = &r100_copy_blit,
774 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
775 .dma = &r200_copy_dma,
776 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
777 .copy = &r200_copy_dma,
778 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
779 },
9e6f3d02
AD		 780 .surface = {
781 .set_reg = r100_set_surface_reg,
782 .clear_reg = r100_clear_surface_reg,
783 },
901ea57d
AD		 784 .hpd = {
785 .init = &rs600_hpd_init,
786 .fini = &rs600_hpd_fini,
787 .sense = &rs600_hpd_sense,
788 .set_polarity = &rs600_hpd_set_polarity,
789 },
a02fa397
AD		 790 .pm = {
791 .misc = &rs600_pm_misc,
792 .prepare = &rs600_pm_prepare,
793 .finish = &rs600_pm_finish,
794 .init_profile = &r420_pm_init_profile,
795 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 796 .get_engine_clock = &radeon_atom_get_engine_clock,
797 .set_engine_clock = &radeon_atom_set_engine_clock,
798 .get_memory_clock = &radeon_atom_get_memory_clock,
799 .set_memory_clock = &radeon_atom_set_memory_clock,
800 .get_pcie_lanes = NULL,
801 .set_pcie_lanes = NULL,
802 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 803 },
0f9e006c
AD		 804 .pflip = {
805 .pre_page_flip = &rs600_pre_page_flip,
806 .page_flip = &rs600_page_flip,
807 .post_page_flip = &rs600_post_page_flip,
808 },
48e7a5f1
DV		 809};
810
811static struct radeon_asic rv515_asic = {
812 .init = &rv515_init,
813 .fini = &rv515_fini,
814 .suspend = &rv515_suspend,
815 .resume = &rv515_resume,
816 .vga_set_state = &r100_vga_set_state,
90aca4d2 817 .asic_reset = &rs600_asic_reset,
54e88e06
AD		 818 .ioctl_wait_idle = NULL,
819 .gui_idle = &r100_gui_idle,
820 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
c5b3b850
AD		 821 .gart = {
822 .tlb_flush = &rv370_pcie_gart_tlb_flush,
823 .set_page = &rv370_pcie_gart_set_page,
824 },
4c87bc26
CK		 825 .ring = {
826 [RADEON_RING_TYPE_GFX_INDEX] = {
827 .ib_execute = &r100_ring_ib_execute,
828 .emit_fence = &r300_fence_ring_emit,
829 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 830 .cs_parse = &r300_cs_parse,
f712812e
AD		 831 .ring_start = &rv515_ring_start,
832 .ring_test = &r100_ring_test,
833 .ib_test = &r100_ib_test,
8ba957b5 834 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 835 .get_rptr = &radeon_ring_generic_get_rptr,
836 .get_wptr = &radeon_ring_generic_get_wptr,
837 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 838 }
839 },
b35ea4ab
AD		 840 .irq = {
841 .set = &rs600_irq_set,
842 .process = &rs600_irq_process,
843 },
c79a49ca
AD		 844 .display = {
845 .get_vblank_counter = &rs600_get_vblank_counter,
846 .bandwidth_update = &rv515_bandwidth_update,
847 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 848 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 849 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 850 },
27cd7769
AD		 851 .copy = {
852 .blit = &r100_copy_blit,
853 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
854 .dma = &r200_copy_dma,
855 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
856 .copy = &r100_copy_blit,
857 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
858 },
9e6f3d02
AD		 859 .surface = {
860 .set_reg = r100_set_surface_reg,
861 .clear_reg = r100_clear_surface_reg,
862 },
901ea57d
AD		 863 .hpd = {
864 .init = &rs600_hpd_init,
865 .fini = &rs600_hpd_fini,
866 .sense = &rs600_hpd_sense,
867 .set_polarity = &rs600_hpd_set_polarity,
868 },
a02fa397
AD		 869 .pm = {
870 .misc = &rs600_pm_misc,
871 .prepare = &rs600_pm_prepare,
872 .finish = &rs600_pm_finish,
873 .init_profile = &r420_pm_init_profile,
874 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 875 .get_engine_clock = &radeon_atom_get_engine_clock,
876 .set_engine_clock = &radeon_atom_set_engine_clock,
877 .get_memory_clock = &radeon_atom_get_memory_clock,
878 .set_memory_clock = &radeon_atom_set_memory_clock,
879 .get_pcie_lanes = &rv370_get_pcie_lanes,
880 .set_pcie_lanes = &rv370_set_pcie_lanes,
881 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 882 },
0f9e006c
AD		 883 .pflip = {
884 .pre_page_flip = &rs600_pre_page_flip,
885 .page_flip = &rs600_page_flip,
886 .post_page_flip = &rs600_post_page_flip,
887 },
48e7a5f1
DV		 888};
889
890static struct radeon_asic r520_asic = {
891 .init = &r520_init,
892 .fini = &rv515_fini,
893 .suspend = &rv515_suspend,
894 .resume = &r520_resume,
895 .vga_set_state = &r100_vga_set_state,
90aca4d2 896 .asic_reset = &rs600_asic_reset,
54e88e06
AD		 897 .ioctl_wait_idle = NULL,
898 .gui_idle = &r100_gui_idle,
899 .mc_wait_for_idle = &r520_mc_wait_for_idle,
c5b3b850
AD		 900 .gart = {
901 .tlb_flush = &rv370_pcie_gart_tlb_flush,
902 .set_page = &rv370_pcie_gart_set_page,
903 },
4c87bc26
CK		 904 .ring = {
905 [RADEON_RING_TYPE_GFX_INDEX] = {
906 .ib_execute = &r100_ring_ib_execute,
907 .emit_fence = &r300_fence_ring_emit,
908 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 909 .cs_parse = &r300_cs_parse,
f712812e
AD		 910 .ring_start = &rv515_ring_start,
911 .ring_test = &r100_ring_test,
912 .ib_test = &r100_ib_test,
8ba957b5 913 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 914 .get_rptr = &radeon_ring_generic_get_rptr,
915 .get_wptr = &radeon_ring_generic_get_wptr,
916 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 917 }
918 },
b35ea4ab
AD		 919 .irq = {
920 .set = &rs600_irq_set,
921 .process = &rs600_irq_process,
922 },
c79a49ca
AD		 923 .display = {
924 .bandwidth_update = &rv515_bandwidth_update,
925 .get_vblank_counter = &rs600_get_vblank_counter,
926 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 927 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 928 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 929 },
27cd7769
AD		 930 .copy = {
931 .blit = &r100_copy_blit,
932 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
933 .dma = &r200_copy_dma,
934 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
935 .copy = &r100_copy_blit,
936 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
937 },
9e6f3d02
AD		 938 .surface = {
939 .set_reg = r100_set_surface_reg,
940 .clear_reg = r100_clear_surface_reg,
941 },
901ea57d
AD		 942 .hpd = {
943 .init = &rs600_hpd_init,
944 .fini = &rs600_hpd_fini,
945 .sense = &rs600_hpd_sense,
946 .set_polarity = &rs600_hpd_set_polarity,
947 },
a02fa397
AD		 948 .pm = {
949 .misc = &rs600_pm_misc,
950 .prepare = &rs600_pm_prepare,
951 .finish = &rs600_pm_finish,
952 .init_profile = &r420_pm_init_profile,
953 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 954 .get_engine_clock = &radeon_atom_get_engine_clock,
955 .set_engine_clock = &radeon_atom_set_engine_clock,
956 .get_memory_clock = &radeon_atom_get_memory_clock,
957 .set_memory_clock = &radeon_atom_set_memory_clock,
958 .get_pcie_lanes = &rv370_get_pcie_lanes,
959 .set_pcie_lanes = &rv370_set_pcie_lanes,
960 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 961 },
0f9e006c
AD		 962 .pflip = {
963 .pre_page_flip = &rs600_pre_page_flip,
964 .page_flip = &rs600_page_flip,
965 .post_page_flip = &rs600_post_page_flip,
966 },
48e7a5f1
DV		 967};
968
969static struct radeon_asic r600_asic = {
970 .init = &r600_init,
971 .fini = &r600_fini,
972 .suspend = &r600_suspend,
973 .resume = &r600_resume,
48e7a5f1 974 .vga_set_state = &r600_vga_set_state,
a2d07b74 975 .asic_reset = &r600_asic_reset,
54e88e06
AD		 976 .ioctl_wait_idle = r600_ioctl_wait_idle,
977 .gui_idle = &r600_gui_idle,
978 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 979 .get_xclk = &r600_get_xclk,
d0418894 980 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 981 .gart = {
982 .tlb_flush = &r600_pcie_gart_tlb_flush,
983 .set_page = &rs600_gart_set_page,
984 },
4c87bc26
CK		 985 .ring = {
986 [RADEON_RING_TYPE_GFX_INDEX] = {
987 .ib_execute = &r600_ring_ib_execute,
988 .emit_fence = &r600_fence_ring_emit,
989 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 990 .cs_parse = &r600_cs_parse,
f712812e
AD		 991 .ring_test = &r600_ring_test,
992 .ib_test = &r600_ib_test,
123bc183 993 .is_lockup = &r600_gfx_is_lockup,
f93bdefe
AD		 994 .get_rptr = &radeon_ring_generic_get_rptr,
995 .get_wptr = &radeon_ring_generic_get_wptr,
996 .set_wptr = &radeon_ring_generic_set_wptr,
4d75658b
AD		 997 },
998 [R600_RING_TYPE_DMA_INDEX] = {
999 .ib_execute = &r600_dma_ring_ib_execute,
1000 .emit_fence = &r600_dma_fence_ring_emit,
1001 .emit_semaphore = &r600_dma_semaphore_ring_emit,
cf4ccd01 1002 .cs_parse = &r600_dma_cs_parse,
4d75658b
AD		 1003 .ring_test = &r600_dma_ring_test,
1004 .ib_test = &r600_dma_ib_test,
1005 .is_lockup = &r600_dma_is_lockup,
f93bdefe
AD		 1006 .get_rptr = &radeon_ring_generic_get_rptr,
1007 .get_wptr = &radeon_ring_generic_get_wptr,
1008 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 1009 }
1010 },
b35ea4ab
AD		 1011 .irq = {
1012 .set = &r600_irq_set,
1013 .process = &r600_irq_process,
1014 },
c79a49ca
AD		 1015 .display = {
1016 .bandwidth_update = &rv515_bandwidth_update,
1017 .get_vblank_counter = &rs600_get_vblank_counter,
1018 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 1019 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1020 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1021 .hdmi_enable = &r600_hdmi_enable,
1022 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 1023 },
27cd7769
AD		 1024 .copy = {
1025 .blit = &r600_copy_blit,
1026 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
4d75658b
AD		 1027 .dma = &r600_copy_dma,
1028 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1029 .copy = &r600_copy_dma,
1030 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1031 },
9e6f3d02
AD		 1032 .surface = {
1033 .set_reg = r600_set_surface_reg,
1034 .clear_reg = r600_clear_surface_reg,
1035 },
901ea57d
AD		 1036 .hpd = {
1037 .init = &r600_hpd_init,
1038 .fini = &r600_hpd_fini,
1039 .sense = &r600_hpd_sense,
1040 .set_polarity = &r600_hpd_set_polarity,
1041 },
a02fa397
AD		 1042 .pm = {
1043 .misc = &r600_pm_misc,
1044 .prepare = &rs600_pm_prepare,
1045 .finish = &rs600_pm_finish,
1046 .init_profile = &r600_pm_init_profile,
1047 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1048 .get_engine_clock = &radeon_atom_get_engine_clock,
1049 .set_engine_clock = &radeon_atom_set_engine_clock,
1050 .get_memory_clock = &radeon_atom_get_memory_clock,
1051 .set_memory_clock = &radeon_atom_set_memory_clock,
1052 .get_pcie_lanes = &r600_get_pcie_lanes,
1053 .set_pcie_lanes = &r600_set_pcie_lanes,
1054 .set_clock_gating = NULL,
6bd1c385 1055 .get_temperature = &rv6xx_get_temp,
a02fa397 1056 },
0f9e006c
AD		 1057 .pflip = {
1058 .pre_page_flip = &rs600_pre_page_flip,
1059 .page_flip = &rs600_page_flip,
1060 .post_page_flip = &rs600_post_page_flip,
1061 },
48e7a5f1
DV		 1062};
1063
f47299c5
AD		 1064static struct radeon_asic rs780_asic = {
1065 .init = &r600_init,
1066 .fini = &r600_fini,
1067 .suspend = &r600_suspend,
1068 .resume = &r600_resume,
f47299c5 1069 .vga_set_state = &r600_vga_set_state,
a2d07b74 1070 .asic_reset = &r600_asic_reset,
54e88e06
AD		 1071 .ioctl_wait_idle = r600_ioctl_wait_idle,
1072 .gui_idle = &r600_gui_idle,
1073 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 1074 .get_xclk = &r600_get_xclk,
d0418894 1075 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1076 .gart = {
1077 .tlb_flush = &r600_pcie_gart_tlb_flush,
1078 .set_page = &rs600_gart_set_page,
1079 },
4c87bc26
CK		 1080 .ring = {
1081 [RADEON_RING_TYPE_GFX_INDEX] = {
1082 .ib_execute = &r600_ring_ib_execute,
1083 .emit_fence = &r600_fence_ring_emit,
1084 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1085 .cs_parse = &r600_cs_parse,
f712812e
AD		 1086 .ring_test = &r600_ring_test,
1087 .ib_test = &r600_ib_test,
123bc183 1088 .is_lockup = &r600_gfx_is_lockup,
f93bdefe
AD		 1089 .get_rptr = &radeon_ring_generic_get_rptr,
1090 .get_wptr = &radeon_ring_generic_get_wptr,
1091 .set_wptr = &radeon_ring_generic_set_wptr,
4d75658b
AD		 1092 },
1093 [R600_RING_TYPE_DMA_INDEX] = {
1094 .ib_execute = &r600_dma_ring_ib_execute,
1095 .emit_fence = &r600_dma_fence_ring_emit,
1096 .emit_semaphore = &r600_dma_semaphore_ring_emit,
cf4ccd01 1097 .cs_parse = &r600_dma_cs_parse,
4d75658b
AD		 1098 .ring_test = &r600_dma_ring_test,
1099 .ib_test = &r600_dma_ib_test,
1100 .is_lockup = &r600_dma_is_lockup,
f93bdefe
AD		 1101 .get_rptr = &radeon_ring_generic_get_rptr,
1102 .get_wptr = &radeon_ring_generic_get_wptr,
1103 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 1104 }
1105 },
b35ea4ab
AD		 1106 .irq = {
1107 .set = &r600_irq_set,
1108 .process = &r600_irq_process,
1109 },
c79a49ca
AD		 1110 .display = {
1111 .bandwidth_update = &rs690_bandwidth_update,
1112 .get_vblank_counter = &rs600_get_vblank_counter,
1113 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 1114 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1115 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1116 .hdmi_enable = &r600_hdmi_enable,
1117 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 1118 },
27cd7769
AD		 1119 .copy = {
1120 .blit = &r600_copy_blit,
1121 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
4d75658b
AD		 1122 .dma = &r600_copy_dma,
1123 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1124 .copy = &r600_copy_dma,
1125 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1126 },
9e6f3d02
AD		 1127 .surface = {
1128 .set_reg = r600_set_surface_reg,
1129 .clear_reg = r600_clear_surface_reg,
1130 },
901ea57d
AD		 1131 .hpd = {
1132 .init = &r600_hpd_init,
1133 .fini = &r600_hpd_fini,
1134 .sense = &r600_hpd_sense,
1135 .set_polarity = &r600_hpd_set_polarity,
1136 },
a02fa397
AD		 1137 .pm = {
1138 .misc = &r600_pm_misc,
1139 .prepare = &rs600_pm_prepare,
1140 .finish = &rs600_pm_finish,
1141 .init_profile = &rs780_pm_init_profile,
1142 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1143 .get_engine_clock = &radeon_atom_get_engine_clock,
1144 .set_engine_clock = &radeon_atom_set_engine_clock,
1145 .get_memory_clock = NULL,
1146 .set_memory_clock = NULL,
1147 .get_pcie_lanes = NULL,
1148 .set_pcie_lanes = NULL,
1149 .set_clock_gating = NULL,
6bd1c385 1150 .get_temperature = &rv6xx_get_temp,
a02fa397 1151 },
0f9e006c
AD		 1152 .pflip = {
1153 .pre_page_flip = &rs600_pre_page_flip,
1154 .page_flip = &rs600_page_flip,
1155 .post_page_flip = &rs600_post_page_flip,
1156 },
f47299c5
AD		 1157};
1158
48e7a5f1
DV		 1159static struct radeon_asic rv770_asic = {
1160 .init = &rv770_init,
1161 .fini = &rv770_fini,
1162 .suspend = &rv770_suspend,
1163 .resume = &rv770_resume,
a2d07b74 1164 .asic_reset = &r600_asic_reset,
48e7a5f1 1165 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1166 .ioctl_wait_idle = r600_ioctl_wait_idle,
1167 .gui_idle = &r600_gui_idle,
1168 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 1169 .get_xclk = &rv770_get_xclk,
d0418894 1170 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1171 .gart = {
1172 .tlb_flush = &r600_pcie_gart_tlb_flush,
1173 .set_page = &rs600_gart_set_page,
1174 },
4c87bc26
CK		 1175 .ring = {
1176 [RADEON_RING_TYPE_GFX_INDEX] = {
1177 .ib_execute = &r600_ring_ib_execute,
1178 .emit_fence = &r600_fence_ring_emit,
1179 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1180 .cs_parse = &r600_cs_parse,
f712812e
AD		 1181 .ring_test = &r600_ring_test,
1182 .ib_test = &r600_ib_test,
123bc183 1183 .is_lockup = &r600_gfx_is_lockup,
f93bdefe
AD		 1184 .get_rptr = &radeon_ring_generic_get_rptr,
1185 .get_wptr = &radeon_ring_generic_get_wptr,
1186 .set_wptr = &radeon_ring_generic_set_wptr,
4d75658b
AD		 1187 },
1188 [R600_RING_TYPE_DMA_INDEX] = {
1189 .ib_execute = &r600_dma_ring_ib_execute,
1190 .emit_fence = &r600_dma_fence_ring_emit,
1191 .emit_semaphore = &r600_dma_semaphore_ring_emit,
cf4ccd01 1192 .cs_parse = &r600_dma_cs_parse,
4d75658b
AD		 1193 .ring_test = &r600_dma_ring_test,
1194 .ib_test = &r600_dma_ib_test,
1195 .is_lockup = &r600_dma_is_lockup,
f93bdefe
AD		 1196 .get_rptr = &radeon_ring_generic_get_rptr,
1197 .get_wptr = &radeon_ring_generic_get_wptr,
1198 .set_wptr = &radeon_ring_generic_set_wptr,
f2ba57b5
CK		 1199 },
1200 [R600_RING_TYPE_UVD_INDEX] = {
1201 .ib_execute = &r600_uvd_ib_execute,
1202 .emit_fence = &r600_uvd_fence_emit,
1203 .emit_semaphore = &r600_uvd_semaphore_emit,
1204 .cs_parse = &radeon_uvd_cs_parse,
1205 .ring_test = &r600_uvd_ring_test,
1206 .ib_test = &r600_uvd_ib_test,
1207 .is_lockup = &radeon_ring_test_lockup,
f93bdefe
AD		 1208 .get_rptr = &radeon_ring_generic_get_rptr,
1209 .get_wptr = &radeon_ring_generic_get_wptr,
1210 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 1211 }
1212 },
b35ea4ab
AD		 1213 .irq = {
1214 .set = &r600_irq_set,
1215 .process = &r600_irq_process,
1216 },
c79a49ca
AD		 1217 .display = {
1218 .bandwidth_update = &rv515_bandwidth_update,
1219 .get_vblank_counter = &rs600_get_vblank_counter,
1220 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 1221 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1222 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1223 .hdmi_enable = &r600_hdmi_enable,
1224 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 1225 },
27cd7769
AD		 1226 .copy = {
1227 .blit = &r600_copy_blit,
1228 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
43fb7787 1229 .dma = &rv770_copy_dma,
4d75658b 1230 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
43fb7787 1231 .copy = &rv770_copy_dma,
2d6cc729 1232 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1233 },
9e6f3d02
AD		 1234 .surface = {
1235 .set_reg = r600_set_surface_reg,
1236 .clear_reg = r600_clear_surface_reg,
1237 },
901ea57d
AD		 1238 .hpd = {
1239 .init = &r600_hpd_init,
1240 .fini = &r600_hpd_fini,
1241 .sense = &r600_hpd_sense,
1242 .set_polarity = &r600_hpd_set_polarity,
1243 },
a02fa397
AD		 1244 .pm = {
1245 .misc = &rv770_pm_misc,
1246 .prepare = &rs600_pm_prepare,
1247 .finish = &rs600_pm_finish,
1248 .init_profile = &r600_pm_init_profile,
1249 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1250 .get_engine_clock = &radeon_atom_get_engine_clock,
1251 .set_engine_clock = &radeon_atom_set_engine_clock,
1252 .get_memory_clock = &radeon_atom_get_memory_clock,
1253 .set_memory_clock = &radeon_atom_set_memory_clock,
1254 .get_pcie_lanes = &r600_get_pcie_lanes,
1255 .set_pcie_lanes = &r600_set_pcie_lanes,
1256 .set_clock_gating = &radeon_atom_set_clock_gating,
ef0e6e65 1257 .set_uvd_clocks = &rv770_set_uvd_clocks,
6bd1c385 1258 .get_temperature = &rv770_get_temp,
a02fa397 1259 },
0f9e006c
AD		 1260 .pflip = {
1261 .pre_page_flip = &rs600_pre_page_flip,
1262 .page_flip = &rv770_page_flip,
1263 .post_page_flip = &rs600_post_page_flip,
1264 },
48e7a5f1
DV		 1265};
1266
1267static struct radeon_asic evergreen_asic = {
1268 .init = &evergreen_init,
1269 .fini = &evergreen_fini,
1270 .suspend = &evergreen_suspend,
1271 .resume = &evergreen_resume,
a2d07b74 1272 .asic_reset = &evergreen_asic_reset,
48e7a5f1 1273 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1274 .ioctl_wait_idle = r600_ioctl_wait_idle,
1275 .gui_idle = &r600_gui_idle,
1276 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1277 .get_xclk = &rv770_get_xclk,
d0418894 1278 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1279 .gart = {
1280 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1281 .set_page = &rs600_gart_set_page,
1282 },
4c87bc26
CK		 1283 .ring = {
1284 [RADEON_RING_TYPE_GFX_INDEX] = {
1285 .ib_execute = &evergreen_ring_ib_execute,
1286 .emit_fence = &r600_fence_ring_emit,
1287 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1288 .cs_parse = &evergreen_cs_parse,
f712812e
AD		 1289 .ring_test = &r600_ring_test,
1290 .ib_test = &r600_ib_test,
123bc183 1291 .is_lockup = &evergreen_gfx_is_lockup,
f93bdefe
AD		 1292 .get_rptr = &radeon_ring_generic_get_rptr,
1293 .get_wptr = &radeon_ring_generic_get_wptr,
1294 .set_wptr = &radeon_ring_generic_set_wptr,
233d1ad5
AD		 1295 },
1296 [R600_RING_TYPE_DMA_INDEX] = {
1297 .ib_execute = &evergreen_dma_ring_ib_execute,
1298 .emit_fence = &evergreen_dma_fence_ring_emit,
1299 .emit_semaphore = &r600_dma_semaphore_ring_emit,
d2ead3ea 1300 .cs_parse = &evergreen_dma_cs_parse,
233d1ad5
AD		 1301 .ring_test = &r600_dma_ring_test,
1302 .ib_test = &r600_dma_ib_test,
123bc183 1303 .is_lockup = &evergreen_dma_is_lockup,
f93bdefe
AD		 1304 .get_rptr = &radeon_ring_generic_get_rptr,
1305 .get_wptr = &radeon_ring_generic_get_wptr,
1306 .set_wptr = &radeon_ring_generic_set_wptr,
f2ba57b5
CK		 1307 },
1308 [R600_RING_TYPE_UVD_INDEX] = {
1309 .ib_execute = &r600_uvd_ib_execute,
1310 .emit_fence = &r600_uvd_fence_emit,
1311 .emit_semaphore = &r600_uvd_semaphore_emit,
1312 .cs_parse = &radeon_uvd_cs_parse,
1313 .ring_test = &r600_uvd_ring_test,
1314 .ib_test = &r600_uvd_ib_test,
1315 .is_lockup = &radeon_ring_test_lockup,
f93bdefe
AD		 1316 .get_rptr = &radeon_ring_generic_get_rptr,
1317 .get_wptr = &radeon_ring_generic_get_wptr,
1318 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 1319 }
1320 },
b35ea4ab
AD		 1321 .irq = {
1322 .set = &evergreen_irq_set,
1323 .process = &evergreen_irq_process,
1324 },
c79a49ca
AD		 1325 .display = {
1326 .bandwidth_update = &evergreen_bandwidth_update,
1327 .get_vblank_counter = &evergreen_get_vblank_counter,
1328 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1329 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1330 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1331 .hdmi_enable = &evergreen_hdmi_enable,
1332 .hdmi_setmode = &evergreen_hdmi_setmode,
c79a49ca 1333 },
27cd7769
AD		 1334 .copy = {
1335 .blit = &r600_copy_blit,
1336 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1337 .dma = &evergreen_copy_dma,
1338 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1339 .copy = &evergreen_copy_dma,
1340 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1341 },
9e6f3d02
AD		 1342 .surface = {
1343 .set_reg = r600_set_surface_reg,
1344 .clear_reg = r600_clear_surface_reg,
1345 },
901ea57d
AD		 1346 .hpd = {
1347 .init = &evergreen_hpd_init,
1348 .fini = &evergreen_hpd_fini,
1349 .sense = &evergreen_hpd_sense,
1350 .set_polarity = &evergreen_hpd_set_polarity,
1351 },
a02fa397
AD		 1352 .pm = {
1353 .misc = &evergreen_pm_misc,
1354 .prepare = &evergreen_pm_prepare,
1355 .finish = &evergreen_pm_finish,
1356 .init_profile = &r600_pm_init_profile,
1357 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1358 .get_engine_clock = &radeon_atom_get_engine_clock,
1359 .set_engine_clock = &radeon_atom_set_engine_clock,
1360 .get_memory_clock = &radeon_atom_get_memory_clock,
1361 .set_memory_clock = &radeon_atom_set_memory_clock,
1362 .get_pcie_lanes = &r600_get_pcie_lanes,
1363 .set_pcie_lanes = &r600_set_pcie_lanes,
1364 .set_clock_gating = NULL,
a8b4925c 1365 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1366 .get_temperature = &evergreen_get_temp,
a02fa397 1367 },
0f9e006c
AD		 1368 .pflip = {
1369 .pre_page_flip = &evergreen_pre_page_flip,
1370 .page_flip = &evergreen_page_flip,
1371 .post_page_flip = &evergreen_post_page_flip,
1372 },
48e7a5f1
DV		 1373};
1374
958261d1
AD		 1375static struct radeon_asic sumo_asic = {
1376 .init = &evergreen_init,
1377 .fini = &evergreen_fini,
1378 .suspend = &evergreen_suspend,
1379 .resume = &evergreen_resume,
958261d1
AD		 1380 .asic_reset = &evergreen_asic_reset,
1381 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1382 .ioctl_wait_idle = r600_ioctl_wait_idle,
1383 .gui_idle = &r600_gui_idle,
1384 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1385 .get_xclk = &r600_get_xclk,
d0418894 1386 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1387 .gart = {
1388 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1389 .set_page = &rs600_gart_set_page,
1390 },
4c87bc26
CK		 1391 .ring = {
1392 [RADEON_RING_TYPE_GFX_INDEX] = {
1393 .ib_execute = &evergreen_ring_ib_execute,
1394 .emit_fence = &r600_fence_ring_emit,
1395 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1396 .cs_parse = &evergreen_cs_parse,
f712812e
AD		 1397 .ring_test = &r600_ring_test,
1398 .ib_test = &r600_ib_test,
123bc183 1399 .is_lockup = &evergreen_gfx_is_lockup,
f93bdefe
AD		 1400 .get_rptr = &radeon_ring_generic_get_rptr,
1401 .get_wptr = &radeon_ring_generic_get_wptr,
1402 .set_wptr = &radeon_ring_generic_set_wptr,
eb0c19c5 1403 },
233d1ad5
AD		 1404 [R600_RING_TYPE_DMA_INDEX] = {
1405 .ib_execute = &evergreen_dma_ring_ib_execute,
1406 .emit_fence = &evergreen_dma_fence_ring_emit,
1407 .emit_semaphore = &r600_dma_semaphore_ring_emit,
d2ead3ea 1408 .cs_parse = &evergreen_dma_cs_parse,
233d1ad5
AD		 1409 .ring_test = &r600_dma_ring_test,
1410 .ib_test = &r600_dma_ib_test,
123bc183 1411 .is_lockup = &evergreen_dma_is_lockup,
f93bdefe
AD		 1412 .get_rptr = &radeon_ring_generic_get_rptr,
1413 .get_wptr = &radeon_ring_generic_get_wptr,
1414 .set_wptr = &radeon_ring_generic_set_wptr,
f2ba57b5
CK		 1415 },
1416 [R600_RING_TYPE_UVD_INDEX] = {
1417 .ib_execute = &r600_uvd_ib_execute,
1418 .emit_fence = &r600_uvd_fence_emit,
1419 .emit_semaphore = &r600_uvd_semaphore_emit,
1420 .cs_parse = &radeon_uvd_cs_parse,
1421 .ring_test = &r600_uvd_ring_test,
1422 .ib_test = &r600_uvd_ib_test,
1423 .is_lockup = &radeon_ring_test_lockup,
f93bdefe
AD		 1424 .get_rptr = &radeon_ring_generic_get_rptr,
1425 .get_wptr = &radeon_ring_generic_get_wptr,
1426 .set_wptr = &radeon_ring_generic_set_wptr,
233d1ad5 1427 }
4c87bc26 1428 },
b35ea4ab
AD		 1429 .irq = {
1430 .set = &evergreen_irq_set,
1431 .process = &evergreen_irq_process,
1432 },
c79a49ca
AD		 1433 .display = {
1434 .bandwidth_update = &evergreen_bandwidth_update,
1435 .get_vblank_counter = &evergreen_get_vblank_counter,
1436 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1437 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1438 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1439 .hdmi_enable = &evergreen_hdmi_enable,
1440 .hdmi_setmode = &evergreen_hdmi_setmode,
c79a49ca 1441 },
27cd7769
AD		 1442 .copy = {
1443 .blit = &r600_copy_blit,
1444 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1445 .dma = &evergreen_copy_dma,
1446 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1447 .copy = &evergreen_copy_dma,
1448 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1449 },
9e6f3d02
AD		 1450 .surface = {
1451 .set_reg = r600_set_surface_reg,
1452 .clear_reg = r600_clear_surface_reg,
1453 },
901ea57d
AD		 1454 .hpd = {
1455 .init = &evergreen_hpd_init,
1456 .fini = &evergreen_hpd_fini,
1457 .sense = &evergreen_hpd_sense,
1458 .set_polarity = &evergreen_hpd_set_polarity,
1459 },
a02fa397
AD		 1460 .pm = {
1461 .misc = &evergreen_pm_misc,
1462 .prepare = &evergreen_pm_prepare,
1463 .finish = &evergreen_pm_finish,
1464 .init_profile = &sumo_pm_init_profile,
1465 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1466 .get_engine_clock = &radeon_atom_get_engine_clock,
1467 .set_engine_clock = &radeon_atom_set_engine_clock,
1468 .get_memory_clock = NULL,
1469 .set_memory_clock = NULL,
1470 .get_pcie_lanes = NULL,
1471 .set_pcie_lanes = NULL,
1472 .set_clock_gating = NULL,
23d33ba3 1473 .set_uvd_clocks = &sumo_set_uvd_clocks,
6bd1c385 1474 .get_temperature = &sumo_get_temp,
a02fa397 1475 },
0f9e006c
AD		 1476 .pflip = {
1477 .pre_page_flip = &evergreen_pre_page_flip,
1478 .page_flip = &evergreen_page_flip,
1479 .post_page_flip = &evergreen_post_page_flip,
1480 },
958261d1
AD		 1481};
1482
a43b7665
AD		 1483static struct radeon_asic btc_asic = {
1484 .init = &evergreen_init,
1485 .fini = &evergreen_fini,
1486 .suspend = &evergreen_suspend,
1487 .resume = &evergreen_resume,
a43b7665
AD		 1488 .asic_reset = &evergreen_asic_reset,
1489 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1490 .ioctl_wait_idle = r600_ioctl_wait_idle,
1491 .gui_idle = &r600_gui_idle,
1492 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1493 .get_xclk = &rv770_get_xclk,
d0418894 1494 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1495 .gart = {
1496 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1497 .set_page = &rs600_gart_set_page,
1498 },
4c87bc26
CK		 1499 .ring = {
1500 [RADEON_RING_TYPE_GFX_INDEX] = {
1501 .ib_execute = &evergreen_ring_ib_execute,
1502 .emit_fence = &r600_fence_ring_emit,
1503 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1504 .cs_parse = &evergreen_cs_parse,
f712812e
AD		 1505 .ring_test = &r600_ring_test,
1506 .ib_test = &r600_ib_test,
123bc183 1507 .is_lockup = &evergreen_gfx_is_lockup,
f93bdefe
AD		 1508 .get_rptr = &radeon_ring_generic_get_rptr,
1509 .get_wptr = &radeon_ring_generic_get_wptr,
1510 .set_wptr = &radeon_ring_generic_set_wptr,
233d1ad5
AD		 1511 },
1512 [R600_RING_TYPE_DMA_INDEX] = {
1513 .ib_execute = &evergreen_dma_ring_ib_execute,
1514 .emit_fence = &evergreen_dma_fence_ring_emit,
1515 .emit_semaphore = &r600_dma_semaphore_ring_emit,
d2ead3ea 1516 .cs_parse = &evergreen_dma_cs_parse,
233d1ad5
AD		 1517 .ring_test = &r600_dma_ring_test,
1518 .ib_test = &r600_dma_ib_test,
123bc183 1519 .is_lockup = &evergreen_dma_is_lockup,
f93bdefe
AD		 1520 .get_rptr = &radeon_ring_generic_get_rptr,
1521 .get_wptr = &radeon_ring_generic_get_wptr,
1522 .set_wptr = &radeon_ring_generic_set_wptr,
f2ba57b5
CK		 1523 },
1524 [R600_RING_TYPE_UVD_INDEX] = {
1525 .ib_execute = &r600_uvd_ib_execute,
1526 .emit_fence = &r600_uvd_fence_emit,
1527 .emit_semaphore = &r600_uvd_semaphore_emit,
1528 .cs_parse = &radeon_uvd_cs_parse,
1529 .ring_test = &r600_uvd_ring_test,
1530 .ib_test = &r600_uvd_ib_test,
1531 .is_lockup = &radeon_ring_test_lockup,
f93bdefe
AD		 1532 .get_rptr = &radeon_ring_generic_get_rptr,
1533 .get_wptr = &radeon_ring_generic_get_wptr,
1534 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 1535 }
1536 },
b35ea4ab
AD		 1537 .irq = {
1538 .set = &evergreen_irq_set,
1539 .process = &evergreen_irq_process,
1540 },
c79a49ca
AD		 1541 .display = {
1542 .bandwidth_update = &evergreen_bandwidth_update,
1543 .get_vblank_counter = &evergreen_get_vblank_counter,
1544 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1545 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1546 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1547 .hdmi_enable = &evergreen_hdmi_enable,
1548 .hdmi_setmode = &evergreen_hdmi_setmode,
c79a49ca 1549 },
27cd7769
AD		 1550 .copy = {
1551 .blit = &r600_copy_blit,
1552 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1553 .dma = &evergreen_copy_dma,
1554 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1555 .copy = &evergreen_copy_dma,
1556 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1557 },
9e6f3d02
AD		 1558 .surface = {
1559 .set_reg = r600_set_surface_reg,
1560 .clear_reg = r600_clear_surface_reg,
1561 },
901ea57d
AD		 1562 .hpd = {
1563 .init = &evergreen_hpd_init,
1564 .fini = &evergreen_hpd_fini,
1565 .sense = &evergreen_hpd_sense,
1566 .set_polarity = &evergreen_hpd_set_polarity,
1567 },
a02fa397
AD		 1568 .pm = {
1569 .misc = &evergreen_pm_misc,
1570 .prepare = &evergreen_pm_prepare,
1571 .finish = &evergreen_pm_finish,
27810fb2 1572 .init_profile = &btc_pm_init_profile,
a02fa397 1573 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1574 .get_engine_clock = &radeon_atom_get_engine_clock,
1575 .set_engine_clock = &radeon_atom_set_engine_clock,
1576 .get_memory_clock = &radeon_atom_get_memory_clock,
1577 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1578 .get_pcie_lanes = &r600_get_pcie_lanes,
1579 .set_pcie_lanes = &r600_set_pcie_lanes,
798bcf73 1580 .set_clock_gating = NULL,
a8b4925c 1581 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1582 .get_temperature = &evergreen_get_temp,
a02fa397 1583 },
0f9e006c
AD		 1584 .pflip = {
1585 .pre_page_flip = &evergreen_pre_page_flip,
1586 .page_flip = &evergreen_page_flip,
1587 .post_page_flip = &evergreen_post_page_flip,
1588 },
a43b7665
AD		 1589};
1590
e3487629
AD		 1591static struct radeon_asic cayman_asic = {
1592 .init = &cayman_init,
1593 .fini = &cayman_fini,
1594 .suspend = &cayman_suspend,
1595 .resume = &cayman_resume,
e3487629
AD		 1596 .asic_reset = &cayman_asic_reset,
1597 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1598 .ioctl_wait_idle = r600_ioctl_wait_idle,
1599 .gui_idle = &r600_gui_idle,
1600 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1601 .get_xclk = &rv770_get_xclk,
d0418894 1602 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1603 .gart = {
1604 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1605 .set_page = &rs600_gart_set_page,
1606 },
05b07147
CK		 1607 .vm = {
1608 .init = &cayman_vm_init,
1609 .fini = &cayman_vm_fini,
df160044 1610 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
05b07147
CK		 1611 .set_page = &cayman_vm_set_page,
1612 },
4c87bc26
CK		 1613 .ring = {
1614 [RADEON_RING_TYPE_GFX_INDEX] = {
721604a1
JG		 1615 .ib_execute = &cayman_ring_ib_execute,
1616 .ib_parse = &evergreen_ib_parse,
b40e7e16 1617 .emit_fence = &cayman_fence_ring_emit,
4c87bc26 1618 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1619 .cs_parse = &evergreen_cs_parse,
f712812e
AD		 1620 .ring_test = &r600_ring_test,
1621 .ib_test = &r600_ib_test,
123bc183 1622 .is_lockup = &cayman_gfx_is_lockup,
9b40e5d8 1623 .vm_flush = &cayman_vm_flush,
f93bdefe
AD		 1624 .get_rptr = &radeon_ring_generic_get_rptr,
1625 .get_wptr = &radeon_ring_generic_get_wptr,
1626 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 1627 },
1628 [CAYMAN_RING_TYPE_CP1_INDEX] = {
721604a1
JG		 1629 .ib_execute = &cayman_ring_ib_execute,
1630 .ib_parse = &evergreen_ib_parse,
b40e7e16 1631 .emit_fence = &cayman_fence_ring_emit,
4c87bc26 1632 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1633 .cs_parse = &evergreen_cs_parse,
f712812e
AD		 1634 .ring_test = &r600_ring_test,
1635 .ib_test = &r600_ib_test,
123bc183 1636 .is_lockup = &cayman_gfx_is_lockup,
9b40e5d8 1637 .vm_flush = &cayman_vm_flush,
f93bdefe
AD		 1638 .get_rptr = &radeon_ring_generic_get_rptr,
1639 .get_wptr = &radeon_ring_generic_get_wptr,
1640 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 1641 },
1642 [CAYMAN_RING_TYPE_CP2_INDEX] = {
721604a1
JG		 1643 .ib_execute = &cayman_ring_ib_execute,
1644 .ib_parse = &evergreen_ib_parse,
b40e7e16 1645 .emit_fence = &cayman_fence_ring_emit,
4c87bc26 1646 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1647 .cs_parse = &evergreen_cs_parse,
f712812e
AD		 1648 .ring_test = &r600_ring_test,
1649 .ib_test = &r600_ib_test,
123bc183 1650 .is_lockup = &cayman_gfx_is_lockup,
9b40e5d8 1651 .vm_flush = &cayman_vm_flush,
f93bdefe
AD		 1652 .get_rptr = &radeon_ring_generic_get_rptr,
1653 .get_wptr = &radeon_ring_generic_get_wptr,
1654 .set_wptr = &radeon_ring_generic_set_wptr,
f60cbd11
AD		 1655 },
1656 [R600_RING_TYPE_DMA_INDEX] = {
1657 .ib_execute = &cayman_dma_ring_ib_execute,
cd459e52 1658 .ib_parse = &evergreen_dma_ib_parse,
f60cbd11
AD		 1659 .emit_fence = &evergreen_dma_fence_ring_emit,
1660 .emit_semaphore = &r600_dma_semaphore_ring_emit,
d2ead3ea 1661 .cs_parse = &evergreen_dma_cs_parse,
f60cbd11
AD		 1662 .ring_test = &r600_dma_ring_test,
1663 .ib_test = &r600_dma_ib_test,
1664 .is_lockup = &cayman_dma_is_lockup,
1665 .vm_flush = &cayman_dma_vm_flush,
f93bdefe
AD		 1666 .get_rptr = &radeon_ring_generic_get_rptr,
1667 .get_wptr = &radeon_ring_generic_get_wptr,
1668 .set_wptr = &radeon_ring_generic_set_wptr,
f60cbd11
AD		 1669 },
1670 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1671 .ib_execute = &cayman_dma_ring_ib_execute,
cd459e52 1672 .ib_parse = &evergreen_dma_ib_parse,
f60cbd11
AD		 1673 .emit_fence = &evergreen_dma_fence_ring_emit,
1674 .emit_semaphore = &r600_dma_semaphore_ring_emit,
d2ead3ea 1675 .cs_parse = &evergreen_dma_cs_parse,
f60cbd11
AD		 1676 .ring_test = &r600_dma_ring_test,
1677 .ib_test = &r600_dma_ib_test,
1678 .is_lockup = &cayman_dma_is_lockup,
1679 .vm_flush = &cayman_dma_vm_flush,
f93bdefe
AD		 1680 .get_rptr = &radeon_ring_generic_get_rptr,
1681 .get_wptr = &radeon_ring_generic_get_wptr,
1682 .set_wptr = &radeon_ring_generic_set_wptr,
f2ba57b5
CK		 1683 },
1684 [R600_RING_TYPE_UVD_INDEX] = {
1685 .ib_execute = &r600_uvd_ib_execute,
1686 .emit_fence = &r600_uvd_fence_emit,
1687 .emit_semaphore = &cayman_uvd_semaphore_emit,
1688 .cs_parse = &radeon_uvd_cs_parse,
1689 .ring_test = &r600_uvd_ring_test,
1690 .ib_test = &r600_uvd_ib_test,
1691 .is_lockup = &radeon_ring_test_lockup,
f93bdefe
AD		 1692 .get_rptr = &radeon_ring_generic_get_rptr,
1693 .get_wptr = &radeon_ring_generic_get_wptr,
1694 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 1695 }
1696 },
b35ea4ab
AD		 1697 .irq = {
1698 .set = &evergreen_irq_set,
1699 .process = &evergreen_irq_process,
1700 },
c79a49ca
AD		 1701 .display = {
1702 .bandwidth_update = &evergreen_bandwidth_update,
1703 .get_vblank_counter = &evergreen_get_vblank_counter,
1704 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1705 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1706 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1707 .hdmi_enable = &evergreen_hdmi_enable,
1708 .hdmi_setmode = &evergreen_hdmi_setmode,
c79a49ca 1709 },
27cd7769
AD		 1710 .copy = {
1711 .blit = &r600_copy_blit,
1712 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
f60cbd11
AD		 1713 .dma = &evergreen_copy_dma,
1714 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1715 .copy = &evergreen_copy_dma,
1716 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1717 },
9e6f3d02
AD		 1718 .surface = {
1719 .set_reg = r600_set_surface_reg,
1720 .clear_reg = r600_clear_surface_reg,
1721 },
901ea57d
AD		 1722 .hpd = {
1723 .init = &evergreen_hpd_init,
1724 .fini = &evergreen_hpd_fini,
1725 .sense = &evergreen_hpd_sense,
1726 .set_polarity = &evergreen_hpd_set_polarity,
1727 },
a02fa397
AD		 1728 .pm = {
1729 .misc = &evergreen_pm_misc,
1730 .prepare = &evergreen_pm_prepare,
1731 .finish = &evergreen_pm_finish,
27810fb2 1732 .init_profile = &btc_pm_init_profile,
a02fa397 1733 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1734 .get_engine_clock = &radeon_atom_get_engine_clock,
1735 .set_engine_clock = &radeon_atom_set_engine_clock,
1736 .get_memory_clock = &radeon_atom_get_memory_clock,
1737 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1738 .get_pcie_lanes = &r600_get_pcie_lanes,
1739 .set_pcie_lanes = &r600_set_pcie_lanes,
798bcf73 1740 .set_clock_gating = NULL,
a8b4925c 1741 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1742 .get_temperature = &evergreen_get_temp,
a02fa397 1743 },
0f9e006c
AD		 1744 .pflip = {
1745 .pre_page_flip = &evergreen_pre_page_flip,
1746 .page_flip = &evergreen_page_flip,
1747 .post_page_flip = &evergreen_post_page_flip,
1748 },
e3487629
AD		 1749};
1750
be63fe8c
AD		 1751static struct radeon_asic trinity_asic = {
1752 .init = &cayman_init,
1753 .fini = &cayman_fini,
1754 .suspend = &cayman_suspend,
1755 .resume = &cayman_resume,
be63fe8c
AD		 1756 .asic_reset = &cayman_asic_reset,
1757 .vga_set_state = &r600_vga_set_state,
1758 .ioctl_wait_idle = r600_ioctl_wait_idle,
1759 .gui_idle = &r600_gui_idle,
1760 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1761 .get_xclk = &r600_get_xclk,
d0418894 1762 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
be63fe8c
AD		 1763 .gart = {
1764 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1765 .set_page = &rs600_gart_set_page,
1766 },
05b07147
CK		 1767 .vm = {
1768 .init = &cayman_vm_init,
1769 .fini = &cayman_vm_fini,
df160044 1770 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
05b07147
CK		 1771 .set_page = &cayman_vm_set_page,
1772 },
be63fe8c
AD		 1773 .ring = {
1774 [RADEON_RING_TYPE_GFX_INDEX] = {
1775 .ib_execute = &cayman_ring_ib_execute,
1776 .ib_parse = &evergreen_ib_parse,
1777 .emit_fence = &cayman_fence_ring_emit,
1778 .emit_semaphore = &r600_semaphore_ring_emit,
1779 .cs_parse = &evergreen_cs_parse,
1780 .ring_test = &r600_ring_test,
1781 .ib_test = &r600_ib_test,
123bc183 1782 .is_lockup = &cayman_gfx_is_lockup,
9b40e5d8 1783 .vm_flush = &cayman_vm_flush,
f93bdefe
AD		 1784 .get_rptr = &radeon_ring_generic_get_rptr,
1785 .get_wptr = &radeon_ring_generic_get_wptr,
1786 .set_wptr = &radeon_ring_generic_set_wptr,
be63fe8c
AD		 1787 },
1788 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1789 .ib_execute = &cayman_ring_ib_execute,
1790 .ib_parse = &evergreen_ib_parse,
1791 .emit_fence = &cayman_fence_ring_emit,
1792 .emit_semaphore = &r600_semaphore_ring_emit,
1793 .cs_parse = &evergreen_cs_parse,
1794 .ring_test = &r600_ring_test,
1795 .ib_test = &r600_ib_test,
123bc183 1796 .is_lockup = &cayman_gfx_is_lockup,
9b40e5d8 1797 .vm_flush = &cayman_vm_flush,
f93bdefe
AD		 1798 .get_rptr = &radeon_ring_generic_get_rptr,
1799 .get_wptr = &radeon_ring_generic_get_wptr,
1800 .set_wptr = &radeon_ring_generic_set_wptr,
be63fe8c
AD		 1801 },
1802 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1803 .ib_execute = &cayman_ring_ib_execute,
1804 .ib_parse = &evergreen_ib_parse,
1805 .emit_fence = &cayman_fence_ring_emit,
1806 .emit_semaphore = &r600_semaphore_ring_emit,
1807 .cs_parse = &evergreen_cs_parse,
1808 .ring_test = &r600_ring_test,
1809 .ib_test = &r600_ib_test,
123bc183 1810 .is_lockup = &cayman_gfx_is_lockup,
9b40e5d8 1811 .vm_flush = &cayman_vm_flush,
f93bdefe
AD		 1812 .get_rptr = &radeon_ring_generic_get_rptr,
1813 .get_wptr = &radeon_ring_generic_get_wptr,
1814 .set_wptr = &radeon_ring_generic_set_wptr,
f60cbd11
AD		 1815 },
1816 [R600_RING_TYPE_DMA_INDEX] = {
1817 .ib_execute = &cayman_dma_ring_ib_execute,
cd459e52 1818 .ib_parse = &evergreen_dma_ib_parse,
f60cbd11
AD		 1819 .emit_fence = &evergreen_dma_fence_ring_emit,
1820 .emit_semaphore = &r600_dma_semaphore_ring_emit,
d2ead3ea 1821 .cs_parse = &evergreen_dma_cs_parse,
f60cbd11
AD		 1822 .ring_test = &r600_dma_ring_test,
1823 .ib_test = &r600_dma_ib_test,
1824 .is_lockup = &cayman_dma_is_lockup,
1825 .vm_flush = &cayman_dma_vm_flush,
f93bdefe
AD		 1826 .get_rptr = &radeon_ring_generic_get_rptr,
1827 .get_wptr = &radeon_ring_generic_get_wptr,
1828 .set_wptr = &radeon_ring_generic_set_wptr,
f60cbd11
AD		 1829 },
1830 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1831 .ib_execute = &cayman_dma_ring_ib_execute,
cd459e52 1832 .ib_parse = &evergreen_dma_ib_parse,
f60cbd11
AD		 1833 .emit_fence = &evergreen_dma_fence_ring_emit,
1834 .emit_semaphore = &r600_dma_semaphore_ring_emit,
d2ead3ea 1835 .cs_parse = &evergreen_dma_cs_parse,
f60cbd11
AD		 1836 .ring_test = &r600_dma_ring_test,
1837 .ib_test = &r600_dma_ib_test,
1838 .is_lockup = &cayman_dma_is_lockup,
1839 .vm_flush = &cayman_dma_vm_flush,
f93bdefe
AD		 1840 .get_rptr = &radeon_ring_generic_get_rptr,
1841 .get_wptr = &radeon_ring_generic_get_wptr,
1842 .set_wptr = &radeon_ring_generic_set_wptr,
f2ba57b5
CK		 1843 },
1844 [R600_RING_TYPE_UVD_INDEX] = {
1845 .ib_execute = &r600_uvd_ib_execute,
1846 .emit_fence = &r600_uvd_fence_emit,
1847 .emit_semaphore = &cayman_uvd_semaphore_emit,
1848 .cs_parse = &radeon_uvd_cs_parse,
1849 .ring_test = &r600_uvd_ring_test,
1850 .ib_test = &r600_uvd_ib_test,
1851 .is_lockup = &radeon_ring_test_lockup,
f93bdefe
AD		 1852 .get_rptr = &radeon_ring_generic_get_rptr,
1853 .get_wptr = &radeon_ring_generic_get_wptr,
1854 .set_wptr = &radeon_ring_generic_set_wptr,
be63fe8c
AD		 1855 }
1856 },
1857 .irq = {
1858 .set = &evergreen_irq_set,
1859 .process = &evergreen_irq_process,
1860 },
1861 .display = {
1862 .bandwidth_update = &dce6_bandwidth_update,
1863 .get_vblank_counter = &evergreen_get_vblank_counter,
1864 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1865 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1866 .get_backlight_level = &atombios_get_backlight_level,
be63fe8c
AD		 1867 },
1868 .copy = {
1869 .blit = &r600_copy_blit,
1870 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
f60cbd11
AD		 1871 .dma = &evergreen_copy_dma,
1872 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1873 .copy = &evergreen_copy_dma,
1874 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
be63fe8c
AD		 1875 },
1876 .surface = {
1877 .set_reg = r600_set_surface_reg,
1878 .clear_reg = r600_clear_surface_reg,
1879 },
1880 .hpd = {
1881 .init = &evergreen_hpd_init,
1882 .fini = &evergreen_hpd_fini,
1883 .sense = &evergreen_hpd_sense,
1884 .set_polarity = &evergreen_hpd_set_polarity,
1885 },
1886 .pm = {
1887 .misc = &evergreen_pm_misc,
1888 .prepare = &evergreen_pm_prepare,
1889 .finish = &evergreen_pm_finish,
1890 .init_profile = &sumo_pm_init_profile,
1891 .get_dynpm_state = &r600_pm_get_dynpm_state,
1892 .get_engine_clock = &radeon_atom_get_engine_clock,
1893 .set_engine_clock = &radeon_atom_set_engine_clock,
1894 .get_memory_clock = NULL,
1895 .set_memory_clock = NULL,
1896 .get_pcie_lanes = NULL,
1897 .set_pcie_lanes = NULL,
1898 .set_clock_gating = NULL,
23d33ba3 1899 .set_uvd_clocks = &sumo_set_uvd_clocks,
29a15221 1900 .get_temperature = &tn_get_temp,
be63fe8c
AD		 1901 },
1902 .pflip = {
1903 .pre_page_flip = &evergreen_pre_page_flip,
1904 .page_flip = &evergreen_page_flip,
1905 .post_page_flip = &evergreen_post_page_flip,
1906 },
1907};
1908
02779c08
AD		 1909static struct radeon_asic si_asic = {
1910 .init = &si_init,
1911 .fini = &si_fini,
1912 .suspend = &si_suspend,
1913 .resume = &si_resume,
02779c08
AD		 1914 .asic_reset = &si_asic_reset,
1915 .vga_set_state = &r600_vga_set_state,
1916 .ioctl_wait_idle = r600_ioctl_wait_idle,
1917 .gui_idle = &r600_gui_idle,
1918 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1919 .get_xclk = &si_get_xclk,
d0418894 1920 .get_gpu_clock_counter = &si_get_gpu_clock_counter,
02779c08
AD		 1921 .gart = {
1922 .tlb_flush = &si_pcie_gart_tlb_flush,
1923 .set_page = &rs600_gart_set_page,
1924 },
05b07147
CK		 1925 .vm = {
1926 .init = &si_vm_init,
1927 .fini = &si_vm_fini,
df160044 1928 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
82ffd92b 1929 .set_page = &si_vm_set_page,
05b07147 1930 },
02779c08
AD		 1931 .ring = {
1932 [RADEON_RING_TYPE_GFX_INDEX] = {
1933 .ib_execute = &si_ring_ib_execute,
1934 .ib_parse = &si_ib_parse,
1935 .emit_fence = &si_fence_ring_emit,
1936 .emit_semaphore = &r600_semaphore_ring_emit,
1937 .cs_parse = NULL,
1938 .ring_test = &r600_ring_test,
1939 .ib_test = &r600_ib_test,
123bc183 1940 .is_lockup = &si_gfx_is_lockup,
ee60e29f 1941 .vm_flush = &si_vm_flush,
f93bdefe
AD		 1942 .get_rptr = &radeon_ring_generic_get_rptr,
1943 .get_wptr = &radeon_ring_generic_get_wptr,
1944 .set_wptr = &radeon_ring_generic_set_wptr,
02779c08
AD		 1945 },
1946 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1947 .ib_execute = &si_ring_ib_execute,
1948 .ib_parse = &si_ib_parse,
1949 .emit_fence = &si_fence_ring_emit,
1950 .emit_semaphore = &r600_semaphore_ring_emit,
1951 .cs_parse = NULL,
1952 .ring_test = &r600_ring_test,
1953 .ib_test = &r600_ib_test,
123bc183 1954 .is_lockup = &si_gfx_is_lockup,
ee60e29f 1955 .vm_flush = &si_vm_flush,
f93bdefe
AD		 1956 .get_rptr = &radeon_ring_generic_get_rptr,
1957 .get_wptr = &radeon_ring_generic_get_wptr,
1958 .set_wptr = &radeon_ring_generic_set_wptr,
02779c08
AD		 1959 },
1960 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1961 .ib_execute = &si_ring_ib_execute,
1962 .ib_parse = &si_ib_parse,
1963 .emit_fence = &si_fence_ring_emit,
1964 .emit_semaphore = &r600_semaphore_ring_emit,
1965 .cs_parse = NULL,
1966 .ring_test = &r600_ring_test,
1967 .ib_test = &r600_ib_test,
123bc183 1968 .is_lockup = &si_gfx_is_lockup,
ee60e29f 1969 .vm_flush = &si_vm_flush,
f93bdefe
AD		 1970 .get_rptr = &radeon_ring_generic_get_rptr,
1971 .get_wptr = &radeon_ring_generic_get_wptr,
1972 .set_wptr = &radeon_ring_generic_set_wptr,
8c5fd7ef
AD		 1973 },
1974 [R600_RING_TYPE_DMA_INDEX] = {
1975 .ib_execute = &cayman_dma_ring_ib_execute,
cd459e52 1976 .ib_parse = &evergreen_dma_ib_parse,
8c5fd7ef
AD		 1977 .emit_fence = &evergreen_dma_fence_ring_emit,
1978 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1979 .cs_parse = NULL,
1980 .ring_test = &r600_dma_ring_test,
1981 .ib_test = &r600_dma_ib_test,
123bc183 1982 .is_lockup = &si_dma_is_lockup,
8c5fd7ef 1983 .vm_flush = &si_dma_vm_flush,
f93bdefe
AD		 1984 .get_rptr = &radeon_ring_generic_get_rptr,
1985 .get_wptr = &radeon_ring_generic_get_wptr,
1986 .set_wptr = &radeon_ring_generic_set_wptr,
8c5fd7ef
AD		 1987 },
1988 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1989 .ib_execute = &cayman_dma_ring_ib_execute,
cd459e52 1990 .ib_parse = &evergreen_dma_ib_parse,
8c5fd7ef
AD		 1991 .emit_fence = &evergreen_dma_fence_ring_emit,
1992 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1993 .cs_parse = NULL,
1994 .ring_test = &r600_dma_ring_test,
1995 .ib_test = &r600_dma_ib_test,
123bc183 1996 .is_lockup = &si_dma_is_lockup,
8c5fd7ef 1997 .vm_flush = &si_dma_vm_flush,
f93bdefe
AD		 1998 .get_rptr = &radeon_ring_generic_get_rptr,
1999 .get_wptr = &radeon_ring_generic_get_wptr,
2000 .set_wptr = &radeon_ring_generic_set_wptr,
f2ba57b5
CK		 2001 },
2002 [R600_RING_TYPE_UVD_INDEX] = {
2003 .ib_execute = &r600_uvd_ib_execute,
2004 .emit_fence = &r600_uvd_fence_emit,
2005 .emit_semaphore = &cayman_uvd_semaphore_emit,
2006 .cs_parse = &radeon_uvd_cs_parse,
2007 .ring_test = &r600_uvd_ring_test,
2008 .ib_test = &r600_uvd_ib_test,
2009 .is_lockup = &radeon_ring_test_lockup,
f93bdefe
AD		 2010 .get_rptr = &radeon_ring_generic_get_rptr,
2011 .get_wptr = &radeon_ring_generic_get_wptr,
2012 .set_wptr = &radeon_ring_generic_set_wptr,
02779c08
AD		 2013 }
2014 },
2015 .irq = {
2016 .set = &si_irq_set,
2017 .process = &si_irq_process,
2018 },
2019 .display = {
2020 .bandwidth_update = &dce6_bandwidth_update,
2021 .get_vblank_counter = &evergreen_get_vblank_counter,
2022 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 2023 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 2024 .get_backlight_level = &atombios_get_backlight_level,
02779c08
AD		 2025 },
2026 .copy = {
2027 .blit = NULL,
2028 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
8c5fd7ef
AD		 2029 .dma = &si_copy_dma,
2030 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 2031 .copy = &si_copy_dma,
2032 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
02779c08
AD		 2033 },
2034 .surface = {
2035 .set_reg = r600_set_surface_reg,
2036 .clear_reg = r600_clear_surface_reg,
2037 },
2038 .hpd = {
2039 .init = &evergreen_hpd_init,
2040 .fini = &evergreen_hpd_fini,
2041 .sense = &evergreen_hpd_sense,
2042 .set_polarity = &evergreen_hpd_set_polarity,
2043 },
2044 .pm = {
2045 .misc = &evergreen_pm_misc,
2046 .prepare = &evergreen_pm_prepare,
2047 .finish = &evergreen_pm_finish,
2048 .init_profile = &sumo_pm_init_profile,
2049 .get_dynpm_state = &r600_pm_get_dynpm_state,
2050 .get_engine_clock = &radeon_atom_get_engine_clock,
2051 .set_engine_clock = &radeon_atom_set_engine_clock,
2052 .get_memory_clock = &radeon_atom_get_memory_clock,
2053 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 2054 .get_pcie_lanes = &r600_get_pcie_lanes,
2055 .set_pcie_lanes = &r600_set_pcie_lanes,
02779c08 2056 .set_clock_gating = NULL,
2539eb02 2057 .set_uvd_clocks = &si_set_uvd_clocks,
6bd1c385 2058 .get_temperature = &si_get_temp,
02779c08
AD		 2059 },
2060 .pflip = {
2061 .pre_page_flip = &evergreen_pre_page_flip,
2062 .page_flip = &evergreen_page_flip,
2063 .post_page_flip = &evergreen_post_page_flip,
2064 },
2065};
2066
0672e27b
AD		 2067static struct radeon_asic ci_asic = {
2068 .init = &cik_init,
2069 .fini = &cik_fini,
2070 .suspend = &cik_suspend,
2071 .resume = &cik_resume,
2072 .asic_reset = &cik_asic_reset,
2073 .vga_set_state = &r600_vga_set_state,
2074 .ioctl_wait_idle = NULL,
2075 .gui_idle = &r600_gui_idle,
2076 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2077 .get_xclk = &cik_get_xclk,
2078 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2079 .gart = {
2080 .tlb_flush = &cik_pcie_gart_tlb_flush,
2081 .set_page = &rs600_gart_set_page,
2082 },
2083 .vm = {
2084 .init = &cik_vm_init,
2085 .fini = &cik_vm_fini,
2086 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2087 .set_page = &cik_vm_set_page,
2088 },
2089 .ring = {
2090 [RADEON_RING_TYPE_GFX_INDEX] = {
2091 .ib_execute = &cik_ring_ib_execute,
2092 .ib_parse = &cik_ib_parse,
2093 .emit_fence = &cik_fence_gfx_ring_emit,
2094 .emit_semaphore = &cik_semaphore_ring_emit,
2095 .cs_parse = NULL,
2096 .ring_test = &cik_ring_test,
2097 .ib_test = &cik_ib_test,
2098 .is_lockup = &cik_gfx_is_lockup,
2099 .vm_flush = &cik_vm_flush,
2100 .get_rptr = &radeon_ring_generic_get_rptr,
2101 .get_wptr = &radeon_ring_generic_get_wptr,
2102 .set_wptr = &radeon_ring_generic_set_wptr,
2103 },
2104 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2105 .ib_execute = &cik_ring_ib_execute,
2106 .ib_parse = &cik_ib_parse,
2107 .emit_fence = &cik_fence_compute_ring_emit,
2108 .emit_semaphore = &cik_semaphore_ring_emit,
2109 .cs_parse = NULL,
2110 .ring_test = &cik_ring_test,
2111 .ib_test = &cik_ib_test,
2112 .is_lockup = &cik_gfx_is_lockup,
2113 .vm_flush = &cik_vm_flush,
2114 .get_rptr = &cik_compute_ring_get_rptr,
2115 .get_wptr = &cik_compute_ring_get_wptr,
2116 .set_wptr = &cik_compute_ring_set_wptr,
2117 },
2118 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2119 .ib_execute = &cik_ring_ib_execute,
2120 .ib_parse = &cik_ib_parse,
2121 .emit_fence = &cik_fence_compute_ring_emit,
2122 .emit_semaphore = &cik_semaphore_ring_emit,
2123 .cs_parse = NULL,
2124 .ring_test = &cik_ring_test,
2125 .ib_test = &cik_ib_test,
2126 .is_lockup = &cik_gfx_is_lockup,
2127 .vm_flush = &cik_vm_flush,
2128 .get_rptr = &cik_compute_ring_get_rptr,
2129 .get_wptr = &cik_compute_ring_get_wptr,
2130 .set_wptr = &cik_compute_ring_set_wptr,
2131 },
2132 [R600_RING_TYPE_DMA_INDEX] = {
2133 .ib_execute = &cik_sdma_ring_ib_execute,
2134 .ib_parse = &cik_ib_parse,
2135 .emit_fence = &cik_sdma_fence_ring_emit,
2136 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2137 .cs_parse = NULL,
2138 .ring_test = &cik_sdma_ring_test,
2139 .ib_test = &cik_sdma_ib_test,
2140 .is_lockup = &cik_sdma_is_lockup,
2141 .vm_flush = &cik_dma_vm_flush,
2142 .get_rptr = &radeon_ring_generic_get_rptr,
2143 .get_wptr = &radeon_ring_generic_get_wptr,
2144 .set_wptr = &radeon_ring_generic_set_wptr,
2145 },
2146 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2147 .ib_execute = &cik_sdma_ring_ib_execute,
2148 .ib_parse = &cik_ib_parse,
2149 .emit_fence = &cik_sdma_fence_ring_emit,
2150 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2151 .cs_parse = NULL,
2152 .ring_test = &cik_sdma_ring_test,
2153 .ib_test = &cik_sdma_ib_test,
2154 .is_lockup = &cik_sdma_is_lockup,
2155 .vm_flush = &cik_dma_vm_flush,
2156 .get_rptr = &radeon_ring_generic_get_rptr,
2157 .get_wptr = &radeon_ring_generic_get_wptr,
2158 .set_wptr = &radeon_ring_generic_set_wptr,
2159 },
2160 [R600_RING_TYPE_UVD_INDEX] = {
2161 .ib_execute = &r600_uvd_ib_execute,
2162 .emit_fence = &r600_uvd_fence_emit,
2163 .emit_semaphore = &cayman_uvd_semaphore_emit,
2164 .cs_parse = &radeon_uvd_cs_parse,
2165 .ring_test = &r600_uvd_ring_test,
2166 .ib_test = &r600_uvd_ib_test,
2167 .is_lockup = &radeon_ring_test_lockup,
2168 .get_rptr = &radeon_ring_generic_get_rptr,
2169 .get_wptr = &radeon_ring_generic_get_wptr,
2170 .set_wptr = &radeon_ring_generic_set_wptr,
2171 }
2172 },
2173 .irq = {
2174 .set = &cik_irq_set,
2175 .process = &cik_irq_process,
2176 },
2177 .display = {
2178 .bandwidth_update = &dce8_bandwidth_update,
2179 .get_vblank_counter = &evergreen_get_vblank_counter,
2180 .wait_for_vblank = &dce4_wait_for_vblank,
2181 },
2182 .copy = {
2183 .blit = NULL,
2184 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2185 .dma = &cik_copy_dma,
2186 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2187 .copy = &cik_copy_dma,
2188 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2189 },
2190 .surface = {
2191 .set_reg = r600_set_surface_reg,
2192 .clear_reg = r600_clear_surface_reg,
2193 },
2194 .hpd = {
2195 .init = &evergreen_hpd_init,
2196 .fini = &evergreen_hpd_fini,
2197 .sense = &evergreen_hpd_sense,
2198 .set_polarity = &evergreen_hpd_set_polarity,
2199 },
2200 .pm = {
2201 .misc = &evergreen_pm_misc,
2202 .prepare = &evergreen_pm_prepare,
2203 .finish = &evergreen_pm_finish,
2204 .init_profile = &sumo_pm_init_profile,
2205 .get_dynpm_state = &r600_pm_get_dynpm_state,
2206 .get_engine_clock = &radeon_atom_get_engine_clock,
2207 .set_engine_clock = &radeon_atom_set_engine_clock,
2208 .get_memory_clock = &radeon_atom_get_memory_clock,
2209 .set_memory_clock = &radeon_atom_set_memory_clock,
2210 .get_pcie_lanes = NULL,
2211 .set_pcie_lanes = NULL,
2212 .set_clock_gating = NULL,
2213 .set_uvd_clocks = &cik_set_uvd_clocks,
2214 },
2215 .pflip = {
2216 .pre_page_flip = &evergreen_pre_page_flip,
2217 .page_flip = &evergreen_page_flip,
2218 .post_page_flip = &evergreen_post_page_flip,
2219 },
2220};
2221
2222static struct radeon_asic kv_asic = {
2223 .init = &cik_init,
2224 .fini = &cik_fini,
2225 .suspend = &cik_suspend,
2226 .resume = &cik_resume,
2227 .asic_reset = &cik_asic_reset,
2228 .vga_set_state = &r600_vga_set_state,
2229 .ioctl_wait_idle = NULL,
2230 .gui_idle = &r600_gui_idle,
2231 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2232 .get_xclk = &cik_get_xclk,
2233 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2234 .gart = {
2235 .tlb_flush = &cik_pcie_gart_tlb_flush,
2236 .set_page = &rs600_gart_set_page,
2237 },
2238 .vm = {
2239 .init = &cik_vm_init,
2240 .fini = &cik_vm_fini,
2241 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2242 .set_page = &cik_vm_set_page,
2243 },
2244 .ring = {
2245 [RADEON_RING_TYPE_GFX_INDEX] = {
2246 .ib_execute = &cik_ring_ib_execute,
2247 .ib_parse = &cik_ib_parse,
2248 .emit_fence = &cik_fence_gfx_ring_emit,
2249 .emit_semaphore = &cik_semaphore_ring_emit,
2250 .cs_parse = NULL,
2251 .ring_test = &cik_ring_test,
2252 .ib_test = &cik_ib_test,
2253 .is_lockup = &cik_gfx_is_lockup,
2254 .vm_flush = &cik_vm_flush,
2255 .get_rptr = &radeon_ring_generic_get_rptr,
2256 .get_wptr = &radeon_ring_generic_get_wptr,
2257 .set_wptr = &radeon_ring_generic_set_wptr,
2258 },
2259 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2260 .ib_execute = &cik_ring_ib_execute,
2261 .ib_parse = &cik_ib_parse,
2262 .emit_fence = &cik_fence_compute_ring_emit,
2263 .emit_semaphore = &cik_semaphore_ring_emit,
2264 .cs_parse = NULL,
2265 .ring_test = &cik_ring_test,
2266 .ib_test = &cik_ib_test,
2267 .is_lockup = &cik_gfx_is_lockup,
2268 .vm_flush = &cik_vm_flush,
2269 .get_rptr = &cik_compute_ring_get_rptr,
2270 .get_wptr = &cik_compute_ring_get_wptr,
2271 .set_wptr = &cik_compute_ring_set_wptr,
2272 },
2273 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2274 .ib_execute = &cik_ring_ib_execute,
2275 .ib_parse = &cik_ib_parse,
2276 .emit_fence = &cik_fence_compute_ring_emit,
2277 .emit_semaphore = &cik_semaphore_ring_emit,
2278 .cs_parse = NULL,
2279 .ring_test = &cik_ring_test,
2280 .ib_test = &cik_ib_test,
2281 .is_lockup = &cik_gfx_is_lockup,
2282 .vm_flush = &cik_vm_flush,
2283 .get_rptr = &cik_compute_ring_get_rptr,
2284 .get_wptr = &cik_compute_ring_get_wptr,
2285 .set_wptr = &cik_compute_ring_set_wptr,
2286 },
2287 [R600_RING_TYPE_DMA_INDEX] = {
2288 .ib_execute = &cik_sdma_ring_ib_execute,
2289 .ib_parse = &cik_ib_parse,
2290 .emit_fence = &cik_sdma_fence_ring_emit,
2291 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2292 .cs_parse = NULL,
2293 .ring_test = &cik_sdma_ring_test,
2294 .ib_test = &cik_sdma_ib_test,
2295 .is_lockup = &cik_sdma_is_lockup,
2296 .vm_flush = &cik_dma_vm_flush,
2297 .get_rptr = &radeon_ring_generic_get_rptr,
2298 .get_wptr = &radeon_ring_generic_get_wptr,
2299 .set_wptr = &radeon_ring_generic_set_wptr,
2300 },
2301 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2302 .ib_execute = &cik_sdma_ring_ib_execute,
2303 .ib_parse = &cik_ib_parse,
2304 .emit_fence = &cik_sdma_fence_ring_emit,
2305 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2306 .cs_parse = NULL,
2307 .ring_test = &cik_sdma_ring_test,
2308 .ib_test = &cik_sdma_ib_test,
2309 .is_lockup = &cik_sdma_is_lockup,
2310 .vm_flush = &cik_dma_vm_flush,
2311 .get_rptr = &radeon_ring_generic_get_rptr,
2312 .get_wptr = &radeon_ring_generic_get_wptr,
2313 .set_wptr = &radeon_ring_generic_set_wptr,
2314 },
2315 [R600_RING_TYPE_UVD_INDEX] = {
2316 .ib_execute = &r600_uvd_ib_execute,
2317 .emit_fence = &r600_uvd_fence_emit,
2318 .emit_semaphore = &cayman_uvd_semaphore_emit,
2319 .cs_parse = &radeon_uvd_cs_parse,
2320 .ring_test = &r600_uvd_ring_test,
2321 .ib_test = &r600_uvd_ib_test,
2322 .is_lockup = &radeon_ring_test_lockup,
2323 .get_rptr = &radeon_ring_generic_get_rptr,
2324 .get_wptr = &radeon_ring_generic_get_wptr,
2325 .set_wptr = &radeon_ring_generic_set_wptr,
2326 }
2327 },
2328 .irq = {
2329 .set = &cik_irq_set,
2330 .process = &cik_irq_process,
2331 },
2332 .display = {
2333 .bandwidth_update = &dce8_bandwidth_update,
2334 .get_vblank_counter = &evergreen_get_vblank_counter,
2335 .wait_for_vblank = &dce4_wait_for_vblank,
2336 },
2337 .copy = {
2338 .blit = NULL,
2339 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2340 .dma = &cik_copy_dma,
2341 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2342 .copy = &cik_copy_dma,
2343 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2344 },
2345 .surface = {
2346 .set_reg = r600_set_surface_reg,
2347 .clear_reg = r600_clear_surface_reg,
2348 },
2349 .hpd = {
2350 .init = &evergreen_hpd_init,
2351 .fini = &evergreen_hpd_fini,
2352 .sense = &evergreen_hpd_sense,
2353 .set_polarity = &evergreen_hpd_set_polarity,
2354 },
2355 .pm = {
2356 .misc = &evergreen_pm_misc,
2357 .prepare = &evergreen_pm_prepare,
2358 .finish = &evergreen_pm_finish,
2359 .init_profile = &sumo_pm_init_profile,
2360 .get_dynpm_state = &r600_pm_get_dynpm_state,
2361 .get_engine_clock = &radeon_atom_get_engine_clock,
2362 .set_engine_clock = &radeon_atom_set_engine_clock,
2363 .get_memory_clock = &radeon_atom_get_memory_clock,
2364 .set_memory_clock = &radeon_atom_set_memory_clock,
2365 .get_pcie_lanes = NULL,
2366 .set_pcie_lanes = NULL,
2367 .set_clock_gating = NULL,
2368 .set_uvd_clocks = &cik_set_uvd_clocks,
2369 },
2370 .pflip = {
2371 .pre_page_flip = &evergreen_pre_page_flip,
2372 .page_flip = &evergreen_page_flip,
2373 .post_page_flip = &evergreen_post_page_flip,
2374 },
2375};
2376
abf1dc67
AD		 2377/**
2378 * radeon_asic_init - register asic specific callbacks
2379 *
2380 * @rdev: radeon device pointer
2381 *
2382 * Registers the appropriate asic specific callbacks for each
2383 * chip family. Also sets other asics specific info like the number
2384 * of crtcs and the register aperture accessors (all asics).
2385 * Returns 0 for success.
2386 */
0a10c851
DV		 2387int radeon_asic_init(struct radeon_device *rdev)
2388{
2389 radeon_register_accessor_init(rdev);
ba7e05e9
AD		 2390
2391 /* set the number of crtcs */
2392 if (rdev->flags & RADEON_SINGLE_CRTC)
2393 rdev->num_crtc = 1;
2394 else
2395 rdev->num_crtc = 2;
2396
948bee3f
AD		 2397 rdev->has_uvd = false;
2398
0a10c851
DV		 2399 switch (rdev->family) {
2400 case CHIP_R100:
2401 case CHIP_RV100:
2402 case CHIP_RS100:
2403 case CHIP_RV200:
2404 case CHIP_RS200:
2405 rdev->asic = &r100_asic;
2406 break;
2407 case CHIP_R200:
2408 case CHIP_RV250:
2409 case CHIP_RS300:
2410 case CHIP_RV280:
2411 rdev->asic = &r200_asic;
2412 break;
2413 case CHIP_R300:
2414 case CHIP_R350:
2415 case CHIP_RV350:
2416 case CHIP_RV380:
2417 if (rdev->flags & RADEON_IS_PCIE)
2418 rdev->asic = &r300_asic_pcie;
2419 else
2420 rdev->asic = &r300_asic;
2421 break;
2422 case CHIP_R420:
2423 case CHIP_R423:
2424 case CHIP_RV410:
2425 rdev->asic = &r420_asic;
07bb084c
AD		 2426 /* handle macs */
2427 if (rdev->bios == NULL) {
798bcf73
AD		 2428 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2429 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2430 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2431 rdev->asic->pm.set_memory_clock = NULL;
37e9b6a6 2432 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
07bb084c 2433 }
0a10c851
DV		 2434 break;
2435 case CHIP_RS400:
2436 case CHIP_RS480:
2437 rdev->asic = &rs400_asic;
2438 break;
2439 case CHIP_RS600:
2440 rdev->asic = &rs600_asic;
2441 break;
2442 case CHIP_RS690:
2443 case CHIP_RS740:
2444 rdev->asic = &rs690_asic;
2445 break;
2446 case CHIP_RV515:
2447 rdev->asic = &rv515_asic;
2448 break;
2449 case CHIP_R520:
2450 case CHIP_RV530:
2451 case CHIP_RV560:
2452 case CHIP_RV570:
2453 case CHIP_R580:
2454 rdev->asic = &r520_asic;
2455 break;
2456 case CHIP_R600:
2457 case CHIP_RV610:
2458 case CHIP_RV630:
2459 case CHIP_RV620:
2460 case CHIP_RV635:
2461 case CHIP_RV670:
f47299c5 2462 rdev->asic = &r600_asic;
948bee3f
AD		 2463 if (rdev->family == CHIP_R600)
2464 rdev->has_uvd = false;
2465 else
2466 rdev->has_uvd = true;
f47299c5 2467 break;
0a10c851
DV		 2468 case CHIP_RS780:
2469 case CHIP_RS880:
f47299c5 2470 rdev->asic = &rs780_asic;
948bee3f 2471 rdev->has_uvd = true;
0a10c851
DV		 2472 break;
2473 case CHIP_RV770:
2474 case CHIP_RV730:
2475 case CHIP_RV710:
2476 case CHIP_RV740:
2477 rdev->asic = &rv770_asic;
948bee3f 2478 rdev->has_uvd = true;
0a10c851
DV		 2479 break;
2480 case CHIP_CEDAR:
2481 case CHIP_REDWOOD:
2482 case CHIP_JUNIPER:
2483 case CHIP_CYPRESS:
2484 case CHIP_HEMLOCK:
ba7e05e9
AD		 2485 /* set num crtcs */
2486 if (rdev->family == CHIP_CEDAR)
2487 rdev->num_crtc = 4;
2488 else
2489 rdev->num_crtc = 6;
0a10c851 2490 rdev->asic = &evergreen_asic;
948bee3f 2491 rdev->has_uvd = true;
0a10c851 2492 break;
958261d1 2493 case CHIP_PALM:
89da5a37
AD		 2494 case CHIP_SUMO:
2495 case CHIP_SUMO2:
958261d1 2496 rdev->asic = &sumo_asic;
948bee3f 2497 rdev->has_uvd = true;
958261d1 2498 break;
a43b7665
AD		 2499 case CHIP_BARTS:
2500 case CHIP_TURKS:
2501 case CHIP_CAICOS:
ba7e05e9
AD		 2502 /* set num crtcs */
2503 if (rdev->family == CHIP_CAICOS)
2504 rdev->num_crtc = 4;
2505 else
2506 rdev->num_crtc = 6;
a43b7665 2507 rdev->asic = &btc_asic;
948bee3f 2508 rdev->has_uvd = true;
a43b7665 2509 break;
e3487629
AD		 2510 case CHIP_CAYMAN:
2511 rdev->asic = &cayman_asic;
ba7e05e9
AD		 2512 /* set num crtcs */
2513 rdev->num_crtc = 6;
948bee3f 2514 rdev->has_uvd = true;
e3487629 2515 break;
be63fe8c
AD		 2516 case CHIP_ARUBA:
2517 rdev->asic = &trinity_asic;
2518 /* set num crtcs */
2519 rdev->num_crtc = 4;
948bee3f 2520 rdev->has_uvd = true;
be63fe8c 2521 break;
02779c08
AD		 2522 case CHIP_TAHITI:
2523 case CHIP_PITCAIRN:
2524 case CHIP_VERDE:
e737a14c 2525 case CHIP_OLAND:
86a45cac 2526 case CHIP_HAINAN:
02779c08
AD		 2527 rdev->asic = &si_asic;
2528 /* set num crtcs */
86a45cac
AD		 2529 if (rdev->family == CHIP_HAINAN)
2530 rdev->num_crtc = 0;
2531 else if (rdev->family == CHIP_OLAND)
e737a14c
AD		 2532 rdev->num_crtc = 2;
2533 else
2534 rdev->num_crtc = 6;
948bee3f
AD		 2535 if (rdev->family == CHIP_HAINAN)
2536 rdev->has_uvd = false;
2537 else
2538 rdev->has_uvd = true;
02779c08 2539 break;
0672e27b
AD		 2540 case CHIP_BONAIRE:
2541 rdev->asic = &ci_asic;
2542 rdev->num_crtc = 6;
2543 break;
2544 case CHIP_KAVERI:
2545 case CHIP_KABINI:
2546 rdev->asic = &kv_asic;
2547 /* set num crtcs */
2548 if (rdev->family == CHIP_KAVERI)
2549 rdev->num_crtc = 4;
2550 else
2551 rdev->num_crtc = 2;
2552 break;
0a10c851
DV		 2553 default:
2554 /* FIXME: not supported yet */
2555 return -EINVAL;
2556 }
2557
2558 if (rdev->flags & RADEON_IS_IGP) {
798bcf73
AD		 2559 rdev->asic->pm.get_memory_clock = NULL;
2560 rdev->asic->pm.set_memory_clock = NULL;
0a10c851
DV		 2561 }
2562
2563 return 0;
2564}
2565
Linux kernel - Deliverables
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