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drm/radeon/dpm: add debugfs support for 7xx/evergreen/btc
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_asic.c
CommitLineData
0a10c851
DV		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/console.h>
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/radeon_drm.h>
33#include <linux/vgaarb.h>
34#include <linux/vga_switcheroo.h>
35#include "radeon_reg.h"
36#include "radeon.h"
37#include "radeon_asic.h"
38#include "atom.h"
39
40/*
41 * Registers accessors functions.
42 */
abf1dc67
AD		 43/**
44 * radeon_invalid_rreg - dummy reg read function
45 *
46 * @rdev: radeon device pointer
47 * @reg: offset of register
48 *
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
52 */
0a10c851
DV		 53static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54{
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
56 BUG_ON(1);
57 return 0;
58}
59
abf1dc67
AD		 60/**
61 * radeon_invalid_wreg - dummy reg write function
62 *
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
66 *
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
69 */
0a10c851
DV		 70static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
71{
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
73 reg, v);
74 BUG_ON(1);
75}
76
abf1dc67
AD		 77/**
78 * radeon_register_accessor_init - sets up the register accessor callbacks
79 *
80 * @rdev: radeon device pointer
81 *
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
84 */
0a10c851
DV		 85static void radeon_register_accessor_init(struct radeon_device *rdev)
86{
87 rdev->mc_rreg = &radeon_invalid_rreg;
88 rdev->mc_wreg = &radeon_invalid_wreg;
89 rdev->pll_rreg = &radeon_invalid_rreg;
90 rdev->pll_wreg = &radeon_invalid_wreg;
91 rdev->pciep_rreg = &radeon_invalid_rreg;
92 rdev->pciep_wreg = &radeon_invalid_wreg;
93
94 /* Don't change order as we are overridding accessor. */
95 if (rdev->family < CHIP_RV515) {
96 rdev->pcie_reg_mask = 0xff;
97 } else {
98 rdev->pcie_reg_mask = 0x7ff;
99 }
100 /* FIXME: not sure here */
101 if (rdev->family <= CHIP_R580) {
102 rdev->pll_rreg = &r100_pll_rreg;
103 rdev->pll_wreg = &r100_pll_wreg;
104 }
105 if (rdev->family >= CHIP_R420) {
106 rdev->mc_rreg = &r420_mc_rreg;
107 rdev->mc_wreg = &r420_mc_wreg;
108 }
109 if (rdev->family >= CHIP_RV515) {
110 rdev->mc_rreg = &rv515_mc_rreg;
111 rdev->mc_wreg = &rv515_mc_wreg;
112 }
113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
114 rdev->mc_rreg = &rs400_mc_rreg;
115 rdev->mc_wreg = &rs400_mc_wreg;
116 }
117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
118 rdev->mc_rreg = &rs690_mc_rreg;
119 rdev->mc_wreg = &rs690_mc_wreg;
120 }
121 if (rdev->family == CHIP_RS600) {
122 rdev->mc_rreg = &rs600_mc_rreg;
123 rdev->mc_wreg = &rs600_mc_wreg;
124 }
65337e60
SL		 125 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
126 rdev->mc_rreg = &rs780_mc_rreg;
127 rdev->mc_wreg = &rs780_mc_wreg;
128 }
6e2c3c0a
AD		 129
130 if (rdev->family >= CHIP_BONAIRE) {
131 rdev->pciep_rreg = &cik_pciep_rreg;
132 rdev->pciep_wreg = &cik_pciep_wreg;
133 } else if (rdev->family >= CHIP_R600) {
0a10c851
DV		 134 rdev->pciep_rreg = &r600_pciep_rreg;
135 rdev->pciep_wreg = &r600_pciep_wreg;
136 }
137}
138
139
140/* helper to disable agp */
abf1dc67
AD		 141/**
142 * radeon_agp_disable - AGP disable helper function
143 *
144 * @rdev: radeon device pointer
145 *
146 * Removes AGP flags and changes the gart callbacks on AGP
147 * cards when using the internal gart rather than AGP (all asics).
148 */
0a10c851
DV		 149void radeon_agp_disable(struct radeon_device *rdev)
150{
151 rdev->flags &= ~RADEON_IS_AGP;
152 if (rdev->family >= CHIP_R600) {
153 DRM_INFO("Forcing AGP to PCIE mode\n");
154 rdev->flags |= RADEON_IS_PCIE;
155 } else if (rdev->family >= CHIP_RV515 ||
156 rdev->family == CHIP_RV380 ||
157 rdev->family == CHIP_RV410 ||
158 rdev->family == CHIP_R423) {
159 DRM_INFO("Forcing AGP to PCIE mode\n");
160 rdev->flags |= RADEON_IS_PCIE;
c5b3b850
AD		 161 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
162 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
0a10c851
DV		 163 } else {
164 DRM_INFO("Forcing AGP to PCI mode\n");
165 rdev->flags |= RADEON_IS_PCI;
c5b3b850
AD		 166 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
167 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
0a10c851
DV		 168 }
169 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
170}
171
172/*
173 * ASIC
174 */
48e7a5f1
DV		 175static struct radeon_asic r100_asic = {
176 .init = &r100_init,
177 .fini = &r100_fini,
178 .suspend = &r100_suspend,
179 .resume = &r100_resume,
180 .vga_set_state = &r100_vga_set_state,
a2d07b74 181 .asic_reset = &r100_asic_reset,
54e88e06
AD		 182 .ioctl_wait_idle = NULL,
183 .gui_idle = &r100_gui_idle,
184 .mc_wait_for_idle = &r100_mc_wait_for_idle,
c5b3b850
AD		 185 .gart = {
186 .tlb_flush = &r100_pci_gart_tlb_flush,
187 .set_page = &r100_pci_gart_set_page,
188 },
4c87bc26
CK		 189 .ring = {
190 [RADEON_RING_TYPE_GFX_INDEX] = {
191 .ib_execute = &r100_ring_ib_execute,
192 .emit_fence = &r100_fence_ring_emit,
193 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 194 .cs_parse = &r100_cs_parse,
f712812e
AD		 195 .ring_start = &r100_ring_start,
196 .ring_test = &r100_ring_test,
197 .ib_test = &r100_ib_test,
312c4a8c 198 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 199 .get_rptr = &radeon_ring_generic_get_rptr,
200 .get_wptr = &radeon_ring_generic_get_wptr,
201 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 202 }
203 },
b35ea4ab
AD		 204 .irq = {
205 .set = &r100_irq_set,
206 .process = &r100_irq_process,
207 },
c79a49ca
AD		 208 .display = {
209 .bandwidth_update = &r100_bandwidth_update,
210 .get_vblank_counter = &r100_get_vblank_counter,
211 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 212 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 213 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 214 },
27cd7769
AD		 215 .copy = {
216 .blit = &r100_copy_blit,
217 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
218 .dma = NULL,
219 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
220 .copy = &r100_copy_blit,
221 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
222 },
9e6f3d02
AD		 223 .surface = {
224 .set_reg = r100_set_surface_reg,
225 .clear_reg = r100_clear_surface_reg,
226 },
901ea57d
AD		 227 .hpd = {
228 .init = &r100_hpd_init,
229 .fini = &r100_hpd_fini,
230 .sense = &r100_hpd_sense,
231 .set_polarity = &r100_hpd_set_polarity,
232 },
a02fa397
AD		 233 .pm = {
234 .misc = &r100_pm_misc,
235 .prepare = &r100_pm_prepare,
236 .finish = &r100_pm_finish,
237 .init_profile = &r100_pm_init_profile,
238 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 239 .get_engine_clock = &radeon_legacy_get_engine_clock,
240 .set_engine_clock = &radeon_legacy_set_engine_clock,
241 .get_memory_clock = &radeon_legacy_get_memory_clock,
242 .set_memory_clock = NULL,
243 .get_pcie_lanes = NULL,
244 .set_pcie_lanes = NULL,
245 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 246 },
0f9e006c
AD		 247 .pflip = {
248 .pre_page_flip = &r100_pre_page_flip,
249 .page_flip = &r100_page_flip,
250 .post_page_flip = &r100_post_page_flip,
251 },
48e7a5f1
DV		 252};
253
254static struct radeon_asic r200_asic = {
255 .init = &r100_init,
256 .fini = &r100_fini,
257 .suspend = &r100_suspend,
258 .resume = &r100_resume,
259 .vga_set_state = &r100_vga_set_state,
a2d07b74 260 .asic_reset = &r100_asic_reset,
54e88e06
AD		 261 .ioctl_wait_idle = NULL,
262 .gui_idle = &r100_gui_idle,
263 .mc_wait_for_idle = &r100_mc_wait_for_idle,
c5b3b850
AD		 264 .gart = {
265 .tlb_flush = &r100_pci_gart_tlb_flush,
266 .set_page = &r100_pci_gart_set_page,
267 },
4c87bc26
CK		 268 .ring = {
269 [RADEON_RING_TYPE_GFX_INDEX] = {
270 .ib_execute = &r100_ring_ib_execute,
271 .emit_fence = &r100_fence_ring_emit,
272 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 273 .cs_parse = &r100_cs_parse,
f712812e
AD		 274 .ring_start = &r100_ring_start,
275 .ring_test = &r100_ring_test,
276 .ib_test = &r100_ib_test,
312c4a8c 277 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 278 .get_rptr = &radeon_ring_generic_get_rptr,
279 .get_wptr = &radeon_ring_generic_get_wptr,
280 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 281 }
282 },
b35ea4ab
AD		 283 .irq = {
284 .set = &r100_irq_set,
285 .process = &r100_irq_process,
286 },
c79a49ca
AD		 287 .display = {
288 .bandwidth_update = &r100_bandwidth_update,
289 .get_vblank_counter = &r100_get_vblank_counter,
290 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 291 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 292 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 293 },
27cd7769
AD		 294 .copy = {
295 .blit = &r100_copy_blit,
296 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
297 .dma = &r200_copy_dma,
298 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
299 .copy = &r100_copy_blit,
300 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
301 },
9e6f3d02
AD		 302 .surface = {
303 .set_reg = r100_set_surface_reg,
304 .clear_reg = r100_clear_surface_reg,
305 },
901ea57d
AD		 306 .hpd = {
307 .init = &r100_hpd_init,
308 .fini = &r100_hpd_fini,
309 .sense = &r100_hpd_sense,
310 .set_polarity = &r100_hpd_set_polarity,
311 },
a02fa397
AD		 312 .pm = {
313 .misc = &r100_pm_misc,
314 .prepare = &r100_pm_prepare,
315 .finish = &r100_pm_finish,
316 .init_profile = &r100_pm_init_profile,
317 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 318 .get_engine_clock = &radeon_legacy_get_engine_clock,
319 .set_engine_clock = &radeon_legacy_set_engine_clock,
320 .get_memory_clock = &radeon_legacy_get_memory_clock,
321 .set_memory_clock = NULL,
322 .get_pcie_lanes = NULL,
323 .set_pcie_lanes = NULL,
324 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 325 },
0f9e006c
AD		 326 .pflip = {
327 .pre_page_flip = &r100_pre_page_flip,
328 .page_flip = &r100_page_flip,
329 .post_page_flip = &r100_post_page_flip,
330 },
48e7a5f1
DV		 331};
332
333static struct radeon_asic r300_asic = {
334 .init = &r300_init,
335 .fini = &r300_fini,
336 .suspend = &r300_suspend,
337 .resume = &r300_resume,
338 .vga_set_state = &r100_vga_set_state,
a2d07b74 339 .asic_reset = &r300_asic_reset,
54e88e06
AD		 340 .ioctl_wait_idle = NULL,
341 .gui_idle = &r100_gui_idle,
342 .mc_wait_for_idle = &r300_mc_wait_for_idle,
c5b3b850
AD		 343 .gart = {
344 .tlb_flush = &r100_pci_gart_tlb_flush,
345 .set_page = &r100_pci_gart_set_page,
346 },
4c87bc26
CK		 347 .ring = {
348 [RADEON_RING_TYPE_GFX_INDEX] = {
349 .ib_execute = &r100_ring_ib_execute,
350 .emit_fence = &r300_fence_ring_emit,
351 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 352 .cs_parse = &r300_cs_parse,
f712812e
AD		 353 .ring_start = &r300_ring_start,
354 .ring_test = &r100_ring_test,
355 .ib_test = &r100_ib_test,
8ba957b5 356 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 357 .get_rptr = &radeon_ring_generic_get_rptr,
358 .get_wptr = &radeon_ring_generic_get_wptr,
359 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 360 }
361 },
b35ea4ab
AD		 362 .irq = {
363 .set = &r100_irq_set,
364 .process = &r100_irq_process,
365 },
c79a49ca
AD		 366 .display = {
367 .bandwidth_update = &r100_bandwidth_update,
368 .get_vblank_counter = &r100_get_vblank_counter,
369 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 370 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 371 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 372 },
27cd7769
AD		 373 .copy = {
374 .blit = &r100_copy_blit,
375 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
376 .dma = &r200_copy_dma,
377 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
378 .copy = &r100_copy_blit,
379 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
380 },
9e6f3d02
AD		 381 .surface = {
382 .set_reg = r100_set_surface_reg,
383 .clear_reg = r100_clear_surface_reg,
384 },
901ea57d
AD		 385 .hpd = {
386 .init = &r100_hpd_init,
387 .fini = &r100_hpd_fini,
388 .sense = &r100_hpd_sense,
389 .set_polarity = &r100_hpd_set_polarity,
390 },
a02fa397
AD		 391 .pm = {
392 .misc = &r100_pm_misc,
393 .prepare = &r100_pm_prepare,
394 .finish = &r100_pm_finish,
395 .init_profile = &r100_pm_init_profile,
396 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 397 .get_engine_clock = &radeon_legacy_get_engine_clock,
398 .set_engine_clock = &radeon_legacy_set_engine_clock,
399 .get_memory_clock = &radeon_legacy_get_memory_clock,
400 .set_memory_clock = NULL,
401 .get_pcie_lanes = &rv370_get_pcie_lanes,
402 .set_pcie_lanes = &rv370_set_pcie_lanes,
403 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 404 },
0f9e006c
AD		 405 .pflip = {
406 .pre_page_flip = &r100_pre_page_flip,
407 .page_flip = &r100_page_flip,
408 .post_page_flip = &r100_post_page_flip,
409 },
48e7a5f1
DV		 410};
411
412static struct radeon_asic r300_asic_pcie = {
413 .init = &r300_init,
414 .fini = &r300_fini,
415 .suspend = &r300_suspend,
416 .resume = &r300_resume,
417 .vga_set_state = &r100_vga_set_state,
a2d07b74 418 .asic_reset = &r300_asic_reset,
54e88e06
AD		 419 .ioctl_wait_idle = NULL,
420 .gui_idle = &r100_gui_idle,
421 .mc_wait_for_idle = &r300_mc_wait_for_idle,
c5b3b850
AD		 422 .gart = {
423 .tlb_flush = &rv370_pcie_gart_tlb_flush,
424 .set_page = &rv370_pcie_gart_set_page,
425 },
4c87bc26
CK		 426 .ring = {
427 [RADEON_RING_TYPE_GFX_INDEX] = {
428 .ib_execute = &r100_ring_ib_execute,
429 .emit_fence = &r300_fence_ring_emit,
430 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 431 .cs_parse = &r300_cs_parse,
f712812e
AD		 432 .ring_start = &r300_ring_start,
433 .ring_test = &r100_ring_test,
434 .ib_test = &r100_ib_test,
8ba957b5 435 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 436 .get_rptr = &radeon_ring_generic_get_rptr,
437 .get_wptr = &radeon_ring_generic_get_wptr,
438 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 439 }
440 },
b35ea4ab
AD		 441 .irq = {
442 .set = &r100_irq_set,
443 .process = &r100_irq_process,
444 },
c79a49ca
AD		 445 .display = {
446 .bandwidth_update = &r100_bandwidth_update,
447 .get_vblank_counter = &r100_get_vblank_counter,
448 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 449 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 450 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 451 },
27cd7769
AD		 452 .copy = {
453 .blit = &r100_copy_blit,
454 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
455 .dma = &r200_copy_dma,
456 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
457 .copy = &r100_copy_blit,
458 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
459 },
9e6f3d02
AD		 460 .surface = {
461 .set_reg = r100_set_surface_reg,
462 .clear_reg = r100_clear_surface_reg,
463 },
901ea57d
AD		 464 .hpd = {
465 .init = &r100_hpd_init,
466 .fini = &r100_hpd_fini,
467 .sense = &r100_hpd_sense,
468 .set_polarity = &r100_hpd_set_polarity,
469 },
a02fa397
AD		 470 .pm = {
471 .misc = &r100_pm_misc,
472 .prepare = &r100_pm_prepare,
473 .finish = &r100_pm_finish,
474 .init_profile = &r100_pm_init_profile,
475 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 476 .get_engine_clock = &radeon_legacy_get_engine_clock,
477 .set_engine_clock = &radeon_legacy_set_engine_clock,
478 .get_memory_clock = &radeon_legacy_get_memory_clock,
479 .set_memory_clock = NULL,
480 .get_pcie_lanes = &rv370_get_pcie_lanes,
481 .set_pcie_lanes = &rv370_set_pcie_lanes,
482 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 483 },
0f9e006c
AD		 484 .pflip = {
485 .pre_page_flip = &r100_pre_page_flip,
486 .page_flip = &r100_page_flip,
487 .post_page_flip = &r100_post_page_flip,
488 },
48e7a5f1
DV		 489};
490
491static struct radeon_asic r420_asic = {
492 .init = &r420_init,
493 .fini = &r420_fini,
494 .suspend = &r420_suspend,
495 .resume = &r420_resume,
496 .vga_set_state = &r100_vga_set_state,
a2d07b74 497 .asic_reset = &r300_asic_reset,
54e88e06
AD		 498 .ioctl_wait_idle = NULL,
499 .gui_idle = &r100_gui_idle,
500 .mc_wait_for_idle = &r300_mc_wait_for_idle,
c5b3b850
AD		 501 .gart = {
502 .tlb_flush = &rv370_pcie_gart_tlb_flush,
503 .set_page = &rv370_pcie_gart_set_page,
504 },
4c87bc26
CK		 505 .ring = {
506 [RADEON_RING_TYPE_GFX_INDEX] = {
507 .ib_execute = &r100_ring_ib_execute,
508 .emit_fence = &r300_fence_ring_emit,
509 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 510 .cs_parse = &r300_cs_parse,
f712812e
AD		 511 .ring_start = &r300_ring_start,
512 .ring_test = &r100_ring_test,
513 .ib_test = &r100_ib_test,
8ba957b5 514 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 515 .get_rptr = &radeon_ring_generic_get_rptr,
516 .get_wptr = &radeon_ring_generic_get_wptr,
517 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 518 }
519 },
b35ea4ab
AD		 520 .irq = {
521 .set = &r100_irq_set,
522 .process = &r100_irq_process,
523 },
c79a49ca
AD		 524 .display = {
525 .bandwidth_update = &r100_bandwidth_update,
526 .get_vblank_counter = &r100_get_vblank_counter,
527 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 528 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 529 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 530 },
27cd7769
AD		 531 .copy = {
532 .blit = &r100_copy_blit,
533 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
534 .dma = &r200_copy_dma,
535 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
536 .copy = &r100_copy_blit,
537 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
538 },
9e6f3d02
AD		 539 .surface = {
540 .set_reg = r100_set_surface_reg,
541 .clear_reg = r100_clear_surface_reg,
542 },
901ea57d
AD		 543 .hpd = {
544 .init = &r100_hpd_init,
545 .fini = &r100_hpd_fini,
546 .sense = &r100_hpd_sense,
547 .set_polarity = &r100_hpd_set_polarity,
548 },
a02fa397
AD		 549 .pm = {
550 .misc = &r100_pm_misc,
551 .prepare = &r100_pm_prepare,
552 .finish = &r100_pm_finish,
553 .init_profile = &r420_pm_init_profile,
554 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 555 .get_engine_clock = &radeon_atom_get_engine_clock,
556 .set_engine_clock = &radeon_atom_set_engine_clock,
557 .get_memory_clock = &radeon_atom_get_memory_clock,
558 .set_memory_clock = &radeon_atom_set_memory_clock,
559 .get_pcie_lanes = &rv370_get_pcie_lanes,
560 .set_pcie_lanes = &rv370_set_pcie_lanes,
561 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 562 },
0f9e006c
AD		 563 .pflip = {
564 .pre_page_flip = &r100_pre_page_flip,
565 .page_flip = &r100_page_flip,
566 .post_page_flip = &r100_post_page_flip,
567 },
48e7a5f1
DV		 568};
569
570static struct radeon_asic rs400_asic = {
571 .init = &rs400_init,
572 .fini = &rs400_fini,
573 .suspend = &rs400_suspend,
574 .resume = &rs400_resume,
575 .vga_set_state = &r100_vga_set_state,
a2d07b74 576 .asic_reset = &r300_asic_reset,
54e88e06
AD		 577 .ioctl_wait_idle = NULL,
578 .gui_idle = &r100_gui_idle,
579 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
c5b3b850
AD		 580 .gart = {
581 .tlb_flush = &rs400_gart_tlb_flush,
582 .set_page = &rs400_gart_set_page,
583 },
4c87bc26
CK		 584 .ring = {
585 [RADEON_RING_TYPE_GFX_INDEX] = {
586 .ib_execute = &r100_ring_ib_execute,
587 .emit_fence = &r300_fence_ring_emit,
588 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 589 .cs_parse = &r300_cs_parse,
f712812e
AD		 590 .ring_start = &r300_ring_start,
591 .ring_test = &r100_ring_test,
592 .ib_test = &r100_ib_test,
8ba957b5 593 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 594 .get_rptr = &radeon_ring_generic_get_rptr,
595 .get_wptr = &radeon_ring_generic_get_wptr,
596 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 597 }
598 },
b35ea4ab
AD		 599 .irq = {
600 .set = &r100_irq_set,
601 .process = &r100_irq_process,
602 },
c79a49ca
AD		 603 .display = {
604 .bandwidth_update = &r100_bandwidth_update,
605 .get_vblank_counter = &r100_get_vblank_counter,
606 .wait_for_vblank = &r100_wait_for_vblank,
37e9b6a6 607 .set_backlight_level = &radeon_legacy_set_backlight_level,
6d92f81d 608 .get_backlight_level = &radeon_legacy_get_backlight_level,
c79a49ca 609 },
27cd7769
AD		 610 .copy = {
611 .blit = &r100_copy_blit,
612 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
613 .dma = &r200_copy_dma,
614 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
615 .copy = &r100_copy_blit,
616 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
617 },
9e6f3d02
AD		 618 .surface = {
619 .set_reg = r100_set_surface_reg,
620 .clear_reg = r100_clear_surface_reg,
621 },
901ea57d
AD		 622 .hpd = {
623 .init = &r100_hpd_init,
624 .fini = &r100_hpd_fini,
625 .sense = &r100_hpd_sense,
626 .set_polarity = &r100_hpd_set_polarity,
627 },
a02fa397
AD		 628 .pm = {
629 .misc = &r100_pm_misc,
630 .prepare = &r100_pm_prepare,
631 .finish = &r100_pm_finish,
632 .init_profile = &r100_pm_init_profile,
633 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 634 .get_engine_clock = &radeon_legacy_get_engine_clock,
635 .set_engine_clock = &radeon_legacy_set_engine_clock,
636 .get_memory_clock = &radeon_legacy_get_memory_clock,
637 .set_memory_clock = NULL,
638 .get_pcie_lanes = NULL,
639 .set_pcie_lanes = NULL,
640 .set_clock_gating = &radeon_legacy_set_clock_gating,
a02fa397 641 },
0f9e006c
AD		 642 .pflip = {
643 .pre_page_flip = &r100_pre_page_flip,
644 .page_flip = &r100_page_flip,
645 .post_page_flip = &r100_post_page_flip,
646 },
48e7a5f1
DV		 647};
648
649static struct radeon_asic rs600_asic = {
650 .init = &rs600_init,
651 .fini = &rs600_fini,
652 .suspend = &rs600_suspend,
653 .resume = &rs600_resume,
654 .vga_set_state = &r100_vga_set_state,
90aca4d2 655 .asic_reset = &rs600_asic_reset,
54e88e06
AD		 656 .ioctl_wait_idle = NULL,
657 .gui_idle = &r100_gui_idle,
658 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
c5b3b850
AD		 659 .gart = {
660 .tlb_flush = &rs600_gart_tlb_flush,
661 .set_page = &rs600_gart_set_page,
662 },
4c87bc26
CK		 663 .ring = {
664 [RADEON_RING_TYPE_GFX_INDEX] = {
665 .ib_execute = &r100_ring_ib_execute,
666 .emit_fence = &r300_fence_ring_emit,
667 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 668 .cs_parse = &r300_cs_parse,
f712812e
AD		 669 .ring_start = &r300_ring_start,
670 .ring_test = &r100_ring_test,
671 .ib_test = &r100_ib_test,
8ba957b5 672 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 673 .get_rptr = &radeon_ring_generic_get_rptr,
674 .get_wptr = &radeon_ring_generic_get_wptr,
675 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 676 }
677 },
b35ea4ab
AD		 678 .irq = {
679 .set = &rs600_irq_set,
680 .process = &rs600_irq_process,
681 },
c79a49ca
AD		 682 .display = {
683 .bandwidth_update = &rs600_bandwidth_update,
684 .get_vblank_counter = &rs600_get_vblank_counter,
685 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 686 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 687 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 688 .hdmi_enable = &r600_hdmi_enable,
689 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 690 },
27cd7769
AD		 691 .copy = {
692 .blit = &r100_copy_blit,
693 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
694 .dma = &r200_copy_dma,
695 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
696 .copy = &r100_copy_blit,
697 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
698 },
9e6f3d02
AD		 699 .surface = {
700 .set_reg = r100_set_surface_reg,
701 .clear_reg = r100_clear_surface_reg,
702 },
901ea57d
AD		 703 .hpd = {
704 .init = &rs600_hpd_init,
705 .fini = &rs600_hpd_fini,
706 .sense = &rs600_hpd_sense,
707 .set_polarity = &rs600_hpd_set_polarity,
708 },
a02fa397
AD		 709 .pm = {
710 .misc = &rs600_pm_misc,
711 .prepare = &rs600_pm_prepare,
712 .finish = &rs600_pm_finish,
713 .init_profile = &r420_pm_init_profile,
714 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 715 .get_engine_clock = &radeon_atom_get_engine_clock,
716 .set_engine_clock = &radeon_atom_set_engine_clock,
717 .get_memory_clock = &radeon_atom_get_memory_clock,
718 .set_memory_clock = &radeon_atom_set_memory_clock,
719 .get_pcie_lanes = NULL,
720 .set_pcie_lanes = NULL,
721 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 722 },
0f9e006c
AD		 723 .pflip = {
724 .pre_page_flip = &rs600_pre_page_flip,
725 .page_flip = &rs600_page_flip,
726 .post_page_flip = &rs600_post_page_flip,
727 },
48e7a5f1
DV		 728};
729
730static struct radeon_asic rs690_asic = {
731 .init = &rs690_init,
732 .fini = &rs690_fini,
733 .suspend = &rs690_suspend,
734 .resume = &rs690_resume,
735 .vga_set_state = &r100_vga_set_state,
90aca4d2 736 .asic_reset = &rs600_asic_reset,
54e88e06
AD		 737 .ioctl_wait_idle = NULL,
738 .gui_idle = &r100_gui_idle,
739 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
c5b3b850
AD		 740 .gart = {
741 .tlb_flush = &rs400_gart_tlb_flush,
742 .set_page = &rs400_gart_set_page,
743 },
4c87bc26
CK		 744 .ring = {
745 [RADEON_RING_TYPE_GFX_INDEX] = {
746 .ib_execute = &r100_ring_ib_execute,
747 .emit_fence = &r300_fence_ring_emit,
748 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 749 .cs_parse = &r300_cs_parse,
f712812e
AD		 750 .ring_start = &r300_ring_start,
751 .ring_test = &r100_ring_test,
752 .ib_test = &r100_ib_test,
8ba957b5 753 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 754 .get_rptr = &radeon_ring_generic_get_rptr,
755 .get_wptr = &radeon_ring_generic_get_wptr,
756 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 757 }
758 },
b35ea4ab
AD		 759 .irq = {
760 .set = &rs600_irq_set,
761 .process = &rs600_irq_process,
762 },
c79a49ca
AD		 763 .display = {
764 .get_vblank_counter = &rs600_get_vblank_counter,
765 .bandwidth_update = &rs690_bandwidth_update,
766 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 767 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 768 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 769 .hdmi_enable = &r600_hdmi_enable,
770 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 771 },
27cd7769
AD		 772 .copy = {
773 .blit = &r100_copy_blit,
774 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
775 .dma = &r200_copy_dma,
776 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
777 .copy = &r200_copy_dma,
778 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
779 },
9e6f3d02
AD		 780 .surface = {
781 .set_reg = r100_set_surface_reg,
782 .clear_reg = r100_clear_surface_reg,
783 },
901ea57d
AD		 784 .hpd = {
785 .init = &rs600_hpd_init,
786 .fini = &rs600_hpd_fini,
787 .sense = &rs600_hpd_sense,
788 .set_polarity = &rs600_hpd_set_polarity,
789 },
a02fa397
AD		 790 .pm = {
791 .misc = &rs600_pm_misc,
792 .prepare = &rs600_pm_prepare,
793 .finish = &rs600_pm_finish,
794 .init_profile = &r420_pm_init_profile,
795 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 796 .get_engine_clock = &radeon_atom_get_engine_clock,
797 .set_engine_clock = &radeon_atom_set_engine_clock,
798 .get_memory_clock = &radeon_atom_get_memory_clock,
799 .set_memory_clock = &radeon_atom_set_memory_clock,
800 .get_pcie_lanes = NULL,
801 .set_pcie_lanes = NULL,
802 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 803 },
0f9e006c
AD		 804 .pflip = {
805 .pre_page_flip = &rs600_pre_page_flip,
806 .page_flip = &rs600_page_flip,
807 .post_page_flip = &rs600_post_page_flip,
808 },
48e7a5f1
DV		 809};
810
811static struct radeon_asic rv515_asic = {
812 .init = &rv515_init,
813 .fini = &rv515_fini,
814 .suspend = &rv515_suspend,
815 .resume = &rv515_resume,
816 .vga_set_state = &r100_vga_set_state,
90aca4d2 817 .asic_reset = &rs600_asic_reset,
54e88e06
AD		 818 .ioctl_wait_idle = NULL,
819 .gui_idle = &r100_gui_idle,
820 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
c5b3b850
AD		 821 .gart = {
822 .tlb_flush = &rv370_pcie_gart_tlb_flush,
823 .set_page = &rv370_pcie_gart_set_page,
824 },
4c87bc26
CK		 825 .ring = {
826 [RADEON_RING_TYPE_GFX_INDEX] = {
827 .ib_execute = &r100_ring_ib_execute,
828 .emit_fence = &r300_fence_ring_emit,
829 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 830 .cs_parse = &r300_cs_parse,
f712812e
AD		 831 .ring_start = &rv515_ring_start,
832 .ring_test = &r100_ring_test,
833 .ib_test = &r100_ib_test,
8ba957b5 834 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 835 .get_rptr = &radeon_ring_generic_get_rptr,
836 .get_wptr = &radeon_ring_generic_get_wptr,
837 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 838 }
839 },
b35ea4ab
AD		 840 .irq = {
841 .set = &rs600_irq_set,
842 .process = &rs600_irq_process,
843 },
c79a49ca
AD		 844 .display = {
845 .get_vblank_counter = &rs600_get_vblank_counter,
846 .bandwidth_update = &rv515_bandwidth_update,
847 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 848 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 849 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 850 },
27cd7769
AD		 851 .copy = {
852 .blit = &r100_copy_blit,
853 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
854 .dma = &r200_copy_dma,
855 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
856 .copy = &r100_copy_blit,
857 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
858 },
9e6f3d02
AD		 859 .surface = {
860 .set_reg = r100_set_surface_reg,
861 .clear_reg = r100_clear_surface_reg,
862 },
901ea57d
AD		 863 .hpd = {
864 .init = &rs600_hpd_init,
865 .fini = &rs600_hpd_fini,
866 .sense = &rs600_hpd_sense,
867 .set_polarity = &rs600_hpd_set_polarity,
868 },
a02fa397
AD		 869 .pm = {
870 .misc = &rs600_pm_misc,
871 .prepare = &rs600_pm_prepare,
872 .finish = &rs600_pm_finish,
873 .init_profile = &r420_pm_init_profile,
874 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 875 .get_engine_clock = &radeon_atom_get_engine_clock,
876 .set_engine_clock = &radeon_atom_set_engine_clock,
877 .get_memory_clock = &radeon_atom_get_memory_clock,
878 .set_memory_clock = &radeon_atom_set_memory_clock,
879 .get_pcie_lanes = &rv370_get_pcie_lanes,
880 .set_pcie_lanes = &rv370_set_pcie_lanes,
881 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 882 },
0f9e006c
AD		 883 .pflip = {
884 .pre_page_flip = &rs600_pre_page_flip,
885 .page_flip = &rs600_page_flip,
886 .post_page_flip = &rs600_post_page_flip,
887 },
48e7a5f1
DV		 888};
889
890static struct radeon_asic r520_asic = {
891 .init = &r520_init,
892 .fini = &rv515_fini,
893 .suspend = &rv515_suspend,
894 .resume = &r520_resume,
895 .vga_set_state = &r100_vga_set_state,
90aca4d2 896 .asic_reset = &rs600_asic_reset,
54e88e06
AD		 897 .ioctl_wait_idle = NULL,
898 .gui_idle = &r100_gui_idle,
899 .mc_wait_for_idle = &r520_mc_wait_for_idle,
c5b3b850
AD		 900 .gart = {
901 .tlb_flush = &rv370_pcie_gart_tlb_flush,
902 .set_page = &rv370_pcie_gart_set_page,
903 },
4c87bc26
CK		 904 .ring = {
905 [RADEON_RING_TYPE_GFX_INDEX] = {
906 .ib_execute = &r100_ring_ib_execute,
907 .emit_fence = &r300_fence_ring_emit,
908 .emit_semaphore = &r100_semaphore_ring_emit,
eb0c19c5 909 .cs_parse = &r300_cs_parse,
f712812e
AD		 910 .ring_start = &rv515_ring_start,
911 .ring_test = &r100_ring_test,
912 .ib_test = &r100_ib_test,
8ba957b5 913 .is_lockup = &r100_gpu_is_lockup,
f93bdefe
AD		 914 .get_rptr = &radeon_ring_generic_get_rptr,
915 .get_wptr = &radeon_ring_generic_get_wptr,
916 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 917 }
918 },
b35ea4ab
AD		 919 .irq = {
920 .set = &rs600_irq_set,
921 .process = &rs600_irq_process,
922 },
c79a49ca
AD		 923 .display = {
924 .bandwidth_update = &rv515_bandwidth_update,
925 .get_vblank_counter = &rs600_get_vblank_counter,
926 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 927 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 928 .get_backlight_level = &atombios_get_backlight_level,
c79a49ca 929 },
27cd7769
AD		 930 .copy = {
931 .blit = &r100_copy_blit,
932 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
933 .dma = &r200_copy_dma,
934 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
935 .copy = &r100_copy_blit,
936 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
937 },
9e6f3d02
AD		 938 .surface = {
939 .set_reg = r100_set_surface_reg,
940 .clear_reg = r100_clear_surface_reg,
941 },
901ea57d
AD		 942 .hpd = {
943 .init = &rs600_hpd_init,
944 .fini = &rs600_hpd_fini,
945 .sense = &rs600_hpd_sense,
946 .set_polarity = &rs600_hpd_set_polarity,
947 },
a02fa397
AD		 948 .pm = {
949 .misc = &rs600_pm_misc,
950 .prepare = &rs600_pm_prepare,
951 .finish = &rs600_pm_finish,
952 .init_profile = &r420_pm_init_profile,
953 .get_dynpm_state = &r100_pm_get_dynpm_state,
798bcf73
AD		 954 .get_engine_clock = &radeon_atom_get_engine_clock,
955 .set_engine_clock = &radeon_atom_set_engine_clock,
956 .get_memory_clock = &radeon_atom_get_memory_clock,
957 .set_memory_clock = &radeon_atom_set_memory_clock,
958 .get_pcie_lanes = &rv370_get_pcie_lanes,
959 .set_pcie_lanes = &rv370_set_pcie_lanes,
960 .set_clock_gating = &radeon_atom_set_clock_gating,
a02fa397 961 },
0f9e006c
AD		 962 .pflip = {
963 .pre_page_flip = &rs600_pre_page_flip,
964 .page_flip = &rs600_page_flip,
965 .post_page_flip = &rs600_post_page_flip,
966 },
48e7a5f1
DV		 967};
968
969static struct radeon_asic r600_asic = {
970 .init = &r600_init,
971 .fini = &r600_fini,
972 .suspend = &r600_suspend,
973 .resume = &r600_resume,
48e7a5f1 974 .vga_set_state = &r600_vga_set_state,
a2d07b74 975 .asic_reset = &r600_asic_reset,
54e88e06
AD		 976 .ioctl_wait_idle = r600_ioctl_wait_idle,
977 .gui_idle = &r600_gui_idle,
978 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 979 .get_xclk = &r600_get_xclk,
d0418894 980 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 981 .gart = {
982 .tlb_flush = &r600_pcie_gart_tlb_flush,
983 .set_page = &rs600_gart_set_page,
984 },
4c87bc26
CK		 985 .ring = {
986 [RADEON_RING_TYPE_GFX_INDEX] = {
987 .ib_execute = &r600_ring_ib_execute,
988 .emit_fence = &r600_fence_ring_emit,
989 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 990 .cs_parse = &r600_cs_parse,
f712812e
AD		 991 .ring_test = &r600_ring_test,
992 .ib_test = &r600_ib_test,
123bc183 993 .is_lockup = &r600_gfx_is_lockup,
f93bdefe
AD		 994 .get_rptr = &radeon_ring_generic_get_rptr,
995 .get_wptr = &radeon_ring_generic_get_wptr,
996 .set_wptr = &radeon_ring_generic_set_wptr,
4d75658b
AD		 997 },
998 [R600_RING_TYPE_DMA_INDEX] = {
999 .ib_execute = &r600_dma_ring_ib_execute,
1000 .emit_fence = &r600_dma_fence_ring_emit,
1001 .emit_semaphore = &r600_dma_semaphore_ring_emit,
cf4ccd01 1002 .cs_parse = &r600_dma_cs_parse,
4d75658b
AD		 1003 .ring_test = &r600_dma_ring_test,
1004 .ib_test = &r600_dma_ib_test,
1005 .is_lockup = &r600_dma_is_lockup,
f93bdefe
AD		 1006 .get_rptr = &radeon_ring_generic_get_rptr,
1007 .get_wptr = &radeon_ring_generic_get_wptr,
1008 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 1009 }
1010 },
b35ea4ab
AD		 1011 .irq = {
1012 .set = &r600_irq_set,
1013 .process = &r600_irq_process,
1014 },
c79a49ca
AD		 1015 .display = {
1016 .bandwidth_update = &rv515_bandwidth_update,
1017 .get_vblank_counter = &rs600_get_vblank_counter,
1018 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 1019 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1020 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1021 .hdmi_enable = &r600_hdmi_enable,
1022 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 1023 },
27cd7769
AD		 1024 .copy = {
1025 .blit = &r600_copy_blit,
1026 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
4d75658b
AD		 1027 .dma = &r600_copy_dma,
1028 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1029 .copy = &r600_copy_dma,
1030 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1031 },
9e6f3d02
AD		 1032 .surface = {
1033 .set_reg = r600_set_surface_reg,
1034 .clear_reg = r600_clear_surface_reg,
1035 },
901ea57d
AD		 1036 .hpd = {
1037 .init = &r600_hpd_init,
1038 .fini = &r600_hpd_fini,
1039 .sense = &r600_hpd_sense,
1040 .set_polarity = &r600_hpd_set_polarity,
1041 },
a02fa397
AD		 1042 .pm = {
1043 .misc = &r600_pm_misc,
1044 .prepare = &rs600_pm_prepare,
1045 .finish = &rs600_pm_finish,
1046 .init_profile = &r600_pm_init_profile,
1047 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1048 .get_engine_clock = &radeon_atom_get_engine_clock,
1049 .set_engine_clock = &radeon_atom_set_engine_clock,
1050 .get_memory_clock = &radeon_atom_get_memory_clock,
1051 .set_memory_clock = &radeon_atom_set_memory_clock,
1052 .get_pcie_lanes = &r600_get_pcie_lanes,
1053 .set_pcie_lanes = &r600_set_pcie_lanes,
1054 .set_clock_gating = NULL,
6bd1c385 1055 .get_temperature = &rv6xx_get_temp,
a02fa397 1056 },
0f9e006c
AD		 1057 .pflip = {
1058 .pre_page_flip = &rs600_pre_page_flip,
1059 .page_flip = &rs600_page_flip,
1060 .post_page_flip = &rs600_post_page_flip,
1061 },
48e7a5f1
DV		 1062};
1063
ca361b65
AD		 1064static struct radeon_asic rv6xx_asic = {
1065 .init = &r600_init,
1066 .fini = &r600_fini,
1067 .suspend = &r600_suspend,
1068 .resume = &r600_resume,
1069 .vga_set_state = &r600_vga_set_state,
1070 .asic_reset = &r600_asic_reset,
1071 .ioctl_wait_idle = r600_ioctl_wait_idle,
1072 .gui_idle = &r600_gui_idle,
1073 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1074 .get_xclk = &r600_get_xclk,
1075 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1076 .gart = {
1077 .tlb_flush = &r600_pcie_gart_tlb_flush,
1078 .set_page = &rs600_gart_set_page,
1079 },
1080 .ring = {
1081 [RADEON_RING_TYPE_GFX_INDEX] = {
1082 .ib_execute = &r600_ring_ib_execute,
1083 .emit_fence = &r600_fence_ring_emit,
1084 .emit_semaphore = &r600_semaphore_ring_emit,
1085 .cs_parse = &r600_cs_parse,
1086 .ring_test = &r600_ring_test,
1087 .ib_test = &r600_ib_test,
1088 .is_lockup = &r600_gfx_is_lockup,
1089 .get_rptr = &radeon_ring_generic_get_rptr,
1090 .get_wptr = &radeon_ring_generic_get_wptr,
1091 .set_wptr = &radeon_ring_generic_set_wptr,
1092 },
1093 [R600_RING_TYPE_DMA_INDEX] = {
1094 .ib_execute = &r600_dma_ring_ib_execute,
1095 .emit_fence = &r600_dma_fence_ring_emit,
1096 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1097 .cs_parse = &r600_dma_cs_parse,
1098 .ring_test = &r600_dma_ring_test,
1099 .ib_test = &r600_dma_ib_test,
1100 .is_lockup = &r600_dma_is_lockup,
1101 .get_rptr = &radeon_ring_generic_get_rptr,
1102 .get_wptr = &radeon_ring_generic_get_wptr,
1103 .set_wptr = &radeon_ring_generic_set_wptr,
1104 }
1105 },
1106 .irq = {
1107 .set = &r600_irq_set,
1108 .process = &r600_irq_process,
1109 },
1110 .display = {
1111 .bandwidth_update = &rv515_bandwidth_update,
1112 .get_vblank_counter = &rs600_get_vblank_counter,
1113 .wait_for_vblank = &avivo_wait_for_vblank,
1114 .set_backlight_level = &atombios_set_backlight_level,
1115 .get_backlight_level = &atombios_get_backlight_level,
1116 },
1117 .copy = {
1118 .blit = &r600_copy_blit,
1119 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1120 .dma = &r600_copy_dma,
1121 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1122 .copy = &r600_copy_dma,
1123 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1124 },
1125 .surface = {
1126 .set_reg = r600_set_surface_reg,
1127 .clear_reg = r600_clear_surface_reg,
1128 },
1129 .hpd = {
1130 .init = &r600_hpd_init,
1131 .fini = &r600_hpd_fini,
1132 .sense = &r600_hpd_sense,
1133 .set_polarity = &r600_hpd_set_polarity,
1134 },
1135 .pm = {
1136 .misc = &r600_pm_misc,
1137 .prepare = &rs600_pm_prepare,
1138 .finish = &rs600_pm_finish,
1139 .init_profile = &r600_pm_init_profile,
1140 .get_dynpm_state = &r600_pm_get_dynpm_state,
1141 .get_engine_clock = &radeon_atom_get_engine_clock,
1142 .set_engine_clock = &radeon_atom_set_engine_clock,
1143 .get_memory_clock = &radeon_atom_get_memory_clock,
1144 .set_memory_clock = &radeon_atom_set_memory_clock,
1145 .get_pcie_lanes = &r600_get_pcie_lanes,
1146 .set_pcie_lanes = &r600_set_pcie_lanes,
1147 .set_clock_gating = NULL,
1148 .get_temperature = &rv6xx_get_temp,
1149 },
4a6369e9
AD		 1150 .dpm = {
1151 .init = &rv6xx_dpm_init,
1152 .setup_asic = &rv6xx_setup_asic,
1153 .enable = &rv6xx_dpm_enable,
1154 .disable = &rv6xx_dpm_disable,
98243917 1155 .pre_set_power_state = &r600_dpm_pre_set_power_state,
4a6369e9 1156 .set_power_state = &rv6xx_dpm_set_power_state,
98243917 1157 .post_set_power_state = &r600_dpm_post_set_power_state,
4a6369e9
AD		 1158 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1159 .fini = &rv6xx_dpm_fini,
1160 .get_sclk = &rv6xx_dpm_get_sclk,
1161 .get_mclk = &rv6xx_dpm_get_mclk,
1162 .print_power_state = &rv6xx_dpm_print_power_state,
242916a5 1163 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
4a6369e9 1164 },
ca361b65
AD		 1165 .pflip = {
1166 .pre_page_flip = &rs600_pre_page_flip,
1167 .page_flip = &rs600_page_flip,
1168 .post_page_flip = &rs600_post_page_flip,
1169 },
1170};
1171
f47299c5
AD		 1172static struct radeon_asic rs780_asic = {
1173 .init = &r600_init,
1174 .fini = &r600_fini,
1175 .suspend = &r600_suspend,
1176 .resume = &r600_resume,
f47299c5 1177 .vga_set_state = &r600_vga_set_state,
a2d07b74 1178 .asic_reset = &r600_asic_reset,
54e88e06
AD		 1179 .ioctl_wait_idle = r600_ioctl_wait_idle,
1180 .gui_idle = &r600_gui_idle,
1181 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 1182 .get_xclk = &r600_get_xclk,
d0418894 1183 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1184 .gart = {
1185 .tlb_flush = &r600_pcie_gart_tlb_flush,
1186 .set_page = &rs600_gart_set_page,
1187 },
4c87bc26
CK		 1188 .ring = {
1189 [RADEON_RING_TYPE_GFX_INDEX] = {
1190 .ib_execute = &r600_ring_ib_execute,
1191 .emit_fence = &r600_fence_ring_emit,
1192 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1193 .cs_parse = &r600_cs_parse,
f712812e
AD		 1194 .ring_test = &r600_ring_test,
1195 .ib_test = &r600_ib_test,
123bc183 1196 .is_lockup = &r600_gfx_is_lockup,
f93bdefe
AD		 1197 .get_rptr = &radeon_ring_generic_get_rptr,
1198 .get_wptr = &radeon_ring_generic_get_wptr,
1199 .set_wptr = &radeon_ring_generic_set_wptr,
4d75658b
AD		 1200 },
1201 [R600_RING_TYPE_DMA_INDEX] = {
1202 .ib_execute = &r600_dma_ring_ib_execute,
1203 .emit_fence = &r600_dma_fence_ring_emit,
1204 .emit_semaphore = &r600_dma_semaphore_ring_emit,
cf4ccd01 1205 .cs_parse = &r600_dma_cs_parse,
4d75658b
AD		 1206 .ring_test = &r600_dma_ring_test,
1207 .ib_test = &r600_dma_ib_test,
1208 .is_lockup = &r600_dma_is_lockup,
f93bdefe
AD		 1209 .get_rptr = &radeon_ring_generic_get_rptr,
1210 .get_wptr = &radeon_ring_generic_get_wptr,
1211 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 1212 }
1213 },
b35ea4ab
AD		 1214 .irq = {
1215 .set = &r600_irq_set,
1216 .process = &r600_irq_process,
1217 },
c79a49ca
AD		 1218 .display = {
1219 .bandwidth_update = &rs690_bandwidth_update,
1220 .get_vblank_counter = &rs600_get_vblank_counter,
1221 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 1222 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1223 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1224 .hdmi_enable = &r600_hdmi_enable,
1225 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 1226 },
27cd7769
AD		 1227 .copy = {
1228 .blit = &r600_copy_blit,
1229 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
4d75658b
AD		 1230 .dma = &r600_copy_dma,
1231 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1232 .copy = &r600_copy_dma,
1233 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1234 },
9e6f3d02
AD		 1235 .surface = {
1236 .set_reg = r600_set_surface_reg,
1237 .clear_reg = r600_clear_surface_reg,
1238 },
901ea57d
AD		 1239 .hpd = {
1240 .init = &r600_hpd_init,
1241 .fini = &r600_hpd_fini,
1242 .sense = &r600_hpd_sense,
1243 .set_polarity = &r600_hpd_set_polarity,
1244 },
a02fa397
AD		 1245 .pm = {
1246 .misc = &r600_pm_misc,
1247 .prepare = &rs600_pm_prepare,
1248 .finish = &rs600_pm_finish,
1249 .init_profile = &rs780_pm_init_profile,
1250 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1251 .get_engine_clock = &radeon_atom_get_engine_clock,
1252 .set_engine_clock = &radeon_atom_set_engine_clock,
1253 .get_memory_clock = NULL,
1254 .set_memory_clock = NULL,
1255 .get_pcie_lanes = NULL,
1256 .set_pcie_lanes = NULL,
1257 .set_clock_gating = NULL,
6bd1c385 1258 .get_temperature = &rv6xx_get_temp,
a02fa397 1259 },
9d67006e
AD		 1260 .dpm = {
1261 .init = &rs780_dpm_init,
1262 .setup_asic = &rs780_dpm_setup_asic,
1263 .enable = &rs780_dpm_enable,
1264 .disable = &rs780_dpm_disable,
98243917 1265 .pre_set_power_state = &r600_dpm_pre_set_power_state,
9d67006e 1266 .set_power_state = &rs780_dpm_set_power_state,
98243917 1267 .post_set_power_state = &r600_dpm_post_set_power_state,
9d67006e
AD		 1268 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1269 .fini = &rs780_dpm_fini,
1270 .get_sclk = &rs780_dpm_get_sclk,
1271 .get_mclk = &rs780_dpm_get_mclk,
1272 .print_power_state = &rs780_dpm_print_power_state,
1273 },
0f9e006c
AD		 1274 .pflip = {
1275 .pre_page_flip = &rs600_pre_page_flip,
1276 .page_flip = &rs600_page_flip,
1277 .post_page_flip = &rs600_post_page_flip,
1278 },
f47299c5
AD		 1279};
1280
48e7a5f1
DV		 1281static struct radeon_asic rv770_asic = {
1282 .init = &rv770_init,
1283 .fini = &rv770_fini,
1284 .suspend = &rv770_suspend,
1285 .resume = &rv770_resume,
a2d07b74 1286 .asic_reset = &r600_asic_reset,
48e7a5f1 1287 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1288 .ioctl_wait_idle = r600_ioctl_wait_idle,
1289 .gui_idle = &r600_gui_idle,
1290 .mc_wait_for_idle = &r600_mc_wait_for_idle,
454d2e2a 1291 .get_xclk = &rv770_get_xclk,
d0418894 1292 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1293 .gart = {
1294 .tlb_flush = &r600_pcie_gart_tlb_flush,
1295 .set_page = &rs600_gart_set_page,
1296 },
4c87bc26
CK		 1297 .ring = {
1298 [RADEON_RING_TYPE_GFX_INDEX] = {
1299 .ib_execute = &r600_ring_ib_execute,
1300 .emit_fence = &r600_fence_ring_emit,
1301 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1302 .cs_parse = &r600_cs_parse,
f712812e
AD		 1303 .ring_test = &r600_ring_test,
1304 .ib_test = &r600_ib_test,
123bc183 1305 .is_lockup = &r600_gfx_is_lockup,
f93bdefe
AD		 1306 .get_rptr = &radeon_ring_generic_get_rptr,
1307 .get_wptr = &radeon_ring_generic_get_wptr,
1308 .set_wptr = &radeon_ring_generic_set_wptr,
4d75658b
AD		 1309 },
1310 [R600_RING_TYPE_DMA_INDEX] = {
1311 .ib_execute = &r600_dma_ring_ib_execute,
1312 .emit_fence = &r600_dma_fence_ring_emit,
1313 .emit_semaphore = &r600_dma_semaphore_ring_emit,
cf4ccd01 1314 .cs_parse = &r600_dma_cs_parse,
4d75658b
AD		 1315 .ring_test = &r600_dma_ring_test,
1316 .ib_test = &r600_dma_ib_test,
1317 .is_lockup = &r600_dma_is_lockup,
f93bdefe
AD		 1318 .get_rptr = &radeon_ring_generic_get_rptr,
1319 .get_wptr = &radeon_ring_generic_get_wptr,
1320 .set_wptr = &radeon_ring_generic_set_wptr,
f2ba57b5
CK		 1321 },
1322 [R600_RING_TYPE_UVD_INDEX] = {
1323 .ib_execute = &r600_uvd_ib_execute,
1324 .emit_fence = &r600_uvd_fence_emit,
1325 .emit_semaphore = &r600_uvd_semaphore_emit,
1326 .cs_parse = &radeon_uvd_cs_parse,
1327 .ring_test = &r600_uvd_ring_test,
1328 .ib_test = &r600_uvd_ib_test,
1329 .is_lockup = &radeon_ring_test_lockup,
f93bdefe
AD		 1330 .get_rptr = &radeon_ring_generic_get_rptr,
1331 .get_wptr = &radeon_ring_generic_get_wptr,
1332 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 1333 }
1334 },
b35ea4ab
AD		 1335 .irq = {
1336 .set = &r600_irq_set,
1337 .process = &r600_irq_process,
1338 },
c79a49ca
AD		 1339 .display = {
1340 .bandwidth_update = &rv515_bandwidth_update,
1341 .get_vblank_counter = &rs600_get_vblank_counter,
1342 .wait_for_vblank = &avivo_wait_for_vblank,
37e9b6a6 1343 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1344 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1345 .hdmi_enable = &r600_hdmi_enable,
1346 .hdmi_setmode = &r600_hdmi_setmode,
c79a49ca 1347 },
27cd7769
AD		 1348 .copy = {
1349 .blit = &r600_copy_blit,
1350 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
43fb7787 1351 .dma = &rv770_copy_dma,
4d75658b 1352 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
43fb7787 1353 .copy = &rv770_copy_dma,
2d6cc729 1354 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1355 },
9e6f3d02
AD		 1356 .surface = {
1357 .set_reg = r600_set_surface_reg,
1358 .clear_reg = r600_clear_surface_reg,
1359 },
901ea57d
AD		 1360 .hpd = {
1361 .init = &r600_hpd_init,
1362 .fini = &r600_hpd_fini,
1363 .sense = &r600_hpd_sense,
1364 .set_polarity = &r600_hpd_set_polarity,
1365 },
a02fa397
AD		 1366 .pm = {
1367 .misc = &rv770_pm_misc,
1368 .prepare = &rs600_pm_prepare,
1369 .finish = &rs600_pm_finish,
1370 .init_profile = &r600_pm_init_profile,
1371 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1372 .get_engine_clock = &radeon_atom_get_engine_clock,
1373 .set_engine_clock = &radeon_atom_set_engine_clock,
1374 .get_memory_clock = &radeon_atom_get_memory_clock,
1375 .set_memory_clock = &radeon_atom_set_memory_clock,
1376 .get_pcie_lanes = &r600_get_pcie_lanes,
1377 .set_pcie_lanes = &r600_set_pcie_lanes,
1378 .set_clock_gating = &radeon_atom_set_clock_gating,
ef0e6e65 1379 .set_uvd_clocks = &rv770_set_uvd_clocks,
6bd1c385 1380 .get_temperature = &rv770_get_temp,
a02fa397 1381 },
66229b20
AD		 1382 .dpm = {
1383 .init = &rv770_dpm_init,
1384 .setup_asic = &rv770_dpm_setup_asic,
1385 .enable = &rv770_dpm_enable,
1386 .disable = &rv770_dpm_disable,
98243917 1387 .pre_set_power_state = &r600_dpm_pre_set_power_state,
66229b20 1388 .set_power_state = &rv770_dpm_set_power_state,
98243917 1389 .post_set_power_state = &r600_dpm_post_set_power_state,
66229b20
AD		 1390 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1391 .fini = &rv770_dpm_fini,
1392 .get_sclk = &rv770_dpm_get_sclk,
1393 .get_mclk = &rv770_dpm_get_mclk,
1394 .print_power_state = &rv770_dpm_print_power_state,
bd210d11 1395 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
66229b20 1396 },
0f9e006c
AD		 1397 .pflip = {
1398 .pre_page_flip = &rs600_pre_page_flip,
1399 .page_flip = &rv770_page_flip,
1400 .post_page_flip = &rs600_post_page_flip,
1401 },
48e7a5f1
DV		 1402};
1403
1404static struct radeon_asic evergreen_asic = {
1405 .init = &evergreen_init,
1406 .fini = &evergreen_fini,
1407 .suspend = &evergreen_suspend,
1408 .resume = &evergreen_resume,
a2d07b74 1409 .asic_reset = &evergreen_asic_reset,
48e7a5f1 1410 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1411 .ioctl_wait_idle = r600_ioctl_wait_idle,
1412 .gui_idle = &r600_gui_idle,
1413 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1414 .get_xclk = &rv770_get_xclk,
d0418894 1415 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1416 .gart = {
1417 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1418 .set_page = &rs600_gart_set_page,
1419 },
4c87bc26
CK		 1420 .ring = {
1421 [RADEON_RING_TYPE_GFX_INDEX] = {
1422 .ib_execute = &evergreen_ring_ib_execute,
1423 .emit_fence = &r600_fence_ring_emit,
1424 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1425 .cs_parse = &evergreen_cs_parse,
f712812e
AD		 1426 .ring_test = &r600_ring_test,
1427 .ib_test = &r600_ib_test,
123bc183 1428 .is_lockup = &evergreen_gfx_is_lockup,
f93bdefe
AD		 1429 .get_rptr = &radeon_ring_generic_get_rptr,
1430 .get_wptr = &radeon_ring_generic_get_wptr,
1431 .set_wptr = &radeon_ring_generic_set_wptr,
233d1ad5
AD		 1432 },
1433 [R600_RING_TYPE_DMA_INDEX] = {
1434 .ib_execute = &evergreen_dma_ring_ib_execute,
1435 .emit_fence = &evergreen_dma_fence_ring_emit,
1436 .emit_semaphore = &r600_dma_semaphore_ring_emit,
d2ead3ea 1437 .cs_parse = &evergreen_dma_cs_parse,
233d1ad5
AD		 1438 .ring_test = &r600_dma_ring_test,
1439 .ib_test = &r600_dma_ib_test,
123bc183 1440 .is_lockup = &evergreen_dma_is_lockup,
f93bdefe
AD		 1441 .get_rptr = &radeon_ring_generic_get_rptr,
1442 .get_wptr = &radeon_ring_generic_get_wptr,
1443 .set_wptr = &radeon_ring_generic_set_wptr,
f2ba57b5
CK		 1444 },
1445 [R600_RING_TYPE_UVD_INDEX] = {
1446 .ib_execute = &r600_uvd_ib_execute,
1447 .emit_fence = &r600_uvd_fence_emit,
1448 .emit_semaphore = &r600_uvd_semaphore_emit,
1449 .cs_parse = &radeon_uvd_cs_parse,
1450 .ring_test = &r600_uvd_ring_test,
1451 .ib_test = &r600_uvd_ib_test,
1452 .is_lockup = &radeon_ring_test_lockup,
f93bdefe
AD		 1453 .get_rptr = &radeon_ring_generic_get_rptr,
1454 .get_wptr = &radeon_ring_generic_get_wptr,
1455 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 1456 }
1457 },
b35ea4ab
AD		 1458 .irq = {
1459 .set = &evergreen_irq_set,
1460 .process = &evergreen_irq_process,
1461 },
c79a49ca
AD		 1462 .display = {
1463 .bandwidth_update = &evergreen_bandwidth_update,
1464 .get_vblank_counter = &evergreen_get_vblank_counter,
1465 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1466 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1467 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1468 .hdmi_enable = &evergreen_hdmi_enable,
1469 .hdmi_setmode = &evergreen_hdmi_setmode,
c79a49ca 1470 },
27cd7769
AD		 1471 .copy = {
1472 .blit = &r600_copy_blit,
1473 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1474 .dma = &evergreen_copy_dma,
1475 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1476 .copy = &evergreen_copy_dma,
1477 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1478 },
9e6f3d02
AD		 1479 .surface = {
1480 .set_reg = r600_set_surface_reg,
1481 .clear_reg = r600_clear_surface_reg,
1482 },
901ea57d
AD		 1483 .hpd = {
1484 .init = &evergreen_hpd_init,
1485 .fini = &evergreen_hpd_fini,
1486 .sense = &evergreen_hpd_sense,
1487 .set_polarity = &evergreen_hpd_set_polarity,
1488 },
a02fa397
AD		 1489 .pm = {
1490 .misc = &evergreen_pm_misc,
1491 .prepare = &evergreen_pm_prepare,
1492 .finish = &evergreen_pm_finish,
1493 .init_profile = &r600_pm_init_profile,
1494 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1495 .get_engine_clock = &radeon_atom_get_engine_clock,
1496 .set_engine_clock = &radeon_atom_set_engine_clock,
1497 .get_memory_clock = &radeon_atom_get_memory_clock,
1498 .set_memory_clock = &radeon_atom_set_memory_clock,
1499 .get_pcie_lanes = &r600_get_pcie_lanes,
1500 .set_pcie_lanes = &r600_set_pcie_lanes,
1501 .set_clock_gating = NULL,
a8b4925c 1502 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1503 .get_temperature = &evergreen_get_temp,
a02fa397 1504 },
dc50ba7f
AD		 1505 .dpm = {
1506 .init = &cypress_dpm_init,
1507 .setup_asic = &cypress_dpm_setup_asic,
1508 .enable = &cypress_dpm_enable,
1509 .disable = &cypress_dpm_disable,
98243917 1510 .pre_set_power_state = &r600_dpm_pre_set_power_state,
dc50ba7f 1511 .set_power_state = &cypress_dpm_set_power_state,
98243917 1512 .post_set_power_state = &r600_dpm_post_set_power_state,
dc50ba7f
AD		 1513 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1514 .fini = &cypress_dpm_fini,
1515 .get_sclk = &rv770_dpm_get_sclk,
1516 .get_mclk = &rv770_dpm_get_mclk,
1517 .print_power_state = &rv770_dpm_print_power_state,
bd210d11 1518 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
dc50ba7f 1519 },
0f9e006c
AD		 1520 .pflip = {
1521 .pre_page_flip = &evergreen_pre_page_flip,
1522 .page_flip = &evergreen_page_flip,
1523 .post_page_flip = &evergreen_post_page_flip,
1524 },
48e7a5f1
DV		 1525};
1526
958261d1
AD		 1527static struct radeon_asic sumo_asic = {
1528 .init = &evergreen_init,
1529 .fini = &evergreen_fini,
1530 .suspend = &evergreen_suspend,
1531 .resume = &evergreen_resume,
958261d1
AD		 1532 .asic_reset = &evergreen_asic_reset,
1533 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1534 .ioctl_wait_idle = r600_ioctl_wait_idle,
1535 .gui_idle = &r600_gui_idle,
1536 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1537 .get_xclk = &r600_get_xclk,
d0418894 1538 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1539 .gart = {
1540 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1541 .set_page = &rs600_gart_set_page,
1542 },
4c87bc26
CK		 1543 .ring = {
1544 [RADEON_RING_TYPE_GFX_INDEX] = {
1545 .ib_execute = &evergreen_ring_ib_execute,
1546 .emit_fence = &r600_fence_ring_emit,
1547 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1548 .cs_parse = &evergreen_cs_parse,
f712812e
AD		 1549 .ring_test = &r600_ring_test,
1550 .ib_test = &r600_ib_test,
123bc183 1551 .is_lockup = &evergreen_gfx_is_lockup,
f93bdefe
AD		 1552 .get_rptr = &radeon_ring_generic_get_rptr,
1553 .get_wptr = &radeon_ring_generic_get_wptr,
1554 .set_wptr = &radeon_ring_generic_set_wptr,
eb0c19c5 1555 },
233d1ad5
AD		 1556 [R600_RING_TYPE_DMA_INDEX] = {
1557 .ib_execute = &evergreen_dma_ring_ib_execute,
1558 .emit_fence = &evergreen_dma_fence_ring_emit,
1559 .emit_semaphore = &r600_dma_semaphore_ring_emit,
d2ead3ea 1560 .cs_parse = &evergreen_dma_cs_parse,
233d1ad5
AD		 1561 .ring_test = &r600_dma_ring_test,
1562 .ib_test = &r600_dma_ib_test,
123bc183 1563 .is_lockup = &evergreen_dma_is_lockup,
f93bdefe
AD		 1564 .get_rptr = &radeon_ring_generic_get_rptr,
1565 .get_wptr = &radeon_ring_generic_get_wptr,
1566 .set_wptr = &radeon_ring_generic_set_wptr,
f2ba57b5
CK		 1567 },
1568 [R600_RING_TYPE_UVD_INDEX] = {
1569 .ib_execute = &r600_uvd_ib_execute,
1570 .emit_fence = &r600_uvd_fence_emit,
1571 .emit_semaphore = &r600_uvd_semaphore_emit,
1572 .cs_parse = &radeon_uvd_cs_parse,
1573 .ring_test = &r600_uvd_ring_test,
1574 .ib_test = &r600_uvd_ib_test,
1575 .is_lockup = &radeon_ring_test_lockup,
f93bdefe
AD		 1576 .get_rptr = &radeon_ring_generic_get_rptr,
1577 .get_wptr = &radeon_ring_generic_get_wptr,
1578 .set_wptr = &radeon_ring_generic_set_wptr,
233d1ad5 1579 }
4c87bc26 1580 },
b35ea4ab
AD		 1581 .irq = {
1582 .set = &evergreen_irq_set,
1583 .process = &evergreen_irq_process,
1584 },
c79a49ca
AD		 1585 .display = {
1586 .bandwidth_update = &evergreen_bandwidth_update,
1587 .get_vblank_counter = &evergreen_get_vblank_counter,
1588 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1589 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1590 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1591 .hdmi_enable = &evergreen_hdmi_enable,
1592 .hdmi_setmode = &evergreen_hdmi_setmode,
c79a49ca 1593 },
27cd7769
AD		 1594 .copy = {
1595 .blit = &r600_copy_blit,
1596 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1597 .dma = &evergreen_copy_dma,
1598 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1599 .copy = &evergreen_copy_dma,
1600 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1601 },
9e6f3d02
AD		 1602 .surface = {
1603 .set_reg = r600_set_surface_reg,
1604 .clear_reg = r600_clear_surface_reg,
1605 },
901ea57d
AD		 1606 .hpd = {
1607 .init = &evergreen_hpd_init,
1608 .fini = &evergreen_hpd_fini,
1609 .sense = &evergreen_hpd_sense,
1610 .set_polarity = &evergreen_hpd_set_polarity,
1611 },
a02fa397
AD		 1612 .pm = {
1613 .misc = &evergreen_pm_misc,
1614 .prepare = &evergreen_pm_prepare,
1615 .finish = &evergreen_pm_finish,
1616 .init_profile = &sumo_pm_init_profile,
1617 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1618 .get_engine_clock = &radeon_atom_get_engine_clock,
1619 .set_engine_clock = &radeon_atom_set_engine_clock,
1620 .get_memory_clock = NULL,
1621 .set_memory_clock = NULL,
1622 .get_pcie_lanes = NULL,
1623 .set_pcie_lanes = NULL,
1624 .set_clock_gating = NULL,
23d33ba3 1625 .set_uvd_clocks = &sumo_set_uvd_clocks,
6bd1c385 1626 .get_temperature = &sumo_get_temp,
a02fa397 1627 },
80ea2c12
AD		 1628 .dpm = {
1629 .init = &sumo_dpm_init,
1630 .setup_asic = &sumo_dpm_setup_asic,
1631 .enable = &sumo_dpm_enable,
1632 .disable = &sumo_dpm_disable,
422a56bc 1633 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
80ea2c12 1634 .set_power_state = &sumo_dpm_set_power_state,
422a56bc 1635 .post_set_power_state = &sumo_dpm_post_set_power_state,
80ea2c12
AD		 1636 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1637 .fini = &sumo_dpm_fini,
1638 .get_sclk = &sumo_dpm_get_sclk,
1639 .get_mclk = &sumo_dpm_get_mclk,
1640 .print_power_state = &sumo_dpm_print_power_state,
1641 },
0f9e006c
AD		 1642 .pflip = {
1643 .pre_page_flip = &evergreen_pre_page_flip,
1644 .page_flip = &evergreen_page_flip,
1645 .post_page_flip = &evergreen_post_page_flip,
1646 },
958261d1
AD		 1647};
1648
a43b7665
AD		 1649static struct radeon_asic btc_asic = {
1650 .init = &evergreen_init,
1651 .fini = &evergreen_fini,
1652 .suspend = &evergreen_suspend,
1653 .resume = &evergreen_resume,
a43b7665
AD		 1654 .asic_reset = &evergreen_asic_reset,
1655 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1656 .ioctl_wait_idle = r600_ioctl_wait_idle,
1657 .gui_idle = &r600_gui_idle,
1658 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1659 .get_xclk = &rv770_get_xclk,
d0418894 1660 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1661 .gart = {
1662 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1663 .set_page = &rs600_gart_set_page,
1664 },
4c87bc26
CK		 1665 .ring = {
1666 [RADEON_RING_TYPE_GFX_INDEX] = {
1667 .ib_execute = &evergreen_ring_ib_execute,
1668 .emit_fence = &r600_fence_ring_emit,
1669 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1670 .cs_parse = &evergreen_cs_parse,
f712812e
AD		 1671 .ring_test = &r600_ring_test,
1672 .ib_test = &r600_ib_test,
123bc183 1673 .is_lockup = &evergreen_gfx_is_lockup,
f93bdefe
AD		 1674 .get_rptr = &radeon_ring_generic_get_rptr,
1675 .get_wptr = &radeon_ring_generic_get_wptr,
1676 .set_wptr = &radeon_ring_generic_set_wptr,
233d1ad5
AD		 1677 },
1678 [R600_RING_TYPE_DMA_INDEX] = {
1679 .ib_execute = &evergreen_dma_ring_ib_execute,
1680 .emit_fence = &evergreen_dma_fence_ring_emit,
1681 .emit_semaphore = &r600_dma_semaphore_ring_emit,
d2ead3ea 1682 .cs_parse = &evergreen_dma_cs_parse,
233d1ad5
AD		 1683 .ring_test = &r600_dma_ring_test,
1684 .ib_test = &r600_dma_ib_test,
123bc183 1685 .is_lockup = &evergreen_dma_is_lockup,
f93bdefe
AD		 1686 .get_rptr = &radeon_ring_generic_get_rptr,
1687 .get_wptr = &radeon_ring_generic_get_wptr,
1688 .set_wptr = &radeon_ring_generic_set_wptr,
f2ba57b5
CK		 1689 },
1690 [R600_RING_TYPE_UVD_INDEX] = {
1691 .ib_execute = &r600_uvd_ib_execute,
1692 .emit_fence = &r600_uvd_fence_emit,
1693 .emit_semaphore = &r600_uvd_semaphore_emit,
1694 .cs_parse = &radeon_uvd_cs_parse,
1695 .ring_test = &r600_uvd_ring_test,
1696 .ib_test = &r600_uvd_ib_test,
1697 .is_lockup = &radeon_ring_test_lockup,
f93bdefe
AD		 1698 .get_rptr = &radeon_ring_generic_get_rptr,
1699 .get_wptr = &radeon_ring_generic_get_wptr,
1700 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 1701 }
1702 },
b35ea4ab
AD		 1703 .irq = {
1704 .set = &evergreen_irq_set,
1705 .process = &evergreen_irq_process,
1706 },
c79a49ca
AD		 1707 .display = {
1708 .bandwidth_update = &evergreen_bandwidth_update,
1709 .get_vblank_counter = &evergreen_get_vblank_counter,
1710 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1711 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1712 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1713 .hdmi_enable = &evergreen_hdmi_enable,
1714 .hdmi_setmode = &evergreen_hdmi_setmode,
c79a49ca 1715 },
27cd7769
AD		 1716 .copy = {
1717 .blit = &r600_copy_blit,
1718 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
233d1ad5
AD		 1719 .dma = &evergreen_copy_dma,
1720 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1721 .copy = &evergreen_copy_dma,
1722 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1723 },
9e6f3d02
AD		 1724 .surface = {
1725 .set_reg = r600_set_surface_reg,
1726 .clear_reg = r600_clear_surface_reg,
1727 },
901ea57d
AD		 1728 .hpd = {
1729 .init = &evergreen_hpd_init,
1730 .fini = &evergreen_hpd_fini,
1731 .sense = &evergreen_hpd_sense,
1732 .set_polarity = &evergreen_hpd_set_polarity,
1733 },
a02fa397
AD		 1734 .pm = {
1735 .misc = &evergreen_pm_misc,
1736 .prepare = &evergreen_pm_prepare,
1737 .finish = &evergreen_pm_finish,
27810fb2 1738 .init_profile = &btc_pm_init_profile,
a02fa397 1739 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1740 .get_engine_clock = &radeon_atom_get_engine_clock,
1741 .set_engine_clock = &radeon_atom_set_engine_clock,
1742 .get_memory_clock = &radeon_atom_get_memory_clock,
1743 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1744 .get_pcie_lanes = &r600_get_pcie_lanes,
1745 .set_pcie_lanes = &r600_set_pcie_lanes,
798bcf73 1746 .set_clock_gating = NULL,
a8b4925c 1747 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1748 .get_temperature = &evergreen_get_temp,
a02fa397 1749 },
6596afd4
AD		 1750 .dpm = {
1751 .init = &btc_dpm_init,
1752 .setup_asic = &btc_dpm_setup_asic,
1753 .enable = &btc_dpm_enable,
1754 .disable = &btc_dpm_disable,
e8a9539f 1755 .pre_set_power_state = &btc_dpm_pre_set_power_state,
6596afd4 1756 .set_power_state = &btc_dpm_set_power_state,
e8a9539f 1757 .post_set_power_state = &btc_dpm_post_set_power_state,
6596afd4
AD		 1758 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1759 .fini = &btc_dpm_fini,
e8a9539f
AD		 1760 .get_sclk = &btc_dpm_get_sclk,
1761 .get_mclk = &btc_dpm_get_mclk,
6596afd4 1762 .print_power_state = &rv770_dpm_print_power_state,
bd210d11 1763 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
6596afd4 1764 },
0f9e006c
AD		 1765 .pflip = {
1766 .pre_page_flip = &evergreen_pre_page_flip,
1767 .page_flip = &evergreen_page_flip,
1768 .post_page_flip = &evergreen_post_page_flip,
1769 },
a43b7665
AD		 1770};
1771
e3487629
AD		 1772static struct radeon_asic cayman_asic = {
1773 .init = &cayman_init,
1774 .fini = &cayman_fini,
1775 .suspend = &cayman_suspend,
1776 .resume = &cayman_resume,
e3487629
AD		 1777 .asic_reset = &cayman_asic_reset,
1778 .vga_set_state = &r600_vga_set_state,
54e88e06
AD		 1779 .ioctl_wait_idle = r600_ioctl_wait_idle,
1780 .gui_idle = &r600_gui_idle,
1781 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1782 .get_xclk = &rv770_get_xclk,
d0418894 1783 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
c5b3b850
AD		 1784 .gart = {
1785 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1786 .set_page = &rs600_gart_set_page,
1787 },
05b07147
CK		 1788 .vm = {
1789 .init = &cayman_vm_init,
1790 .fini = &cayman_vm_fini,
df160044 1791 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
05b07147
CK		 1792 .set_page = &cayman_vm_set_page,
1793 },
4c87bc26
CK		 1794 .ring = {
1795 [RADEON_RING_TYPE_GFX_INDEX] = {
721604a1
JG		 1796 .ib_execute = &cayman_ring_ib_execute,
1797 .ib_parse = &evergreen_ib_parse,
b40e7e16 1798 .emit_fence = &cayman_fence_ring_emit,
4c87bc26 1799 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1800 .cs_parse = &evergreen_cs_parse,
f712812e
AD		 1801 .ring_test = &r600_ring_test,
1802 .ib_test = &r600_ib_test,
123bc183 1803 .is_lockup = &cayman_gfx_is_lockup,
9b40e5d8 1804 .vm_flush = &cayman_vm_flush,
f93bdefe
AD		 1805 .get_rptr = &radeon_ring_generic_get_rptr,
1806 .get_wptr = &radeon_ring_generic_get_wptr,
1807 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 1808 },
1809 [CAYMAN_RING_TYPE_CP1_INDEX] = {
721604a1
JG		 1810 .ib_execute = &cayman_ring_ib_execute,
1811 .ib_parse = &evergreen_ib_parse,
b40e7e16 1812 .emit_fence = &cayman_fence_ring_emit,
4c87bc26 1813 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1814 .cs_parse = &evergreen_cs_parse,
f712812e
AD		 1815 .ring_test = &r600_ring_test,
1816 .ib_test = &r600_ib_test,
123bc183 1817 .is_lockup = &cayman_gfx_is_lockup,
9b40e5d8 1818 .vm_flush = &cayman_vm_flush,
f93bdefe
AD		 1819 .get_rptr = &radeon_ring_generic_get_rptr,
1820 .get_wptr = &radeon_ring_generic_get_wptr,
1821 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 1822 },
1823 [CAYMAN_RING_TYPE_CP2_INDEX] = {
721604a1
JG		 1824 .ib_execute = &cayman_ring_ib_execute,
1825 .ib_parse = &evergreen_ib_parse,
b40e7e16 1826 .emit_fence = &cayman_fence_ring_emit,
4c87bc26 1827 .emit_semaphore = &r600_semaphore_ring_emit,
eb0c19c5 1828 .cs_parse = &evergreen_cs_parse,
f712812e
AD		 1829 .ring_test = &r600_ring_test,
1830 .ib_test = &r600_ib_test,
123bc183 1831 .is_lockup = &cayman_gfx_is_lockup,
9b40e5d8 1832 .vm_flush = &cayman_vm_flush,
f93bdefe
AD		 1833 .get_rptr = &radeon_ring_generic_get_rptr,
1834 .get_wptr = &radeon_ring_generic_get_wptr,
1835 .set_wptr = &radeon_ring_generic_set_wptr,
f60cbd11
AD		 1836 },
1837 [R600_RING_TYPE_DMA_INDEX] = {
1838 .ib_execute = &cayman_dma_ring_ib_execute,
cd459e52 1839 .ib_parse = &evergreen_dma_ib_parse,
f60cbd11
AD		 1840 .emit_fence = &evergreen_dma_fence_ring_emit,
1841 .emit_semaphore = &r600_dma_semaphore_ring_emit,
d2ead3ea 1842 .cs_parse = &evergreen_dma_cs_parse,
f60cbd11
AD		 1843 .ring_test = &r600_dma_ring_test,
1844 .ib_test = &r600_dma_ib_test,
1845 .is_lockup = &cayman_dma_is_lockup,
1846 .vm_flush = &cayman_dma_vm_flush,
f93bdefe
AD		 1847 .get_rptr = &radeon_ring_generic_get_rptr,
1848 .get_wptr = &radeon_ring_generic_get_wptr,
1849 .set_wptr = &radeon_ring_generic_set_wptr,
f60cbd11
AD		 1850 },
1851 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1852 .ib_execute = &cayman_dma_ring_ib_execute,
cd459e52 1853 .ib_parse = &evergreen_dma_ib_parse,
f60cbd11
AD		 1854 .emit_fence = &evergreen_dma_fence_ring_emit,
1855 .emit_semaphore = &r600_dma_semaphore_ring_emit,
d2ead3ea 1856 .cs_parse = &evergreen_dma_cs_parse,
f60cbd11
AD		 1857 .ring_test = &r600_dma_ring_test,
1858 .ib_test = &r600_dma_ib_test,
1859 .is_lockup = &cayman_dma_is_lockup,
1860 .vm_flush = &cayman_dma_vm_flush,
f93bdefe
AD		 1861 .get_rptr = &radeon_ring_generic_get_rptr,
1862 .get_wptr = &radeon_ring_generic_get_wptr,
1863 .set_wptr = &radeon_ring_generic_set_wptr,
f2ba57b5
CK		 1864 },
1865 [R600_RING_TYPE_UVD_INDEX] = {
1866 .ib_execute = &r600_uvd_ib_execute,
1867 .emit_fence = &r600_uvd_fence_emit,
1868 .emit_semaphore = &cayman_uvd_semaphore_emit,
1869 .cs_parse = &radeon_uvd_cs_parse,
1870 .ring_test = &r600_uvd_ring_test,
1871 .ib_test = &r600_uvd_ib_test,
1872 .is_lockup = &radeon_ring_test_lockup,
f93bdefe
AD		 1873 .get_rptr = &radeon_ring_generic_get_rptr,
1874 .get_wptr = &radeon_ring_generic_get_wptr,
1875 .set_wptr = &radeon_ring_generic_set_wptr,
4c87bc26
CK		 1876 }
1877 },
b35ea4ab
AD		 1878 .irq = {
1879 .set = &evergreen_irq_set,
1880 .process = &evergreen_irq_process,
1881 },
c79a49ca
AD		 1882 .display = {
1883 .bandwidth_update = &evergreen_bandwidth_update,
1884 .get_vblank_counter = &evergreen_get_vblank_counter,
1885 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 1886 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 1887 .get_backlight_level = &atombios_get_backlight_level,
a973bea1
AD		 1888 .hdmi_enable = &evergreen_hdmi_enable,
1889 .hdmi_setmode = &evergreen_hdmi_setmode,
c79a49ca 1890 },
27cd7769
AD		 1891 .copy = {
1892 .blit = &r600_copy_blit,
1893 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
f60cbd11
AD		 1894 .dma = &evergreen_copy_dma,
1895 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 1896 .copy = &evergreen_copy_dma,
1897 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
27cd7769 1898 },
9e6f3d02
AD		 1899 .surface = {
1900 .set_reg = r600_set_surface_reg,
1901 .clear_reg = r600_clear_surface_reg,
1902 },
901ea57d
AD		 1903 .hpd = {
1904 .init = &evergreen_hpd_init,
1905 .fini = &evergreen_hpd_fini,
1906 .sense = &evergreen_hpd_sense,
1907 .set_polarity = &evergreen_hpd_set_polarity,
1908 },
a02fa397
AD		 1909 .pm = {
1910 .misc = &evergreen_pm_misc,
1911 .prepare = &evergreen_pm_prepare,
1912 .finish = &evergreen_pm_finish,
27810fb2 1913 .init_profile = &btc_pm_init_profile,
a02fa397 1914 .get_dynpm_state = &r600_pm_get_dynpm_state,
798bcf73
AD		 1915 .get_engine_clock = &radeon_atom_get_engine_clock,
1916 .set_engine_clock = &radeon_atom_set_engine_clock,
1917 .get_memory_clock = &radeon_atom_get_memory_clock,
1918 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 1919 .get_pcie_lanes = &r600_get_pcie_lanes,
1920 .set_pcie_lanes = &r600_set_pcie_lanes,
798bcf73 1921 .set_clock_gating = NULL,
a8b4925c 1922 .set_uvd_clocks = &evergreen_set_uvd_clocks,
6bd1c385 1923 .get_temperature = &evergreen_get_temp,
a02fa397 1924 },
69e0b57a
AD		 1925 .dpm = {
1926 .init = &ni_dpm_init,
1927 .setup_asic = &ni_dpm_setup_asic,
1928 .enable = &ni_dpm_enable,
1929 .disable = &ni_dpm_disable,
fee3d744 1930 .pre_set_power_state = &ni_dpm_pre_set_power_state,
69e0b57a 1931 .set_power_state = &ni_dpm_set_power_state,
fee3d744 1932 .post_set_power_state = &ni_dpm_post_set_power_state,
69e0b57a
AD		 1933 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1934 .fini = &ni_dpm_fini,
1935 .get_sclk = &ni_dpm_get_sclk,
1936 .get_mclk = &ni_dpm_get_mclk,
1937 .print_power_state = &ni_dpm_print_power_state,
1938 },
0f9e006c
AD		 1939 .pflip = {
1940 .pre_page_flip = &evergreen_pre_page_flip,
1941 .page_flip = &evergreen_page_flip,
1942 .post_page_flip = &evergreen_post_page_flip,
1943 },
e3487629
AD		 1944};
1945
be63fe8c
AD		 1946static struct radeon_asic trinity_asic = {
1947 .init = &cayman_init,
1948 .fini = &cayman_fini,
1949 .suspend = &cayman_suspend,
1950 .resume = &cayman_resume,
be63fe8c
AD		 1951 .asic_reset = &cayman_asic_reset,
1952 .vga_set_state = &r600_vga_set_state,
1953 .ioctl_wait_idle = r600_ioctl_wait_idle,
1954 .gui_idle = &r600_gui_idle,
1955 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 1956 .get_xclk = &r600_get_xclk,
d0418894 1957 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
be63fe8c
AD		 1958 .gart = {
1959 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1960 .set_page = &rs600_gart_set_page,
1961 },
05b07147
CK		 1962 .vm = {
1963 .init = &cayman_vm_init,
1964 .fini = &cayman_vm_fini,
df160044 1965 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
05b07147
CK		 1966 .set_page = &cayman_vm_set_page,
1967 },
be63fe8c
AD		 1968 .ring = {
1969 [RADEON_RING_TYPE_GFX_INDEX] = {
1970 .ib_execute = &cayman_ring_ib_execute,
1971 .ib_parse = &evergreen_ib_parse,
1972 .emit_fence = &cayman_fence_ring_emit,
1973 .emit_semaphore = &r600_semaphore_ring_emit,
1974 .cs_parse = &evergreen_cs_parse,
1975 .ring_test = &r600_ring_test,
1976 .ib_test = &r600_ib_test,
123bc183 1977 .is_lockup = &cayman_gfx_is_lockup,
9b40e5d8 1978 .vm_flush = &cayman_vm_flush,
f93bdefe
AD		 1979 .get_rptr = &radeon_ring_generic_get_rptr,
1980 .get_wptr = &radeon_ring_generic_get_wptr,
1981 .set_wptr = &radeon_ring_generic_set_wptr,
be63fe8c
AD		 1982 },
1983 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1984 .ib_execute = &cayman_ring_ib_execute,
1985 .ib_parse = &evergreen_ib_parse,
1986 .emit_fence = &cayman_fence_ring_emit,
1987 .emit_semaphore = &r600_semaphore_ring_emit,
1988 .cs_parse = &evergreen_cs_parse,
1989 .ring_test = &r600_ring_test,
1990 .ib_test = &r600_ib_test,
123bc183 1991 .is_lockup = &cayman_gfx_is_lockup,
9b40e5d8 1992 .vm_flush = &cayman_vm_flush,
f93bdefe
AD		 1993 .get_rptr = &radeon_ring_generic_get_rptr,
1994 .get_wptr = &radeon_ring_generic_get_wptr,
1995 .set_wptr = &radeon_ring_generic_set_wptr,
be63fe8c
AD		 1996 },
1997 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1998 .ib_execute = &cayman_ring_ib_execute,
1999 .ib_parse = &evergreen_ib_parse,
2000 .emit_fence = &cayman_fence_ring_emit,
2001 .emit_semaphore = &r600_semaphore_ring_emit,
2002 .cs_parse = &evergreen_cs_parse,
2003 .ring_test = &r600_ring_test,
2004 .ib_test = &r600_ib_test,
123bc183 2005 .is_lockup = &cayman_gfx_is_lockup,
9b40e5d8 2006 .vm_flush = &cayman_vm_flush,
f93bdefe
AD		 2007 .get_rptr = &radeon_ring_generic_get_rptr,
2008 .get_wptr = &radeon_ring_generic_get_wptr,
2009 .set_wptr = &radeon_ring_generic_set_wptr,
f60cbd11
AD		 2010 },
2011 [R600_RING_TYPE_DMA_INDEX] = {
2012 .ib_execute = &cayman_dma_ring_ib_execute,
cd459e52 2013 .ib_parse = &evergreen_dma_ib_parse,
f60cbd11
AD		 2014 .emit_fence = &evergreen_dma_fence_ring_emit,
2015 .emit_semaphore = &r600_dma_semaphore_ring_emit,
d2ead3ea 2016 .cs_parse = &evergreen_dma_cs_parse,
f60cbd11
AD		 2017 .ring_test = &r600_dma_ring_test,
2018 .ib_test = &r600_dma_ib_test,
2019 .is_lockup = &cayman_dma_is_lockup,
2020 .vm_flush = &cayman_dma_vm_flush,
f93bdefe
AD		 2021 .get_rptr = &radeon_ring_generic_get_rptr,
2022 .get_wptr = &radeon_ring_generic_get_wptr,
2023 .set_wptr = &radeon_ring_generic_set_wptr,
f60cbd11
AD		 2024 },
2025 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2026 .ib_execute = &cayman_dma_ring_ib_execute,
cd459e52 2027 .ib_parse = &evergreen_dma_ib_parse,
f60cbd11
AD		 2028 .emit_fence = &evergreen_dma_fence_ring_emit,
2029 .emit_semaphore = &r600_dma_semaphore_ring_emit,
d2ead3ea 2030 .cs_parse = &evergreen_dma_cs_parse,
f60cbd11
AD		 2031 .ring_test = &r600_dma_ring_test,
2032 .ib_test = &r600_dma_ib_test,
2033 .is_lockup = &cayman_dma_is_lockup,
2034 .vm_flush = &cayman_dma_vm_flush,
f93bdefe
AD		 2035 .get_rptr = &radeon_ring_generic_get_rptr,
2036 .get_wptr = &radeon_ring_generic_get_wptr,
2037 .set_wptr = &radeon_ring_generic_set_wptr,
f2ba57b5
CK		 2038 },
2039 [R600_RING_TYPE_UVD_INDEX] = {
2040 .ib_execute = &r600_uvd_ib_execute,
2041 .emit_fence = &r600_uvd_fence_emit,
2042 .emit_semaphore = &cayman_uvd_semaphore_emit,
2043 .cs_parse = &radeon_uvd_cs_parse,
2044 .ring_test = &r600_uvd_ring_test,
2045 .ib_test = &r600_uvd_ib_test,
2046 .is_lockup = &radeon_ring_test_lockup,
f93bdefe
AD		 2047 .get_rptr = &radeon_ring_generic_get_rptr,
2048 .get_wptr = &radeon_ring_generic_get_wptr,
2049 .set_wptr = &radeon_ring_generic_set_wptr,
be63fe8c
AD		 2050 }
2051 },
2052 .irq = {
2053 .set = &evergreen_irq_set,
2054 .process = &evergreen_irq_process,
2055 },
2056 .display = {
2057 .bandwidth_update = &dce6_bandwidth_update,
2058 .get_vblank_counter = &evergreen_get_vblank_counter,
2059 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 2060 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 2061 .get_backlight_level = &atombios_get_backlight_level,
be63fe8c
AD		 2062 },
2063 .copy = {
2064 .blit = &r600_copy_blit,
2065 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
f60cbd11
AD		 2066 .dma = &evergreen_copy_dma,
2067 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 2068 .copy = &evergreen_copy_dma,
2069 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
be63fe8c
AD		 2070 },
2071 .surface = {
2072 .set_reg = r600_set_surface_reg,
2073 .clear_reg = r600_clear_surface_reg,
2074 },
2075 .hpd = {
2076 .init = &evergreen_hpd_init,
2077 .fini = &evergreen_hpd_fini,
2078 .sense = &evergreen_hpd_sense,
2079 .set_polarity = &evergreen_hpd_set_polarity,
2080 },
2081 .pm = {
2082 .misc = &evergreen_pm_misc,
2083 .prepare = &evergreen_pm_prepare,
2084 .finish = &evergreen_pm_finish,
2085 .init_profile = &sumo_pm_init_profile,
2086 .get_dynpm_state = &r600_pm_get_dynpm_state,
2087 .get_engine_clock = &radeon_atom_get_engine_clock,
2088 .set_engine_clock = &radeon_atom_set_engine_clock,
2089 .get_memory_clock = NULL,
2090 .set_memory_clock = NULL,
2091 .get_pcie_lanes = NULL,
2092 .set_pcie_lanes = NULL,
2093 .set_clock_gating = NULL,
23d33ba3 2094 .set_uvd_clocks = &sumo_set_uvd_clocks,
29a15221 2095 .get_temperature = &tn_get_temp,
be63fe8c 2096 },
d70229f7
AD		 2097 .dpm = {
2098 .init = &trinity_dpm_init,
2099 .setup_asic = &trinity_dpm_setup_asic,
2100 .enable = &trinity_dpm_enable,
2101 .disable = &trinity_dpm_disable,
a284c48a 2102 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
d70229f7 2103 .set_power_state = &trinity_dpm_set_power_state,
a284c48a 2104 .post_set_power_state = &trinity_dpm_post_set_power_state,
d70229f7
AD		 2105 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
2106 .fini = &trinity_dpm_fini,
2107 .get_sclk = &trinity_dpm_get_sclk,
2108 .get_mclk = &trinity_dpm_get_mclk,
2109 .print_power_state = &trinity_dpm_print_power_state,
2110 },
be63fe8c
AD		 2111 .pflip = {
2112 .pre_page_flip = &evergreen_pre_page_flip,
2113 .page_flip = &evergreen_page_flip,
2114 .post_page_flip = &evergreen_post_page_flip,
2115 },
2116};
2117
02779c08
AD		 2118static struct radeon_asic si_asic = {
2119 .init = &si_init,
2120 .fini = &si_fini,
2121 .suspend = &si_suspend,
2122 .resume = &si_resume,
02779c08
AD		 2123 .asic_reset = &si_asic_reset,
2124 .vga_set_state = &r600_vga_set_state,
2125 .ioctl_wait_idle = r600_ioctl_wait_idle,
2126 .gui_idle = &r600_gui_idle,
2127 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
454d2e2a 2128 .get_xclk = &si_get_xclk,
d0418894 2129 .get_gpu_clock_counter = &si_get_gpu_clock_counter,
02779c08
AD		 2130 .gart = {
2131 .tlb_flush = &si_pcie_gart_tlb_flush,
2132 .set_page = &rs600_gart_set_page,
2133 },
05b07147
CK		 2134 .vm = {
2135 .init = &si_vm_init,
2136 .fini = &si_vm_fini,
df160044 2137 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
82ffd92b 2138 .set_page = &si_vm_set_page,
05b07147 2139 },
02779c08
AD		 2140 .ring = {
2141 [RADEON_RING_TYPE_GFX_INDEX] = {
2142 .ib_execute = &si_ring_ib_execute,
2143 .ib_parse = &si_ib_parse,
2144 .emit_fence = &si_fence_ring_emit,
2145 .emit_semaphore = &r600_semaphore_ring_emit,
2146 .cs_parse = NULL,
2147 .ring_test = &r600_ring_test,
2148 .ib_test = &r600_ib_test,
123bc183 2149 .is_lockup = &si_gfx_is_lockup,
ee60e29f 2150 .vm_flush = &si_vm_flush,
f93bdefe
AD		 2151 .get_rptr = &radeon_ring_generic_get_rptr,
2152 .get_wptr = &radeon_ring_generic_get_wptr,
2153 .set_wptr = &radeon_ring_generic_set_wptr,
02779c08
AD		 2154 },
2155 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2156 .ib_execute = &si_ring_ib_execute,
2157 .ib_parse = &si_ib_parse,
2158 .emit_fence = &si_fence_ring_emit,
2159 .emit_semaphore = &r600_semaphore_ring_emit,
2160 .cs_parse = NULL,
2161 .ring_test = &r600_ring_test,
2162 .ib_test = &r600_ib_test,
123bc183 2163 .is_lockup = &si_gfx_is_lockup,
ee60e29f 2164 .vm_flush = &si_vm_flush,
f93bdefe
AD		 2165 .get_rptr = &radeon_ring_generic_get_rptr,
2166 .get_wptr = &radeon_ring_generic_get_wptr,
2167 .set_wptr = &radeon_ring_generic_set_wptr,
02779c08
AD		 2168 },
2169 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2170 .ib_execute = &si_ring_ib_execute,
2171 .ib_parse = &si_ib_parse,
2172 .emit_fence = &si_fence_ring_emit,
2173 .emit_semaphore = &r600_semaphore_ring_emit,
2174 .cs_parse = NULL,
2175 .ring_test = &r600_ring_test,
2176 .ib_test = &r600_ib_test,
123bc183 2177 .is_lockup = &si_gfx_is_lockup,
ee60e29f 2178 .vm_flush = &si_vm_flush,
f93bdefe
AD		 2179 .get_rptr = &radeon_ring_generic_get_rptr,
2180 .get_wptr = &radeon_ring_generic_get_wptr,
2181 .set_wptr = &radeon_ring_generic_set_wptr,
8c5fd7ef
AD		 2182 },
2183 [R600_RING_TYPE_DMA_INDEX] = {
2184 .ib_execute = &cayman_dma_ring_ib_execute,
cd459e52 2185 .ib_parse = &evergreen_dma_ib_parse,
8c5fd7ef
AD		 2186 .emit_fence = &evergreen_dma_fence_ring_emit,
2187 .emit_semaphore = &r600_dma_semaphore_ring_emit,
2188 .cs_parse = NULL,
2189 .ring_test = &r600_dma_ring_test,
2190 .ib_test = &r600_dma_ib_test,
123bc183 2191 .is_lockup = &si_dma_is_lockup,
8c5fd7ef 2192 .vm_flush = &si_dma_vm_flush,
f93bdefe
AD		 2193 .get_rptr = &radeon_ring_generic_get_rptr,
2194 .get_wptr = &radeon_ring_generic_get_wptr,
2195 .set_wptr = &radeon_ring_generic_set_wptr,
8c5fd7ef
AD		 2196 },
2197 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2198 .ib_execute = &cayman_dma_ring_ib_execute,
cd459e52 2199 .ib_parse = &evergreen_dma_ib_parse,
8c5fd7ef
AD		 2200 .emit_fence = &evergreen_dma_fence_ring_emit,
2201 .emit_semaphore = &r600_dma_semaphore_ring_emit,
2202 .cs_parse = NULL,
2203 .ring_test = &r600_dma_ring_test,
2204 .ib_test = &r600_dma_ib_test,
123bc183 2205 .is_lockup = &si_dma_is_lockup,
8c5fd7ef 2206 .vm_flush = &si_dma_vm_flush,
f93bdefe
AD		 2207 .get_rptr = &radeon_ring_generic_get_rptr,
2208 .get_wptr = &radeon_ring_generic_get_wptr,
2209 .set_wptr = &radeon_ring_generic_set_wptr,
f2ba57b5
CK		 2210 },
2211 [R600_RING_TYPE_UVD_INDEX] = {
2212 .ib_execute = &r600_uvd_ib_execute,
2213 .emit_fence = &r600_uvd_fence_emit,
2214 .emit_semaphore = &cayman_uvd_semaphore_emit,
2215 .cs_parse = &radeon_uvd_cs_parse,
2216 .ring_test = &r600_uvd_ring_test,
2217 .ib_test = &r600_uvd_ib_test,
2218 .is_lockup = &radeon_ring_test_lockup,
f93bdefe
AD		 2219 .get_rptr = &radeon_ring_generic_get_rptr,
2220 .get_wptr = &radeon_ring_generic_get_wptr,
2221 .set_wptr = &radeon_ring_generic_set_wptr,
02779c08
AD		 2222 }
2223 },
2224 .irq = {
2225 .set = &si_irq_set,
2226 .process = &si_irq_process,
2227 },
2228 .display = {
2229 .bandwidth_update = &dce6_bandwidth_update,
2230 .get_vblank_counter = &evergreen_get_vblank_counter,
2231 .wait_for_vblank = &dce4_wait_for_vblank,
37e9b6a6 2232 .set_backlight_level = &atombios_set_backlight_level,
6d92f81d 2233 .get_backlight_level = &atombios_get_backlight_level,
02779c08
AD		 2234 },
2235 .copy = {
2236 .blit = NULL,
2237 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
8c5fd7ef
AD		 2238 .dma = &si_copy_dma,
2239 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2d6cc729
AD		 2240 .copy = &si_copy_dma,
2241 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
02779c08
AD		 2242 },
2243 .surface = {
2244 .set_reg = r600_set_surface_reg,
2245 .clear_reg = r600_clear_surface_reg,
2246 },
2247 .hpd = {
2248 .init = &evergreen_hpd_init,
2249 .fini = &evergreen_hpd_fini,
2250 .sense = &evergreen_hpd_sense,
2251 .set_polarity = &evergreen_hpd_set_polarity,
2252 },
2253 .pm = {
2254 .misc = &evergreen_pm_misc,
2255 .prepare = &evergreen_pm_prepare,
2256 .finish = &evergreen_pm_finish,
2257 .init_profile = &sumo_pm_init_profile,
2258 .get_dynpm_state = &r600_pm_get_dynpm_state,
2259 .get_engine_clock = &radeon_atom_get_engine_clock,
2260 .set_engine_clock = &radeon_atom_set_engine_clock,
2261 .get_memory_clock = &radeon_atom_get_memory_clock,
2262 .set_memory_clock = &radeon_atom_set_memory_clock,
55b615ae
AD		 2263 .get_pcie_lanes = &r600_get_pcie_lanes,
2264 .set_pcie_lanes = &r600_set_pcie_lanes,
02779c08 2265 .set_clock_gating = NULL,
2539eb02 2266 .set_uvd_clocks = &si_set_uvd_clocks,
6bd1c385 2267 .get_temperature = &si_get_temp,
02779c08 2268 },
a9e61410
AD		 2269 .dpm = {
2270 .init = &si_dpm_init,
2271 .setup_asic = &si_dpm_setup_asic,
2272 .enable = &si_dpm_enable,
2273 .disable = &si_dpm_disable,
2274 .pre_set_power_state = &si_dpm_pre_set_power_state,
2275 .set_power_state = &si_dpm_set_power_state,
2276 .post_set_power_state = &si_dpm_post_set_power_state,
2277 .display_configuration_changed = &si_dpm_display_configuration_changed,
2278 .fini = &si_dpm_fini,
2279 .get_sclk = &ni_dpm_get_sclk,
2280 .get_mclk = &ni_dpm_get_mclk,
2281 .print_power_state = &ni_dpm_print_power_state,
2282 },
02779c08
AD		 2283 .pflip = {
2284 .pre_page_flip = &evergreen_pre_page_flip,
2285 .page_flip = &evergreen_page_flip,
2286 .post_page_flip = &evergreen_post_page_flip,
2287 },
2288};
2289
0672e27b
AD		 2290static struct radeon_asic ci_asic = {
2291 .init = &cik_init,
2292 .fini = &cik_fini,
2293 .suspend = &cik_suspend,
2294 .resume = &cik_resume,
2295 .asic_reset = &cik_asic_reset,
2296 .vga_set_state = &r600_vga_set_state,
2297 .ioctl_wait_idle = NULL,
2298 .gui_idle = &r600_gui_idle,
2299 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2300 .get_xclk = &cik_get_xclk,
2301 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2302 .gart = {
2303 .tlb_flush = &cik_pcie_gart_tlb_flush,
2304 .set_page = &rs600_gart_set_page,
2305 },
2306 .vm = {
2307 .init = &cik_vm_init,
2308 .fini = &cik_vm_fini,
2309 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2310 .set_page = &cik_vm_set_page,
2311 },
2312 .ring = {
2313 [RADEON_RING_TYPE_GFX_INDEX] = {
2314 .ib_execute = &cik_ring_ib_execute,
2315 .ib_parse = &cik_ib_parse,
2316 .emit_fence = &cik_fence_gfx_ring_emit,
2317 .emit_semaphore = &cik_semaphore_ring_emit,
2318 .cs_parse = NULL,
2319 .ring_test = &cik_ring_test,
2320 .ib_test = &cik_ib_test,
2321 .is_lockup = &cik_gfx_is_lockup,
2322 .vm_flush = &cik_vm_flush,
2323 .get_rptr = &radeon_ring_generic_get_rptr,
2324 .get_wptr = &radeon_ring_generic_get_wptr,
2325 .set_wptr = &radeon_ring_generic_set_wptr,
2326 },
2327 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2328 .ib_execute = &cik_ring_ib_execute,
2329 .ib_parse = &cik_ib_parse,
2330 .emit_fence = &cik_fence_compute_ring_emit,
2331 .emit_semaphore = &cik_semaphore_ring_emit,
2332 .cs_parse = NULL,
2333 .ring_test = &cik_ring_test,
2334 .ib_test = &cik_ib_test,
2335 .is_lockup = &cik_gfx_is_lockup,
2336 .vm_flush = &cik_vm_flush,
2337 .get_rptr = &cik_compute_ring_get_rptr,
2338 .get_wptr = &cik_compute_ring_get_wptr,
2339 .set_wptr = &cik_compute_ring_set_wptr,
2340 },
2341 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2342 .ib_execute = &cik_ring_ib_execute,
2343 .ib_parse = &cik_ib_parse,
2344 .emit_fence = &cik_fence_compute_ring_emit,
2345 .emit_semaphore = &cik_semaphore_ring_emit,
2346 .cs_parse = NULL,
2347 .ring_test = &cik_ring_test,
2348 .ib_test = &cik_ib_test,
2349 .is_lockup = &cik_gfx_is_lockup,
2350 .vm_flush = &cik_vm_flush,
2351 .get_rptr = &cik_compute_ring_get_rptr,
2352 .get_wptr = &cik_compute_ring_get_wptr,
2353 .set_wptr = &cik_compute_ring_set_wptr,
2354 },
2355 [R600_RING_TYPE_DMA_INDEX] = {
2356 .ib_execute = &cik_sdma_ring_ib_execute,
2357 .ib_parse = &cik_ib_parse,
2358 .emit_fence = &cik_sdma_fence_ring_emit,
2359 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2360 .cs_parse = NULL,
2361 .ring_test = &cik_sdma_ring_test,
2362 .ib_test = &cik_sdma_ib_test,
2363 .is_lockup = &cik_sdma_is_lockup,
2364 .vm_flush = &cik_dma_vm_flush,
2365 .get_rptr = &radeon_ring_generic_get_rptr,
2366 .get_wptr = &radeon_ring_generic_get_wptr,
2367 .set_wptr = &radeon_ring_generic_set_wptr,
2368 },
2369 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2370 .ib_execute = &cik_sdma_ring_ib_execute,
2371 .ib_parse = &cik_ib_parse,
2372 .emit_fence = &cik_sdma_fence_ring_emit,
2373 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2374 .cs_parse = NULL,
2375 .ring_test = &cik_sdma_ring_test,
2376 .ib_test = &cik_sdma_ib_test,
2377 .is_lockup = &cik_sdma_is_lockup,
2378 .vm_flush = &cik_dma_vm_flush,
2379 .get_rptr = &radeon_ring_generic_get_rptr,
2380 .get_wptr = &radeon_ring_generic_get_wptr,
2381 .set_wptr = &radeon_ring_generic_set_wptr,
2382 },
2383 [R600_RING_TYPE_UVD_INDEX] = {
2384 .ib_execute = &r600_uvd_ib_execute,
2385 .emit_fence = &r600_uvd_fence_emit,
2386 .emit_semaphore = &cayman_uvd_semaphore_emit,
2387 .cs_parse = &radeon_uvd_cs_parse,
2388 .ring_test = &r600_uvd_ring_test,
2389 .ib_test = &r600_uvd_ib_test,
2390 .is_lockup = &radeon_ring_test_lockup,
2391 .get_rptr = &radeon_ring_generic_get_rptr,
2392 .get_wptr = &radeon_ring_generic_get_wptr,
2393 .set_wptr = &radeon_ring_generic_set_wptr,
2394 }
2395 },
2396 .irq = {
2397 .set = &cik_irq_set,
2398 .process = &cik_irq_process,
2399 },
2400 .display = {
2401 .bandwidth_update = &dce8_bandwidth_update,
2402 .get_vblank_counter = &evergreen_get_vblank_counter,
2403 .wait_for_vblank = &dce4_wait_for_vblank,
2404 },
2405 .copy = {
2406 .blit = NULL,
2407 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2408 .dma = &cik_copy_dma,
2409 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2410 .copy = &cik_copy_dma,
2411 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2412 },
2413 .surface = {
2414 .set_reg = r600_set_surface_reg,
2415 .clear_reg = r600_clear_surface_reg,
2416 },
2417 .hpd = {
2418 .init = &evergreen_hpd_init,
2419 .fini = &evergreen_hpd_fini,
2420 .sense = &evergreen_hpd_sense,
2421 .set_polarity = &evergreen_hpd_set_polarity,
2422 },
2423 .pm = {
2424 .misc = &evergreen_pm_misc,
2425 .prepare = &evergreen_pm_prepare,
2426 .finish = &evergreen_pm_finish,
2427 .init_profile = &sumo_pm_init_profile,
2428 .get_dynpm_state = &r600_pm_get_dynpm_state,
2429 .get_engine_clock = &radeon_atom_get_engine_clock,
2430 .set_engine_clock = &radeon_atom_set_engine_clock,
2431 .get_memory_clock = &radeon_atom_get_memory_clock,
2432 .set_memory_clock = &radeon_atom_set_memory_clock,
2433 .get_pcie_lanes = NULL,
2434 .set_pcie_lanes = NULL,
2435 .set_clock_gating = NULL,
2436 .set_uvd_clocks = &cik_set_uvd_clocks,
2437 },
2438 .pflip = {
2439 .pre_page_flip = &evergreen_pre_page_flip,
2440 .page_flip = &evergreen_page_flip,
2441 .post_page_flip = &evergreen_post_page_flip,
2442 },
2443};
2444
2445static struct radeon_asic kv_asic = {
2446 .init = &cik_init,
2447 .fini = &cik_fini,
2448 .suspend = &cik_suspend,
2449 .resume = &cik_resume,
2450 .asic_reset = &cik_asic_reset,
2451 .vga_set_state = &r600_vga_set_state,
2452 .ioctl_wait_idle = NULL,
2453 .gui_idle = &r600_gui_idle,
2454 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2455 .get_xclk = &cik_get_xclk,
2456 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2457 .gart = {
2458 .tlb_flush = &cik_pcie_gart_tlb_flush,
2459 .set_page = &rs600_gart_set_page,
2460 },
2461 .vm = {
2462 .init = &cik_vm_init,
2463 .fini = &cik_vm_fini,
2464 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2465 .set_page = &cik_vm_set_page,
2466 },
2467 .ring = {
2468 [RADEON_RING_TYPE_GFX_INDEX] = {
2469 .ib_execute = &cik_ring_ib_execute,
2470 .ib_parse = &cik_ib_parse,
2471 .emit_fence = &cik_fence_gfx_ring_emit,
2472 .emit_semaphore = &cik_semaphore_ring_emit,
2473 .cs_parse = NULL,
2474 .ring_test = &cik_ring_test,
2475 .ib_test = &cik_ib_test,
2476 .is_lockup = &cik_gfx_is_lockup,
2477 .vm_flush = &cik_vm_flush,
2478 .get_rptr = &radeon_ring_generic_get_rptr,
2479 .get_wptr = &radeon_ring_generic_get_wptr,
2480 .set_wptr = &radeon_ring_generic_set_wptr,
2481 },
2482 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2483 .ib_execute = &cik_ring_ib_execute,
2484 .ib_parse = &cik_ib_parse,
2485 .emit_fence = &cik_fence_compute_ring_emit,
2486 .emit_semaphore = &cik_semaphore_ring_emit,
2487 .cs_parse = NULL,
2488 .ring_test = &cik_ring_test,
2489 .ib_test = &cik_ib_test,
2490 .is_lockup = &cik_gfx_is_lockup,
2491 .vm_flush = &cik_vm_flush,
2492 .get_rptr = &cik_compute_ring_get_rptr,
2493 .get_wptr = &cik_compute_ring_get_wptr,
2494 .set_wptr = &cik_compute_ring_set_wptr,
2495 },
2496 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2497 .ib_execute = &cik_ring_ib_execute,
2498 .ib_parse = &cik_ib_parse,
2499 .emit_fence = &cik_fence_compute_ring_emit,
2500 .emit_semaphore = &cik_semaphore_ring_emit,
2501 .cs_parse = NULL,
2502 .ring_test = &cik_ring_test,
2503 .ib_test = &cik_ib_test,
2504 .is_lockup = &cik_gfx_is_lockup,
2505 .vm_flush = &cik_vm_flush,
2506 .get_rptr = &cik_compute_ring_get_rptr,
2507 .get_wptr = &cik_compute_ring_get_wptr,
2508 .set_wptr = &cik_compute_ring_set_wptr,
2509 },
2510 [R600_RING_TYPE_DMA_INDEX] = {
2511 .ib_execute = &cik_sdma_ring_ib_execute,
2512 .ib_parse = &cik_ib_parse,
2513 .emit_fence = &cik_sdma_fence_ring_emit,
2514 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2515 .cs_parse = NULL,
2516 .ring_test = &cik_sdma_ring_test,
2517 .ib_test = &cik_sdma_ib_test,
2518 .is_lockup = &cik_sdma_is_lockup,
2519 .vm_flush = &cik_dma_vm_flush,
2520 .get_rptr = &radeon_ring_generic_get_rptr,
2521 .get_wptr = &radeon_ring_generic_get_wptr,
2522 .set_wptr = &radeon_ring_generic_set_wptr,
2523 },
2524 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2525 .ib_execute = &cik_sdma_ring_ib_execute,
2526 .ib_parse = &cik_ib_parse,
2527 .emit_fence = &cik_sdma_fence_ring_emit,
2528 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2529 .cs_parse = NULL,
2530 .ring_test = &cik_sdma_ring_test,
2531 .ib_test = &cik_sdma_ib_test,
2532 .is_lockup = &cik_sdma_is_lockup,
2533 .vm_flush = &cik_dma_vm_flush,
2534 .get_rptr = &radeon_ring_generic_get_rptr,
2535 .get_wptr = &radeon_ring_generic_get_wptr,
2536 .set_wptr = &radeon_ring_generic_set_wptr,
2537 },
2538 [R600_RING_TYPE_UVD_INDEX] = {
2539 .ib_execute = &r600_uvd_ib_execute,
2540 .emit_fence = &r600_uvd_fence_emit,
2541 .emit_semaphore = &cayman_uvd_semaphore_emit,
2542 .cs_parse = &radeon_uvd_cs_parse,
2543 .ring_test = &r600_uvd_ring_test,
2544 .ib_test = &r600_uvd_ib_test,
2545 .is_lockup = &radeon_ring_test_lockup,
2546 .get_rptr = &radeon_ring_generic_get_rptr,
2547 .get_wptr = &radeon_ring_generic_get_wptr,
2548 .set_wptr = &radeon_ring_generic_set_wptr,
2549 }
2550 },
2551 .irq = {
2552 .set = &cik_irq_set,
2553 .process = &cik_irq_process,
2554 },
2555 .display = {
2556 .bandwidth_update = &dce8_bandwidth_update,
2557 .get_vblank_counter = &evergreen_get_vblank_counter,
2558 .wait_for_vblank = &dce4_wait_for_vblank,
2559 },
2560 .copy = {
2561 .blit = NULL,
2562 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2563 .dma = &cik_copy_dma,
2564 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2565 .copy = &cik_copy_dma,
2566 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2567 },
2568 .surface = {
2569 .set_reg = r600_set_surface_reg,
2570 .clear_reg = r600_clear_surface_reg,
2571 },
2572 .hpd = {
2573 .init = &evergreen_hpd_init,
2574 .fini = &evergreen_hpd_fini,
2575 .sense = &evergreen_hpd_sense,
2576 .set_polarity = &evergreen_hpd_set_polarity,
2577 },
2578 .pm = {
2579 .misc = &evergreen_pm_misc,
2580 .prepare = &evergreen_pm_prepare,
2581 .finish = &evergreen_pm_finish,
2582 .init_profile = &sumo_pm_init_profile,
2583 .get_dynpm_state = &r600_pm_get_dynpm_state,
2584 .get_engine_clock = &radeon_atom_get_engine_clock,
2585 .set_engine_clock = &radeon_atom_set_engine_clock,
2586 .get_memory_clock = &radeon_atom_get_memory_clock,
2587 .set_memory_clock = &radeon_atom_set_memory_clock,
2588 .get_pcie_lanes = NULL,
2589 .set_pcie_lanes = NULL,
2590 .set_clock_gating = NULL,
2591 .set_uvd_clocks = &cik_set_uvd_clocks,
2592 },
2593 .pflip = {
2594 .pre_page_flip = &evergreen_pre_page_flip,
2595 .page_flip = &evergreen_page_flip,
2596 .post_page_flip = &evergreen_post_page_flip,
2597 },
2598};
2599
abf1dc67
AD		 2600/**
2601 * radeon_asic_init - register asic specific callbacks
2602 *
2603 * @rdev: radeon device pointer
2604 *
2605 * Registers the appropriate asic specific callbacks for each
2606 * chip family. Also sets other asics specific info like the number
2607 * of crtcs and the register aperture accessors (all asics).
2608 * Returns 0 for success.
2609 */
0a10c851
DV		 2610int radeon_asic_init(struct radeon_device *rdev)
2611{
2612 radeon_register_accessor_init(rdev);
ba7e05e9
AD		 2613
2614 /* set the number of crtcs */
2615 if (rdev->flags & RADEON_SINGLE_CRTC)
2616 rdev->num_crtc = 1;
2617 else
2618 rdev->num_crtc = 2;
2619
948bee3f
AD		 2620 rdev->has_uvd = false;
2621
0a10c851
DV		 2622 switch (rdev->family) {
2623 case CHIP_R100:
2624 case CHIP_RV100:
2625 case CHIP_RS100:
2626 case CHIP_RV200:
2627 case CHIP_RS200:
2628 rdev->asic = &r100_asic;
2629 break;
2630 case CHIP_R200:
2631 case CHIP_RV250:
2632 case CHIP_RS300:
2633 case CHIP_RV280:
2634 rdev->asic = &r200_asic;
2635 break;
2636 case CHIP_R300:
2637 case CHIP_R350:
2638 case CHIP_RV350:
2639 case CHIP_RV380:
2640 if (rdev->flags & RADEON_IS_PCIE)
2641 rdev->asic = &r300_asic_pcie;
2642 else
2643 rdev->asic = &r300_asic;
2644 break;
2645 case CHIP_R420:
2646 case CHIP_R423:
2647 case CHIP_RV410:
2648 rdev->asic = &r420_asic;
07bb084c
AD		 2649 /* handle macs */
2650 if (rdev->bios == NULL) {
798bcf73
AD		 2651 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2652 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2653 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2654 rdev->asic->pm.set_memory_clock = NULL;
37e9b6a6 2655 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
07bb084c 2656 }
0a10c851
DV		 2657 break;
2658 case CHIP_RS400:
2659 case CHIP_RS480:
2660 rdev->asic = &rs400_asic;
2661 break;
2662 case CHIP_RS600:
2663 rdev->asic = &rs600_asic;
2664 break;
2665 case CHIP_RS690:
2666 case CHIP_RS740:
2667 rdev->asic = &rs690_asic;
2668 break;
2669 case CHIP_RV515:
2670 rdev->asic = &rv515_asic;
2671 break;
2672 case CHIP_R520:
2673 case CHIP_RV530:
2674 case CHIP_RV560:
2675 case CHIP_RV570:
2676 case CHIP_R580:
2677 rdev->asic = &r520_asic;
2678 break;
2679 case CHIP_R600:
ca361b65
AD		 2680 rdev->asic = &r600_asic;
2681 break;
0a10c851
DV		 2682 case CHIP_RV610:
2683 case CHIP_RV630:
2684 case CHIP_RV620:
2685 case CHIP_RV635:
2686 case CHIP_RV670:
ca361b65
AD		 2687 rdev->asic = &rv6xx_asic;
2688 rdev->has_uvd = true;
f47299c5 2689 break;
0a10c851
DV		 2690 case CHIP_RS780:
2691 case CHIP_RS880:
f47299c5 2692 rdev->asic = &rs780_asic;
948bee3f 2693 rdev->has_uvd = true;
0a10c851
DV		 2694 break;
2695 case CHIP_RV770:
2696 case CHIP_RV730:
2697 case CHIP_RV710:
2698 case CHIP_RV740:
2699 rdev->asic = &rv770_asic;
948bee3f 2700 rdev->has_uvd = true;
0a10c851
DV		 2701 break;
2702 case CHIP_CEDAR:
2703 case CHIP_REDWOOD:
2704 case CHIP_JUNIPER:
2705 case CHIP_CYPRESS:
2706 case CHIP_HEMLOCK:
ba7e05e9
AD		 2707 /* set num crtcs */
2708 if (rdev->family == CHIP_CEDAR)
2709 rdev->num_crtc = 4;
2710 else
2711 rdev->num_crtc = 6;
0a10c851 2712 rdev->asic = &evergreen_asic;
948bee3f 2713 rdev->has_uvd = true;
0a10c851 2714 break;
958261d1 2715 case CHIP_PALM:
89da5a37
AD		 2716 case CHIP_SUMO:
2717 case CHIP_SUMO2:
958261d1 2718 rdev->asic = &sumo_asic;
948bee3f 2719 rdev->has_uvd = true;
958261d1 2720 break;
a43b7665
AD		 2721 case CHIP_BARTS:
2722 case CHIP_TURKS:
2723 case CHIP_CAICOS:
ba7e05e9
AD		 2724 /* set num crtcs */
2725 if (rdev->family == CHIP_CAICOS)
2726 rdev->num_crtc = 4;
2727 else
2728 rdev->num_crtc = 6;
a43b7665 2729 rdev->asic = &btc_asic;
948bee3f 2730 rdev->has_uvd = true;
a43b7665 2731 break;
e3487629
AD		 2732 case CHIP_CAYMAN:
2733 rdev->asic = &cayman_asic;
ba7e05e9
AD		 2734 /* set num crtcs */
2735 rdev->num_crtc = 6;
948bee3f 2736 rdev->has_uvd = true;
e3487629 2737 break;
be63fe8c
AD		 2738 case CHIP_ARUBA:
2739 rdev->asic = &trinity_asic;
2740 /* set num crtcs */
2741 rdev->num_crtc = 4;
948bee3f 2742 rdev->has_uvd = true;
be63fe8c 2743 break;
02779c08
AD		 2744 case CHIP_TAHITI:
2745 case CHIP_PITCAIRN:
2746 case CHIP_VERDE:
e737a14c 2747 case CHIP_OLAND:
86a45cac 2748 case CHIP_HAINAN:
02779c08
AD		 2749 rdev->asic = &si_asic;
2750 /* set num crtcs */
86a45cac
AD		 2751 if (rdev->family == CHIP_HAINAN)
2752 rdev->num_crtc = 0;
2753 else if (rdev->family == CHIP_OLAND)
e737a14c
AD		 2754 rdev->num_crtc = 2;
2755 else
2756 rdev->num_crtc = 6;
948bee3f
AD		 2757 if (rdev->family == CHIP_HAINAN)
2758 rdev->has_uvd = false;
2759 else
2760 rdev->has_uvd = true;
02779c08 2761 break;
0672e27b
AD		 2762 case CHIP_BONAIRE:
2763 rdev->asic = &ci_asic;
2764 rdev->num_crtc = 6;
2765 break;
2766 case CHIP_KAVERI:
2767 case CHIP_KABINI:
2768 rdev->asic = &kv_asic;
2769 /* set num crtcs */
2770 if (rdev->family == CHIP_KAVERI)
2771 rdev->num_crtc = 4;
2772 else
2773 rdev->num_crtc = 2;
2774 break;
0a10c851
DV		 2775 default:
2776 /* FIXME: not supported yet */
2777 return -EINVAL;
2778 }
2779
2780 if (rdev->flags & RADEON_IS_IGP) {
798bcf73
AD		 2781 rdev->asic->pm.get_memory_clock = NULL;
2782 rdev->asic->pm.set_memory_clock = NULL;
0a10c851
DV		 2783 }
2784
2785 return 0;
2786}
2787
Linux kernel - Deliverables
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