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0a10c851 DV |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | ||
29 | #include <linux/console.h> | |
30 | #include <drm/drmP.h> | |
31 | #include <drm/drm_crtc_helper.h> | |
32 | #include <drm/radeon_drm.h> | |
33 | #include <linux/vgaarb.h> | |
34 | #include <linux/vga_switcheroo.h> | |
35 | #include "radeon_reg.h" | |
36 | #include "radeon.h" | |
37 | #include "radeon_asic.h" | |
38 | #include "atom.h" | |
39 | ||
40 | /* | |
41 | * Registers accessors functions. | |
42 | */ | |
abf1dc67 AD |
43 | /** |
44 | * radeon_invalid_rreg - dummy reg read function | |
45 | * | |
46 | * @rdev: radeon device pointer | |
47 | * @reg: offset of register | |
48 | * | |
49 | * Dummy register read function. Used for register blocks | |
50 | * that certain asics don't have (all asics). | |
51 | * Returns the value in the register. | |
52 | */ | |
0a10c851 DV |
53 | static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) |
54 | { | |
55 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); | |
56 | BUG_ON(1); | |
57 | return 0; | |
58 | } | |
59 | ||
abf1dc67 AD |
60 | /** |
61 | * radeon_invalid_wreg - dummy reg write function | |
62 | * | |
63 | * @rdev: radeon device pointer | |
64 | * @reg: offset of register | |
65 | * @v: value to write to the register | |
66 | * | |
67 | * Dummy register read function. Used for register blocks | |
68 | * that certain asics don't have (all asics). | |
69 | */ | |
0a10c851 DV |
70 | static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
71 | { | |
72 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", | |
73 | reg, v); | |
74 | BUG_ON(1); | |
75 | } | |
76 | ||
abf1dc67 AD |
77 | /** |
78 | * radeon_register_accessor_init - sets up the register accessor callbacks | |
79 | * | |
80 | * @rdev: radeon device pointer | |
81 | * | |
82 | * Sets up the register accessor callbacks for various register | |
83 | * apertures. Not all asics have all apertures (all asics). | |
84 | */ | |
0a10c851 DV |
85 | static void radeon_register_accessor_init(struct radeon_device *rdev) |
86 | { | |
87 | rdev->mc_rreg = &radeon_invalid_rreg; | |
88 | rdev->mc_wreg = &radeon_invalid_wreg; | |
89 | rdev->pll_rreg = &radeon_invalid_rreg; | |
90 | rdev->pll_wreg = &radeon_invalid_wreg; | |
91 | rdev->pciep_rreg = &radeon_invalid_rreg; | |
92 | rdev->pciep_wreg = &radeon_invalid_wreg; | |
93 | ||
94 | /* Don't change order as we are overridding accessor. */ | |
95 | if (rdev->family < CHIP_RV515) { | |
96 | rdev->pcie_reg_mask = 0xff; | |
97 | } else { | |
98 | rdev->pcie_reg_mask = 0x7ff; | |
99 | } | |
100 | /* FIXME: not sure here */ | |
101 | if (rdev->family <= CHIP_R580) { | |
102 | rdev->pll_rreg = &r100_pll_rreg; | |
103 | rdev->pll_wreg = &r100_pll_wreg; | |
104 | } | |
105 | if (rdev->family >= CHIP_R420) { | |
106 | rdev->mc_rreg = &r420_mc_rreg; | |
107 | rdev->mc_wreg = &r420_mc_wreg; | |
108 | } | |
109 | if (rdev->family >= CHIP_RV515) { | |
110 | rdev->mc_rreg = &rv515_mc_rreg; | |
111 | rdev->mc_wreg = &rv515_mc_wreg; | |
112 | } | |
113 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { | |
114 | rdev->mc_rreg = &rs400_mc_rreg; | |
115 | rdev->mc_wreg = &rs400_mc_wreg; | |
116 | } | |
117 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { | |
118 | rdev->mc_rreg = &rs690_mc_rreg; | |
119 | rdev->mc_wreg = &rs690_mc_wreg; | |
120 | } | |
121 | if (rdev->family == CHIP_RS600) { | |
122 | rdev->mc_rreg = &rs600_mc_rreg; | |
123 | rdev->mc_wreg = &rs600_mc_wreg; | |
124 | } | |
65337e60 SL |
125 | if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { |
126 | rdev->mc_rreg = &rs780_mc_rreg; | |
127 | rdev->mc_wreg = &rs780_mc_wreg; | |
128 | } | |
6e2c3c0a AD |
129 | |
130 | if (rdev->family >= CHIP_BONAIRE) { | |
131 | rdev->pciep_rreg = &cik_pciep_rreg; | |
132 | rdev->pciep_wreg = &cik_pciep_wreg; | |
133 | } else if (rdev->family >= CHIP_R600) { | |
0a10c851 DV |
134 | rdev->pciep_rreg = &r600_pciep_rreg; |
135 | rdev->pciep_wreg = &r600_pciep_wreg; | |
136 | } | |
137 | } | |
138 | ||
139 | ||
140 | /* helper to disable agp */ | |
abf1dc67 AD |
141 | /** |
142 | * radeon_agp_disable - AGP disable helper function | |
143 | * | |
144 | * @rdev: radeon device pointer | |
145 | * | |
146 | * Removes AGP flags and changes the gart callbacks on AGP | |
147 | * cards when using the internal gart rather than AGP (all asics). | |
148 | */ | |
0a10c851 DV |
149 | void radeon_agp_disable(struct radeon_device *rdev) |
150 | { | |
151 | rdev->flags &= ~RADEON_IS_AGP; | |
152 | if (rdev->family >= CHIP_R600) { | |
153 | DRM_INFO("Forcing AGP to PCIE mode\n"); | |
154 | rdev->flags |= RADEON_IS_PCIE; | |
155 | } else if (rdev->family >= CHIP_RV515 || | |
156 | rdev->family == CHIP_RV380 || | |
157 | rdev->family == CHIP_RV410 || | |
158 | rdev->family == CHIP_R423) { | |
159 | DRM_INFO("Forcing AGP to PCIE mode\n"); | |
160 | rdev->flags |= RADEON_IS_PCIE; | |
c5b3b850 AD |
161 | rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; |
162 | rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; | |
0a10c851 DV |
163 | } else { |
164 | DRM_INFO("Forcing AGP to PCI mode\n"); | |
165 | rdev->flags |= RADEON_IS_PCI; | |
c5b3b850 AD |
166 | rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; |
167 | rdev->asic->gart.set_page = &r100_pci_gart_set_page; | |
0a10c851 DV |
168 | } |
169 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; | |
170 | } | |
171 | ||
172 | /* | |
173 | * ASIC | |
174 | */ | |
76a0df85 CK |
175 | |
176 | static struct radeon_asic_ring r100_gfx_ring = { | |
177 | .ib_execute = &r100_ring_ib_execute, | |
178 | .emit_fence = &r100_fence_ring_emit, | |
179 | .emit_semaphore = &r100_semaphore_ring_emit, | |
180 | .cs_parse = &r100_cs_parse, | |
181 | .ring_start = &r100_ring_start, | |
182 | .ring_test = &r100_ring_test, | |
183 | .ib_test = &r100_ib_test, | |
184 | .is_lockup = &r100_gpu_is_lockup, | |
ea31bf69 AD |
185 | .get_rptr = &r100_gfx_get_rptr, |
186 | .get_wptr = &r100_gfx_get_wptr, | |
187 | .set_wptr = &r100_gfx_set_wptr, | |
72a9987e | 188 | .hdp_flush = &r100_ring_hdp_flush, |
76a0df85 CK |
189 | }; |
190 | ||
48e7a5f1 DV |
191 | static struct radeon_asic r100_asic = { |
192 | .init = &r100_init, | |
193 | .fini = &r100_fini, | |
194 | .suspend = &r100_suspend, | |
195 | .resume = &r100_resume, | |
196 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 197 | .asic_reset = &r100_asic_reset, |
124764f1 | 198 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
199 | .gui_idle = &r100_gui_idle, |
200 | .mc_wait_for_idle = &r100_mc_wait_for_idle, | |
c5b3b850 AD |
201 | .gart = { |
202 | .tlb_flush = &r100_pci_gart_tlb_flush, | |
203 | .set_page = &r100_pci_gart_set_page, | |
204 | }, | |
4c87bc26 | 205 | .ring = { |
76a0df85 | 206 | [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring |
4c87bc26 | 207 | }, |
b35ea4ab AD |
208 | .irq = { |
209 | .set = &r100_irq_set, | |
210 | .process = &r100_irq_process, | |
211 | }, | |
c79a49ca AD |
212 | .display = { |
213 | .bandwidth_update = &r100_bandwidth_update, | |
214 | .get_vblank_counter = &r100_get_vblank_counter, | |
215 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 216 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 217 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 218 | }, |
27cd7769 AD |
219 | .copy = { |
220 | .blit = &r100_copy_blit, | |
221 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
222 | .dma = NULL, | |
223 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
224 | .copy = &r100_copy_blit, | |
225 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
226 | }, | |
9e6f3d02 AD |
227 | .surface = { |
228 | .set_reg = r100_set_surface_reg, | |
229 | .clear_reg = r100_clear_surface_reg, | |
230 | }, | |
901ea57d AD |
231 | .hpd = { |
232 | .init = &r100_hpd_init, | |
233 | .fini = &r100_hpd_fini, | |
234 | .sense = &r100_hpd_sense, | |
235 | .set_polarity = &r100_hpd_set_polarity, | |
236 | }, | |
a02fa397 AD |
237 | .pm = { |
238 | .misc = &r100_pm_misc, | |
239 | .prepare = &r100_pm_prepare, | |
240 | .finish = &r100_pm_finish, | |
241 | .init_profile = &r100_pm_init_profile, | |
242 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
243 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
244 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
245 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
246 | .set_memory_clock = NULL, | |
247 | .get_pcie_lanes = NULL, | |
248 | .set_pcie_lanes = NULL, | |
249 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 250 | }, |
0f9e006c | 251 | .pflip = { |
0f9e006c | 252 | .page_flip = &r100_page_flip, |
157fa14d | 253 | .page_flip_pending = &r100_page_flip_pending, |
0f9e006c | 254 | }, |
48e7a5f1 DV |
255 | }; |
256 | ||
257 | static struct radeon_asic r200_asic = { | |
258 | .init = &r100_init, | |
259 | .fini = &r100_fini, | |
260 | .suspend = &r100_suspend, | |
261 | .resume = &r100_resume, | |
262 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 263 | .asic_reset = &r100_asic_reset, |
124764f1 | 264 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
265 | .gui_idle = &r100_gui_idle, |
266 | .mc_wait_for_idle = &r100_mc_wait_for_idle, | |
c5b3b850 AD |
267 | .gart = { |
268 | .tlb_flush = &r100_pci_gart_tlb_flush, | |
269 | .set_page = &r100_pci_gart_set_page, | |
270 | }, | |
4c87bc26 | 271 | .ring = { |
76a0df85 | 272 | [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring |
4c87bc26 | 273 | }, |
b35ea4ab AD |
274 | .irq = { |
275 | .set = &r100_irq_set, | |
276 | .process = &r100_irq_process, | |
277 | }, | |
c79a49ca AD |
278 | .display = { |
279 | .bandwidth_update = &r100_bandwidth_update, | |
280 | .get_vblank_counter = &r100_get_vblank_counter, | |
281 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 282 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 283 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 284 | }, |
27cd7769 AD |
285 | .copy = { |
286 | .blit = &r100_copy_blit, | |
287 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
288 | .dma = &r200_copy_dma, | |
289 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
290 | .copy = &r100_copy_blit, | |
291 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
292 | }, | |
9e6f3d02 AD |
293 | .surface = { |
294 | .set_reg = r100_set_surface_reg, | |
295 | .clear_reg = r100_clear_surface_reg, | |
296 | }, | |
901ea57d AD |
297 | .hpd = { |
298 | .init = &r100_hpd_init, | |
299 | .fini = &r100_hpd_fini, | |
300 | .sense = &r100_hpd_sense, | |
301 | .set_polarity = &r100_hpd_set_polarity, | |
302 | }, | |
a02fa397 AD |
303 | .pm = { |
304 | .misc = &r100_pm_misc, | |
305 | .prepare = &r100_pm_prepare, | |
306 | .finish = &r100_pm_finish, | |
307 | .init_profile = &r100_pm_init_profile, | |
308 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
309 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
310 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
311 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
312 | .set_memory_clock = NULL, | |
313 | .get_pcie_lanes = NULL, | |
314 | .set_pcie_lanes = NULL, | |
315 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 316 | }, |
0f9e006c | 317 | .pflip = { |
0f9e006c | 318 | .page_flip = &r100_page_flip, |
157fa14d | 319 | .page_flip_pending = &r100_page_flip_pending, |
0f9e006c | 320 | }, |
48e7a5f1 DV |
321 | }; |
322 | ||
76a0df85 CK |
323 | static struct radeon_asic_ring r300_gfx_ring = { |
324 | .ib_execute = &r100_ring_ib_execute, | |
325 | .emit_fence = &r300_fence_ring_emit, | |
326 | .emit_semaphore = &r100_semaphore_ring_emit, | |
327 | .cs_parse = &r300_cs_parse, | |
328 | .ring_start = &r300_ring_start, | |
329 | .ring_test = &r100_ring_test, | |
330 | .ib_test = &r100_ib_test, | |
331 | .is_lockup = &r100_gpu_is_lockup, | |
ea31bf69 AD |
332 | .get_rptr = &r100_gfx_get_rptr, |
333 | .get_wptr = &r100_gfx_get_wptr, | |
334 | .set_wptr = &r100_gfx_set_wptr, | |
72a9987e | 335 | .hdp_flush = &r100_ring_hdp_flush, |
76a0df85 CK |
336 | }; |
337 | ||
48e7a5f1 DV |
338 | static struct radeon_asic r300_asic = { |
339 | .init = &r300_init, | |
340 | .fini = &r300_fini, | |
341 | .suspend = &r300_suspend, | |
342 | .resume = &r300_resume, | |
343 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 344 | .asic_reset = &r300_asic_reset, |
124764f1 | 345 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
346 | .gui_idle = &r100_gui_idle, |
347 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | |
c5b3b850 AD |
348 | .gart = { |
349 | .tlb_flush = &r100_pci_gart_tlb_flush, | |
350 | .set_page = &r100_pci_gart_set_page, | |
351 | }, | |
4c87bc26 | 352 | .ring = { |
76a0df85 | 353 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 354 | }, |
b35ea4ab AD |
355 | .irq = { |
356 | .set = &r100_irq_set, | |
357 | .process = &r100_irq_process, | |
358 | }, | |
c79a49ca AD |
359 | .display = { |
360 | .bandwidth_update = &r100_bandwidth_update, | |
361 | .get_vblank_counter = &r100_get_vblank_counter, | |
362 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 363 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 364 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 365 | }, |
27cd7769 AD |
366 | .copy = { |
367 | .blit = &r100_copy_blit, | |
368 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
369 | .dma = &r200_copy_dma, | |
370 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
371 | .copy = &r100_copy_blit, | |
372 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
373 | }, | |
9e6f3d02 AD |
374 | .surface = { |
375 | .set_reg = r100_set_surface_reg, | |
376 | .clear_reg = r100_clear_surface_reg, | |
377 | }, | |
901ea57d AD |
378 | .hpd = { |
379 | .init = &r100_hpd_init, | |
380 | .fini = &r100_hpd_fini, | |
381 | .sense = &r100_hpd_sense, | |
382 | .set_polarity = &r100_hpd_set_polarity, | |
383 | }, | |
a02fa397 AD |
384 | .pm = { |
385 | .misc = &r100_pm_misc, | |
386 | .prepare = &r100_pm_prepare, | |
387 | .finish = &r100_pm_finish, | |
388 | .init_profile = &r100_pm_init_profile, | |
389 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
390 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
391 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
392 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
393 | .set_memory_clock = NULL, | |
394 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
395 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
396 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 397 | }, |
0f9e006c | 398 | .pflip = { |
0f9e006c | 399 | .page_flip = &r100_page_flip, |
157fa14d | 400 | .page_flip_pending = &r100_page_flip_pending, |
0f9e006c | 401 | }, |
48e7a5f1 DV |
402 | }; |
403 | ||
404 | static struct radeon_asic r300_asic_pcie = { | |
405 | .init = &r300_init, | |
406 | .fini = &r300_fini, | |
407 | .suspend = &r300_suspend, | |
408 | .resume = &r300_resume, | |
409 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 410 | .asic_reset = &r300_asic_reset, |
124764f1 | 411 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
412 | .gui_idle = &r100_gui_idle, |
413 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | |
c5b3b850 AD |
414 | .gart = { |
415 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
416 | .set_page = &rv370_pcie_gart_set_page, | |
417 | }, | |
4c87bc26 | 418 | .ring = { |
76a0df85 | 419 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 420 | }, |
b35ea4ab AD |
421 | .irq = { |
422 | .set = &r100_irq_set, | |
423 | .process = &r100_irq_process, | |
424 | }, | |
c79a49ca AD |
425 | .display = { |
426 | .bandwidth_update = &r100_bandwidth_update, | |
427 | .get_vblank_counter = &r100_get_vblank_counter, | |
428 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 429 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 430 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 431 | }, |
27cd7769 AD |
432 | .copy = { |
433 | .blit = &r100_copy_blit, | |
434 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
435 | .dma = &r200_copy_dma, | |
436 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
437 | .copy = &r100_copy_blit, | |
438 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
439 | }, | |
9e6f3d02 AD |
440 | .surface = { |
441 | .set_reg = r100_set_surface_reg, | |
442 | .clear_reg = r100_clear_surface_reg, | |
443 | }, | |
901ea57d AD |
444 | .hpd = { |
445 | .init = &r100_hpd_init, | |
446 | .fini = &r100_hpd_fini, | |
447 | .sense = &r100_hpd_sense, | |
448 | .set_polarity = &r100_hpd_set_polarity, | |
449 | }, | |
a02fa397 AD |
450 | .pm = { |
451 | .misc = &r100_pm_misc, | |
452 | .prepare = &r100_pm_prepare, | |
453 | .finish = &r100_pm_finish, | |
454 | .init_profile = &r100_pm_init_profile, | |
455 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
456 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
457 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
458 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
459 | .set_memory_clock = NULL, | |
460 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
461 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
462 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 463 | }, |
0f9e006c | 464 | .pflip = { |
0f9e006c | 465 | .page_flip = &r100_page_flip, |
157fa14d | 466 | .page_flip_pending = &r100_page_flip_pending, |
0f9e006c | 467 | }, |
48e7a5f1 DV |
468 | }; |
469 | ||
470 | static struct radeon_asic r420_asic = { | |
471 | .init = &r420_init, | |
472 | .fini = &r420_fini, | |
473 | .suspend = &r420_suspend, | |
474 | .resume = &r420_resume, | |
475 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 476 | .asic_reset = &r300_asic_reset, |
124764f1 | 477 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
478 | .gui_idle = &r100_gui_idle, |
479 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | |
c5b3b850 AD |
480 | .gart = { |
481 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
482 | .set_page = &rv370_pcie_gart_set_page, | |
483 | }, | |
4c87bc26 | 484 | .ring = { |
76a0df85 | 485 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 486 | }, |
b35ea4ab AD |
487 | .irq = { |
488 | .set = &r100_irq_set, | |
489 | .process = &r100_irq_process, | |
490 | }, | |
c79a49ca AD |
491 | .display = { |
492 | .bandwidth_update = &r100_bandwidth_update, | |
493 | .get_vblank_counter = &r100_get_vblank_counter, | |
494 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 495 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 496 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 497 | }, |
27cd7769 AD |
498 | .copy = { |
499 | .blit = &r100_copy_blit, | |
500 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
501 | .dma = &r200_copy_dma, | |
502 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
503 | .copy = &r100_copy_blit, | |
504 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
505 | }, | |
9e6f3d02 AD |
506 | .surface = { |
507 | .set_reg = r100_set_surface_reg, | |
508 | .clear_reg = r100_clear_surface_reg, | |
509 | }, | |
901ea57d AD |
510 | .hpd = { |
511 | .init = &r100_hpd_init, | |
512 | .fini = &r100_hpd_fini, | |
513 | .sense = &r100_hpd_sense, | |
514 | .set_polarity = &r100_hpd_set_polarity, | |
515 | }, | |
a02fa397 AD |
516 | .pm = { |
517 | .misc = &r100_pm_misc, | |
518 | .prepare = &r100_pm_prepare, | |
519 | .finish = &r100_pm_finish, | |
520 | .init_profile = &r420_pm_init_profile, | |
521 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
522 | .get_engine_clock = &radeon_atom_get_engine_clock, |
523 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
524 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
525 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
526 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
527 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
528 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 529 | }, |
0f9e006c | 530 | .pflip = { |
0f9e006c | 531 | .page_flip = &r100_page_flip, |
157fa14d | 532 | .page_flip_pending = &r100_page_flip_pending, |
0f9e006c | 533 | }, |
48e7a5f1 DV |
534 | }; |
535 | ||
536 | static struct radeon_asic rs400_asic = { | |
537 | .init = &rs400_init, | |
538 | .fini = &rs400_fini, | |
539 | .suspend = &rs400_suspend, | |
540 | .resume = &rs400_resume, | |
541 | .vga_set_state = &r100_vga_set_state, | |
a2d07b74 | 542 | .asic_reset = &r300_asic_reset, |
124764f1 | 543 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
544 | .gui_idle = &r100_gui_idle, |
545 | .mc_wait_for_idle = &rs400_mc_wait_for_idle, | |
c5b3b850 AD |
546 | .gart = { |
547 | .tlb_flush = &rs400_gart_tlb_flush, | |
548 | .set_page = &rs400_gart_set_page, | |
549 | }, | |
4c87bc26 | 550 | .ring = { |
76a0df85 | 551 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 552 | }, |
b35ea4ab AD |
553 | .irq = { |
554 | .set = &r100_irq_set, | |
555 | .process = &r100_irq_process, | |
556 | }, | |
c79a49ca AD |
557 | .display = { |
558 | .bandwidth_update = &r100_bandwidth_update, | |
559 | .get_vblank_counter = &r100_get_vblank_counter, | |
560 | .wait_for_vblank = &r100_wait_for_vblank, | |
37e9b6a6 | 561 | .set_backlight_level = &radeon_legacy_set_backlight_level, |
6d92f81d | 562 | .get_backlight_level = &radeon_legacy_get_backlight_level, |
c79a49ca | 563 | }, |
27cd7769 AD |
564 | .copy = { |
565 | .blit = &r100_copy_blit, | |
566 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
567 | .dma = &r200_copy_dma, | |
568 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
569 | .copy = &r100_copy_blit, | |
570 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
571 | }, | |
9e6f3d02 AD |
572 | .surface = { |
573 | .set_reg = r100_set_surface_reg, | |
574 | .clear_reg = r100_clear_surface_reg, | |
575 | }, | |
901ea57d AD |
576 | .hpd = { |
577 | .init = &r100_hpd_init, | |
578 | .fini = &r100_hpd_fini, | |
579 | .sense = &r100_hpd_sense, | |
580 | .set_polarity = &r100_hpd_set_polarity, | |
581 | }, | |
a02fa397 AD |
582 | .pm = { |
583 | .misc = &r100_pm_misc, | |
584 | .prepare = &r100_pm_prepare, | |
585 | .finish = &r100_pm_finish, | |
586 | .init_profile = &r100_pm_init_profile, | |
587 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
588 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
589 | .set_engine_clock = &radeon_legacy_set_engine_clock, | |
590 | .get_memory_clock = &radeon_legacy_get_memory_clock, | |
591 | .set_memory_clock = NULL, | |
592 | .get_pcie_lanes = NULL, | |
593 | .set_pcie_lanes = NULL, | |
594 | .set_clock_gating = &radeon_legacy_set_clock_gating, | |
a02fa397 | 595 | }, |
0f9e006c | 596 | .pflip = { |
0f9e006c | 597 | .page_flip = &r100_page_flip, |
157fa14d | 598 | .page_flip_pending = &r100_page_flip_pending, |
0f9e006c | 599 | }, |
48e7a5f1 DV |
600 | }; |
601 | ||
602 | static struct radeon_asic rs600_asic = { | |
603 | .init = &rs600_init, | |
604 | .fini = &rs600_fini, | |
605 | .suspend = &rs600_suspend, | |
606 | .resume = &rs600_resume, | |
607 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 608 | .asic_reset = &rs600_asic_reset, |
124764f1 | 609 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
610 | .gui_idle = &r100_gui_idle, |
611 | .mc_wait_for_idle = &rs600_mc_wait_for_idle, | |
c5b3b850 AD |
612 | .gart = { |
613 | .tlb_flush = &rs600_gart_tlb_flush, | |
614 | .set_page = &rs600_gart_set_page, | |
615 | }, | |
4c87bc26 | 616 | .ring = { |
76a0df85 | 617 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 618 | }, |
b35ea4ab AD |
619 | .irq = { |
620 | .set = &rs600_irq_set, | |
621 | .process = &rs600_irq_process, | |
622 | }, | |
c79a49ca AD |
623 | .display = { |
624 | .bandwidth_update = &rs600_bandwidth_update, | |
625 | .get_vblank_counter = &rs600_get_vblank_counter, | |
626 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 627 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 628 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
629 | .hdmi_enable = &r600_hdmi_enable, |
630 | .hdmi_setmode = &r600_hdmi_setmode, | |
c79a49ca | 631 | }, |
27cd7769 AD |
632 | .copy = { |
633 | .blit = &r100_copy_blit, | |
634 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
635 | .dma = &r200_copy_dma, | |
636 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
637 | .copy = &r100_copy_blit, | |
638 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
639 | }, | |
9e6f3d02 AD |
640 | .surface = { |
641 | .set_reg = r100_set_surface_reg, | |
642 | .clear_reg = r100_clear_surface_reg, | |
643 | }, | |
901ea57d AD |
644 | .hpd = { |
645 | .init = &rs600_hpd_init, | |
646 | .fini = &rs600_hpd_fini, | |
647 | .sense = &rs600_hpd_sense, | |
648 | .set_polarity = &rs600_hpd_set_polarity, | |
649 | }, | |
a02fa397 AD |
650 | .pm = { |
651 | .misc = &rs600_pm_misc, | |
652 | .prepare = &rs600_pm_prepare, | |
653 | .finish = &rs600_pm_finish, | |
654 | .init_profile = &r420_pm_init_profile, | |
655 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
656 | .get_engine_clock = &radeon_atom_get_engine_clock, |
657 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
658 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
659 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
660 | .get_pcie_lanes = NULL, | |
661 | .set_pcie_lanes = NULL, | |
662 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 663 | }, |
0f9e006c | 664 | .pflip = { |
0f9e006c | 665 | .page_flip = &rs600_page_flip, |
157fa14d | 666 | .page_flip_pending = &rs600_page_flip_pending, |
0f9e006c | 667 | }, |
48e7a5f1 DV |
668 | }; |
669 | ||
670 | static struct radeon_asic rs690_asic = { | |
671 | .init = &rs690_init, | |
672 | .fini = &rs690_fini, | |
673 | .suspend = &rs690_suspend, | |
674 | .resume = &rs690_resume, | |
675 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 676 | .asic_reset = &rs600_asic_reset, |
124764f1 | 677 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
678 | .gui_idle = &r100_gui_idle, |
679 | .mc_wait_for_idle = &rs690_mc_wait_for_idle, | |
c5b3b850 AD |
680 | .gart = { |
681 | .tlb_flush = &rs400_gart_tlb_flush, | |
682 | .set_page = &rs400_gart_set_page, | |
683 | }, | |
4c87bc26 | 684 | .ring = { |
76a0df85 | 685 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 686 | }, |
b35ea4ab AD |
687 | .irq = { |
688 | .set = &rs600_irq_set, | |
689 | .process = &rs600_irq_process, | |
690 | }, | |
c79a49ca AD |
691 | .display = { |
692 | .get_vblank_counter = &rs600_get_vblank_counter, | |
693 | .bandwidth_update = &rs690_bandwidth_update, | |
694 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 695 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 696 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
697 | .hdmi_enable = &r600_hdmi_enable, |
698 | .hdmi_setmode = &r600_hdmi_setmode, | |
c79a49ca | 699 | }, |
27cd7769 AD |
700 | .copy = { |
701 | .blit = &r100_copy_blit, | |
702 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
703 | .dma = &r200_copy_dma, | |
704 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
705 | .copy = &r200_copy_dma, | |
706 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
707 | }, | |
9e6f3d02 AD |
708 | .surface = { |
709 | .set_reg = r100_set_surface_reg, | |
710 | .clear_reg = r100_clear_surface_reg, | |
711 | }, | |
901ea57d AD |
712 | .hpd = { |
713 | .init = &rs600_hpd_init, | |
714 | .fini = &rs600_hpd_fini, | |
715 | .sense = &rs600_hpd_sense, | |
716 | .set_polarity = &rs600_hpd_set_polarity, | |
717 | }, | |
a02fa397 AD |
718 | .pm = { |
719 | .misc = &rs600_pm_misc, | |
720 | .prepare = &rs600_pm_prepare, | |
721 | .finish = &rs600_pm_finish, | |
722 | .init_profile = &r420_pm_init_profile, | |
723 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
724 | .get_engine_clock = &radeon_atom_get_engine_clock, |
725 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
726 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
727 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
728 | .get_pcie_lanes = NULL, | |
729 | .set_pcie_lanes = NULL, | |
730 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 731 | }, |
0f9e006c | 732 | .pflip = { |
0f9e006c | 733 | .page_flip = &rs600_page_flip, |
157fa14d | 734 | .page_flip_pending = &rs600_page_flip_pending, |
0f9e006c | 735 | }, |
48e7a5f1 DV |
736 | }; |
737 | ||
738 | static struct radeon_asic rv515_asic = { | |
739 | .init = &rv515_init, | |
740 | .fini = &rv515_fini, | |
741 | .suspend = &rv515_suspend, | |
742 | .resume = &rv515_resume, | |
743 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 744 | .asic_reset = &rs600_asic_reset, |
124764f1 | 745 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
746 | .gui_idle = &r100_gui_idle, |
747 | .mc_wait_for_idle = &rv515_mc_wait_for_idle, | |
c5b3b850 AD |
748 | .gart = { |
749 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
750 | .set_page = &rv370_pcie_gart_set_page, | |
751 | }, | |
4c87bc26 | 752 | .ring = { |
76a0df85 | 753 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 754 | }, |
b35ea4ab AD |
755 | .irq = { |
756 | .set = &rs600_irq_set, | |
757 | .process = &rs600_irq_process, | |
758 | }, | |
c79a49ca AD |
759 | .display = { |
760 | .get_vblank_counter = &rs600_get_vblank_counter, | |
761 | .bandwidth_update = &rv515_bandwidth_update, | |
762 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 763 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 764 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 765 | }, |
27cd7769 AD |
766 | .copy = { |
767 | .blit = &r100_copy_blit, | |
768 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
769 | .dma = &r200_copy_dma, | |
770 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
771 | .copy = &r100_copy_blit, | |
772 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
773 | }, | |
9e6f3d02 AD |
774 | .surface = { |
775 | .set_reg = r100_set_surface_reg, | |
776 | .clear_reg = r100_clear_surface_reg, | |
777 | }, | |
901ea57d AD |
778 | .hpd = { |
779 | .init = &rs600_hpd_init, | |
780 | .fini = &rs600_hpd_fini, | |
781 | .sense = &rs600_hpd_sense, | |
782 | .set_polarity = &rs600_hpd_set_polarity, | |
783 | }, | |
a02fa397 AD |
784 | .pm = { |
785 | .misc = &rs600_pm_misc, | |
786 | .prepare = &rs600_pm_prepare, | |
787 | .finish = &rs600_pm_finish, | |
788 | .init_profile = &r420_pm_init_profile, | |
789 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
790 | .get_engine_clock = &radeon_atom_get_engine_clock, |
791 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
792 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
793 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
794 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
795 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
796 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 797 | }, |
0f9e006c | 798 | .pflip = { |
0f9e006c | 799 | .page_flip = &rs600_page_flip, |
157fa14d | 800 | .page_flip_pending = &rs600_page_flip_pending, |
0f9e006c | 801 | }, |
48e7a5f1 DV |
802 | }; |
803 | ||
804 | static struct radeon_asic r520_asic = { | |
805 | .init = &r520_init, | |
806 | .fini = &rv515_fini, | |
807 | .suspend = &rv515_suspend, | |
808 | .resume = &r520_resume, | |
809 | .vga_set_state = &r100_vga_set_state, | |
90aca4d2 | 810 | .asic_reset = &rs600_asic_reset, |
124764f1 | 811 | .mmio_hdp_flush = NULL, |
54e88e06 AD |
812 | .gui_idle = &r100_gui_idle, |
813 | .mc_wait_for_idle = &r520_mc_wait_for_idle, | |
c5b3b850 AD |
814 | .gart = { |
815 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | |
816 | .set_page = &rv370_pcie_gart_set_page, | |
817 | }, | |
4c87bc26 | 818 | .ring = { |
76a0df85 | 819 | [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring |
4c87bc26 | 820 | }, |
b35ea4ab AD |
821 | .irq = { |
822 | .set = &rs600_irq_set, | |
823 | .process = &rs600_irq_process, | |
824 | }, | |
c79a49ca AD |
825 | .display = { |
826 | .bandwidth_update = &rv515_bandwidth_update, | |
827 | .get_vblank_counter = &rs600_get_vblank_counter, | |
828 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 829 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 830 | .get_backlight_level = &atombios_get_backlight_level, |
c79a49ca | 831 | }, |
27cd7769 AD |
832 | .copy = { |
833 | .blit = &r100_copy_blit, | |
834 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
835 | .dma = &r200_copy_dma, | |
836 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
837 | .copy = &r100_copy_blit, | |
838 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | |
839 | }, | |
9e6f3d02 AD |
840 | .surface = { |
841 | .set_reg = r100_set_surface_reg, | |
842 | .clear_reg = r100_clear_surface_reg, | |
843 | }, | |
901ea57d AD |
844 | .hpd = { |
845 | .init = &rs600_hpd_init, | |
846 | .fini = &rs600_hpd_fini, | |
847 | .sense = &rs600_hpd_sense, | |
848 | .set_polarity = &rs600_hpd_set_polarity, | |
849 | }, | |
a02fa397 AD |
850 | .pm = { |
851 | .misc = &rs600_pm_misc, | |
852 | .prepare = &rs600_pm_prepare, | |
853 | .finish = &rs600_pm_finish, | |
854 | .init_profile = &r420_pm_init_profile, | |
855 | .get_dynpm_state = &r100_pm_get_dynpm_state, | |
798bcf73 AD |
856 | .get_engine_clock = &radeon_atom_get_engine_clock, |
857 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
858 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
859 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
860 | .get_pcie_lanes = &rv370_get_pcie_lanes, | |
861 | .set_pcie_lanes = &rv370_set_pcie_lanes, | |
862 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
a02fa397 | 863 | }, |
0f9e006c | 864 | .pflip = { |
0f9e006c | 865 | .page_flip = &rs600_page_flip, |
157fa14d | 866 | .page_flip_pending = &rs600_page_flip_pending, |
0f9e006c | 867 | }, |
48e7a5f1 DV |
868 | }; |
869 | ||
76a0df85 CK |
870 | static struct radeon_asic_ring r600_gfx_ring = { |
871 | .ib_execute = &r600_ring_ib_execute, | |
872 | .emit_fence = &r600_fence_ring_emit, | |
873 | .emit_semaphore = &r600_semaphore_ring_emit, | |
874 | .cs_parse = &r600_cs_parse, | |
875 | .ring_test = &r600_ring_test, | |
876 | .ib_test = &r600_ib_test, | |
877 | .is_lockup = &r600_gfx_is_lockup, | |
ea31bf69 AD |
878 | .get_rptr = &r600_gfx_get_rptr, |
879 | .get_wptr = &r600_gfx_get_wptr, | |
880 | .set_wptr = &r600_gfx_set_wptr, | |
76a0df85 CK |
881 | }; |
882 | ||
883 | static struct radeon_asic_ring r600_dma_ring = { | |
884 | .ib_execute = &r600_dma_ring_ib_execute, | |
885 | .emit_fence = &r600_dma_fence_ring_emit, | |
886 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
887 | .cs_parse = &r600_dma_cs_parse, | |
888 | .ring_test = &r600_dma_ring_test, | |
889 | .ib_test = &r600_dma_ib_test, | |
890 | .is_lockup = &r600_dma_is_lockup, | |
2e1e6dad CK |
891 | .get_rptr = &r600_dma_get_rptr, |
892 | .get_wptr = &r600_dma_get_wptr, | |
893 | .set_wptr = &r600_dma_set_wptr, | |
76a0df85 CK |
894 | }; |
895 | ||
48e7a5f1 DV |
896 | static struct radeon_asic r600_asic = { |
897 | .init = &r600_init, | |
898 | .fini = &r600_fini, | |
899 | .suspend = &r600_suspend, | |
900 | .resume = &r600_resume, | |
48e7a5f1 | 901 | .vga_set_state = &r600_vga_set_state, |
a2d07b74 | 902 | .asic_reset = &r600_asic_reset, |
124764f1 | 903 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
54e88e06 AD |
904 | .gui_idle = &r600_gui_idle, |
905 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
454d2e2a | 906 | .get_xclk = &r600_get_xclk, |
d0418894 | 907 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
908 | .gart = { |
909 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
910 | .set_page = &rs600_gart_set_page, | |
911 | }, | |
4c87bc26 | 912 | .ring = { |
76a0df85 CK |
913 | [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, |
914 | [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, | |
4c87bc26 | 915 | }, |
b35ea4ab AD |
916 | .irq = { |
917 | .set = &r600_irq_set, | |
918 | .process = &r600_irq_process, | |
919 | }, | |
c79a49ca AD |
920 | .display = { |
921 | .bandwidth_update = &rv515_bandwidth_update, | |
922 | .get_vblank_counter = &rs600_get_vblank_counter, | |
923 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 924 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 925 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
926 | .hdmi_enable = &r600_hdmi_enable, |
927 | .hdmi_setmode = &r600_hdmi_setmode, | |
c79a49ca | 928 | }, |
27cd7769 | 929 | .copy = { |
8dddb993 | 930 | .blit = &r600_copy_cpdma, |
27cd7769 | 931 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
4d75658b AD |
932 | .dma = &r600_copy_dma, |
933 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
bfea6a68 | 934 | .copy = &r600_copy_cpdma, |
aeea40cb | 935 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
27cd7769 | 936 | }, |
9e6f3d02 AD |
937 | .surface = { |
938 | .set_reg = r600_set_surface_reg, | |
939 | .clear_reg = r600_clear_surface_reg, | |
940 | }, | |
901ea57d AD |
941 | .hpd = { |
942 | .init = &r600_hpd_init, | |
943 | .fini = &r600_hpd_fini, | |
944 | .sense = &r600_hpd_sense, | |
945 | .set_polarity = &r600_hpd_set_polarity, | |
946 | }, | |
a02fa397 AD |
947 | .pm = { |
948 | .misc = &r600_pm_misc, | |
949 | .prepare = &rs600_pm_prepare, | |
950 | .finish = &rs600_pm_finish, | |
951 | .init_profile = &r600_pm_init_profile, | |
952 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
953 | .get_engine_clock = &radeon_atom_get_engine_clock, |
954 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
955 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
956 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
957 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
958 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
959 | .set_clock_gating = NULL, | |
6bd1c385 | 960 | .get_temperature = &rv6xx_get_temp, |
a02fa397 | 961 | }, |
0f9e006c | 962 | .pflip = { |
0f9e006c | 963 | .page_flip = &rs600_page_flip, |
157fa14d | 964 | .page_flip_pending = &rs600_page_flip_pending, |
0f9e006c | 965 | }, |
48e7a5f1 DV |
966 | }; |
967 | ||
856754c3 CK |
968 | static struct radeon_asic_ring rv6xx_uvd_ring = { |
969 | .ib_execute = &uvd_v1_0_ib_execute, | |
970 | .emit_fence = &uvd_v1_0_fence_emit, | |
971 | .emit_semaphore = &uvd_v1_0_semaphore_emit, | |
972 | .cs_parse = &radeon_uvd_cs_parse, | |
973 | .ring_test = &uvd_v1_0_ring_test, | |
974 | .ib_test = &uvd_v1_0_ib_test, | |
975 | .is_lockup = &radeon_ring_test_lockup, | |
976 | .get_rptr = &uvd_v1_0_get_rptr, | |
977 | .get_wptr = &uvd_v1_0_get_wptr, | |
978 | .set_wptr = &uvd_v1_0_set_wptr, | |
979 | }; | |
980 | ||
ca361b65 AD |
981 | static struct radeon_asic rv6xx_asic = { |
982 | .init = &r600_init, | |
983 | .fini = &r600_fini, | |
984 | .suspend = &r600_suspend, | |
985 | .resume = &r600_resume, | |
986 | .vga_set_state = &r600_vga_set_state, | |
987 | .asic_reset = &r600_asic_reset, | |
124764f1 | 988 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
ca361b65 AD |
989 | .gui_idle = &r600_gui_idle, |
990 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
991 | .get_xclk = &r600_get_xclk, | |
992 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, | |
993 | .gart = { | |
994 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
995 | .set_page = &rs600_gart_set_page, | |
996 | }, | |
997 | .ring = { | |
76a0df85 CK |
998 | [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, |
999 | [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, | |
856754c3 | 1000 | [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring, |
ca361b65 AD |
1001 | }, |
1002 | .irq = { | |
1003 | .set = &r600_irq_set, | |
1004 | .process = &r600_irq_process, | |
1005 | }, | |
1006 | .display = { | |
1007 | .bandwidth_update = &rv515_bandwidth_update, | |
1008 | .get_vblank_counter = &rs600_get_vblank_counter, | |
1009 | .wait_for_vblank = &avivo_wait_for_vblank, | |
1010 | .set_backlight_level = &atombios_set_backlight_level, | |
1011 | .get_backlight_level = &atombios_get_backlight_level, | |
99d79aa2 AD |
1012 | .hdmi_enable = &r600_hdmi_enable, |
1013 | .hdmi_setmode = &r600_hdmi_setmode, | |
ca361b65 AD |
1014 | }, |
1015 | .copy = { | |
8dddb993 | 1016 | .blit = &r600_copy_cpdma, |
ca361b65 AD |
1017 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1018 | .dma = &r600_copy_dma, | |
1019 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
bfea6a68 | 1020 | .copy = &r600_copy_cpdma, |
aeea40cb | 1021 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
ca361b65 AD |
1022 | }, |
1023 | .surface = { | |
1024 | .set_reg = r600_set_surface_reg, | |
1025 | .clear_reg = r600_clear_surface_reg, | |
1026 | }, | |
1027 | .hpd = { | |
1028 | .init = &r600_hpd_init, | |
1029 | .fini = &r600_hpd_fini, | |
1030 | .sense = &r600_hpd_sense, | |
1031 | .set_polarity = &r600_hpd_set_polarity, | |
1032 | }, | |
1033 | .pm = { | |
1034 | .misc = &r600_pm_misc, | |
1035 | .prepare = &rs600_pm_prepare, | |
1036 | .finish = &rs600_pm_finish, | |
1037 | .init_profile = &r600_pm_init_profile, | |
1038 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
1039 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
1040 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1041 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1042 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1043 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
1044 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
1045 | .set_clock_gating = NULL, | |
1046 | .get_temperature = &rv6xx_get_temp, | |
1b9ba70a | 1047 | .set_uvd_clocks = &r600_set_uvd_clocks, |
ca361b65 | 1048 | }, |
4a6369e9 AD |
1049 | .dpm = { |
1050 | .init = &rv6xx_dpm_init, | |
1051 | .setup_asic = &rv6xx_setup_asic, | |
1052 | .enable = &rv6xx_dpm_enable, | |
a4643ba3 | 1053 | .late_enable = &r600_dpm_late_enable, |
4a6369e9 | 1054 | .disable = &rv6xx_dpm_disable, |
98243917 | 1055 | .pre_set_power_state = &r600_dpm_pre_set_power_state, |
4a6369e9 | 1056 | .set_power_state = &rv6xx_dpm_set_power_state, |
98243917 | 1057 | .post_set_power_state = &r600_dpm_post_set_power_state, |
4a6369e9 AD |
1058 | .display_configuration_changed = &rv6xx_dpm_display_configuration_changed, |
1059 | .fini = &rv6xx_dpm_fini, | |
1060 | .get_sclk = &rv6xx_dpm_get_sclk, | |
1061 | .get_mclk = &rv6xx_dpm_get_mclk, | |
1062 | .print_power_state = &rv6xx_dpm_print_power_state, | |
242916a5 | 1063 | .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level, |
f4f85a8c | 1064 | .force_performance_level = &rv6xx_dpm_force_performance_level, |
4a6369e9 | 1065 | }, |
ca361b65 | 1066 | .pflip = { |
ca361b65 | 1067 | .page_flip = &rs600_page_flip, |
157fa14d | 1068 | .page_flip_pending = &rs600_page_flip_pending, |
ca361b65 AD |
1069 | }, |
1070 | }; | |
1071 | ||
f47299c5 AD |
1072 | static struct radeon_asic rs780_asic = { |
1073 | .init = &r600_init, | |
1074 | .fini = &r600_fini, | |
1075 | .suspend = &r600_suspend, | |
1076 | .resume = &r600_resume, | |
f47299c5 | 1077 | .vga_set_state = &r600_vga_set_state, |
a2d07b74 | 1078 | .asic_reset = &r600_asic_reset, |
124764f1 | 1079 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
54e88e06 AD |
1080 | .gui_idle = &r600_gui_idle, |
1081 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
454d2e2a | 1082 | .get_xclk = &r600_get_xclk, |
d0418894 | 1083 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
1084 | .gart = { |
1085 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
1086 | .set_page = &rs600_gart_set_page, | |
1087 | }, | |
4c87bc26 | 1088 | .ring = { |
76a0df85 CK |
1089 | [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, |
1090 | [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, | |
856754c3 | 1091 | [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring, |
4c87bc26 | 1092 | }, |
b35ea4ab AD |
1093 | .irq = { |
1094 | .set = &r600_irq_set, | |
1095 | .process = &r600_irq_process, | |
1096 | }, | |
c79a49ca AD |
1097 | .display = { |
1098 | .bandwidth_update = &rs690_bandwidth_update, | |
1099 | .get_vblank_counter = &rs600_get_vblank_counter, | |
1100 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 1101 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1102 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
1103 | .hdmi_enable = &r600_hdmi_enable, |
1104 | .hdmi_setmode = &r600_hdmi_setmode, | |
c79a49ca | 1105 | }, |
27cd7769 | 1106 | .copy = { |
8dddb993 | 1107 | .blit = &r600_copy_cpdma, |
27cd7769 | 1108 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
4d75658b AD |
1109 | .dma = &r600_copy_dma, |
1110 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
bfea6a68 | 1111 | .copy = &r600_copy_cpdma, |
aeea40cb | 1112 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
27cd7769 | 1113 | }, |
9e6f3d02 AD |
1114 | .surface = { |
1115 | .set_reg = r600_set_surface_reg, | |
1116 | .clear_reg = r600_clear_surface_reg, | |
1117 | }, | |
901ea57d AD |
1118 | .hpd = { |
1119 | .init = &r600_hpd_init, | |
1120 | .fini = &r600_hpd_fini, | |
1121 | .sense = &r600_hpd_sense, | |
1122 | .set_polarity = &r600_hpd_set_polarity, | |
1123 | }, | |
a02fa397 AD |
1124 | .pm = { |
1125 | .misc = &r600_pm_misc, | |
1126 | .prepare = &rs600_pm_prepare, | |
1127 | .finish = &rs600_pm_finish, | |
1128 | .init_profile = &rs780_pm_init_profile, | |
1129 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1130 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1131 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1132 | .get_memory_clock = NULL, | |
1133 | .set_memory_clock = NULL, | |
1134 | .get_pcie_lanes = NULL, | |
1135 | .set_pcie_lanes = NULL, | |
1136 | .set_clock_gating = NULL, | |
6bd1c385 | 1137 | .get_temperature = &rv6xx_get_temp, |
1b9ba70a | 1138 | .set_uvd_clocks = &r600_set_uvd_clocks, |
a02fa397 | 1139 | }, |
9d67006e AD |
1140 | .dpm = { |
1141 | .init = &rs780_dpm_init, | |
1142 | .setup_asic = &rs780_dpm_setup_asic, | |
1143 | .enable = &rs780_dpm_enable, | |
a4643ba3 | 1144 | .late_enable = &r600_dpm_late_enable, |
9d67006e | 1145 | .disable = &rs780_dpm_disable, |
98243917 | 1146 | .pre_set_power_state = &r600_dpm_pre_set_power_state, |
9d67006e | 1147 | .set_power_state = &rs780_dpm_set_power_state, |
98243917 | 1148 | .post_set_power_state = &r600_dpm_post_set_power_state, |
9d67006e AD |
1149 | .display_configuration_changed = &rs780_dpm_display_configuration_changed, |
1150 | .fini = &rs780_dpm_fini, | |
1151 | .get_sclk = &rs780_dpm_get_sclk, | |
1152 | .get_mclk = &rs780_dpm_get_mclk, | |
1153 | .print_power_state = &rs780_dpm_print_power_state, | |
444bddc4 | 1154 | .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level, |
63580c3e | 1155 | .force_performance_level = &rs780_dpm_force_performance_level, |
9d67006e | 1156 | }, |
0f9e006c | 1157 | .pflip = { |
0f9e006c | 1158 | .page_flip = &rs600_page_flip, |
157fa14d | 1159 | .page_flip_pending = &rs600_page_flip_pending, |
0f9e006c | 1160 | }, |
f47299c5 AD |
1161 | }; |
1162 | ||
76a0df85 | 1163 | static struct radeon_asic_ring rv770_uvd_ring = { |
e409b128 CK |
1164 | .ib_execute = &uvd_v1_0_ib_execute, |
1165 | .emit_fence = &uvd_v2_2_fence_emit, | |
1166 | .emit_semaphore = &uvd_v1_0_semaphore_emit, | |
76a0df85 | 1167 | .cs_parse = &radeon_uvd_cs_parse, |
e409b128 CK |
1168 | .ring_test = &uvd_v1_0_ring_test, |
1169 | .ib_test = &uvd_v1_0_ib_test, | |
76a0df85 | 1170 | .is_lockup = &radeon_ring_test_lockup, |
e409b128 CK |
1171 | .get_rptr = &uvd_v1_0_get_rptr, |
1172 | .get_wptr = &uvd_v1_0_get_wptr, | |
1173 | .set_wptr = &uvd_v1_0_set_wptr, | |
76a0df85 CK |
1174 | }; |
1175 | ||
48e7a5f1 DV |
1176 | static struct radeon_asic rv770_asic = { |
1177 | .init = &rv770_init, | |
1178 | .fini = &rv770_fini, | |
1179 | .suspend = &rv770_suspend, | |
1180 | .resume = &rv770_resume, | |
a2d07b74 | 1181 | .asic_reset = &r600_asic_reset, |
48e7a5f1 | 1182 | .vga_set_state = &r600_vga_set_state, |
124764f1 | 1183 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
54e88e06 AD |
1184 | .gui_idle = &r600_gui_idle, |
1185 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | |
454d2e2a | 1186 | .get_xclk = &rv770_get_xclk, |
d0418894 | 1187 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
1188 | .gart = { |
1189 | .tlb_flush = &r600_pcie_gart_tlb_flush, | |
1190 | .set_page = &rs600_gart_set_page, | |
1191 | }, | |
4c87bc26 | 1192 | .ring = { |
76a0df85 CK |
1193 | [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring, |
1194 | [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring, | |
1195 | [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, | |
4c87bc26 | 1196 | }, |
b35ea4ab AD |
1197 | .irq = { |
1198 | .set = &r600_irq_set, | |
1199 | .process = &r600_irq_process, | |
1200 | }, | |
c79a49ca AD |
1201 | .display = { |
1202 | .bandwidth_update = &rv515_bandwidth_update, | |
1203 | .get_vblank_counter = &rs600_get_vblank_counter, | |
1204 | .wait_for_vblank = &avivo_wait_for_vblank, | |
37e9b6a6 | 1205 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1206 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 | 1207 | .hdmi_enable = &r600_hdmi_enable, |
8f33a156 | 1208 | .hdmi_setmode = &dce3_1_hdmi_setmode, |
c79a49ca | 1209 | }, |
27cd7769 | 1210 | .copy = { |
8dddb993 | 1211 | .blit = &r600_copy_cpdma, |
27cd7769 | 1212 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
43fb7787 | 1213 | .dma = &rv770_copy_dma, |
4d75658b | 1214 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, |
43fb7787 | 1215 | .copy = &rv770_copy_dma, |
2d6cc729 | 1216 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, |
27cd7769 | 1217 | }, |
9e6f3d02 AD |
1218 | .surface = { |
1219 | .set_reg = r600_set_surface_reg, | |
1220 | .clear_reg = r600_clear_surface_reg, | |
1221 | }, | |
901ea57d AD |
1222 | .hpd = { |
1223 | .init = &r600_hpd_init, | |
1224 | .fini = &r600_hpd_fini, | |
1225 | .sense = &r600_hpd_sense, | |
1226 | .set_polarity = &r600_hpd_set_polarity, | |
1227 | }, | |
a02fa397 AD |
1228 | .pm = { |
1229 | .misc = &rv770_pm_misc, | |
1230 | .prepare = &rs600_pm_prepare, | |
1231 | .finish = &rs600_pm_finish, | |
1232 | .init_profile = &r600_pm_init_profile, | |
1233 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1234 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1235 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1236 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1237 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1238 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
1239 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
1240 | .set_clock_gating = &radeon_atom_set_clock_gating, | |
ef0e6e65 | 1241 | .set_uvd_clocks = &rv770_set_uvd_clocks, |
6bd1c385 | 1242 | .get_temperature = &rv770_get_temp, |
a02fa397 | 1243 | }, |
66229b20 AD |
1244 | .dpm = { |
1245 | .init = &rv770_dpm_init, | |
1246 | .setup_asic = &rv770_dpm_setup_asic, | |
1247 | .enable = &rv770_dpm_enable, | |
a3f11245 | 1248 | .late_enable = &rv770_dpm_late_enable, |
66229b20 | 1249 | .disable = &rv770_dpm_disable, |
98243917 | 1250 | .pre_set_power_state = &r600_dpm_pre_set_power_state, |
66229b20 | 1251 | .set_power_state = &rv770_dpm_set_power_state, |
98243917 | 1252 | .post_set_power_state = &r600_dpm_post_set_power_state, |
66229b20 AD |
1253 | .display_configuration_changed = &rv770_dpm_display_configuration_changed, |
1254 | .fini = &rv770_dpm_fini, | |
1255 | .get_sclk = &rv770_dpm_get_sclk, | |
1256 | .get_mclk = &rv770_dpm_get_mclk, | |
1257 | .print_power_state = &rv770_dpm_print_power_state, | |
bd210d11 | 1258 | .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, |
8b5e6b7f | 1259 | .force_performance_level = &rv770_dpm_force_performance_level, |
b06195d9 | 1260 | .vblank_too_short = &rv770_dpm_vblank_too_short, |
66229b20 | 1261 | }, |
0f9e006c | 1262 | .pflip = { |
0f9e006c | 1263 | .page_flip = &rv770_page_flip, |
157fa14d | 1264 | .page_flip_pending = &rv770_page_flip_pending, |
0f9e006c | 1265 | }, |
48e7a5f1 DV |
1266 | }; |
1267 | ||
76a0df85 CK |
1268 | static struct radeon_asic_ring evergreen_gfx_ring = { |
1269 | .ib_execute = &evergreen_ring_ib_execute, | |
1270 | .emit_fence = &r600_fence_ring_emit, | |
1271 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1272 | .cs_parse = &evergreen_cs_parse, | |
1273 | .ring_test = &r600_ring_test, | |
1274 | .ib_test = &r600_ib_test, | |
1275 | .is_lockup = &evergreen_gfx_is_lockup, | |
ea31bf69 AD |
1276 | .get_rptr = &r600_gfx_get_rptr, |
1277 | .get_wptr = &r600_gfx_get_wptr, | |
1278 | .set_wptr = &r600_gfx_set_wptr, | |
76a0df85 CK |
1279 | }; |
1280 | ||
1281 | static struct radeon_asic_ring evergreen_dma_ring = { | |
1282 | .ib_execute = &evergreen_dma_ring_ib_execute, | |
1283 | .emit_fence = &evergreen_dma_fence_ring_emit, | |
1284 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
1285 | .cs_parse = &evergreen_dma_cs_parse, | |
1286 | .ring_test = &r600_dma_ring_test, | |
1287 | .ib_test = &r600_dma_ib_test, | |
1288 | .is_lockup = &evergreen_dma_is_lockup, | |
2e1e6dad CK |
1289 | .get_rptr = &r600_dma_get_rptr, |
1290 | .get_wptr = &r600_dma_get_wptr, | |
1291 | .set_wptr = &r600_dma_set_wptr, | |
76a0df85 CK |
1292 | }; |
1293 | ||
48e7a5f1 DV |
1294 | static struct radeon_asic evergreen_asic = { |
1295 | .init = &evergreen_init, | |
1296 | .fini = &evergreen_fini, | |
1297 | .suspend = &evergreen_suspend, | |
1298 | .resume = &evergreen_resume, | |
a2d07b74 | 1299 | .asic_reset = &evergreen_asic_reset, |
48e7a5f1 | 1300 | .vga_set_state = &r600_vga_set_state, |
124764f1 | 1301 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
54e88e06 AD |
1302 | .gui_idle = &r600_gui_idle, |
1303 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1304 | .get_xclk = &rv770_get_xclk, |
d0418894 | 1305 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
1306 | .gart = { |
1307 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
1308 | .set_page = &rs600_gart_set_page, | |
1309 | }, | |
4c87bc26 | 1310 | .ring = { |
76a0df85 CK |
1311 | [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, |
1312 | [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, | |
1313 | [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, | |
4c87bc26 | 1314 | }, |
b35ea4ab AD |
1315 | .irq = { |
1316 | .set = &evergreen_irq_set, | |
1317 | .process = &evergreen_irq_process, | |
1318 | }, | |
c79a49ca AD |
1319 | .display = { |
1320 | .bandwidth_update = &evergreen_bandwidth_update, | |
1321 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1322 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1323 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1324 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
1325 | .hdmi_enable = &evergreen_hdmi_enable, |
1326 | .hdmi_setmode = &evergreen_hdmi_setmode, | |
c79a49ca | 1327 | }, |
27cd7769 | 1328 | .copy = { |
8dddb993 | 1329 | .blit = &r600_copy_cpdma, |
27cd7769 | 1330 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
233d1ad5 AD |
1331 | .dma = &evergreen_copy_dma, |
1332 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1333 | .copy = &evergreen_copy_dma, |
1334 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
27cd7769 | 1335 | }, |
9e6f3d02 AD |
1336 | .surface = { |
1337 | .set_reg = r600_set_surface_reg, | |
1338 | .clear_reg = r600_clear_surface_reg, | |
1339 | }, | |
901ea57d AD |
1340 | .hpd = { |
1341 | .init = &evergreen_hpd_init, | |
1342 | .fini = &evergreen_hpd_fini, | |
1343 | .sense = &evergreen_hpd_sense, | |
1344 | .set_polarity = &evergreen_hpd_set_polarity, | |
1345 | }, | |
a02fa397 AD |
1346 | .pm = { |
1347 | .misc = &evergreen_pm_misc, | |
1348 | .prepare = &evergreen_pm_prepare, | |
1349 | .finish = &evergreen_pm_finish, | |
1350 | .init_profile = &r600_pm_init_profile, | |
1351 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1352 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1353 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1354 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1355 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
1356 | .get_pcie_lanes = &r600_get_pcie_lanes, | |
1357 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
1358 | .set_clock_gating = NULL, | |
a8b4925c | 1359 | .set_uvd_clocks = &evergreen_set_uvd_clocks, |
6bd1c385 | 1360 | .get_temperature = &evergreen_get_temp, |
a02fa397 | 1361 | }, |
dc50ba7f AD |
1362 | .dpm = { |
1363 | .init = &cypress_dpm_init, | |
1364 | .setup_asic = &cypress_dpm_setup_asic, | |
1365 | .enable = &cypress_dpm_enable, | |
a3f11245 | 1366 | .late_enable = &rv770_dpm_late_enable, |
dc50ba7f | 1367 | .disable = &cypress_dpm_disable, |
98243917 | 1368 | .pre_set_power_state = &r600_dpm_pre_set_power_state, |
dc50ba7f | 1369 | .set_power_state = &cypress_dpm_set_power_state, |
98243917 | 1370 | .post_set_power_state = &r600_dpm_post_set_power_state, |
dc50ba7f AD |
1371 | .display_configuration_changed = &cypress_dpm_display_configuration_changed, |
1372 | .fini = &cypress_dpm_fini, | |
1373 | .get_sclk = &rv770_dpm_get_sclk, | |
1374 | .get_mclk = &rv770_dpm_get_mclk, | |
1375 | .print_power_state = &rv770_dpm_print_power_state, | |
bd210d11 | 1376 | .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level, |
8b5e6b7f | 1377 | .force_performance_level = &rv770_dpm_force_performance_level, |
d0b54bdc | 1378 | .vblank_too_short = &cypress_dpm_vblank_too_short, |
dc50ba7f | 1379 | }, |
0f9e006c | 1380 | .pflip = { |
0f9e006c | 1381 | .page_flip = &evergreen_page_flip, |
157fa14d | 1382 | .page_flip_pending = &evergreen_page_flip_pending, |
0f9e006c | 1383 | }, |
48e7a5f1 DV |
1384 | }; |
1385 | ||
958261d1 AD |
1386 | static struct radeon_asic sumo_asic = { |
1387 | .init = &evergreen_init, | |
1388 | .fini = &evergreen_fini, | |
1389 | .suspend = &evergreen_suspend, | |
1390 | .resume = &evergreen_resume, | |
958261d1 AD |
1391 | .asic_reset = &evergreen_asic_reset, |
1392 | .vga_set_state = &r600_vga_set_state, | |
124764f1 | 1393 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
54e88e06 AD |
1394 | .gui_idle = &r600_gui_idle, |
1395 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1396 | .get_xclk = &r600_get_xclk, |
d0418894 | 1397 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
1398 | .gart = { |
1399 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
1400 | .set_page = &rs600_gart_set_page, | |
1401 | }, | |
4c87bc26 | 1402 | .ring = { |
76a0df85 CK |
1403 | [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, |
1404 | [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, | |
1405 | [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, | |
4c87bc26 | 1406 | }, |
b35ea4ab AD |
1407 | .irq = { |
1408 | .set = &evergreen_irq_set, | |
1409 | .process = &evergreen_irq_process, | |
1410 | }, | |
c79a49ca AD |
1411 | .display = { |
1412 | .bandwidth_update = &evergreen_bandwidth_update, | |
1413 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1414 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1415 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1416 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
1417 | .hdmi_enable = &evergreen_hdmi_enable, |
1418 | .hdmi_setmode = &evergreen_hdmi_setmode, | |
c79a49ca | 1419 | }, |
27cd7769 | 1420 | .copy = { |
8dddb993 | 1421 | .blit = &r600_copy_cpdma, |
27cd7769 | 1422 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
233d1ad5 AD |
1423 | .dma = &evergreen_copy_dma, |
1424 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1425 | .copy = &evergreen_copy_dma, |
1426 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
27cd7769 | 1427 | }, |
9e6f3d02 AD |
1428 | .surface = { |
1429 | .set_reg = r600_set_surface_reg, | |
1430 | .clear_reg = r600_clear_surface_reg, | |
1431 | }, | |
901ea57d AD |
1432 | .hpd = { |
1433 | .init = &evergreen_hpd_init, | |
1434 | .fini = &evergreen_hpd_fini, | |
1435 | .sense = &evergreen_hpd_sense, | |
1436 | .set_polarity = &evergreen_hpd_set_polarity, | |
1437 | }, | |
a02fa397 AD |
1438 | .pm = { |
1439 | .misc = &evergreen_pm_misc, | |
1440 | .prepare = &evergreen_pm_prepare, | |
1441 | .finish = &evergreen_pm_finish, | |
1442 | .init_profile = &sumo_pm_init_profile, | |
1443 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
798bcf73 AD |
1444 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1445 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1446 | .get_memory_clock = NULL, | |
1447 | .set_memory_clock = NULL, | |
1448 | .get_pcie_lanes = NULL, | |
1449 | .set_pcie_lanes = NULL, | |
1450 | .set_clock_gating = NULL, | |
23d33ba3 | 1451 | .set_uvd_clocks = &sumo_set_uvd_clocks, |
6bd1c385 | 1452 | .get_temperature = &sumo_get_temp, |
a02fa397 | 1453 | }, |
80ea2c12 AD |
1454 | .dpm = { |
1455 | .init = &sumo_dpm_init, | |
1456 | .setup_asic = &sumo_dpm_setup_asic, | |
1457 | .enable = &sumo_dpm_enable, | |
14ec9fab | 1458 | .late_enable = &sumo_dpm_late_enable, |
80ea2c12 | 1459 | .disable = &sumo_dpm_disable, |
422a56bc | 1460 | .pre_set_power_state = &sumo_dpm_pre_set_power_state, |
80ea2c12 | 1461 | .set_power_state = &sumo_dpm_set_power_state, |
422a56bc | 1462 | .post_set_power_state = &sumo_dpm_post_set_power_state, |
80ea2c12 AD |
1463 | .display_configuration_changed = &sumo_dpm_display_configuration_changed, |
1464 | .fini = &sumo_dpm_fini, | |
1465 | .get_sclk = &sumo_dpm_get_sclk, | |
1466 | .get_mclk = &sumo_dpm_get_mclk, | |
1467 | .print_power_state = &sumo_dpm_print_power_state, | |
fb70160c | 1468 | .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level, |
5d5e5591 | 1469 | .force_performance_level = &sumo_dpm_force_performance_level, |
80ea2c12 | 1470 | }, |
0f9e006c | 1471 | .pflip = { |
0f9e006c | 1472 | .page_flip = &evergreen_page_flip, |
157fa14d | 1473 | .page_flip_pending = &evergreen_page_flip_pending, |
0f9e006c | 1474 | }, |
958261d1 AD |
1475 | }; |
1476 | ||
a43b7665 AD |
1477 | static struct radeon_asic btc_asic = { |
1478 | .init = &evergreen_init, | |
1479 | .fini = &evergreen_fini, | |
1480 | .suspend = &evergreen_suspend, | |
1481 | .resume = &evergreen_resume, | |
a43b7665 AD |
1482 | .asic_reset = &evergreen_asic_reset, |
1483 | .vga_set_state = &r600_vga_set_state, | |
124764f1 | 1484 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
54e88e06 AD |
1485 | .gui_idle = &r600_gui_idle, |
1486 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1487 | .get_xclk = &rv770_get_xclk, |
d0418894 | 1488 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
1489 | .gart = { |
1490 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | |
1491 | .set_page = &rs600_gart_set_page, | |
1492 | }, | |
4c87bc26 | 1493 | .ring = { |
76a0df85 CK |
1494 | [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring, |
1495 | [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring, | |
1496 | [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring, | |
4c87bc26 | 1497 | }, |
b35ea4ab AD |
1498 | .irq = { |
1499 | .set = &evergreen_irq_set, | |
1500 | .process = &evergreen_irq_process, | |
1501 | }, | |
c79a49ca AD |
1502 | .display = { |
1503 | .bandwidth_update = &evergreen_bandwidth_update, | |
1504 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1505 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1506 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1507 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
1508 | .hdmi_enable = &evergreen_hdmi_enable, |
1509 | .hdmi_setmode = &evergreen_hdmi_setmode, | |
c79a49ca | 1510 | }, |
27cd7769 | 1511 | .copy = { |
8dddb993 | 1512 | .blit = &r600_copy_cpdma, |
27cd7769 | 1513 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
233d1ad5 AD |
1514 | .dma = &evergreen_copy_dma, |
1515 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1516 | .copy = &evergreen_copy_dma, |
1517 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
27cd7769 | 1518 | }, |
9e6f3d02 AD |
1519 | .surface = { |
1520 | .set_reg = r600_set_surface_reg, | |
1521 | .clear_reg = r600_clear_surface_reg, | |
1522 | }, | |
901ea57d AD |
1523 | .hpd = { |
1524 | .init = &evergreen_hpd_init, | |
1525 | .fini = &evergreen_hpd_fini, | |
1526 | .sense = &evergreen_hpd_sense, | |
1527 | .set_polarity = &evergreen_hpd_set_polarity, | |
1528 | }, | |
a02fa397 AD |
1529 | .pm = { |
1530 | .misc = &evergreen_pm_misc, | |
1531 | .prepare = &evergreen_pm_prepare, | |
1532 | .finish = &evergreen_pm_finish, | |
27810fb2 | 1533 | .init_profile = &btc_pm_init_profile, |
a02fa397 | 1534 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
798bcf73 AD |
1535 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1536 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1537 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1538 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
55b615ae AD |
1539 | .get_pcie_lanes = &r600_get_pcie_lanes, |
1540 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
798bcf73 | 1541 | .set_clock_gating = NULL, |
a8b4925c | 1542 | .set_uvd_clocks = &evergreen_set_uvd_clocks, |
6bd1c385 | 1543 | .get_temperature = &evergreen_get_temp, |
a02fa397 | 1544 | }, |
6596afd4 AD |
1545 | .dpm = { |
1546 | .init = &btc_dpm_init, | |
1547 | .setup_asic = &btc_dpm_setup_asic, | |
1548 | .enable = &btc_dpm_enable, | |
a3f11245 | 1549 | .late_enable = &rv770_dpm_late_enable, |
6596afd4 | 1550 | .disable = &btc_dpm_disable, |
e8a9539f | 1551 | .pre_set_power_state = &btc_dpm_pre_set_power_state, |
6596afd4 | 1552 | .set_power_state = &btc_dpm_set_power_state, |
e8a9539f | 1553 | .post_set_power_state = &btc_dpm_post_set_power_state, |
6596afd4 AD |
1554 | .display_configuration_changed = &cypress_dpm_display_configuration_changed, |
1555 | .fini = &btc_dpm_fini, | |
e8a9539f AD |
1556 | .get_sclk = &btc_dpm_get_sclk, |
1557 | .get_mclk = &btc_dpm_get_mclk, | |
6596afd4 | 1558 | .print_power_state = &rv770_dpm_print_power_state, |
9f3f63f2 | 1559 | .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level, |
8b5e6b7f | 1560 | .force_performance_level = &rv770_dpm_force_performance_level, |
a84301c6 | 1561 | .vblank_too_short = &btc_dpm_vblank_too_short, |
6596afd4 | 1562 | }, |
0f9e006c | 1563 | .pflip = { |
0f9e006c | 1564 | .page_flip = &evergreen_page_flip, |
157fa14d | 1565 | .page_flip_pending = &evergreen_page_flip_pending, |
0f9e006c | 1566 | }, |
a43b7665 AD |
1567 | }; |
1568 | ||
76a0df85 CK |
1569 | static struct radeon_asic_ring cayman_gfx_ring = { |
1570 | .ib_execute = &cayman_ring_ib_execute, | |
1571 | .ib_parse = &evergreen_ib_parse, | |
1572 | .emit_fence = &cayman_fence_ring_emit, | |
1573 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1574 | .cs_parse = &evergreen_cs_parse, | |
1575 | .ring_test = &r600_ring_test, | |
1576 | .ib_test = &r600_ib_test, | |
1577 | .is_lockup = &cayman_gfx_is_lockup, | |
1578 | .vm_flush = &cayman_vm_flush, | |
ea31bf69 AD |
1579 | .get_rptr = &cayman_gfx_get_rptr, |
1580 | .get_wptr = &cayman_gfx_get_wptr, | |
1581 | .set_wptr = &cayman_gfx_set_wptr, | |
76a0df85 CK |
1582 | }; |
1583 | ||
1584 | static struct radeon_asic_ring cayman_dma_ring = { | |
1585 | .ib_execute = &cayman_dma_ring_ib_execute, | |
1586 | .ib_parse = &evergreen_dma_ib_parse, | |
1587 | .emit_fence = &evergreen_dma_fence_ring_emit, | |
1588 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
1589 | .cs_parse = &evergreen_dma_cs_parse, | |
1590 | .ring_test = &r600_dma_ring_test, | |
1591 | .ib_test = &r600_dma_ib_test, | |
1592 | .is_lockup = &cayman_dma_is_lockup, | |
1593 | .vm_flush = &cayman_dma_vm_flush, | |
ea31bf69 AD |
1594 | .get_rptr = &cayman_dma_get_rptr, |
1595 | .get_wptr = &cayman_dma_get_wptr, | |
1596 | .set_wptr = &cayman_dma_set_wptr | |
76a0df85 CK |
1597 | }; |
1598 | ||
1599 | static struct radeon_asic_ring cayman_uvd_ring = { | |
e409b128 CK |
1600 | .ib_execute = &uvd_v1_0_ib_execute, |
1601 | .emit_fence = &uvd_v2_2_fence_emit, | |
1602 | .emit_semaphore = &uvd_v3_1_semaphore_emit, | |
76a0df85 | 1603 | .cs_parse = &radeon_uvd_cs_parse, |
e409b128 CK |
1604 | .ring_test = &uvd_v1_0_ring_test, |
1605 | .ib_test = &uvd_v1_0_ib_test, | |
76a0df85 | 1606 | .is_lockup = &radeon_ring_test_lockup, |
e409b128 CK |
1607 | .get_rptr = &uvd_v1_0_get_rptr, |
1608 | .get_wptr = &uvd_v1_0_get_wptr, | |
1609 | .set_wptr = &uvd_v1_0_set_wptr, | |
76a0df85 CK |
1610 | }; |
1611 | ||
e3487629 AD |
1612 | static struct radeon_asic cayman_asic = { |
1613 | .init = &cayman_init, | |
1614 | .fini = &cayman_fini, | |
1615 | .suspend = &cayman_suspend, | |
1616 | .resume = &cayman_resume, | |
e3487629 AD |
1617 | .asic_reset = &cayman_asic_reset, |
1618 | .vga_set_state = &r600_vga_set_state, | |
124764f1 | 1619 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
54e88e06 AD |
1620 | .gui_idle = &r600_gui_idle, |
1621 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1622 | .get_xclk = &rv770_get_xclk, |
d0418894 | 1623 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
c5b3b850 AD |
1624 | .gart = { |
1625 | .tlb_flush = &cayman_pcie_gart_tlb_flush, | |
1626 | .set_page = &rs600_gart_set_page, | |
1627 | }, | |
05b07147 CK |
1628 | .vm = { |
1629 | .init = &cayman_vm_init, | |
1630 | .fini = &cayman_vm_fini, | |
03f62abd CK |
1631 | .copy_pages = &cayman_dma_vm_copy_pages, |
1632 | .write_pages = &cayman_dma_vm_write_pages, | |
1633 | .set_pages = &cayman_dma_vm_set_pages, | |
1634 | .pad_ib = &cayman_dma_vm_pad_ib, | |
05b07147 | 1635 | }, |
4c87bc26 | 1636 | .ring = { |
76a0df85 CK |
1637 | [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, |
1638 | [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, | |
1639 | [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, | |
1640 | [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, | |
1641 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, | |
1642 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, | |
4c87bc26 | 1643 | }, |
b35ea4ab AD |
1644 | .irq = { |
1645 | .set = &evergreen_irq_set, | |
1646 | .process = &evergreen_irq_process, | |
1647 | }, | |
c79a49ca AD |
1648 | .display = { |
1649 | .bandwidth_update = &evergreen_bandwidth_update, | |
1650 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1651 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1652 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1653 | .get_backlight_level = &atombios_get_backlight_level, |
a973bea1 AD |
1654 | .hdmi_enable = &evergreen_hdmi_enable, |
1655 | .hdmi_setmode = &evergreen_hdmi_setmode, | |
c79a49ca | 1656 | }, |
27cd7769 | 1657 | .copy = { |
8dddb993 | 1658 | .blit = &r600_copy_cpdma, |
27cd7769 | 1659 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
f60cbd11 AD |
1660 | .dma = &evergreen_copy_dma, |
1661 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1662 | .copy = &evergreen_copy_dma, |
1663 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
27cd7769 | 1664 | }, |
9e6f3d02 AD |
1665 | .surface = { |
1666 | .set_reg = r600_set_surface_reg, | |
1667 | .clear_reg = r600_clear_surface_reg, | |
1668 | }, | |
901ea57d AD |
1669 | .hpd = { |
1670 | .init = &evergreen_hpd_init, | |
1671 | .fini = &evergreen_hpd_fini, | |
1672 | .sense = &evergreen_hpd_sense, | |
1673 | .set_polarity = &evergreen_hpd_set_polarity, | |
1674 | }, | |
a02fa397 AD |
1675 | .pm = { |
1676 | .misc = &evergreen_pm_misc, | |
1677 | .prepare = &evergreen_pm_prepare, | |
1678 | .finish = &evergreen_pm_finish, | |
27810fb2 | 1679 | .init_profile = &btc_pm_init_profile, |
a02fa397 | 1680 | .get_dynpm_state = &r600_pm_get_dynpm_state, |
798bcf73 AD |
1681 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1682 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1683 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1684 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
55b615ae AD |
1685 | .get_pcie_lanes = &r600_get_pcie_lanes, |
1686 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
798bcf73 | 1687 | .set_clock_gating = NULL, |
a8b4925c | 1688 | .set_uvd_clocks = &evergreen_set_uvd_clocks, |
6bd1c385 | 1689 | .get_temperature = &evergreen_get_temp, |
a02fa397 | 1690 | }, |
69e0b57a AD |
1691 | .dpm = { |
1692 | .init = &ni_dpm_init, | |
1693 | .setup_asic = &ni_dpm_setup_asic, | |
1694 | .enable = &ni_dpm_enable, | |
a3f11245 | 1695 | .late_enable = &rv770_dpm_late_enable, |
69e0b57a | 1696 | .disable = &ni_dpm_disable, |
fee3d744 | 1697 | .pre_set_power_state = &ni_dpm_pre_set_power_state, |
69e0b57a | 1698 | .set_power_state = &ni_dpm_set_power_state, |
fee3d744 | 1699 | .post_set_power_state = &ni_dpm_post_set_power_state, |
69e0b57a AD |
1700 | .display_configuration_changed = &cypress_dpm_display_configuration_changed, |
1701 | .fini = &ni_dpm_fini, | |
1702 | .get_sclk = &ni_dpm_get_sclk, | |
1703 | .get_mclk = &ni_dpm_get_mclk, | |
1704 | .print_power_state = &ni_dpm_print_power_state, | |
bdf0c4f0 | 1705 | .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level, |
170a47f0 | 1706 | .force_performance_level = &ni_dpm_force_performance_level, |
76ad73e5 | 1707 | .vblank_too_short = &ni_dpm_vblank_too_short, |
69e0b57a | 1708 | }, |
0f9e006c | 1709 | .pflip = { |
0f9e006c | 1710 | .page_flip = &evergreen_page_flip, |
157fa14d | 1711 | .page_flip_pending = &evergreen_page_flip_pending, |
0f9e006c | 1712 | }, |
e3487629 AD |
1713 | }; |
1714 | ||
be63fe8c AD |
1715 | static struct radeon_asic trinity_asic = { |
1716 | .init = &cayman_init, | |
1717 | .fini = &cayman_fini, | |
1718 | .suspend = &cayman_suspend, | |
1719 | .resume = &cayman_resume, | |
be63fe8c AD |
1720 | .asic_reset = &cayman_asic_reset, |
1721 | .vga_set_state = &r600_vga_set_state, | |
124764f1 | 1722 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
be63fe8c AD |
1723 | .gui_idle = &r600_gui_idle, |
1724 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1725 | .get_xclk = &r600_get_xclk, |
d0418894 | 1726 | .get_gpu_clock_counter = &r600_get_gpu_clock_counter, |
be63fe8c AD |
1727 | .gart = { |
1728 | .tlb_flush = &cayman_pcie_gart_tlb_flush, | |
1729 | .set_page = &rs600_gart_set_page, | |
1730 | }, | |
05b07147 CK |
1731 | .vm = { |
1732 | .init = &cayman_vm_init, | |
1733 | .fini = &cayman_vm_fini, | |
03f62abd CK |
1734 | .copy_pages = &cayman_dma_vm_copy_pages, |
1735 | .write_pages = &cayman_dma_vm_write_pages, | |
1736 | .set_pages = &cayman_dma_vm_set_pages, | |
1737 | .pad_ib = &cayman_dma_vm_pad_ib, | |
05b07147 | 1738 | }, |
be63fe8c | 1739 | .ring = { |
76a0df85 CK |
1740 | [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring, |
1741 | [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring, | |
1742 | [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring, | |
1743 | [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring, | |
1744 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring, | |
1745 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, | |
be63fe8c AD |
1746 | }, |
1747 | .irq = { | |
1748 | .set = &evergreen_irq_set, | |
1749 | .process = &evergreen_irq_process, | |
1750 | }, | |
1751 | .display = { | |
1752 | .bandwidth_update = &dce6_bandwidth_update, | |
1753 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1754 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1755 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1756 | .get_backlight_level = &atombios_get_backlight_level, |
b530602f AD |
1757 | .hdmi_enable = &evergreen_hdmi_enable, |
1758 | .hdmi_setmode = &evergreen_hdmi_setmode, | |
be63fe8c AD |
1759 | }, |
1760 | .copy = { | |
8dddb993 | 1761 | .blit = &r600_copy_cpdma, |
be63fe8c | 1762 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
f60cbd11 AD |
1763 | .dma = &evergreen_copy_dma, |
1764 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1765 | .copy = &evergreen_copy_dma, |
1766 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
be63fe8c AD |
1767 | }, |
1768 | .surface = { | |
1769 | .set_reg = r600_set_surface_reg, | |
1770 | .clear_reg = r600_clear_surface_reg, | |
1771 | }, | |
1772 | .hpd = { | |
1773 | .init = &evergreen_hpd_init, | |
1774 | .fini = &evergreen_hpd_fini, | |
1775 | .sense = &evergreen_hpd_sense, | |
1776 | .set_polarity = &evergreen_hpd_set_polarity, | |
1777 | }, | |
1778 | .pm = { | |
1779 | .misc = &evergreen_pm_misc, | |
1780 | .prepare = &evergreen_pm_prepare, | |
1781 | .finish = &evergreen_pm_finish, | |
1782 | .init_profile = &sumo_pm_init_profile, | |
1783 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
1784 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
1785 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1786 | .get_memory_clock = NULL, | |
1787 | .set_memory_clock = NULL, | |
1788 | .get_pcie_lanes = NULL, | |
1789 | .set_pcie_lanes = NULL, | |
1790 | .set_clock_gating = NULL, | |
23d33ba3 | 1791 | .set_uvd_clocks = &sumo_set_uvd_clocks, |
29a15221 | 1792 | .get_temperature = &tn_get_temp, |
be63fe8c | 1793 | }, |
d70229f7 AD |
1794 | .dpm = { |
1795 | .init = &trinity_dpm_init, | |
1796 | .setup_asic = &trinity_dpm_setup_asic, | |
1797 | .enable = &trinity_dpm_enable, | |
bda44c1a | 1798 | .late_enable = &trinity_dpm_late_enable, |
d70229f7 | 1799 | .disable = &trinity_dpm_disable, |
a284c48a | 1800 | .pre_set_power_state = &trinity_dpm_pre_set_power_state, |
d70229f7 | 1801 | .set_power_state = &trinity_dpm_set_power_state, |
a284c48a | 1802 | .post_set_power_state = &trinity_dpm_post_set_power_state, |
d70229f7 AD |
1803 | .display_configuration_changed = &trinity_dpm_display_configuration_changed, |
1804 | .fini = &trinity_dpm_fini, | |
1805 | .get_sclk = &trinity_dpm_get_sclk, | |
1806 | .get_mclk = &trinity_dpm_get_mclk, | |
1807 | .print_power_state = &trinity_dpm_print_power_state, | |
490ab931 | 1808 | .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level, |
9b5de596 | 1809 | .force_performance_level = &trinity_dpm_force_performance_level, |
11877060 | 1810 | .enable_bapm = &trinity_dpm_enable_bapm, |
d70229f7 | 1811 | }, |
be63fe8c | 1812 | .pflip = { |
be63fe8c | 1813 | .page_flip = &evergreen_page_flip, |
157fa14d | 1814 | .page_flip_pending = &evergreen_page_flip_pending, |
be63fe8c AD |
1815 | }, |
1816 | }; | |
1817 | ||
76a0df85 CK |
1818 | static struct radeon_asic_ring si_gfx_ring = { |
1819 | .ib_execute = &si_ring_ib_execute, | |
1820 | .ib_parse = &si_ib_parse, | |
1821 | .emit_fence = &si_fence_ring_emit, | |
1822 | .emit_semaphore = &r600_semaphore_ring_emit, | |
1823 | .cs_parse = NULL, | |
1824 | .ring_test = &r600_ring_test, | |
1825 | .ib_test = &r600_ib_test, | |
1826 | .is_lockup = &si_gfx_is_lockup, | |
1827 | .vm_flush = &si_vm_flush, | |
ea31bf69 AD |
1828 | .get_rptr = &cayman_gfx_get_rptr, |
1829 | .get_wptr = &cayman_gfx_get_wptr, | |
1830 | .set_wptr = &cayman_gfx_set_wptr, | |
76a0df85 CK |
1831 | }; |
1832 | ||
1833 | static struct radeon_asic_ring si_dma_ring = { | |
1834 | .ib_execute = &cayman_dma_ring_ib_execute, | |
1835 | .ib_parse = &evergreen_dma_ib_parse, | |
1836 | .emit_fence = &evergreen_dma_fence_ring_emit, | |
1837 | .emit_semaphore = &r600_dma_semaphore_ring_emit, | |
1838 | .cs_parse = NULL, | |
1839 | .ring_test = &r600_dma_ring_test, | |
1840 | .ib_test = &r600_dma_ib_test, | |
1841 | .is_lockup = &si_dma_is_lockup, | |
1842 | .vm_flush = &si_dma_vm_flush, | |
ea31bf69 AD |
1843 | .get_rptr = &cayman_dma_get_rptr, |
1844 | .get_wptr = &cayman_dma_get_wptr, | |
1845 | .set_wptr = &cayman_dma_set_wptr, | |
76a0df85 CK |
1846 | }; |
1847 | ||
02779c08 AD |
1848 | static struct radeon_asic si_asic = { |
1849 | .init = &si_init, | |
1850 | .fini = &si_fini, | |
1851 | .suspend = &si_suspend, | |
1852 | .resume = &si_resume, | |
02779c08 AD |
1853 | .asic_reset = &si_asic_reset, |
1854 | .vga_set_state = &r600_vga_set_state, | |
124764f1 | 1855 | .mmio_hdp_flush = r600_mmio_hdp_flush, |
02779c08 AD |
1856 | .gui_idle = &r600_gui_idle, |
1857 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
454d2e2a | 1858 | .get_xclk = &si_get_xclk, |
d0418894 | 1859 | .get_gpu_clock_counter = &si_get_gpu_clock_counter, |
02779c08 AD |
1860 | .gart = { |
1861 | .tlb_flush = &si_pcie_gart_tlb_flush, | |
1862 | .set_page = &rs600_gart_set_page, | |
1863 | }, | |
05b07147 CK |
1864 | .vm = { |
1865 | .init = &si_vm_init, | |
1866 | .fini = &si_vm_fini, | |
03f62abd CK |
1867 | .copy_pages = &si_dma_vm_copy_pages, |
1868 | .write_pages = &si_dma_vm_write_pages, | |
1869 | .set_pages = &si_dma_vm_set_pages, | |
1870 | .pad_ib = &cayman_dma_vm_pad_ib, | |
05b07147 | 1871 | }, |
02779c08 | 1872 | .ring = { |
76a0df85 CK |
1873 | [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring, |
1874 | [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring, | |
1875 | [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring, | |
1876 | [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring, | |
1877 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring, | |
1878 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, | |
02779c08 AD |
1879 | }, |
1880 | .irq = { | |
1881 | .set = &si_irq_set, | |
1882 | .process = &si_irq_process, | |
1883 | }, | |
1884 | .display = { | |
1885 | .bandwidth_update = &dce6_bandwidth_update, | |
1886 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
1887 | .wait_for_vblank = &dce4_wait_for_vblank, | |
37e9b6a6 | 1888 | .set_backlight_level = &atombios_set_backlight_level, |
6d92f81d | 1889 | .get_backlight_level = &atombios_get_backlight_level, |
b530602f AD |
1890 | .hdmi_enable = &evergreen_hdmi_enable, |
1891 | .hdmi_setmode = &evergreen_hdmi_setmode, | |
02779c08 AD |
1892 | }, |
1893 | .copy = { | |
5c722739 | 1894 | .blit = &r600_copy_cpdma, |
02779c08 | 1895 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
8c5fd7ef AD |
1896 | .dma = &si_copy_dma, |
1897 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2d6cc729 AD |
1898 | .copy = &si_copy_dma, |
1899 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
02779c08 AD |
1900 | }, |
1901 | .surface = { | |
1902 | .set_reg = r600_set_surface_reg, | |
1903 | .clear_reg = r600_clear_surface_reg, | |
1904 | }, | |
1905 | .hpd = { | |
1906 | .init = &evergreen_hpd_init, | |
1907 | .fini = &evergreen_hpd_fini, | |
1908 | .sense = &evergreen_hpd_sense, | |
1909 | .set_polarity = &evergreen_hpd_set_polarity, | |
1910 | }, | |
1911 | .pm = { | |
1912 | .misc = &evergreen_pm_misc, | |
1913 | .prepare = &evergreen_pm_prepare, | |
1914 | .finish = &evergreen_pm_finish, | |
1915 | .init_profile = &sumo_pm_init_profile, | |
1916 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
1917 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
1918 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
1919 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
1920 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
55b615ae AD |
1921 | .get_pcie_lanes = &r600_get_pcie_lanes, |
1922 | .set_pcie_lanes = &r600_set_pcie_lanes, | |
02779c08 | 1923 | .set_clock_gating = NULL, |
2539eb02 | 1924 | .set_uvd_clocks = &si_set_uvd_clocks, |
6bd1c385 | 1925 | .get_temperature = &si_get_temp, |
02779c08 | 1926 | }, |
a9e61410 AD |
1927 | .dpm = { |
1928 | .init = &si_dpm_init, | |
1929 | .setup_asic = &si_dpm_setup_asic, | |
1930 | .enable = &si_dpm_enable, | |
963c115d | 1931 | .late_enable = &si_dpm_late_enable, |
a9e61410 AD |
1932 | .disable = &si_dpm_disable, |
1933 | .pre_set_power_state = &si_dpm_pre_set_power_state, | |
1934 | .set_power_state = &si_dpm_set_power_state, | |
1935 | .post_set_power_state = &si_dpm_post_set_power_state, | |
1936 | .display_configuration_changed = &si_dpm_display_configuration_changed, | |
1937 | .fini = &si_dpm_fini, | |
1938 | .get_sclk = &ni_dpm_get_sclk, | |
1939 | .get_mclk = &ni_dpm_get_mclk, | |
1940 | .print_power_state = &ni_dpm_print_power_state, | |
7982128c | 1941 | .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, |
a160a6a3 | 1942 | .force_performance_level = &si_dpm_force_performance_level, |
f4dec318 | 1943 | .vblank_too_short = &ni_dpm_vblank_too_short, |
a9e61410 | 1944 | }, |
02779c08 | 1945 | .pflip = { |
02779c08 | 1946 | .page_flip = &evergreen_page_flip, |
157fa14d | 1947 | .page_flip_pending = &evergreen_page_flip_pending, |
02779c08 AD |
1948 | }, |
1949 | }; | |
1950 | ||
76a0df85 CK |
1951 | static struct radeon_asic_ring ci_gfx_ring = { |
1952 | .ib_execute = &cik_ring_ib_execute, | |
1953 | .ib_parse = &cik_ib_parse, | |
1954 | .emit_fence = &cik_fence_gfx_ring_emit, | |
1955 | .emit_semaphore = &cik_semaphore_ring_emit, | |
1956 | .cs_parse = NULL, | |
1957 | .ring_test = &cik_ring_test, | |
1958 | .ib_test = &cik_ib_test, | |
1959 | .is_lockup = &cik_gfx_is_lockup, | |
1960 | .vm_flush = &cik_vm_flush, | |
ea31bf69 AD |
1961 | .get_rptr = &cik_gfx_get_rptr, |
1962 | .get_wptr = &cik_gfx_get_wptr, | |
1963 | .set_wptr = &cik_gfx_set_wptr, | |
76a0df85 CK |
1964 | }; |
1965 | ||
1966 | static struct radeon_asic_ring ci_cp_ring = { | |
1967 | .ib_execute = &cik_ring_ib_execute, | |
1968 | .ib_parse = &cik_ib_parse, | |
1969 | .emit_fence = &cik_fence_compute_ring_emit, | |
1970 | .emit_semaphore = &cik_semaphore_ring_emit, | |
1971 | .cs_parse = NULL, | |
1972 | .ring_test = &cik_ring_test, | |
1973 | .ib_test = &cik_ib_test, | |
1974 | .is_lockup = &cik_gfx_is_lockup, | |
1975 | .vm_flush = &cik_vm_flush, | |
ea31bf69 AD |
1976 | .get_rptr = &cik_compute_get_rptr, |
1977 | .get_wptr = &cik_compute_get_wptr, | |
1978 | .set_wptr = &cik_compute_set_wptr, | |
76a0df85 CK |
1979 | }; |
1980 | ||
1981 | static struct radeon_asic_ring ci_dma_ring = { | |
1982 | .ib_execute = &cik_sdma_ring_ib_execute, | |
1983 | .ib_parse = &cik_ib_parse, | |
1984 | .emit_fence = &cik_sdma_fence_ring_emit, | |
1985 | .emit_semaphore = &cik_sdma_semaphore_ring_emit, | |
1986 | .cs_parse = NULL, | |
1987 | .ring_test = &cik_sdma_ring_test, | |
1988 | .ib_test = &cik_sdma_ib_test, | |
1989 | .is_lockup = &cik_sdma_is_lockup, | |
1990 | .vm_flush = &cik_dma_vm_flush, | |
ea31bf69 AD |
1991 | .get_rptr = &cik_sdma_get_rptr, |
1992 | .get_wptr = &cik_sdma_get_wptr, | |
1993 | .set_wptr = &cik_sdma_set_wptr, | |
76a0df85 CK |
1994 | }; |
1995 | ||
d93f7937 CK |
1996 | static struct radeon_asic_ring ci_vce_ring = { |
1997 | .ib_execute = &radeon_vce_ib_execute, | |
1998 | .emit_fence = &radeon_vce_fence_emit, | |
1999 | .emit_semaphore = &radeon_vce_semaphore_emit, | |
2000 | .cs_parse = &radeon_vce_cs_parse, | |
2001 | .ring_test = &radeon_vce_ring_test, | |
2002 | .ib_test = &radeon_vce_ib_test, | |
2003 | .is_lockup = &radeon_ring_test_lockup, | |
2004 | .get_rptr = &vce_v1_0_get_rptr, | |
2005 | .get_wptr = &vce_v1_0_get_wptr, | |
2006 | .set_wptr = &vce_v1_0_set_wptr, | |
2007 | }; | |
2008 | ||
0672e27b AD |
2009 | static struct radeon_asic ci_asic = { |
2010 | .init = &cik_init, | |
2011 | .fini = &cik_fini, | |
2012 | .suspend = &cik_suspend, | |
2013 | .resume = &cik_resume, | |
2014 | .asic_reset = &cik_asic_reset, | |
2015 | .vga_set_state = &r600_vga_set_state, | |
72a9987e | 2016 | .mmio_hdp_flush = &r600_mmio_hdp_flush, |
0672e27b AD |
2017 | .gui_idle = &r600_gui_idle, |
2018 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
2019 | .get_xclk = &cik_get_xclk, | |
2020 | .get_gpu_clock_counter = &cik_get_gpu_clock_counter, | |
2021 | .gart = { | |
2022 | .tlb_flush = &cik_pcie_gart_tlb_flush, | |
2023 | .set_page = &rs600_gart_set_page, | |
2024 | }, | |
2025 | .vm = { | |
2026 | .init = &cik_vm_init, | |
2027 | .fini = &cik_vm_fini, | |
03f62abd CK |
2028 | .copy_pages = &cik_sdma_vm_copy_pages, |
2029 | .write_pages = &cik_sdma_vm_write_pages, | |
2030 | .set_pages = &cik_sdma_vm_set_pages, | |
2031 | .pad_ib = &cik_sdma_vm_pad_ib, | |
0672e27b AD |
2032 | }, |
2033 | .ring = { | |
76a0df85 CK |
2034 | [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, |
2035 | [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, | |
2036 | [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, | |
2037 | [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, | |
2038 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, | |
2039 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, | |
d93f7937 CK |
2040 | [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, |
2041 | [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, | |
0672e27b AD |
2042 | }, |
2043 | .irq = { | |
2044 | .set = &cik_irq_set, | |
2045 | .process = &cik_irq_process, | |
2046 | }, | |
2047 | .display = { | |
2048 | .bandwidth_update = &dce8_bandwidth_update, | |
2049 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
2050 | .wait_for_vblank = &dce4_wait_for_vblank, | |
7272c9d2 SL |
2051 | .set_backlight_level = &atombios_set_backlight_level, |
2052 | .get_backlight_level = &atombios_get_backlight_level, | |
b530602f AD |
2053 | .hdmi_enable = &evergreen_hdmi_enable, |
2054 | .hdmi_setmode = &evergreen_hdmi_setmode, | |
0672e27b AD |
2055 | }, |
2056 | .copy = { | |
7819678f | 2057 | .blit = &cik_copy_cpdma, |
0672e27b AD |
2058 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
2059 | .dma = &cik_copy_dma, | |
2060 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
b5be1a83 CK |
2061 | .copy = &cik_copy_dma, |
2062 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
0672e27b AD |
2063 | }, |
2064 | .surface = { | |
2065 | .set_reg = r600_set_surface_reg, | |
2066 | .clear_reg = r600_clear_surface_reg, | |
2067 | }, | |
2068 | .hpd = { | |
2069 | .init = &evergreen_hpd_init, | |
2070 | .fini = &evergreen_hpd_fini, | |
2071 | .sense = &evergreen_hpd_sense, | |
2072 | .set_polarity = &evergreen_hpd_set_polarity, | |
2073 | }, | |
2074 | .pm = { | |
2075 | .misc = &evergreen_pm_misc, | |
2076 | .prepare = &evergreen_pm_prepare, | |
2077 | .finish = &evergreen_pm_finish, | |
2078 | .init_profile = &sumo_pm_init_profile, | |
2079 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
2080 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
2081 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
2082 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
2083 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
2084 | .get_pcie_lanes = NULL, | |
2085 | .set_pcie_lanes = NULL, | |
2086 | .set_clock_gating = NULL, | |
2087 | .set_uvd_clocks = &cik_set_uvd_clocks, | |
5ad6bf91 | 2088 | .set_vce_clocks = &cik_set_vce_clocks, |
286d9cc6 | 2089 | .get_temperature = &ci_get_temp, |
0672e27b | 2090 | }, |
cc8dbbb4 AD |
2091 | .dpm = { |
2092 | .init = &ci_dpm_init, | |
2093 | .setup_asic = &ci_dpm_setup_asic, | |
2094 | .enable = &ci_dpm_enable, | |
90208427 | 2095 | .late_enable = &ci_dpm_late_enable, |
cc8dbbb4 AD |
2096 | .disable = &ci_dpm_disable, |
2097 | .pre_set_power_state = &ci_dpm_pre_set_power_state, | |
2098 | .set_power_state = &ci_dpm_set_power_state, | |
2099 | .post_set_power_state = &ci_dpm_post_set_power_state, | |
2100 | .display_configuration_changed = &ci_dpm_display_configuration_changed, | |
2101 | .fini = &ci_dpm_fini, | |
2102 | .get_sclk = &ci_dpm_get_sclk, | |
2103 | .get_mclk = &ci_dpm_get_mclk, | |
2104 | .print_power_state = &ci_dpm_print_power_state, | |
94b4adc5 | 2105 | .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level, |
89536fd6 | 2106 | .force_performance_level = &ci_dpm_force_performance_level, |
5496131e | 2107 | .vblank_too_short = &ci_dpm_vblank_too_short, |
942bdf7f | 2108 | .powergate_uvd = &ci_dpm_powergate_uvd, |
cc8dbbb4 | 2109 | }, |
0672e27b | 2110 | .pflip = { |
0672e27b | 2111 | .page_flip = &evergreen_page_flip, |
157fa14d | 2112 | .page_flip_pending = &evergreen_page_flip_pending, |
0672e27b AD |
2113 | }, |
2114 | }; | |
2115 | ||
2116 | static struct radeon_asic kv_asic = { | |
2117 | .init = &cik_init, | |
2118 | .fini = &cik_fini, | |
2119 | .suspend = &cik_suspend, | |
2120 | .resume = &cik_resume, | |
2121 | .asic_reset = &cik_asic_reset, | |
2122 | .vga_set_state = &r600_vga_set_state, | |
72a9987e | 2123 | .mmio_hdp_flush = &r600_mmio_hdp_flush, |
0672e27b AD |
2124 | .gui_idle = &r600_gui_idle, |
2125 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | |
2126 | .get_xclk = &cik_get_xclk, | |
2127 | .get_gpu_clock_counter = &cik_get_gpu_clock_counter, | |
2128 | .gart = { | |
2129 | .tlb_flush = &cik_pcie_gart_tlb_flush, | |
2130 | .set_page = &rs600_gart_set_page, | |
2131 | }, | |
2132 | .vm = { | |
2133 | .init = &cik_vm_init, | |
2134 | .fini = &cik_vm_fini, | |
03f62abd CK |
2135 | .copy_pages = &cik_sdma_vm_copy_pages, |
2136 | .write_pages = &cik_sdma_vm_write_pages, | |
2137 | .set_pages = &cik_sdma_vm_set_pages, | |
2138 | .pad_ib = &cik_sdma_vm_pad_ib, | |
0672e27b AD |
2139 | }, |
2140 | .ring = { | |
76a0df85 CK |
2141 | [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring, |
2142 | [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring, | |
2143 | [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring, | |
2144 | [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring, | |
2145 | [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring, | |
2146 | [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring, | |
d93f7937 CK |
2147 | [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring, |
2148 | [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring, | |
0672e27b AD |
2149 | }, |
2150 | .irq = { | |
2151 | .set = &cik_irq_set, | |
2152 | .process = &cik_irq_process, | |
2153 | }, | |
2154 | .display = { | |
2155 | .bandwidth_update = &dce8_bandwidth_update, | |
2156 | .get_vblank_counter = &evergreen_get_vblank_counter, | |
2157 | .wait_for_vblank = &dce4_wait_for_vblank, | |
7272c9d2 SL |
2158 | .set_backlight_level = &atombios_set_backlight_level, |
2159 | .get_backlight_level = &atombios_get_backlight_level, | |
b530602f AD |
2160 | .hdmi_enable = &evergreen_hdmi_enable, |
2161 | .hdmi_setmode = &evergreen_hdmi_setmode, | |
0672e27b AD |
2162 | }, |
2163 | .copy = { | |
7819678f | 2164 | .blit = &cik_copy_cpdma, |
0672e27b AD |
2165 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
2166 | .dma = &cik_copy_dma, | |
2167 | .dma_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2168 | .copy = &cik_copy_dma, | |
2169 | .copy_ring_index = R600_RING_TYPE_DMA_INDEX, | |
2170 | }, | |
2171 | .surface = { | |
2172 | .set_reg = r600_set_surface_reg, | |
2173 | .clear_reg = r600_clear_surface_reg, | |
2174 | }, | |
2175 | .hpd = { | |
2176 | .init = &evergreen_hpd_init, | |
2177 | .fini = &evergreen_hpd_fini, | |
2178 | .sense = &evergreen_hpd_sense, | |
2179 | .set_polarity = &evergreen_hpd_set_polarity, | |
2180 | }, | |
2181 | .pm = { | |
2182 | .misc = &evergreen_pm_misc, | |
2183 | .prepare = &evergreen_pm_prepare, | |
2184 | .finish = &evergreen_pm_finish, | |
2185 | .init_profile = &sumo_pm_init_profile, | |
2186 | .get_dynpm_state = &r600_pm_get_dynpm_state, | |
2187 | .get_engine_clock = &radeon_atom_get_engine_clock, | |
2188 | .set_engine_clock = &radeon_atom_set_engine_clock, | |
2189 | .get_memory_clock = &radeon_atom_get_memory_clock, | |
2190 | .set_memory_clock = &radeon_atom_set_memory_clock, | |
2191 | .get_pcie_lanes = NULL, | |
2192 | .set_pcie_lanes = NULL, | |
2193 | .set_clock_gating = NULL, | |
2194 | .set_uvd_clocks = &cik_set_uvd_clocks, | |
5ad6bf91 | 2195 | .set_vce_clocks = &cik_set_vce_clocks, |
286d9cc6 | 2196 | .get_temperature = &kv_get_temp, |
0672e27b | 2197 | }, |
41a524ab AD |
2198 | .dpm = { |
2199 | .init = &kv_dpm_init, | |
2200 | .setup_asic = &kv_dpm_setup_asic, | |
2201 | .enable = &kv_dpm_enable, | |
d8852c34 | 2202 | .late_enable = &kv_dpm_late_enable, |
41a524ab AD |
2203 | .disable = &kv_dpm_disable, |
2204 | .pre_set_power_state = &kv_dpm_pre_set_power_state, | |
2205 | .set_power_state = &kv_dpm_set_power_state, | |
2206 | .post_set_power_state = &kv_dpm_post_set_power_state, | |
2207 | .display_configuration_changed = &kv_dpm_display_configuration_changed, | |
2208 | .fini = &kv_dpm_fini, | |
2209 | .get_sclk = &kv_dpm_get_sclk, | |
2210 | .get_mclk = &kv_dpm_get_mclk, | |
2211 | .print_power_state = &kv_dpm_print_power_state, | |
ae3e40e8 | 2212 | .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level, |
2b4c8022 | 2213 | .force_performance_level = &kv_dpm_force_performance_level, |
77df508a | 2214 | .powergate_uvd = &kv_dpm_powergate_uvd, |
b7a5ae97 | 2215 | .enable_bapm = &kv_dpm_enable_bapm, |
41a524ab | 2216 | }, |
0672e27b | 2217 | .pflip = { |
0672e27b | 2218 | .page_flip = &evergreen_page_flip, |
157fa14d | 2219 | .page_flip_pending = &evergreen_page_flip_pending, |
0672e27b AD |
2220 | }, |
2221 | }; | |
2222 | ||
abf1dc67 AD |
2223 | /** |
2224 | * radeon_asic_init - register asic specific callbacks | |
2225 | * | |
2226 | * @rdev: radeon device pointer | |
2227 | * | |
2228 | * Registers the appropriate asic specific callbacks for each | |
2229 | * chip family. Also sets other asics specific info like the number | |
2230 | * of crtcs and the register aperture accessors (all asics). | |
2231 | * Returns 0 for success. | |
2232 | */ | |
0a10c851 DV |
2233 | int radeon_asic_init(struct radeon_device *rdev) |
2234 | { | |
2235 | radeon_register_accessor_init(rdev); | |
ba7e05e9 AD |
2236 | |
2237 | /* set the number of crtcs */ | |
2238 | if (rdev->flags & RADEON_SINGLE_CRTC) | |
2239 | rdev->num_crtc = 1; | |
2240 | else | |
2241 | rdev->num_crtc = 2; | |
2242 | ||
948bee3f AD |
2243 | rdev->has_uvd = false; |
2244 | ||
0a10c851 DV |
2245 | switch (rdev->family) { |
2246 | case CHIP_R100: | |
2247 | case CHIP_RV100: | |
2248 | case CHIP_RS100: | |
2249 | case CHIP_RV200: | |
2250 | case CHIP_RS200: | |
2251 | rdev->asic = &r100_asic; | |
2252 | break; | |
2253 | case CHIP_R200: | |
2254 | case CHIP_RV250: | |
2255 | case CHIP_RS300: | |
2256 | case CHIP_RV280: | |
2257 | rdev->asic = &r200_asic; | |
2258 | break; | |
2259 | case CHIP_R300: | |
2260 | case CHIP_R350: | |
2261 | case CHIP_RV350: | |
2262 | case CHIP_RV380: | |
2263 | if (rdev->flags & RADEON_IS_PCIE) | |
2264 | rdev->asic = &r300_asic_pcie; | |
2265 | else | |
2266 | rdev->asic = &r300_asic; | |
2267 | break; | |
2268 | case CHIP_R420: | |
2269 | case CHIP_R423: | |
2270 | case CHIP_RV410: | |
2271 | rdev->asic = &r420_asic; | |
07bb084c AD |
2272 | /* handle macs */ |
2273 | if (rdev->bios == NULL) { | |
798bcf73 AD |
2274 | rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock; |
2275 | rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock; | |
2276 | rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock; | |
2277 | rdev->asic->pm.set_memory_clock = NULL; | |
37e9b6a6 | 2278 | rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level; |
07bb084c | 2279 | } |
0a10c851 DV |
2280 | break; |
2281 | case CHIP_RS400: | |
2282 | case CHIP_RS480: | |
2283 | rdev->asic = &rs400_asic; | |
2284 | break; | |
2285 | case CHIP_RS600: | |
2286 | rdev->asic = &rs600_asic; | |
2287 | break; | |
2288 | case CHIP_RS690: | |
2289 | case CHIP_RS740: | |
2290 | rdev->asic = &rs690_asic; | |
2291 | break; | |
2292 | case CHIP_RV515: | |
2293 | rdev->asic = &rv515_asic; | |
2294 | break; | |
2295 | case CHIP_R520: | |
2296 | case CHIP_RV530: | |
2297 | case CHIP_RV560: | |
2298 | case CHIP_RV570: | |
2299 | case CHIP_R580: | |
2300 | rdev->asic = &r520_asic; | |
2301 | break; | |
2302 | case CHIP_R600: | |
ca361b65 AD |
2303 | rdev->asic = &r600_asic; |
2304 | break; | |
0a10c851 DV |
2305 | case CHIP_RV610: |
2306 | case CHIP_RV630: | |
2307 | case CHIP_RV620: | |
2308 | case CHIP_RV635: | |
2309 | case CHIP_RV670: | |
ca361b65 AD |
2310 | rdev->asic = &rv6xx_asic; |
2311 | rdev->has_uvd = true; | |
f47299c5 | 2312 | break; |
0a10c851 DV |
2313 | case CHIP_RS780: |
2314 | case CHIP_RS880: | |
f47299c5 | 2315 | rdev->asic = &rs780_asic; |
bdc99722 AD |
2316 | /* 760G/780V/880V don't have UVD */ |
2317 | if ((rdev->pdev->device == 0x9616)|| | |
2318 | (rdev->pdev->device == 0x9611)|| | |
2319 | (rdev->pdev->device == 0x9613)|| | |
2320 | (rdev->pdev->device == 0x9711)|| | |
2321 | (rdev->pdev->device == 0x9713)) | |
2322 | rdev->has_uvd = false; | |
2323 | else | |
2324 | rdev->has_uvd = true; | |
0a10c851 DV |
2325 | break; |
2326 | case CHIP_RV770: | |
2327 | case CHIP_RV730: | |
2328 | case CHIP_RV710: | |
2329 | case CHIP_RV740: | |
2330 | rdev->asic = &rv770_asic; | |
948bee3f | 2331 | rdev->has_uvd = true; |
0a10c851 DV |
2332 | break; |
2333 | case CHIP_CEDAR: | |
2334 | case CHIP_REDWOOD: | |
2335 | case CHIP_JUNIPER: | |
2336 | case CHIP_CYPRESS: | |
2337 | case CHIP_HEMLOCK: | |
ba7e05e9 AD |
2338 | /* set num crtcs */ |
2339 | if (rdev->family == CHIP_CEDAR) | |
2340 | rdev->num_crtc = 4; | |
2341 | else | |
2342 | rdev->num_crtc = 6; | |
0a10c851 | 2343 | rdev->asic = &evergreen_asic; |
948bee3f | 2344 | rdev->has_uvd = true; |
0a10c851 | 2345 | break; |
958261d1 | 2346 | case CHIP_PALM: |
89da5a37 AD |
2347 | case CHIP_SUMO: |
2348 | case CHIP_SUMO2: | |
958261d1 | 2349 | rdev->asic = &sumo_asic; |
948bee3f | 2350 | rdev->has_uvd = true; |
958261d1 | 2351 | break; |
a43b7665 AD |
2352 | case CHIP_BARTS: |
2353 | case CHIP_TURKS: | |
2354 | case CHIP_CAICOS: | |
ba7e05e9 AD |
2355 | /* set num crtcs */ |
2356 | if (rdev->family == CHIP_CAICOS) | |
2357 | rdev->num_crtc = 4; | |
2358 | else | |
2359 | rdev->num_crtc = 6; | |
a43b7665 | 2360 | rdev->asic = &btc_asic; |
948bee3f | 2361 | rdev->has_uvd = true; |
a43b7665 | 2362 | break; |
e3487629 AD |
2363 | case CHIP_CAYMAN: |
2364 | rdev->asic = &cayman_asic; | |
ba7e05e9 AD |
2365 | /* set num crtcs */ |
2366 | rdev->num_crtc = 6; | |
948bee3f | 2367 | rdev->has_uvd = true; |
e3487629 | 2368 | break; |
be63fe8c AD |
2369 | case CHIP_ARUBA: |
2370 | rdev->asic = &trinity_asic; | |
2371 | /* set num crtcs */ | |
2372 | rdev->num_crtc = 4; | |
948bee3f | 2373 | rdev->has_uvd = true; |
be63fe8c | 2374 | break; |
02779c08 AD |
2375 | case CHIP_TAHITI: |
2376 | case CHIP_PITCAIRN: | |
2377 | case CHIP_VERDE: | |
e737a14c | 2378 | case CHIP_OLAND: |
86a45cac | 2379 | case CHIP_HAINAN: |
02779c08 AD |
2380 | rdev->asic = &si_asic; |
2381 | /* set num crtcs */ | |
86a45cac AD |
2382 | if (rdev->family == CHIP_HAINAN) |
2383 | rdev->num_crtc = 0; | |
2384 | else if (rdev->family == CHIP_OLAND) | |
e737a14c AD |
2385 | rdev->num_crtc = 2; |
2386 | else | |
2387 | rdev->num_crtc = 6; | |
948bee3f AD |
2388 | if (rdev->family == CHIP_HAINAN) |
2389 | rdev->has_uvd = false; | |
2390 | else | |
2391 | rdev->has_uvd = true; | |
0116e1ef AD |
2392 | switch (rdev->family) { |
2393 | case CHIP_TAHITI: | |
2394 | rdev->cg_flags = | |
090f4b6a | 2395 | RADEON_CG_SUPPORT_GFX_MGCG | |
0116e1ef | 2396 | RADEON_CG_SUPPORT_GFX_MGLS | |
e16866ec | 2397 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
0116e1ef AD |
2398 | RADEON_CG_SUPPORT_GFX_CGLS | |
2399 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2400 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2401 | RADEON_CG_SUPPORT_MC_MGCG | | |
2402 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2403 | RADEON_CG_SUPPORT_BIF_LS | | |
2404 | RADEON_CG_SUPPORT_VCE_MGCG | | |
2405 | RADEON_CG_SUPPORT_UVD_MGCG | | |
2406 | RADEON_CG_SUPPORT_HDP_LS | | |
2407 | RADEON_CG_SUPPORT_HDP_MGCG; | |
2408 | rdev->pg_flags = 0; | |
2409 | break; | |
2410 | case CHIP_PITCAIRN: | |
2411 | rdev->cg_flags = | |
090f4b6a | 2412 | RADEON_CG_SUPPORT_GFX_MGCG | |
0116e1ef | 2413 | RADEON_CG_SUPPORT_GFX_MGLS | |
e16866ec | 2414 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
0116e1ef AD |
2415 | RADEON_CG_SUPPORT_GFX_CGLS | |
2416 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2417 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2418 | RADEON_CG_SUPPORT_GFX_RLC_LS | | |
2419 | RADEON_CG_SUPPORT_MC_LS | | |
2420 | RADEON_CG_SUPPORT_MC_MGCG | | |
2421 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2422 | RADEON_CG_SUPPORT_BIF_LS | | |
2423 | RADEON_CG_SUPPORT_VCE_MGCG | | |
2424 | RADEON_CG_SUPPORT_UVD_MGCG | | |
2425 | RADEON_CG_SUPPORT_HDP_LS | | |
2426 | RADEON_CG_SUPPORT_HDP_MGCG; | |
2427 | rdev->pg_flags = 0; | |
2428 | break; | |
2429 | case CHIP_VERDE: | |
2430 | rdev->cg_flags = | |
090f4b6a | 2431 | RADEON_CG_SUPPORT_GFX_MGCG | |
0116e1ef | 2432 | RADEON_CG_SUPPORT_GFX_MGLS | |
e16866ec | 2433 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
0116e1ef AD |
2434 | RADEON_CG_SUPPORT_GFX_CGLS | |
2435 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2436 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2437 | RADEON_CG_SUPPORT_GFX_RLC_LS | | |
2438 | RADEON_CG_SUPPORT_MC_LS | | |
2439 | RADEON_CG_SUPPORT_MC_MGCG | | |
2440 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2441 | RADEON_CG_SUPPORT_BIF_LS | | |
2442 | RADEON_CG_SUPPORT_VCE_MGCG | | |
2443 | RADEON_CG_SUPPORT_UVD_MGCG | | |
2444 | RADEON_CG_SUPPORT_HDP_LS | | |
2445 | RADEON_CG_SUPPORT_HDP_MGCG; | |
ca6ebb39 | 2446 | rdev->pg_flags = 0 | |
2b19d17f | 2447 | /*RADEON_PG_SUPPORT_GFX_PG | */ |
ca6ebb39 | 2448 | RADEON_PG_SUPPORT_SDMA; |
0116e1ef AD |
2449 | break; |
2450 | case CHIP_OLAND: | |
2451 | rdev->cg_flags = | |
090f4b6a | 2452 | RADEON_CG_SUPPORT_GFX_MGCG | |
0116e1ef | 2453 | RADEON_CG_SUPPORT_GFX_MGLS | |
e16866ec | 2454 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
0116e1ef AD |
2455 | RADEON_CG_SUPPORT_GFX_CGLS | |
2456 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2457 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2458 | RADEON_CG_SUPPORT_GFX_RLC_LS | | |
2459 | RADEON_CG_SUPPORT_MC_LS | | |
2460 | RADEON_CG_SUPPORT_MC_MGCG | | |
2461 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2462 | RADEON_CG_SUPPORT_BIF_LS | | |
2463 | RADEON_CG_SUPPORT_UVD_MGCG | | |
2464 | RADEON_CG_SUPPORT_HDP_LS | | |
2465 | RADEON_CG_SUPPORT_HDP_MGCG; | |
2466 | rdev->pg_flags = 0; | |
2467 | break; | |
2468 | case CHIP_HAINAN: | |
2469 | rdev->cg_flags = | |
090f4b6a | 2470 | RADEON_CG_SUPPORT_GFX_MGCG | |
0116e1ef | 2471 | RADEON_CG_SUPPORT_GFX_MGLS | |
e16866ec | 2472 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
0116e1ef AD |
2473 | RADEON_CG_SUPPORT_GFX_CGLS | |
2474 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2475 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2476 | RADEON_CG_SUPPORT_GFX_RLC_LS | | |
2477 | RADEON_CG_SUPPORT_MC_LS | | |
2478 | RADEON_CG_SUPPORT_MC_MGCG | | |
2479 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2480 | RADEON_CG_SUPPORT_BIF_LS | | |
2481 | RADEON_CG_SUPPORT_HDP_LS | | |
2482 | RADEON_CG_SUPPORT_HDP_MGCG; | |
2483 | rdev->pg_flags = 0; | |
2484 | break; | |
2485 | default: | |
2486 | rdev->cg_flags = 0; | |
2487 | rdev->pg_flags = 0; | |
2488 | break; | |
2489 | } | |
02779c08 | 2490 | break; |
0672e27b | 2491 | case CHIP_BONAIRE: |
41971b37 | 2492 | case CHIP_HAWAII: |
0672e27b AD |
2493 | rdev->asic = &ci_asic; |
2494 | rdev->num_crtc = 6; | |
22c775ce | 2495 | rdev->has_uvd = true; |
41971b37 AD |
2496 | if (rdev->family == CHIP_BONAIRE) { |
2497 | rdev->cg_flags = | |
2498 | RADEON_CG_SUPPORT_GFX_MGCG | | |
2499 | RADEON_CG_SUPPORT_GFX_MGLS | | |
6960948d | 2500 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
41971b37 AD |
2501 | RADEON_CG_SUPPORT_GFX_CGLS | |
2502 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2503 | RADEON_CG_SUPPORT_GFX_CGTS_LS | | |
2504 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2505 | RADEON_CG_SUPPORT_MC_LS | | |
2506 | RADEON_CG_SUPPORT_MC_MGCG | | |
2507 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2508 | RADEON_CG_SUPPORT_SDMA_LS | | |
2509 | RADEON_CG_SUPPORT_BIF_LS | | |
2510 | RADEON_CG_SUPPORT_VCE_MGCG | | |
2511 | RADEON_CG_SUPPORT_UVD_MGCG | | |
2512 | RADEON_CG_SUPPORT_HDP_LS | | |
2513 | RADEON_CG_SUPPORT_HDP_MGCG; | |
2514 | rdev->pg_flags = 0; | |
2515 | } else { | |
2516 | rdev->cg_flags = | |
2517 | RADEON_CG_SUPPORT_GFX_MGCG | | |
2518 | RADEON_CG_SUPPORT_GFX_MGLS | | |
6960948d | 2519 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
41971b37 AD |
2520 | RADEON_CG_SUPPORT_GFX_CGLS | |
2521 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2522 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2523 | RADEON_CG_SUPPORT_MC_LS | | |
2524 | RADEON_CG_SUPPORT_MC_MGCG | | |
2525 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2526 | RADEON_CG_SUPPORT_SDMA_LS | | |
2527 | RADEON_CG_SUPPORT_BIF_LS | | |
2528 | RADEON_CG_SUPPORT_VCE_MGCG | | |
2529 | RADEON_CG_SUPPORT_UVD_MGCG | | |
2530 | RADEON_CG_SUPPORT_HDP_LS | | |
2531 | RADEON_CG_SUPPORT_HDP_MGCG; | |
2532 | rdev->pg_flags = 0; | |
2533 | } | |
0672e27b AD |
2534 | break; |
2535 | case CHIP_KAVERI: | |
2536 | case CHIP_KABINI: | |
b0a9f22a | 2537 | case CHIP_MULLINS: |
0672e27b AD |
2538 | rdev->asic = &kv_asic; |
2539 | /* set num crtcs */ | |
473359bc | 2540 | if (rdev->family == CHIP_KAVERI) { |
0672e27b | 2541 | rdev->num_crtc = 4; |
473359bc | 2542 | rdev->cg_flags = |
773dc10a | 2543 | RADEON_CG_SUPPORT_GFX_MGCG | |
473359bc | 2544 | RADEON_CG_SUPPORT_GFX_MGLS | |
6960948d | 2545 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
473359bc AD |
2546 | RADEON_CG_SUPPORT_GFX_CGLS | |
2547 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2548 | RADEON_CG_SUPPORT_GFX_CGTS_LS | | |
2549 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2550 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2551 | RADEON_CG_SUPPORT_SDMA_LS | | |
2552 | RADEON_CG_SUPPORT_BIF_LS | | |
2553 | RADEON_CG_SUPPORT_VCE_MGCG | | |
2554 | RADEON_CG_SUPPORT_UVD_MGCG | | |
2555 | RADEON_CG_SUPPORT_HDP_LS | | |
2556 | RADEON_CG_SUPPORT_HDP_MGCG; | |
2557 | rdev->pg_flags = 0; | |
2b19d17f | 2558 | /*RADEON_PG_SUPPORT_GFX_PG | |
473359bc AD |
2559 | RADEON_PG_SUPPORT_GFX_SMG | |
2560 | RADEON_PG_SUPPORT_GFX_DMG | | |
2561 | RADEON_PG_SUPPORT_UVD | | |
2562 | RADEON_PG_SUPPORT_VCE | | |
2563 | RADEON_PG_SUPPORT_CP | | |
2564 | RADEON_PG_SUPPORT_GDS | | |
2565 | RADEON_PG_SUPPORT_RLC_SMU_HS | | |
2566 | RADEON_PG_SUPPORT_ACP | | |
2567 | RADEON_PG_SUPPORT_SAMU;*/ | |
2568 | } else { | |
0672e27b | 2569 | rdev->num_crtc = 2; |
473359bc | 2570 | rdev->cg_flags = |
773dc10a | 2571 | RADEON_CG_SUPPORT_GFX_MGCG | |
473359bc | 2572 | RADEON_CG_SUPPORT_GFX_MGLS | |
6960948d | 2573 | /*RADEON_CG_SUPPORT_GFX_CGCG |*/ |
473359bc AD |
2574 | RADEON_CG_SUPPORT_GFX_CGLS | |
2575 | RADEON_CG_SUPPORT_GFX_CGTS | | |
2576 | RADEON_CG_SUPPORT_GFX_CGTS_LS | | |
2577 | RADEON_CG_SUPPORT_GFX_CP_LS | | |
2578 | RADEON_CG_SUPPORT_SDMA_MGCG | | |
2579 | RADEON_CG_SUPPORT_SDMA_LS | | |
2580 | RADEON_CG_SUPPORT_BIF_LS | | |
2581 | RADEON_CG_SUPPORT_VCE_MGCG | | |
2582 | RADEON_CG_SUPPORT_UVD_MGCG | | |
2583 | RADEON_CG_SUPPORT_HDP_LS | | |
2584 | RADEON_CG_SUPPORT_HDP_MGCG; | |
2585 | rdev->pg_flags = 0; | |
2b19d17f | 2586 | /*RADEON_PG_SUPPORT_GFX_PG | |
473359bc AD |
2587 | RADEON_PG_SUPPORT_GFX_SMG | |
2588 | RADEON_PG_SUPPORT_UVD | | |
2589 | RADEON_PG_SUPPORT_VCE | | |
2590 | RADEON_PG_SUPPORT_CP | | |
2591 | RADEON_PG_SUPPORT_GDS | | |
2592 | RADEON_PG_SUPPORT_RLC_SMU_HS | | |
2593 | RADEON_PG_SUPPORT_SAMU;*/ | |
2594 | } | |
22c775ce | 2595 | rdev->has_uvd = true; |
0672e27b | 2596 | break; |
0a10c851 DV |
2597 | default: |
2598 | /* FIXME: not supported yet */ | |
2599 | return -EINVAL; | |
2600 | } | |
2601 | ||
2602 | if (rdev->flags & RADEON_IS_IGP) { | |
798bcf73 AD |
2603 | rdev->asic->pm.get_memory_clock = NULL; |
2604 | rdev->asic->pm.set_memory_clock = NULL; | |
0a10c851 DV |
2605 | } |
2606 | ||
2607 | return 0; | |
2608 | } | |
2609 |